2026-01-29 01:32:02.694 [INFO] transceiver.py:125 Init transceiver 'BTS@172.18.28.20:5700'
2026-01-29 01:32:02.694 [DEBUG] data_if.py:31 Init TRXD interface (L:0.0.0.0:5702 <-> R:172.18.28.20:5802)
2026-01-29 01:32:02.694 [DEBUG] ctrl_if.py:29 Init TRXC interface (L:0.0.0.0:5701 <-> R:172.18.28.20:5801)
2026-01-29 01:32:02.694 [INFO] transceiver.py:125 Init transceiver 'MS@172.18.28.22:6700'
2026-01-29 01:32:02.694 [DEBUG] data_if.py:31 Init TRXD interface (L:0.0.0.0:6702 <-> R:172.18.28.22:6802)
2026-01-29 01:32:02.694 [DEBUG] ctrl_if.py:29 Init TRXC interface (L:0.0.0.0:6701 <-> R:172.18.28.22:6801)
2026-01-29 01:32:02.694 [INFO] transceiver.py:125 Init transceiver 'TRX1@172.18.28.20:5700/1'
2026-01-29 01:32:02.694 [DEBUG] data_if.py:31 Init TRXD interface (L:0.0.0.0:5704 <-> R:172.18.28.20:5804)
2026-01-29 01:32:02.694 [DEBUG] ctrl_if.py:29 Init TRXC interface (L:0.0.0.0:5703 <-> R:172.18.28.20:5803)
2026-01-29 01:32:02.694 [INFO] transceiver.py:125 Init transceiver 'TRX2@172.18.28.20:5700/2'
2026-01-29 01:32:02.694 [DEBUG] data_if.py:31 Init TRXD interface (L:0.0.0.0:5706 <-> R:172.18.28.20:5806)
2026-01-29 01:32:02.694 [DEBUG] ctrl_if.py:29 Init TRXC interface (L:0.0.0.0:5705 <-> R:172.18.28.20:5805)
2026-01-29 01:32:02.694 [INFO] transceiver.py:125 Init transceiver 'TRX3@172.18.28.20:5700/3'
2026-01-29 01:32:02.694 [DEBUG] data_if.py:31 Init TRXD interface (L:0.0.0.0:5708 <-> R:172.18.28.20:5808)
2026-01-29 01:32:02.694 [DEBUG] ctrl_if.py:29 Init TRXC interface (L:0.0.0.0:5707 <-> R:172.18.28.20:5807)
2026-01-29 01:32:02.694 [INFO] fake_trx.py:429 Init complete
2026-01-29 01:32:02.694 [INFO] fake_trx.py:460 Setting real time process scheduler to SCHED_RR, priority 30
2026-01-29 01:32:04.309 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 01:32:04.310 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.28.20:5700) Recv POWEROFF cmd
2026-01-29 01:32:04.310 [INFO] ctrl_if_trx.py:117 (BTS@172.18.28.20:5700) Stopping transceiver...
2026-01-29 01:32:04.310 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 01:32:04.310 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 01:32:04.311 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 01:32:07.324 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 01:32:07.326 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.28.20:5700) Recv SETFORMAT cmd
2026-01-29 01:32:07.326 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.28.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 01:32:07.327 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.28.20:5700) Recv SETFORMAT cmd
2026-01-29 01:32:07.327 [INFO] ctrl_if_trx.py:201 (BTS@172.18.28.20:5700) TRXD header version 0 -> 1
2026-01-29 01:32:07.333 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.28.20:5700/1) Recv RXTUNE cmd
2026-01-29 01:32:07.333 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.28.20:5700/1) Recv TXTUNE cmd
2026-01-29 01:32:07.334 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.28.20:5700/1) Recv SETFORMAT cmd
2026-01-29 01:32:07.334 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.28.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 01:32:07.334 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 01:32:07.335 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.28.20:5700/1) Recv NOMTXPOWER cmd
2026-01-29 01:32:07.335 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.28.20:5700/1) Recv SETFORMAT cmd
2026-01-29 01:32:07.335 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.28.20:5700/1) TRXD header version 0 -> 1
2026-01-29 01:32:07.338 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.28.20:5700/2) Recv RXTUNE cmd
2026-01-29 01:32:07.338 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.28.20:5700/2) Recv TXTUNE cmd
2026-01-29 01:32:07.338 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.28.20:5700/2) Recv SETFORMAT cmd
2026-01-29 01:32:07.338 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.28.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 01:32:07.339 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 01:32:07.339 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.28.20:5700/2) Recv NOMTXPOWER cmd
2026-01-29 01:32:07.339 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.28.20:5700/2) Recv SETFORMAT cmd
2026-01-29 01:32:07.339 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.28.20:5700/2) TRXD header version 0 -> 1
2026-01-29 01:32:07.342 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.28.20:5700/3) Recv RXTUNE cmd
2026-01-29 01:32:07.342 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.28.20:5700/3) Recv TXTUNE cmd
2026-01-29 01:32:07.342 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.28.20:5700/3) Recv SETFORMAT cmd
2026-01-29 01:32:07.342 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.28.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 01:32:07.342 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 01:32:07.343 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.28.20:5700/3) Recv NOMTXPOWER cmd
2026-01-29 01:32:07.343 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.28.20:5700/3) Recv SETFORMAT cmd
2026-01-29 01:32:07.343 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.28.20:5700/3) TRXD header version 0 -> 1
2026-01-29 01:32:07.345 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.28.20:5700) Recv RXTUNE cmd
2026-01-29 01:32:07.345 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETTSC
2026-01-29 01:32:07.345 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETTSC
2026-01-29 01:32:07.345 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETTSC
2026-01-29 01:32:07.345 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.28.20:5700) Recv TXTUNE cmd
2026-01-29 01:32:07.345 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETTSC
2026-01-29 01:32:07.345 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.28.20:5700) Recv NOMTXPOWER cmd
2026-01-29 01:32:07.345 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETRXGAIN
2026-01-29 01:32:07.346 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.28.20:5700) Recv POWERON CMD
2026-01-29 01:32:07.346 [INFO] ctrl_if_trx.py:109 (BTS@172.18.28.20:5700) Starting transceiver...
2026-01-29 01:32:07.346 [INFO] transceiver.py:243 Starting clock generator
2026-01-29 01:32:07.346 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-01-29 01:32:07.346 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:32:07.346 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETRXGAIN
2026-01-29 01:32:07.346 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETRXGAIN
2026-01-29 01:32:07.346 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETRXGAIN
2026-01-29 01:32:07.347 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:32:07.347 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:32:07.347 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:32:07.347 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 01:32:07.347 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:32:07.347 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:32:07.347 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 01:32:07.347 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:32:07.347 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:32:07.347 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:32:07.347 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 01:32:07.347 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:32:07.347 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:32:07.347 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:32:07.347 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 01:32:07.347 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:32:07.347 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:32:07.347 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:32:07.347 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 01:32:07.347 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:32:07.347 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:32:07.347 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:32:07.347 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 01:32:07.347 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:32:07.347 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:32:07.347 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 01:32:07.347 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:32:07.348 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 01:32:07.348 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:32:07.348 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:32:07.348 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:32:07.351 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-01-29 01:32:07.833 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-01-29 01:32:07.878 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:07.878 [DEBUG] fake_trx.py:278 (BTS@172.18.28.20:5700) Recv FAKE_TOA cmd
2026-01-29 01:32:07.879 [DEBUG] fake_trx.py:297 (BTS@172.18.28.20:5700) Recv FAKE_RSSI cmd
2026-01-29 01:32:07.879 [DEBUG] fake_trx.py:322 (BTS@172.18.28.20:5700) Recv FAKE_CI cmd
2026-01-29 01:32:07.895 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 01:32:07.895 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 01:32:07.895 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 01:32:07.901 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 01:32:07.901 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 01:32:07.901 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 01:32:07.902 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.28.22:6700) Recv POWERON CMD
2026-01-29 01:32:07.902 [INFO] ctrl_if_trx.py:109 (MS@172.18.28.22:6700) Starting transceiver...
2026-01-29 01:32:07.944 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:08.105 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 01:32:08.106 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 01:32:08.106 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 01:32:08.107 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 01:32:08.305 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-01-29 01:32:08.350 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 01:32:08.350 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 01:32:08.352 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 01:32:08.355 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 01:32:08.505 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 01:32:08.507 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:08.509 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 01:32:08.510 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 01:32:08.529 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 01:32:08.529 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 01:32:08.529 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 01:32:08.530 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 01:32:08.531 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 01:32:08.531 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 01:32:08.531 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.28.22:6700) Recv POWERON CMD
2026-01-29 01:32:08.531 [INFO] ctrl_if_trx.py:109 (MS@172.18.28.22:6700) Starting transceiver...
2026-01-29 01:32:08.555 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:08.603 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 01:32:08.604 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 01:32:08.604 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 01:32:08.604 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 01:32:08.776 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-01-29 01:32:08.994 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 01:32:08.995 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:08.998 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 01:32:08.998 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 01:32:09.018 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 01:32:09.018 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 01:32:09.019 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 01:32:09.020 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 01:32:09.020 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 01:32:09.020 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 01:32:09.020 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.28.22:6700) Recv POWERON CMD
2026-01-29 01:32:09.020 [INFO] ctrl_if_trx.py:109 (MS@172.18.28.22:6700) Starting transceiver...
2026-01-29 01:32:09.074 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:09.247 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-01-29 01:32:09.282 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 01:32:09.282 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 01:32:09.282 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 01:32:09.283 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 01:32:09.351 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 01:32:09.351 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 01:32:09.352 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 01:32:09.356 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 01:32:09.681 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 01:32:09.683 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:09.686 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 01:32:09.686 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 01:32:09.699 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 01:32:09.699 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 01:32:09.699 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 01:32:09.700 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 01:32:09.700 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 01:32:09.701 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 01:32:09.701 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.28.22:6700) Recv POWERON CMD
2026-01-29 01:32:09.701 [INFO] ctrl_if_trx.py:109 (MS@172.18.28.22:6700) Starting transceiver...
2026-01-29 01:32:09.718 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-01-29 01:32:09.732 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:09.780 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 01:32:09.780 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 01:32:09.780 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 01:32:09.781 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 01:32:10.171 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 01:32:10.173 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:10.176 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 01:32:10.176 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 01:32:10.189 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-01-29 01:32:10.194 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 01:32:10.194 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 01:32:10.194 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 01:32:10.195 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 01:32:10.195 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 01:32:10.195 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 01:32:10.195 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.28.22:6700) Recv POWERON CMD
2026-01-29 01:32:10.195 [INFO] ctrl_if_trx.py:109 (MS@172.18.28.22:6700) Starting transceiver...
2026-01-29 01:32:10.253 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:10.351 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 01:32:10.352 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 01:32:10.353 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 01:32:10.357 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 01:32:10.459 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 01:32:10.459 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 01:32:10.459 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 01:32:10.459 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 01:32:10.660 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-01-29 01:32:11.130 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-01-29 01:32:11.191 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 01:32:11.193 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:11.195 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 01:32:11.196 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 01:32:11.211 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 01:32:11.211 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 01:32:11.211 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 01:32:11.213 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 01:32:11.213 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 01:32:11.213 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 01:32:11.213 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.28.22:6700) Recv POWERON CMD
2026-01-29 01:32:11.213 [INFO] ctrl_if_trx.py:109 (MS@172.18.28.22:6700) Starting transceiver...
2026-01-29 01:32:11.223 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:11.352 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 01:32:11.353 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 01:32:11.354 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 01:32:11.358 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 01:32:11.401 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 01:32:11.401 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 01:32:11.401 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 01:32:11.401 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 01:32:11.601 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-01-29 01:32:12.072 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-01-29 01:32:12.211 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 01:32:12.212 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:12.215 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 01:32:12.215 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 01:32:12.230 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 01:32:12.230 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 01:32:12.231 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 01:32:12.232 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 01:32:12.232 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 01:32:12.232 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 01:32:12.232 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.28.22:6700) Recv POWERON CMD
2026-01-29 01:32:12.232 [INFO] ctrl_if_trx.py:109 (MS@172.18.28.22:6700) Starting transceiver...
2026-01-29 01:32:12.277 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:12.342 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 01:32:12.342 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 01:32:12.343 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 01:32:12.343 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 01:32:12.543 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-01-29 01:32:12.751 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 01:32:12.753 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:12.756 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 01:32:12.756 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 01:32:12.773 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 01:32:12.773 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 01:32:12.774 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 01:32:12.775 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 01:32:12.775 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 01:32:12.775 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 01:32:12.775 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.28.22:6700) Recv POWERON CMD
2026-01-29 01:32:12.776 [INFO] ctrl_if_trx.py:109 (MS@172.18.28.22:6700) Starting transceiver...
2026-01-29 01:32:12.840 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 01:32:12.841 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:13.013 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-01-29 01:32:13.048 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 01:32:13.048 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 01:32:13.048 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 01:32:13.049 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 01:32:13.484 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-01-29 01:32:13.771 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 01:32:13.773 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:13.776 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 01:32:13.777 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 01:32:13.795 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 01:32:13.795 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 01:32:13.795 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 01:32:13.796 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 01:32:13.796 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 01:32:13.796 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 01:32:13.796 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.28.22:6700) Recv POWERON CMD
2026-01-29 01:32:13.796 [INFO] ctrl_if_trx.py:109 (MS@172.18.28.22:6700) Starting transceiver...
2026-01-29 01:32:13.813 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:13.960 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-01-29 01:32:13.996 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 01:32:13.997 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 01:32:13.997 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 01:32:13.997 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 01:32:14.429 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-01-29 01:32:14.793 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 01:32:14.795 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:14.798 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 01:32:14.798 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 01:32:14.814 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 01:32:14.814 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 01:32:14.814 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 01:32:14.815 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 01:32:14.816 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 01:32:14.816 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 01:32:14.816 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.28.22:6700) Recv POWERON CMD
2026-01-29 01:32:14.816 [INFO] ctrl_if_trx.py:109 (MS@172.18.28.22:6700) Starting transceiver...
2026-01-29 01:32:14.868 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 01:32:14.869 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:14.899 [DEBUG] clck_gen.py:113 IND CLOCK 1632
2026-01-29 01:32:14.933 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 01:32:14.934 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 01:32:14.934 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 01:32:14.934 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 01:32:15.370 [DEBUG] clck_gen.py:113 IND CLOCK 1734
2026-01-29 01:32:15.693 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 01:32:15.695 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:15.697 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 01:32:15.698 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 01:32:15.716 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 01:32:15.716 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 01:32:15.716 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 01:32:15.717 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 01:32:15.717 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 01:32:15.717 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 01:32:15.717 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.28.22:6700) Recv POWERON CMD
2026-01-29 01:32:15.717 [INFO] ctrl_if_trx.py:109 (MS@172.18.28.22:6700) Starting transceiver...
2026-01-29 01:32:15.751 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:15.840 [DEBUG] clck_gen.py:113 IND CLOCK 1836
2026-01-29 01:32:15.875 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 01:32:15.875 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 01:32:15.875 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 01:32:15.876 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 01:32:16.311 [DEBUG] clck_gen.py:113 IND CLOCK 1938
2026-01-29 01:32:16.653 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 01:32:16.655 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:16.658 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 01:32:16.658 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 01:32:16.666 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 01:32:16.666 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 01:32:16.667 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 01:32:16.667 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 01:32:16.667 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 01:32:16.667 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 01:32:16.668 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.28.22:6700) Recv POWERON CMD
2026-01-29 01:32:16.668 [INFO] ctrl_if_trx.py:109 (MS@172.18.28.22:6700) Starting transceiver...
2026-01-29 01:32:16.688 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:16.782 [DEBUG] clck_gen.py:113 IND CLOCK 2040
2026-01-29 01:32:16.816 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 01:32:16.817 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 01:32:16.817 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 01:32:16.817 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 01:32:17.193 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 01:32:17.195 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:17.198 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 01:32:17.198 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 01:32:17.214 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 01:32:17.214 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 01:32:17.214 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 01:32:17.215 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 01:32:17.215 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 01:32:17.215 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 01:32:17.215 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.28.22:6700) Recv POWERON CMD
2026-01-29 01:32:17.215 [INFO] ctrl_if_trx.py:109 (MS@172.18.28.22:6700) Starting transceiver...
2026-01-29 01:32:17.253 [DEBUG] clck_gen.py:113 IND CLOCK 2142
2026-01-29 01:32:17.269 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:17.314 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 01:32:17.315 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 01:32:17.315 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 01:32:17.315 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 01:32:17.406 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 01:32:17.408 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:17.411 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 01:32:17.411 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 01:32:17.421 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 01:32:17.421 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 01:32:17.421 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 01:32:17.422 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 01:32:17.422 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 01:32:17.423 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 01:32:17.423 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.28.22:6700) Recv POWERON CMD
2026-01-29 01:32:17.423 [INFO] ctrl_if_trx.py:109 (MS@172.18.28.22:6700) Starting transceiver...
2026-01-29 01:32:17.459 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:17.523 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 01:32:17.523 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 01:32:17.523 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 01:32:17.524 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 01:32:17.723 [DEBUG] clck_gen.py:113 IND CLOCK 2244
2026-01-29 01:32:17.895 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 01:32:17.897 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:17.900 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 01:32:17.900 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 01:32:17.919 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 01:32:17.919 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 01:32:17.919 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 01:32:17.920 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 01:32:17.920 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 01:32:17.920 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 01:32:17.920 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.28.22:6700) Recv POWERON CMD
2026-01-29 01:32:17.920 [INFO] ctrl_if_trx.py:109 (MS@172.18.28.22:6700) Starting transceiver...
2026-01-29 01:32:17.975 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:18.021 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 01:32:18.021 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 01:32:18.021 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 01:32:18.021 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 01:32:18.194 [DEBUG] clck_gen.py:113 IND CLOCK 2346
2026-01-29 01:32:18.384 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 01:32:18.386 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:18.390 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 01:32:18.390 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 01:32:18.408 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 01:32:18.408 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 01:32:18.408 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 01:32:18.410 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 01:32:18.410 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 01:32:18.410 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 01:32:18.410 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.28.22:6700) Recv POWERON CMD
2026-01-29 01:32:18.410 [INFO] ctrl_if_trx.py:109 (MS@172.18.28.22:6700) Starting transceiver...
2026-01-29 01:32:18.445 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:18.491 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 01:32:18.492 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 01:32:18.492 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 01:32:18.492 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 01:32:18.665 [DEBUG] clck_gen.py:113 IND CLOCK 2448
2026-01-29 01:32:18.873 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 01:32:18.875 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:18.878 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 01:32:18.878 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 01:32:18.890 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 01:32:18.890 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 01:32:18.890 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 01:32:18.891 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 01:32:18.891 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 01:32:18.891 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 01:32:18.891 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.28.22:6700) Recv POWERON CMD
2026-01-29 01:32:18.891 [INFO] ctrl_if_trx.py:109 (MS@172.18.28.22:6700) Starting transceiver...
2026-01-29 01:32:18.913 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:18.962 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 01:32:18.962 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 01:32:18.963 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 01:32:18.963 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 01:32:19.053 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 01:32:19.055 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:19.058 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 01:32:19.058 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 01:32:19.076 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 01:32:19.076 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 01:32:19.076 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 01:32:19.078 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 01:32:19.078 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 01:32:19.078 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 01:32:19.078 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.28.22:6700) Recv POWERON CMD
2026-01-29 01:32:19.078 [INFO] ctrl_if_trx.py:109 (MS@172.18.28.22:6700) Starting transceiver...
2026-01-29 01:32:19.105 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:19.135 [DEBUG] clck_gen.py:113 IND CLOCK 2550
2026-01-29 01:32:19.170 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 01:32:19.171 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 01:32:19.171 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 01:32:19.171 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 01:32:19.543 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 01:32:19.544 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:19.545 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 01:32:19.545 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 01:32:19.554 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 01:32:19.554 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 01:32:19.554 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 01:32:19.556 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 01:32:19.556 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 01:32:19.556 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 01:32:19.556 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.28.22:6700) Recv POWERON CMD
2026-01-29 01:32:19.556 [INFO] ctrl_if_trx.py:109 (MS@172.18.28.22:6700) Starting transceiver...
2026-01-29 01:32:19.606 [DEBUG] clck_gen.py:113 IND CLOCK 2652
2026-01-29 01:32:19.622 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:19.668 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 01:32:19.669 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 01:32:19.669 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 01:32:19.669 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 01:32:20.032 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 01:32:20.034 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:20.037 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 01:32:20.037 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 01:32:20.054 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 01:32:20.054 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 01:32:20.054 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 01:32:20.056 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 01:32:20.056 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 01:32:20.056 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 01:32:20.056 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.28.22:6700) Recv POWERON CMD
2026-01-29 01:32:20.056 [INFO] ctrl_if_trx.py:109 (MS@172.18.28.22:6700) Starting transceiver...
2026-01-29 01:32:20.077 [DEBUG] clck_gen.py:113 IND CLOCK 2754
2026-01-29 01:32:20.092 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:20.139 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 01:32:20.139 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 01:32:20.140 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 01:32:20.140 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 01:32:20.519 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 01:32:20.520 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:20.520 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 01:32:20.521 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 01:32:20.524 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 01:32:20.524 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 01:32:20.524 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 01:32:20.524 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 01:32:20.524 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 01:32:20.524 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 01:32:20.524 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 01:32:20.524 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 01:32:20.524 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.28.20:5700) Recv POWEROFF cmd
2026-01-29 01:32:20.524 [INFO] ctrl_if_trx.py:117 (BTS@172.18.28.20:5700) Stopping transceiver...
2026-01-29 01:32:20.524 [INFO] transceiver.py:246 Stopping clock generator
2026-01-29 01:32:20.525 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=2853 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 01:32:20.525 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=2853 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 01:32:20.525 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=2853 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 01:32:20.525 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=2853 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 01:32:20.525 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=2853 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 01:32:25.527 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.28.20:5700) Recv POWEROFF cmd
2026-01-29 01:32:25.528 [INFO] ctrl_if_trx.py:117 (BTS@172.18.28.20:5700) Stopping transceiver...
2026-01-29 01:32:25.529 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 01:32:25.530 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 01:32:25.531 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 01:32:25.532 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 01:32:25.534 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 01:32:25.535 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.28.20:5700) Recv SETFORMAT cmd
2026-01-29 01:32:25.535 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.28.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 01:32:25.535 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.28.20:5700) Recv SETFORMAT cmd
2026-01-29 01:32:25.535 [INFO] ctrl_if_trx.py:201 (BTS@172.18.28.20:5700) TRXD header version 1 -> 1
2026-01-29 01:32:25.537 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.28.20:5700/1) Recv RXTUNE cmd
2026-01-29 01:32:25.537 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.28.20:5700/1) Recv TXTUNE cmd
2026-01-29 01:32:25.538 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.28.20:5700/1) Recv SETFORMAT cmd
2026-01-29 01:32:25.538 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.28.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 01:32:25.538 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 01:32:25.538 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.28.20:5700/1) Recv NOMTXPOWER cmd
2026-01-29 01:32:25.539 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.28.20:5700/1) Recv SETFORMAT cmd
2026-01-29 01:32:25.539 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.28.20:5700/1) TRXD header version 1 -> 1
2026-01-29 01:32:25.540 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.28.20:5700/2) Recv RXTUNE cmd
2026-01-29 01:32:25.540 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.28.20:5700/2) Recv TXTUNE cmd
2026-01-29 01:32:25.540 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.28.20:5700/2) Recv SETFORMAT cmd
2026-01-29 01:32:25.540 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.28.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 01:32:25.540 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 01:32:25.540 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.28.20:5700/2) Recv NOMTXPOWER cmd
2026-01-29 01:32:25.540 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.28.20:5700/2) Recv SETFORMAT cmd
2026-01-29 01:32:25.540 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.28.20:5700/2) TRXD header version 1 -> 1
2026-01-29 01:32:25.542 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.28.20:5700/3) Recv RXTUNE cmd
2026-01-29 01:32:25.542 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.28.20:5700/3) Recv TXTUNE cmd
2026-01-29 01:32:25.542 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.28.20:5700/3) Recv SETFORMAT cmd
2026-01-29 01:32:25.542 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.28.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 01:32:25.542 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 01:32:25.542 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.28.20:5700/3) Recv NOMTXPOWER cmd
2026-01-29 01:32:25.542 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.28.20:5700/3) Recv SETFORMAT cmd
2026-01-29 01:32:25.542 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.28.20:5700/3) TRXD header version 1 -> 1
2026-01-29 01:32:25.544 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.28.20:5700) Recv RXTUNE cmd
2026-01-29 01:32:25.544 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETTSC
2026-01-29 01:32:25.544 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETTSC
2026-01-29 01:32:25.544 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETTSC
2026-01-29 01:32:25.544 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.28.20:5700) Recv TXTUNE cmd
2026-01-29 01:32:25.544 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETRXGAIN
2026-01-29 01:32:25.544 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETRXGAIN
2026-01-29 01:32:25.544 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETRXGAIN
2026-01-29 01:32:25.544 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETTSC
2026-01-29 01:32:25.544 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:32:25.544 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:32:25.544 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:32:25.544 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.28.20:5700) Recv NOMTXPOWER cmd
2026-01-29 01:32:25.544 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:32:25.544 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:32:25.544 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:32:25.544 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.28.20:5700) Recv POWERON CMD
2026-01-29 01:32:25.544 [INFO] ctrl_if_trx.py:109 (BTS@172.18.28.20:5700) Starting transceiver...
2026-01-29 01:32:25.544 [INFO] transceiver.py:243 Starting clock generator
2026-01-29 01:32:25.545 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-01-29 01:32:25.545 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:32:25.545 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:32:25.545 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:32:25.545 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETRXGAIN
2026-01-29 01:32:25.545 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:32:25.545 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:32:25.545 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:32:25.545 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 01:32:25.545 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:32:25.545 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:32:25.545 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:32:25.545 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 01:32:25.545 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:32:25.545 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:32:25.545 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:32:25.545 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 01:32:25.545 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:32:25.545 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:32:25.545 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:32:25.545 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 01:32:25.545 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:32:25.545 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:32:25.545 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:32:25.546 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 01:32:25.546 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 01:32:25.546 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 01:32:25.546 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 01:32:25.549 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-01-29 01:32:26.033 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-01-29 01:32:26.068 [DEBUG] fake_trx.py:278 (BTS@172.18.28.20:5700) Recv FAKE_TOA cmd
2026-01-29 01:32:26.070 [DEBUG] fake_trx.py:297 (BTS@172.18.28.20:5700) Recv FAKE_RSSI cmd
2026-01-29 01:32:26.071 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:26.072 [DEBUG] fake_trx.py:322 (BTS@172.18.28.20:5700) Recv FAKE_CI cmd
2026-01-29 01:32:26.095 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 01:32:26.095 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 01:32:26.096 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 01:32:26.104 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:26.108 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:26.112 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:26.116 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:26.120 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:26.125 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:26.129 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:26.133 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:26.137 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:26.141 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:26.145 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:26.149 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:26.153 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:26.156 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:26.160 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:26.163 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:26.167 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:26.171 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:26.175 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:26.178 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:26.181 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:26.185 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:26.188 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:26.191 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:26.195 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:26.199 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:26.203 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:26.207 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:26.210 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:26.212 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:26.215 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:26.217 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:26.220 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:26.223 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:26.227 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:26.230 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:26.233 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:26.236 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:26.239 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:26.242 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:26.245 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:26.248 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:26.251 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:26.255 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:26.260 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:26.264 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:26.268 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:26.272 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:26.275 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:26.279 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:26.282 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:26.285 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:26.288 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:26.291 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:26.293 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:26.296 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:26.298 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:26.299 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:26.301 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:26.303 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:26.305 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:26.306 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:26.308 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:26.309 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:26.311 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:26.313 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:26.314 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:26.316 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
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2026-01-29 01:32:26.479 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:26.480 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:26.480 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:26.481 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:26.482 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:26.482 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:26.483 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:26.483 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:26.484 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:26.485 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:26.485 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:26.486 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:26.487 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:26.487 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:26.488 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:26.488 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:26.489 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:26.490 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:26.490 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:26.491 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:26.491 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:26.492 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:26.492 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:26.493 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:26.493 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:26.494 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:26.494 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:26.495 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:26.495 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:26.496 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:26.496 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:26.497 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:26.497 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:26.498 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:26.498 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:26.499 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:26.499 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:26.500 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:26.500 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:26.500 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:26.501 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:26.501 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:26.502 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:26.502 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:26.503 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:26.503 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:26.503 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:26.504 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-01-29 01:32:26.504 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:26.504 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:26.505 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:26.505 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:26.505 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:26.506 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:26.506 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:26.507 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:26.507 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:26.507 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:26.508 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:26.508 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:26.509 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:26.509 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:26.509 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:26.510 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:26.510 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:26.511 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:26.511 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:26.512 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:26.512 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:26.512 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:26.513 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:26.513 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:26.514 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:26.514 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:26.514 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:26.515 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:26.515 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:26.516 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:26.516 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:26.516 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:26.517 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:26.517 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:26.518 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:26.518 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:26.519 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:26.519 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:26.520 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:26.520 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:26.520 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:26.521 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:26.521 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:26.522 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:26.522 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:26.523 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:26.523 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:26.524 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:26.524 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:26.524 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:26.525 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:26.525 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:26.526 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:26.526 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:26.527 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:26.527 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:26.528 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:26.528 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:26.529 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:26.529 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:26.530 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:26.531 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:26.531 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:26.532 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:26.532 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:26.533 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:26.533 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:26.533 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:26.534 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:26.534 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:26.535 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:26.535 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:26.536 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:26.536 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:26.536 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:26.537 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:26.537 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:26.538 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:26.538 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:26.539 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:26.539 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:26.540 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:26.540 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:26.540 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:26.541 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:26.541 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:26.542 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:26.542 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:26.543 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:26.543 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:26.543 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:26.544 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:26.544 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:26.545 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:26.545 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:26.546 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:26.546 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:26.546 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 01:32:26.546 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:26.547 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 01:32:26.547 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:26.547 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:26.548 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 01:32:26.548 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:26.548 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:26.549 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:26.549 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:26.549 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 01:32:26.549 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:26.550 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:26.550 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:26.551 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:26.551 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:26.552 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:26.552 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
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2026-01-29 01:32:26.695 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
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2026-01-29 01:32:26.696 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:26.696 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:26.697 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:26.698 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:26.698 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:26.699 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:26.699 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:26.700 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:26.700 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:26.701 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:26.701 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:26.702 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:26.702 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:26.703 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:26.703 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:26.704 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:26.704 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:26.705 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:26.705 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:26.706 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:26.706 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:26.707 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:26.707 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:26.708 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:26.708 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:26.708 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:26.709 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:26.709 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:26.710 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:26.710 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:26.711 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:26.711 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:26.712 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:26.712 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:26.713 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:26.713 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:26.714 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:26.714 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:26.715 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:26.715 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:26.716 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:26.717 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:26.717 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:26.718 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:26.719 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:26.719 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:26.720 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:26.721 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:26.722 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:26.722 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:26.723 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:26.724 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:26.725 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:26.726 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:26.727 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:26.727 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:26.728 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:26.729 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:26.730 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:26.731 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:26.732 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:26.732 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:26.733 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:26.734 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:26.735 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:26.736 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:26.737 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:26.737 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:26.738 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:26.739 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:26.740 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:26.741 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:26.742 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:26.743 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:26.744 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:26.744 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:26.745 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:26.746 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:26.747 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:26.748 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:26.749 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:26.750 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:26.751 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:26.752 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:26.753 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:26.754 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:26.755 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:26.756 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:26.757 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:26.758 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:26.759 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:26.760 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:26.761 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:26.762 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:26.763 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:26.764 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:26.765 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:26.766 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:26.767 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:26.768 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:26.769 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:26.770 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:26.772 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:26.773 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:26.775 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:26.777 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:26.778 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:26.780 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:26.782 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:26.784 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:26.786 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:26.787 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:26.789 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:26.791 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:26.800 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 01:32:26.800 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 01:32:26.800 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 01:32:26.800 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 01:32:26.801 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 01:32:26.801 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 01:32:26.801 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 01:32:26.801 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 01:32:26.801 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.28.20:5700) Recv POWEROFF cmd
2026-01-29 01:32:26.801 [INFO] ctrl_if_trx.py:117 (BTS@172.18.28.20:5700) Stopping transceiver...
2026-01-29 01:32:26.801 [INFO] transceiver.py:246 Stopping clock generator
2026-01-29 01:32:31.804 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.28.20:5700) Recv POWEROFF cmd
2026-01-29 01:32:31.804 [INFO] ctrl_if_trx.py:117 (BTS@172.18.28.20:5700) Stopping transceiver...
2026-01-29 01:32:31.806 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 01:32:31.807 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 01:32:31.807 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 01:32:31.807 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 01:32:31.810 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 01:32:31.810 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.28.20:5700) Recv SETFORMAT cmd
2026-01-29 01:32:31.810 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.28.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 01:32:31.810 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.28.20:5700) Recv SETFORMAT cmd
2026-01-29 01:32:31.810 [INFO] ctrl_if_trx.py:201 (BTS@172.18.28.20:5700) TRXD header version 1 -> 1
2026-01-29 01:32:31.813 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.28.20:5700/1) Recv RXTUNE cmd
2026-01-29 01:32:31.813 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.28.20:5700/1) Recv TXTUNE cmd
2026-01-29 01:32:31.813 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.28.20:5700/1) Recv SETFORMAT cmd
2026-01-29 01:32:31.813 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.28.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 01:32:31.813 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 01:32:31.813 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.28.20:5700/1) Recv NOMTXPOWER cmd
2026-01-29 01:32:31.814 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.28.20:5700/1) Recv SETFORMAT cmd
2026-01-29 01:32:31.814 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.28.20:5700/1) TRXD header version 1 -> 1
2026-01-29 01:32:31.815 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.28.20:5700/2) Recv RXTUNE cmd
2026-01-29 01:32:31.816 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.28.20:5700/2) Recv TXTUNE cmd
2026-01-29 01:32:31.816 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.28.20:5700/2) Recv SETFORMAT cmd
2026-01-29 01:32:31.816 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.28.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 01:32:31.816 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 01:32:31.816 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.28.20:5700/2) Recv NOMTXPOWER cmd
2026-01-29 01:32:31.816 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.28.20:5700/2) Recv SETFORMAT cmd
2026-01-29 01:32:31.816 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.28.20:5700/2) TRXD header version 1 -> 1
2026-01-29 01:32:31.817 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.28.20:5700/3) Recv RXTUNE cmd
2026-01-29 01:32:31.817 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.28.20:5700/3) Recv TXTUNE cmd
2026-01-29 01:32:31.818 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.28.20:5700/3) Recv SETFORMAT cmd
2026-01-29 01:32:31.818 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.28.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 01:32:31.818 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 01:32:31.818 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.28.20:5700/3) Recv NOMTXPOWER cmd
2026-01-29 01:32:31.818 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.28.20:5700/3) Recv SETFORMAT cmd
2026-01-29 01:32:31.818 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.28.20:5700/3) TRXD header version 1 -> 1
2026-01-29 01:32:31.820 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.28.20:5700) Recv RXTUNE cmd
2026-01-29 01:32:31.820 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETTSC
2026-01-29 01:32:31.820 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETTSC
2026-01-29 01:32:31.820 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETTSC
2026-01-29 01:32:31.820 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.28.20:5700) Recv TXTUNE cmd
2026-01-29 01:32:31.820 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETRXGAIN
2026-01-29 01:32:31.820 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETRXGAIN
2026-01-29 01:32:31.820 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETRXGAIN
2026-01-29 01:32:31.820 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETTSC
2026-01-29 01:32:31.820 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:32:31.820 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:32:31.820 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:32:31.820 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.28.20:5700) Recv NOMTXPOWER cmd
2026-01-29 01:32:31.820 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:32:31.820 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:32:31.820 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:32:31.820 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.28.20:5700) Recv POWERON CMD
2026-01-29 01:32:31.820 [INFO] ctrl_if_trx.py:109 (BTS@172.18.28.20:5700) Starting transceiver...
2026-01-29 01:32:31.820 [INFO] transceiver.py:243 Starting clock generator
2026-01-29 01:32:31.820 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-01-29 01:32:31.820 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:32:31.820 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:32:31.820 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:32:31.821 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETRXGAIN
2026-01-29 01:32:31.821 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:32:31.821 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:32:31.821 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:32:31.821 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 01:32:31.821 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:32:31.821 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:32:31.821 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:32:31.821 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 01:32:31.821 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:32:31.821 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:32:31.821 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:32:31.821 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 01:32:31.821 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:32:31.821 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:32:31.821 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:32:31.821 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 01:32:31.821 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:32:31.821 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:32:31.821 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:32:31.821 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 01:32:31.821 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 01:32:31.821 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 01:32:31.821 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 01:32:31.825 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-01-29 01:32:32.308 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-01-29 01:32:32.344 [DEBUG] fake_trx.py:278 (BTS@172.18.28.20:5700) Recv FAKE_TOA cmd
2026-01-29 01:32:32.346 [DEBUG] fake_trx.py:297 (BTS@172.18.28.20:5700) Recv FAKE_RSSI cmd
2026-01-29 01:32:32.347 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:32.348 [DEBUG] fake_trx.py:322 (BTS@172.18.28.20:5700) Recv FAKE_CI cmd
2026-01-29 01:32:32.371 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 01:32:32.371 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 01:32:32.372 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 01:32:32.377 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:32.386 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:32.400 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 01:32:32.400 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 01:32:32.400 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 01:32:32.401 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 01:32:32.406 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 01:32:32.406 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 01:32:32.406 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 01:32:32.406 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 01:32:32.406 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.28.20:5700) Recv POWEROFF cmd
2026-01-29 01:32:32.406 [INFO] ctrl_if_trx.py:117 (BTS@172.18.28.20:5700) Stopping transceiver...
2026-01-29 01:32:32.406 [INFO] transceiver.py:246 Stopping clock generator
2026-01-29 01:32:32.407 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=124 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 01:32:32.407 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=124 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 01:32:32.407 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=124 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 01:32:32.407 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=124 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 01:32:37.402 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.28.20:5700) Recv POWEROFF cmd
2026-01-29 01:32:37.402 [INFO] ctrl_if_trx.py:117 (BTS@172.18.28.20:5700) Stopping transceiver...
2026-01-29 01:32:37.403 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 01:32:37.405 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 01:32:37.405 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 01:32:37.406 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 01:32:37.408 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 01:32:37.408 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.28.20:5700) Recv SETFORMAT cmd
2026-01-29 01:32:37.408 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.28.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 01:32:37.409 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.28.20:5700) Recv SETFORMAT cmd
2026-01-29 01:32:37.409 [INFO] ctrl_if_trx.py:201 (BTS@172.18.28.20:5700) TRXD header version 1 -> 1
2026-01-29 01:32:37.409 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.28.20:5700/1) Recv RXTUNE cmd
2026-01-29 01:32:37.409 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.28.20:5700/1) Recv TXTUNE cmd
2026-01-29 01:32:37.410 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.28.20:5700/1) Recv SETFORMAT cmd
2026-01-29 01:32:37.410 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.28.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 01:32:37.410 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 01:32:37.410 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.28.20:5700/1) Recv NOMTXPOWER cmd
2026-01-29 01:32:37.410 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.28.20:5700/1) Recv SETFORMAT cmd
2026-01-29 01:32:37.410 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.28.20:5700/1) TRXD header version 1 -> 1
2026-01-29 01:32:37.410 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.28.20:5700/2) Recv RXTUNE cmd
2026-01-29 01:32:37.410 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.28.20:5700/2) Recv TXTUNE cmd
2026-01-29 01:32:37.410 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.28.20:5700/2) Recv SETFORMAT cmd
2026-01-29 01:32:37.410 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.28.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 01:32:37.410 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 01:32:37.411 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.28.20:5700/2) Recv NOMTXPOWER cmd
2026-01-29 01:32:37.411 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.28.20:5700/2) Recv SETFORMAT cmd
2026-01-29 01:32:37.411 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.28.20:5700/2) TRXD header version 1 -> 1
2026-01-29 01:32:37.411 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.28.20:5700/3) Recv RXTUNE cmd
2026-01-29 01:32:37.411 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.28.20:5700/3) Recv TXTUNE cmd
2026-01-29 01:32:37.411 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.28.20:5700/3) Recv SETFORMAT cmd
2026-01-29 01:32:37.411 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.28.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 01:32:37.412 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 01:32:37.412 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.28.20:5700/3) Recv NOMTXPOWER cmd
2026-01-29 01:32:37.412 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.28.20:5700/3) Recv SETFORMAT cmd
2026-01-29 01:32:37.412 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.28.20:5700/3) TRXD header version 1 -> 1
2026-01-29 01:32:37.413 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.28.20:5700) Recv RXTUNE cmd
2026-01-29 01:32:37.413 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETTSC
2026-01-29 01:32:37.413 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETTSC
2026-01-29 01:32:37.413 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETTSC
2026-01-29 01:32:37.413 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.28.20:5700) Recv TXTUNE cmd
2026-01-29 01:32:37.413 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETRXGAIN
2026-01-29 01:32:37.413 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETRXGAIN
2026-01-29 01:32:37.413 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETRXGAIN
2026-01-29 01:32:37.413 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETTSC
2026-01-29 01:32:37.413 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:32:37.413 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:32:37.413 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.28.20:5700) Recv NOMTXPOWER cmd
2026-01-29 01:32:37.413 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:32:37.413 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:32:37.413 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:32:37.413 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.28.20:5700) Recv POWERON CMD
2026-01-29 01:32:37.413 [INFO] ctrl_if_trx.py:109 (BTS@172.18.28.20:5700) Starting transceiver...
2026-01-29 01:32:37.413 [INFO] transceiver.py:243 Starting clock generator
2026-01-29 01:32:37.413 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-01-29 01:32:37.413 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:32:37.413 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:32:37.413 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:32:37.414 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETRXGAIN
2026-01-29 01:32:37.414 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:32:37.414 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:32:37.414 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:32:37.414 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 01:32:37.414 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:32:37.414 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:32:37.414 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:32:37.414 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 01:32:37.414 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:32:37.414 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:32:37.414 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:32:37.414 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 01:32:37.414 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:32:37.414 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:32:37.414 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:32:37.414 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 01:32:37.414 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:32:37.414 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:32:37.414 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:32:37.414 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 01:32:37.414 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:32:37.414 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 01:32:37.414 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 01:32:37.414 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 01:32:37.418 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-01-29 01:32:37.903 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-01-29 01:32:37.936 [DEBUG] fake_trx.py:278 (BTS@172.18.28.20:5700) Recv FAKE_TOA cmd
2026-01-29 01:32:37.938 [DEBUG] fake_trx.py:297 (BTS@172.18.28.20:5700) Recv FAKE_RSSI cmd
2026-01-29 01:32:37.939 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:37.940 [DEBUG] fake_trx.py:322 (BTS@172.18.28.20:5700) Recv FAKE_CI cmd
2026-01-29 01:32:37.957 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 01:32:37.957 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 01:32:37.958 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 01:32:37.976 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 01:32:37.976 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 01:32:37.976 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 01:32:37.976 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 01:32:37.977 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 01:32:37.977 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 01:32:37.977 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 01:32:37.977 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 01:32:37.977 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.28.20:5700) Recv POWEROFF cmd
2026-01-29 01:32:37.977 [INFO] ctrl_if_trx.py:117 (BTS@172.18.28.20:5700) Stopping transceiver...
2026-01-29 01:32:37.978 [INFO] transceiver.py:246 Stopping clock generator
2026-01-29 01:32:37.978 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=120 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 01:32:37.978 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=120 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 01:32:37.978 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=120 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 01:32:37.978 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=120 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 01:32:37.978 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=120 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 01:32:37.978 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=120 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 01:32:37.978 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=120 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 01:32:37.978 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=120 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 01:32:42.978 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.28.20:5700) Recv POWEROFF cmd
2026-01-29 01:32:42.978 [INFO] ctrl_if_trx.py:117 (BTS@172.18.28.20:5700) Stopping transceiver...
2026-01-29 01:32:42.982 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 01:32:42.982 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 01:32:42.982 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 01:32:42.982 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 01:32:42.988 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 01:32:42.989 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.28.20:5700) Recv SETFORMAT cmd
2026-01-29 01:32:42.989 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.28.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 01:32:42.989 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.28.20:5700) Recv SETFORMAT cmd
2026-01-29 01:32:42.989 [INFO] ctrl_if_trx.py:201 (BTS@172.18.28.20:5700) TRXD header version 1 -> 1
2026-01-29 01:32:42.991 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.28.20:5700/1) Recv RXTUNE cmd
2026-01-29 01:32:42.991 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.28.20:5700/1) Recv TXTUNE cmd
2026-01-29 01:32:42.992 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.28.20:5700/1) Recv SETFORMAT cmd
2026-01-29 01:32:42.992 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.28.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 01:32:42.992 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 01:32:42.993 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.28.20:5700/1) Recv NOMTXPOWER cmd
2026-01-29 01:32:42.993 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.28.20:5700/1) Recv SETFORMAT cmd
2026-01-29 01:32:42.993 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.28.20:5700/1) TRXD header version 1 -> 1
2026-01-29 01:32:42.994 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.28.20:5700/2) Recv RXTUNE cmd
2026-01-29 01:32:42.995 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.28.20:5700/2) Recv TXTUNE cmd
2026-01-29 01:32:42.995 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.28.20:5700/2) Recv SETFORMAT cmd
2026-01-29 01:32:42.995 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.28.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 01:32:42.996 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 01:32:42.996 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.28.20:5700/2) Recv NOMTXPOWER cmd
2026-01-29 01:32:42.996 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.28.20:5700/2) Recv SETFORMAT cmd
2026-01-29 01:32:42.996 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.28.20:5700/2) TRXD header version 1 -> 1
2026-01-29 01:32:42.997 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.28.20:5700/3) Recv RXTUNE cmd
2026-01-29 01:32:42.997 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.28.20:5700/3) Recv TXTUNE cmd
2026-01-29 01:32:42.997 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.28.20:5700/3) Recv SETFORMAT cmd
2026-01-29 01:32:42.997 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.28.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 01:32:42.997 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 01:32:42.997 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.28.20:5700/3) Recv NOMTXPOWER cmd
2026-01-29 01:32:42.998 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.28.20:5700/3) Recv SETFORMAT cmd
2026-01-29 01:32:42.998 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.28.20:5700/3) TRXD header version 1 -> 1
2026-01-29 01:32:43.000 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.28.20:5700) Recv RXTUNE cmd
2026-01-29 01:32:43.000 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETTSC
2026-01-29 01:32:43.000 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETTSC
2026-01-29 01:32:43.001 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETTSC
2026-01-29 01:32:43.001 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.28.20:5700) Recv TXTUNE cmd
2026-01-29 01:32:43.001 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETRXGAIN
2026-01-29 01:32:43.001 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETRXGAIN
2026-01-29 01:32:43.001 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETRXGAIN
2026-01-29 01:32:43.001 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETTSC
2026-01-29 01:32:43.001 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:32:43.001 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:32:43.001 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:32:43.001 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.28.20:5700) Recv NOMTXPOWER cmd
2026-01-29 01:32:43.001 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:32:43.001 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:32:43.001 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:32:43.001 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.28.20:5700) Recv POWERON CMD
2026-01-29 01:32:43.001 [INFO] ctrl_if_trx.py:109 (BTS@172.18.28.20:5700) Starting transceiver...
2026-01-29 01:32:43.001 [INFO] transceiver.py:243 Starting clock generator
2026-01-29 01:32:43.001 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-01-29 01:32:43.001 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:32:43.001 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:32:43.002 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:32:43.002 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETRXGAIN
2026-01-29 01:32:43.002 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:32:43.002 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:32:43.002 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:32:43.002 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 01:32:43.002 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:32:43.002 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:32:43.002 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:32:43.002 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 01:32:43.002 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:32:43.002 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:32:43.002 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:32:43.002 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 01:32:43.002 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:32:43.002 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:32:43.002 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:32:43.002 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 01:32:43.002 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:32:43.002 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:32:43.002 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:32:43.002 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 01:32:43.002 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 01:32:43.003 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 01:32:43.003 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 01:32:43.006 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-01-29 01:32:43.490 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-01-29 01:32:43.531 [DEBUG] fake_trx.py:278 (BTS@172.18.28.20:5700) Recv FAKE_TOA cmd
2026-01-29 01:32:43.533 [DEBUG] fake_trx.py:297 (BTS@172.18.28.20:5700) Recv FAKE_RSSI cmd
2026-01-29 01:32:43.533 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:43.535 [DEBUG] fake_trx.py:322 (BTS@172.18.28.20:5700) Recv FAKE_CI cmd
2026-01-29 01:32:43.560 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 01:32:43.561 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 01:32:43.561 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 01:32:43.587 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 01:32:43.587 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 01:32:43.587 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 01:32:43.595 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 01:32:43.595 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 01:32:43.595 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 01:32:43.603 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 01:32:43.603 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 01:32:43.603 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 01:32:43.612 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 01:32:43.612 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 01:32:43.612 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 01:32:43.620 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 01:32:43.620 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 01:32:43.620 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 01:32:43.628 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 01:32:43.628 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 01:32:43.628 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 01:32:43.637 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 01:32:43.637 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 01:32:43.637 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 01:32:43.645 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 01:32:43.645 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 01:32:43.645 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 01:32:43.654 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 01:32:43.654 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 01:32:43.654 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 01:32:43.661 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 01:32:43.662 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 01:32:43.662 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 01:32:43.669 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 01:32:43.669 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 01:32:43.669 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 01:32:43.676 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 01:32:43.676 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 01:32:43.676 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 01:32:43.680 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 01:32:43.680 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 01:32:43.680 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 01:32:43.680 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 01:32:43.681 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 01:32:43.681 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 01:32:43.681 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 01:32:43.681 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 01:32:43.681 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.28.20:5700) Recv POWEROFF cmd
2026-01-29 01:32:43.682 [INFO] ctrl_if_trx.py:117 (BTS@172.18.28.20:5700) Stopping transceiver...
2026-01-29 01:32:43.682 [INFO] transceiver.py:246 Stopping clock generator
2026-01-29 01:32:48.684 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.28.20:5700) Recv POWEROFF cmd
2026-01-29 01:32:48.685 [INFO] ctrl_if_trx.py:117 (BTS@172.18.28.20:5700) Stopping transceiver...
2026-01-29 01:32:48.686 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 01:32:48.687 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 01:32:48.687 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 01:32:48.688 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 01:32:48.697 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 01:32:48.699 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.28.20:5700) Recv SETFORMAT cmd
2026-01-29 01:32:48.699 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.28.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 01:32:48.700 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.28.20:5700) Recv SETFORMAT cmd
2026-01-29 01:32:48.700 [INFO] ctrl_if_trx.py:201 (BTS@172.18.28.20:5700) TRXD header version 1 -> 1
2026-01-29 01:32:48.704 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.28.20:5700/1) Recv RXTUNE cmd
2026-01-29 01:32:48.705 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.28.20:5700/1) Recv TXTUNE cmd
2026-01-29 01:32:48.705 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.28.20:5700/1) Recv SETFORMAT cmd
2026-01-29 01:32:48.705 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.28.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 01:32:48.705 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 01:32:48.705 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.28.20:5700/1) Recv NOMTXPOWER cmd
2026-01-29 01:32:48.705 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.28.20:5700/1) Recv SETFORMAT cmd
2026-01-29 01:32:48.705 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.28.20:5700/1) TRXD header version 1 -> 1
2026-01-29 01:32:48.708 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.28.20:5700/2) Recv RXTUNE cmd
2026-01-29 01:32:48.708 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.28.20:5700/2) Recv TXTUNE cmd
2026-01-29 01:32:48.708 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.28.20:5700/2) Recv SETFORMAT cmd
2026-01-29 01:32:48.708 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.28.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 01:32:48.708 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 01:32:48.708 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.28.20:5700/2) Recv NOMTXPOWER cmd
2026-01-29 01:32:48.709 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.28.20:5700/2) Recv SETFORMAT cmd
2026-01-29 01:32:48.709 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.28.20:5700/2) TRXD header version 1 -> 1
2026-01-29 01:32:48.711 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.28.20:5700/3) Recv RXTUNE cmd
2026-01-29 01:32:48.711 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.28.20:5700/3) Recv TXTUNE cmd
2026-01-29 01:32:48.711 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.28.20:5700/3) Recv SETFORMAT cmd
2026-01-29 01:32:48.711 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.28.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 01:32:48.711 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 01:32:48.711 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.28.20:5700/3) Recv NOMTXPOWER cmd
2026-01-29 01:32:48.711 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.28.20:5700/3) Recv SETFORMAT cmd
2026-01-29 01:32:48.711 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.28.20:5700/3) TRXD header version 1 -> 1
2026-01-29 01:32:48.714 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.28.20:5700) Recv RXTUNE cmd
2026-01-29 01:32:48.714 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETTSC
2026-01-29 01:32:48.714 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETTSC
2026-01-29 01:32:48.714 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETTSC
2026-01-29 01:32:48.714 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.28.20:5700) Recv TXTUNE cmd
2026-01-29 01:32:48.714 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETRXGAIN
2026-01-29 01:32:48.714 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETRXGAIN
2026-01-29 01:32:48.714 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETRXGAIN
2026-01-29 01:32:48.714 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETTSC
2026-01-29 01:32:48.715 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:32:48.715 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:32:48.715 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:32:48.715 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.28.20:5700) Recv NOMTXPOWER cmd
2026-01-29 01:32:48.715 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:32:48.715 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:32:48.715 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:32:48.715 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.28.20:5700) Recv POWERON CMD
2026-01-29 01:32:48.715 [INFO] ctrl_if_trx.py:109 (BTS@172.18.28.20:5700) Starting transceiver...
2026-01-29 01:32:48.715 [INFO] transceiver.py:243 Starting clock generator
2026-01-29 01:32:48.715 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-01-29 01:32:48.715 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:32:48.715 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:32:48.715 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:32:48.715 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETRXGAIN
2026-01-29 01:32:48.715 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:32:48.715 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:32:48.715 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:32:48.715 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 01:32:48.716 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:32:48.716 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:32:48.716 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:32:48.716 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 01:32:48.716 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:32:48.716 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:32:48.716 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:32:48.716 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 01:32:48.716 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:32:48.716 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:32:48.716 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:32:48.716 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 01:32:48.716 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:32:48.716 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 01:32:48.716 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:32:48.716 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:32:48.716 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 01:32:48.716 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 01:32:48.716 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 01:32:48.720 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-01-29 01:32:49.204 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-01-29 01:32:49.245 [DEBUG] fake_trx.py:278 (BTS@172.18.28.20:5700) Recv FAKE_TOA cmd
2026-01-29 01:32:49.245 [DEBUG] fake_trx.py:297 (BTS@172.18.28.20:5700) Recv FAKE_RSSI cmd
2026-01-29 01:32:49.248 [DEBUG] fake_trx.py:322 (BTS@172.18.28.20:5700) Recv FAKE_CI cmd
2026-01-29 01:32:49.249 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:49.271 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 01:32:49.271 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 01:32:49.272 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 01:32:49.277 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 01:32:49.277 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 01:32:49.278 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 01:32:49.278 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.28.22:6700) Recv POWERON CMD
2026-01-29 01:32:49.278 [INFO] ctrl_if_trx.py:109 (MS@172.18.28.22:6700) Starting transceiver...
2026-01-29 01:32:49.300 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:49.305 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 01:32:49.305 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 01:32:49.305 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 01:32:49.305 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 01:32:49.406 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:49.681 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-01-29 01:32:49.718 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 01:32:49.719 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 01:32:49.719 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 01:32:49.722 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 01:32:50.159 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-01-29 01:32:50.637 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-01-29 01:32:50.719 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 01:32:50.719 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 01:32:50.720 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 01:32:50.724 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 01:32:51.114 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-01-29 01:32:51.592 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-01-29 01:32:51.720 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 01:32:51.720 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 01:32:51.721 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 01:32:51.725 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 01:32:52.070 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-01-29 01:32:52.548 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-01-29 01:32:52.722 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 01:32:52.722 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 01:32:52.722 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 01:32:52.726 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 01:32:53.026 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-01-29 01:32:53.406 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:53.406 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 01:32:53.407 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 01:32:53.407 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 01:32:53.413 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 01:32:53.413 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 01:32:53.413 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 01:32:53.414 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 01:32:53.414 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 01:32:53.414 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 01:32:53.414 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.28.22:6700) Recv POWERON CMD
2026-01-29 01:32:53.414 [INFO] ctrl_if_trx.py:109 (MS@172.18.28.22:6700) Starting transceiver...
2026-01-29 01:32:53.447 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:53.452 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 01:32:53.452 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 01:32:53.453 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 01:32:53.453 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 01:32:53.503 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-01-29 01:32:53.723 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 01:32:53.723 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 01:32:53.723 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 01:32:53.723 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:53.727 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 01:32:53.981 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-01-29 01:32:54.459 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-01-29 01:32:54.945 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-01-29 01:32:55.422 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-01-29 01:32:55.900 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-01-29 01:32:56.378 [DEBUG] clck_gen.py:113 IND CLOCK 1632
2026-01-29 01:32:56.855 [DEBUG] clck_gen.py:113 IND CLOCK 1734
2026-01-29 01:32:57.333 [DEBUG] clck_gen.py:113 IND CLOCK 1836
2026-01-29 01:32:57.725 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:57.728 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 01:32:57.728 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 01:32:57.728 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 01:32:57.742 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 01:32:57.742 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 01:32:57.742 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 01:32:57.744 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 01:32:57.744 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 01:32:57.744 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 01:32:57.744 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.28.22:6700) Recv POWERON CMD
2026-01-29 01:32:57.744 [INFO] ctrl_if_trx.py:109 (MS@172.18.28.22:6700) Starting transceiver...
2026-01-29 01:32:57.751 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:57.753 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 01:32:57.753 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 01:32:57.753 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 01:32:57.753 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 01:32:57.811 [DEBUG] clck_gen.py:113 IND CLOCK 1938
2026-01-29 01:32:58.249 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:58.289 [DEBUG] clck_gen.py:113 IND CLOCK 2040
2026-01-29 01:32:58.767 [DEBUG] clck_gen.py:113 IND CLOCK 2142
2026-01-29 01:32:59.244 [DEBUG] clck_gen.py:113 IND CLOCK 2244
2026-01-29 01:32:59.722 [DEBUG] clck_gen.py:113 IND CLOCK 2346
2026-01-29 01:33:00.200 [DEBUG] clck_gen.py:113 IND CLOCK 2448
2026-01-29 01:33:00.678 [DEBUG] clck_gen.py:113 IND CLOCK 2550
2026-01-29 01:33:01.156 [DEBUG] clck_gen.py:113 IND CLOCK 2652
2026-01-29 01:33:01.634 [DEBUG] clck_gen.py:113 IND CLOCK 2754
2026-01-29 01:33:02.112 [DEBUG] clck_gen.py:113 IND CLOCK 2856
2026-01-29 01:33:02.250 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:33:02.252 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 01:33:02.253 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 01:33:02.253 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 01:33:02.267 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 01:33:02.267 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 01:33:02.267 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 01:33:02.269 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 01:33:02.269 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 01:33:02.269 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 01:33:02.269 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.28.22:6700) Recv POWERON CMD
2026-01-29 01:33:02.269 [INFO] ctrl_if_trx.py:109 (MS@172.18.28.22:6700) Starting transceiver...
2026-01-29 01:33:02.301 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:33:02.308 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 01:33:02.308 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 01:33:02.308 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 01:33:02.308 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 01:33:02.568 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:33:02.590 [DEBUG] clck_gen.py:113 IND CLOCK 2958
2026-01-29 01:33:03.068 [DEBUG] clck_gen.py:113 IND CLOCK 3060
2026-01-29 01:33:03.546 [DEBUG] clck_gen.py:113 IND CLOCK 3162
2026-01-29 01:33:04.024 [DEBUG] clck_gen.py:113 IND CLOCK 3264
2026-01-29 01:33:04.502 [DEBUG] clck_gen.py:113 IND CLOCK 3366
2026-01-29 01:33:04.980 [DEBUG] clck_gen.py:113 IND CLOCK 3468
2026-01-29 01:33:05.457 [DEBUG] clck_gen.py:113 IND CLOCK 3570
2026-01-29 01:33:05.935 [DEBUG] clck_gen.py:113 IND CLOCK 3672
2026-01-29 01:33:06.413 [DEBUG] clck_gen.py:113 IND CLOCK 3774
2026-01-29 01:33:06.570 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:33:06.574 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 01:33:06.575 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 01:33:06.575 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 01:33:06.594 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 01:33:06.595 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 01:33:06.595 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 01:33:06.596 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 01:33:06.597 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 01:33:06.597 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 01:33:06.597 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.28.22:6700) Recv POWERON CMD
2026-01-29 01:33:06.597 [INFO] ctrl_if_trx.py:109 (MS@172.18.28.22:6700) Starting transceiver...
2026-01-29 01:33:06.650 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:33:06.654 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 01:33:06.655 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 01:33:06.655 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 01:33:06.656 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 01:33:06.892 [DEBUG] clck_gen.py:113 IND CLOCK 3876
2026-01-29 01:33:07.232 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:33:07.370 [DEBUG] clck_gen.py:113 IND CLOCK 3978
2026-01-29 01:33:07.848 [DEBUG] clck_gen.py:113 IND CLOCK 4080
2026-01-29 01:33:08.326 [DEBUG] clck_gen.py:113 IND CLOCK 4182
2026-01-29 01:33:08.803 [DEBUG] clck_gen.py:113 IND CLOCK 4284
2026-01-29 01:33:09.281 [DEBUG] clck_gen.py:113 IND CLOCK 4386
2026-01-29 01:33:09.758 [DEBUG] clck_gen.py:113 IND CLOCK 4488
2026-01-29 01:33:10.236 [DEBUG] clck_gen.py:113 IND CLOCK 4590
2026-01-29 01:33:10.715 [DEBUG] clck_gen.py:113 IND CLOCK 4692
2026-01-29 01:33:11.193 [DEBUG] clck_gen.py:113 IND CLOCK 4794
2026-01-29 01:33:11.235 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:33:11.238 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 01:33:11.239 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 01:33:11.239 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 01:33:11.258 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 01:33:11.258 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 01:33:11.259 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 01:33:11.260 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 01:33:11.260 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 01:33:11.260 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 01:33:11.260 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.28.22:6700) Recv POWERON CMD
2026-01-29 01:33:11.260 [INFO] ctrl_if_trx.py:109 (MS@172.18.28.22:6700) Starting transceiver...
2026-01-29 01:33:11.287 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:33:11.292 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 01:33:11.293 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 01:33:11.293 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 01:33:11.293 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 01:33:11.671 [DEBUG] clck_gen.py:113 IND CLOCK 4896
2026-01-29 01:33:11.684 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:33:12.149 [DEBUG] clck_gen.py:113 IND CLOCK 4998
2026-01-29 01:33:12.627 [DEBUG] clck_gen.py:113 IND CLOCK 5100
2026-01-29 01:33:13.105 [DEBUG] clck_gen.py:113 IND CLOCK 5202
2026-01-29 01:33:13.583 [DEBUG] clck_gen.py:113 IND CLOCK 5304
2026-01-29 01:33:14.062 [DEBUG] clck_gen.py:113 IND CLOCK 5406
2026-01-29 01:33:14.540 [DEBUG] clck_gen.py:113 IND CLOCK 5508
2026-01-29 01:33:15.017 [DEBUG] clck_gen.py:113 IND CLOCK 5610
2026-01-29 01:33:15.495 [DEBUG] clck_gen.py:113 IND CLOCK 5712
2026-01-29 01:33:15.687 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:33:15.690 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 01:33:15.690 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 01:33:15.690 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 01:33:15.690 [WARNING] transceiver.py:257 (MS@172.18.28.22:6700) RX TRXD message (fn=5756 tn=1 pwr=0), but transceiver is not running => dropping...
2026-01-29 01:33:15.703 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 01:33:15.703 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 01:33:15.703 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 01:33:15.705 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 01:33:15.705 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 01:33:15.705 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 01:33:15.705 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.28.22:6700) Recv POWERON CMD
2026-01-29 01:33:15.705 [INFO] ctrl_if_trx.py:109 (MS@172.18.28.22:6700) Starting transceiver...
2026-01-29 01:33:15.731 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:33:15.734 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 01:33:15.735 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 01:33:15.735 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 01:33:15.735 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 01:33:15.973 [DEBUG] clck_gen.py:113 IND CLOCK 5814
2026-01-29 01:33:16.129 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:33:16.451 [DEBUG] clck_gen.py:113 IND CLOCK 5916
2026-01-29 01:33:16.929 [DEBUG] clck_gen.py:113 IND CLOCK 6018
2026-01-29 01:33:17.408 [DEBUG] clck_gen.py:113 IND CLOCK 6120
2026-01-29 01:33:17.885 [DEBUG] clck_gen.py:113 IND CLOCK 6222
2026-01-29 01:33:18.363 [DEBUG] clck_gen.py:113 IND CLOCK 6324
2026-01-29 01:33:18.841 [DEBUG] clck_gen.py:113 IND CLOCK 6426
2026-01-29 01:33:19.319 [DEBUG] clck_gen.py:113 IND CLOCK 6528
2026-01-29 01:33:19.797 [DEBUG] clck_gen.py:113 IND CLOCK 6630
2026-01-29 01:33:20.132 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:33:20.135 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 01:33:20.136 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 01:33:20.136 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 01:33:20.155 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 01:33:20.155 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 01:33:20.155 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 01:33:20.156 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 01:33:20.156 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 01:33:20.156 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 01:33:20.156 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.28.22:6700) Recv POWERON CMD
2026-01-29 01:33:20.156 [INFO] ctrl_if_trx.py:109 (MS@172.18.28.22:6700) Starting transceiver...
2026-01-29 01:33:20.168 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 01:33:20.169 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:33:20.170 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 01:33:20.170 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 01:33:20.170 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 01:33:20.171 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 01:33:20.274 [DEBUG] clck_gen.py:113 IND CLOCK 6732
2026-01-29 01:33:20.573 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:33:20.753 [DEBUG] clck_gen.py:113 IND CLOCK 6834
2026-01-29 01:33:21.231 [DEBUG] clck_gen.py:113 IND CLOCK 6936
2026-01-29 01:33:21.709 [DEBUG] clck_gen.py:113 IND CLOCK 7038
2026-01-29 01:33:22.186 [DEBUG] clck_gen.py:113 IND CLOCK 7140
2026-01-29 01:33:22.665 [DEBUG] clck_gen.py:113 IND CLOCK 7242
2026-01-29 01:33:23.143 [DEBUG] clck_gen.py:113 IND CLOCK 7344
2026-01-29 01:33:23.621 [DEBUG] clck_gen.py:113 IND CLOCK 7446
2026-01-29 01:33:24.099 [DEBUG] clck_gen.py:113 IND CLOCK 7548
2026-01-29 01:33:24.576 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:33:24.578 [DEBUG] clck_gen.py:113 IND CLOCK 7650
2026-01-29 01:33:24.579 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 01:33:24.579 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 01:33:24.580 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 01:33:24.599 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 01:33:24.599 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 01:33:24.599 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 01:33:24.600 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 01:33:24.600 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 01:33:24.600 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 01:33:24.600 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.28.22:6700) Recv POWERON CMD
2026-01-29 01:33:24.600 [INFO] ctrl_if_trx.py:109 (MS@172.18.28.22:6700) Starting transceiver...
2026-01-29 01:33:24.625 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:33:24.629 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 01:33:24.629 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 01:33:24.630 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 01:33:24.630 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 01:33:25.020 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:33:25.055 [DEBUG] clck_gen.py:113 IND CLOCK 7752
2026-01-29 01:33:25.534 [DEBUG] clck_gen.py:113 IND CLOCK 7854
2026-01-29 01:33:26.012 [DEBUG] clck_gen.py:113 IND CLOCK 7956
2026-01-29 01:33:26.491 [DEBUG] clck_gen.py:113 IND CLOCK 8058
2026-01-29 01:33:26.970 [DEBUG] clck_gen.py:113 IND CLOCK 8160
2026-01-29 01:33:27.448 [DEBUG] clck_gen.py:113 IND CLOCK 8262
2026-01-29 01:33:27.925 [DEBUG] clck_gen.py:113 IND CLOCK 8364
2026-01-29 01:33:28.403 [DEBUG] clck_gen.py:113 IND CLOCK 8466
2026-01-29 01:33:28.881 [DEBUG] clck_gen.py:113 IND CLOCK 8568
2026-01-29 01:33:29.022 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:33:29.025 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 01:33:29.025 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 01:33:29.025 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 01:33:29.043 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 01:33:29.043 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 01:33:29.043 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 01:33:29.044 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 01:33:29.044 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 01:33:29.044 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 01:33:29.044 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.28.22:6700) Recv POWERON CMD
2026-01-29 01:33:29.044 [INFO] ctrl_if_trx.py:109 (MS@172.18.28.22:6700) Starting transceiver...
2026-01-29 01:33:29.065 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 01:33:29.065 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:33:29.068 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 01:33:29.068 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 01:33:29.068 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 01:33:29.068 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 01:33:29.357 [DEBUG] clck_gen.py:113 IND CLOCK 8670
2026-01-29 01:33:29.831 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:33:29.835 [DEBUG] clck_gen.py:113 IND CLOCK 8772
2026-01-29 01:33:30.313 [DEBUG] clck_gen.py:113 IND CLOCK 8874
2026-01-29 01:33:30.791 [DEBUG] clck_gen.py:113 IND CLOCK 8976
2026-01-29 01:33:31.269 [DEBUG] clck_gen.py:113 IND CLOCK 9078
2026-01-29 01:33:31.747 [DEBUG] clck_gen.py:113 IND CLOCK 9180
2026-01-29 01:33:32.226 [DEBUG] clck_gen.py:113 IND CLOCK 9282
2026-01-29 01:33:32.703 [DEBUG] clck_gen.py:113 IND CLOCK 9384
2026-01-29 01:33:33.181 [DEBUG] clck_gen.py:113 IND CLOCK 9486
2026-01-29 01:33:33.659 [DEBUG] clck_gen.py:113 IND CLOCK 9588
2026-01-29 01:33:33.834 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:33:33.837 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 01:33:33.838 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 01:33:33.838 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 01:33:33.853 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 01:33:33.853 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 01:33:33.853 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 01:33:33.854 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 01:33:33.854 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 01:33:33.854 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 01:33:33.854 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.28.22:6700) Recv POWERON CMD
2026-01-29 01:33:33.854 [INFO] ctrl_if_trx.py:109 (MS@172.18.28.22:6700) Starting transceiver...
2026-01-29 01:33:33.896 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:33:33.897 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 01:33:33.897 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 01:33:33.898 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 01:33:33.898 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 01:33:34.137 [DEBUG] clck_gen.py:113 IND CLOCK 9690
2026-01-29 01:33:34.616 [DEBUG] clck_gen.py:113 IND CLOCK 9792
2026-01-29 01:33:34.712 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:33:35.094 [DEBUG] clck_gen.py:113 IND CLOCK 9894
2026-01-29 01:33:35.572 [DEBUG] clck_gen.py:113 IND CLOCK 9996
2026-01-29 01:33:36.051 [DEBUG] clck_gen.py:113 IND CLOCK 10098
2026-01-29 01:33:36.529 [DEBUG] clck_gen.py:113 IND CLOCK 10200
2026-01-29 01:33:37.007 [DEBUG] clck_gen.py:113 IND CLOCK 10302
2026-01-29 01:33:37.485 [DEBUG] clck_gen.py:113 IND CLOCK 10404
2026-01-29 01:33:37.963 [DEBUG] clck_gen.py:113 IND CLOCK 10506
2026-01-29 01:33:38.441 [DEBUG] clck_gen.py:113 IND CLOCK 10608
2026-01-29 01:33:38.714 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:33:38.718 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 01:33:38.718 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 01:33:38.718 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 01:33:38.737 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 01:33:38.737 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 01:33:38.737 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 01:33:38.739 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 01:33:38.739 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 01:33:38.739 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 01:33:38.739 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.28.22:6700) Recv POWERON CMD
2026-01-29 01:33:38.739 [INFO] ctrl_if_trx.py:109 (MS@172.18.28.22:6700) Starting transceiver...
2026-01-29 01:33:38.772 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:33:38.777 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 01:33:38.777 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 01:33:38.777 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 01:33:38.778 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 01:33:38.917 [DEBUG] clck_gen.py:113 IND CLOCK 10710
2026-01-29 01:33:39.157 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:33:39.395 [DEBUG] clck_gen.py:113 IND CLOCK 10812
2026-01-29 01:33:39.874 [DEBUG] clck_gen.py:113 IND CLOCK 10914
2026-01-29 01:33:40.352 [DEBUG] clck_gen.py:113 IND CLOCK 11016
2026-01-29 01:33:40.830 [DEBUG] clck_gen.py:113 IND CLOCK 11118
2026-01-29 01:33:41.308 [DEBUG] clck_gen.py:113 IND CLOCK 11220
2026-01-29 01:33:41.786 [DEBUG] clck_gen.py:113 IND CLOCK 11322
2026-01-29 01:33:42.264 [DEBUG] clck_gen.py:113 IND CLOCK 11424
2026-01-29 01:33:42.742 [DEBUG] clck_gen.py:113 IND CLOCK 11526
2026-01-29 01:33:43.159 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:33:43.162 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 01:33:43.162 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 01:33:43.162 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 01:33:43.179 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 01:33:43.179 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 01:33:43.179 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 01:33:43.181 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 01:33:43.181 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 01:33:43.181 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 01:33:43.181 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.28.22:6700) Recv POWERON CMD
2026-01-29 01:33:43.181 [INFO] ctrl_if_trx.py:109 (MS@172.18.28.22:6700) Starting transceiver...
2026-01-29 01:33:43.214 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:33:43.216 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 01:33:43.217 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 01:33:43.218 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 01:33:43.218 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 01:33:43.220 [DEBUG] clck_gen.py:113 IND CLOCK 11628
2026-01-29 01:33:43.377 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:33:43.699 [DEBUG] clck_gen.py:113 IND CLOCK 11730
2026-01-29 01:33:44.177 [DEBUG] clck_gen.py:113 IND CLOCK 11832
2026-01-29 01:33:44.654 [DEBUG] clck_gen.py:113 IND CLOCK 11934
2026-01-29 01:33:45.132 [DEBUG] clck_gen.py:113 IND CLOCK 12036
2026-01-29 01:33:45.610 [DEBUG] clck_gen.py:113 IND CLOCK 12138
2026-01-29 01:33:46.089 [DEBUG] clck_gen.py:113 IND CLOCK 12240
2026-01-29 01:33:46.566 [DEBUG] clck_gen.py:113 IND CLOCK 12342
2026-01-29 01:33:47.044 [DEBUG] clck_gen.py:113 IND CLOCK 12444
2026-01-29 01:33:47.378 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:33:47.381 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 01:33:47.382 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 01:33:47.382 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 01:33:47.400 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 01:33:47.400 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 01:33:47.401 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 01:33:47.402 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 01:33:47.402 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 01:33:47.402 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 01:33:47.402 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.28.22:6700) Recv POWERON CMD
2026-01-29 01:33:47.402 [INFO] ctrl_if_trx.py:109 (MS@172.18.28.22:6700) Starting transceiver...
2026-01-29 01:33:47.417 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:33:47.421 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 01:33:47.421 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 01:33:47.421 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 01:33:47.421 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 01:33:47.522 [DEBUG] clck_gen.py:113 IND CLOCK 12546
2026-01-29 01:33:47.697 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:33:48.001 [DEBUG] clck_gen.py:113 IND CLOCK 12648
2026-01-29 01:33:48.478 [DEBUG] clck_gen.py:113 IND CLOCK 12750
2026-01-29 01:33:48.956 [DEBUG] clck_gen.py:113 IND CLOCK 12852
2026-01-29 01:33:49.434 [DEBUG] clck_gen.py:113 IND CLOCK 12954
2026-01-29 01:33:49.912 [DEBUG] clck_gen.py:113 IND CLOCK 13056
2026-01-29 01:33:50.389 [DEBUG] clck_gen.py:113 IND CLOCK 13158
2026-01-29 01:33:50.867 [DEBUG] clck_gen.py:113 IND CLOCK 13260
2026-01-29 01:33:51.345 [DEBUG] clck_gen.py:113 IND CLOCK 13362
2026-01-29 01:33:51.698 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:33:51.701 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 01:33:51.702 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 01:33:51.702 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 01:33:51.720 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 01:33:51.720 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 01:33:51.720 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 01:33:51.721 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 01:33:51.721 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 01:33:51.721 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 01:33:51.721 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.28.22:6700) Recv POWERON CMD
2026-01-29 01:33:51.721 [INFO] ctrl_if_trx.py:109 (MS@172.18.28.22:6700) Starting transceiver...
2026-01-29 01:33:51.767 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:33:51.768 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 01:33:51.768 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 01:33:51.769 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 01:33:51.769 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 01:33:51.822 [DEBUG] clck_gen.py:113 IND CLOCK 13464
2026-01-29 01:33:52.016 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:33:52.300 [DEBUG] clck_gen.py:113 IND CLOCK 13566
2026-01-29 01:33:52.778 [DEBUG] clck_gen.py:113 IND CLOCK 13668
2026-01-29 01:33:53.255 [DEBUG] clck_gen.py:113 IND CLOCK 13770
2026-01-29 01:33:53.732 [DEBUG] clck_gen.py:113 IND CLOCK 13872
2026-01-29 01:33:54.210 [DEBUG] clck_gen.py:113 IND CLOCK 13974
2026-01-29 01:33:54.688 [DEBUG] clck_gen.py:113 IND CLOCK 14076
2026-01-29 01:33:55.165 [DEBUG] clck_gen.py:113 IND CLOCK 14178
2026-01-29 01:33:55.643 [DEBUG] clck_gen.py:113 IND CLOCK 14280
2026-01-29 01:33:56.017 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:33:56.020 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 01:33:56.020 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 01:33:56.020 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 01:33:56.030 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 01:33:56.030 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 01:33:56.030 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 01:33:56.032 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 01:33:56.032 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 01:33:56.032 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 01:33:56.032 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.28.22:6700) Recv POWERON CMD
2026-01-29 01:33:56.032 [INFO] ctrl_if_trx.py:109 (MS@172.18.28.22:6700) Starting transceiver...
2026-01-29 01:33:56.065 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:33:56.070 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 01:33:56.071 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 01:33:56.071 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 01:33:56.071 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 01:33:56.120 [DEBUG] clck_gen.py:113 IND CLOCK 14382
2026-01-29 01:33:56.332 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:33:56.598 [DEBUG] clck_gen.py:113 IND CLOCK 14484
2026-01-29 01:33:57.076 [DEBUG] clck_gen.py:113 IND CLOCK 14586
2026-01-29 01:33:57.554 [DEBUG] clck_gen.py:113 IND CLOCK 14688
2026-01-29 01:33:58.031 [DEBUG] clck_gen.py:113 IND CLOCK 14790
2026-01-29 01:33:58.509 [DEBUG] clck_gen.py:113 IND CLOCK 14892
2026-01-29 01:33:58.986 [DEBUG] clck_gen.py:113 IND CLOCK 14994
2026-01-29 01:33:59.464 [DEBUG] clck_gen.py:113 IND CLOCK 15096
2026-01-29 01:33:59.942 [DEBUG] clck_gen.py:113 IND CLOCK 15198
2026-01-29 01:34:00.333 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:34:00.336 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 01:34:00.336 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 01:34:00.336 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 01:34:00.356 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 01:34:00.356 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 01:34:00.356 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 01:34:00.357 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 01:34:00.357 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 01:34:00.357 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 01:34:00.357 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.28.22:6700) Recv POWERON CMD
2026-01-29 01:34:00.357 [INFO] ctrl_if_trx.py:109 (MS@172.18.28.22:6700) Starting transceiver...
2026-01-29 01:34:00.359 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:34:00.360 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 01:34:00.360 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 01:34:00.360 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 01:34:00.360 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 01:34:00.420 [DEBUG] clck_gen.py:113 IND CLOCK 15300
2026-01-29 01:34:00.812 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:34:00.898 [DEBUG] clck_gen.py:113 IND CLOCK 15402
2026-01-29 01:34:01.376 [DEBUG] clck_gen.py:113 IND CLOCK 15504
2026-01-29 01:34:01.853 [DEBUG] clck_gen.py:113 IND CLOCK 15606
2026-01-29 01:34:02.331 [DEBUG] clck_gen.py:113 IND CLOCK 15708
2026-01-29 01:34:02.809 [DEBUG] clck_gen.py:113 IND CLOCK 15810
2026-01-29 01:34:03.287 [DEBUG] clck_gen.py:113 IND CLOCK 15912
2026-01-29 01:34:03.766 [DEBUG] clck_gen.py:113 IND CLOCK 16014
2026-01-29 01:34:04.243 [DEBUG] clck_gen.py:113 IND CLOCK 16116
2026-01-29 01:34:04.721 [DEBUG] clck_gen.py:113 IND CLOCK 16218
2026-01-29 01:34:04.813 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:34:04.816 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 01:34:04.817 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 01:34:04.817 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 01:34:04.828 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 01:34:04.828 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 01:34:04.828 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 01:34:04.829 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 01:34:04.829 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 01:34:04.829 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 01:34:04.829 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.28.22:6700) Recv POWERON CMD
2026-01-29 01:34:04.829 [INFO] ctrl_if_trx.py:109 (MS@172.18.28.22:6700) Starting transceiver...
2026-01-29 01:34:04.862 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:34:04.867 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 01:34:04.867 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 01:34:04.868 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 01:34:04.868 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 01:34:05.131 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:34:05.199 [DEBUG] clck_gen.py:113 IND CLOCK 16320
2026-01-29 01:34:05.677 [DEBUG] clck_gen.py:113 IND CLOCK 16422
2026-01-29 01:34:06.155 [DEBUG] clck_gen.py:113 IND CLOCK 16524
2026-01-29 01:34:06.633 [DEBUG] clck_gen.py:113 IND CLOCK 16626
2026-01-29 01:34:07.111 [DEBUG] clck_gen.py:113 IND CLOCK 16728
2026-01-29 01:34:07.588 [DEBUG] clck_gen.py:113 IND CLOCK 16830
2026-01-29 01:34:08.067 [DEBUG] clck_gen.py:113 IND CLOCK 16932
2026-01-29 01:34:08.544 [DEBUG] clck_gen.py:113 IND CLOCK 17034
2026-01-29 01:34:09.021 [DEBUG] clck_gen.py:113 IND CLOCK 17136
2026-01-29 01:34:09.132 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:34:09.135 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 01:34:09.135 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 01:34:09.136 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 01:34:09.155 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 01:34:09.155 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 01:34:09.155 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 01:34:09.157 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 01:34:09.157 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 01:34:09.157 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 01:34:09.157 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.28.22:6700) Recv POWERON CMD
2026-01-29 01:34:09.157 [INFO] ctrl_if_trx.py:109 (MS@172.18.28.22:6700) Starting transceiver...
2026-01-29 01:34:09.207 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:34:09.212 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 01:34:09.212 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 01:34:09.212 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 01:34:09.212 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 01:34:09.449 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:34:09.498 [DEBUG] clck_gen.py:113 IND CLOCK 17238
2026-01-29 01:34:09.976 [DEBUG] clck_gen.py:113 IND CLOCK 17340
2026-01-29 01:34:10.454 [DEBUG] clck_gen.py:113 IND CLOCK 17442
2026-01-29 01:34:10.932 [DEBUG] clck_gen.py:113 IND CLOCK 17544
2026-01-29 01:34:11.410 [DEBUG] clck_gen.py:113 IND CLOCK 17646
2026-01-29 01:34:11.887 [DEBUG] clck_gen.py:113 IND CLOCK 17748
2026-01-29 01:34:12.365 [DEBUG] clck_gen.py:113 IND CLOCK 17850
2026-01-29 01:34:12.843 [DEBUG] clck_gen.py:113 IND CLOCK 17952
2026-01-29 01:34:13.321 [DEBUG] clck_gen.py:113 IND CLOCK 18054
2026-01-29 01:34:13.450 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:34:13.453 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 01:34:13.454 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 01:34:13.454 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 01:34:13.476 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 01:34:13.476 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 01:34:13.477 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 01:34:13.478 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 01:34:13.478 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 01:34:13.478 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 01:34:13.479 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.28.22:6700) Recv POWERON CMD
2026-01-29 01:34:13.479 [INFO] ctrl_if_trx.py:109 (MS@172.18.28.22:6700) Starting transceiver...
2026-01-29 01:34:13.510 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:34:13.515 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 01:34:13.515 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 01:34:13.515 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 01:34:13.516 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 01:34:13.768 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:34:13.799 [DEBUG] clck_gen.py:113 IND CLOCK 18156
2026-01-29 01:34:14.277 [DEBUG] clck_gen.py:113 IND CLOCK 18258
2026-01-29 01:34:14.754 [DEBUG] clck_gen.py:113 IND CLOCK 18360
2026-01-29 01:34:15.232 [DEBUG] clck_gen.py:113 IND CLOCK 18462
2026-01-29 01:34:15.710 [DEBUG] clck_gen.py:113 IND CLOCK 18564
2026-01-29 01:34:16.187 [DEBUG] clck_gen.py:113 IND CLOCK 18666
2026-01-29 01:34:16.665 [DEBUG] clck_gen.py:113 IND CLOCK 18768
2026-01-29 01:34:17.143 [DEBUG] clck_gen.py:113 IND CLOCK 18870
2026-01-29 01:34:17.621 [DEBUG] clck_gen.py:113 IND CLOCK 18972
2026-01-29 01:34:17.769 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:34:17.772 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 01:34:17.772 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 01:34:17.772 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 01:34:17.788 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 01:34:17.788 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 01:34:17.788 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 01:34:17.788 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 01:34:17.793 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 01:34:17.793 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 01:34:17.793 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 01:34:17.793 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 01:34:17.793 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.28.20:5700) Recv POWEROFF cmd
2026-01-29 01:34:17.793 [INFO] ctrl_if_trx.py:117 (BTS@172.18.28.20:5700) Stopping transceiver...
2026-01-29 01:34:17.794 [INFO] transceiver.py:246 Stopping clock generator
2026-01-29 01:34:17.794 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=19011 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 01:34:17.794 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=19011 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 01:34:17.794 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=19011 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 01:34:17.794 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=19011 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 01:34:17.794 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=19011 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 01:34:17.794 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=19011 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 01:34:17.794 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=19011 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 01:34:17.795 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=19011 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 01:34:22.790 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.28.20:5700) Recv POWEROFF cmd
2026-01-29 01:34:22.790 [INFO] ctrl_if_trx.py:117 (BTS@172.18.28.20:5700) Stopping transceiver...
2026-01-29 01:34:22.792 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 01:34:22.793 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 01:34:22.794 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 01:34:22.795 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 01:34:22.803 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 01:34:22.804 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.28.20:5700) Recv SETFORMAT cmd
2026-01-29 01:34:22.804 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.28.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 01:34:22.804 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.28.20:5700) Recv SETFORMAT cmd
2026-01-29 01:34:22.804 [INFO] ctrl_if_trx.py:201 (BTS@172.18.28.20:5700) TRXD header version 1 -> 1
2026-01-29 01:34:22.807 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.28.20:5700/1) Recv RXTUNE cmd
2026-01-29 01:34:22.808 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.28.20:5700/1) Recv TXTUNE cmd
2026-01-29 01:34:22.808 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.28.20:5700/1) Recv SETFORMAT cmd
2026-01-29 01:34:22.808 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.28.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 01:34:22.809 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 01:34:22.809 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.28.20:5700/1) Recv NOMTXPOWER cmd
2026-01-29 01:34:22.809 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.28.20:5700/1) Recv SETFORMAT cmd
2026-01-29 01:34:22.809 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.28.20:5700/1) TRXD header version 1 -> 1
2026-01-29 01:34:22.811 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.28.20:5700/2) Recv RXTUNE cmd
2026-01-29 01:34:22.811 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.28.20:5700/2) Recv TXTUNE cmd
2026-01-29 01:34:22.811 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.28.20:5700/2) Recv SETFORMAT cmd
2026-01-29 01:34:22.811 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.28.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 01:34:22.811 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 01:34:22.811 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.28.20:5700/2) Recv NOMTXPOWER cmd
2026-01-29 01:34:22.811 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.28.20:5700/2) Recv SETFORMAT cmd
2026-01-29 01:34:22.811 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.28.20:5700/2) TRXD header version 1 -> 1
2026-01-29 01:34:22.813 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.28.20:5700/3) Recv RXTUNE cmd
2026-01-29 01:34:22.813 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.28.20:5700/3) Recv TXTUNE cmd
2026-01-29 01:34:22.814 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.28.20:5700/3) Recv SETFORMAT cmd
2026-01-29 01:34:22.814 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.28.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 01:34:22.814 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 01:34:22.814 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.28.20:5700/3) Recv NOMTXPOWER cmd
2026-01-29 01:34:22.814 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.28.20:5700/3) Recv SETFORMAT cmd
2026-01-29 01:34:22.814 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.28.20:5700/3) TRXD header version 1 -> 1
2026-01-29 01:34:22.816 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.28.20:5700) Recv RXTUNE cmd
2026-01-29 01:34:22.816 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETTSC
2026-01-29 01:34:22.816 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETTSC
2026-01-29 01:34:22.816 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETTSC
2026-01-29 01:34:22.816 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.28.20:5700) Recv TXTUNE cmd
2026-01-29 01:34:22.816 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETRXGAIN
2026-01-29 01:34:22.816 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETRXGAIN
2026-01-29 01:34:22.817 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETRXGAIN
2026-01-29 01:34:22.817 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETTSC
2026-01-29 01:34:22.817 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:34:22.817 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:34:22.817 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:34:22.817 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.28.20:5700) Recv NOMTXPOWER cmd
2026-01-29 01:34:22.817 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:34:22.817 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:34:22.817 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:34:22.817 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.28.20:5700) Recv POWERON CMD
2026-01-29 01:34:22.817 [INFO] ctrl_if_trx.py:109 (BTS@172.18.28.20:5700) Starting transceiver...
2026-01-29 01:34:22.817 [INFO] transceiver.py:243 Starting clock generator
2026-01-29 01:34:22.817 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-01-29 01:34:22.817 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:34:22.817 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:34:22.817 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:34:22.817 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETRXGAIN
2026-01-29 01:34:22.817 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:34:22.817 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:34:22.817 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 01:34:22.817 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:34:22.818 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:34:22.818 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 01:34:22.818 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:34:22.818 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:34:22.818 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 01:34:22.818 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:34:22.818 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:34:22.818 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:34:22.818 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 01:34:22.818 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:34:22.818 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:34:22.818 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:34:22.818 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 01:34:22.818 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:34:22.818 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:34:22.818 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 01:34:22.818 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 01:34:22.818 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:34:22.818 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 01:34:22.818 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 01:34:22.819 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 01:34:22.819 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 01:34:22.819 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 01:34:22.819 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.28.20:5700) Recv POWEROFF cmd
2026-01-29 01:34:22.819 [INFO] ctrl_if_trx.py:117 (BTS@172.18.28.20:5700) Stopping transceiver...
2026-01-29 01:34:22.819 [INFO] transceiver.py:246 Stopping clock generator
2026-01-29 01:34:27.822 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.28.20:5700) Recv POWEROFF cmd
2026-01-29 01:34:27.822 [INFO] ctrl_if_trx.py:117 (BTS@172.18.28.20:5700) Stopping transceiver...
2026-01-29 01:34:27.825 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 01:34:27.825 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 01:34:27.825 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 01:34:27.825 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 01:34:27.827 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 01:34:27.828 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.28.20:5700) Recv SETFORMAT cmd
2026-01-29 01:34:27.828 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.28.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 01:34:27.828 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.28.20:5700) Recv SETFORMAT cmd
2026-01-29 01:34:27.828 [INFO] ctrl_if_trx.py:201 (BTS@172.18.28.20:5700) TRXD header version 1 -> 1
2026-01-29 01:34:27.829 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.28.20:5700/1) Recv RXTUNE cmd
2026-01-29 01:34:27.829 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.28.20:5700/1) Recv TXTUNE cmd
2026-01-29 01:34:27.829 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.28.20:5700/1) Recv SETFORMAT cmd
2026-01-29 01:34:27.829 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.28.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 01:34:27.829 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 01:34:27.829 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.28.20:5700/1) Recv NOMTXPOWER cmd
2026-01-29 01:34:27.829 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.28.20:5700/1) Recv SETFORMAT cmd
2026-01-29 01:34:27.829 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.28.20:5700/1) TRXD header version 1 -> 1
2026-01-29 01:34:27.830 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.28.20:5700/2) Recv RXTUNE cmd
2026-01-29 01:34:27.830 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.28.20:5700/2) Recv TXTUNE cmd
2026-01-29 01:34:27.830 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.28.20:5700/2) Recv SETFORMAT cmd
2026-01-29 01:34:27.830 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.28.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 01:34:27.830 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 01:34:27.830 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.28.20:5700/2) Recv NOMTXPOWER cmd
2026-01-29 01:34:27.830 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.28.20:5700/2) Recv SETFORMAT cmd
2026-01-29 01:34:27.830 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.28.20:5700/2) TRXD header version 1 -> 1
2026-01-29 01:34:27.831 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.28.20:5700/3) Recv RXTUNE cmd
2026-01-29 01:34:27.831 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.28.20:5700/3) Recv TXTUNE cmd
2026-01-29 01:34:27.831 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.28.20:5700/3) Recv SETFORMAT cmd
2026-01-29 01:34:27.831 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.28.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 01:34:27.831 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 01:34:27.831 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.28.20:5700/3) Recv NOMTXPOWER cmd
2026-01-29 01:34:27.831 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.28.20:5700/3) Recv SETFORMAT cmd
2026-01-29 01:34:27.831 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.28.20:5700/3) TRXD header version 1 -> 1
2026-01-29 01:34:27.832 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.28.20:5700) Recv RXTUNE cmd
2026-01-29 01:34:27.832 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETTSC
2026-01-29 01:34:27.832 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETTSC
2026-01-29 01:34:27.832 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETTSC
2026-01-29 01:34:27.832 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.28.20:5700) Recv TXTUNE cmd
2026-01-29 01:34:27.832 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETRXGAIN
2026-01-29 01:34:27.832 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETRXGAIN
2026-01-29 01:34:27.833 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETRXGAIN
2026-01-29 01:34:27.833 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETTSC
2026-01-29 01:34:27.833 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:34:27.833 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:34:27.833 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:34:27.833 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.28.20:5700) Recv NOMTXPOWER cmd
2026-01-29 01:34:27.833 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:34:27.833 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:34:27.833 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:34:27.833 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.28.20:5700) Recv POWERON CMD
2026-01-29 01:34:27.833 [INFO] ctrl_if_trx.py:109 (BTS@172.18.28.20:5700) Starting transceiver...
2026-01-29 01:34:27.833 [INFO] transceiver.py:243 Starting clock generator
2026-01-29 01:34:27.833 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-01-29 01:34:27.833 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:34:27.833 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:34:27.833 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:34:27.833 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETRXGAIN
2026-01-29 01:34:27.833 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:34:27.833 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:34:27.833 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 01:34:27.833 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:34:27.833 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:34:27.833 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:34:27.833 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 01:34:27.833 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:34:27.833 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:34:27.833 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:34:27.833 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 01:34:27.833 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:34:27.833 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:34:27.833 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:34:27.833 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 01:34:27.833 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:34:27.833 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:34:27.833 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:34:27.833 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 01:34:27.833 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:34:27.833 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 01:34:27.833 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 01:34:27.834 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 01:34:27.838 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-01-29 01:34:28.321 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-01-29 01:34:28.358 [DEBUG] fake_trx.py:278 (BTS@172.18.28.20:5700) Recv FAKE_TOA cmd
2026-01-29 01:34:28.360 [DEBUG] fake_trx.py:297 (BTS@172.18.28.20:5700) Recv FAKE_RSSI cmd
2026-01-29 01:34:28.362 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:34:28.362 [DEBUG] fake_trx.py:322 (BTS@172.18.28.20:5700) Recv FAKE_CI cmd
2026-01-29 01:34:28.388 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 01:34:28.388 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 01:34:28.389 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 01:34:28.395 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 01:34:28.395 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 01:34:28.395 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 01:34:28.396 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.28.22:6700) Recv POWERON CMD
2026-01-29 01:34:28.396 [INFO] ctrl_if_trx.py:109 (MS@172.18.28.22:6700) Starting transceiver...
2026-01-29 01:34:28.416 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:34:28.422 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 01:34:28.422 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 01:34:28.423 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 01:34:28.423 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 01:34:28.523 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:34:28.525 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 01:34:28.526 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 01:34:28.526 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 01:34:28.534 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 01:34:28.534 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 01:34:28.534 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 01:34:28.536 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 01:34:28.536 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 01:34:28.536 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 01:34:28.536 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.28.22:6700) Recv POWERON CMD
2026-01-29 01:34:28.536 [INFO] ctrl_if_trx.py:109 (MS@172.18.28.22:6700) Starting transceiver...
2026-01-29 01:34:28.578 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:34:28.584 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 01:34:28.584 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 01:34:28.584 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 01:34:28.584 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 01:34:28.798 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-01-29 01:34:28.835 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 01:34:28.836 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 01:34:28.836 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 01:34:28.837 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 01:34:29.019 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:34:29.022 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 01:34:29.022 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 01:34:29.023 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 01:34:29.044 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 01:34:29.044 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 01:34:29.044 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 01:34:29.045 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 01:34:29.046 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 01:34:29.046 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 01:34:29.046 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.28.22:6700) Recv POWERON CMD
2026-01-29 01:34:29.046 [INFO] ctrl_if_trx.py:109 (MS@172.18.28.22:6700) Starting transceiver...
2026-01-29 01:34:29.086 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:34:29.091 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 01:34:29.092 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 01:34:29.092 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 01:34:29.092 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 01:34:29.235 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:34:29.239 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 01:34:29.239 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 01:34:29.239 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 01:34:29.248 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 01:34:29.248 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 01:34:29.248 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 01:34:29.250 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 01:34:29.250 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 01:34:29.250 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 01:34:29.250 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.28.22:6700) Recv POWERON CMD
2026-01-29 01:34:29.250 [INFO] ctrl_if_trx.py:109 (MS@172.18.28.22:6700) Starting transceiver...
2026-01-29 01:34:29.275 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-01-29 01:34:29.295 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:34:29.301 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 01:34:29.302 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 01:34:29.302 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 01:34:29.302 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 01:34:29.731 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:34:29.733 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 01:34:29.734 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 01:34:29.734 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 01:34:29.743 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 01:34:29.743 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 01:34:29.743 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 01:34:29.744 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 01:34:29.744 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 01:34:29.745 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 01:34:29.745 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.28.22:6700) Recv POWERON CMD
2026-01-29 01:34:29.745 [INFO] ctrl_if_trx.py:109 (MS@172.18.28.22:6700) Starting transceiver...
2026-01-29 01:34:29.753 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-01-29 01:34:29.799 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:34:29.804 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 01:34:29.805 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 01:34:29.805 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 01:34:29.805 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 01:34:29.836 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 01:34:29.836 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 01:34:29.836 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 01:34:29.837 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 01:34:30.230 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-01-29 01:34:30.265 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:34:30.268 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 01:34:30.268 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 01:34:30.268 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 01:34:30.285 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 01:34:30.285 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 01:34:30.285 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 01:34:30.287 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 01:34:30.287 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 01:34:30.287 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 01:34:30.287 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.28.22:6700) Recv POWERON CMD
2026-01-29 01:34:30.287 [INFO] ctrl_if_trx.py:109 (MS@172.18.28.22:6700) Starting transceiver...
2026-01-29 01:34:30.334 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:34:30.339 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 01:34:30.339 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 01:34:30.339 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 01:34:30.339 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 01:34:30.707 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-01-29 01:34:30.812 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:34:30.814 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 01:34:30.814 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 01:34:30.815 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 01:34:30.831 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 01:34:30.831 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 01:34:30.831 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 01:34:30.833 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 01:34:30.833 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 01:34:30.833 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 01:34:30.833 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.28.22:6700) Recv POWERON CMD
2026-01-29 01:34:30.833 [INFO] ctrl_if_trx.py:109 (MS@172.18.28.22:6700) Starting transceiver...
2026-01-29 01:34:30.836 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 01:34:30.836 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 01:34:30.838 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 01:34:30.838 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 01:34:30.842 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:34:30.843 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 01:34:30.843 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 01:34:30.843 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 01:34:30.844 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 01:34:31.184 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-01-29 01:34:31.359 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:34:31.361 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 01:34:31.361 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 01:34:31.361 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 01:34:31.375 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 01:34:31.375 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 01:34:31.375 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 01:34:31.378 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 01:34:31.378 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 01:34:31.378 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 01:34:31.378 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.28.22:6700) Recv POWERON CMD
2026-01-29 01:34:31.378 [INFO] ctrl_if_trx.py:109 (MS@172.18.28.22:6700) Starting transceiver...
2026-01-29 01:34:31.421 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 01:34:31.421 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:34:31.426 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 01:34:31.426 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 01:34:31.427 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 01:34:31.427 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 01:34:31.662 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-01-29 01:34:31.838 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 01:34:31.838 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 01:34:31.838 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 01:34:31.839 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 01:34:31.906 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:34:31.908 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 01:34:31.908 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 01:34:31.908 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 01:34:31.926 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 01:34:31.926 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 01:34:31.926 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 01:34:31.928 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 01:34:31.929 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 01:34:31.929 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 01:34:31.929 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.28.22:6700) Recv POWERON CMD
2026-01-29 01:34:31.929 [INFO] ctrl_if_trx.py:109 (MS@172.18.28.22:6700) Starting transceiver...
2026-01-29 01:34:31.970 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:34:31.975 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 01:34:31.975 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 01:34:31.976 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 01:34:31.976 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 01:34:32.140 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-01-29 01:34:32.453 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:34:32.457 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 01:34:32.458 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 01:34:32.458 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 01:34:32.474 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 01:34:32.474 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 01:34:32.474 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 01:34:32.476 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 01:34:32.476 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 01:34:32.476 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 01:34:32.476 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.28.22:6700) Recv POWERON CMD
2026-01-29 01:34:32.476 [INFO] ctrl_if_trx.py:109 (MS@172.18.28.22:6700) Starting transceiver...
2026-01-29 01:34:32.518 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 01:34:32.519 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:34:32.524 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 01:34:32.524 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 01:34:32.525 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 01:34:32.525 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 01:34:32.618 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-01-29 01:34:32.839 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 01:34:32.839 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 01:34:32.839 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 01:34:32.839 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 01:34:33.096 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-01-29 01:34:33.368 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:34:33.371 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 01:34:33.371 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 01:34:33.371 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 01:34:33.388 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 01:34:33.388 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 01:34:33.388 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 01:34:33.390 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 01:34:33.390 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 01:34:33.390 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 01:34:33.390 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.28.22:6700) Recv POWERON CMD
2026-01-29 01:34:33.390 [INFO] ctrl_if_trx.py:109 (MS@172.18.28.22:6700) Starting transceiver...
2026-01-29 01:34:33.434 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:34:33.440 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 01:34:33.441 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 01:34:33.441 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 01:34:33.441 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 01:34:33.574 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-01-29 01:34:33.855 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:34:33.858 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 01:34:33.858 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 01:34:33.859 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 01:34:33.875 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 01:34:33.875 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 01:34:33.875 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 01:34:33.877 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 01:34:33.877 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 01:34:33.877 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 01:34:33.877 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.28.22:6700) Recv POWERON CMD
2026-01-29 01:34:33.877 [INFO] ctrl_if_trx.py:109 (MS@172.18.28.22:6700) Starting transceiver...
2026-01-29 01:34:33.918 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:34:33.932 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 01:34:33.932 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 01:34:33.933 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 01:34:33.933 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 01:34:34.051 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-01-29 01:34:34.402 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:34:34.404 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 01:34:34.405 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 01:34:34.405 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 01:34:34.422 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 01:34:34.422 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 01:34:34.422 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 01:34:34.424 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 01:34:34.424 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 01:34:34.424 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 01:34:34.424 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.28.22:6700) Recv POWERON CMD
2026-01-29 01:34:34.424 [INFO] ctrl_if_trx.py:109 (MS@172.18.28.22:6700) Starting transceiver...
2026-01-29 01:34:34.472 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:34:34.477 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 01:34:34.477 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 01:34:34.478 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 01:34:34.478 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 01:34:34.529 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-01-29 01:34:34.685 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:34:34.688 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 01:34:34.689 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 01:34:34.689 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 01:34:34.698 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 01:34:34.698 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 01:34:34.699 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 01:34:34.700 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 01:34:34.700 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 01:34:34.700 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 01:34:34.700 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.28.22:6700) Recv POWERON CMD
2026-01-29 01:34:34.700 [INFO] ctrl_if_trx.py:109 (MS@172.18.28.22:6700) Starting transceiver...
2026-01-29 01:34:34.742 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:34:34.747 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 01:34:34.747 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 01:34:34.748 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 01:34:34.748 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 01:34:35.007 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-01-29 01:34:35.182 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:34:35.184 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 01:34:35.185 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 01:34:35.185 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 01:34:35.194 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 01:34:35.194 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 01:34:35.194 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 01:34:35.196 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 01:34:35.196 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 01:34:35.196 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 01:34:35.196 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.28.22:6700) Recv POWERON CMD
2026-01-29 01:34:35.196 [INFO] ctrl_if_trx.py:109 (MS@172.18.28.22:6700) Starting transceiver...
2026-01-29 01:34:35.242 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:34:35.247 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 01:34:35.247 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 01:34:35.248 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 01:34:35.248 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 01:34:35.484 [DEBUG] clck_gen.py:113 IND CLOCK 1632
2026-01-29 01:34:35.677 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:34:35.680 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 01:34:35.681 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 01:34:35.681 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 01:34:35.697 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 01:34:35.698 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 01:34:35.698 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 01:34:35.699 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 01:34:35.699 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 01:34:35.699 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 01:34:35.699 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.28.22:6700) Recv POWERON CMD
2026-01-29 01:34:35.699 [INFO] ctrl_if_trx.py:109 (MS@172.18.28.22:6700) Starting transceiver...
2026-01-29 01:34:35.746 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:34:35.751 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 01:34:35.751 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 01:34:35.752 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 01:34:35.752 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 01:34:35.960 [DEBUG] clck_gen.py:113 IND CLOCK 1734
2026-01-29 01:34:36.172 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:34:36.174 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 01:34:36.175 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 01:34:36.175 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 01:34:36.193 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 01:34:36.193 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 01:34:36.193 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 01:34:36.195 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 01:34:36.195 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 01:34:36.195 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 01:34:36.195 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.28.22:6700) Recv POWERON CMD
2026-01-29 01:34:36.195 [INFO] ctrl_if_trx.py:109 (MS@172.18.28.22:6700) Starting transceiver...
2026-01-29 01:34:36.243 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:34:36.248 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 01:34:36.248 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 01:34:36.248 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 01:34:36.249 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 01:34:36.352 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:34:36.355 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 01:34:36.356 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 01:34:36.356 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 01:34:36.366 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 01:34:36.366 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 01:34:36.366 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 01:34:36.367 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 01:34:36.368 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 01:34:36.368 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 01:34:36.368 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.28.22:6700) Recv POWERON CMD
2026-01-29 01:34:36.368 [INFO] ctrl_if_trx.py:109 (MS@172.18.28.22:6700) Starting transceiver...
2026-01-29 01:34:36.410 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:34:36.415 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 01:34:36.415 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 01:34:36.416 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 01:34:36.416 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 01:34:36.437 [DEBUG] clck_gen.py:113 IND CLOCK 1836
2026-01-29 01:34:36.848 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:34:36.850 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 01:34:36.851 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 01:34:36.851 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 01:34:36.857 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 01:34:36.857 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 01:34:36.857 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 01:34:36.859 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 01:34:36.859 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 01:34:36.859 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 01:34:36.859 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.28.22:6700) Recv POWERON CMD
2026-01-29 01:34:36.859 [INFO] ctrl_if_trx.py:109 (MS@172.18.28.22:6700) Starting transceiver...
2026-01-29 01:34:36.909 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:34:36.914 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 01:34:36.914 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 01:34:36.914 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 01:34:36.915 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 01:34:36.915 [DEBUG] clck_gen.py:113 IND CLOCK 1938
2026-01-29 01:34:37.344 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:34:37.347 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 01:34:37.347 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 01:34:37.348 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 01:34:37.366 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 01:34:37.366 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 01:34:37.366 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 01:34:37.368 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 01:34:37.368 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 01:34:37.368 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 01:34:37.368 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.28.22:6700) Recv POWERON CMD
2026-01-29 01:34:37.368 [INFO] ctrl_if_trx.py:109 (MS@172.18.28.22:6700) Starting transceiver...
2026-01-29 01:34:37.393 [DEBUG] clck_gen.py:113 IND CLOCK 2040
2026-01-29 01:34:37.414 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:34:37.419 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 01:34:37.419 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 01:34:37.420 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 01:34:37.420 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 01:34:37.840 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:34:37.843 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 01:34:37.844 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 01:34:37.844 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 01:34:37.849 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 01:34:37.849 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 01:34:37.849 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 01:34:37.849 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 01:34:37.850 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 01:34:37.850 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 01:34:37.850 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 01:34:37.850 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 01:34:37.850 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.28.20:5700) Recv POWEROFF cmd
2026-01-29 01:34:37.850 [INFO] ctrl_if_trx.py:117 (BTS@172.18.28.20:5700) Stopping transceiver...
2026-01-29 01:34:37.850 [INFO] transceiver.py:246 Stopping clock generator
2026-01-29 01:34:37.851 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=2141 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 01:34:37.851 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=2141 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 01:34:37.851 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=2141 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 01:34:37.851 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=2141 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 01:34:37.851 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=2141 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 01:34:37.851 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=2141 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 01:34:37.851 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=2141 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 01:34:37.851 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=2141 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 01:34:42.853 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.28.20:5700) Recv POWEROFF cmd
2026-01-29 01:34:42.853 [INFO] ctrl_if_trx.py:117 (BTS@172.18.28.20:5700) Stopping transceiver...
2026-01-29 01:34:42.855 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 01:34:42.856 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 01:34:42.857 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 01:34:42.857 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 01:34:42.866 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 01:34:42.867 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.28.20:5700) Recv SETFORMAT cmd
2026-01-29 01:34:42.867 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.28.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 01:34:42.868 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.28.20:5700) Recv SETFORMAT cmd
2026-01-29 01:34:42.868 [INFO] ctrl_if_trx.py:201 (BTS@172.18.28.20:5700) TRXD header version 1 -> 1
2026-01-29 01:34:42.871 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.28.20:5700/1) Recv RXTUNE cmd
2026-01-29 01:34:42.871 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.28.20:5700/1) Recv TXTUNE cmd
2026-01-29 01:34:42.872 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.28.20:5700/1) Recv SETFORMAT cmd
2026-01-29 01:34:42.872 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.28.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 01:34:42.872 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 01:34:42.873 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.28.20:5700/1) Recv NOMTXPOWER cmd
2026-01-29 01:34:42.873 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.28.20:5700/1) Recv SETFORMAT cmd
2026-01-29 01:34:42.873 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.28.20:5700/1) TRXD header version 1 -> 1
2026-01-29 01:34:42.874 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.28.20:5700/2) Recv RXTUNE cmd
2026-01-29 01:34:42.874 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.28.20:5700/2) Recv TXTUNE cmd
2026-01-29 01:34:42.874 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.28.20:5700/2) Recv SETFORMAT cmd
2026-01-29 01:34:42.874 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.28.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 01:34:42.874 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 01:34:42.874 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.28.20:5700/2) Recv NOMTXPOWER cmd
2026-01-29 01:34:42.875 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.28.20:5700/2) Recv SETFORMAT cmd
2026-01-29 01:34:42.875 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.28.20:5700/2) TRXD header version 1 -> 1
2026-01-29 01:34:42.876 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.28.20:5700/3) Recv RXTUNE cmd
2026-01-29 01:34:42.877 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.28.20:5700/3) Recv TXTUNE cmd
2026-01-29 01:34:42.877 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.28.20:5700/3) Recv SETFORMAT cmd
2026-01-29 01:34:42.877 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.28.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 01:34:42.877 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 01:34:42.877 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.28.20:5700/3) Recv NOMTXPOWER cmd
2026-01-29 01:34:42.877 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.28.20:5700/3) Recv SETFORMAT cmd
2026-01-29 01:34:42.877 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.28.20:5700/3) TRXD header version 1 -> 1
2026-01-29 01:34:42.879 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.28.20:5700) Recv RXTUNE cmd
2026-01-29 01:34:42.879 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETTSC
2026-01-29 01:34:42.879 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETTSC
2026-01-29 01:34:42.880 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETTSC
2026-01-29 01:34:42.880 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.28.20:5700) Recv TXTUNE cmd
2026-01-29 01:34:42.880 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETRXGAIN
2026-01-29 01:34:42.880 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETRXGAIN
2026-01-29 01:34:42.880 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETRXGAIN
2026-01-29 01:34:42.880 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETTSC
2026-01-29 01:34:42.880 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:34:42.880 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:34:42.880 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.28.20:5700) Recv NOMTXPOWER cmd
2026-01-29 01:34:42.880 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:34:42.880 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:34:42.880 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:34:42.880 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.28.20:5700) Recv POWERON CMD
2026-01-29 01:34:42.880 [INFO] ctrl_if_trx.py:109 (BTS@172.18.28.20:5700) Starting transceiver...
2026-01-29 01:34:42.880 [INFO] transceiver.py:243 Starting clock generator
2026-01-29 01:34:42.880 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-01-29 01:34:42.880 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:34:42.880 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:34:42.880 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:34:42.881 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETRXGAIN
2026-01-29 01:34:42.881 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:34:42.881 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:34:42.881 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 01:34:42.881 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:34:42.881 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:34:42.881 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:34:42.881 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 01:34:42.881 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:34:42.881 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:34:42.881 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:34:42.881 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 01:34:42.881 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:34:42.881 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:34:42.881 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:34:42.881 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 01:34:42.881 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:34:42.881 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:34:42.881 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:34:42.881 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 01:34:42.881 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:34:42.881 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 01:34:42.881 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:34:42.881 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 01:34:42.881 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 01:34:42.885 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-01-29 01:34:43.368 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-01-29 01:34:43.412 [DEBUG] fake_trx.py:278 (BTS@172.18.28.20:5700) Recv FAKE_TOA cmd
2026-01-29 01:34:43.414 [DEBUG] fake_trx.py:297 (BTS@172.18.28.20:5700) Recv FAKE_RSSI cmd
2026-01-29 01:34:43.415 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:34:43.416 [DEBUG] fake_trx.py:322 (BTS@172.18.28.20:5700) Recv FAKE_CI cmd
2026-01-29 01:34:43.429 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 01:34:43.429 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 01:34:43.429 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 01:34:43.434 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 01:34:43.434 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 01:34:43.435 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 01:34:43.435 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.28.22:6700) Recv POWERON CMD
2026-01-29 01:34:43.435 [INFO] ctrl_if_trx.py:109 (MS@172.18.28.22:6700) Starting transceiver...
2026-01-29 01:34:43.463 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:34:43.469 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 01:34:43.470 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 01:34:43.470 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 01:34:43.470 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 01:34:43.846 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-01-29 01:34:43.883 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 01:34:43.884 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 01:34:43.884 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 01:34:43.887 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 01:34:44.048 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:34:44.053 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:34:44.324 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-01-29 01:34:44.526 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:34:44.529 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 01:34:44.529 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 01:34:44.530 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 01:34:44.539 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 01:34:44.539 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 01:34:44.539 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 01:34:44.540 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 01:34:44.540 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 01:34:44.540 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 01:34:44.540 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.28.22:6700) Recv POWERON CMD
2026-01-29 01:34:44.540 [INFO] ctrl_if_trx.py:109 (MS@172.18.28.22:6700) Starting transceiver...
2026-01-29 01:34:44.582 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:34:44.587 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 01:34:44.587 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 01:34:44.588 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 01:34:44.588 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 01:34:44.802 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-01-29 01:34:44.884 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 01:34:44.885 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 01:34:44.885 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 01:34:44.888 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 01:34:45.280 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-01-29 01:34:45.500 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:34:45.504 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:34:45.758 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-01-29 01:34:45.886 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 01:34:45.886 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 01:34:45.886 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 01:34:45.888 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 01:34:45.978 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:34:45.980 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 01:34:45.981 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 01:34:45.981 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 01:34:45.991 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 01:34:45.991 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 01:34:45.991 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 01:34:45.992 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 01:34:45.992 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 01:34:45.992 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 01:34:45.992 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.28.22:6700) Recv POWERON CMD
2026-01-29 01:34:45.992 [INFO] ctrl_if_trx.py:109 (MS@172.18.28.22:6700) Starting transceiver...
2026-01-29 01:34:46.040 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:34:46.045 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 01:34:46.045 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 01:34:46.046 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 01:34:46.046 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 01:34:46.235 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-01-29 01:34:46.673 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:34:46.678 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:34:46.713 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-01-29 01:34:46.886 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 01:34:46.887 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 01:34:46.887 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 01:34:46.889 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 01:34:47.151 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:34:47.154 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 01:34:47.155 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 01:34:47.155 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 01:34:47.166 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 01:34:47.166 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 01:34:47.166 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 01:34:47.168 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 01:34:47.168 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 01:34:47.168 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 01:34:47.168 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.28.22:6700) Recv POWERON CMD
2026-01-29 01:34:47.168 [INFO] ctrl_if_trx.py:109 (MS@172.18.28.22:6700) Starting transceiver...
2026-01-29 01:34:47.190 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-01-29 01:34:47.210 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:34:47.216 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 01:34:47.216 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 01:34:47.217 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 01:34:47.218 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 01:34:47.668 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-01-29 01:34:47.888 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 01:34:47.888 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 01:34:47.888 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 01:34:47.890 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 01:34:48.124 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:34:48.129 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:34:48.146 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-01-29 01:34:48.602 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:34:48.605 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 01:34:48.605 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 01:34:48.605 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 01:34:48.623 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 01:34:48.623 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 01:34:48.623 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 01:34:48.624 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-01-29 01:34:48.625 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 01:34:48.625 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 01:34:48.625 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 01:34:48.625 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.28.22:6700) Recv POWERON CMD
2026-01-29 01:34:48.625 [INFO] ctrl_if_trx.py:109 (MS@172.18.28.22:6700) Starting transceiver...
2026-01-29 01:34:48.671 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:34:48.676 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 01:34:48.676 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 01:34:48.676 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 01:34:48.677 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 01:34:49.101 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-01-29 01:34:49.579 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-01-29 01:34:49.698 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:34:49.702 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:34:50.057 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-01-29 01:34:50.185 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:34:50.187 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 01:34:50.188 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 01:34:50.188 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 01:34:50.204 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 01:34:50.204 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 01:34:50.204 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 01:34:50.206 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 01:34:50.206 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 01:34:50.206 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 01:34:50.206 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.28.22:6700) Recv POWERON CMD
2026-01-29 01:34:50.206 [INFO] ctrl_if_trx.py:109 (MS@172.18.28.22:6700) Starting transceiver...
2026-01-29 01:34:50.254 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:34:50.259 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 01:34:50.259 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 01:34:50.259 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 01:34:50.259 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 01:34:50.535 [DEBUG] clck_gen.py:113 IND CLOCK 1632
2026-01-29 01:34:51.013 [DEBUG] clck_gen.py:113 IND CLOCK 1734
2026-01-29 01:34:51.219 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:34:51.224 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:34:51.491 [DEBUG] clck_gen.py:113 IND CLOCK 1836
2026-01-29 01:34:51.707 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:34:51.709 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 01:34:51.710 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 01:34:51.710 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 01:34:51.710 [WARNING] transceiver.py:257 (MS@172.18.28.22:6700) RX TRXD message (fn=1885 tn=6 pwr=0), but transceiver is not running => dropping...
2026-01-29 01:34:51.725 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 01:34:51.725 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 01:34:51.725 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 01:34:51.727 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 01:34:51.727 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 01:34:51.727 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 01:34:51.727 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.28.22:6700) Recv POWERON CMD
2026-01-29 01:34:51.727 [INFO] ctrl_if_trx.py:109 (MS@172.18.28.22:6700) Starting transceiver...
2026-01-29 01:34:51.773 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:34:51.779 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 01:34:51.779 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 01:34:51.779 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 01:34:51.779 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 01:34:51.969 [DEBUG] clck_gen.py:113 IND CLOCK 1938
2026-01-29 01:34:52.447 [DEBUG] clck_gen.py:113 IND CLOCK 2040
2026-01-29 01:34:52.741 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:34:52.745 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:34:52.925 [DEBUG] clck_gen.py:113 IND CLOCK 2142
2026-01-29 01:34:53.228 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:34:53.231 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 01:34:53.232 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 01:34:53.232 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 01:34:53.248 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 01:34:53.248 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 01:34:53.248 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 01:34:53.250 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 01:34:53.250 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 01:34:53.250 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 01:34:53.250 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.28.22:6700) Recv POWERON CMD
2026-01-29 01:34:53.250 [INFO] ctrl_if_trx.py:109 (MS@172.18.28.22:6700) Starting transceiver...
2026-01-29 01:34:53.299 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 01:34:53.300 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:34:53.305 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 01:34:53.305 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 01:34:53.306 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 01:34:53.306 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 01:34:53.402 [DEBUG] clck_gen.py:113 IND CLOCK 2244
2026-01-29 01:34:53.880 [DEBUG] clck_gen.py:113 IND CLOCK 2346
2026-01-29 01:34:54.263 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:34:54.267 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:34:54.357 [DEBUG] clck_gen.py:113 IND CLOCK 2448
2026-01-29 01:34:54.749 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:34:54.751 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 01:34:54.751 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 01:34:54.752 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 01:34:54.769 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 01:34:54.769 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 01:34:54.769 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 01:34:54.772 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 01:34:54.772 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 01:34:54.772 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 01:34:54.772 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.28.22:6700) Recv POWERON CMD
2026-01-29 01:34:54.772 [INFO] ctrl_if_trx.py:109 (MS@172.18.28.22:6700) Starting transceiver...
2026-01-29 01:34:54.814 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:34:54.819 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 01:34:54.820 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 01:34:54.820 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 01:34:54.820 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 01:34:54.834 [DEBUG] clck_gen.py:113 IND CLOCK 2550
2026-01-29 01:34:55.312 [DEBUG] clck_gen.py:113 IND CLOCK 2652
2026-01-29 01:34:55.782 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:34:55.786 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:34:55.790 [DEBUG] clck_gen.py:113 IND CLOCK 2754
2026-01-29 01:34:56.269 [DEBUG] clck_gen.py:113 IND CLOCK 2856
2026-01-29 01:34:56.269 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:34:56.272 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 01:34:56.273 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 01:34:56.273 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 01:34:56.291 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 01:34:56.291 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 01:34:56.291 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 01:34:56.293 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 01:34:56.293 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 01:34:56.293 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 01:34:56.293 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.28.22:6700) Recv POWERON CMD
2026-01-29 01:34:56.293 [INFO] ctrl_if_trx.py:109 (MS@172.18.28.22:6700) Starting transceiver...
2026-01-29 01:34:56.334 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 01:34:56.335 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:34:56.340 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 01:34:56.340 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 01:34:56.341 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 01:34:56.341 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 01:34:56.746 [DEBUG] clck_gen.py:113 IND CLOCK 2958
2026-01-29 01:34:57.224 [DEBUG] clck_gen.py:113 IND CLOCK 3060
2026-01-29 01:34:57.671 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:34:57.675 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:34:57.702 [DEBUG] clck_gen.py:113 IND CLOCK 3162
2026-01-29 01:34:58.155 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:34:58.156 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 01:34:58.156 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 01:34:58.156 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 01:34:58.163 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 01:34:58.163 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 01:34:58.163 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 01:34:58.165 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 01:34:58.165 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 01:34:58.165 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 01:34:58.165 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.28.22:6700) Recv POWERON CMD
2026-01-29 01:34:58.165 [INFO] ctrl_if_trx.py:109 (MS@172.18.28.22:6700) Starting transceiver...
2026-01-29 01:34:58.178 [DEBUG] clck_gen.py:113 IND CLOCK 3264
2026-01-29 01:34:58.206 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:34:58.207 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 01:34:58.208 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 01:34:58.208 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 01:34:58.208 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 01:34:58.650 [DEBUG] clck_gen.py:113 IND CLOCK 3366
2026-01-29 01:34:59.125 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:34:59.128 [DEBUG] clck_gen.py:113 IND CLOCK 3468
2026-01-29 01:34:59.129 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:34:59.606 [DEBUG] clck_gen.py:113 IND CLOCK 3570
2026-01-29 01:34:59.619 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:34:59.621 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 01:34:59.622 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 01:34:59.622 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 01:34:59.641 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 01:34:59.642 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 01:34:59.642 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 01:34:59.644 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 01:34:59.644 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 01:34:59.644 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 01:34:59.644 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.28.22:6700) Recv POWERON CMD
2026-01-29 01:34:59.644 [INFO] ctrl_if_trx.py:109 (MS@172.18.28.22:6700) Starting transceiver...
2026-01-29 01:34:59.686 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:34:59.691 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 01:34:59.691 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 01:34:59.691 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 01:34:59.692 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 01:35:00.084 [DEBUG] clck_gen.py:113 IND CLOCK 3672
2026-01-29 01:35:00.562 [DEBUG] clck_gen.py:113 IND CLOCK 3774
2026-01-29 01:35:00.653 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:35:00.657 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:35:01.040 [DEBUG] clck_gen.py:113 IND CLOCK 3876
2026-01-29 01:35:01.141 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:35:01.144 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 01:35:01.144 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 01:35:01.145 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 01:35:01.162 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 01:35:01.162 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 01:35:01.162 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 01:35:01.164 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 01:35:01.164 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 01:35:01.164 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 01:35:01.164 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.28.22:6700) Recv POWERON CMD
2026-01-29 01:35:01.164 [INFO] ctrl_if_trx.py:109 (MS@172.18.28.22:6700) Starting transceiver...
2026-01-29 01:35:01.206 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:35:01.212 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 01:35:01.212 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 01:35:01.213 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 01:35:01.213 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 01:35:01.517 [DEBUG] clck_gen.py:113 IND CLOCK 3978
2026-01-29 01:35:01.995 [DEBUG] clck_gen.py:113 IND CLOCK 4080
2026-01-29 01:35:02.152 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:35:02.157 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:35:02.473 [DEBUG] clck_gen.py:113 IND CLOCK 4182
2026-01-29 01:35:02.629 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:35:02.631 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 01:35:02.632 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 01:35:02.632 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 01:35:02.649 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 01:35:02.649 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 01:35:02.649 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 01:35:02.651 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 01:35:02.651 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 01:35:02.651 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 01:35:02.651 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.28.22:6700) Recv POWERON CMD
2026-01-29 01:35:02.651 [INFO] ctrl_if_trx.py:109 (MS@172.18.28.22:6700) Starting transceiver...
2026-01-29 01:35:02.698 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:35:02.703 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 01:35:02.704 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 01:35:02.704 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 01:35:02.704 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 01:35:02.951 [DEBUG] clck_gen.py:113 IND CLOCK 4284
2026-01-29 01:35:03.429 [DEBUG] clck_gen.py:113 IND CLOCK 4386
2026-01-29 01:35:03.604 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:35:03.608 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:35:03.907 [DEBUG] clck_gen.py:113 IND CLOCK 4488
2026-01-29 01:35:04.082 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:35:04.084 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 01:35:04.084 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 01:35:04.084 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 01:35:04.104 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 01:35:04.104 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 01:35:04.104 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 01:35:04.106 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 01:35:04.106 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 01:35:04.106 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 01:35:04.106 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.28.22:6700) Recv POWERON CMD
2026-01-29 01:35:04.106 [INFO] ctrl_if_trx.py:109 (MS@172.18.28.22:6700) Starting transceiver...
2026-01-29 01:35:04.146 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:35:04.151 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 01:35:04.152 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 01:35:04.152 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 01:35:04.153 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 01:35:04.385 [DEBUG] clck_gen.py:113 IND CLOCK 4590
2026-01-29 01:35:04.862 [DEBUG] clck_gen.py:113 IND CLOCK 4692
2026-01-29 01:35:05.056 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:35:05.060 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:35:05.340 [DEBUG] clck_gen.py:113 IND CLOCK 4794
2026-01-29 01:35:05.533 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:35:05.536 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 01:35:05.536 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 01:35:05.536 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 01:35:05.553 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 01:35:05.553 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 01:35:05.553 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 01:35:05.555 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 01:35:05.555 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 01:35:05.555 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 01:35:05.555 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.28.22:6700) Recv POWERON CMD
2026-01-29 01:35:05.555 [INFO] ctrl_if_trx.py:109 (MS@172.18.28.22:6700) Starting transceiver...
2026-01-29 01:35:05.602 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:35:05.607 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 01:35:05.607 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 01:35:05.607 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 01:35:05.607 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 01:35:05.817 [DEBUG] clck_gen.py:113 IND CLOCK 4896
2026-01-29 01:35:06.295 [DEBUG] clck_gen.py:113 IND CLOCK 4998
2026-01-29 01:35:06.506 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:35:06.510 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:35:06.772 [DEBUG] clck_gen.py:113 IND CLOCK 5100
2026-01-29 01:35:06.984 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:35:06.987 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 01:35:06.987 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 01:35:06.987 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 01:35:07.004 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 01:35:07.004 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 01:35:07.004 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 01:35:07.006 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 01:35:07.007 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 01:35:07.007 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 01:35:07.007 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.28.22:6700) Recv POWERON CMD
2026-01-29 01:35:07.007 [INFO] ctrl_if_trx.py:109 (MS@172.18.28.22:6700) Starting transceiver...
2026-01-29 01:35:07.055 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:35:07.059 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 01:35:07.060 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 01:35:07.060 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 01:35:07.061 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 01:35:07.250 [DEBUG] clck_gen.py:113 IND CLOCK 5202
2026-01-29 01:35:07.641 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:35:07.645 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:35:07.727 [DEBUG] clck_gen.py:113 IND CLOCK 5304
2026-01-29 01:35:08.119 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:35:08.121 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 01:35:08.122 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 01:35:08.122 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 01:35:08.140 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 01:35:08.140 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 01:35:08.140 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 01:35:08.142 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 01:35:08.142 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 01:35:08.142 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 01:35:08.142 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.28.22:6700) Recv POWERON CMD
2026-01-29 01:35:08.142 [INFO] ctrl_if_trx.py:109 (MS@172.18.28.22:6700) Starting transceiver...
2026-01-29 01:35:08.186 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:35:08.191 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 01:35:08.192 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 01:35:08.193 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 01:35:08.193 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 01:35:08.205 [DEBUG] clck_gen.py:113 IND CLOCK 5406
2026-01-29 01:35:08.683 [DEBUG] clck_gen.py:113 IND CLOCK 5508
2026-01-29 01:35:09.093 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:35:09.098 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:35:09.160 [DEBUG] clck_gen.py:113 IND CLOCK 5610
2026-01-29 01:35:09.571 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:35:09.574 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 01:35:09.575 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 01:35:09.575 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 01:35:09.593 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 01:35:09.593 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 01:35:09.593 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 01:35:09.594 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 01:35:09.595 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 01:35:09.595 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 01:35:09.595 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.28.22:6700) Recv POWERON CMD
2026-01-29 01:35:09.595 [INFO] ctrl_if_trx.py:109 (MS@172.18.28.22:6700) Starting transceiver...
2026-01-29 01:35:09.638 [DEBUG] clck_gen.py:113 IND CLOCK 5712
2026-01-29 01:35:09.638 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:35:09.643 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 01:35:09.644 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 01:35:09.644 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 01:35:09.644 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 01:35:10.116 [DEBUG] clck_gen.py:113 IND CLOCK 5814
2026-01-29 01:35:10.544 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:35:10.549 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:35:10.594 [DEBUG] clck_gen.py:113 IND CLOCK 5916
2026-01-29 01:35:11.022 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:35:11.025 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 01:35:11.025 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 01:35:11.026 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 01:35:11.043 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 01:35:11.043 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 01:35:11.044 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 01:35:11.046 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 01:35:11.046 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 01:35:11.046 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 01:35:11.046 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.28.22:6700) Recv POWERON CMD
2026-01-29 01:35:11.046 [INFO] ctrl_if_trx.py:109 (MS@172.18.28.22:6700) Starting transceiver...
2026-01-29 01:35:11.071 [DEBUG] clck_gen.py:113 IND CLOCK 6018
2026-01-29 01:35:11.090 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:35:11.095 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 01:35:11.096 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 01:35:11.096 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 01:35:11.097 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 01:35:11.548 [DEBUG] clck_gen.py:113 IND CLOCK 6120
2026-01-29 01:35:11.995 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:35:12.000 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:35:12.026 [DEBUG] clck_gen.py:113 IND CLOCK 6222
2026-01-29 01:35:12.473 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:35:12.476 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 01:35:12.476 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 01:35:12.476 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 01:35:12.487 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 01:35:12.487 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 01:35:12.487 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 01:35:12.487 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 01:35:12.490 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 01:35:12.490 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 01:35:12.490 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 01:35:12.490 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.28.20:5700) Recv POWEROFF cmd
2026-01-29 01:35:12.490 [INFO] ctrl_if_trx.py:117 (BTS@172.18.28.20:5700) Stopping transceiver...
2026-01-29 01:35:12.490 [INFO] transceiver.py:246 Stopping clock generator
2026-01-29 01:35:12.490 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 01:35:12.490 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=6323 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 01:35:12.490 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=6323 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 01:35:17.495 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.28.20:5700) Recv POWEROFF cmd
2026-01-29 01:35:17.495 [INFO] ctrl_if_trx.py:117 (BTS@172.18.28.20:5700) Stopping transceiver...
2026-01-29 01:35:17.495 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 01:35:17.495 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 01:35:17.495 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 01:35:17.495 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 01:35:17.504 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 01:35:17.506 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.28.20:5700) Recv SETFORMAT cmd
2026-01-29 01:35:17.506 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.28.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 01:35:17.507 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.28.20:5700) Recv SETFORMAT cmd
2026-01-29 01:35:17.507 [INFO] ctrl_if_trx.py:201 (BTS@172.18.28.20:5700) TRXD header version 1 -> 1
2026-01-29 01:35:17.512 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.28.20:5700/1) Recv RXTUNE cmd
2026-01-29 01:35:17.513 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.28.20:5700/1) Recv TXTUNE cmd
2026-01-29 01:35:17.513 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.28.20:5700/1) Recv SETFORMAT cmd
2026-01-29 01:35:17.514 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.28.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 01:35:17.514 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 01:35:17.514 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.28.20:5700/1) Recv NOMTXPOWER cmd
2026-01-29 01:35:17.515 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.28.20:5700/1) Recv SETFORMAT cmd
2026-01-29 01:35:17.515 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.28.20:5700/1) TRXD header version 1 -> 1
2026-01-29 01:35:17.517 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.28.20:5700/2) Recv RXTUNE cmd
2026-01-29 01:35:17.517 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.28.20:5700/2) Recv TXTUNE cmd
2026-01-29 01:35:17.518 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.28.20:5700/2) Recv SETFORMAT cmd
2026-01-29 01:35:17.518 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.28.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 01:35:17.518 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 01:35:17.518 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.28.20:5700/2) Recv NOMTXPOWER cmd
2026-01-29 01:35:17.518 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.28.20:5700/2) Recv SETFORMAT cmd
2026-01-29 01:35:17.519 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.28.20:5700/2) TRXD header version 1 -> 1
2026-01-29 01:35:17.520 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.28.20:5700/3) Recv RXTUNE cmd
2026-01-29 01:35:17.520 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.28.20:5700/3) Recv TXTUNE cmd
2026-01-29 01:35:17.520 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.28.20:5700/3) Recv SETFORMAT cmd
2026-01-29 01:35:17.521 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.28.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 01:35:17.521 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 01:35:17.521 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.28.20:5700/3) Recv NOMTXPOWER cmd
2026-01-29 01:35:17.521 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.28.20:5700/3) Recv SETFORMAT cmd
2026-01-29 01:35:17.521 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.28.20:5700/3) TRXD header version 1 -> 1
2026-01-29 01:35:17.524 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.28.20:5700) Recv RXTUNE cmd
2026-01-29 01:35:17.524 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETTSC
2026-01-29 01:35:17.524 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETTSC
2026-01-29 01:35:17.524 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETTSC
2026-01-29 01:35:17.524 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.28.20:5700) Recv TXTUNE cmd
2026-01-29 01:35:17.524 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETRXGAIN
2026-01-29 01:35:17.524 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETRXGAIN
2026-01-29 01:35:17.524 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETRXGAIN
2026-01-29 01:35:17.524 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETTSC
2026-01-29 01:35:17.524 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:35:17.524 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:35:17.524 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.28.20:5700) Recv NOMTXPOWER cmd
2026-01-29 01:35:17.524 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:35:17.524 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:35:17.524 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:35:17.524 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.28.20:5700) Recv POWERON CMD
2026-01-29 01:35:17.524 [INFO] ctrl_if_trx.py:109 (BTS@172.18.28.20:5700) Starting transceiver...
2026-01-29 01:35:17.524 [INFO] transceiver.py:243 Starting clock generator
2026-01-29 01:35:17.525 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-01-29 01:35:17.525 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:35:17.525 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:35:17.525 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:35:17.525 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETRXGAIN
2026-01-29 01:35:17.525 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:35:17.525 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:35:17.525 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 01:35:17.525 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:35:17.525 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:35:17.525 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:35:17.525 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 01:35:17.525 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:35:17.525 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:35:17.526 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:35:17.526 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 01:35:17.526 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:35:17.526 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:35:17.526 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:35:17.526 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 01:35:17.526 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:35:17.526 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:35:17.526 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 01:35:17.526 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:35:17.526 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 01:35:17.526 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:35:17.526 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 01:35:17.526 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:35:17.526 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 01:35:17.530 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-01-29 01:35:18.014 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-01-29 01:35:18.056 [DEBUG] fake_trx.py:278 (BTS@172.18.28.20:5700) Recv FAKE_TOA cmd
2026-01-29 01:35:18.059 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:35:18.059 [DEBUG] fake_trx.py:297 (BTS@172.18.28.20:5700) Recv FAKE_RSSI cmd
2026-01-29 01:35:18.061 [DEBUG] fake_trx.py:322 (BTS@172.18.28.20:5700) Recv FAKE_CI cmd
2026-01-29 01:35:18.083 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 01:35:18.084 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 01:35:18.084 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 01:35:18.091 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 01:35:18.091 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 01:35:18.091 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 01:35:18.091 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.28.22:6700) Recv POWERON CMD
2026-01-29 01:35:18.092 [INFO] ctrl_if_trx.py:109 (MS@172.18.28.22:6700) Starting transceiver...
2026-01-29 01:35:18.107 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:35:18.113 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 01:35:18.114 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 01:35:18.114 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 01:35:18.114 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 01:35:18.491 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-01-29 01:35:18.529 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 01:35:18.529 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 01:35:18.532 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 01:35:18.536 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 01:35:18.969 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-01-29 01:35:19.447 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-01-29 01:35:19.530 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 01:35:19.530 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 01:35:19.533 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 01:35:19.537 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 01:35:19.925 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-01-29 01:35:20.403 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-01-29 01:35:20.531 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 01:35:20.531 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 01:35:20.533 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 01:35:20.538 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 01:35:20.881 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-01-29 01:35:21.358 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-01-29 01:35:21.532 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 01:35:21.532 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 01:35:21.534 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 01:35:21.539 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 01:35:21.836 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-01-29 01:35:22.038 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:35:22.040 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 01:35:22.041 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 01:35:22.041 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 01:35:22.058 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 01:35:22.058 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 01:35:22.058 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 01:35:22.060 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 01:35:22.060 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 01:35:22.060 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 01:35:22.060 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.28.22:6700) Recv POWERON CMD
2026-01-29 01:35:22.060 [INFO] ctrl_if_trx.py:109 (MS@172.18.28.22:6700) Starting transceiver...
2026-01-29 01:35:22.102 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:35:22.107 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 01:35:22.108 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 01:35:22.108 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 01:35:22.109 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 01:35:22.314 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-01-29 01:35:22.533 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 01:35:22.534 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 01:35:22.535 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 01:35:22.540 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 01:35:22.792 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-01-29 01:35:23.269 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-01-29 01:35:23.746 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-01-29 01:35:24.223 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-01-29 01:35:24.701 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-01-29 01:35:25.179 [DEBUG] clck_gen.py:113 IND CLOCK 1632
2026-01-29 01:35:25.657 [DEBUG] clck_gen.py:113 IND CLOCK 1734
2026-01-29 01:35:26.134 [DEBUG] clck_gen.py:113 IND CLOCK 1836
2026-01-29 01:35:26.355 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:35:26.357 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 01:35:26.357 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 01:35:26.358 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 01:35:26.375 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 01:35:26.375 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 01:35:26.375 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 01:35:26.377 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 01:35:26.377 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 01:35:26.377 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 01:35:26.377 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.28.22:6700) Recv POWERON CMD
2026-01-29 01:35:26.377 [INFO] ctrl_if_trx.py:109 (MS@172.18.28.22:6700) Starting transceiver...
2026-01-29 01:35:26.418 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:35:26.423 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 01:35:26.424 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 01:35:26.424 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 01:35:26.424 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 01:35:26.612 [DEBUG] clck_gen.py:113 IND CLOCK 1938
2026-01-29 01:35:27.089 [DEBUG] clck_gen.py:113 IND CLOCK 2040
2026-01-29 01:35:27.567 [DEBUG] clck_gen.py:113 IND CLOCK 2142
2026-01-29 01:35:28.044 [DEBUG] clck_gen.py:113 IND CLOCK 2244
2026-01-29 01:35:28.522 [DEBUG] clck_gen.py:113 IND CLOCK 2346
2026-01-29 01:35:29.000 [DEBUG] clck_gen.py:113 IND CLOCK 2448
2026-01-29 01:35:29.478 [DEBUG] clck_gen.py:113 IND CLOCK 2550
2026-01-29 01:35:29.956 [DEBUG] clck_gen.py:113 IND CLOCK 2652
2026-01-29 01:35:30.393 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:35:30.397 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 01:35:30.397 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 01:35:30.397 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 01:35:30.417 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 01:35:30.417 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 01:35:30.417 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 01:35:30.419 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 01:35:30.419 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 01:35:30.419 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 01:35:30.419 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.28.22:6700) Recv POWERON CMD
2026-01-29 01:35:30.419 [INFO] ctrl_if_trx.py:109 (MS@172.18.28.22:6700) Starting transceiver...
2026-01-29 01:35:30.433 [DEBUG] clck_gen.py:113 IND CLOCK 2754
2026-01-29 01:35:30.463 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:35:30.467 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 01:35:30.468 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 01:35:30.468 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 01:35:30.468 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 01:35:30.910 [DEBUG] clck_gen.py:113 IND CLOCK 2856
2026-01-29 01:35:31.388 [DEBUG] clck_gen.py:113 IND CLOCK 2958
2026-01-29 01:35:31.866 [DEBUG] clck_gen.py:113 IND CLOCK 3060
2026-01-29 01:35:32.344 [DEBUG] clck_gen.py:113 IND CLOCK 3162
2026-01-29 01:35:32.822 [DEBUG] clck_gen.py:113 IND CLOCK 3264
2026-01-29 01:35:33.300 [DEBUG] clck_gen.py:113 IND CLOCK 3366
2026-01-29 01:35:33.778 [DEBUG] clck_gen.py:113 IND CLOCK 3468
2026-01-29 01:35:34.256 [DEBUG] clck_gen.py:113 IND CLOCK 3570
2026-01-29 01:35:34.712 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:35:34.715 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 01:35:34.715 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 01:35:34.715 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 01:35:34.732 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 01:35:34.732 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 01:35:34.732 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 01:35:34.733 [DEBUG] clck_gen.py:113 IND CLOCK 3672
2026-01-29 01:35:34.735 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 01:35:34.735 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 01:35:34.735 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 01:35:34.735 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.28.22:6700) Recv POWERON CMD
2026-01-29 01:35:34.735 [INFO] ctrl_if_trx.py:109 (MS@172.18.28.22:6700) Starting transceiver...
2026-01-29 01:35:34.780 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:35:34.784 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 01:35:34.785 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 01:35:34.785 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 01:35:34.786 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 01:35:35.211 [DEBUG] clck_gen.py:113 IND CLOCK 3774
2026-01-29 01:35:35.688 [DEBUG] clck_gen.py:113 IND CLOCK 3876
2026-01-29 01:35:36.166 [DEBUG] clck_gen.py:113 IND CLOCK 3978
2026-01-29 01:35:36.644 [DEBUG] clck_gen.py:113 IND CLOCK 4080
2026-01-29 01:35:37.122 [DEBUG] clck_gen.py:113 IND CLOCK 4182
2026-01-29 01:35:37.600 [DEBUG] clck_gen.py:113 IND CLOCK 4284
2026-01-29 01:35:38.077 [DEBUG] clck_gen.py:113 IND CLOCK 4386
2026-01-29 01:35:38.551 [DEBUG] clck_gen.py:113 IND CLOCK 4488
2026-01-29 01:35:39.027 [DEBUG] clck_gen.py:113 IND CLOCK 4590
2026-01-29 01:35:39.432 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:35:39.435 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 01:35:39.436 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 01:35:39.436 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 01:35:39.451 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 01:35:39.451 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 01:35:39.451 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 01:35:39.453 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 01:35:39.453 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 01:35:39.453 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 01:35:39.453 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.28.22:6700) Recv POWERON CMD
2026-01-29 01:35:39.453 [INFO] ctrl_if_trx.py:109 (MS@172.18.28.22:6700) Starting transceiver...
2026-01-29 01:35:39.498 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:35:39.504 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 01:35:39.505 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 01:35:39.505 [DEBUG] clck_gen.py:113 IND CLOCK 4692
2026-01-29 01:35:39.505 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 01:35:39.506 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 01:35:39.983 [DEBUG] clck_gen.py:113 IND CLOCK 4794
2026-01-29 01:35:40.460 [DEBUG] clck_gen.py:113 IND CLOCK 4896
2026-01-29 01:35:40.938 [DEBUG] clck_gen.py:113 IND CLOCK 4998
2026-01-29 01:35:41.416 [DEBUG] clck_gen.py:113 IND CLOCK 5100
2026-01-29 01:35:41.894 [DEBUG] clck_gen.py:113 IND CLOCK 5202
2026-01-29 01:35:42.372 [DEBUG] clck_gen.py:113 IND CLOCK 5304
2026-01-29 01:35:42.851 [DEBUG] clck_gen.py:113 IND CLOCK 5406
2026-01-29 01:35:43.328 [DEBUG] clck_gen.py:113 IND CLOCK 5508
2026-01-29 01:35:43.807 [DEBUG] clck_gen.py:113 IND CLOCK 5610
2026-01-29 01:35:43.884 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:35:43.887 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 01:35:43.887 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 01:35:43.887 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 01:35:43.887 [WARNING] transceiver.py:257 (MS@172.18.28.22:6700) RX TRXD message (fn=5629 tn=7 pwr=0), but transceiver is not running => dropping...
2026-01-29 01:35:43.903 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 01:35:43.903 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 01:35:43.903 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 01:35:43.905 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 01:35:43.905 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 01:35:43.905 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 01:35:43.905 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.28.22:6700) Recv POWERON CMD
2026-01-29 01:35:43.905 [INFO] ctrl_if_trx.py:109 (MS@172.18.28.22:6700) Starting transceiver...
2026-01-29 01:35:43.946 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:35:43.952 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 01:35:43.952 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 01:35:43.953 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 01:35:43.953 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 01:35:44.284 [DEBUG] clck_gen.py:113 IND CLOCK 5712
2026-01-29 01:35:44.762 [DEBUG] clck_gen.py:113 IND CLOCK 5814
2026-01-29 01:35:45.240 [DEBUG] clck_gen.py:113 IND CLOCK 5916
2026-01-29 01:35:45.718 [DEBUG] clck_gen.py:113 IND CLOCK 6018
2026-01-29 01:35:46.196 [DEBUG] clck_gen.py:113 IND CLOCK 6120
2026-01-29 01:35:46.675 [DEBUG] clck_gen.py:113 IND CLOCK 6222
2026-01-29 01:35:47.152 [DEBUG] clck_gen.py:113 IND CLOCK 6324
2026-01-29 01:35:47.630 [DEBUG] clck_gen.py:113 IND CLOCK 6426
2026-01-29 01:35:48.107 [DEBUG] clck_gen.py:113 IND CLOCK 6528
2026-01-29 01:35:48.328 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:35:48.331 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 01:35:48.331 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 01:35:48.331 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 01:35:48.346 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 01:35:48.346 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 01:35:48.346 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 01:35:48.348 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 01:35:48.348 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 01:35:48.348 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 01:35:48.348 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.28.22:6700) Recv POWERON CMD
2026-01-29 01:35:48.348 [INFO] ctrl_if_trx.py:109 (MS@172.18.28.22:6700) Starting transceiver...
2026-01-29 01:35:48.390 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 01:35:48.391 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:35:48.396 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 01:35:48.397 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 01:35:48.397 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 01:35:48.397 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 01:35:48.585 [DEBUG] clck_gen.py:113 IND CLOCK 6630
2026-01-29 01:35:49.063 [DEBUG] clck_gen.py:113 IND CLOCK 6732
2026-01-29 01:35:49.541 [DEBUG] clck_gen.py:113 IND CLOCK 6834
2026-01-29 01:35:50.019 [DEBUG] clck_gen.py:113 IND CLOCK 6936
2026-01-29 01:35:50.496 [DEBUG] clck_gen.py:113 IND CLOCK 7038
2026-01-29 01:35:50.975 [DEBUG] clck_gen.py:113 IND CLOCK 7140
2026-01-29 01:35:51.452 [DEBUG] clck_gen.py:113 IND CLOCK 7242
2026-01-29 01:35:51.930 [DEBUG] clck_gen.py:113 IND CLOCK 7344
2026-01-29 01:35:52.408 [DEBUG] clck_gen.py:113 IND CLOCK 7446
2026-01-29 01:35:52.772 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:35:52.774 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 01:35:52.775 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 01:35:52.775 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 01:35:52.792 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 01:35:52.792 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 01:35:52.792 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 01:35:52.794 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 01:35:52.794 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 01:35:52.794 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 01:35:52.794 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.28.22:6700) Recv POWERON CMD
2026-01-29 01:35:52.794 [INFO] ctrl_if_trx.py:109 (MS@172.18.28.22:6700) Starting transceiver...
2026-01-29 01:35:52.839 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:35:52.844 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 01:35:52.844 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 01:35:52.844 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 01:35:52.845 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 01:35:52.886 [DEBUG] clck_gen.py:113 IND CLOCK 7548
2026-01-29 01:35:53.364 [DEBUG] clck_gen.py:113 IND CLOCK 7650
2026-01-29 01:35:53.841 [DEBUG] clck_gen.py:113 IND CLOCK 7752
2026-01-29 01:35:54.319 [DEBUG] clck_gen.py:113 IND CLOCK 7854
2026-01-29 01:35:54.798 [DEBUG] clck_gen.py:113 IND CLOCK 7956
2026-01-29 01:35:55.276 [DEBUG] clck_gen.py:113 IND CLOCK 8058
2026-01-29 01:35:55.754 [DEBUG] clck_gen.py:113 IND CLOCK 8160
2026-01-29 01:35:56.232 [DEBUG] clck_gen.py:113 IND CLOCK 8262
2026-01-29 01:35:56.710 [DEBUG] clck_gen.py:113 IND CLOCK 8364
2026-01-29 01:35:57.188 [DEBUG] clck_gen.py:113 IND CLOCK 8466
2026-01-29 01:35:57.224 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:35:57.226 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 01:35:57.227 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 01:35:57.227 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 01:35:57.236 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 01:35:57.236 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 01:35:57.236 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 01:35:57.238 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 01:35:57.238 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 01:35:57.238 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 01:35:57.238 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.28.22:6700) Recv POWERON CMD
2026-01-29 01:35:57.238 [INFO] ctrl_if_trx.py:109 (MS@172.18.28.22:6700) Starting transceiver...
2026-01-29 01:35:57.282 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 01:35:57.283 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:35:57.287 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 01:35:57.288 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 01:35:57.288 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 01:35:57.288 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 01:35:57.665 [DEBUG] clck_gen.py:113 IND CLOCK 8568
2026-01-29 01:35:58.143 [DEBUG] clck_gen.py:113 IND CLOCK 8670
2026-01-29 01:35:58.620 [DEBUG] clck_gen.py:113 IND CLOCK 8772
2026-01-29 01:35:59.098 [DEBUG] clck_gen.py:113 IND CLOCK 8874
2026-01-29 01:35:59.576 [DEBUG] clck_gen.py:113 IND CLOCK 8976
2026-01-29 01:36:00.054 [DEBUG] clck_gen.py:113 IND CLOCK 9078
2026-01-29 01:36:00.532 [DEBUG] clck_gen.py:113 IND CLOCK 9180
2026-01-29 01:36:01.010 [DEBUG] clck_gen.py:113 IND CLOCK 9282
2026-01-29 01:36:01.488 [DEBUG] clck_gen.py:113 IND CLOCK 9384
2026-01-29 01:36:01.547 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:36:01.550 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 01:36:01.550 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 01:36:01.550 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 01:36:01.566 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 01:36:01.566 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 01:36:01.567 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 01:36:01.569 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 01:36:01.569 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 01:36:01.569 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 01:36:01.569 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.28.22:6700) Recv POWERON CMD
2026-01-29 01:36:01.569 [INFO] ctrl_if_trx.py:109 (MS@172.18.28.22:6700) Starting transceiver...
2026-01-29 01:36:01.610 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:36:01.615 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 01:36:01.616 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 01:36:01.616 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 01:36:01.616 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 01:36:01.965 [DEBUG] clck_gen.py:113 IND CLOCK 9486
2026-01-29 01:36:02.444 [DEBUG] clck_gen.py:113 IND CLOCK 9588
2026-01-29 01:36:02.922 [DEBUG] clck_gen.py:113 IND CLOCK 9690
2026-01-29 01:36:03.400 [DEBUG] clck_gen.py:113 IND CLOCK 9792
2026-01-29 01:36:03.878 [DEBUG] clck_gen.py:113 IND CLOCK 9894
2026-01-29 01:36:04.356 [DEBUG] clck_gen.py:113 IND CLOCK 9996
2026-01-29 01:36:04.835 [DEBUG] clck_gen.py:113 IND CLOCK 10098
2026-01-29 01:36:05.313 [DEBUG] clck_gen.py:113 IND CLOCK 10200
2026-01-29 01:36:05.791 [DEBUG] clck_gen.py:113 IND CLOCK 10302
2026-01-29 01:36:05.934 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:36:05.936 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 01:36:05.937 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 01:36:05.937 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 01:36:05.954 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 01:36:05.954 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 01:36:05.954 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 01:36:05.956 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 01:36:05.956 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 01:36:05.956 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 01:36:05.956 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.28.22:6700) Recv POWERON CMD
2026-01-29 01:36:05.957 [INFO] ctrl_if_trx.py:109 (MS@172.18.28.22:6700) Starting transceiver...
2026-01-29 01:36:05.998 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:36:06.003 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 01:36:06.004 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 01:36:06.005 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 01:36:06.005 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 01:36:06.269 [DEBUG] clck_gen.py:113 IND CLOCK 10404
2026-01-29 01:36:06.747 [DEBUG] clck_gen.py:113 IND CLOCK 10506
2026-01-29 01:36:07.225 [DEBUG] clck_gen.py:113 IND CLOCK 10608
2026-01-29 01:36:07.703 [DEBUG] clck_gen.py:113 IND CLOCK 10710
2026-01-29 01:36:08.182 [DEBUG] clck_gen.py:113 IND CLOCK 10812
2026-01-29 01:36:08.660 [DEBUG] clck_gen.py:113 IND CLOCK 10914
2026-01-29 01:36:09.138 [DEBUG] clck_gen.py:113 IND CLOCK 11016
2026-01-29 01:36:09.615 [DEBUG] clck_gen.py:113 IND CLOCK 11118
2026-01-29 01:36:10.094 [DEBUG] clck_gen.py:113 IND CLOCK 11220
2026-01-29 01:36:10.379 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:36:10.382 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 01:36:10.383 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 01:36:10.383 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 01:36:10.400 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 01:36:10.400 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 01:36:10.400 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 01:36:10.402 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 01:36:10.402 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 01:36:10.402 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 01:36:10.402 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.28.22:6700) Recv POWERON CMD
2026-01-29 01:36:10.402 [INFO] ctrl_if_trx.py:109 (MS@172.18.28.22:6700) Starting transceiver...
2026-01-29 01:36:10.442 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:36:10.448 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 01:36:10.449 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 01:36:10.450 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 01:36:10.450 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 01:36:10.571 [DEBUG] clck_gen.py:113 IND CLOCK 11322
2026-01-29 01:36:11.049 [DEBUG] clck_gen.py:113 IND CLOCK 11424
2026-01-29 01:36:11.527 [DEBUG] clck_gen.py:113 IND CLOCK 11526
2026-01-29 01:36:12.004 [DEBUG] clck_gen.py:113 IND CLOCK 11628
2026-01-29 01:36:12.481 [DEBUG] clck_gen.py:113 IND CLOCK 11730
2026-01-29 01:36:12.959 [DEBUG] clck_gen.py:113 IND CLOCK 11832
2026-01-29 01:36:13.437 [DEBUG] clck_gen.py:113 IND CLOCK 11934
2026-01-29 01:36:13.915 [DEBUG] clck_gen.py:113 IND CLOCK 12036
2026-01-29 01:36:14.393 [DEBUG] clck_gen.py:113 IND CLOCK 12138
2026-01-29 01:36:14.550 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:36:14.553 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 01:36:14.553 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 01:36:14.553 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 01:36:14.563 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 01:36:14.563 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 01:36:14.563 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 01:36:14.565 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 01:36:14.565 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 01:36:14.565 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 01:36:14.565 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.28.22:6700) Recv POWERON CMD
2026-01-29 01:36:14.565 [INFO] ctrl_if_trx.py:109 (MS@172.18.28.22:6700) Starting transceiver...
2026-01-29 01:36:14.606 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:36:14.612 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 01:36:14.613 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 01:36:14.613 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 01:36:14.614 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 01:36:14.870 [DEBUG] clck_gen.py:113 IND CLOCK 12240
2026-01-29 01:36:15.348 [DEBUG] clck_gen.py:113 IND CLOCK 12342
2026-01-29 01:36:15.827 [DEBUG] clck_gen.py:113 IND CLOCK 12444
2026-01-29 01:36:16.305 [DEBUG] clck_gen.py:113 IND CLOCK 12546
2026-01-29 01:36:16.782 [DEBUG] clck_gen.py:113 IND CLOCK 12648
2026-01-29 01:36:17.260 [DEBUG] clck_gen.py:113 IND CLOCK 12750
2026-01-29 01:36:17.738 [DEBUG] clck_gen.py:113 IND CLOCK 12852
2026-01-29 01:36:18.215 [DEBUG] clck_gen.py:113 IND CLOCK 12954
2026-01-29 01:36:18.693 [DEBUG] clck_gen.py:113 IND CLOCK 13056
2026-01-29 01:36:18.868 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:36:18.872 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 01:36:18.872 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 01:36:18.872 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 01:36:18.890 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 01:36:18.890 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 01:36:18.890 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 01:36:18.892 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 01:36:18.892 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 01:36:18.892 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 01:36:18.892 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.28.22:6700) Recv POWERON CMD
2026-01-29 01:36:18.892 [INFO] ctrl_if_trx.py:109 (MS@172.18.28.22:6700) Starting transceiver...
2026-01-29 01:36:18.958 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:36:18.964 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 01:36:18.965 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 01:36:18.965 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 01:36:18.965 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 01:36:19.171 [DEBUG] clck_gen.py:113 IND CLOCK 13158
2026-01-29 01:36:19.649 [DEBUG] clck_gen.py:113 IND CLOCK 13260
2026-01-29 01:36:20.126 [DEBUG] clck_gen.py:113 IND CLOCK 13362
2026-01-29 01:36:20.603 [DEBUG] clck_gen.py:113 IND CLOCK 13464
2026-01-29 01:36:21.081 [DEBUG] clck_gen.py:113 IND CLOCK 13566
2026-01-29 01:36:21.559 [DEBUG] clck_gen.py:113 IND CLOCK 13668
2026-01-29 01:36:22.035 [DEBUG] clck_gen.py:113 IND CLOCK 13770
2026-01-29 01:36:22.513 [DEBUG] clck_gen.py:113 IND CLOCK 13872
2026-01-29 01:36:22.991 [DEBUG] clck_gen.py:113 IND CLOCK 13974
2026-01-29 01:36:23.184 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:36:23.187 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 01:36:23.188 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 01:36:23.188 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 01:36:23.204 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 01:36:23.204 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 01:36:23.205 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 01:36:23.207 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 01:36:23.207 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 01:36:23.207 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 01:36:23.207 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.28.22:6700) Recv POWERON CMD
2026-01-29 01:36:23.207 [INFO] ctrl_if_trx.py:109 (MS@172.18.28.22:6700) Starting transceiver...
2026-01-29 01:36:23.254 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:36:23.259 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 01:36:23.260 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 01:36:23.260 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 01:36:23.261 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 01:36:23.468 [DEBUG] clck_gen.py:113 IND CLOCK 14076
2026-01-29 01:36:23.945 [DEBUG] clck_gen.py:113 IND CLOCK 14178
2026-01-29 01:36:24.423 [DEBUG] clck_gen.py:113 IND CLOCK 14280
2026-01-29 01:36:24.900 [DEBUG] clck_gen.py:113 IND CLOCK 14382
2026-01-29 01:36:25.378 [DEBUG] clck_gen.py:113 IND CLOCK 14484
2026-01-29 01:36:25.855 [DEBUG] clck_gen.py:113 IND CLOCK 14586
2026-01-29 01:36:26.333 [DEBUG] clck_gen.py:113 IND CLOCK 14688
2026-01-29 01:36:26.811 [DEBUG] clck_gen.py:113 IND CLOCK 14790
2026-01-29 01:36:27.288 [DEBUG] clck_gen.py:113 IND CLOCK 14892
2026-01-29 01:36:27.500 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:36:27.502 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 01:36:27.503 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 01:36:27.503 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 01:36:27.513 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 01:36:27.514 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 01:36:27.514 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 01:36:27.515 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 01:36:27.516 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 01:36:27.516 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 01:36:27.516 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.28.22:6700) Recv POWERON CMD
2026-01-29 01:36:27.516 [INFO] ctrl_if_trx.py:109 (MS@172.18.28.22:6700) Starting transceiver...
2026-01-29 01:36:27.557 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:36:27.562 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 01:36:27.562 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 01:36:27.563 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 01:36:27.563 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 01:36:27.765 [DEBUG] clck_gen.py:113 IND CLOCK 14994
2026-01-29 01:36:28.242 [DEBUG] clck_gen.py:113 IND CLOCK 15096
2026-01-29 01:36:28.720 [DEBUG] clck_gen.py:113 IND CLOCK 15198
2026-01-29 01:36:29.197 [DEBUG] clck_gen.py:113 IND CLOCK 15300
2026-01-29 01:36:29.674 [DEBUG] clck_gen.py:113 IND CLOCK 15402
2026-01-29 01:36:30.152 [DEBUG] clck_gen.py:113 IND CLOCK 15504
2026-01-29 01:36:30.629 [DEBUG] clck_gen.py:113 IND CLOCK 15606
2026-01-29 01:36:31.107 [DEBUG] clck_gen.py:113 IND CLOCK 15708
2026-01-29 01:36:31.499 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:36:31.502 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 01:36:31.502 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 01:36:31.502 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 01:36:31.519 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 01:36:31.519 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 01:36:31.519 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 01:36:31.521 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 01:36:31.521 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 01:36:31.521 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 01:36:31.521 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.28.22:6700) Recv POWERON CMD
2026-01-29 01:36:31.521 [INFO] ctrl_if_trx.py:109 (MS@172.18.28.22:6700) Starting transceiver...
2026-01-29 01:36:31.559 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:36:31.565 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 01:36:31.565 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 01:36:31.566 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 01:36:31.566 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 01:36:31.584 [DEBUG] clck_gen.py:113 IND CLOCK 15810
2026-01-29 01:36:32.061 [DEBUG] clck_gen.py:113 IND CLOCK 15912
2026-01-29 01:36:32.539 [DEBUG] clck_gen.py:113 IND CLOCK 16014
2026-01-29 01:36:33.017 [DEBUG] clck_gen.py:113 IND CLOCK 16116
2026-01-29 01:36:33.495 [DEBUG] clck_gen.py:113 IND CLOCK 16218
2026-01-29 01:36:33.973 [DEBUG] clck_gen.py:113 IND CLOCK 16320
2026-01-29 01:36:34.451 [DEBUG] clck_gen.py:113 IND CLOCK 16422
2026-01-29 01:36:34.929 [DEBUG] clck_gen.py:113 IND CLOCK 16524
2026-01-29 01:36:35.407 [DEBUG] clck_gen.py:113 IND CLOCK 16626
2026-01-29 01:36:35.817 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:36:35.820 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 01:36:35.820 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 01:36:35.821 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 01:36:35.837 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 01:36:35.837 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 01:36:35.837 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 01:36:35.840 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 01:36:35.840 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 01:36:35.840 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 01:36:35.840 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.28.22:6700) Recv POWERON CMD
2026-01-29 01:36:35.840 [INFO] ctrl_if_trx.py:109 (MS@172.18.28.22:6700) Starting transceiver...
2026-01-29 01:36:35.882 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:36:35.884 [DEBUG] clck_gen.py:113 IND CLOCK 16728
2026-01-29 01:36:35.888 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 01:36:35.888 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 01:36:35.888 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 01:36:35.888 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 01:36:36.362 [DEBUG] clck_gen.py:113 IND CLOCK 16830
2026-01-29 01:36:36.840 [DEBUG] clck_gen.py:113 IND CLOCK 16932
2026-01-29 01:36:37.318 [DEBUG] clck_gen.py:113 IND CLOCK 17034
2026-01-29 01:36:37.796 [DEBUG] clck_gen.py:113 IND CLOCK 17136
2026-01-29 01:36:38.274 [DEBUG] clck_gen.py:113 IND CLOCK 17238
2026-01-29 01:36:38.751 [DEBUG] clck_gen.py:113 IND CLOCK 17340
2026-01-29 01:36:39.229 [DEBUG] clck_gen.py:113 IND CLOCK 17442
2026-01-29 01:36:39.707 [DEBUG] clck_gen.py:113 IND CLOCK 17544
2026-01-29 01:36:40.136 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:36:40.138 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 01:36:40.138 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 01:36:40.139 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 01:36:40.154 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 01:36:40.154 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 01:36:40.154 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 01:36:40.156 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 01:36:40.156 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 01:36:40.156 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 01:36:40.156 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.28.22:6700) Recv POWERON CMD
2026-01-29 01:36:40.156 [INFO] ctrl_if_trx.py:109 (MS@172.18.28.22:6700) Starting transceiver...
2026-01-29 01:36:40.185 [DEBUG] clck_gen.py:113 IND CLOCK 17646
2026-01-29 01:36:40.199 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:36:40.204 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 01:36:40.205 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 01:36:40.205 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 01:36:40.206 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 01:36:40.662 [DEBUG] clck_gen.py:113 IND CLOCK 17748
2026-01-29 01:36:41.140 [DEBUG] clck_gen.py:113 IND CLOCK 17850
2026-01-29 01:36:41.618 [DEBUG] clck_gen.py:113 IND CLOCK 17952
2026-01-29 01:36:42.095 [DEBUG] clck_gen.py:113 IND CLOCK 18054
2026-01-29 01:36:42.573 [DEBUG] clck_gen.py:113 IND CLOCK 18156
2026-01-29 01:36:43.051 [DEBUG] clck_gen.py:113 IND CLOCK 18258
2026-01-29 01:36:43.529 [DEBUG] clck_gen.py:113 IND CLOCK 18360
2026-01-29 01:36:44.006 [DEBUG] clck_gen.py:113 IND CLOCK 18462
2026-01-29 01:36:44.454 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:36:44.457 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 01:36:44.458 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 01:36:44.458 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 01:36:44.465 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 01:36:44.465 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 01:36:44.465 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 01:36:44.465 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 01:36:44.466 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 01:36:44.466 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 01:36:44.466 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 01:36:44.466 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 01:36:44.466 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.28.20:5700) Recv POWEROFF cmd
2026-01-29 01:36:44.466 [INFO] ctrl_if_trx.py:117 (BTS@172.18.28.20:5700) Stopping transceiver...
2026-01-29 01:36:44.466 [INFO] transceiver.py:246 Stopping clock generator
2026-01-29 01:36:49.469 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.28.20:5700) Recv POWEROFF cmd
2026-01-29 01:36:49.469 [INFO] ctrl_if_trx.py:117 (BTS@172.18.28.20:5700) Stopping transceiver...
2026-01-29 01:36:49.471 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 01:36:49.472 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 01:36:49.474 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 01:36:49.477 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 01:36:49.486 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 01:36:49.486 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.28.20:5700) Recv SETFORMAT cmd
2026-01-29 01:36:49.486 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.28.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 01:36:49.486 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.28.20:5700) Recv SETFORMAT cmd
2026-01-29 01:36:49.486 [INFO] ctrl_if_trx.py:201 (BTS@172.18.28.20:5700) TRXD header version 1 -> 1
2026-01-29 01:36:49.487 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.28.20:5700/1) Recv RXTUNE cmd
2026-01-29 01:36:49.487 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.28.20:5700/1) Recv TXTUNE cmd
2026-01-29 01:36:49.487 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.28.20:5700/1) Recv SETFORMAT cmd
2026-01-29 01:36:49.487 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.28.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 01:36:49.487 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 01:36:49.487 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.28.20:5700/1) Recv NOMTXPOWER cmd
2026-01-29 01:36:49.487 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.28.20:5700/1) Recv SETFORMAT cmd
2026-01-29 01:36:49.487 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.28.20:5700/1) TRXD header version 1 -> 1
2026-01-29 01:36:49.487 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.28.20:5700/2) Recv RXTUNE cmd
2026-01-29 01:36:49.487 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.28.20:5700/2) Recv TXTUNE cmd
2026-01-29 01:36:49.487 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.28.20:5700/2) Recv SETFORMAT cmd
2026-01-29 01:36:49.487 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.28.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 01:36:49.487 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 01:36:49.488 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.28.20:5700/2) Recv NOMTXPOWER cmd
2026-01-29 01:36:49.488 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.28.20:5700/2) Recv SETFORMAT cmd
2026-01-29 01:36:49.488 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.28.20:5700/2) TRXD header version 1 -> 1
2026-01-29 01:36:49.489 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.28.20:5700/3) Recv RXTUNE cmd
2026-01-29 01:36:49.489 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.28.20:5700/3) Recv TXTUNE cmd
2026-01-29 01:36:49.489 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.28.20:5700/3) Recv SETFORMAT cmd
2026-01-29 01:36:49.489 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.28.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 01:36:49.489 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 01:36:49.489 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.28.20:5700/3) Recv NOMTXPOWER cmd
2026-01-29 01:36:49.489 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.28.20:5700/3) Recv SETFORMAT cmd
2026-01-29 01:36:49.489 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.28.20:5700/3) TRXD header version 1 -> 1
2026-01-29 01:36:49.491 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.28.20:5700) Recv RXTUNE cmd
2026-01-29 01:36:49.492 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETTSC
2026-01-29 01:36:49.492 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETTSC
2026-01-29 01:36:49.492 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETTSC
2026-01-29 01:36:49.492 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.28.20:5700) Recv TXTUNE cmd
2026-01-29 01:36:49.492 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETRXGAIN
2026-01-29 01:36:49.492 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETRXGAIN
2026-01-29 01:36:49.492 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETRXGAIN
2026-01-29 01:36:49.492 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETTSC
2026-01-29 01:36:49.492 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:36:49.492 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:36:49.492 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:36:49.492 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.28.20:5700) Recv NOMTXPOWER cmd
2026-01-29 01:36:49.492 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:36:49.492 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:36:49.492 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:36:49.492 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.28.20:5700) Recv POWERON CMD
2026-01-29 01:36:49.492 [INFO] ctrl_if_trx.py:109 (BTS@172.18.28.20:5700) Starting transceiver...
2026-01-29 01:36:49.492 [INFO] transceiver.py:243 Starting clock generator
2026-01-29 01:36:49.492 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-01-29 01:36:49.492 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:36:49.493 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:36:49.493 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:36:49.493 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETRXGAIN
2026-01-29 01:36:49.493 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:36:49.493 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:36:49.493 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 01:36:49.493 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:36:49.493 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:36:49.493 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:36:49.493 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 01:36:49.493 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:36:49.494 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:36:49.494 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:36:49.494 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 01:36:49.494 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:36:49.494 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:36:49.494 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:36:49.494 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 01:36:49.494 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:36:49.494 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:36:49.494 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:36:49.494 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 01:36:49.494 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:36:49.494 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 01:36:49.494 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 01:36:49.494 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 01:36:49.494 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 01:36:49.494 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 01:36:49.494 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 01:36:49.494 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 01:36:49.494 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.28.20:5700) Recv POWEROFF cmd
2026-01-29 01:36:49.494 [INFO] ctrl_if_trx.py:117 (BTS@172.18.28.20:5700) Stopping transceiver...
2026-01-29 01:36:49.494 [INFO] transceiver.py:246 Stopping clock generator
2026-01-29 01:36:54.497 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.28.20:5700) Recv POWEROFF cmd
2026-01-29 01:36:54.497 [INFO] ctrl_if_trx.py:117 (BTS@172.18.28.20:5700) Stopping transceiver...
2026-01-29 01:36:54.501 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 01:36:54.501 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 01:36:54.501 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 01:36:54.501 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 01:36:54.508 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 01:36:54.508 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.28.20:5700) Recv SETFORMAT cmd
2026-01-29 01:36:54.508 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.28.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 01:36:54.508 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.28.20:5700) Recv SETFORMAT cmd
2026-01-29 01:36:54.508 [INFO] ctrl_if_trx.py:201 (BTS@172.18.28.20:5700) TRXD header version 1 -> 1
2026-01-29 01:36:54.511 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.28.20:5700/1) Recv RXTUNE cmd
2026-01-29 01:36:54.511 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.28.20:5700/1) Recv TXTUNE cmd
2026-01-29 01:36:54.511 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.28.20:5700/1) Recv SETFORMAT cmd
2026-01-29 01:36:54.512 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.28.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 01:36:54.512 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 01:36:54.512 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.28.20:5700/1) Recv NOMTXPOWER cmd
2026-01-29 01:36:54.513 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.28.20:5700/1) Recv SETFORMAT cmd
2026-01-29 01:36:54.513 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.28.20:5700/1) TRXD header version 1 -> 1
2026-01-29 01:36:54.514 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.28.20:5700/2) Recv RXTUNE cmd
2026-01-29 01:36:54.514 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.28.20:5700/2) Recv TXTUNE cmd
2026-01-29 01:36:54.514 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.28.20:5700/2) Recv SETFORMAT cmd
2026-01-29 01:36:54.514 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.28.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 01:36:54.514 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 01:36:54.514 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.28.20:5700/2) Recv NOMTXPOWER cmd
2026-01-29 01:36:54.514 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.28.20:5700/2) Recv SETFORMAT cmd
2026-01-29 01:36:54.514 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.28.20:5700/2) TRXD header version 1 -> 1
2026-01-29 01:36:54.517 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.28.20:5700/3) Recv RXTUNE cmd
2026-01-29 01:36:54.517 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.28.20:5700/3) Recv TXTUNE cmd
2026-01-29 01:36:54.517 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.28.20:5700/3) Recv SETFORMAT cmd
2026-01-29 01:36:54.517 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.28.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 01:36:54.517 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 01:36:54.517 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.28.20:5700/3) Recv NOMTXPOWER cmd
2026-01-29 01:36:54.517 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.28.20:5700/3) Recv SETFORMAT cmd
2026-01-29 01:36:54.517 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.28.20:5700/3) TRXD header version 1 -> 1
2026-01-29 01:36:54.519 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.28.20:5700) Recv RXTUNE cmd
2026-01-29 01:36:54.519 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETTSC
2026-01-29 01:36:54.519 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETTSC
2026-01-29 01:36:54.520 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETTSC
2026-01-29 01:36:54.520 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.28.20:5700) Recv TXTUNE cmd
2026-01-29 01:36:54.520 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETRXGAIN
2026-01-29 01:36:54.520 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETRXGAIN
2026-01-29 01:36:54.520 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETRXGAIN
2026-01-29 01:36:54.520 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETTSC
2026-01-29 01:36:54.520 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:36:54.520 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:36:54.520 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:36:54.520 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.28.20:5700) Recv NOMTXPOWER cmd
2026-01-29 01:36:54.520 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:36:54.520 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:36:54.520 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:36:54.520 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.28.20:5700) Recv POWERON CMD
2026-01-29 01:36:54.520 [INFO] ctrl_if_trx.py:109 (BTS@172.18.28.20:5700) Starting transceiver...
2026-01-29 01:36:54.520 [INFO] transceiver.py:243 Starting clock generator
2026-01-29 01:36:54.521 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-01-29 01:36:54.521 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:36:54.521 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:36:54.521 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:36:54.521 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETRXGAIN
2026-01-29 01:36:54.521 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:36:54.521 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:36:54.521 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:36:54.521 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 01:36:54.521 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:36:54.521 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:36:54.521 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 01:36:54.521 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:36:54.521 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:36:54.521 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:36:54.521 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 01:36:54.521 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:36:54.521 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:36:54.521 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:36:54.521 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 01:36:54.522 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:36:54.522 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:36:54.522 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:36:54.522 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 01:36:54.522 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:36:54.522 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 01:36:54.522 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 01:36:54.522 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 01:36:54.525 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-01-29 01:36:55.006 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-01-29 01:36:55.049 [DEBUG] fake_trx.py:278 (BTS@172.18.28.20:5700) Recv FAKE_TOA cmd
2026-01-29 01:36:55.051 [DEBUG] fake_trx.py:297 (BTS@172.18.28.20:5700) Recv FAKE_RSSI cmd
2026-01-29 01:36:55.053 [DEBUG] fake_trx.py:322 (BTS@172.18.28.20:5700) Recv FAKE_CI cmd
2026-01-29 01:36:55.053 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:36:55.072 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 01:36:55.072 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 01:36:55.072 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 01:36:55.076 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 01:36:55.077 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 01:36:55.077 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 01:36:55.077 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.28.22:6700) Recv POWERON CMD
2026-01-29 01:36:55.077 [INFO] ctrl_if_trx.py:109 (MS@172.18.28.22:6700) Starting transceiver...
2026-01-29 01:36:55.101 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:36:55.107 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 01:36:55.107 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 01:36:55.107 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 01:36:55.107 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 01:36:55.484 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-01-29 01:36:55.523 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 01:36:55.523 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 01:36:55.524 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 01:36:55.526 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 01:36:55.961 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-01-29 01:36:56.440 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-01-29 01:36:56.524 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 01:36:56.524 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 01:36:56.524 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 01:36:56.528 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 01:36:56.918 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-01-29 01:36:57.395 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-01-29 01:36:57.524 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 01:36:57.525 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 01:36:57.525 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 01:36:57.528 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 01:36:57.873 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-01-29 01:36:58.351 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-01-29 01:36:58.526 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 01:36:58.526 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 01:36:58.526 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 01:36:58.529 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 01:36:58.829 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-01-29 01:36:59.163 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:36:59.166 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 01:36:59.167 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 01:36:59.167 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 01:36:59.185 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 01:36:59.185 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 01:36:59.185 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 01:36:59.188 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 01:36:59.188 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 01:36:59.188 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 01:36:59.188 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.28.22:6700) Recv POWERON CMD
2026-01-29 01:36:59.188 [INFO] ctrl_if_trx.py:109 (MS@172.18.28.22:6700) Starting transceiver...
2026-01-29 01:36:59.230 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:36:59.235 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 01:36:59.236 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 01:36:59.236 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 01:36:59.237 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 01:36:59.306 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-01-29 01:36:59.527 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 01:36:59.527 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 01:36:59.527 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 01:36:59.530 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 01:36:59.784 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-01-29 01:37:00.270 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-01-29 01:37:00.748 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-01-29 01:37:01.226 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-01-29 01:37:01.703 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-01-29 01:37:02.181 [DEBUG] clck_gen.py:113 IND CLOCK 1632
2026-01-29 01:37:02.659 [DEBUG] clck_gen.py:113 IND CLOCK 1734
2026-01-29 01:37:03.137 [DEBUG] clck_gen.py:113 IND CLOCK 1836
2026-01-29 01:37:03.491 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:37:03.494 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 01:37:03.494 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 01:37:03.494 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 01:37:03.504 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 01:37:03.504 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 01:37:03.504 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 01:37:03.505 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 01:37:03.505 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 01:37:03.505 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 01:37:03.505 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.28.22:6700) Recv POWERON CMD
2026-01-29 01:37:03.505 [INFO] ctrl_if_trx.py:109 (MS@172.18.28.22:6700) Starting transceiver...
2026-01-29 01:37:03.528 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:37:03.532 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 01:37:03.533 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 01:37:03.533 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 01:37:03.533 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 01:37:03.614 [DEBUG] clck_gen.py:113 IND CLOCK 1938
2026-01-29 01:37:04.092 [DEBUG] clck_gen.py:113 IND CLOCK 2040
2026-01-29 01:37:04.569 [DEBUG] clck_gen.py:113 IND CLOCK 2142
2026-01-29 01:37:05.047 [DEBUG] clck_gen.py:113 IND CLOCK 2244
2026-01-29 01:37:05.525 [DEBUG] clck_gen.py:113 IND CLOCK 2346
2026-01-29 01:37:06.003 [DEBUG] clck_gen.py:113 IND CLOCK 2448
2026-01-29 01:37:06.480 [DEBUG] clck_gen.py:113 IND CLOCK 2550
2026-01-29 01:37:06.958 [DEBUG] clck_gen.py:113 IND CLOCK 2652
2026-01-29 01:37:07.436 [DEBUG] clck_gen.py:113 IND CLOCK 2754
2026-01-29 01:37:07.530 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:37:07.533 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 01:37:07.533 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 01:37:07.533 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 01:37:07.550 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 01:37:07.550 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 01:37:07.551 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 01:37:07.552 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 01:37:07.552 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 01:37:07.553 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 01:37:07.553 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.28.22:6700) Recv POWERON CMD
2026-01-29 01:37:07.553 [INFO] ctrl_if_trx.py:109 (MS@172.18.28.22:6700) Starting transceiver...
2026-01-29 01:37:07.594 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:37:07.599 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 01:37:07.600 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 01:37:07.600 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 01:37:07.600 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 01:37:07.913 [DEBUG] clck_gen.py:113 IND CLOCK 2856
2026-01-29 01:37:08.390 [DEBUG] clck_gen.py:113 IND CLOCK 2958
2026-01-29 01:37:08.867 [DEBUG] clck_gen.py:113 IND CLOCK 3060
2026-01-29 01:37:09.344 [DEBUG] clck_gen.py:113 IND CLOCK 3162
2026-01-29 01:37:09.821 [DEBUG] clck_gen.py:113 IND CLOCK 3264
2026-01-29 01:37:10.298 [DEBUG] clck_gen.py:113 IND CLOCK 3366
2026-01-29 01:37:10.776 [DEBUG] clck_gen.py:113 IND CLOCK 3468
2026-01-29 01:37:11.254 [DEBUG] clck_gen.py:113 IND CLOCK 3570
2026-01-29 01:37:11.732 [DEBUG] clck_gen.py:113 IND CLOCK 3672
2026-01-29 01:37:11.846 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:37:11.848 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 01:37:11.849 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 01:37:11.849 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 01:37:11.855 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 01:37:11.855 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 01:37:11.855 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 01:37:11.857 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 01:37:11.857 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 01:37:11.857 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 01:37:11.857 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.28.22:6700) Recv POWERON CMD
2026-01-29 01:37:11.857 [INFO] ctrl_if_trx.py:109 (MS@172.18.28.22:6700) Starting transceiver...
2026-01-29 01:37:11.898 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:37:11.903 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 01:37:11.904 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 01:37:11.904 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 01:37:11.904 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 01:37:12.209 [DEBUG] clck_gen.py:113 IND CLOCK 3774
2026-01-29 01:37:12.687 [DEBUG] clck_gen.py:113 IND CLOCK 3876
2026-01-29 01:37:13.166 [DEBUG] clck_gen.py:113 IND CLOCK 3978
2026-01-29 01:37:13.643 [DEBUG] clck_gen.py:113 IND CLOCK 4080
2026-01-29 01:37:14.121 [DEBUG] clck_gen.py:113 IND CLOCK 4182
2026-01-29 01:37:14.599 [DEBUG] clck_gen.py:113 IND CLOCK 4284
2026-01-29 01:37:15.076 [DEBUG] clck_gen.py:113 IND CLOCK 4386
2026-01-29 01:37:15.554 [DEBUG] clck_gen.py:113 IND CLOCK 4488
2026-01-29 01:37:16.032 [DEBUG] clck_gen.py:113 IND CLOCK 4590
2026-01-29 01:37:16.510 [DEBUG] clck_gen.py:113 IND CLOCK 4692
2026-01-29 01:37:16.516 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:37:16.518 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 01:37:16.519 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 01:37:16.519 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 01:37:16.537 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 01:37:16.537 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 01:37:16.538 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 01:37:16.540 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 01:37:16.540 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 01:37:16.540 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 01:37:16.540 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.28.22:6700) Recv POWERON CMD
2026-01-29 01:37:16.540 [INFO] ctrl_if_trx.py:109 (MS@172.18.28.22:6700) Starting transceiver...
2026-01-29 01:37:16.582 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:37:16.587 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 01:37:16.588 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 01:37:16.588 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 01:37:16.589 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 01:37:16.987 [DEBUG] clck_gen.py:113 IND CLOCK 4794
2026-01-29 01:37:17.466 [DEBUG] clck_gen.py:113 IND CLOCK 4896
2026-01-29 01:37:17.944 [DEBUG] clck_gen.py:113 IND CLOCK 4998
2026-01-29 01:37:18.422 [DEBUG] clck_gen.py:113 IND CLOCK 5100
2026-01-29 01:37:18.900 [DEBUG] clck_gen.py:113 IND CLOCK 5202
2026-01-29 01:37:19.378 [DEBUG] clck_gen.py:113 IND CLOCK 5304
2026-01-29 01:37:19.855 [DEBUG] clck_gen.py:113 IND CLOCK 5406
2026-01-29 01:37:20.333 [DEBUG] clck_gen.py:113 IND CLOCK 5508
2026-01-29 01:37:20.812 [DEBUG] clck_gen.py:113 IND CLOCK 5610
2026-01-29 01:37:20.966 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:37:20.968 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 01:37:20.969 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 01:37:20.969 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 01:37:20.986 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 01:37:20.986 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 01:37:20.987 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 01:37:20.988 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 01:37:20.988 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 01:37:20.989 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 01:37:20.989 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.28.22:6700) Recv POWERON CMD
2026-01-29 01:37:20.989 [INFO] ctrl_if_trx.py:109 (MS@172.18.28.22:6700) Starting transceiver...
2026-01-29 01:37:21.030 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:37:21.035 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 01:37:21.036 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 01:37:21.036 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 01:37:21.037 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 01:37:21.289 [DEBUG] clck_gen.py:113 IND CLOCK 5712
2026-01-29 01:37:21.767 [DEBUG] clck_gen.py:113 IND CLOCK 5814
2026-01-29 01:37:22.245 [DEBUG] clck_gen.py:113 IND CLOCK 5916
2026-01-29 01:37:22.721 [DEBUG] clck_gen.py:113 IND CLOCK 6018
2026-01-29 01:37:23.199 [DEBUG] clck_gen.py:113 IND CLOCK 6120
2026-01-29 01:37:23.676 [DEBUG] clck_gen.py:113 IND CLOCK 6222
2026-01-29 01:37:24.154 [DEBUG] clck_gen.py:113 IND CLOCK 6324
2026-01-29 01:37:24.632 [DEBUG] clck_gen.py:113 IND CLOCK 6426
2026-01-29 01:37:25.110 [DEBUG] clck_gen.py:113 IND CLOCK 6528
2026-01-29 01:37:25.411 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:37:25.413 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 01:37:25.414 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 01:37:25.414 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 01:37:25.436 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 01:37:25.436 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 01:37:25.436 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 01:37:25.439 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 01:37:25.440 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 01:37:25.440 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 01:37:25.440 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.28.22:6700) Recv POWERON CMD
2026-01-29 01:37:25.440 [INFO] ctrl_if_trx.py:109 (MS@172.18.28.22:6700) Starting transceiver...
2026-01-29 01:37:25.486 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 01:37:25.487 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:37:25.491 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 01:37:25.492 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 01:37:25.492 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 01:37:25.492 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 01:37:25.587 [DEBUG] clck_gen.py:113 IND CLOCK 6630
2026-01-29 01:37:26.065 [DEBUG] clck_gen.py:113 IND CLOCK 6732
2026-01-29 01:37:26.543 [DEBUG] clck_gen.py:113 IND CLOCK 6834
2026-01-29 01:37:27.021 [DEBUG] clck_gen.py:113 IND CLOCK 6936
2026-01-29 01:37:27.499 [DEBUG] clck_gen.py:113 IND CLOCK 7038
2026-01-29 01:37:27.978 [DEBUG] clck_gen.py:113 IND CLOCK 7140
2026-01-29 01:37:28.455 [DEBUG] clck_gen.py:113 IND CLOCK 7242
2026-01-29 01:37:28.933 [DEBUG] clck_gen.py:113 IND CLOCK 7344
2026-01-29 01:37:29.410 [DEBUG] clck_gen.py:113 IND CLOCK 7446
2026-01-29 01:37:29.852 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:37:29.855 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 01:37:29.856 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 01:37:29.856 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 01:37:29.865 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 01:37:29.865 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 01:37:29.866 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 01:37:29.867 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 01:37:29.867 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 01:37:29.867 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 01:37:29.867 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.28.22:6700) Recv POWERON CMD
2026-01-29 01:37:29.867 [INFO] ctrl_if_trx.py:109 (MS@172.18.28.22:6700) Starting transceiver...
2026-01-29 01:37:29.887 [DEBUG] clck_gen.py:113 IND CLOCK 7548
2026-01-29 01:37:29.911 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:37:29.915 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 01:37:29.916 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 01:37:29.916 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 01:37:29.916 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 01:37:30.365 [DEBUG] clck_gen.py:113 IND CLOCK 7650
2026-01-29 01:37:30.844 [DEBUG] clck_gen.py:113 IND CLOCK 7752
2026-01-29 01:37:31.321 [DEBUG] clck_gen.py:113 IND CLOCK 7854
2026-01-29 01:37:31.799 [DEBUG] clck_gen.py:113 IND CLOCK 7956
2026-01-29 01:37:32.277 [DEBUG] clck_gen.py:113 IND CLOCK 8058
2026-01-29 01:37:32.755 [DEBUG] clck_gen.py:113 IND CLOCK 8160
2026-01-29 01:37:33.234 [DEBUG] clck_gen.py:113 IND CLOCK 8262
2026-01-29 01:37:33.712 [DEBUG] clck_gen.py:113 IND CLOCK 8364
2026-01-29 01:37:34.190 [DEBUG] clck_gen.py:113 IND CLOCK 8466
2026-01-29 01:37:34.296 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:37:34.298 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 01:37:34.299 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 01:37:34.299 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 01:37:34.311 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 01:37:34.311 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 01:37:34.311 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 01:37:34.313 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 01:37:34.313 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 01:37:34.313 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 01:37:34.313 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.28.22:6700) Recv POWERON CMD
2026-01-29 01:37:34.313 [INFO] ctrl_if_trx.py:109 (MS@172.18.28.22:6700) Starting transceiver...
2026-01-29 01:37:34.354 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 01:37:34.355 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:37:34.360 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 01:37:34.361 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 01:37:34.361 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 01:37:34.361 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 01:37:34.667 [DEBUG] clck_gen.py:113 IND CLOCK 8568
2026-01-29 01:37:35.144 [DEBUG] clck_gen.py:113 IND CLOCK 8670
2026-01-29 01:37:35.621 [DEBUG] clck_gen.py:113 IND CLOCK 8772
2026-01-29 01:37:36.099 [DEBUG] clck_gen.py:113 IND CLOCK 8874
2026-01-29 01:37:36.576 [DEBUG] clck_gen.py:113 IND CLOCK 8976
2026-01-29 01:37:37.054 [DEBUG] clck_gen.py:113 IND CLOCK 9078
2026-01-29 01:37:37.532 [DEBUG] clck_gen.py:113 IND CLOCK 9180
2026-01-29 01:37:38.010 [DEBUG] clck_gen.py:113 IND CLOCK 9282
2026-01-29 01:37:38.488 [DEBUG] clck_gen.py:113 IND CLOCK 9384
2026-01-29 01:37:38.965 [DEBUG] clck_gen.py:113 IND CLOCK 9486
2026-01-29 01:37:39.443 [DEBUG] clck_gen.py:113 IND CLOCK 9588
2026-01-29 01:37:39.600 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:37:39.603 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 01:37:39.603 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 01:37:39.603 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 01:37:39.621 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 01:37:39.621 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 01:37:39.621 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 01:37:39.624 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 01:37:39.624 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 01:37:39.624 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 01:37:39.624 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.28.22:6700) Recv POWERON CMD
2026-01-29 01:37:39.624 [INFO] ctrl_if_trx.py:109 (MS@172.18.28.22:6700) Starting transceiver...
2026-01-29 01:37:39.680 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:37:39.685 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 01:37:39.685 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 01:37:39.685 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 01:37:39.686 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 01:37:39.921 [DEBUG] clck_gen.py:113 IND CLOCK 9690
2026-01-29 01:37:40.400 [DEBUG] clck_gen.py:113 IND CLOCK 9792
2026-01-29 01:37:40.878 [DEBUG] clck_gen.py:113 IND CLOCK 9894
2026-01-29 01:37:41.356 [DEBUG] clck_gen.py:113 IND CLOCK 9996
2026-01-29 01:37:41.834 [DEBUG] clck_gen.py:113 IND CLOCK 10098
2026-01-29 01:37:42.312 [DEBUG] clck_gen.py:113 IND CLOCK 10200
2026-01-29 01:37:42.790 [DEBUG] clck_gen.py:113 IND CLOCK 10302
2026-01-29 01:37:43.268 [DEBUG] clck_gen.py:113 IND CLOCK 10404
2026-01-29 01:37:43.746 [DEBUG] clck_gen.py:113 IND CLOCK 10506
2026-01-29 01:37:44.224 [DEBUG] clck_gen.py:113 IND CLOCK 10608
2026-01-29 01:37:44.471 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:37:44.474 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 01:37:44.474 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 01:37:44.475 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 01:37:44.489 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 01:37:44.489 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 01:37:44.489 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 01:37:44.491 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 01:37:44.491 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 01:37:44.491 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 01:37:44.492 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.28.22:6700) Recv POWERON CMD
2026-01-29 01:37:44.492 [INFO] ctrl_if_trx.py:109 (MS@172.18.28.22:6700) Starting transceiver...
2026-01-29 01:37:44.534 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:37:44.540 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 01:37:44.540 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 01:37:44.540 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 01:37:44.541 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 01:37:44.702 [DEBUG] clck_gen.py:113 IND CLOCK 10710
2026-01-29 01:37:45.180 [DEBUG] clck_gen.py:113 IND CLOCK 10812
2026-01-29 01:37:45.658 [DEBUG] clck_gen.py:113 IND CLOCK 10914
2026-01-29 01:37:46.136 [DEBUG] clck_gen.py:113 IND CLOCK 11016
2026-01-29 01:37:46.613 [DEBUG] clck_gen.py:113 IND CLOCK 11118
2026-01-29 01:37:47.091 [DEBUG] clck_gen.py:113 IND CLOCK 11220
2026-01-29 01:37:47.569 [DEBUG] clck_gen.py:113 IND CLOCK 11322
2026-01-29 01:37:48.048 [DEBUG] clck_gen.py:113 IND CLOCK 11424
2026-01-29 01:37:48.526 [DEBUG] clck_gen.py:113 IND CLOCK 11526
2026-01-29 01:37:48.916 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:37:48.919 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 01:37:48.919 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 01:37:48.919 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 01:37:48.934 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 01:37:48.934 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 01:37:48.934 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 01:37:48.936 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 01:37:48.936 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 01:37:48.936 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 01:37:48.936 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.28.22:6700) Recv POWERON CMD
2026-01-29 01:37:48.936 [INFO] ctrl_if_trx.py:109 (MS@172.18.28.22:6700) Starting transceiver...
2026-01-29 01:37:48.978 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:37:48.983 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 01:37:48.984 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 01:37:48.984 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 01:37:48.985 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 01:37:49.004 [DEBUG] clck_gen.py:113 IND CLOCK 11628
2026-01-29 01:37:49.482 [DEBUG] clck_gen.py:113 IND CLOCK 11730
2026-01-29 01:37:49.961 [DEBUG] clck_gen.py:113 IND CLOCK 11832
2026-01-29 01:37:50.438 [DEBUG] clck_gen.py:113 IND CLOCK 11934
2026-01-29 01:37:50.916 [DEBUG] clck_gen.py:113 IND CLOCK 12036
2026-01-29 01:37:51.394 [DEBUG] clck_gen.py:113 IND CLOCK 12138
2026-01-29 01:37:51.872 [DEBUG] clck_gen.py:113 IND CLOCK 12240
2026-01-29 01:37:52.350 [DEBUG] clck_gen.py:113 IND CLOCK 12342
2026-01-29 01:37:52.828 [DEBUG] clck_gen.py:113 IND CLOCK 12444
2026-01-29 01:37:53.118 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:37:53.121 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 01:37:53.121 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 01:37:53.121 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 01:37:53.138 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 01:37:53.138 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 01:37:53.138 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 01:37:53.140 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 01:37:53.140 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 01:37:53.140 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 01:37:53.140 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.28.22:6700) Recv POWERON CMD
2026-01-29 01:37:53.140 [INFO] ctrl_if_trx.py:109 (MS@172.18.28.22:6700) Starting transceiver...
2026-01-29 01:37:53.182 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:37:53.187 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 01:37:53.188 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 01:37:53.189 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 01:37:53.189 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 01:37:53.305 [DEBUG] clck_gen.py:113 IND CLOCK 12546
2026-01-29 01:37:53.782 [DEBUG] clck_gen.py:113 IND CLOCK 12648
2026-01-29 01:37:54.260 [DEBUG] clck_gen.py:113 IND CLOCK 12750
2026-01-29 01:37:54.738 [DEBUG] clck_gen.py:113 IND CLOCK 12852
2026-01-29 01:37:55.216 [DEBUG] clck_gen.py:113 IND CLOCK 12954
2026-01-29 01:37:55.694 [DEBUG] clck_gen.py:113 IND CLOCK 13056
2026-01-29 01:37:56.172 [DEBUG] clck_gen.py:113 IND CLOCK 13158
2026-01-29 01:37:56.645 [DEBUG] clck_gen.py:113 IND CLOCK 13260
2026-01-29 01:37:57.122 [DEBUG] clck_gen.py:113 IND CLOCK 13362
2026-01-29 01:37:57.435 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:37:57.438 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 01:37:57.439 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 01:37:57.439 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 01:37:57.459 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 01:37:57.459 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 01:37:57.459 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 01:37:57.461 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 01:37:57.461 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 01:37:57.461 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 01:37:57.461 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.28.22:6700) Recv POWERON CMD
2026-01-29 01:37:57.461 [INFO] ctrl_if_trx.py:109 (MS@172.18.28.22:6700) Starting transceiver...
2026-01-29 01:37:57.502 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:37:57.508 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 01:37:57.508 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 01:37:57.508 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 01:37:57.508 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 01:37:57.600 [DEBUG] clck_gen.py:113 IND CLOCK 13464
2026-01-29 01:37:58.078 [DEBUG] clck_gen.py:113 IND CLOCK 13566
2026-01-29 01:37:58.554 [DEBUG] clck_gen.py:113 IND CLOCK 13668
2026-01-29 01:37:59.032 [DEBUG] clck_gen.py:113 IND CLOCK 13770
2026-01-29 01:37:59.510 [DEBUG] clck_gen.py:113 IND CLOCK 13872
2026-01-29 01:37:59.988 [DEBUG] clck_gen.py:113 IND CLOCK 13974
2026-01-29 01:38:00.465 [DEBUG] clck_gen.py:113 IND CLOCK 14076
2026-01-29 01:38:00.943 [DEBUG] clck_gen.py:113 IND CLOCK 14178
2026-01-29 01:38:01.421 [DEBUG] clck_gen.py:113 IND CLOCK 14280
2026-01-29 01:38:01.748 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:38:01.751 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 01:38:01.752 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 01:38:01.752 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 01:38:01.771 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 01:38:01.771 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 01:38:01.771 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 01:38:01.773 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 01:38:01.773 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 01:38:01.773 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 01:38:01.773 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.28.22:6700) Recv POWERON CMD
2026-01-29 01:38:01.773 [INFO] ctrl_if_trx.py:109 (MS@172.18.28.22:6700) Starting transceiver...
2026-01-29 01:38:01.818 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:38:01.823 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 01:38:01.824 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 01:38:01.824 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 01:38:01.824 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 01:38:01.898 [DEBUG] clck_gen.py:113 IND CLOCK 14382
2026-01-29 01:38:02.375 [DEBUG] clck_gen.py:113 IND CLOCK 14484
2026-01-29 01:38:02.852 [DEBUG] clck_gen.py:113 IND CLOCK 14586
2026-01-29 01:38:03.330 [DEBUG] clck_gen.py:113 IND CLOCK 14688
2026-01-29 01:38:03.807 [DEBUG] clck_gen.py:113 IND CLOCK 14790
2026-01-29 01:38:04.284 [DEBUG] clck_gen.py:113 IND CLOCK 14892
2026-01-29 01:38:04.762 [DEBUG] clck_gen.py:113 IND CLOCK 14994
2026-01-29 01:38:05.237 [DEBUG] clck_gen.py:113 IND CLOCK 15096
2026-01-29 01:38:05.713 [DEBUG] clck_gen.py:113 IND CLOCK 15198
2026-01-29 01:38:06.065 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:38:06.067 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 01:38:06.068 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 01:38:06.068 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 01:38:06.081 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 01:38:06.082 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 01:38:06.082 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 01:38:06.084 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 01:38:06.084 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 01:38:06.084 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 01:38:06.084 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.28.22:6700) Recv POWERON CMD
2026-01-29 01:38:06.084 [INFO] ctrl_if_trx.py:109 (MS@172.18.28.22:6700) Starting transceiver...
2026-01-29 01:38:06.134 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:38:06.139 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 01:38:06.139 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 01:38:06.139 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 01:38:06.140 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 01:38:06.191 [DEBUG] clck_gen.py:113 IND CLOCK 15300
2026-01-29 01:38:06.669 [DEBUG] clck_gen.py:113 IND CLOCK 15402
2026-01-29 01:38:07.148 [DEBUG] clck_gen.py:113 IND CLOCK 15504
2026-01-29 01:38:07.625 [DEBUG] clck_gen.py:113 IND CLOCK 15606
2026-01-29 01:38:08.103 [DEBUG] clck_gen.py:113 IND CLOCK 15708
2026-01-29 01:38:08.580 [DEBUG] clck_gen.py:113 IND CLOCK 15810
2026-01-29 01:38:09.058 [DEBUG] clck_gen.py:113 IND CLOCK 15912
2026-01-29 01:38:09.536 [DEBUG] clck_gen.py:113 IND CLOCK 16014
2026-01-29 01:38:10.014 [DEBUG] clck_gen.py:113 IND CLOCK 16116
2026-01-29 01:38:10.491 [DEBUG] clck_gen.py:113 IND CLOCK 16218
2026-01-29 01:38:10.540 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:38:10.542 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 01:38:10.543 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 01:38:10.543 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 01:38:10.560 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 01:38:10.560 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 01:38:10.560 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 01:38:10.561 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 01:38:10.561 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 01:38:10.561 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 01:38:10.562 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.28.22:6700) Recv POWERON CMD
2026-01-29 01:38:10.562 [INFO] ctrl_if_trx.py:109 (MS@172.18.28.22:6700) Starting transceiver...
2026-01-29 01:38:10.602 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:38:10.607 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 01:38:10.608 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 01:38:10.608 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 01:38:10.608 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 01:38:10.969 [DEBUG] clck_gen.py:113 IND CLOCK 16320
2026-01-29 01:38:11.447 [DEBUG] clck_gen.py:113 IND CLOCK 16422
2026-01-29 01:38:11.924 [DEBUG] clck_gen.py:113 IND CLOCK 16524
2026-01-29 01:38:12.403 [DEBUG] clck_gen.py:113 IND CLOCK 16626
2026-01-29 01:38:12.881 [DEBUG] clck_gen.py:113 IND CLOCK 16728
2026-01-29 01:38:13.359 [DEBUG] clck_gen.py:113 IND CLOCK 16830
2026-01-29 01:38:13.837 [DEBUG] clck_gen.py:113 IND CLOCK 16932
2026-01-29 01:38:14.315 [DEBUG] clck_gen.py:113 IND CLOCK 17034
2026-01-29 01:38:14.793 [DEBUG] clck_gen.py:113 IND CLOCK 17136
2026-01-29 01:38:14.858 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:38:14.861 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 01:38:14.861 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 01:38:14.861 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 01:38:14.880 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 01:38:14.880 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 01:38:14.880 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 01:38:14.882 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 01:38:14.882 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 01:38:14.882 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 01:38:14.882 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.28.22:6700) Recv POWERON CMD
2026-01-29 01:38:14.882 [INFO] ctrl_if_trx.py:109 (MS@172.18.28.22:6700) Starting transceiver...
2026-01-29 01:38:14.932 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:38:14.937 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 01:38:14.938 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 01:38:14.938 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 01:38:14.938 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 01:38:15.271 [DEBUG] clck_gen.py:113 IND CLOCK 17238
2026-01-29 01:38:15.749 [DEBUG] clck_gen.py:113 IND CLOCK 17340
2026-01-29 01:38:16.227 [DEBUG] clck_gen.py:113 IND CLOCK 17442
2026-01-29 01:38:16.705 [DEBUG] clck_gen.py:113 IND CLOCK 17544
2026-01-29 01:38:17.183 [DEBUG] clck_gen.py:113 IND CLOCK 17646
2026-01-29 01:38:17.661 [DEBUG] clck_gen.py:113 IND CLOCK 17748
2026-01-29 01:38:18.139 [DEBUG] clck_gen.py:113 IND CLOCK 17850
2026-01-29 01:38:18.617 [DEBUG] clck_gen.py:113 IND CLOCK 17952
2026-01-29 01:38:19.094 [DEBUG] clck_gen.py:113 IND CLOCK 18054
2026-01-29 01:38:19.178 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:38:19.180 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 01:38:19.181 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 01:38:19.181 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 01:38:19.198 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 01:38:19.198 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 01:38:19.198 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 01:38:19.200 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 01:38:19.200 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 01:38:19.200 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 01:38:19.200 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.28.22:6700) Recv POWERON CMD
2026-01-29 01:38:19.200 [INFO] ctrl_if_trx.py:109 (MS@172.18.28.22:6700) Starting transceiver...
2026-01-29 01:38:19.247 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:38:19.252 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 01:38:19.253 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 01:38:19.253 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 01:38:19.253 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 01:38:19.572 [DEBUG] clck_gen.py:113 IND CLOCK 18156
2026-01-29 01:38:20.050 [DEBUG] clck_gen.py:113 IND CLOCK 18258
2026-01-29 01:38:20.527 [DEBUG] clck_gen.py:113 IND CLOCK 18360
2026-01-29 01:38:21.005 [DEBUG] clck_gen.py:113 IND CLOCK 18462
2026-01-29 01:38:21.483 [DEBUG] clck_gen.py:113 IND CLOCK 18564
2026-01-29 01:38:21.960 [DEBUG] clck_gen.py:113 IND CLOCK 18666
2026-01-29 01:38:22.437 [DEBUG] clck_gen.py:113 IND CLOCK 18768
2026-01-29 01:38:22.914 [DEBUG] clck_gen.py:113 IND CLOCK 18870
2026-01-29 01:38:23.391 [DEBUG] clck_gen.py:113 IND CLOCK 18972
2026-01-29 01:38:23.497 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:38:23.500 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 01:38:23.500 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 01:38:23.500 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 01:38:23.514 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 01:38:23.515 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 01:38:23.515 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 01:38:23.515 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 01:38:23.517 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 01:38:23.517 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 01:38:23.517 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 01:38:23.517 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 01:38:23.517 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.28.20:5700) Recv POWEROFF cmd
2026-01-29 01:38:23.517 [INFO] ctrl_if_trx.py:117 (BTS@172.18.28.20:5700) Stopping transceiver...
2026-01-29 01:38:23.517 [INFO] transceiver.py:246 Stopping clock generator
2026-01-29 01:38:23.517 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=19000 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 01:38:23.517 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=19000 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 01:38:23.517 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=19000 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 01:38:28.518 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.28.20:5700) Recv POWEROFF cmd
2026-01-29 01:38:28.518 [INFO] ctrl_if_trx.py:117 (BTS@172.18.28.20:5700) Stopping transceiver...
2026-01-29 01:38:28.523 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 01:38:28.523 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 01:38:28.523 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 01:38:28.524 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 01:38:28.533 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 01:38:28.533 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.28.20:5700) Recv SETFORMAT cmd
2026-01-29 01:38:28.533 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.28.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 01:38:28.534 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.28.20:5700) Recv SETFORMAT cmd
2026-01-29 01:38:28.534 [INFO] ctrl_if_trx.py:201 (BTS@172.18.28.20:5700) TRXD header version 1 -> 1
2026-01-29 01:38:28.535 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.28.20:5700/1) Recv RXTUNE cmd
2026-01-29 01:38:28.535 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.28.20:5700/1) Recv TXTUNE cmd
2026-01-29 01:38:28.535 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.28.20:5700/1) Recv SETFORMAT cmd
2026-01-29 01:38:28.535 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.28.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 01:38:28.535 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 01:38:28.536 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.28.20:5700/1) Recv NOMTXPOWER cmd
2026-01-29 01:38:28.536 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.28.20:5700/1) Recv SETFORMAT cmd
2026-01-29 01:38:28.536 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.28.20:5700/1) TRXD header version 1 -> 1
2026-01-29 01:38:28.537 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.28.20:5700/2) Recv RXTUNE cmd
2026-01-29 01:38:28.537 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.28.20:5700/2) Recv TXTUNE cmd
2026-01-29 01:38:28.537 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.28.20:5700/2) Recv SETFORMAT cmd
2026-01-29 01:38:28.537 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.28.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 01:38:28.537 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 01:38:28.537 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.28.20:5700/2) Recv NOMTXPOWER cmd
2026-01-29 01:38:28.537 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.28.20:5700/2) Recv SETFORMAT cmd
2026-01-29 01:38:28.537 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.28.20:5700/2) TRXD header version 1 -> 1
2026-01-29 01:38:28.538 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.28.20:5700/3) Recv RXTUNE cmd
2026-01-29 01:38:28.538 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.28.20:5700/3) Recv TXTUNE cmd
2026-01-29 01:38:28.538 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.28.20:5700/3) Recv SETFORMAT cmd
2026-01-29 01:38:28.538 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.28.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 01:38:28.538 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 01:38:28.538 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.28.20:5700/3) Recv NOMTXPOWER cmd
2026-01-29 01:38:28.538 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.28.20:5700/3) Recv SETFORMAT cmd
2026-01-29 01:38:28.538 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.28.20:5700/3) TRXD header version 1 -> 1
2026-01-29 01:38:28.540 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.28.20:5700) Recv RXTUNE cmd
2026-01-29 01:38:28.540 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETTSC
2026-01-29 01:38:28.540 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETTSC
2026-01-29 01:38:28.540 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETTSC
2026-01-29 01:38:28.540 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.28.20:5700) Recv TXTUNE cmd
2026-01-29 01:38:28.540 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETRXGAIN
2026-01-29 01:38:28.540 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETRXGAIN
2026-01-29 01:38:28.540 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETRXGAIN
2026-01-29 01:38:28.540 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETTSC
2026-01-29 01:38:28.540 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:38:28.540 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:38:28.540 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:38:28.540 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.28.20:5700) Recv NOMTXPOWER cmd
2026-01-29 01:38:28.540 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:38:28.540 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:38:28.540 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:38:28.540 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.28.20:5700) Recv POWERON CMD
2026-01-29 01:38:28.540 [INFO] ctrl_if_trx.py:109 (BTS@172.18.28.20:5700) Starting transceiver...
2026-01-29 01:38:28.540 [INFO] transceiver.py:243 Starting clock generator
2026-01-29 01:38:28.540 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-01-29 01:38:28.540 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:38:28.540 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:38:28.540 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:38:28.540 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETRXGAIN
2026-01-29 01:38:28.540 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:38:28.540 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:38:28.540 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 01:38:28.540 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:38:28.541 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:38:28.541 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:38:28.541 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 01:38:28.541 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:38:28.541 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:38:28.541 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:38:28.541 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 01:38:28.541 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:38:28.541 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:38:28.541 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:38:28.541 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 01:38:28.541 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:38:28.541 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:38:28.541 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 01:38:28.541 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:38:28.541 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 01:38:28.541 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 01:38:28.542 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:38:28.542 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 01:38:28.542 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 01:38:28.542 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 01:38:28.542 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 01:38:28.542 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 01:38:28.542 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.28.20:5700) Recv POWEROFF cmd
2026-01-29 01:38:28.542 [INFO] ctrl_if_trx.py:117 (BTS@172.18.28.20:5700) Stopping transceiver...
2026-01-29 01:38:28.542 [INFO] transceiver.py:246 Stopping clock generator
2026-01-29 01:38:33.545 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.28.20:5700) Recv POWEROFF cmd
2026-01-29 01:38:33.545 [INFO] ctrl_if_trx.py:117 (BTS@172.18.28.20:5700) Stopping transceiver...
2026-01-29 01:38:33.547 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 01:38:33.548 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 01:38:33.548 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 01:38:33.549 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 01:38:33.551 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 01:38:33.551 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.28.20:5700) Recv SETFORMAT cmd
2026-01-29 01:38:33.551 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.28.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 01:38:33.551 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.28.20:5700) Recv SETFORMAT cmd
2026-01-29 01:38:33.551 [INFO] ctrl_if_trx.py:201 (BTS@172.18.28.20:5700) TRXD header version 1 -> 1
2026-01-29 01:38:33.552 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.28.20:5700/1) Recv RXTUNE cmd
2026-01-29 01:38:33.552 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.28.20:5700/1) Recv TXTUNE cmd
2026-01-29 01:38:33.552 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.28.20:5700/1) Recv SETFORMAT cmd
2026-01-29 01:38:33.552 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.28.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 01:38:33.552 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 01:38:33.553 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.28.20:5700/1) Recv NOMTXPOWER cmd
2026-01-29 01:38:33.553 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.28.20:5700/1) Recv SETFORMAT cmd
2026-01-29 01:38:33.553 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.28.20:5700/1) TRXD header version 1 -> 1
2026-01-29 01:38:33.553 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.28.20:5700/2) Recv RXTUNE cmd
2026-01-29 01:38:33.553 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.28.20:5700/2) Recv TXTUNE cmd
2026-01-29 01:38:33.553 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.28.20:5700/2) Recv SETFORMAT cmd
2026-01-29 01:38:33.553 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.28.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 01:38:33.553 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 01:38:33.553 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.28.20:5700/2) Recv NOMTXPOWER cmd
2026-01-29 01:38:33.553 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.28.20:5700/2) Recv SETFORMAT cmd
2026-01-29 01:38:33.553 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.28.20:5700/2) TRXD header version 1 -> 1
2026-01-29 01:38:33.554 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.28.20:5700/3) Recv RXTUNE cmd
2026-01-29 01:38:33.554 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.28.20:5700/3) Recv TXTUNE cmd
2026-01-29 01:38:33.554 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.28.20:5700/3) Recv SETFORMAT cmd
2026-01-29 01:38:33.554 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.28.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 01:38:33.554 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 01:38:33.554 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.28.20:5700/3) Recv NOMTXPOWER cmd
2026-01-29 01:38:33.554 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.28.20:5700/3) Recv SETFORMAT cmd
2026-01-29 01:38:33.554 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.28.20:5700/3) TRXD header version 1 -> 1
2026-01-29 01:38:33.556 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.28.20:5700) Recv RXTUNE cmd
2026-01-29 01:38:33.556 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETTSC
2026-01-29 01:38:33.556 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETTSC
2026-01-29 01:38:33.556 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETTSC
2026-01-29 01:38:33.556 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.28.20:5700) Recv TXTUNE cmd
2026-01-29 01:38:33.556 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETRXGAIN
2026-01-29 01:38:33.556 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETRXGAIN
2026-01-29 01:38:33.556 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETRXGAIN
2026-01-29 01:38:33.556 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETTSC
2026-01-29 01:38:33.556 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:38:33.556 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:38:33.556 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.28.20:5700) Recv NOMTXPOWER cmd
2026-01-29 01:38:33.556 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:38:33.556 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:38:33.556 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:38:33.556 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.28.20:5700) Recv POWERON CMD
2026-01-29 01:38:33.556 [INFO] ctrl_if_trx.py:109 (BTS@172.18.28.20:5700) Starting transceiver...
2026-01-29 01:38:33.556 [INFO] transceiver.py:243 Starting clock generator
2026-01-29 01:38:33.556 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-01-29 01:38:33.556 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:38:33.556 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:38:33.556 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:38:33.556 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETRXGAIN
2026-01-29 01:38:33.556 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:38:33.556 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:38:33.556 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:38:33.556 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 01:38:33.556 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:38:33.556 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:38:33.556 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:38:33.556 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 01:38:33.557 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:38:33.557 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:38:33.557 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:38:33.557 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 01:38:33.557 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:38:33.557 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:38:33.557 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:38:33.557 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 01:38:33.557 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:38:33.557 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:38:33.557 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:38:33.557 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 01:38:33.557 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:38:33.557 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 01:38:33.557 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 01:38:33.557 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 01:38:33.561 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-01-29 01:38:34.043 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-01-29 01:38:34.080 [DEBUG] fake_trx.py:278 (BTS@172.18.28.20:5700) Recv FAKE_TOA cmd
2026-01-29 01:38:34.082 [DEBUG] fake_trx.py:297 (BTS@172.18.28.20:5700) Recv FAKE_RSSI cmd
2026-01-29 01:38:34.083 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:38:34.084 [DEBUG] fake_trx.py:322 (BTS@172.18.28.20:5700) Recv FAKE_CI cmd
2026-01-29 01:38:34.109 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 01:38:34.109 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 01:38:34.110 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 01:38:34.118 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 01:38:34.118 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 01:38:34.118 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 01:38:34.118 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.28.22:6700) Recv POWERON CMD
2026-01-29 01:38:34.118 [INFO] ctrl_if_trx.py:109 (MS@172.18.28.22:6700) Starting transceiver...
2026-01-29 01:38:34.139 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:38:34.145 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 01:38:34.145 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 01:38:34.145 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 01:38:34.145 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 01:38:34.520 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-01-29 01:38:34.558 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 01:38:34.558 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 01:38:34.559 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 01:38:34.560 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 01:38:34.998 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-01-29 01:38:35.200 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:38:35.203 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 01:38:35.203 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 01:38:35.203 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 01:38:35.223 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 01:38:35.223 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 01:38:35.223 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 01:38:35.225 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 01:38:35.225 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 01:38:35.225 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 01:38:35.225 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.28.22:6700) Recv POWERON CMD
2026-01-29 01:38:35.225 [INFO] ctrl_if_trx.py:109 (MS@172.18.28.22:6700) Starting transceiver...
2026-01-29 01:38:35.267 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:38:35.272 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 01:38:35.272 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 01:38:35.273 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 01:38:35.273 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 01:38:35.473 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-01-29 01:38:35.559 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 01:38:35.560 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 01:38:35.560 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 01:38:35.561 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 01:38:35.950 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-01-29 01:38:36.428 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-01-29 01:38:36.560 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 01:38:36.560 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 01:38:36.561 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 01:38:36.562 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 01:38:36.649 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:38:36.652 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 01:38:36.653 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 01:38:36.653 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 01:38:36.666 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 01:38:36.666 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 01:38:36.666 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 01:38:36.669 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 01:38:36.669 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 01:38:36.669 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 01:38:36.669 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.28.22:6700) Recv POWERON CMD
2026-01-29 01:38:36.669 [INFO] ctrl_if_trx.py:109 (MS@172.18.28.22:6700) Starting transceiver...
2026-01-29 01:38:36.712 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:38:36.717 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 01:38:36.718 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 01:38:36.718 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 01:38:36.718 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 01:38:36.906 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-01-29 01:38:37.384 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-01-29 01:38:37.561 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 01:38:37.561 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 01:38:37.561 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 01:38:37.563 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 01:38:37.821 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:38:37.825 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 01:38:37.825 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 01:38:37.825 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 01:38:37.844 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 01:38:37.844 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 01:38:37.844 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 01:38:37.847 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 01:38:37.847 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 01:38:37.847 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 01:38:37.847 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.28.22:6700) Recv POWERON CMD
2026-01-29 01:38:37.847 [INFO] ctrl_if_trx.py:109 (MS@172.18.28.22:6700) Starting transceiver...
2026-01-29 01:38:37.861 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-01-29 01:38:37.890 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:38:37.896 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 01:38:37.896 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 01:38:37.896 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 01:38:37.896 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 01:38:38.338 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-01-29 01:38:38.562 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 01:38:38.563 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 01:38:38.563 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 01:38:38.564 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 01:38:38.815 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-01-29 01:38:39.271 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:38:39.273 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 01:38:39.274 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 01:38:39.274 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 01:38:39.286 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 01:38:39.286 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 01:38:39.286 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 01:38:39.289 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 01:38:39.289 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 01:38:39.289 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 01:38:39.289 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.28.22:6700) Recv POWERON CMD
2026-01-29 01:38:39.289 [INFO] ctrl_if_trx.py:109 (MS@172.18.28.22:6700) Starting transceiver...
2026-01-29 01:38:39.293 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-01-29 01:38:39.340 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:38:39.345 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 01:38:39.345 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 01:38:39.345 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 01:38:39.346 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 01:38:39.770 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-01-29 01:38:40.248 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-01-29 01:38:40.726 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-01-29 01:38:40.854 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:38:40.857 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 01:38:40.858 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 01:38:40.858 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 01:38:40.872 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 01:38:40.872 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 01:38:40.872 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 01:38:40.874 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 01:38:40.874 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 01:38:40.874 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 01:38:40.874 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.28.22:6700) Recv POWERON CMD
2026-01-29 01:38:40.874 [INFO] ctrl_if_trx.py:109 (MS@172.18.28.22:6700) Starting transceiver...
2026-01-29 01:38:40.918 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:38:40.923 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 01:38:40.924 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 01:38:40.924 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 01:38:40.924 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 01:38:41.204 [DEBUG] clck_gen.py:113 IND CLOCK 1632
2026-01-29 01:38:41.681 [DEBUG] clck_gen.py:113 IND CLOCK 1734
2026-01-29 01:38:42.159 [DEBUG] clck_gen.py:113 IND CLOCK 1836
2026-01-29 01:38:42.375 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:38:42.377 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 01:38:42.377 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 01:38:42.378 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 01:38:42.397 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 01:38:42.397 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 01:38:42.397 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 01:38:42.399 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 01:38:42.399 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 01:38:42.400 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 01:38:42.400 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.28.22:6700) Recv POWERON CMD
2026-01-29 01:38:42.400 [INFO] ctrl_if_trx.py:109 (MS@172.18.28.22:6700) Starting transceiver...
2026-01-29 01:38:42.443 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:38:42.448 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 01:38:42.448 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 01:38:42.449 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 01:38:42.449 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 01:38:42.637 [DEBUG] clck_gen.py:113 IND CLOCK 1938
2026-01-29 01:38:43.115 [DEBUG] clck_gen.py:113 IND CLOCK 2040
2026-01-29 01:38:43.593 [DEBUG] clck_gen.py:113 IND CLOCK 2142
2026-01-29 01:38:43.896 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:38:43.899 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 01:38:43.900 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 01:38:43.900 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 01:38:43.918 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 01:38:43.918 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 01:38:43.918 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 01:38:43.921 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 01:38:43.921 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 01:38:43.921 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 01:38:43.921 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.28.22:6700) Recv POWERON CMD
2026-01-29 01:38:43.921 [INFO] ctrl_if_trx.py:109 (MS@172.18.28.22:6700) Starting transceiver...
2026-01-29 01:38:43.968 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 01:38:43.969 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:38:43.974 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 01:38:43.974 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 01:38:43.975 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 01:38:43.975 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 01:38:44.070 [DEBUG] clck_gen.py:113 IND CLOCK 2244
2026-01-29 01:38:44.548 [DEBUG] clck_gen.py:113 IND CLOCK 2346
2026-01-29 01:38:45.026 [DEBUG] clck_gen.py:113 IND CLOCK 2448
2026-01-29 01:38:45.418 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:38:45.420 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 01:38:45.421 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 01:38:45.421 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 01:38:45.440 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 01:38:45.440 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 01:38:45.440 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 01:38:45.442 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 01:38:45.442 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 01:38:45.442 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 01:38:45.442 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.28.22:6700) Recv POWERON CMD
2026-01-29 01:38:45.442 [INFO] ctrl_if_trx.py:109 (MS@172.18.28.22:6700) Starting transceiver...
2026-01-29 01:38:45.499 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:38:45.503 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 01:38:45.504 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 01:38:45.504 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 01:38:45.504 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 01:38:45.504 [DEBUG] clck_gen.py:113 IND CLOCK 2550
2026-01-29 01:38:45.983 [DEBUG] clck_gen.py:113 IND CLOCK 2652
2026-01-29 01:38:46.460 [DEBUG] clck_gen.py:113 IND CLOCK 2754
2026-01-29 01:38:46.938 [DEBUG] clck_gen.py:113 IND CLOCK 2856
2026-01-29 01:38:46.939 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:38:46.941 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 01:38:46.942 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 01:38:46.942 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 01:38:46.959 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 01:38:46.959 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 01:38:46.959 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 01:38:46.961 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 01:38:46.961 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 01:38:46.961 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 01:38:46.961 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.28.22:6700) Recv POWERON CMD
2026-01-29 01:38:46.961 [INFO] ctrl_if_trx.py:109 (MS@172.18.28.22:6700) Starting transceiver...
2026-01-29 01:38:47.002 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 01:38:47.004 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:38:47.009 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 01:38:47.010 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 01:38:47.010 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 01:38:47.010 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 01:38:47.416 [DEBUG] clck_gen.py:113 IND CLOCK 2958
2026-01-29 01:38:47.893 [DEBUG] clck_gen.py:113 IND CLOCK 3060
2026-01-29 01:38:48.340 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:38:48.344 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 01:38:48.344 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 01:38:48.344 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 01:38:48.362 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 01:38:48.362 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 01:38:48.363 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 01:38:48.365 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 01:38:48.365 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 01:38:48.365 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 01:38:48.365 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.28.22:6700) Recv POWERON CMD
2026-01-29 01:38:48.365 [INFO] ctrl_if_trx.py:109 (MS@172.18.28.22:6700) Starting transceiver...
2026-01-29 01:38:48.371 [DEBUG] clck_gen.py:113 IND CLOCK 3162
2026-01-29 01:38:48.419 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:38:48.424 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 01:38:48.425 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 01:38:48.425 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 01:38:48.425 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 01:38:48.848 [DEBUG] clck_gen.py:113 IND CLOCK 3264
2026-01-29 01:38:49.326 [DEBUG] clck_gen.py:113 IND CLOCK 3366
2026-01-29 01:38:49.801 [DEBUG] clck_gen.py:113 IND CLOCK 3468
2026-01-29 01:38:49.801 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:38:49.805 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 01:38:49.805 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 01:38:49.806 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 01:38:49.824 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 01:38:49.824 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 01:38:49.824 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 01:38:49.826 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 01:38:49.826 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 01:38:49.826 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 01:38:49.826 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.28.22:6700) Recv POWERON CMD
2026-01-29 01:38:49.826 [INFO] ctrl_if_trx.py:109 (MS@172.18.28.22:6700) Starting transceiver...
2026-01-29 01:38:49.870 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:38:49.876 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 01:38:49.876 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 01:38:49.877 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 01:38:49.877 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 01:38:50.270 [DEBUG] clck_gen.py:113 IND CLOCK 3570
2026-01-29 01:38:50.742 [DEBUG] clck_gen.py:113 IND CLOCK 3672
2026-01-29 01:38:51.220 [DEBUG] clck_gen.py:113 IND CLOCK 3774
2026-01-29 01:38:51.312 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:38:51.315 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 01:38:51.316 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 01:38:51.316 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 01:38:51.330 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 01:38:51.330 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 01:38:51.330 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 01:38:51.333 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 01:38:51.333 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 01:38:51.333 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 01:38:51.333 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.28.22:6700) Recv POWERON CMD
2026-01-29 01:38:51.333 [INFO] ctrl_if_trx.py:109 (MS@172.18.28.22:6700) Starting transceiver...
2026-01-29 01:38:51.374 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:38:51.380 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 01:38:51.380 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 01:38:51.380 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 01:38:51.380 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 01:38:51.692 [DEBUG] clck_gen.py:113 IND CLOCK 3876
2026-01-29 01:38:52.166 [DEBUG] clck_gen.py:113 IND CLOCK 3978
2026-01-29 01:38:52.644 [DEBUG] clck_gen.py:113 IND CLOCK 4080
2026-01-29 01:38:52.800 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:38:52.803 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 01:38:52.804 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 01:38:52.804 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 01:38:52.813 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 01:38:52.813 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 01:38:52.813 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 01:38:52.815 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 01:38:52.815 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 01:38:52.815 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 01:38:52.815 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.28.22:6700) Recv POWERON CMD
2026-01-29 01:38:52.815 [INFO] ctrl_if_trx.py:109 (MS@172.18.28.22:6700) Starting transceiver...
2026-01-29 01:38:52.858 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:38:52.863 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 01:38:52.863 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 01:38:52.864 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 01:38:52.864 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 01:38:53.118 [DEBUG] clck_gen.py:113 IND CLOCK 4182
2026-01-29 01:38:53.596 [DEBUG] clck_gen.py:113 IND CLOCK 4284
2026-01-29 01:38:54.074 [DEBUG] clck_gen.py:113 IND CLOCK 4386
2026-01-29 01:38:54.249 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:38:54.251 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 01:38:54.252 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 01:38:54.252 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 01:38:54.271 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 01:38:54.271 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 01:38:54.271 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 01:38:54.273 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 01:38:54.273 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 01:38:54.273 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 01:38:54.273 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.28.22:6700) Recv POWERON CMD
2026-01-29 01:38:54.273 [INFO] ctrl_if_trx.py:109 (MS@172.18.28.22:6700) Starting transceiver...
2026-01-29 01:38:54.315 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:38:54.319 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 01:38:54.320 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 01:38:54.320 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 01:38:54.320 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 01:38:54.546 [DEBUG] clck_gen.py:113 IND CLOCK 4488
2026-01-29 01:38:55.019 [DEBUG] clck_gen.py:113 IND CLOCK 4590
2026-01-29 01:38:55.498 [DEBUG] clck_gen.py:113 IND CLOCK 4692
2026-01-29 01:38:55.691 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:38:55.694 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 01:38:55.694 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 01:38:55.694 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 01:38:55.713 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 01:38:55.713 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 01:38:55.713 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 01:38:55.716 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 01:38:55.716 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 01:38:55.716 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 01:38:55.716 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.28.22:6700) Recv POWERON CMD
2026-01-29 01:38:55.716 [INFO] ctrl_if_trx.py:109 (MS@172.18.28.22:6700) Starting transceiver...
2026-01-29 01:38:55.758 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:38:55.763 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 01:38:55.764 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 01:38:55.764 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 01:38:55.764 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 01:38:55.972 [DEBUG] clck_gen.py:113 IND CLOCK 4794
2026-01-29 01:38:56.450 [DEBUG] clck_gen.py:113 IND CLOCK 4896
2026-01-29 01:38:56.928 [DEBUG] clck_gen.py:113 IND CLOCK 4998
2026-01-29 01:38:57.139 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:38:57.142 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 01:38:57.143 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 01:38:57.143 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 01:38:57.162 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 01:38:57.162 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 01:38:57.162 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 01:38:57.164 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 01:38:57.164 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 01:38:57.164 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 01:38:57.164 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.28.22:6700) Recv POWERON CMD
2026-01-29 01:38:57.164 [INFO] ctrl_if_trx.py:109 (MS@172.18.28.22:6700) Starting transceiver...
2026-01-29 01:38:57.211 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:38:57.215 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 01:38:57.215 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 01:38:57.216 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 01:38:57.216 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 01:38:57.405 [DEBUG] clck_gen.py:113 IND CLOCK 5100
2026-01-29 01:38:57.883 [DEBUG] clck_gen.py:113 IND CLOCK 5202
2026-01-29 01:38:58.275 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:38:58.278 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 01:38:58.278 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 01:38:58.278 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 01:38:58.295 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 01:38:58.295 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 01:38:58.295 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 01:38:58.297 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 01:38:58.297 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 01:38:58.297 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 01:38:58.297 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.28.22:6700) Recv POWERON CMD
2026-01-29 01:38:58.297 [INFO] ctrl_if_trx.py:109 (MS@172.18.28.22:6700) Starting transceiver...
2026-01-29 01:38:58.338 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:38:58.344 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 01:38:58.344 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 01:38:58.344 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 01:38:58.344 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 01:38:58.360 [DEBUG] clck_gen.py:113 IND CLOCK 5304
2026-01-29 01:38:58.838 [DEBUG] clck_gen.py:113 IND CLOCK 5406
2026-01-29 01:38:59.316 [DEBUG] clck_gen.py:113 IND CLOCK 5508
2026-01-29 01:38:59.726 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:38:59.728 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 01:38:59.728 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 01:38:59.728 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 01:38:59.746 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 01:38:59.746 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 01:38:59.746 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 01:38:59.749 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 01:38:59.749 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 01:38:59.749 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 01:38:59.749 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.28.22:6700) Recv POWERON CMD
2026-01-29 01:38:59.749 [INFO] ctrl_if_trx.py:109 (MS@172.18.28.22:6700) Starting transceiver...
2026-01-29 01:38:59.790 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:38:59.793 [DEBUG] clck_gen.py:113 IND CLOCK 5610
2026-01-29 01:38:59.795 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 01:38:59.796 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 01:38:59.796 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 01:38:59.796 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 01:39:00.271 [DEBUG] clck_gen.py:113 IND CLOCK 5712
2026-01-29 01:39:00.749 [DEBUG] clck_gen.py:113 IND CLOCK 5814
2026-01-29 01:39:01.178 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:39:01.181 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 01:39:01.181 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 01:39:01.181 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 01:39:01.199 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 01:39:01.199 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 01:39:01.199 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 01:39:01.201 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 01:39:01.201 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 01:39:01.201 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 01:39:01.201 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.28.22:6700) Recv POWERON CMD
2026-01-29 01:39:01.201 [INFO] ctrl_if_trx.py:109 (MS@172.18.28.22:6700) Starting transceiver...
2026-01-29 01:39:01.226 [DEBUG] clck_gen.py:113 IND CLOCK 5916
2026-01-29 01:39:01.242 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:39:01.247 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 01:39:01.248 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 01:39:01.248 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 01:39:01.248 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 01:39:01.704 [DEBUG] clck_gen.py:113 IND CLOCK 6018
2026-01-29 01:39:02.182 [DEBUG] clck_gen.py:113 IND CLOCK 6120
2026-01-29 01:39:02.629 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:39:02.633 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 01:39:02.634 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 01:39:02.634 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 01:39:02.641 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 01:39:02.641 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 01:39:02.642 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 01:39:02.642 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 01:39:02.643 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 01:39:02.643 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 01:39:02.643 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 01:39:02.643 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.28.20:5700) Recv POWEROFF cmd
2026-01-29 01:39:02.643 [INFO] ctrl_if_trx.py:117 (BTS@172.18.28.20:5700) Stopping transceiver...
2026-01-29 01:39:02.643 [INFO] transceiver.py:246 Stopping clock generator
2026-01-29 01:39:02.643 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 01:39:07.646 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.28.20:5700) Recv POWEROFF cmd
2026-01-29 01:39:07.646 [INFO] ctrl_if_trx.py:117 (BTS@172.18.28.20:5700) Stopping transceiver...
2026-01-29 01:39:07.647 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 01:39:07.649 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 01:39:07.651 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 01:39:07.653 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 01:39:07.661 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 01:39:07.661 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.28.20:5700) Recv SETFORMAT cmd
2026-01-29 01:39:07.661 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.28.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 01:39:07.661 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.28.20:5700) Recv SETFORMAT cmd
2026-01-29 01:39:07.662 [INFO] ctrl_if_trx.py:201 (BTS@172.18.28.20:5700) TRXD header version 1 -> 1
2026-01-29 01:39:07.663 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.28.20:5700/1) Recv RXTUNE cmd
2026-01-29 01:39:07.663 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.28.20:5700/1) Recv TXTUNE cmd
2026-01-29 01:39:07.663 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.28.20:5700/1) Recv SETFORMAT cmd
2026-01-29 01:39:07.663 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.28.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 01:39:07.664 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 01:39:07.664 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.28.20:5700/1) Recv NOMTXPOWER cmd
2026-01-29 01:39:07.664 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.28.20:5700/1) Recv SETFORMAT cmd
2026-01-29 01:39:07.664 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.28.20:5700/1) TRXD header version 1 -> 1
2026-01-29 01:39:07.665 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.28.20:5700/2) Recv RXTUNE cmd
2026-01-29 01:39:07.665 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.28.20:5700/2) Recv TXTUNE cmd
2026-01-29 01:39:07.665 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.28.20:5700/2) Recv SETFORMAT cmd
2026-01-29 01:39:07.665 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.28.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 01:39:07.665 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 01:39:07.665 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.28.20:5700/2) Recv NOMTXPOWER cmd
2026-01-29 01:39:07.665 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.28.20:5700/2) Recv SETFORMAT cmd
2026-01-29 01:39:07.665 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.28.20:5700/2) TRXD header version 1 -> 1
2026-01-29 01:39:07.666 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.28.20:5700/3) Recv RXTUNE cmd
2026-01-29 01:39:07.666 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.28.20:5700/3) Recv TXTUNE cmd
2026-01-29 01:39:07.666 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.28.20:5700/3) Recv SETFORMAT cmd
2026-01-29 01:39:07.666 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.28.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 01:39:07.667 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 01:39:07.667 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.28.20:5700/3) Recv NOMTXPOWER cmd
2026-01-29 01:39:07.667 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.28.20:5700/3) Recv SETFORMAT cmd
2026-01-29 01:39:07.667 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.28.20:5700/3) TRXD header version 1 -> 1
2026-01-29 01:39:07.668 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.28.20:5700) Recv RXTUNE cmd
2026-01-29 01:39:07.668 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETTSC
2026-01-29 01:39:07.668 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETTSC
2026-01-29 01:39:07.668 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETTSC
2026-01-29 01:39:07.668 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.28.20:5700) Recv TXTUNE cmd
2026-01-29 01:39:07.668 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETRXGAIN
2026-01-29 01:39:07.669 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETRXGAIN
2026-01-29 01:39:07.669 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETRXGAIN
2026-01-29 01:39:07.669 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETTSC
2026-01-29 01:39:07.669 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:39:07.669 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:39:07.669 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:39:07.669 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.28.20:5700) Recv NOMTXPOWER cmd
2026-01-29 01:39:07.669 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:39:07.669 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:39:07.669 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:39:07.669 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.28.20:5700) Recv POWERON CMD
2026-01-29 01:39:07.669 [INFO] ctrl_if_trx.py:109 (BTS@172.18.28.20:5700) Starting transceiver...
2026-01-29 01:39:07.669 [INFO] transceiver.py:243 Starting clock generator
2026-01-29 01:39:07.669 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-01-29 01:39:07.669 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:39:07.669 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:39:07.669 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:39:07.669 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETRXGAIN
2026-01-29 01:39:07.669 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:39:07.669 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:39:07.669 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:39:07.669 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 01:39:07.669 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:39:07.669 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:39:07.669 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:39:07.669 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 01:39:07.669 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:39:07.669 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:39:07.669 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:39:07.669 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 01:39:07.670 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:39:07.670 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:39:07.670 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:39:07.670 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 01:39:07.670 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:39:07.670 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:39:07.670 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:39:07.670 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 01:39:07.670 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 01:39:07.670 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 01:39:07.670 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 01:39:07.674 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-01-29 01:39:08.154 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-01-29 01:39:08.192 [DEBUG] fake_trx.py:278 (BTS@172.18.28.20:5700) Recv FAKE_TOA cmd
2026-01-29 01:39:08.195 [DEBUG] fake_trx.py:297 (BTS@172.18.28.20:5700) Recv FAKE_RSSI cmd
2026-01-29 01:39:08.196 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:39:08.197 [DEBUG] fake_trx.py:322 (BTS@172.18.28.20:5700) Recv FAKE_CI cmd
2026-01-29 01:39:08.211 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 01:39:08.211 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 01:39:08.211 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 01:39:08.217 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 01:39:08.218 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 01:39:08.218 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 01:39:08.218 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.28.22:6700) Recv POWERON CMD
2026-01-29 01:39:08.218 [INFO] ctrl_if_trx.py:109 (MS@172.18.28.22:6700) Starting transceiver...
2026-01-29 01:39:08.249 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD HANDOVER
2026-01-29 01:39:08.254 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 01:39:08.255 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 01:39:08.255 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 01:39:08.255 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 01:39:08.631 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-01-29 01:39:08.671 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 01:39:08.672 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 01:39:08.672 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 01:39:08.674 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 01:39:09.109 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-01-29 01:39:09.587 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-01-29 01:39:09.672 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 01:39:09.673 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 01:39:09.673 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 01:39:09.674 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 01:39:10.064 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-01-29 01:39:10.542 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-01-29 01:39:10.673 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 01:39:10.673 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 01:39:10.673 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 01:39:10.676 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 01:39:11.020 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-01-29 01:39:11.257 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:39:11.498 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-01-29 01:39:11.674 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 01:39:11.674 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 01:39:11.675 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 01:39:11.677 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 01:39:11.976 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-01-29 01:39:12.049 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:39:12.052 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 01:39:12.053 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 01:39:12.053 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 01:39:12.053 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 01:39:12.053 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 01:39:12.054 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 01:39:12.054 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 01:39:12.054 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.28.22:6700) Recv POWERON CMD
2026-01-29 01:39:12.054 [INFO] ctrl_if_trx.py:109 (MS@172.18.28.22:6700) Starting transceiver...
2026-01-29 01:39:12.068 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD HANDOVER
2026-01-29 01:39:12.071 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 01:39:12.071 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 01:39:12.071 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 01:39:12.072 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 01:39:12.451 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-01-29 01:39:12.674 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 01:39:12.675 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 01:39:12.675 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 01:39:12.678 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 01:39:12.924 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-01-29 01:39:13.402 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-01-29 01:39:13.880 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-01-29 01:39:14.358 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-01-29 01:39:14.835 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-01-29 01:39:15.072 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:39:15.313 [DEBUG] clck_gen.py:113 IND CLOCK 1632
2026-01-29 01:39:15.791 [DEBUG] clck_gen.py:113 IND CLOCK 1734
2026-01-29 01:39:15.938 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:39:15.940 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 01:39:15.941 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 01:39:15.941 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 01:39:15.957 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 01:39:15.957 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 01:39:15.957 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 01:39:15.959 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 01:39:15.959 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 01:39:15.959 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 01:39:15.960 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.28.22:6700) Recv POWERON CMD
2026-01-29 01:39:15.960 [INFO] ctrl_if_trx.py:109 (MS@172.18.28.22:6700) Starting transceiver...
2026-01-29 01:39:16.002 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD HANDOVER
2026-01-29 01:39:16.007 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 01:39:16.007 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 01:39:16.007 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 01:39:16.008 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 01:39:16.268 [DEBUG] clck_gen.py:113 IND CLOCK 1836
2026-01-29 01:39:16.745 [DEBUG] clck_gen.py:113 IND CLOCK 1938
2026-01-29 01:39:17.223 [DEBUG] clck_gen.py:113 IND CLOCK 2040
2026-01-29 01:39:17.701 [DEBUG] clck_gen.py:113 IND CLOCK 2142
2026-01-29 01:39:18.180 [DEBUG] clck_gen.py:113 IND CLOCK 2244
2026-01-29 01:39:18.658 [DEBUG] clck_gen.py:113 IND CLOCK 2346
2026-01-29 01:39:19.015 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:39:19.137 [DEBUG] clck_gen.py:113 IND CLOCK 2448
2026-01-29 01:39:19.588 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:39:19.591 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 01:39:19.591 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 01:39:19.592 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 01:39:19.592 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 01:39:19.592 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 01:39:19.593 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 01:39:19.593 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 01:39:19.593 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.28.22:6700) Recv POWERON CMD
2026-01-29 01:39:19.593 [INFO] ctrl_if_trx.py:109 (MS@172.18.28.22:6700) Starting transceiver...
2026-01-29 01:39:19.607 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD HANDOVER
2026-01-29 01:39:19.610 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 01:39:19.610 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 01:39:19.610 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 01:39:19.610 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 01:39:19.615 [DEBUG] clck_gen.py:113 IND CLOCK 2550
2026-01-29 01:39:20.093 [DEBUG] clck_gen.py:113 IND CLOCK 2652
2026-01-29 01:39:20.571 [DEBUG] clck_gen.py:113 IND CLOCK 2754
2026-01-29 01:39:21.050 [DEBUG] clck_gen.py:113 IND CLOCK 2856
2026-01-29 01:39:21.527 [DEBUG] clck_gen.py:113 IND CLOCK 2958
2026-01-29 01:39:22.005 [DEBUG] clck_gen.py:113 IND CLOCK 3060
2026-01-29 01:39:22.484 [DEBUG] clck_gen.py:113 IND CLOCK 3162
2026-01-29 01:39:22.615 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:39:22.962 [DEBUG] clck_gen.py:113 IND CLOCK 3264
2026-01-29 01:39:23.007 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:39:23.009 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 01:39:23.010 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 01:39:23.010 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 01:39:23.028 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 01:39:23.028 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 01:39:23.028 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 01:39:23.032 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 01:39:23.032 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 01:39:23.032 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 01:39:23.032 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.28.22:6700) Recv POWERON CMD
2026-01-29 01:39:23.032 [INFO] ctrl_if_trx.py:109 (MS@172.18.28.22:6700) Starting transceiver...
2026-01-29 01:39:23.074 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD HANDOVER
2026-01-29 01:39:23.079 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 01:39:23.079 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 01:39:23.080 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 01:39:23.080 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 01:39:23.439 [DEBUG] clck_gen.py:113 IND CLOCK 3366
2026-01-29 01:39:23.917 [DEBUG] clck_gen.py:113 IND CLOCK 3468
2026-01-29 01:39:24.395 [DEBUG] clck_gen.py:113 IND CLOCK 3570
2026-01-29 01:39:24.873 [DEBUG] clck_gen.py:113 IND CLOCK 3672
2026-01-29 01:39:25.351 [DEBUG] clck_gen.py:113 IND CLOCK 3774
2026-01-29 01:39:25.830 [DEBUG] clck_gen.py:113 IND CLOCK 3876
2026-01-29 01:39:26.274 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:39:26.308 [DEBUG] clck_gen.py:113 IND CLOCK 3978
2026-01-29 01:39:26.746 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:39:26.749 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 01:39:26.749 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 01:39:26.749 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 01:39:26.750 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 01:39:26.751 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 01:39:26.751 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 01:39:26.751 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 01:39:26.751 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.28.22:6700) Recv POWERON CMD
2026-01-29 01:39:26.751 [INFO] ctrl_if_trx.py:109 (MS@172.18.28.22:6700) Starting transceiver...
2026-01-29 01:39:26.778 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD HANDOVER
2026-01-29 01:39:26.782 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 01:39:26.782 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 01:39:26.782 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 01:39:26.782 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 01:39:26.785 [DEBUG] clck_gen.py:113 IND CLOCK 4080
2026-01-29 01:39:27.262 [DEBUG] clck_gen.py:113 IND CLOCK 4182
2026-01-29 01:39:27.740 [DEBUG] clck_gen.py:113 IND CLOCK 4284
2026-01-29 01:39:28.218 [DEBUG] clck_gen.py:113 IND CLOCK 4386
2026-01-29 01:39:28.696 [DEBUG] clck_gen.py:113 IND CLOCK 4488
2026-01-29 01:39:29.172 [DEBUG] clck_gen.py:113 IND CLOCK 4590
2026-01-29 01:39:29.650 [DEBUG] clck_gen.py:113 IND CLOCK 4692
2026-01-29 01:39:29.859 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:39:30.087 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:39:30.090 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 01:39:30.091 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 01:39:30.091 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 01:39:30.108 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 01:39:30.108 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 01:39:30.108 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 01:39:30.111 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 01:39:30.111 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 01:39:30.111 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 01:39:30.111 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.28.22:6700) Recv POWERON CMD
2026-01-29 01:39:30.111 [INFO] ctrl_if_trx.py:109 (MS@172.18.28.22:6700) Starting transceiver...
2026-01-29 01:39:30.127 [DEBUG] clck_gen.py:113 IND CLOCK 4794
2026-01-29 01:39:30.154 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD HANDOVER
2026-01-29 01:39:30.159 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 01:39:30.159 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 01:39:30.160 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 01:39:30.160 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 01:39:30.604 [DEBUG] clck_gen.py:113 IND CLOCK 4896
2026-01-29 01:39:31.082 [DEBUG] clck_gen.py:113 IND CLOCK 4998
2026-01-29 01:39:31.560 [DEBUG] clck_gen.py:113 IND CLOCK 5100
2026-01-29 01:39:32.038 [DEBUG] clck_gen.py:113 IND CLOCK 5202
2026-01-29 01:39:32.515 [DEBUG] clck_gen.py:113 IND CLOCK 5304
2026-01-29 01:39:32.994 [DEBUG] clck_gen.py:113 IND CLOCK 5406
2026-01-29 01:39:33.365 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:39:33.471 [DEBUG] clck_gen.py:113 IND CLOCK 5508
2026-01-29 01:39:33.863 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:39:33.865 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 01:39:33.866 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 01:39:33.866 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 01:39:33.866 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 01:39:33.867 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 01:39:33.868 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 01:39:33.868 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 01:39:33.869 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.28.22:6700) Recv POWERON CMD
2026-01-29 01:39:33.869 [INFO] ctrl_if_trx.py:109 (MS@172.18.28.22:6700) Starting transceiver...
2026-01-29 01:39:33.890 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD HANDOVER
2026-01-29 01:39:33.893 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 01:39:33.893 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 01:39:33.893 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 01:39:33.893 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 01:39:33.949 [DEBUG] clck_gen.py:113 IND CLOCK 5610
2026-01-29 01:39:34.427 [DEBUG] clck_gen.py:113 IND CLOCK 5712
2026-01-29 01:39:34.905 [DEBUG] clck_gen.py:113 IND CLOCK 5814
2026-01-29 01:39:35.384 [DEBUG] clck_gen.py:113 IND CLOCK 5916
2026-01-29 01:39:35.861 [DEBUG] clck_gen.py:113 IND CLOCK 6018
2026-01-29 01:39:36.340 [DEBUG] clck_gen.py:113 IND CLOCK 6120
2026-01-29 01:39:36.818 [DEBUG] clck_gen.py:113 IND CLOCK 6222
2026-01-29 01:39:36.954 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:39:37.210 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:39:37.213 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 01:39:37.213 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 01:39:37.214 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 01:39:37.225 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 01:39:37.226 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 01:39:37.226 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 01:39:37.226 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 01:39:37.231 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 01:39:37.231 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 01:39:37.231 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 01:39:37.231 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.28.20:5700) Recv POWEROFF cmd
2026-01-29 01:39:37.231 [INFO] ctrl_if_trx.py:117 (BTS@172.18.28.20:5700) Stopping transceiver...
2026-01-29 01:39:37.232 [INFO] transceiver.py:246 Stopping clock generator
2026-01-29 01:39:37.232 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 01:39:37.232 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=6313 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 01:39:37.232 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=6313 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 01:39:37.232 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=6313 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 01:39:37.232 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=6313 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 01:39:37.232 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=6313 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 01:39:37.233 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=6313 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 01:39:37.233 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=6313 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 01:39:37.233 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=6313 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 01:39:42.228 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.28.20:5700) Recv POWEROFF cmd
2026-01-29 01:39:42.228 [INFO] ctrl_if_trx.py:117 (BTS@172.18.28.20:5700) Stopping transceiver...
2026-01-29 01:39:42.229 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 01:39:42.234 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 01:39:42.234 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 01:39:42.235 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 01:39:42.246 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 01:39:42.247 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.28.20:5700) Recv SETFORMAT cmd
2026-01-29 01:39:42.247 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.28.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 01:39:42.247 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.28.20:5700) Recv SETFORMAT cmd
2026-01-29 01:39:42.247 [INFO] ctrl_if_trx.py:201 (BTS@172.18.28.20:5700) TRXD header version 1 -> 1
2026-01-29 01:39:42.250 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.28.20:5700/1) Recv RXTUNE cmd
2026-01-29 01:39:42.250 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.28.20:5700/1) Recv TXTUNE cmd
2026-01-29 01:39:42.250 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.28.20:5700/1) Recv SETFORMAT cmd
2026-01-29 01:39:42.250 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.28.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 01:39:42.250 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 01:39:42.251 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.28.20:5700/1) Recv NOMTXPOWER cmd
2026-01-29 01:39:42.251 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.28.20:5700/1) Recv SETFORMAT cmd
2026-01-29 01:39:42.251 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.28.20:5700/1) TRXD header version 1 -> 1
2026-01-29 01:39:42.252 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.28.20:5700/2) Recv RXTUNE cmd
2026-01-29 01:39:42.252 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.28.20:5700/2) Recv TXTUNE cmd
2026-01-29 01:39:42.252 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.28.20:5700/2) Recv SETFORMAT cmd
2026-01-29 01:39:42.252 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.28.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 01:39:42.252 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 01:39:42.252 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.28.20:5700/2) Recv NOMTXPOWER cmd
2026-01-29 01:39:42.252 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.28.20:5700/2) Recv SETFORMAT cmd
2026-01-29 01:39:42.252 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.28.20:5700/2) TRXD header version 1 -> 1
2026-01-29 01:39:42.254 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.28.20:5700/3) Recv RXTUNE cmd
2026-01-29 01:39:42.254 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.28.20:5700/3) Recv TXTUNE cmd
2026-01-29 01:39:42.254 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.28.20:5700/3) Recv SETFORMAT cmd
2026-01-29 01:39:42.254 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.28.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 01:39:42.254 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.28.20:5700/3) Recv NOMTXPOWER cmd
2026-01-29 01:39:42.254 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 01:39:42.254 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.28.20:5700/3) Recv SETFORMAT cmd
2026-01-29 01:39:42.254 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.28.20:5700/3) TRXD header version 1 -> 1
2026-01-29 01:39:42.256 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.28.20:5700) Recv RXTUNE cmd
2026-01-29 01:39:42.256 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETTSC
2026-01-29 01:39:42.256 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETTSC
2026-01-29 01:39:42.256 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETTSC
2026-01-29 01:39:42.256 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.28.20:5700) Recv TXTUNE cmd
2026-01-29 01:39:42.256 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETRXGAIN
2026-01-29 01:39:42.256 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETRXGAIN
2026-01-29 01:39:42.256 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETRXGAIN
2026-01-29 01:39:42.256 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETTSC
2026-01-29 01:39:42.256 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:39:42.256 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:39:42.256 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:39:42.256 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.28.20:5700) Recv NOMTXPOWER cmd
2026-01-29 01:39:42.256 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:39:42.256 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:39:42.256 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.28.20:5700) Recv POWERON CMD
2026-01-29 01:39:42.256 [INFO] ctrl_if_trx.py:109 (BTS@172.18.28.20:5700) Starting transceiver...
2026-01-29 01:39:42.256 [INFO] transceiver.py:243 Starting clock generator
2026-01-29 01:39:42.256 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-01-29 01:39:42.257 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:39:42.257 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:39:42.257 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:39:42.257 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETRXGAIN
2026-01-29 01:39:42.257 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:39:42.257 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:39:42.257 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 01:39:42.257 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:39:42.257 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 01:39:42.257 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:39:42.257 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:39:42.257 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:39:42.257 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 01:39:42.257 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:39:42.257 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:39:42.257 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:39:42.257 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 01:39:42.257 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:39:42.257 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:39:42.257 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 01:39:42.257 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:39:42.257 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:39:42.257 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:39:42.257 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 01:39:42.257 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:39:42.257 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 01:39:42.257 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:39:42.257 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 01:39:42.261 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-01-29 01:39:42.742 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-01-29 01:39:42.787 [DEBUG] fake_trx.py:278 (BTS@172.18.28.20:5700) Recv FAKE_TOA cmd
2026-01-29 01:39:42.789 [DEBUG] fake_trx.py:297 (BTS@172.18.28.20:5700) Recv FAKE_RSSI cmd
2026-01-29 01:39:42.791 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:39:42.791 [DEBUG] fake_trx.py:322 (BTS@172.18.28.20:5700) Recv FAKE_CI cmd
2026-01-29 01:39:42.812 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 01:39:42.812 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 01:39:42.813 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 01:39:42.819 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 01:39:42.820 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 01:39:42.820 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 01:39:42.821 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.28.22:6700) Recv POWERON CMD
2026-01-29 01:39:42.821 [INFO] ctrl_if_trx.py:109 (MS@172.18.28.22:6700) Starting transceiver...
2026-01-29 01:39:42.839 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD HANDOVER
2026-01-29 01:39:42.844 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 01:39:42.844 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 01:39:42.845 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 01:39:42.845 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 01:39:43.220 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-01-29 01:39:43.259 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 01:39:43.259 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 01:39:43.260 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 01:39:43.262 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 01:39:43.697 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-01-29 01:39:44.174 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-01-29 01:39:44.260 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 01:39:44.261 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 01:39:44.262 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 01:39:44.262 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 01:39:44.652 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-01-29 01:39:45.130 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-01-29 01:39:45.261 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 01:39:45.261 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 01:39:45.264 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 01:39:45.264 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 01:39:45.608 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-01-29 01:39:45.849 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:39:46.085 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-01-29 01:39:46.262 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 01:39:46.262 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 01:39:46.265 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 01:39:46.265 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 01:39:46.563 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-01-29 01:39:46.636 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:39:46.639 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 01:39:46.640 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 01:39:46.640 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 01:39:46.640 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 01:39:46.641 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 01:39:46.642 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 01:39:46.642 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 01:39:46.642 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.28.22:6700) Recv POWERON CMD
2026-01-29 01:39:46.643 [INFO] ctrl_if_trx.py:109 (MS@172.18.28.22:6700) Starting transceiver...
2026-01-29 01:39:46.655 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD HANDOVER
2026-01-29 01:39:46.658 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 01:39:46.658 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 01:39:46.658 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 01:39:46.658 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 01:39:47.041 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-01-29 01:39:47.262 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 01:39:47.263 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 01:39:47.266 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 01:39:47.267 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 01:39:47.518 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-01-29 01:39:47.995 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-01-29 01:39:48.473 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-01-29 01:39:48.951 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-01-29 01:39:49.430 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-01-29 01:39:49.662 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:39:49.908 [DEBUG] clck_gen.py:113 IND CLOCK 1632
2026-01-29 01:39:50.386 [DEBUG] clck_gen.py:113 IND CLOCK 1734
2026-01-29 01:39:50.532 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:39:50.535 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 01:39:50.535 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 01:39:50.535 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 01:39:50.536 [WARNING] transceiver.py:257 (MS@172.18.28.22:6700) RX TRXD message (fn=1768 tn=4 pwr=0), but transceiver is not running => dropping...
2026-01-29 01:39:50.536 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 01:39:50.536 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 01:39:50.536 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 01:39:50.536 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 01:39:50.536 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.28.22:6700) Recv POWERON CMD
2026-01-29 01:39:50.536 [INFO] ctrl_if_trx.py:109 (MS@172.18.28.22:6700) Starting transceiver...
2026-01-29 01:39:50.570 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD HANDOVER
2026-01-29 01:39:50.573 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 01:39:50.573 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 01:39:50.573 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 01:39:50.573 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 01:39:50.865 [DEBUG] clck_gen.py:113 IND CLOCK 1836
2026-01-29 01:39:51.343 [DEBUG] clck_gen.py:113 IND CLOCK 1938
2026-01-29 01:39:51.821 [DEBUG] clck_gen.py:113 IND CLOCK 2040
2026-01-29 01:39:52.299 [DEBUG] clck_gen.py:113 IND CLOCK 2142
2026-01-29 01:39:52.777 [DEBUG] clck_gen.py:113 IND CLOCK 2244
2026-01-29 01:39:53.255 [DEBUG] clck_gen.py:113 IND CLOCK 2346
2026-01-29 01:39:53.579 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:39:53.733 [DEBUG] clck_gen.py:113 IND CLOCK 2448
2026-01-29 01:39:54.210 [DEBUG] clck_gen.py:113 IND CLOCK 2550
2026-01-29 01:39:54.430 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:39:54.433 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 01:39:54.434 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 01:39:54.434 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 01:39:54.434 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 01:39:54.434 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 01:39:54.434 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 01:39:54.435 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 01:39:54.435 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.28.22:6700) Recv POWERON CMD
2026-01-29 01:39:54.435 [INFO] ctrl_if_trx.py:109 (MS@172.18.28.22:6700) Starting transceiver...
2026-01-29 01:39:54.445 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD HANDOVER
2026-01-29 01:39:54.448 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 01:39:54.448 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 01:39:54.449 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 01:39:54.449 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 01:39:54.688 [DEBUG] clck_gen.py:113 IND CLOCK 2652
2026-01-29 01:39:54.920 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:39:55.165 [DEBUG] clck_gen.py:113 IND CLOCK 2754
2026-01-29 01:39:55.404 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:39:55.406 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 01:39:55.407 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 01:39:55.407 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 01:39:55.424 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 01:39:55.424 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 01:39:55.425 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 01:39:55.426 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 01:39:55.426 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 01:39:55.426 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 01:39:55.426 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.28.22:6700) Recv POWERON CMD
2026-01-29 01:39:55.426 [INFO] ctrl_if_trx.py:109 (MS@172.18.28.22:6700) Starting transceiver...
2026-01-29 01:39:55.471 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD HANDOVER
2026-01-29 01:39:55.476 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 01:39:55.476 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 01:39:55.476 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 01:39:55.476 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 01:39:55.643 [DEBUG] clck_gen.py:113 IND CLOCK 2856
2026-01-29 01:39:56.121 [DEBUG] clck_gen.py:113 IND CLOCK 2958
2026-01-29 01:39:56.599 [DEBUG] clck_gen.py:113 IND CLOCK 3060
2026-01-29 01:39:57.078 [DEBUG] clck_gen.py:113 IND CLOCK 3162
2026-01-29 01:39:57.556 [DEBUG] clck_gen.py:113 IND CLOCK 3264
2026-01-29 01:39:58.033 [DEBUG] clck_gen.py:113 IND CLOCK 3366
2026-01-29 01:39:58.482 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:39:58.511 [DEBUG] clck_gen.py:113 IND CLOCK 3468
2026-01-29 01:39:58.989 [DEBUG] clck_gen.py:113 IND CLOCK 3570
2026-01-29 01:39:59.062 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:39:59.064 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 01:39:59.065 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 01:39:59.065 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 01:39:59.065 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 01:39:59.065 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 01:39:59.066 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 01:39:59.066 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 01:39:59.066 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.28.22:6700) Recv POWERON CMD
2026-01-29 01:39:59.066 [INFO] ctrl_if_trx.py:109 (MS@172.18.28.22:6700) Starting transceiver...
2026-01-29 01:39:59.080 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD HANDOVER
2026-01-29 01:39:59.083 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 01:39:59.083 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 01:39:59.083 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 01:39:59.084 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 01:39:59.467 [DEBUG] clck_gen.py:113 IND CLOCK 3672
2026-01-29 01:39:59.946 [DEBUG] clck_gen.py:113 IND CLOCK 3774
2026-01-29 01:40:00.424 [DEBUG] clck_gen.py:113 IND CLOCK 3876
2026-01-29 01:40:00.903 [DEBUG] clck_gen.py:113 IND CLOCK 3978
2026-01-29 01:40:01.381 [DEBUG] clck_gen.py:113 IND CLOCK 4080
2026-01-29 01:40:01.860 [DEBUG] clck_gen.py:113 IND CLOCK 4182
2026-01-29 01:40:02.092 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:40:02.338 [DEBUG] clck_gen.py:113 IND CLOCK 4284
2026-01-29 01:40:02.815 [DEBUG] clck_gen.py:113 IND CLOCK 4386
2026-01-29 01:40:02.963 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:40:02.966 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 01:40:02.967 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 01:40:02.967 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 01:40:02.967 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 01:40:02.968 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 01:40:02.968 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 01:40:02.969 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 01:40:02.969 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.28.22:6700) Recv POWERON CMD
2026-01-29 01:40:02.969 [INFO] ctrl_if_trx.py:109 (MS@172.18.28.22:6700) Starting transceiver...
2026-01-29 01:40:02.999 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD HANDOVER
2026-01-29 01:40:03.002 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 01:40:03.003 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 01:40:03.003 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 01:40:03.004 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 01:40:03.290 [DEBUG] clck_gen.py:113 IND CLOCK 4488
2026-01-29 01:40:03.763 [DEBUG] clck_gen.py:113 IND CLOCK 4590
2026-01-29 01:40:04.241 [DEBUG] clck_gen.py:113 IND CLOCK 4692
2026-01-29 01:40:04.719 [DEBUG] clck_gen.py:113 IND CLOCK 4794
2026-01-29 01:40:05.197 [DEBUG] clck_gen.py:113 IND CLOCK 4896
2026-01-29 01:40:05.675 [DEBUG] clck_gen.py:113 IND CLOCK 4998
2026-01-29 01:40:06.005 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:40:06.153 [DEBUG] clck_gen.py:113 IND CLOCK 5100
2026-01-29 01:40:06.631 [DEBUG] clck_gen.py:113 IND CLOCK 5202
2026-01-29 01:40:06.852 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:40:06.855 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 01:40:06.855 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 01:40:06.856 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 01:40:06.856 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 01:40:06.857 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 01:40:06.857 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 01:40:06.857 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 01:40:06.857 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.28.22:6700) Recv POWERON CMD
2026-01-29 01:40:06.857 [INFO] ctrl_if_trx.py:109 (MS@172.18.28.22:6700) Starting transceiver...
2026-01-29 01:40:06.865 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD HANDOVER
2026-01-29 01:40:06.869 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 01:40:06.869 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 01:40:06.870 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 01:40:06.870 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 01:40:07.110 [DEBUG] clck_gen.py:113 IND CLOCK 5304
2026-01-29 01:40:07.347 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:40:07.588 [DEBUG] clck_gen.py:113 IND CLOCK 5406
2026-01-29 01:40:07.827 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:40:07.830 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 01:40:07.831 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 01:40:07.831 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 01:40:07.847 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 01:40:07.847 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 01:40:07.847 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 01:40:07.849 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 01:40:07.849 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 01:40:07.849 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 01:40:07.849 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.28.22:6700) Recv POWERON CMD
2026-01-29 01:40:07.849 [INFO] ctrl_if_trx.py:109 (MS@172.18.28.22:6700) Starting transceiver...
2026-01-29 01:40:07.890 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD HANDOVER
2026-01-29 01:40:07.895 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 01:40:07.895 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 01:40:07.896 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 01:40:07.897 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 01:40:08.065 [DEBUG] clck_gen.py:113 IND CLOCK 5508
2026-01-29 01:40:08.543 [DEBUG] clck_gen.py:113 IND CLOCK 5610
2026-01-29 01:40:09.021 [DEBUG] clck_gen.py:113 IND CLOCK 5712
2026-01-29 01:40:09.498 [DEBUG] clck_gen.py:113 IND CLOCK 5814
2026-01-29 01:40:09.976 [DEBUG] clck_gen.py:113 IND CLOCK 5916
2026-01-29 01:40:10.454 [DEBUG] clck_gen.py:113 IND CLOCK 6018
2026-01-29 01:40:10.899 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:40:10.933 [DEBUG] clck_gen.py:113 IND CLOCK 6120
2026-01-29 01:40:11.370 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:40:11.372 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 01:40:11.373 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 01:40:11.373 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 01:40:11.373 [WARNING] transceiver.py:257 (MS@172.18.28.22:6700) RX TRXD message (fn=6217 tn=7 pwr=0), but transceiver is not running => dropping...
2026-01-29 01:40:11.373 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 01:40:11.373 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 01:40:11.374 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 01:40:11.374 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 01:40:11.374 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.28.22:6700) Recv POWERON CMD
2026-01-29 01:40:11.374 [INFO] ctrl_if_trx.py:109 (MS@172.18.28.22:6700) Starting transceiver...
2026-01-29 01:40:11.403 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD HANDOVER
2026-01-29 01:40:11.406 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 01:40:11.406 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 01:40:11.406 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 01:40:11.407 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 01:40:11.411 [DEBUG] clck_gen.py:113 IND CLOCK 6222
2026-01-29 01:40:11.889 [DEBUG] clck_gen.py:113 IND CLOCK 6324
2026-01-29 01:40:12.362 [DEBUG] clck_gen.py:113 IND CLOCK 6426
2026-01-29 01:40:12.831 [DEBUG] clck_gen.py:113 IND CLOCK 6528
2026-01-29 01:40:13.310 [DEBUG] clck_gen.py:113 IND CLOCK 6630
2026-01-29 01:40:13.787 [DEBUG] clck_gen.py:113 IND CLOCK 6732
2026-01-29 01:40:14.265 [DEBUG] clck_gen.py:113 IND CLOCK 6834
2026-01-29 01:40:14.474 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:40:14.702 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:40:14.705 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 01:40:14.706 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 01:40:14.706 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 01:40:14.706 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 01:40:14.707 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 01:40:14.707 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 01:40:14.708 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 01:40:14.708 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.28.22:6700) Recv POWERON CMD
2026-01-29 01:40:14.708 [INFO] ctrl_if_trx.py:109 (MS@172.18.28.22:6700) Starting transceiver...
2026-01-29 01:40:14.734 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD HANDOVER
2026-01-29 01:40:14.737 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 01:40:14.737 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 01:40:14.738 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 01:40:14.738 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 01:40:14.742 [DEBUG] clck_gen.py:113 IND CLOCK 6936
2026-01-29 01:40:15.211 [DEBUG] clck_gen.py:113 IND CLOCK 7038
2026-01-29 01:40:15.684 [DEBUG] clck_gen.py:113 IND CLOCK 7140
2026-01-29 01:40:16.163 [DEBUG] clck_gen.py:113 IND CLOCK 7242
2026-01-29 01:40:16.640 [DEBUG] clck_gen.py:113 IND CLOCK 7344
2026-01-29 01:40:17.118 [DEBUG] clck_gen.py:113 IND CLOCK 7446
2026-01-29 01:40:17.596 [DEBUG] clck_gen.py:113 IND CLOCK 7548
2026-01-29 01:40:17.805 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:40:18.034 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:40:18.036 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 01:40:18.037 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 01:40:18.037 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 01:40:18.037 [WARNING] transceiver.py:257 (MS@172.18.28.22:6700) RX TRXD message (fn=7645 tn=6 pwr=0), but transceiver is not running => dropping...
2026-01-29 01:40:18.037 [WARNING] transceiver.py:257 (MS@172.18.28.22:6700) RX TRXD message (fn=7645 tn=7 pwr=0), but transceiver is not running => dropping...
2026-01-29 01:40:18.037 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 01:40:18.037 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 01:40:18.037 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 01:40:18.038 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 01:40:18.038 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.28.22:6700) Recv POWERON CMD
2026-01-29 01:40:18.038 [INFO] ctrl_if_trx.py:109 (MS@172.18.28.22:6700) Starting transceiver...
2026-01-29 01:40:18.066 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD HANDOVER
2026-01-29 01:40:18.069 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 01:40:18.069 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 01:40:18.069 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 01:40:18.069 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 01:40:18.074 [DEBUG] clck_gen.py:113 IND CLOCK 7650
2026-01-29 01:40:18.519 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:40:18.552 [DEBUG] clck_gen.py:113 IND CLOCK 7752
2026-01-29 01:40:18.989 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:40:18.992 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 01:40:18.993 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 01:40:18.993 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 01:40:19.011 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 01:40:19.011 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 01:40:19.011 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 01:40:19.013 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 01:40:19.013 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 01:40:19.013 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 01:40:19.013 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.28.22:6700) Recv POWERON CMD
2026-01-29 01:40:19.013 [INFO] ctrl_if_trx.py:109 (MS@172.18.28.22:6700) Starting transceiver...
2026-01-29 01:40:19.029 [DEBUG] clck_gen.py:113 IND CLOCK 7854
2026-01-29 01:40:19.054 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD HANDOVER
2026-01-29 01:40:19.059 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 01:40:19.060 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 01:40:19.060 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 01:40:19.060 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 01:40:19.507 [DEBUG] clck_gen.py:113 IND CLOCK 7956
2026-01-29 01:40:19.986 [DEBUG] clck_gen.py:113 IND CLOCK 8058
2026-01-29 01:40:20.464 [DEBUG] clck_gen.py:113 IND CLOCK 8160
2026-01-29 01:40:20.942 [DEBUG] clck_gen.py:113 IND CLOCK 8262
2026-01-29 01:40:21.421 [DEBUG] clck_gen.py:113 IND CLOCK 8364
2026-01-29 01:40:21.899 [DEBUG] clck_gen.py:113 IND CLOCK 8466
2026-01-29 01:40:22.270 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:40:22.377 [DEBUG] clck_gen.py:113 IND CLOCK 8568
2026-01-29 01:40:22.769 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:40:22.772 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 01:40:22.772 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 01:40:22.772 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 01:40:22.773 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 01:40:22.773 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 01:40:22.773 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 01:40:22.773 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 01:40:22.774 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.28.22:6700) Recv POWERON CMD
2026-01-29 01:40:22.774 [INFO] ctrl_if_trx.py:109 (MS@172.18.28.22:6700) Starting transceiver...
2026-01-29 01:40:22.796 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD HANDOVER
2026-01-29 01:40:22.799 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 01:40:22.799 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 01:40:22.799 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 01:40:22.800 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 01:40:22.855 [DEBUG] clck_gen.py:113 IND CLOCK 8670
2026-01-29 01:40:23.333 [DEBUG] clck_gen.py:113 IND CLOCK 8772
2026-01-29 01:40:23.811 [DEBUG] clck_gen.py:113 IND CLOCK 8874
2026-01-29 01:40:24.288 [DEBUG] clck_gen.py:113 IND CLOCK 8976
2026-01-29 01:40:24.766 [DEBUG] clck_gen.py:113 IND CLOCK 9078
2026-01-29 01:40:25.245 [DEBUG] clck_gen.py:113 IND CLOCK 9180
2026-01-29 01:40:25.722 [DEBUG] clck_gen.py:113 IND CLOCK 9282
2026-01-29 01:40:25.858 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:40:26.114 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:40:26.116 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 01:40:26.117 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 01:40:26.117 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 01:40:26.118 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 01:40:26.118 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 01:40:26.118 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 01:40:26.118 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 01:40:26.119 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.28.22:6700) Recv POWERON CMD
2026-01-29 01:40:26.119 [INFO] ctrl_if_trx.py:109 (MS@172.18.28.22:6700) Starting transceiver...
2026-01-29 01:40:26.141 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD HANDOVER
2026-01-29 01:40:26.144 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 01:40:26.144 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 01:40:26.144 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 01:40:26.145 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 01:40:26.201 [DEBUG] clck_gen.py:113 IND CLOCK 9384
2026-01-29 01:40:26.679 [DEBUG] clck_gen.py:113 IND CLOCK 9486
2026-01-29 01:40:27.157 [DEBUG] clck_gen.py:113 IND CLOCK 9588
2026-01-29 01:40:27.635 [DEBUG] clck_gen.py:113 IND CLOCK 9690
2026-01-29 01:40:28.113 [DEBUG] clck_gen.py:113 IND CLOCK 9792
2026-01-29 01:40:28.591 [DEBUG] clck_gen.py:113 IND CLOCK 9894
2026-01-29 01:40:29.069 [DEBUG] clck_gen.py:113 IND CLOCK 9996
2026-01-29 01:40:29.204 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:40:29.460 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:40:29.463 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 01:40:29.463 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 01:40:29.463 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 01:40:29.463 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 01:40:29.464 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 01:40:29.464 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 01:40:29.464 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 01:40:29.464 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.28.22:6700) Recv POWERON CMD
2026-01-29 01:40:29.464 [INFO] ctrl_if_trx.py:109 (MS@172.18.28.22:6700) Starting transceiver...
2026-01-29 01:40:29.487 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD HANDOVER
2026-01-29 01:40:29.490 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 01:40:29.490 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 01:40:29.490 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 01:40:29.491 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 01:40:29.546 [DEBUG] clck_gen.py:113 IND CLOCK 10098
2026-01-29 01:40:30.024 [DEBUG] clck_gen.py:113 IND CLOCK 10200
2026-01-29 01:40:30.159 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:40:30.415 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:40:30.418 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 01:40:30.418 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 01:40:30.419 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 01:40:30.431 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 01:40:30.431 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 01:40:30.431 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 01:40:30.431 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 01:40:30.433 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 01:40:30.433 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 01:40:30.433 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 01:40:30.433 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.28.20:5700) Recv POWEROFF cmd
2026-01-29 01:40:30.433 [INFO] ctrl_if_trx.py:117 (BTS@172.18.28.20:5700) Stopping transceiver...
2026-01-29 01:40:30.434 [INFO] transceiver.py:246 Stopping clock generator
2026-01-29 01:40:30.434 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 01:40:30.434 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=10290 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 01:40:30.434 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=10290 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 01:40:30.434 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=10290 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 01:40:30.434 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=10290 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 01:40:30.434 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=10290 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 01:40:30.434 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=10290 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 01:40:30.434 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=10290 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 01:40:30.434 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=10290 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 01:40:35.435 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.28.20:5700) Recv POWEROFF cmd
2026-01-29 01:40:35.435 [INFO] ctrl_if_trx.py:117 (BTS@172.18.28.20:5700) Stopping transceiver...
2026-01-29 01:40:35.437 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 01:40:35.438 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 01:40:35.438 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 01:40:35.438 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 01:40:35.444 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 01:40:35.446 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.28.20:5700) Recv SETFORMAT cmd
2026-01-29 01:40:35.446 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.28.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 01:40:35.447 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.28.20:5700) Recv SETFORMAT cmd
2026-01-29 01:40:35.447 [INFO] ctrl_if_trx.py:201 (BTS@172.18.28.20:5700) TRXD header version 1 -> 1
2026-01-29 01:40:35.451 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.28.20:5700/1) Recv RXTUNE cmd
2026-01-29 01:40:35.451 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.28.20:5700/1) Recv TXTUNE cmd
2026-01-29 01:40:35.451 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.28.20:5700/1) Recv SETFORMAT cmd
2026-01-29 01:40:35.451 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.28.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 01:40:35.451 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 01:40:35.451 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.28.20:5700/1) Recv NOMTXPOWER cmd
2026-01-29 01:40:35.452 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.28.20:5700/1) Recv SETFORMAT cmd
2026-01-29 01:40:35.452 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.28.20:5700/1) TRXD header version 1 -> 1
2026-01-29 01:40:35.454 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.28.20:5700/2) Recv RXTUNE cmd
2026-01-29 01:40:35.454 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.28.20:5700/2) Recv TXTUNE cmd
2026-01-29 01:40:35.454 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.28.20:5700/2) Recv SETFORMAT cmd
2026-01-29 01:40:35.455 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.28.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 01:40:35.455 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 01:40:35.455 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.28.20:5700/2) Recv NOMTXPOWER cmd
2026-01-29 01:40:35.455 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.28.20:5700/2) Recv SETFORMAT cmd
2026-01-29 01:40:35.455 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.28.20:5700/2) TRXD header version 1 -> 1
2026-01-29 01:40:35.457 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.28.20:5700/3) Recv RXTUNE cmd
2026-01-29 01:40:35.457 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.28.20:5700/3) Recv TXTUNE cmd
2026-01-29 01:40:35.457 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.28.20:5700/3) Recv SETFORMAT cmd
2026-01-29 01:40:35.457 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.28.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 01:40:35.457 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 01:40:35.457 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.28.20:5700/3) Recv NOMTXPOWER cmd
2026-01-29 01:40:35.458 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.28.20:5700/3) Recv SETFORMAT cmd
2026-01-29 01:40:35.458 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.28.20:5700/3) TRXD header version 1 -> 1
2026-01-29 01:40:35.460 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.28.20:5700) Recv RXTUNE cmd
2026-01-29 01:40:35.460 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETTSC
2026-01-29 01:40:35.460 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETTSC
2026-01-29 01:40:35.460 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETTSC
2026-01-29 01:40:35.460 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.28.20:5700) Recv TXTUNE cmd
2026-01-29 01:40:35.461 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETRXGAIN
2026-01-29 01:40:35.461 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETRXGAIN
2026-01-29 01:40:35.461 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETRXGAIN
2026-01-29 01:40:35.461 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETTSC
2026-01-29 01:40:35.461 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:40:35.461 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:40:35.461 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:40:35.461 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.28.20:5700) Recv NOMTXPOWER cmd
2026-01-29 01:40:35.461 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:40:35.461 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:40:35.461 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:40:35.461 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.28.20:5700) Recv POWERON CMD
2026-01-29 01:40:35.461 [INFO] ctrl_if_trx.py:109 (BTS@172.18.28.20:5700) Starting transceiver...
2026-01-29 01:40:35.461 [INFO] transceiver.py:243 Starting clock generator
2026-01-29 01:40:35.461 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-01-29 01:40:35.461 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:40:35.461 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:40:35.461 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:40:35.461 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETRXGAIN
2026-01-29 01:40:35.462 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:40:35.462 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:40:35.462 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:40:35.462 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 01:40:35.462 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:40:35.462 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:40:35.462 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:40:35.462 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 01:40:35.462 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:40:35.462 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:40:35.462 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:40:35.462 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 01:40:35.462 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:40:35.462 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:40:35.462 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:40:35.462 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 01:40:35.462 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:40:35.462 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:40:35.462 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:40:35.462 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 01:40:35.462 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 01:40:35.462 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 01:40:35.463 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 01:40:35.466 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-01-29 01:40:35.949 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-01-29 01:40:35.996 [DEBUG] fake_trx.py:278 (BTS@172.18.28.20:5700) Recv FAKE_TOA cmd
2026-01-29 01:40:35.999 [DEBUG] fake_trx.py:297 (BTS@172.18.28.20:5700) Recv FAKE_RSSI cmd
2026-01-29 01:40:36.000 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:40:36.003 [DEBUG] fake_trx.py:322 (BTS@172.18.28.20:5700) Recv FAKE_CI cmd
2026-01-29 01:40:36.008 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 01:40:36.008 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 01:40:36.009 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 01:40:36.010 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 01:40:36.010 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 01:40:36.011 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 01:40:36.011 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.28.22:6700) Recv POWERON CMD
2026-01-29 01:40:36.011 [INFO] ctrl_if_trx.py:109 (MS@172.18.28.22:6700) Starting transceiver...
2026-01-29 01:40:36.426 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-01-29 01:40:36.464 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 01:40:36.464 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 01:40:36.466 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 01:40:36.469 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 01:40:36.898 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-01-29 01:40:37.369 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-01-29 01:40:37.465 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 01:40:37.465 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 01:40:37.467 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 01:40:37.469 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 01:40:37.839 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-01-29 01:40:38.310 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-01-29 01:40:38.466 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 01:40:38.466 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 01:40:38.468 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 01:40:38.469 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 01:40:38.781 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-01-29 01:40:39.255 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-01-29 01:40:39.466 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 01:40:39.467 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 01:40:39.469 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 01:40:39.470 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 01:40:39.729 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-01-29 01:40:40.201 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-01-29 01:40:40.467 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 01:40:40.468 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 01:40:40.469 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 01:40:40.471 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 01:40:40.672 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-01-29 01:40:41.143 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-01-29 01:40:41.618 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-01-29 01:40:42.091 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-01-29 01:40:42.561 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-01-29 01:40:43.032 [DEBUG] clck_gen.py:113 IND CLOCK 1632
2026-01-29 01:40:43.502 [DEBUG] clck_gen.py:113 IND CLOCK 1734
2026-01-29 01:40:43.973 [DEBUG] clck_gen.py:113 IND CLOCK 1836
2026-01-29 01:40:44.444 [DEBUG] clck_gen.py:113 IND CLOCK 1938
2026-01-29 01:40:44.786 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 01:40:44.786 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 01:40:44.793 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 01:40:44.793 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 01:40:44.793 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 01:40:44.793 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 01:40:44.799 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 01:40:44.799 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 01:40:44.799 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 01:40:44.800 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.28.20:5700) Recv POWEROFF cmd
2026-01-29 01:40:44.800 [INFO] ctrl_if_trx.py:117 (BTS@172.18.28.20:5700) Stopping transceiver...
2026-01-29 01:40:44.800 [INFO] transceiver.py:246 Stopping clock generator
2026-01-29 01:40:44.800 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 01:40:44.800 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=2015 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 01:40:49.796 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.28.20:5700) Recv POWEROFF cmd
2026-01-29 01:40:49.797 [INFO] ctrl_if_trx.py:117 (BTS@172.18.28.20:5700) Stopping transceiver...
2026-01-29 01:40:49.798 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 01:40:49.803 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 01:40:49.803 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 01:40:49.803 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 01:40:49.811 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 01:40:49.811 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.28.20:5700) Recv SETFORMAT cmd
2026-01-29 01:40:49.811 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.28.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 01:40:49.812 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.28.20:5700) Recv SETFORMAT cmd
2026-01-29 01:40:49.812 [INFO] ctrl_if_trx.py:201 (BTS@172.18.28.20:5700) TRXD header version 1 -> 1
2026-01-29 01:40:49.813 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.28.20:5700/1) Recv RXTUNE cmd
2026-01-29 01:40:49.814 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.28.20:5700/1) Recv TXTUNE cmd
2026-01-29 01:40:49.814 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.28.20:5700/1) Recv SETFORMAT cmd
2026-01-29 01:40:49.814 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.28.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 01:40:49.814 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 01:40:49.815 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.28.20:5700/1) Recv NOMTXPOWER cmd
2026-01-29 01:40:49.815 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.28.20:5700/1) Recv SETFORMAT cmd
2026-01-29 01:40:49.815 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.28.20:5700/1) TRXD header version 1 -> 1
2026-01-29 01:40:49.816 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.28.20:5700/2) Recv RXTUNE cmd
2026-01-29 01:40:49.816 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.28.20:5700/2) Recv TXTUNE cmd
2026-01-29 01:40:49.816 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.28.20:5700/2) Recv SETFORMAT cmd
2026-01-29 01:40:49.816 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.28.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 01:40:49.817 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 01:40:49.817 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.28.20:5700/2) Recv NOMTXPOWER cmd
2026-01-29 01:40:49.817 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.28.20:5700/2) Recv SETFORMAT cmd
2026-01-29 01:40:49.817 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.28.20:5700/2) TRXD header version 1 -> 1
2026-01-29 01:40:49.819 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.28.20:5700/3) Recv RXTUNE cmd
2026-01-29 01:40:49.819 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.28.20:5700/3) Recv TXTUNE cmd
2026-01-29 01:40:49.819 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.28.20:5700/3) Recv SETFORMAT cmd
2026-01-29 01:40:49.819 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.28.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 01:40:49.819 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 01:40:49.819 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.28.20:5700/3) Recv NOMTXPOWER cmd
2026-01-29 01:40:49.819 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.28.20:5700/3) Recv SETFORMAT cmd
2026-01-29 01:40:49.820 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.28.20:5700/3) TRXD header version 1 -> 1
2026-01-29 01:40:49.822 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.28.20:5700) Recv RXTUNE cmd
2026-01-29 01:40:49.822 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETTSC
2026-01-29 01:40:49.822 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETTSC
2026-01-29 01:40:49.822 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETTSC
2026-01-29 01:40:49.822 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.28.20:5700) Recv TXTUNE cmd
2026-01-29 01:40:49.822 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETRXGAIN
2026-01-29 01:40:49.822 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETRXGAIN
2026-01-29 01:40:49.823 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETRXGAIN
2026-01-29 01:40:49.823 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETTSC
2026-01-29 01:40:49.823 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:40:49.823 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:40:49.823 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:40:49.823 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.28.20:5700) Recv NOMTXPOWER cmd
2026-01-29 01:40:49.823 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:40:49.823 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:40:49.823 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:40:49.823 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.28.20:5700) Recv POWERON CMD
2026-01-29 01:40:49.823 [INFO] ctrl_if_trx.py:109 (BTS@172.18.28.20:5700) Starting transceiver...
2026-01-29 01:40:49.823 [INFO] transceiver.py:243 Starting clock generator
2026-01-29 01:40:49.823 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-01-29 01:40:49.823 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:40:49.823 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:40:49.823 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:40:49.823 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETRXGAIN
2026-01-29 01:40:49.823 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:40:49.823 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:40:49.823 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:40:49.823 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 01:40:49.823 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:40:49.824 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:40:49.824 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:40:49.824 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 01:40:49.824 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:40:49.824 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:40:49.824 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:40:49.824 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 01:40:49.824 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:40:49.824 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:40:49.824 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:40:49.824 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 01:40:49.824 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:40:49.824 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:40:49.824 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:40:49.824 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 01:40:49.824 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 01:40:49.824 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 01:40:49.824 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 01:40:49.828 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-01-29 01:40:50.310 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-01-29 01:40:50.353 [DEBUG] fake_trx.py:278 (BTS@172.18.28.20:5700) Recv FAKE_TOA cmd
2026-01-29 01:40:50.356 [DEBUG] fake_trx.py:297 (BTS@172.18.28.20:5700) Recv FAKE_RSSI cmd
2026-01-29 01:40:50.357 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:40:50.358 [DEBUG] fake_trx.py:322 (BTS@172.18.28.20:5700) Recv FAKE_CI cmd
2026-01-29 01:40:50.361 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 01:40:50.362 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 01:40:50.362 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 01:40:50.362 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 01:40:50.363 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 01:40:50.363 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 01:40:50.363 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.28.22:6700) Recv POWERON CMD
2026-01-29 01:40:50.363 [INFO] ctrl_if_trx.py:109 (MS@172.18.28.22:6700) Starting transceiver...
2026-01-29 01:40:50.785 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-01-29 01:40:50.826 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 01:40:50.826 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 01:40:50.826 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 01:40:50.828 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 01:40:51.263 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-01-29 01:40:51.740 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-01-29 01:40:51.827 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 01:40:51.827 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 01:40:51.827 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 01:40:51.829 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 01:40:52.212 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-01-29 01:40:52.685 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-01-29 01:40:52.828 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 01:40:52.829 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 01:40:52.829 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 01:40:52.830 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 01:40:53.161 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-01-29 01:40:53.630 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-01-29 01:40:53.830 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 01:40:53.830 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 01:40:53.830 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 01:40:53.830 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 01:40:54.103 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-01-29 01:40:54.575 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-01-29 01:40:54.830 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 01:40:54.830 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 01:40:54.831 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 01:40:54.831 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 01:40:55.046 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-01-29 01:40:55.517 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-01-29 01:40:55.988 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-01-29 01:40:56.458 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-01-29 01:40:56.929 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-01-29 01:40:57.400 [DEBUG] clck_gen.py:113 IND CLOCK 1632
2026-01-29 01:40:57.871 [DEBUG] clck_gen.py:113 IND CLOCK 1734
2026-01-29 01:40:58.341 [DEBUG] clck_gen.py:113 IND CLOCK 1836
2026-01-29 01:40:58.811 [DEBUG] clck_gen.py:113 IND CLOCK 1938
2026-01-29 01:40:59.186 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 01:40:59.186 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 01:40:59.192 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 01:40:59.192 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 01:40:59.192 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 01:40:59.193 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 01:40:59.200 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 01:40:59.200 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 01:40:59.200 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 01:40:59.200 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 01:40:59.200 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.28.20:5700) Recv POWEROFF cmd
2026-01-29 01:40:59.200 [INFO] ctrl_if_trx.py:117 (BTS@172.18.28.20:5700) Stopping transceiver...
2026-01-29 01:40:59.200 [INFO] transceiver.py:246 Stopping clock generator
2026-01-29 01:40:59.201 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=2022 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 01:40:59.201 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=2022 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 01:40:59.201 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=2022 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 01:40:59.201 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=2022 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 01:40:59.201 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=2022 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 01:40:59.201 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=2022 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 01:40:59.201 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=2023 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 01:40:59.201 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=2023 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 01:40:59.202 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=2023 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 01:40:59.202 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=2023 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 01:40:59.202 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=2023 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 01:40:59.202 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=2023 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 01:40:59.202 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=2023 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 01:40:59.202 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=2023 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 01:40:59.202 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=2024 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 01:40:59.202 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=2024 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 01:40:59.202 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=2024 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 01:40:59.202 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=2024 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 01:40:59.202 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=2024 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 01:40:59.202 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=2024 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 01:40:59.202 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=2024 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 01:40:59.203 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=2024 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 01:41:04.196 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.28.20:5700) Recv POWEROFF cmd
2026-01-29 01:41:04.196 [INFO] ctrl_if_trx.py:117 (BTS@172.18.28.20:5700) Stopping transceiver...
2026-01-29 01:41:04.198 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 01:41:04.200 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 01:41:04.202 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 01:41:04.205 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 01:41:04.215 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 01:41:04.216 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.28.20:5700) Recv SETFORMAT cmd
2026-01-29 01:41:04.216 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.28.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 01:41:04.216 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.28.20:5700) Recv SETFORMAT cmd
2026-01-29 01:41:04.216 [INFO] ctrl_if_trx.py:201 (BTS@172.18.28.20:5700) TRXD header version 1 -> 1
2026-01-29 01:41:04.218 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.28.20:5700/1) Recv RXTUNE cmd
2026-01-29 01:41:04.218 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.28.20:5700/1) Recv TXTUNE cmd
2026-01-29 01:41:04.219 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.28.20:5700/1) Recv SETFORMAT cmd
2026-01-29 01:41:04.219 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.28.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 01:41:04.219 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 01:41:04.220 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.28.20:5700/1) Recv NOMTXPOWER cmd
2026-01-29 01:41:04.220 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.28.20:5700/1) Recv SETFORMAT cmd
2026-01-29 01:41:04.220 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.28.20:5700/1) TRXD header version 1 -> 1
2026-01-29 01:41:04.221 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.28.20:5700/2) Recv RXTUNE cmd
2026-01-29 01:41:04.221 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.28.20:5700/2) Recv TXTUNE cmd
2026-01-29 01:41:04.222 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.28.20:5700/2) Recv SETFORMAT cmd
2026-01-29 01:41:04.222 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.28.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 01:41:04.222 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 01:41:04.222 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.28.20:5700/2) Recv NOMTXPOWER cmd
2026-01-29 01:41:04.222 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.28.20:5700/2) Recv SETFORMAT cmd
2026-01-29 01:41:04.222 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.28.20:5700/2) TRXD header version 1 -> 1
2026-01-29 01:41:04.224 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.28.20:5700/3) Recv RXTUNE cmd
2026-01-29 01:41:04.224 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.28.20:5700/3) Recv TXTUNE cmd
2026-01-29 01:41:04.224 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.28.20:5700/3) Recv SETFORMAT cmd
2026-01-29 01:41:04.224 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.28.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 01:41:04.224 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 01:41:04.225 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.28.20:5700/3) Recv NOMTXPOWER cmd
2026-01-29 01:41:04.225 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.28.20:5700/3) Recv SETFORMAT cmd
2026-01-29 01:41:04.225 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.28.20:5700/3) TRXD header version 1 -> 1
2026-01-29 01:41:04.227 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.28.20:5700) Recv RXTUNE cmd
2026-01-29 01:41:04.227 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETTSC
2026-01-29 01:41:04.227 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETTSC
2026-01-29 01:41:04.227 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETTSC
2026-01-29 01:41:04.228 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.28.20:5700) Recv TXTUNE cmd
2026-01-29 01:41:04.228 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETRXGAIN
2026-01-29 01:41:04.228 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETRXGAIN
2026-01-29 01:41:04.228 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETRXGAIN
2026-01-29 01:41:04.228 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETTSC
2026-01-29 01:41:04.228 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:41:04.228 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:41:04.228 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:41:04.228 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.28.20:5700) Recv NOMTXPOWER cmd
2026-01-29 01:41:04.228 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:41:04.228 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:41:04.228 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:41:04.228 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.28.20:5700) Recv POWERON CMD
2026-01-29 01:41:04.228 [INFO] ctrl_if_trx.py:109 (BTS@172.18.28.20:5700) Starting transceiver...
2026-01-29 01:41:04.228 [INFO] transceiver.py:243 Starting clock generator
2026-01-29 01:41:04.228 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-01-29 01:41:04.228 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:41:04.228 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:41:04.228 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:41:04.229 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETRXGAIN
2026-01-29 01:41:04.229 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:41:04.229 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:41:04.229 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 01:41:04.229 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:41:04.229 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:41:04.229 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:41:04.229 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 01:41:04.229 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:41:04.229 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:41:04.229 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:41:04.229 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 01:41:04.229 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:41:04.229 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:41:04.229 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:41:04.229 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 01:41:04.229 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:41:04.229 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:41:04.229 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 01:41:04.229 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:41:04.229 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:41:04.229 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 01:41:04.229 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 01:41:04.230 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 01:41:04.233 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-01-29 01:41:04.713 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-01-29 01:41:04.756 [DEBUG] fake_trx.py:278 (BTS@172.18.28.20:5700) Recv FAKE_TOA cmd
2026-01-29 01:41:04.759 [DEBUG] fake_trx.py:297 (BTS@172.18.28.20:5700) Recv FAKE_RSSI cmd
2026-01-29 01:41:04.760 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:41:04.761 [DEBUG] fake_trx.py:322 (BTS@172.18.28.20:5700) Recv FAKE_CI cmd
2026-01-29 01:41:04.764 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 01:41:04.764 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 01:41:04.764 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 01:41:05.183 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-01-29 01:41:05.231 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 01:41:05.231 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 01:41:05.233 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 01:41:05.235 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 01:41:05.651 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-01-29 01:41:05.765 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 01:41:05.766 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 01:41:05.766 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 01:41:05.766 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.28.22:6700) Recv POWERON CMD
2026-01-29 01:41:05.766 [INFO] ctrl_if_trx.py:109 (MS@172.18.28.22:6700) Starting transceiver...
2026-01-29 01:41:06.127 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-01-29 01:41:06.232 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 01:41:06.233 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 01:41:06.233 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 01:41:06.236 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 01:41:06.598 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-01-29 01:41:07.075 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-01-29 01:41:07.233 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 01:41:07.233 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 01:41:07.234 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 01:41:07.237 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 01:41:07.553 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-01-29 01:41:08.027 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-01-29 01:41:08.233 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 01:41:08.234 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 01:41:08.235 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 01:41:08.238 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 01:41:08.501 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-01-29 01:41:08.974 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-01-29 01:41:09.234 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 01:41:09.234 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 01:41:09.235 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 01:41:09.239 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 01:41:09.445 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-01-29 01:41:09.916 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-01-29 01:41:10.386 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-01-29 01:41:10.857 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-01-29 01:41:11.329 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-01-29 01:41:11.804 [DEBUG] clck_gen.py:113 IND CLOCK 1632
2026-01-29 01:41:12.276 [DEBUG] clck_gen.py:113 IND CLOCK 1734
2026-01-29 01:41:12.748 [DEBUG] clck_gen.py:113 IND CLOCK 1836
2026-01-29 01:41:13.219 [DEBUG] clck_gen.py:113 IND CLOCK 1938
2026-01-29 01:41:13.689 [DEBUG] clck_gen.py:113 IND CLOCK 2040
2026-01-29 01:41:14.159 [DEBUG] clck_gen.py:113 IND CLOCK 2142
2026-01-29 01:41:14.630 [DEBUG] clck_gen.py:113 IND CLOCK 2244
2026-01-29 01:41:15.108 [DEBUG] clck_gen.py:113 IND CLOCK 2346
2026-01-29 01:41:15.585 [DEBUG] clck_gen.py:113 IND CLOCK 2448
2026-01-29 01:41:16.063 [DEBUG] clck_gen.py:113 IND CLOCK 2550
2026-01-29 01:41:16.540 [DEBUG] clck_gen.py:113 IND CLOCK 2652
2026-01-29 01:41:17.018 [DEBUG] clck_gen.py:113 IND CLOCK 2754
2026-01-29 01:41:17.496 [DEBUG] clck_gen.py:113 IND CLOCK 2856
2026-01-29 01:41:17.581 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 01:41:17.581 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 01:41:17.589 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 01:41:17.589 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 01:41:17.589 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 01:41:17.589 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 01:41:17.590 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 01:41:17.590 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 01:41:17.590 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 01:41:17.590 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 01:41:17.591 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.28.20:5700) Recv POWEROFF cmd
2026-01-29 01:41:17.591 [INFO] ctrl_if_trx.py:117 (BTS@172.18.28.20:5700) Stopping transceiver...
2026-01-29 01:41:17.591 [INFO] transceiver.py:246 Stopping clock generator
2026-01-29 01:41:22.591 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.28.20:5700) Recv POWEROFF cmd
2026-01-29 01:41:22.591 [INFO] ctrl_if_trx.py:117 (BTS@172.18.28.20:5700) Stopping transceiver...
2026-01-29 01:41:22.593 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 01:41:22.594 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 01:41:22.595 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 01:41:22.595 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 01:41:22.602 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 01:41:22.602 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.28.20:5700) Recv SETFORMAT cmd
2026-01-29 01:41:22.602 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.28.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 01:41:22.603 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.28.20:5700) Recv SETFORMAT cmd
2026-01-29 01:41:22.603 [INFO] ctrl_if_trx.py:201 (BTS@172.18.28.20:5700) TRXD header version 1 -> 1
2026-01-29 01:41:22.605 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.28.20:5700/1) Recv RXTUNE cmd
2026-01-29 01:41:22.605 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.28.20:5700/1) Recv TXTUNE cmd
2026-01-29 01:41:22.605 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.28.20:5700/1) Recv SETFORMAT cmd
2026-01-29 01:41:22.605 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.28.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 01:41:22.606 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 01:41:22.606 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.28.20:5700/1) Recv NOMTXPOWER cmd
2026-01-29 01:41:22.606 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.28.20:5700/1) Recv SETFORMAT cmd
2026-01-29 01:41:22.607 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.28.20:5700/1) TRXD header version 1 -> 1
2026-01-29 01:41:22.607 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.28.20:5700/2) Recv RXTUNE cmd
2026-01-29 01:41:22.607 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.28.20:5700/2) Recv TXTUNE cmd
2026-01-29 01:41:22.607 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.28.20:5700/2) Recv SETFORMAT cmd
2026-01-29 01:41:22.607 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.28.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 01:41:22.607 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 01:41:22.608 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.28.20:5700/2) Recv NOMTXPOWER cmd
2026-01-29 01:41:22.608 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.28.20:5700/2) Recv SETFORMAT cmd
2026-01-29 01:41:22.608 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.28.20:5700/2) TRXD header version 1 -> 1
2026-01-29 01:41:22.609 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.28.20:5700/3) Recv RXTUNE cmd
2026-01-29 01:41:22.609 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.28.20:5700/3) Recv TXTUNE cmd
2026-01-29 01:41:22.609 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.28.20:5700/3) Recv SETFORMAT cmd
2026-01-29 01:41:22.609 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.28.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 01:41:22.610 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 01:41:22.610 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.28.20:5700/3) Recv NOMTXPOWER cmd
2026-01-29 01:41:22.610 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.28.20:5700/3) Recv SETFORMAT cmd
2026-01-29 01:41:22.610 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.28.20:5700/3) TRXD header version 1 -> 1
2026-01-29 01:41:22.612 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.28.20:5700) Recv RXTUNE cmd
2026-01-29 01:41:22.612 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETTSC
2026-01-29 01:41:22.612 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETTSC
2026-01-29 01:41:22.612 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETTSC
2026-01-29 01:41:22.612 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.28.20:5700) Recv TXTUNE cmd
2026-01-29 01:41:22.612 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETRXGAIN
2026-01-29 01:41:22.612 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETRXGAIN
2026-01-29 01:41:22.612 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETRXGAIN
2026-01-29 01:41:22.612 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETTSC
2026-01-29 01:41:22.612 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:41:22.612 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:41:22.612 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.28.20:5700) Recv NOMTXPOWER cmd
2026-01-29 01:41:22.612 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:41:22.612 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:41:22.612 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:41:22.612 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.28.20:5700) Recv POWERON CMD
2026-01-29 01:41:22.612 [INFO] ctrl_if_trx.py:109 (BTS@172.18.28.20:5700) Starting transceiver...
2026-01-29 01:41:22.612 [INFO] transceiver.py:243 Starting clock generator
2026-01-29 01:41:22.613 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-01-29 01:41:22.613 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:41:22.613 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:41:22.613 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:41:22.613 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETRXGAIN
2026-01-29 01:41:22.613 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:41:22.613 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:41:22.613 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:41:22.613 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 01:41:22.613 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:41:22.613 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:41:22.613 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:41:22.613 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 01:41:22.613 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:41:22.613 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:41:22.613 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:41:22.613 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 01:41:22.613 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:41:22.613 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:41:22.613 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 01:41:22.613 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:41:22.613 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 01:41:22.613 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:41:22.613 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:41:22.613 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:41:22.613 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 01:41:22.614 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:41:22.614 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 01:41:22.614 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 01:41:22.617 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-01-29 01:41:23.099 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-01-29 01:41:23.141 [DEBUG] fake_trx.py:278 (BTS@172.18.28.20:5700) Recv FAKE_TOA cmd
2026-01-29 01:41:23.144 [DEBUG] fake_trx.py:297 (BTS@172.18.28.20:5700) Recv FAKE_RSSI cmd
2026-01-29 01:41:23.145 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:41:23.146 [DEBUG] fake_trx.py:322 (BTS@172.18.28.20:5700) Recv FAKE_CI cmd
2026-01-29 01:41:23.150 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 01:41:23.150 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 01:41:23.151 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 01:41:23.151 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 01:41:23.152 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 01:41:23.152 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 01:41:23.153 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.28.22:6700) Recv POWERON CMD
2026-01-29 01:41:23.153 [INFO] ctrl_if_trx.py:109 (MS@172.18.28.22:6700) Starting transceiver...
2026-01-29 01:41:23.577 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-01-29 01:41:23.615 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 01:41:23.615 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 01:41:23.617 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 01:41:23.618 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 01:41:24.054 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-01-29 01:41:24.189 [DEBUG] fake_trx.py:278 (BTS@172.18.28.20:5700) Recv FAKE_TOA cmd
2026-01-29 01:41:24.532 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-01-29 01:41:24.615 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 01:41:24.616 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 01:41:24.618 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 01:41:24.620 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 01:41:24.735 [DEBUG] fake_trx.py:278 (BTS@172.18.28.20:5700) Recv FAKE_TOA cmd
2026-01-29 01:41:25.010 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-01-29 01:41:25.258 [DEBUG] fake_trx.py:278 (BTS@172.18.28.20:5700) Recv FAKE_TOA cmd
2026-01-29 01:41:25.488 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-01-29 01:41:25.617 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 01:41:25.617 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 01:41:25.620 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 01:41:25.621 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 01:41:25.965 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-01-29 01:41:26.443 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-01-29 01:41:26.618 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 01:41:26.618 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 01:41:26.620 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 01:41:26.622 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 01:41:26.921 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-01-29 01:41:27.280 [DEBUG] fake_trx.py:278 (BTS@172.18.28.20:5700) Recv FAKE_TOA cmd
2026-01-29 01:41:27.399 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-01-29 01:41:27.619 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 01:41:27.619 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 01:41:27.621 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 01:41:27.624 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 01:41:27.789 [DEBUG] fake_trx.py:278 (BTS@172.18.28.20:5700) Recv FAKE_TOA cmd
2026-01-29 01:41:27.877 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-01-29 01:41:28.315 [DEBUG] fake_trx.py:278 (BTS@172.18.28.20:5700) Recv FAKE_TOA cmd
2026-01-29 01:41:28.355 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-01-29 01:41:28.833 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-01-29 01:41:28.845 [DEBUG] fake_trx.py:278 (BTS@172.18.28.20:5700) Recv FAKE_TOA cmd
2026-01-29 01:41:29.310 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-01-29 01:41:29.788 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-01-29 01:41:30.266 [DEBUG] clck_gen.py:113 IND CLOCK 1632
2026-01-29 01:41:30.744 [DEBUG] clck_gen.py:113 IND CLOCK 1734
2026-01-29 01:41:30.868 [DEBUG] fake_trx.py:278 (BTS@172.18.28.20:5700) Recv FAKE_TOA cmd
2026-01-29 01:41:31.222 [DEBUG] clck_gen.py:113 IND CLOCK 1836
2026-01-29 01:41:31.700 [DEBUG] clck_gen.py:113 IND CLOCK 1938
2026-01-29 01:41:32.177 [DEBUG] clck_gen.py:113 IND CLOCK 2040
2026-01-29 01:41:32.655 [DEBUG] clck_gen.py:113 IND CLOCK 2142
2026-01-29 01:41:32.879 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 01:41:32.879 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 01:41:32.885 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 01:41:32.886 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 01:41:32.886 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 01:41:32.886 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 01:41:32.892 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 01:41:32.892 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 01:41:32.892 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 01:41:32.892 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.28.20:5700) Recv POWEROFF cmd
2026-01-29 01:41:32.892 [INFO] ctrl_if_trx.py:117 (BTS@172.18.28.20:5700) Stopping transceiver...
2026-01-29 01:41:32.892 [INFO] transceiver.py:246 Stopping clock generator
2026-01-29 01:41:32.893 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 01:41:32.893 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=2193 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 01:41:32.893 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=2193 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 01:41:37.890 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.28.20:5700) Recv POWEROFF cmd
2026-01-29 01:41:37.890 [INFO] ctrl_if_trx.py:117 (BTS@172.18.28.20:5700) Stopping transceiver...
2026-01-29 01:41:37.891 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 01:41:37.892 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 01:41:37.893 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 01:41:37.893 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 01:41:37.900 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 01:41:37.901 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.28.20:5700) Recv SETFORMAT cmd
2026-01-29 01:41:37.901 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.28.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 01:41:37.902 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.28.20:5700) Recv SETFORMAT cmd
2026-01-29 01:41:37.902 [INFO] ctrl_if_trx.py:201 (BTS@172.18.28.20:5700) TRXD header version 1 -> 1
2026-01-29 01:41:37.904 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.28.20:5700/1) Recv RXTUNE cmd
2026-01-29 01:41:37.904 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.28.20:5700/1) Recv TXTUNE cmd
2026-01-29 01:41:37.905 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.28.20:5700/1) Recv SETFORMAT cmd
2026-01-29 01:41:37.905 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.28.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 01:41:37.905 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 01:41:37.905 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.28.20:5700/1) Recv NOMTXPOWER cmd
2026-01-29 01:41:37.906 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.28.20:5700/1) Recv SETFORMAT cmd
2026-01-29 01:41:37.906 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.28.20:5700/1) TRXD header version 1 -> 1
2026-01-29 01:41:37.907 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.28.20:5700/2) Recv RXTUNE cmd
2026-01-29 01:41:37.907 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.28.20:5700/2) Recv TXTUNE cmd
2026-01-29 01:41:37.907 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.28.20:5700/2) Recv SETFORMAT cmd
2026-01-29 01:41:37.907 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.28.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 01:41:37.907 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 01:41:37.907 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.28.20:5700/2) Recv NOMTXPOWER cmd
2026-01-29 01:41:37.907 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.28.20:5700/2) Recv SETFORMAT cmd
2026-01-29 01:41:37.907 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.28.20:5700/2) TRXD header version 1 -> 1
2026-01-29 01:41:37.909 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.28.20:5700/3) Recv RXTUNE cmd
2026-01-29 01:41:37.909 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.28.20:5700/3) Recv TXTUNE cmd
2026-01-29 01:41:37.909 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.28.20:5700/3) Recv SETFORMAT cmd
2026-01-29 01:41:37.909 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.28.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 01:41:37.909 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 01:41:37.909 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.28.20:5700/3) Recv NOMTXPOWER cmd
2026-01-29 01:41:37.909 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.28.20:5700/3) Recv SETFORMAT cmd
2026-01-29 01:41:37.909 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.28.20:5700/3) TRXD header version 1 -> 1
2026-01-29 01:41:37.912 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.28.20:5700) Recv RXTUNE cmd
2026-01-29 01:41:37.912 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETTSC
2026-01-29 01:41:37.912 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETTSC
2026-01-29 01:41:37.912 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETTSC
2026-01-29 01:41:37.912 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.28.20:5700) Recv TXTUNE cmd
2026-01-29 01:41:37.912 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETRXGAIN
2026-01-29 01:41:37.912 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETRXGAIN
2026-01-29 01:41:37.912 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETRXGAIN
2026-01-29 01:41:37.912 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETTSC
2026-01-29 01:41:37.912 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:41:37.912 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:41:37.912 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.28.20:5700) Recv NOMTXPOWER cmd
2026-01-29 01:41:37.912 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:41:37.912 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:41:37.912 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:41:37.912 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.28.20:5700) Recv POWERON CMD
2026-01-29 01:41:37.912 [INFO] ctrl_if_trx.py:109 (BTS@172.18.28.20:5700) Starting transceiver...
2026-01-29 01:41:37.912 [INFO] transceiver.py:243 Starting clock generator
2026-01-29 01:41:37.912 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-01-29 01:41:37.912 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:41:37.912 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:41:37.912 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:41:37.913 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETRXGAIN
2026-01-29 01:41:37.913 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:41:37.913 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:41:37.913 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:41:37.913 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 01:41:37.913 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:41:37.913 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:41:37.913 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:41:37.913 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 01:41:37.913 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:41:37.913 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:41:37.913 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:41:37.913 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 01:41:37.913 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:41:37.913 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:41:37.913 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:41:37.913 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 01:41:37.913 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:41:37.913 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:41:37.913 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 01:41:37.913 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:41:37.913 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:41:37.913 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 01:41:37.913 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 01:41:37.913 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 01:41:37.917 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-01-29 01:41:38.399 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-01-29 01:41:38.440 [DEBUG] fake_trx.py:278 (BTS@172.18.28.20:5700) Recv FAKE_TOA cmd
2026-01-29 01:41:38.442 [DEBUG] fake_trx.py:297 (BTS@172.18.28.20:5700) Recv FAKE_RSSI cmd
2026-01-29 01:41:38.443 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:41:38.444 [DEBUG] fake_trx.py:322 (BTS@172.18.28.20:5700) Recv FAKE_CI cmd
2026-01-29 01:41:38.457 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 01:41:38.457 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 01:41:38.457 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 01:41:38.460 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 01:41:38.460 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 01:41:38.460 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 01:41:38.460 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.28.22:6700) Recv POWERON CMD
2026-01-29 01:41:38.460 [INFO] ctrl_if_trx.py:109 (MS@172.18.28.22:6700) Starting transceiver...
2026-01-29 01:41:38.496 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD HANDOVER
2026-01-29 01:41:38.502 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 01:41:38.502 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 01:41:38.503 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 01:41:38.503 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 01:41:38.562 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:41:38.566 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:41:38.568 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 01:41:38.569 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 01:41:38.569 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 01:41:38.586 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 01:41:38.586 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 01:41:38.586 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 01:41:38.587 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 01:41:38.587 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 01:41:38.587 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 01:41:38.587 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.28.22:6700) Recv POWERON CMD
2026-01-29 01:41:38.587 [INFO] ctrl_if_trx.py:109 (MS@172.18.28.22:6700) Starting transceiver...
2026-01-29 01:41:38.638 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD HANDOVER
2026-01-29 01:41:38.643 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 01:41:38.643 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 01:41:38.643 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 01:41:38.643 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 01:41:38.816 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:41:38.820 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:41:38.822 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 01:41:38.823 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 01:41:38.823 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 01:41:38.832 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 01:41:38.832 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 01:41:38.832 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 01:41:38.833 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 01:41:38.833 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 01:41:38.833 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 01:41:38.833 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.28.22:6700) Recv POWERON CMD
2026-01-29 01:41:38.833 [INFO] ctrl_if_trx.py:109 (MS@172.18.28.22:6700) Starting transceiver...
2026-01-29 01:41:38.873 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD HANDOVER
2026-01-29 01:41:38.874 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 01:41:38.874 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 01:41:38.874 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 01:41:38.874 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 01:41:38.876 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-01-29 01:41:38.914 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 01:41:38.915 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 01:41:38.916 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 01:41:38.918 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 01:41:39.085 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:41:39.089 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:41:39.092 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 01:41:39.092 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 01:41:39.092 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 01:41:39.102 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 01:41:39.102 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 01:41:39.102 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 01:41:39.103 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 01:41:39.103 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 01:41:39.103 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 01:41:39.103 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.28.22:6700) Recv POWERON CMD
2026-01-29 01:41:39.103 [INFO] ctrl_if_trx.py:109 (MS@172.18.28.22:6700) Starting transceiver...
2026-01-29 01:41:39.109 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD HANDOVER
2026-01-29 01:41:39.110 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 01:41:39.110 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 01:41:39.110 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 01:41:39.110 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 01:41:39.112 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:41:39.113 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:41:39.114 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 01:41:39.114 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 01:41:39.114 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 01:41:39.123 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 01:41:39.123 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 01:41:39.123 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 01:41:39.124 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 01:41:39.124 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 01:41:39.124 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 01:41:39.125 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.28.22:6700) Recv POWERON CMD
2026-01-29 01:41:39.125 [INFO] ctrl_if_trx.py:109 (MS@172.18.28.22:6700) Starting transceiver...
2026-01-29 01:41:39.160 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD HANDOVER
2026-01-29 01:41:39.165 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 01:41:39.165 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 01:41:39.165 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 01:41:39.165 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 01:41:39.168 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:41:39.172 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:41:39.175 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 01:41:39.176 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 01:41:39.176 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 01:41:39.189 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 01:41:39.189 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 01:41:39.189 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 01:41:39.190 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 01:41:39.190 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 01:41:39.190 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 01:41:39.190 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.28.22:6700) Recv POWERON CMD
2026-01-29 01:41:39.190 [INFO] ctrl_if_trx.py:109 (MS@172.18.28.22:6700) Starting transceiver...
2026-01-29 01:41:39.201 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD HANDOVER
2026-01-29 01:41:39.203 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 01:41:39.203 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 01:41:39.203 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 01:41:39.203 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 01:41:39.204 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:41:39.206 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:41:39.207 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 01:41:39.207 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 01:41:39.207 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 01:41:39.216 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 01:41:39.216 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 01:41:39.217 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 01:41:39.217 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 01:41:39.218 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 01:41:39.218 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 01:41:39.218 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.28.22:6700) Recv POWERON CMD
2026-01-29 01:41:39.218 [INFO] ctrl_if_trx.py:109 (MS@172.18.28.22:6700) Starting transceiver...
2026-01-29 01:41:39.252 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD HANDOVER
2026-01-29 01:41:39.256 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 01:41:39.256 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 01:41:39.256 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 01:41:39.257 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 01:41:39.260 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:41:39.264 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:41:39.266 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 01:41:39.267 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 01:41:39.267 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 01:41:39.283 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 01:41:39.284 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 01:41:39.284 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 01:41:39.285 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 01:41:39.285 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 01:41:39.285 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 01:41:39.285 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.28.22:6700) Recv POWERON CMD
2026-01-29 01:41:39.285 [INFO] ctrl_if_trx.py:109 (MS@172.18.28.22:6700) Starting transceiver...
2026-01-29 01:41:39.293 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 01:41:39.293 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD HANDOVER
2026-01-29 01:41:39.294 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 01:41:39.294 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 01:41:39.294 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 01:41:39.294 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 01:41:39.306 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:41:39.308 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:41:39.310 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 01:41:39.310 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 01:41:39.310 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 01:41:39.323 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 01:41:39.323 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 01:41:39.323 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 01:41:39.324 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 01:41:39.324 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 01:41:39.324 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 01:41:39.325 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.28.22:6700) Recv POWERON CMD
2026-01-29 01:41:39.325 [INFO] ctrl_if_trx.py:109 (MS@172.18.28.22:6700) Starting transceiver...
2026-01-29 01:41:39.347 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD HANDOVER
2026-01-29 01:41:39.349 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-01-29 01:41:39.351 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 01:41:39.352 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 01:41:39.352 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 01:41:39.352 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 01:41:39.357 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:41:39.361 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:41:39.364 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 01:41:39.364 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 01:41:39.365 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 01:41:39.377 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 01:41:39.377 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 01:41:39.377 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 01:41:39.378 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 01:41:39.378 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 01:41:39.378 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 01:41:39.378 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.28.22:6700) Recv POWERON CMD
2026-01-29 01:41:39.378 [INFO] ctrl_if_trx.py:109 (MS@172.18.28.22:6700) Starting transceiver...
2026-01-29 01:41:39.390 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 01:41:39.390 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD HANDOVER
2026-01-29 01:41:39.391 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 01:41:39.391 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 01:41:39.391 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 01:41:39.391 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 01:41:39.393 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:41:39.394 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:41:39.395 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 01:41:39.395 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 01:41:39.395 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 01:41:39.404 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 01:41:39.404 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 01:41:39.404 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 01:41:39.405 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 01:41:39.405 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 01:41:39.405 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 01:41:39.405 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.28.22:6700) Recv POWERON CMD
2026-01-29 01:41:39.405 [INFO] ctrl_if_trx.py:109 (MS@172.18.28.22:6700) Starting transceiver...
2026-01-29 01:41:39.442 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD HANDOVER
2026-01-29 01:41:39.446 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 01:41:39.446 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 01:41:39.447 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 01:41:39.447 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 01:41:39.454 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:41:39.458 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:41:39.460 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 01:41:39.461 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 01:41:39.461 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 01:41:39.476 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 01:41:39.476 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 01:41:39.476 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 01:41:39.477 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 01:41:39.477 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 01:41:39.477 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 01:41:39.477 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.28.22:6700) Recv POWERON CMD
2026-01-29 01:41:39.477 [INFO] ctrl_if_trx.py:109 (MS@172.18.28.22:6700) Starting transceiver...
2026-01-29 01:41:39.482 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD HANDOVER
2026-01-29 01:41:39.483 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 01:41:39.483 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 01:41:39.483 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 01:41:39.483 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 01:41:39.491 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:41:39.492 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:41:39.493 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 01:41:39.493 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 01:41:39.493 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 01:41:39.504 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 01:41:39.504 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 01:41:39.504 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 01:41:39.505 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 01:41:39.505 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 01:41:39.506 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 01:41:39.506 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.28.22:6700) Recv POWERON CMD
2026-01-29 01:41:39.506 [INFO] ctrl_if_trx.py:109 (MS@172.18.28.22:6700) Starting transceiver...
2026-01-29 01:41:39.533 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD HANDOVER
2026-01-29 01:41:39.537 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 01:41:39.537 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 01:41:39.538 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 01:41:39.538 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 01:41:39.644 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:41:39.649 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:41:39.652 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 01:41:39.653 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 01:41:39.653 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 01:41:39.662 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 01:41:39.662 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 01:41:39.662 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 01:41:39.663 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 01:41:39.663 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 01:41:39.663 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 01:41:39.663 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.28.22:6700) Recv POWERON CMD
2026-01-29 01:41:39.663 [INFO] ctrl_if_trx.py:109 (MS@172.18.28.22:6700) Starting transceiver...
2026-01-29 01:41:39.672 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD HANDOVER
2026-01-29 01:41:39.673 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 01:41:39.674 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 01:41:39.674 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 01:41:39.674 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 01:41:39.675 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:41:39.677 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:41:39.678 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 01:41:39.678 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 01:41:39.678 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 01:41:39.688 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 01:41:39.688 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 01:41:39.688 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 01:41:39.689 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 01:41:39.689 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 01:41:39.689 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 01:41:39.689 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.28.22:6700) Recv POWERON CMD
2026-01-29 01:41:39.689 [INFO] ctrl_if_trx.py:109 (MS@172.18.28.22:6700) Starting transceiver...
2026-01-29 01:41:39.723 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD HANDOVER
2026-01-29 01:41:39.728 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 01:41:39.728 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 01:41:39.728 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 01:41:39.728 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 01:41:39.819 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-01-29 01:41:39.915 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 01:41:39.916 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 01:41:39.917 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:41:39.917 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 01:41:39.919 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 01:41:39.920 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:41:39.923 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 01:41:39.923 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 01:41:39.923 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 01:41:39.942 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 01:41:39.942 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 01:41:39.942 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 01:41:39.944 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 01:41:39.944 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 01:41:39.944 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 01:41:39.944 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.28.22:6700) Recv POWERON CMD
2026-01-29 01:41:39.944 [INFO] ctrl_if_trx.py:109 (MS@172.18.28.22:6700) Starting transceiver...
2026-01-29 01:41:39.954 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD HANDOVER
2026-01-29 01:41:39.955 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 01:41:39.955 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 01:41:39.955 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 01:41:39.955 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 01:41:40.170 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:41:40.174 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:41:40.177 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 01:41:40.177 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 01:41:40.177 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 01:41:40.196 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 01:41:40.196 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 01:41:40.196 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 01:41:40.198 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 01:41:40.198 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 01:41:40.198 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 01:41:40.198 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.28.22:6700) Recv POWERON CMD
2026-01-29 01:41:40.198 [INFO] ctrl_if_trx.py:109 (MS@172.18.28.22:6700) Starting transceiver...
2026-01-29 01:41:40.240 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD HANDOVER
2026-01-29 01:41:40.245 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 01:41:40.245 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 01:41:40.245 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 01:41:40.246 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 01:41:40.296 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-01-29 01:41:40.431 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:41:40.435 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:41:40.437 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 01:41:40.438 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 01:41:40.438 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 01:41:40.456 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 01:41:40.456 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 01:41:40.457 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 01:41:40.458 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 01:41:40.458 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 01:41:40.458 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 01:41:40.458 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.28.22:6700) Recv POWERON CMD
2026-01-29 01:41:40.458 [INFO] ctrl_if_trx.py:109 (MS@172.18.28.22:6700) Starting transceiver...
2026-01-29 01:41:40.481 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD HANDOVER
2026-01-29 01:41:40.485 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 01:41:40.486 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 01:41:40.487 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 01:41:40.487 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 01:41:40.685 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:41:40.689 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:41:40.692 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 01:41:40.692 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 01:41:40.692 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 01:41:40.712 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 01:41:40.712 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 01:41:40.712 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 01:41:40.713 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 01:41:40.713 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 01:41:40.714 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 01:41:40.714 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.28.22:6700) Recv POWERON CMD
2026-01-29 01:41:40.714 [INFO] ctrl_if_trx.py:109 (MS@172.18.28.22:6700) Starting transceiver...
2026-01-29 01:41:40.768 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD HANDOVER
2026-01-29 01:41:40.769 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 01:41:40.769 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 01:41:40.769 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 01:41:40.769 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 01:41:40.773 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-01-29 01:41:40.917 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 01:41:40.917 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 01:41:40.918 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 01:41:40.920 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 01:41:40.946 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:41:40.950 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:41:40.952 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 01:41:40.953 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 01:41:40.953 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 01:41:40.966 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 01:41:40.966 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 01:41:40.966 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 01:41:40.967 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 01:41:40.967 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 01:41:40.967 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 01:41:40.968 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.28.22:6700) Recv POWERON CMD
2026-01-29 01:41:40.968 [INFO] ctrl_if_trx.py:109 (MS@172.18.28.22:6700) Starting transceiver...
2026-01-29 01:41:41.011 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD HANDOVER
2026-01-29 01:41:41.012 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 01:41:41.012 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 01:41:41.012 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 01:41:41.012 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 01:41:41.200 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:41:41.204 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:41:41.207 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 01:41:41.207 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 01:41:41.207 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 01:41:41.218 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 01:41:41.218 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 01:41:41.218 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 01:41:41.218 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 01:41:41.223 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 01:41:41.223 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 01:41:41.223 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 01:41:41.224 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 01:41:41.224 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.28.20:5700) Recv POWEROFF cmd
2026-01-29 01:41:41.224 [INFO] ctrl_if_trx.py:117 (BTS@172.18.28.20:5700) Stopping transceiver...
2026-01-29 01:41:41.224 [INFO] transceiver.py:246 Stopping clock generator
2026-01-29 01:41:41.224 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=711 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 01:41:41.224 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=711 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 01:41:41.224 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=711 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 01:41:41.224 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=711 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 01:41:41.224 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=711 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 01:41:41.224 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=711 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 01:41:46.220 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.28.20:5700) Recv POWEROFF cmd
2026-01-29 01:41:46.220 [INFO] ctrl_if_trx.py:117 (BTS@172.18.28.20:5700) Stopping transceiver...
2026-01-29 01:41:46.222 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 01:41:46.222 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 01:41:46.222 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 01:41:46.223 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 01:41:46.226 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 01:41:46.226 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.28.20:5700) Recv SETFORMAT cmd
2026-01-29 01:41:46.227 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.28.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 01:41:46.227 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.28.20:5700) Recv SETFORMAT cmd
2026-01-29 01:41:46.227 [INFO] ctrl_if_trx.py:201 (BTS@172.18.28.20:5700) TRXD header version 1 -> 1
2026-01-29 01:41:46.228 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.28.20:5700/1) Recv RXTUNE cmd
2026-01-29 01:41:46.229 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.28.20:5700/1) Recv TXTUNE cmd
2026-01-29 01:41:46.229 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.28.20:5700/1) Recv SETFORMAT cmd
2026-01-29 01:41:46.229 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.28.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 01:41:46.229 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 01:41:46.229 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.28.20:5700/1) Recv NOMTXPOWER cmd
2026-01-29 01:41:46.230 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.28.20:5700/1) Recv SETFORMAT cmd
2026-01-29 01:41:46.230 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.28.20:5700/1) TRXD header version 1 -> 1
2026-01-29 01:41:46.230 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.28.20:5700/2) Recv RXTUNE cmd
2026-01-29 01:41:46.231 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.28.20:5700/2) Recv TXTUNE cmd
2026-01-29 01:41:46.231 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.28.20:5700/2) Recv SETFORMAT cmd
2026-01-29 01:41:46.231 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.28.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 01:41:46.231 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 01:41:46.231 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.28.20:5700/2) Recv NOMTXPOWER cmd
2026-01-29 01:41:46.231 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.28.20:5700/2) Recv SETFORMAT cmd
2026-01-29 01:41:46.231 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.28.20:5700/2) TRXD header version 1 -> 1
2026-01-29 01:41:46.232 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.28.20:5700/3) Recv RXTUNE cmd
2026-01-29 01:41:46.232 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.28.20:5700/3) Recv TXTUNE cmd
2026-01-29 01:41:46.232 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.28.20:5700/3) Recv SETFORMAT cmd
2026-01-29 01:41:46.232 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.28.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 01:41:46.232 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 01:41:46.232 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.28.20:5700/3) Recv NOMTXPOWER cmd
2026-01-29 01:41:46.233 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.28.20:5700/3) Recv SETFORMAT cmd
2026-01-29 01:41:46.233 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.28.20:5700/3) TRXD header version 1 -> 1
2026-01-29 01:41:46.234 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.28.20:5700) Recv RXTUNE cmd
2026-01-29 01:41:46.234 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETTSC
2026-01-29 01:41:46.234 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETTSC
2026-01-29 01:41:46.234 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETTSC
2026-01-29 01:41:46.234 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.28.20:5700) Recv TXTUNE cmd
2026-01-29 01:41:46.234 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETRXGAIN
2026-01-29 01:41:46.234 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETRXGAIN
2026-01-29 01:41:46.235 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETRXGAIN
2026-01-29 01:41:46.235 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETTSC
2026-01-29 01:41:46.235 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:41:46.235 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:41:46.235 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:41:46.235 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.28.20:5700) Recv NOMTXPOWER cmd
2026-01-29 01:41:46.235 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:41:46.235 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:41:46.235 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:41:46.235 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.28.20:5700) Recv POWERON CMD
2026-01-29 01:41:46.235 [INFO] ctrl_if_trx.py:109 (BTS@172.18.28.20:5700) Starting transceiver...
2026-01-29 01:41:46.235 [INFO] transceiver.py:243 Starting clock generator
2026-01-29 01:41:46.235 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-01-29 01:41:46.235 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:41:46.235 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:41:46.235 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:41:46.235 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETRXGAIN
2026-01-29 01:41:46.235 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:41:46.235 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:41:46.235 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 01:41:46.235 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:41:46.235 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:41:46.235 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:41:46.235 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 01:41:46.235 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:41:46.235 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:41:46.235 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:41:46.235 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 01:41:46.235 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:41:46.235 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:41:46.236 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:41:46.236 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 01:41:46.236 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:41:46.236 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:41:46.236 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:41:46.236 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 01:41:46.236 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:41:46.236 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 01:41:46.236 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 01:41:46.236 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 01:41:46.240 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-01-29 01:41:46.724 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-01-29 01:41:46.760 [DEBUG] fake_trx.py:278 (BTS@172.18.28.20:5700) Recv FAKE_TOA cmd
2026-01-29 01:41:46.762 [DEBUG] fake_trx.py:297 (BTS@172.18.28.20:5700) Recv FAKE_RSSI cmd
2026-01-29 01:41:46.764 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:41:46.765 [DEBUG] fake_trx.py:322 (BTS@172.18.28.20:5700) Recv FAKE_CI cmd
2026-01-29 01:41:46.784 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 01:41:46.785 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 01:41:46.785 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 01:41:46.790 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 01:41:46.790 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 01:41:46.791 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 01:41:46.791 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.28.22:6700) Recv POWERON CMD
2026-01-29 01:41:46.791 [INFO] ctrl_if_trx.py:109 (MS@172.18.28.22:6700) Starting transceiver...
2026-01-29 01:41:46.821 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD HANDOVER
2026-01-29 01:41:46.826 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 01:41:46.827 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 01:41:46.827 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 01:41:46.827 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 01:41:46.882 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:41:47.201 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-01-29 01:41:47.238 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 01:41:47.238 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 01:41:47.238 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 01:41:47.240 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 01:41:47.679 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-01-29 01:41:48.157 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-01-29 01:41:48.238 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 01:41:48.239 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 01:41:48.239 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 01:41:48.240 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 01:41:48.635 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-01-29 01:41:48.885 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 01:41:48.885 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 01:41:48.889 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 01:41:48.890 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 01:41:48.890 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 01:41:48.890 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 01:41:48.891 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 01:41:48.891 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 01:41:48.891 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 01:41:48.891 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.28.20:5700) Recv POWEROFF cmd
2026-01-29 01:41:48.891 [INFO] ctrl_if_trx.py:117 (BTS@172.18.28.20:5700) Stopping transceiver...
2026-01-29 01:41:48.891 [INFO] transceiver.py:246 Stopping clock generator
2026-01-29 01:41:48.891 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 01:41:48.891 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=567 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 01:41:48.891 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=567 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 01:41:48.891 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=567 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 01:41:48.891 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=567 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 01:41:48.891 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=567 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 01:41:48.891 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=567 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 01:41:48.891 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=567 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 01:41:48.891 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=567 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 01:41:53.893 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.28.20:5700) Recv POWEROFF cmd
2026-01-29 01:41:53.893 [INFO] ctrl_if_trx.py:117 (BTS@172.18.28.20:5700) Stopping transceiver...
2026-01-29 01:41:53.897 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 01:41:53.897 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 01:41:53.897 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 01:41:53.897 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 01:41:53.906 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 01:41:53.907 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.28.20:5700) Recv SETFORMAT cmd
2026-01-29 01:41:53.907 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.28.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 01:41:53.908 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.28.20:5700) Recv SETFORMAT cmd
2026-01-29 01:41:53.908 [INFO] ctrl_if_trx.py:201 (BTS@172.18.28.20:5700) TRXD header version 1 -> 1
2026-01-29 01:41:53.912 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.28.20:5700/1) Recv RXTUNE cmd
2026-01-29 01:41:53.913 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.28.20:5700/1) Recv TXTUNE cmd
2026-01-29 01:41:53.913 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.28.20:5700/1) Recv SETFORMAT cmd
2026-01-29 01:41:53.913 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.28.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 01:41:53.913 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 01:41:53.913 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.28.20:5700/1) Recv NOMTXPOWER cmd
2026-01-29 01:41:53.914 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.28.20:5700/1) Recv SETFORMAT cmd
2026-01-29 01:41:53.914 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.28.20:5700/1) TRXD header version 1 -> 1
2026-01-29 01:41:53.917 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.28.20:5700/2) Recv RXTUNE cmd
2026-01-29 01:41:53.917 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.28.20:5700/2) Recv TXTUNE cmd
2026-01-29 01:41:53.917 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.28.20:5700/2) Recv SETFORMAT cmd
2026-01-29 01:41:53.917 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.28.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 01:41:53.917 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 01:41:53.917 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.28.20:5700/2) Recv NOMTXPOWER cmd
2026-01-29 01:41:53.917 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.28.20:5700/2) Recv SETFORMAT cmd
2026-01-29 01:41:53.917 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.28.20:5700/2) TRXD header version 1 -> 1
2026-01-29 01:41:53.920 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.28.20:5700/3) Recv RXTUNE cmd
2026-01-29 01:41:53.920 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.28.20:5700/3) Recv TXTUNE cmd
2026-01-29 01:41:53.920 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.28.20:5700/3) Recv SETFORMAT cmd
2026-01-29 01:41:53.920 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.28.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 01:41:53.920 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 01:41:53.920 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.28.20:5700/3) Recv NOMTXPOWER cmd
2026-01-29 01:41:53.920 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.28.20:5700/3) Recv SETFORMAT cmd
2026-01-29 01:41:53.920 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.28.20:5700/3) TRXD header version 1 -> 1
2026-01-29 01:41:53.923 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.28.20:5700) Recv RXTUNE cmd
2026-01-29 01:41:53.923 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETTSC
2026-01-29 01:41:53.923 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETTSC
2026-01-29 01:41:53.923 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETTSC
2026-01-29 01:41:53.923 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.28.20:5700) Recv TXTUNE cmd
2026-01-29 01:41:53.923 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETRXGAIN
2026-01-29 01:41:53.924 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETRXGAIN
2026-01-29 01:41:53.924 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETRXGAIN
2026-01-29 01:41:53.924 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETTSC
2026-01-29 01:41:53.924 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:41:53.924 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:41:53.924 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.28.20:5700) Recv NOMTXPOWER cmd
2026-01-29 01:41:53.924 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:41:53.924 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:41:53.924 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:41:53.924 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.28.20:5700) Recv POWERON CMD
2026-01-29 01:41:53.924 [INFO] ctrl_if_trx.py:109 (BTS@172.18.28.20:5700) Starting transceiver...
2026-01-29 01:41:53.924 [INFO] transceiver.py:243 Starting clock generator
2026-01-29 01:41:53.924 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-01-29 01:41:53.924 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:41:53.924 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:41:53.924 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:41:53.924 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETRXGAIN
2026-01-29 01:41:53.926 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:41:53.926 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 01:41:53.926 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:41:53.926 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:41:53.926 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 01:41:53.926 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:41:53.926 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:41:53.926 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 01:41:53.926 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:41:53.926 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:41:53.926 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 01:41:53.926 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:41:53.926 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:41:53.926 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 01:41:53.926 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:41:53.926 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:41:53.926 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 01:41:53.926 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 01:41:53.926 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:41:53.926 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 01:41:53.926 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:41:53.926 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 01:41:53.926 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:41:53.926 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 01:41:53.926 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:41:53.926 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.28.20:5700) Recv POWEROFF cmd
2026-01-29 01:41:53.926 [INFO] ctrl_if_trx.py:117 (BTS@172.18.28.20:5700) Stopping transceiver...
2026-01-29 01:41:53.926 [INFO] transceiver.py:246 Stopping clock generator
2026-01-29 01:41:53.926 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 01:41:53.926 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:41:58.929 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.28.20:5700) Recv POWEROFF cmd
2026-01-29 01:41:58.929 [INFO] ctrl_if_trx.py:117 (BTS@172.18.28.20:5700) Stopping transceiver...
2026-01-29 01:41:58.931 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 01:41:58.932 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 01:41:58.933 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 01:41:58.934 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 01:41:58.942 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 01:41:58.943 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.28.20:5700) Recv SETFORMAT cmd
2026-01-29 01:41:58.943 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.28.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 01:41:58.943 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.28.20:5700) Recv SETFORMAT cmd
2026-01-29 01:41:58.943 [INFO] ctrl_if_trx.py:201 (BTS@172.18.28.20:5700) TRXD header version 1 -> 1
2026-01-29 01:41:58.946 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.28.20:5700/1) Recv RXTUNE cmd
2026-01-29 01:41:58.946 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.28.20:5700/1) Recv TXTUNE cmd
2026-01-29 01:41:58.947 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.28.20:5700/1) Recv SETFORMAT cmd
2026-01-29 01:41:58.947 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.28.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 01:41:58.947 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 01:41:58.947 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.28.20:5700/1) Recv NOMTXPOWER cmd
2026-01-29 01:41:58.948 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.28.20:5700/1) Recv SETFORMAT cmd
2026-01-29 01:41:58.948 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.28.20:5700/1) TRXD header version 1 -> 1
2026-01-29 01:41:58.949 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.28.20:5700/2) Recv RXTUNE cmd
2026-01-29 01:41:58.949 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.28.20:5700/2) Recv TXTUNE cmd
2026-01-29 01:41:58.949 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.28.20:5700/2) Recv SETFORMAT cmd
2026-01-29 01:41:58.949 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.28.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 01:41:58.949 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 01:41:58.950 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.28.20:5700/2) Recv NOMTXPOWER cmd
2026-01-29 01:41:58.950 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.28.20:5700/2) Recv SETFORMAT cmd
2026-01-29 01:41:58.950 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.28.20:5700/2) TRXD header version 1 -> 1
2026-01-29 01:41:58.952 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.28.20:5700/3) Recv RXTUNE cmd
2026-01-29 01:41:58.952 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.28.20:5700/3) Recv TXTUNE cmd
2026-01-29 01:41:58.953 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.28.20:5700/3) Recv SETFORMAT cmd
2026-01-29 01:41:58.953 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.28.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 01:41:58.953 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 01:41:58.953 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.28.20:5700/3) Recv NOMTXPOWER cmd
2026-01-29 01:41:58.953 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.28.20:5700/3) Recv SETFORMAT cmd
2026-01-29 01:41:58.953 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.28.20:5700/3) TRXD header version 1 -> 1
2026-01-29 01:41:58.956 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.28.20:5700) Recv RXTUNE cmd
2026-01-29 01:41:58.956 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETTSC
2026-01-29 01:41:58.956 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETTSC
2026-01-29 01:41:58.956 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETTSC
2026-01-29 01:41:58.956 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.28.20:5700) Recv TXTUNE cmd
2026-01-29 01:41:58.956 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETRXGAIN
2026-01-29 01:41:58.956 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETRXGAIN
2026-01-29 01:41:58.957 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETRXGAIN
2026-01-29 01:41:58.957 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETTSC
2026-01-29 01:41:58.957 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:41:58.957 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:41:58.957 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:41:58.957 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.28.20:5700) Recv NOMTXPOWER cmd
2026-01-29 01:41:58.957 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:41:58.957 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:41:58.957 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:41:58.957 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.28.20:5700) Recv POWERON CMD
2026-01-29 01:41:58.957 [INFO] ctrl_if_trx.py:109 (BTS@172.18.28.20:5700) Starting transceiver...
2026-01-29 01:41:58.957 [INFO] transceiver.py:243 Starting clock generator
2026-01-29 01:41:58.957 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-01-29 01:41:58.957 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:41:58.957 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:41:58.957 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:41:58.957 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETRXGAIN
2026-01-29 01:41:58.958 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:41:58.958 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:41:58.958 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:41:58.958 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 01:41:58.958 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:41:58.958 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:41:58.958 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:41:58.958 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 01:41:58.958 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:41:58.958 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:41:58.958 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:41:58.958 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 01:41:58.958 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:41:58.958 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:41:58.958 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:41:58.958 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 01:41:58.958 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:41:58.958 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:41:58.958 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:41:58.958 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 01:41:58.958 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 01:41:58.959 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 01:41:58.959 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 01:41:58.962 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-01-29 01:41:59.447 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-01-29 01:41:59.481 [DEBUG] fake_trx.py:278 (BTS@172.18.28.20:5700) Recv FAKE_TOA cmd
2026-01-29 01:41:59.482 [DEBUG] fake_trx.py:297 (BTS@172.18.28.20:5700) Recv FAKE_RSSI cmd
2026-01-29 01:41:59.483 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:41:59.483 [DEBUG] fake_trx.py:322 (BTS@172.18.28.20:5700) Recv FAKE_CI cmd
2026-01-29 01:41:59.924 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-01-29 01:41:59.960 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 01:41:59.961 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 01:41:59.961 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 01:41:59.965 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 01:42:00.402 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-01-29 01:42:00.883 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-01-29 01:42:00.962 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 01:42:00.962 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 01:42:00.962 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 01:42:00.967 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 01:42:01.360 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-01-29 01:42:01.829 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-01-29 01:42:01.962 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 01:42:01.963 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 01:42:01.963 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 01:42:01.968 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 01:42:02.300 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-01-29 01:42:02.780 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-01-29 01:42:02.963 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 01:42:02.964 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 01:42:02.964 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 01:42:02.969 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 01:42:03.249 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-01-29 01:42:03.718 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-01-29 01:42:03.965 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 01:42:03.965 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 01:42:03.966 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 01:42:03.971 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 01:42:04.191 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-01-29 01:42:04.660 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-01-29 01:42:05.002 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 01:42:05.003 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 01:42:05.003 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 01:42:05.003 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 01:42:05.004 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 01:42:05.004 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 01:42:05.004 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 01:42:05.004 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.28.20:5700) Recv POWEROFF cmd
2026-01-29 01:42:05.004 [INFO] ctrl_if_trx.py:117 (BTS@172.18.28.20:5700) Stopping transceiver...
2026-01-29 01:42:05.004 [INFO] transceiver.py:246 Stopping clock generator
2026-01-29 01:42:05.004 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 01:42:10.004 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.28.20:5700) Recv POWEROFF cmd
2026-01-29 01:42:10.004 [INFO] ctrl_if_trx.py:117 (BTS@172.18.28.20:5700) Stopping transceiver...
2026-01-29 01:42:10.006 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 01:42:10.007 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 01:42:10.008 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 01:42:10.008 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 01:42:10.017 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 01:42:10.018 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.28.20:5700) Recv SETFORMAT cmd
2026-01-29 01:42:10.018 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.28.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 01:42:10.019 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.28.20:5700) Recv SETFORMAT cmd
2026-01-29 01:42:10.019 [INFO] ctrl_if_trx.py:201 (BTS@172.18.28.20:5700) TRXD header version 1 -> 1
2026-01-29 01:42:10.023 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.28.20:5700/1) Recv RXTUNE cmd
2026-01-29 01:42:10.024 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.28.20:5700/1) Recv TXTUNE cmd
2026-01-29 01:42:10.024 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.28.20:5700/1) Recv SETFORMAT cmd
2026-01-29 01:42:10.025 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.28.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 01:42:10.025 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 01:42:10.025 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.28.20:5700/1) Recv NOMTXPOWER cmd
2026-01-29 01:42:10.026 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.28.20:5700/1) Recv SETFORMAT cmd
2026-01-29 01:42:10.026 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.28.20:5700/1) TRXD header version 1 -> 1
2026-01-29 01:42:10.028 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.28.20:5700/2) Recv RXTUNE cmd
2026-01-29 01:42:10.028 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.28.20:5700/2) Recv TXTUNE cmd
2026-01-29 01:42:10.029 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.28.20:5700/2) Recv SETFORMAT cmd
2026-01-29 01:42:10.029 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.28.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 01:42:10.029 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 01:42:10.029 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.28.20:5700/2) Recv NOMTXPOWER cmd
2026-01-29 01:42:10.029 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.28.20:5700/2) Recv SETFORMAT cmd
2026-01-29 01:42:10.029 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.28.20:5700/2) TRXD header version 1 -> 1
2026-01-29 01:42:10.031 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.28.20:5700/3) Recv RXTUNE cmd
2026-01-29 01:42:10.032 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.28.20:5700/3) Recv TXTUNE cmd
2026-01-29 01:42:10.032 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.28.20:5700/3) Recv SETFORMAT cmd
2026-01-29 01:42:10.032 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.28.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 01:42:10.032 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 01:42:10.032 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.28.20:5700/3) Recv NOMTXPOWER cmd
2026-01-29 01:42:10.032 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.28.20:5700/3) Recv SETFORMAT cmd
2026-01-29 01:42:10.032 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.28.20:5700/3) TRXD header version 1 -> 1
2026-01-29 01:42:10.035 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.28.20:5700) Recv RXTUNE cmd
2026-01-29 01:42:10.035 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETTSC
2026-01-29 01:42:10.035 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETTSC
2026-01-29 01:42:10.036 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETTSC
2026-01-29 01:42:10.036 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.28.20:5700) Recv TXTUNE cmd
2026-01-29 01:42:10.036 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETRXGAIN
2026-01-29 01:42:10.036 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETRXGAIN
2026-01-29 01:42:10.036 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETRXGAIN
2026-01-29 01:42:10.036 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETTSC
2026-01-29 01:42:10.036 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:42:10.036 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:42:10.036 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.28.20:5700) Recv NOMTXPOWER cmd
2026-01-29 01:42:10.036 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:42:10.036 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:42:10.036 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:42:10.036 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.28.20:5700) Recv POWERON CMD
2026-01-29 01:42:10.036 [INFO] ctrl_if_trx.py:109 (BTS@172.18.28.20:5700) Starting transceiver...
2026-01-29 01:42:10.036 [INFO] transceiver.py:243 Starting clock generator
2026-01-29 01:42:10.036 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-01-29 01:42:10.037 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:42:10.037 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:42:10.037 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:42:10.037 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETRXGAIN
2026-01-29 01:42:10.037 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:42:10.037 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:42:10.037 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:42:10.037 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 01:42:10.037 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:42:10.037 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:42:10.037 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:42:10.037 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 01:42:10.037 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:42:10.037 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:42:10.037 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:42:10.038 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 01:42:10.038 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:42:10.038 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:42:10.038 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:42:10.038 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 01:42:10.038 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:42:10.038 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:42:10.038 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:42:10.038 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 01:42:10.038 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:42:10.038 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 01:42:10.038 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 01:42:10.038 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 01:42:10.041 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-01-29 01:42:10.523 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-01-29 01:42:10.562 [DEBUG] fake_trx.py:278 (BTS@172.18.28.20:5700) Recv FAKE_TOA cmd
2026-01-29 01:42:10.562 [DEBUG] fake_trx.py:297 (BTS@172.18.28.20:5700) Recv FAKE_RSSI cmd
2026-01-29 01:42:10.563 [DEBUG] fake_trx.py:322 (BTS@172.18.28.20:5700) Recv FAKE_CI cmd
2026-01-29 01:42:10.563 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:42:11.004 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-01-29 01:42:11.040 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 01:42:11.040 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 01:42:11.040 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 01:42:11.042 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 01:42:11.482 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-01-29 01:42:11.957 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-01-29 01:42:12.041 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 01:42:12.041 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 01:42:12.042 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 01:42:12.043 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 01:42:12.437 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-01-29 01:42:12.918 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-01-29 01:42:13.042 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 01:42:13.042 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 01:42:13.043 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 01:42:13.045 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 01:42:13.396 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-01-29 01:42:13.874 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-01-29 01:42:14.043 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 01:42:14.043 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 01:42:14.044 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 01:42:14.046 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 01:42:14.355 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-01-29 01:42:14.836 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-01-29 01:42:15.044 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 01:42:15.070 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 01:42:15.070 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 01:42:15.070 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 01:42:15.317 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-01-29 01:42:15.574 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 01:42:15.574 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 01:42:15.575 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 01:42:15.575 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 01:42:15.576 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 01:42:15.576 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 01:42:15.576 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 01:42:15.576 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.28.20:5700) Recv POWEROFF cmd
2026-01-29 01:42:15.576 [INFO] ctrl_if_trx.py:117 (BTS@172.18.28.20:5700) Stopping transceiver...
2026-01-29 01:42:15.576 [INFO] transceiver.py:246 Stopping clock generator
2026-01-29 01:42:15.576 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 01:42:15.576 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=1179 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 01:42:15.576 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=1179 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 01:42:20.578 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.28.20:5700) Recv POWEROFF cmd
2026-01-29 01:42:20.578 [INFO] ctrl_if_trx.py:117 (BTS@172.18.28.20:5700) Stopping transceiver...
2026-01-29 01:42:20.580 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 01:42:20.581 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 01:42:20.581 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 01:42:20.582 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 01:42:20.588 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 01:42:20.589 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.28.20:5700) Recv SETFORMAT cmd
2026-01-29 01:42:20.589 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.28.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 01:42:20.589 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.28.20:5700) Recv SETFORMAT cmd
2026-01-29 01:42:20.590 [INFO] ctrl_if_trx.py:201 (BTS@172.18.28.20:5700) TRXD header version 1 -> 1
2026-01-29 01:42:20.594 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.28.20:5700/1) Recv RXTUNE cmd
2026-01-29 01:42:20.594 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.28.20:5700/1) Recv TXTUNE cmd
2026-01-29 01:42:20.595 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.28.20:5700/1) Recv SETFORMAT cmd
2026-01-29 01:42:20.595 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.28.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 01:42:20.595 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 01:42:20.596 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.28.20:5700/1) Recv NOMTXPOWER cmd
2026-01-29 01:42:20.596 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.28.20:5700/1) Recv SETFORMAT cmd
2026-01-29 01:42:20.596 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.28.20:5700/1) TRXD header version 1 -> 1
2026-01-29 01:42:20.598 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.28.20:5700/2) Recv RXTUNE cmd
2026-01-29 01:42:20.598 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.28.20:5700/2) Recv TXTUNE cmd
2026-01-29 01:42:20.598 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.28.20:5700/2) Recv SETFORMAT cmd
2026-01-29 01:42:20.598 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.28.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 01:42:20.599 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 01:42:20.599 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.28.20:5700/2) Recv NOMTXPOWER cmd
2026-01-29 01:42:20.599 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.28.20:5700/2) Recv SETFORMAT cmd
2026-01-29 01:42:20.599 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.28.20:5700/2) TRXD header version 1 -> 1
2026-01-29 01:42:20.602 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.28.20:5700/3) Recv RXTUNE cmd
2026-01-29 01:42:20.602 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.28.20:5700/3) Recv TXTUNE cmd
2026-01-29 01:42:20.602 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.28.20:5700/3) Recv SETFORMAT cmd
2026-01-29 01:42:20.602 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.28.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 01:42:20.602 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 01:42:20.602 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.28.20:5700/3) Recv NOMTXPOWER cmd
2026-01-29 01:42:20.602 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.28.20:5700/3) Recv SETFORMAT cmd
2026-01-29 01:42:20.602 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.28.20:5700/3) TRXD header version 1 -> 1
2026-01-29 01:42:20.605 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.28.20:5700) Recv RXTUNE cmd
2026-01-29 01:42:20.605 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETTSC
2026-01-29 01:42:20.605 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETTSC
2026-01-29 01:42:20.605 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETTSC
2026-01-29 01:42:20.605 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.28.20:5700) Recv TXTUNE cmd
2026-01-29 01:42:20.605 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETRXGAIN
2026-01-29 01:42:20.605 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETRXGAIN
2026-01-29 01:42:20.605 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETRXGAIN
2026-01-29 01:42:20.605 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETTSC
2026-01-29 01:42:20.606 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:42:20.606 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:42:20.606 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:42:20.606 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.28.20:5700) Recv NOMTXPOWER cmd
2026-01-29 01:42:20.606 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:42:20.606 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:42:20.606 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:42:20.606 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.28.20:5700) Recv POWERON CMD
2026-01-29 01:42:20.606 [INFO] ctrl_if_trx.py:109 (BTS@172.18.28.20:5700) Starting transceiver...
2026-01-29 01:42:20.606 [INFO] transceiver.py:243 Starting clock generator
2026-01-29 01:42:20.606 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-01-29 01:42:20.606 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:42:20.606 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:42:20.606 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:42:20.606 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETRXGAIN
2026-01-29 01:42:20.607 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:42:20.607 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:42:20.607 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:42:20.607 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 01:42:20.607 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:42:20.607 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:42:20.607 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 01:42:20.607 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:42:20.607 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:42:20.607 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:42:20.608 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 01:42:20.608 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:42:20.608 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:42:20.608 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:42:20.608 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 01:42:20.608 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:42:20.608 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:42:20.608 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:42:20.608 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 01:42:20.608 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:42:20.608 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 01:42:20.608 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 01:42:20.608 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 01:42:20.608 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 01:42:20.608 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 01:42:20.608 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 01:42:20.608 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 01:42:20.608 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.28.20:5700) Recv POWEROFF cmd
2026-01-29 01:42:20.608 [INFO] ctrl_if_trx.py:117 (BTS@172.18.28.20:5700) Stopping transceiver...
2026-01-29 01:42:20.608 [INFO] transceiver.py:246 Stopping clock generator
2026-01-29 01:42:25.631 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.28.20:5700) Recv POWEROFF cmd
2026-01-29 01:42:25.631 [INFO] ctrl_if_trx.py:117 (BTS@172.18.28.20:5700) Stopping transceiver...
2026-01-29 01:42:25.632 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 01:42:25.634 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 01:42:25.634 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 01:42:25.635 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 01:42:25.639 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 01:42:25.641 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.28.20:5700) Recv SETFORMAT cmd
2026-01-29 01:42:25.641 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.28.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 01:42:25.641 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.28.20:5700) Recv SETFORMAT cmd
2026-01-29 01:42:25.641 [INFO] ctrl_if_trx.py:201 (BTS@172.18.28.20:5700) TRXD header version 1 -> 1
2026-01-29 01:42:25.646 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.28.20:5700/1) Recv RXTUNE cmd
2026-01-29 01:42:25.646 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.28.20:5700/1) Recv TXTUNE cmd
2026-01-29 01:42:25.646 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.28.20:5700/1) Recv SETFORMAT cmd
2026-01-29 01:42:25.646 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.28.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 01:42:25.646 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 01:42:25.647 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.28.20:5700/1) Recv NOMTXPOWER cmd
2026-01-29 01:42:25.647 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.28.20:5700/1) Recv SETFORMAT cmd
2026-01-29 01:42:25.647 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.28.20:5700/1) TRXD header version 1 -> 1
2026-01-29 01:42:25.649 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.28.20:5700/2) Recv RXTUNE cmd
2026-01-29 01:42:25.649 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.28.20:5700/2) Recv TXTUNE cmd
2026-01-29 01:42:25.649 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.28.20:5700/2) Recv SETFORMAT cmd
2026-01-29 01:42:25.649 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.28.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 01:42:25.649 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 01:42:25.649 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.28.20:5700/2) Recv NOMTXPOWER cmd
2026-01-29 01:42:25.649 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.28.20:5700/2) Recv SETFORMAT cmd
2026-01-29 01:42:25.649 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.28.20:5700/2) TRXD header version 1 -> 1
2026-01-29 01:42:25.651 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.28.20:5700/3) Recv RXTUNE cmd
2026-01-29 01:42:25.651 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.28.20:5700/3) Recv TXTUNE cmd
2026-01-29 01:42:25.651 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.28.20:5700/3) Recv SETFORMAT cmd
2026-01-29 01:42:25.651 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.28.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 01:42:25.651 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 01:42:25.652 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.28.20:5700/3) Recv NOMTXPOWER cmd
2026-01-29 01:42:25.652 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.28.20:5700/3) Recv SETFORMAT cmd
2026-01-29 01:42:25.652 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.28.20:5700/3) TRXD header version 1 -> 1
2026-01-29 01:42:25.654 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.28.20:5700) Recv RXTUNE cmd
2026-01-29 01:42:25.654 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETTSC
2026-01-29 01:42:25.654 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETTSC
2026-01-29 01:42:25.654 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETTSC
2026-01-29 01:42:25.654 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.28.20:5700) Recv TXTUNE cmd
2026-01-29 01:42:25.654 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETRXGAIN
2026-01-29 01:42:25.654 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETRXGAIN
2026-01-29 01:42:25.654 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETRXGAIN
2026-01-29 01:42:25.654 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETTSC
2026-01-29 01:42:25.654 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:42:25.654 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:42:25.654 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:42:25.654 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.28.20:5700) Recv NOMTXPOWER cmd
2026-01-29 01:42:25.654 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:42:25.654 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:42:25.655 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:42:25.655 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.28.20:5700) Recv POWERON CMD
2026-01-29 01:42:25.655 [INFO] ctrl_if_trx.py:109 (BTS@172.18.28.20:5700) Starting transceiver...
2026-01-29 01:42:25.655 [INFO] transceiver.py:243 Starting clock generator
2026-01-29 01:42:25.655 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-01-29 01:42:25.655 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:42:25.655 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:42:25.655 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:42:25.655 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETRXGAIN
2026-01-29 01:42:25.655 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:42:25.655 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:42:25.655 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:42:25.655 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 01:42:25.655 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:42:25.655 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:42:25.655 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:42:25.655 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 01:42:25.655 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:42:25.655 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:42:25.655 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:42:25.655 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 01:42:25.655 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:42:25.655 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:42:25.655 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:42:25.656 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 01:42:25.656 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:42:25.656 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:42:25.656 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 01:42:25.656 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:42:25.656 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 01:42:25.656 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 01:42:25.656 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 01:42:25.660 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-01-29 01:42:26.142 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-01-29 01:42:26.184 [DEBUG] fake_trx.py:278 (BTS@172.18.28.20:5700) Recv FAKE_TOA cmd
2026-01-29 01:42:26.187 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:42:26.188 [DEBUG] fake_trx.py:297 (BTS@172.18.28.20:5700) Recv FAKE_RSSI cmd
2026-01-29 01:42:26.191 [DEBUG] fake_trx.py:322 (BTS@172.18.28.20:5700) Recv FAKE_CI cmd
2026-01-29 01:42:26.193 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 01:42:26.193 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 01:42:26.194 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 01:42:26.622 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-01-29 01:42:26.658 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 01:42:26.659 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 01:42:26.659 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 01:42:26.662 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 01:42:27.102 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-01-29 01:42:27.195 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 01:42:27.195 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 01:42:27.196 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 01:42:27.196 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.28.22:6700) Recv POWERON CMD
2026-01-29 01:42:27.196 [INFO] ctrl_if_trx.py:109 (MS@172.18.28.22:6700) Starting transceiver...
2026-01-29 01:42:27.579 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-01-29 01:42:27.659 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 01:42:27.659 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 01:42:27.660 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 01:42:27.663 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 01:42:28.051 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-01-29 01:42:28.522 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-01-29 01:42:28.660 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 01:42:28.660 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 01:42:28.660 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 01:42:28.663 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 01:42:28.993 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-01-29 01:42:29.463 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-01-29 01:42:29.660 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 01:42:29.661 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 01:42:29.661 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 01:42:29.664 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 01:42:29.934 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-01-29 01:42:30.405 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-01-29 01:42:30.661 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 01:42:30.661 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 01:42:30.661 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 01:42:30.664 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 01:42:30.876 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-01-29 01:42:31.346 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-01-29 01:42:31.817 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-01-29 01:42:32.288 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-01-29 01:42:32.760 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-01-29 01:42:33.231 [DEBUG] clck_gen.py:113 IND CLOCK 1632
2026-01-29 01:42:33.705 [DEBUG] clck_gen.py:113 IND CLOCK 1734
2026-01-29 01:42:34.177 [DEBUG] clck_gen.py:113 IND CLOCK 1836
2026-01-29 01:42:34.648 [DEBUG] clck_gen.py:113 IND CLOCK 1938
2026-01-29 01:42:35.118 [DEBUG] clck_gen.py:113 IND CLOCK 2040
2026-01-29 01:42:35.589 [DEBUG] clck_gen.py:113 IND CLOCK 2142
2026-01-29 01:42:36.062 [DEBUG] clck_gen.py:113 IND CLOCK 2244
2026-01-29 01:42:36.540 [DEBUG] clck_gen.py:113 IND CLOCK 2346
2026-01-29 01:42:37.017 [DEBUG] clck_gen.py:113 IND CLOCK 2448
2026-01-29 01:42:37.495 [DEBUG] clck_gen.py:113 IND CLOCK 2550
2026-01-29 01:42:37.973 [DEBUG] clck_gen.py:113 IND CLOCK 2652
2026-01-29 01:42:38.450 [DEBUG] clck_gen.py:113 IND CLOCK 2754
2026-01-29 01:42:38.928 [DEBUG] clck_gen.py:113 IND CLOCK 2856
2026-01-29 01:42:39.403 [DEBUG] clck_gen.py:113 IND CLOCK 2958
2026-01-29 01:42:39.880 [DEBUG] clck_gen.py:113 IND CLOCK 3060
2026-01-29 01:42:40.358 [DEBUG] clck_gen.py:113 IND CLOCK 3162
2026-01-29 01:42:40.836 [DEBUG] clck_gen.py:113 IND CLOCK 3264
2026-01-29 01:42:40.969 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 01:42:40.969 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 01:42:40.977 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 01:42:40.977 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 01:42:40.977 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 01:42:40.977 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 01:42:40.984 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 01:42:40.984 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 01:42:40.984 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 01:42:40.984 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 01:42:40.985 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.28.20:5700) Recv POWEROFF cmd
2026-01-29 01:42:40.985 [INFO] ctrl_if_trx.py:117 (BTS@172.18.28.20:5700) Stopping transceiver...
2026-01-29 01:42:40.985 [INFO] transceiver.py:246 Stopping clock generator
2026-01-29 01:42:40.985 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=3296 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 01:42:40.985 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=3296 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 01:42:40.985 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=3296 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 01:42:40.985 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=3296 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 01:42:40.985 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=3296 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 01:42:40.985 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=3296 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 01:42:40.986 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=3297 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 01:42:40.986 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=3297 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 01:42:40.986 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=3297 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 01:42:40.986 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=3297 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 01:42:40.986 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=3297 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 01:42:40.986 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=3297 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 01:42:40.986 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=3297 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 01:42:40.986 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=3297 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 01:42:40.986 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=3298 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 01:42:40.986 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=3298 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 01:42:40.986 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=3298 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 01:42:40.986 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=3298 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 01:42:40.986 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=3298 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 01:42:40.986 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=3298 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 01:42:40.987 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=3298 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 01:42:40.987 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=3298 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 01:42:45.981 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.28.20:5700) Recv POWEROFF cmd
2026-01-29 01:42:45.981 [INFO] ctrl_if_trx.py:117 (BTS@172.18.28.20:5700) Stopping transceiver...
2026-01-29 01:42:45.983 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 01:42:45.984 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 01:42:45.985 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 01:42:45.985 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 01:42:45.994 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 01:42:45.995 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.28.20:5700) Recv SETFORMAT cmd
2026-01-29 01:42:45.995 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.28.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 01:42:45.996 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.28.20:5700) Recv SETFORMAT cmd
2026-01-29 01:42:45.996 [INFO] ctrl_if_trx.py:201 (BTS@172.18.28.20:5700) TRXD header version 1 -> 1
2026-01-29 01:42:46.000 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.28.20:5700/1) Recv RXTUNE cmd
2026-01-29 01:42:46.000 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.28.20:5700/1) Recv TXTUNE cmd
2026-01-29 01:42:46.000 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.28.20:5700/1) Recv SETFORMAT cmd
2026-01-29 01:42:46.001 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.28.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 01:42:46.001 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 01:42:46.001 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.28.20:5700/1) Recv NOMTXPOWER cmd
2026-01-29 01:42:46.002 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.28.20:5700/1) Recv SETFORMAT cmd
2026-01-29 01:42:46.002 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.28.20:5700/1) TRXD header version 1 -> 1
2026-01-29 01:42:46.003 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.28.20:5700/2) Recv RXTUNE cmd
2026-01-29 01:42:46.003 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.28.20:5700/2) Recv TXTUNE cmd
2026-01-29 01:42:46.004 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.28.20:5700/2) Recv SETFORMAT cmd
2026-01-29 01:42:46.004 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.28.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 01:42:46.004 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 01:42:46.004 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.28.20:5700/2) Recv NOMTXPOWER cmd
2026-01-29 01:42:46.004 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.28.20:5700/2) Recv SETFORMAT cmd
2026-01-29 01:42:46.004 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.28.20:5700/2) TRXD header version 1 -> 1
2026-01-29 01:42:46.005 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.28.20:5700/3) Recv RXTUNE cmd
2026-01-29 01:42:46.006 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.28.20:5700/3) Recv TXTUNE cmd
2026-01-29 01:42:46.006 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.28.20:5700/3) Recv SETFORMAT cmd
2026-01-29 01:42:46.006 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.28.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 01:42:46.006 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 01:42:46.006 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.28.20:5700/3) Recv NOMTXPOWER cmd
2026-01-29 01:42:46.006 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.28.20:5700/3) Recv SETFORMAT cmd
2026-01-29 01:42:46.006 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.28.20:5700/3) TRXD header version 1 -> 1
2026-01-29 01:42:46.008 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.28.20:5700) Recv RXTUNE cmd
2026-01-29 01:42:46.008 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETTSC
2026-01-29 01:42:46.008 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETTSC
2026-01-29 01:42:46.008 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETTSC
2026-01-29 01:42:46.009 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.28.20:5700) Recv TXTUNE cmd
2026-01-29 01:42:46.009 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETRXGAIN
2026-01-29 01:42:46.009 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETRXGAIN
2026-01-29 01:42:46.009 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETRXGAIN
2026-01-29 01:42:46.009 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETTSC
2026-01-29 01:42:46.009 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:42:46.009 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:42:46.009 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.28.20:5700) Recv NOMTXPOWER cmd
2026-01-29 01:42:46.009 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:42:46.009 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:42:46.009 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:42:46.009 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.28.20:5700) Recv POWERON CMD
2026-01-29 01:42:46.009 [INFO] ctrl_if_trx.py:109 (BTS@172.18.28.20:5700) Starting transceiver...
2026-01-29 01:42:46.009 [INFO] transceiver.py:243 Starting clock generator
2026-01-29 01:42:46.009 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-01-29 01:42:46.009 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:42:46.009 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:42:46.009 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:42:46.009 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETRXGAIN
2026-01-29 01:42:46.009 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:42:46.010 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:42:46.010 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:42:46.010 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 01:42:46.010 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:42:46.010 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:42:46.010 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:42:46.010 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 01:42:46.010 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:42:46.010 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:42:46.010 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:42:46.010 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 01:42:46.010 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:42:46.010 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:42:46.010 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 01:42:46.010 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:42:46.010 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:42:46.010 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 01:42:46.010 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:42:46.010 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 01:42:46.010 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:42:46.010 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 01:42:46.010 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:42:46.010 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 01:42:46.014 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-01-29 01:42:46.497 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-01-29 01:42:46.543 [DEBUG] fake_trx.py:278 (BTS@172.18.28.20:5700) Recv FAKE_TOA cmd
2026-01-29 01:42:46.544 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:42:46.544 [DEBUG] fake_trx.py:297 (BTS@172.18.28.20:5700) Recv FAKE_RSSI cmd
2026-01-29 01:42:46.545 [DEBUG] fake_trx.py:322 (BTS@172.18.28.20:5700) Recv FAKE_CI cmd
2026-01-29 01:42:46.567 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 01:42:46.567 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 01:42:46.567 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 01:42:46.570 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 01:42:46.570 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 01:42:46.571 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 01:42:46.571 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.28.22:6700) Recv POWERON CMD
2026-01-29 01:42:46.571 [INFO] ctrl_if_trx.py:109 (MS@172.18.28.22:6700) Starting transceiver...
2026-01-29 01:42:46.588 [DEBUG] fake_trx.py:297 (BTS@172.18.28.20:5700) Recv FAKE_RSSI cmd
2026-01-29 01:42:46.591 [DEBUG] fake_trx.py:278 (BTS@172.18.28.20:5700) Recv FAKE_TOA cmd
2026-01-29 01:42:46.596 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:42:46.600 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 01:42:46.600 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 01:42:46.600 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 01:42:46.600 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 01:42:46.973 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-01-29 01:42:47.011 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 01:42:47.012 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 01:42:47.013 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 01:42:47.016 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 01:42:47.451 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-01-29 01:42:47.930 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-01-29 01:42:48.013 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 01:42:48.013 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 01:42:48.014 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 01:42:48.017 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 01:42:48.405 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-01-29 01:42:48.883 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-01-29 01:42:49.013 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 01:42:49.014 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 01:42:49.015 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 01:42:49.018 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 01:42:49.361 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-01-29 01:42:49.839 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-01-29 01:42:50.015 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 01:42:50.015 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 01:42:50.016 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 01:42:50.019 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 01:42:50.318 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-01-29 01:42:50.795 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-01-29 01:42:51.016 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 01:42:51.016 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 01:42:51.016 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 01:42:51.020 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 01:42:51.273 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-01-29 01:42:51.750 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-01-29 01:42:52.228 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-01-29 01:42:52.705 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-01-29 01:42:53.183 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-01-29 01:42:53.660 [DEBUG] clck_gen.py:113 IND CLOCK 1632
2026-01-29 01:42:54.138 [DEBUG] clck_gen.py:113 IND CLOCK 1734
2026-01-29 01:42:54.604 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:42:54.606 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 01:42:54.607 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 01:42:54.607 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 01:42:54.616 [DEBUG] clck_gen.py:113 IND CLOCK 1836
2026-01-29 01:42:54.618 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 01:42:54.621 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 01:42:54.622 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 01:42:54.622 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 01:42:54.624 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 01:42:54.625 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 01:42:54.625 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 01:42:54.625 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 01:42:54.625 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.28.20:5700) Recv POWEROFF cmd
2026-01-29 01:42:54.625 [INFO] ctrl_if_trx.py:117 (BTS@172.18.28.20:5700) Stopping transceiver...
2026-01-29 01:42:54.625 [INFO] transceiver.py:246 Stopping clock generator
2026-01-29 01:42:54.625 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=1841 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 01:42:54.626 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=1841 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 01:42:54.626 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=1841 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 01:42:54.626 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=1841 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 01:42:54.626 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=1841 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 01:42:54.626 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=1841 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 01:42:59.620 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.28.20:5700) Recv POWEROFF cmd
2026-01-29 01:42:59.620 [INFO] ctrl_if_trx.py:117 (BTS@172.18.28.20:5700) Stopping transceiver...
2026-01-29 01:42:59.622 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 01:42:59.623 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 01:42:59.623 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 01:42:59.624 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 01:42:59.631 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 01:42:59.633 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.28.20:5700) Recv SETFORMAT cmd
2026-01-29 01:42:59.633 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.28.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 01:42:59.633 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.28.20:5700) Recv SETFORMAT cmd
2026-01-29 01:42:59.633 [INFO] ctrl_if_trx.py:201 (BTS@172.18.28.20:5700) TRXD header version 1 -> 1
2026-01-29 01:42:59.638 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.28.20:5700/1) Recv RXTUNE cmd
2026-01-29 01:42:59.639 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.28.20:5700/1) Recv TXTUNE cmd
2026-01-29 01:42:59.639 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.28.20:5700/1) Recv SETFORMAT cmd
2026-01-29 01:42:59.639 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.28.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 01:42:59.640 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 01:42:59.641 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.28.20:5700/1) Recv NOMTXPOWER cmd
2026-01-29 01:42:59.641 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.28.20:5700/1) Recv SETFORMAT cmd
2026-01-29 01:42:59.641 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.28.20:5700/1) TRXD header version 1 -> 1
2026-01-29 01:42:59.643 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.28.20:5700/2) Recv RXTUNE cmd
2026-01-29 01:42:59.643 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.28.20:5700/2) Recv TXTUNE cmd
2026-01-29 01:42:59.643 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.28.20:5700/2) Recv SETFORMAT cmd
2026-01-29 01:42:59.644 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.28.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 01:42:59.644 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 01:42:59.644 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.28.20:5700/2) Recv NOMTXPOWER cmd
2026-01-29 01:42:59.644 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.28.20:5700/2) Recv SETFORMAT cmd
2026-01-29 01:42:59.644 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.28.20:5700/2) TRXD header version 1 -> 1
2026-01-29 01:42:59.646 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.28.20:5700/3) Recv RXTUNE cmd
2026-01-29 01:42:59.646 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.28.20:5700/3) Recv TXTUNE cmd
2026-01-29 01:42:59.646 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.28.20:5700/3) Recv SETFORMAT cmd
2026-01-29 01:42:59.646 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.28.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 01:42:59.646 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 01:42:59.646 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.28.20:5700/3) Recv NOMTXPOWER cmd
2026-01-29 01:42:59.646 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.28.20:5700/3) Recv SETFORMAT cmd
2026-01-29 01:42:59.646 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.28.20:5700/3) TRXD header version 1 -> 1
2026-01-29 01:42:59.649 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.28.20:5700) Recv RXTUNE cmd
2026-01-29 01:42:59.649 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETTSC
2026-01-29 01:42:59.649 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETTSC
2026-01-29 01:42:59.649 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETTSC
2026-01-29 01:42:59.649 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.28.20:5700) Recv TXTUNE cmd
2026-01-29 01:42:59.649 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETRXGAIN
2026-01-29 01:42:59.649 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETRXGAIN
2026-01-29 01:42:59.649 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETRXGAIN
2026-01-29 01:42:59.649 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETTSC
2026-01-29 01:42:59.649 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:42:59.649 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:42:59.649 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:42:59.649 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.28.20:5700) Recv NOMTXPOWER cmd
2026-01-29 01:42:59.649 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:42:59.649 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:42:59.649 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:42:59.649 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.28.20:5700) Recv POWERON CMD
2026-01-29 01:42:59.650 [INFO] ctrl_if_trx.py:109 (BTS@172.18.28.20:5700) Starting transceiver...
2026-01-29 01:42:59.650 [INFO] transceiver.py:243 Starting clock generator
2026-01-29 01:42:59.650 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-01-29 01:42:59.650 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:42:59.650 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:42:59.650 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:42:59.650 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETRXGAIN
2026-01-29 01:42:59.650 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:42:59.650 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:42:59.650 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:42:59.650 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 01:42:59.650 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:42:59.650 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:42:59.650 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:42:59.650 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 01:42:59.650 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:42:59.650 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:42:59.650 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:42:59.650 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 01:42:59.651 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:42:59.651 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:42:59.651 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:42:59.651 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 01:42:59.651 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:42:59.651 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:42:59.651 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:42:59.651 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 01:42:59.651 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 01:42:59.651 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 01:42:59.651 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 01:42:59.654 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-01-29 01:43:00.137 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-01-29 01:43:00.172 [DEBUG] fake_trx.py:278 (BTS@172.18.28.20:5700) Recv FAKE_TOA cmd
2026-01-29 01:43:00.174 [DEBUG] fake_trx.py:297 (BTS@172.18.28.20:5700) Recv FAKE_RSSI cmd
2026-01-29 01:43:00.174 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:43:00.177 [DEBUG] fake_trx.py:322 (BTS@172.18.28.20:5700) Recv FAKE_CI cmd
2026-01-29 01:43:00.201 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 01:43:00.201 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 01:43:00.201 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 01:43:00.202 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 01:43:00.202 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 01:43:00.203 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 01:43:00.203 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.28.22:6700) Recv POWERON CMD
2026-01-29 01:43:00.203 [INFO] ctrl_if_trx.py:109 (MS@172.18.28.22:6700) Starting transceiver...
2026-01-29 01:43:00.229 [DEBUG] fake_trx.py:297 (BTS@172.18.28.20:5700) Recv FAKE_RSSI cmd
2026-01-29 01:43:00.233 [DEBUG] fake_trx.py:278 (BTS@172.18.28.20:5700) Recv FAKE_TOA cmd
2026-01-29 01:43:00.240 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:43:00.246 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 01:43:00.246 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 01:43:00.246 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 01:43:00.246 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 01:43:00.615 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-01-29 01:43:00.652 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 01:43:00.653 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 01:43:00.653 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 01:43:00.656 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 01:43:01.093 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-01-29 01:43:01.120 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 01:43:01.120 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 01:43:01.124 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 01:43:01.125 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 01:43:01.125 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 01:43:01.125 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 01:43:01.126 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 01:43:01.126 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 01:43:01.126 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 01:43:01.126 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.28.20:5700) Recv POWEROFF cmd
2026-01-29 01:43:01.126 [INFO] ctrl_if_trx.py:117 (BTS@172.18.28.20:5700) Stopping transceiver...
2026-01-29 01:43:01.126 [INFO] transceiver.py:246 Stopping clock generator
2026-01-29 01:43:01.126 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 01:43:01.126 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=315 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 01:43:01.126 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=315 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 01:43:01.126 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=315 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 01:43:01.126 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=315 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 01:43:01.126 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=315 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 01:43:01.126 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=315 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 01:43:01.126 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=315 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 01:43:06.127 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.28.20:5700) Recv POWEROFF cmd
2026-01-29 01:43:06.127 [INFO] ctrl_if_trx.py:117 (BTS@172.18.28.20:5700) Stopping transceiver...
2026-01-29 01:43:06.128 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 01:43:06.130 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 01:43:06.131 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 01:43:06.131 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 01:43:06.138 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 01:43:06.139 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.28.20:5700) Recv SETFORMAT cmd
2026-01-29 01:43:06.139 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.28.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 01:43:06.139 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.28.20:5700) Recv SETFORMAT cmd
2026-01-29 01:43:06.139 [INFO] ctrl_if_trx.py:201 (BTS@172.18.28.20:5700) TRXD header version 1 -> 1
2026-01-29 01:43:06.141 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.28.20:5700/1) Recv RXTUNE cmd
2026-01-29 01:43:06.142 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.28.20:5700/1) Recv TXTUNE cmd
2026-01-29 01:43:06.142 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.28.20:5700/1) Recv SETFORMAT cmd
2026-01-29 01:43:06.142 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.28.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 01:43:06.142 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 01:43:06.142 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.28.20:5700/1) Recv NOMTXPOWER cmd
2026-01-29 01:43:06.142 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.28.20:5700/1) Recv SETFORMAT cmd
2026-01-29 01:43:06.142 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.28.20:5700/1) TRXD header version 1 -> 1
2026-01-29 01:43:06.144 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.28.20:5700/2) Recv RXTUNE cmd
2026-01-29 01:43:06.144 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.28.20:5700/2) Recv TXTUNE cmd
2026-01-29 01:43:06.145 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.28.20:5700/2) Recv SETFORMAT cmd
2026-01-29 01:43:06.145 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.28.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 01:43:06.145 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 01:43:06.145 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.28.20:5700/2) Recv NOMTXPOWER cmd
2026-01-29 01:43:06.145 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.28.20:5700/2) Recv SETFORMAT cmd
2026-01-29 01:43:06.145 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.28.20:5700/2) TRXD header version 1 -> 1
2026-01-29 01:43:06.147 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.28.20:5700/3) Recv RXTUNE cmd
2026-01-29 01:43:06.147 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.28.20:5700/3) Recv TXTUNE cmd
2026-01-29 01:43:06.147 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.28.20:5700/3) Recv SETFORMAT cmd
2026-01-29 01:43:06.147 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.28.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 01:43:06.147 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 01:43:06.147 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.28.20:5700/3) Recv NOMTXPOWER cmd
2026-01-29 01:43:06.147 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.28.20:5700/3) Recv SETFORMAT cmd
2026-01-29 01:43:06.147 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.28.20:5700/3) TRXD header version 1 -> 1
2026-01-29 01:43:06.150 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.28.20:5700) Recv RXTUNE cmd
2026-01-29 01:43:06.150 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETTSC
2026-01-29 01:43:06.150 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETTSC
2026-01-29 01:43:06.150 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETTSC
2026-01-29 01:43:06.150 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.28.20:5700) Recv TXTUNE cmd
2026-01-29 01:43:06.150 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETRXGAIN
2026-01-29 01:43:06.150 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETRXGAIN
2026-01-29 01:43:06.150 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETRXGAIN
2026-01-29 01:43:06.150 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETTSC
2026-01-29 01:43:06.150 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:43:06.150 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:43:06.150 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:43:06.150 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.28.20:5700) Recv NOMTXPOWER cmd
2026-01-29 01:43:06.150 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:43:06.150 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:43:06.151 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:43:06.151 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.28.20:5700) Recv POWERON CMD
2026-01-29 01:43:06.151 [INFO] ctrl_if_trx.py:109 (BTS@172.18.28.20:5700) Starting transceiver...
2026-01-29 01:43:06.151 [INFO] transceiver.py:243 Starting clock generator
2026-01-29 01:43:06.151 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-01-29 01:43:06.151 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:43:06.151 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:43:06.151 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:43:06.151 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETRXGAIN
2026-01-29 01:43:06.151 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:43:06.151 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:43:06.151 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:43:06.151 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 01:43:06.152 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:43:06.152 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:43:06.152 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:43:06.152 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 01:43:06.152 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:43:06.152 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:43:06.152 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:43:06.152 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 01:43:06.152 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:43:06.152 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:43:06.152 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:43:06.152 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 01:43:06.153 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:43:06.153 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:43:06.153 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:43:06.153 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 01:43:06.153 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 01:43:06.153 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 01:43:06.153 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 01:43:06.155 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-01-29 01:43:06.636 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-01-29 01:43:06.680 [DEBUG] fake_trx.py:278 (BTS@172.18.28.20:5700) Recv FAKE_TOA cmd
2026-01-29 01:43:06.681 [DEBUG] fake_trx.py:297 (BTS@172.18.28.20:5700) Recv FAKE_RSSI cmd
2026-01-29 01:43:06.682 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:43:06.683 [DEBUG] fake_trx.py:322 (BTS@172.18.28.20:5700) Recv FAKE_CI cmd
2026-01-29 01:43:06.698 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 01:43:06.698 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 01:43:06.698 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 01:43:06.705 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 01:43:06.705 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 01:43:06.706 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 01:43:06.706 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.28.22:6700) Recv POWERON CMD
2026-01-29 01:43:06.707 [INFO] ctrl_if_trx.py:109 (MS@172.18.28.22:6700) Starting transceiver...
2026-01-29 01:43:06.729 [DEBUG] fake_trx.py:297 (BTS@172.18.28.20:5700) Recv FAKE_RSSI cmd
2026-01-29 01:43:06.732 [DEBUG] fake_trx.py:278 (BTS@172.18.28.20:5700) Recv FAKE_TOA cmd
2026-01-29 01:43:06.741 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:43:06.748 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 01:43:06.749 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 01:43:06.749 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 01:43:06.749 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 01:43:07.114 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-01-29 01:43:07.155 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 01:43:07.155 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 01:43:07.156 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 01:43:07.158 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 01:43:07.592 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-01-29 01:43:08.070 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-01-29 01:43:08.155 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 01:43:08.156 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 01:43:08.157 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 01:43:08.159 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 01:43:08.547 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-01-29 01:43:09.025 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-01-29 01:43:09.157 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 01:43:09.157 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 01:43:09.159 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 01:43:09.159 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 01:43:09.503 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-01-29 01:43:09.981 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-01-29 01:43:10.157 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 01:43:10.158 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 01:43:10.159 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 01:43:10.161 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 01:43:10.458 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-01-29 01:43:10.936 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-01-29 01:43:11.158 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 01:43:11.159 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 01:43:11.160 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 01:43:11.162 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 01:43:11.414 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-01-29 01:43:11.892 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-01-29 01:43:12.370 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-01-29 01:43:12.848 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-01-29 01:43:13.326 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-01-29 01:43:13.804 [DEBUG] clck_gen.py:113 IND CLOCK 1632
2026-01-29 01:43:14.282 [DEBUG] clck_gen.py:113 IND CLOCK 1734
2026-01-29 01:43:14.752 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:43:14.754 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 01:43:14.755 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 01:43:14.755 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 01:43:14.760 [DEBUG] clck_gen.py:113 IND CLOCK 1836
2026-01-29 01:43:14.775 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 01:43:14.775 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 01:43:14.775 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 01:43:14.776 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 01:43:14.776 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 01:43:14.776 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 01:43:14.776 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.28.22:6700) Recv POWERON CMD
2026-01-29 01:43:14.776 [INFO] ctrl_if_trx.py:109 (MS@172.18.28.22:6700) Starting transceiver...
2026-01-29 01:43:14.806 [DEBUG] fake_trx.py:297 (BTS@172.18.28.20:5700) Recv FAKE_RSSI cmd
2026-01-29 01:43:14.810 [DEBUG] fake_trx.py:278 (BTS@172.18.28.20:5700) Recv FAKE_TOA cmd
2026-01-29 01:43:14.816 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:43:14.820 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 01:43:14.820 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 01:43:14.820 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 01:43:14.820 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 01:43:15.237 [DEBUG] clck_gen.py:113 IND CLOCK 1938
2026-01-29 01:43:15.715 [DEBUG] clck_gen.py:113 IND CLOCK 2040
2026-01-29 01:43:16.193 [DEBUG] clck_gen.py:113 IND CLOCK 2142
2026-01-29 01:43:16.671 [DEBUG] clck_gen.py:113 IND CLOCK 2244
2026-01-29 01:43:17.149 [DEBUG] clck_gen.py:113 IND CLOCK 2346
2026-01-29 01:43:17.627 [DEBUG] clck_gen.py:113 IND CLOCK 2448
2026-01-29 01:43:18.104 [DEBUG] clck_gen.py:113 IND CLOCK 2550
2026-01-29 01:43:18.583 [DEBUG] clck_gen.py:113 IND CLOCK 2652
2026-01-29 01:43:19.061 [DEBUG] clck_gen.py:113 IND CLOCK 2754
2026-01-29 01:43:19.540 [DEBUG] clck_gen.py:113 IND CLOCK 2856
2026-01-29 01:43:20.018 [DEBUG] clck_gen.py:113 IND CLOCK 2958
2026-01-29 01:43:20.496 [DEBUG] clck_gen.py:113 IND CLOCK 3060
2026-01-29 01:43:20.973 [DEBUG] clck_gen.py:113 IND CLOCK 3162
2026-01-29 01:43:21.452 [DEBUG] clck_gen.py:113 IND CLOCK 3264
2026-01-29 01:43:21.930 [DEBUG] clck_gen.py:113 IND CLOCK 3366
2026-01-29 01:43:22.409 [DEBUG] clck_gen.py:113 IND CLOCK 3468
2026-01-29 01:43:22.823 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:43:22.825 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 01:43:22.826 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 01:43:22.826 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 01:43:22.837 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 01:43:22.837 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 01:43:22.837 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 01:43:22.837 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 01:43:22.838 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 01:43:22.838 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 01:43:22.838 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 01:43:22.838 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.28.20:5700) Recv POWEROFF cmd
2026-01-29 01:43:22.838 [INFO] ctrl_if_trx.py:117 (BTS@172.18.28.20:5700) Stopping transceiver...
2026-01-29 01:43:22.838 [INFO] transceiver.py:246 Stopping clock generator
2026-01-29 01:43:22.838 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 01:43:22.838 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=3563 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 01:43:22.838 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=3563 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 01:43:22.838 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=3563 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 01:43:22.839 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=3563 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 01:43:22.839 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=3563 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 01:43:22.839 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=3563 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 01:43:22.839 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=3563 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 01:43:22.839 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=3563 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 01:43:27.839 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.28.20:5700) Recv POWEROFF cmd
2026-01-29 01:43:27.839 [INFO] ctrl_if_trx.py:117 (BTS@172.18.28.20:5700) Stopping transceiver...
2026-01-29 01:43:27.840 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 01:43:27.842 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 01:43:27.843 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 01:43:27.843 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 01:43:27.852 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 01:43:27.853 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.28.20:5700) Recv SETFORMAT cmd
2026-01-29 01:43:27.853 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.28.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 01:43:27.854 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.28.20:5700) Recv SETFORMAT cmd
2026-01-29 01:43:27.854 [INFO] ctrl_if_trx.py:201 (BTS@172.18.28.20:5700) TRXD header version 1 -> 1
2026-01-29 01:43:27.859 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.28.20:5700/1) Recv RXTUNE cmd
2026-01-29 01:43:27.859 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.28.20:5700/1) Recv TXTUNE cmd
2026-01-29 01:43:27.860 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.28.20:5700/1) Recv SETFORMAT cmd
2026-01-29 01:43:27.860 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.28.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 01:43:27.860 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 01:43:27.861 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.28.20:5700/1) Recv NOMTXPOWER cmd
2026-01-29 01:43:27.861 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.28.20:5700/1) Recv SETFORMAT cmd
2026-01-29 01:43:27.861 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.28.20:5700/1) TRXD header version 1 -> 1
2026-01-29 01:43:27.862 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.28.20:5700/2) Recv RXTUNE cmd
2026-01-29 01:43:27.863 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.28.20:5700/2) Recv TXTUNE cmd
2026-01-29 01:43:27.863 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.28.20:5700/2) Recv SETFORMAT cmd
2026-01-29 01:43:27.863 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.28.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 01:43:27.863 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 01:43:27.863 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.28.20:5700/2) Recv NOMTXPOWER cmd
2026-01-29 01:43:27.864 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.28.20:5700/2) Recv SETFORMAT cmd
2026-01-29 01:43:27.864 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.28.20:5700/2) TRXD header version 1 -> 1
2026-01-29 01:43:27.865 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.28.20:5700/3) Recv RXTUNE cmd
2026-01-29 01:43:27.865 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.28.20:5700/3) Recv TXTUNE cmd
2026-01-29 01:43:27.865 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.28.20:5700/3) Recv SETFORMAT cmd
2026-01-29 01:43:27.865 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.28.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 01:43:27.865 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 01:43:27.865 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.28.20:5700/3) Recv NOMTXPOWER cmd
2026-01-29 01:43:27.866 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.28.20:5700/3) Recv SETFORMAT cmd
2026-01-29 01:43:27.866 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.28.20:5700/3) TRXD header version 1 -> 1
2026-01-29 01:43:27.868 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.28.20:5700) Recv RXTUNE cmd
2026-01-29 01:43:27.868 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETTSC
2026-01-29 01:43:27.868 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETTSC
2026-01-29 01:43:27.868 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETTSC
2026-01-29 01:43:27.868 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.28.20:5700) Recv TXTUNE cmd
2026-01-29 01:43:27.868 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETRXGAIN
2026-01-29 01:43:27.869 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETRXGAIN
2026-01-29 01:43:27.869 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETRXGAIN
2026-01-29 01:43:27.869 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETTSC
2026-01-29 01:43:27.869 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:43:27.869 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:43:27.869 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.28.20:5700) Recv NOMTXPOWER cmd
2026-01-29 01:43:27.869 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:43:27.869 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:43:27.869 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:43:27.869 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.28.20:5700) Recv POWERON CMD
2026-01-29 01:43:27.869 [INFO] ctrl_if_trx.py:109 (BTS@172.18.28.20:5700) Starting transceiver...
2026-01-29 01:43:27.869 [INFO] transceiver.py:243 Starting clock generator
2026-01-29 01:43:27.869 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-01-29 01:43:27.869 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:43:27.869 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:43:27.869 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:43:27.870 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETRXGAIN
2026-01-29 01:43:27.870 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:43:27.870 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:43:27.870 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:43:27.870 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 01:43:27.870 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:43:27.870 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:43:27.870 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:43:27.870 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 01:43:27.870 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:43:27.870 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:43:27.870 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:43:27.870 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 01:43:27.870 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:43:27.871 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:43:27.871 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:43:27.871 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 01:43:27.871 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:43:27.871 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:43:27.871 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:43:27.871 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 01:43:27.871 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:43:27.871 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 01:43:27.871 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 01:43:27.871 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 01:43:27.874 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-01-29 01:43:28.358 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-01-29 01:43:28.394 [DEBUG] fake_trx.py:278 (BTS@172.18.28.20:5700) Recv FAKE_TOA cmd
2026-01-29 01:43:28.395 [DEBUG] fake_trx.py:297 (BTS@172.18.28.20:5700) Recv FAKE_RSSI cmd
2026-01-29 01:43:28.396 [DEBUG] fake_trx.py:322 (BTS@172.18.28.20:5700) Recv FAKE_CI cmd
2026-01-29 01:43:28.397 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:43:28.409 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 01:43:28.409 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 01:43:28.409 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 01:43:28.415 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 01:43:28.415 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 01:43:28.415 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 01:43:28.415 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.28.22:6700) Recv POWERON CMD
2026-01-29 01:43:28.415 [INFO] ctrl_if_trx.py:109 (MS@172.18.28.22:6700) Starting transceiver...
2026-01-29 01:43:28.450 [DEBUG] fake_trx.py:297 (BTS@172.18.28.20:5700) Recv FAKE_RSSI cmd
2026-01-29 01:43:28.454 [DEBUG] fake_trx.py:278 (BTS@172.18.28.20:5700) Recv FAKE_TOA cmd
2026-01-29 01:43:28.462 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:43:28.468 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 01:43:28.468 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 01:43:28.468 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 01:43:28.468 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 01:43:28.835 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-01-29 01:43:28.872 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 01:43:28.873 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 01:43:28.874 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 01:43:28.877 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 01:43:29.314 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-01-29 01:43:29.792 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-01-29 01:43:29.874 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 01:43:29.874 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 01:43:29.875 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 01:43:29.878 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 01:43:30.269 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-01-29 01:43:30.748 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-01-29 01:43:30.875 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 01:43:30.875 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 01:43:30.875 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 01:43:30.879 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 01:43:31.225 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-01-29 01:43:31.703 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-01-29 01:43:31.875 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 01:43:31.876 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 01:43:31.876 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 01:43:31.880 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 01:43:32.181 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-01-29 01:43:32.659 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-01-29 01:43:32.876 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 01:43:32.877 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 01:43:32.877 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 01:43:32.881 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 01:43:33.137 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-01-29 01:43:33.615 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-01-29 01:43:34.093 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-01-29 01:43:34.571 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-01-29 01:43:35.049 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-01-29 01:43:35.527 [DEBUG] clck_gen.py:113 IND CLOCK 1632
2026-01-29 01:43:36.006 [DEBUG] clck_gen.py:113 IND CLOCK 1734
2026-01-29 01:43:36.471 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:43:36.474 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 01:43:36.475 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 01:43:36.475 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 01:43:36.484 [DEBUG] clck_gen.py:113 IND CLOCK 1836
2026-01-29 01:43:36.492 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 01:43:36.492 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 01:43:36.492 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 01:43:36.493 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 01:43:36.494 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 01:43:36.494 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 01:43:36.494 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.28.22:6700) Recv POWERON CMD
2026-01-29 01:43:36.494 [INFO] ctrl_if_trx.py:109 (MS@172.18.28.22:6700) Starting transceiver...
2026-01-29 01:43:36.530 [DEBUG] fake_trx.py:297 (BTS@172.18.28.20:5700) Recv FAKE_RSSI cmd
2026-01-29 01:43:36.534 [DEBUG] fake_trx.py:278 (BTS@172.18.28.20:5700) Recv FAKE_TOA cmd
2026-01-29 01:43:36.541 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:43:36.545 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 01:43:36.545 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 01:43:36.546 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 01:43:36.546 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 01:43:36.962 [DEBUG] clck_gen.py:113 IND CLOCK 1938
2026-01-29 01:43:37.440 [DEBUG] clck_gen.py:113 IND CLOCK 2040
2026-01-29 01:43:37.918 [DEBUG] clck_gen.py:113 IND CLOCK 2142
2026-01-29 01:43:38.395 [DEBUG] clck_gen.py:113 IND CLOCK 2244
2026-01-29 01:43:38.872 [DEBUG] clck_gen.py:113 IND CLOCK 2346
2026-01-29 01:43:39.350 [DEBUG] clck_gen.py:113 IND CLOCK 2448
2026-01-29 01:43:39.829 [DEBUG] clck_gen.py:113 IND CLOCK 2550
2026-01-29 01:43:40.306 [DEBUG] clck_gen.py:113 IND CLOCK 2652
2026-01-29 01:43:40.784 [DEBUG] clck_gen.py:113 IND CLOCK 2754
2026-01-29 01:43:41.262 [DEBUG] clck_gen.py:113 IND CLOCK 2856
2026-01-29 01:43:41.740 [DEBUG] clck_gen.py:113 IND CLOCK 2958
2026-01-29 01:43:42.218 [DEBUG] clck_gen.py:113 IND CLOCK 3060
2026-01-29 01:43:42.697 [DEBUG] clck_gen.py:113 IND CLOCK 3162
2026-01-29 01:43:43.175 [DEBUG] clck_gen.py:113 IND CLOCK 3264
2026-01-29 01:43:43.654 [DEBUG] clck_gen.py:113 IND CLOCK 3366
2026-01-29 01:43:44.132 [DEBUG] clck_gen.py:113 IND CLOCK 3468
2026-01-29 01:43:44.548 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:43:44.551 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 01:43:44.551 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 01:43:44.551 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 01:43:44.562 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 01:43:44.563 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 01:43:44.563 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 01:43:44.563 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 01:43:44.565 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 01:43:44.565 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 01:43:44.565 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 01:43:44.565 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.28.20:5700) Recv POWEROFF cmd
2026-01-29 01:43:44.565 [INFO] ctrl_if_trx.py:117 (BTS@172.18.28.20:5700) Stopping transceiver...
2026-01-29 01:43:44.565 [INFO] transceiver.py:246 Stopping clock generator
2026-01-29 01:43:44.565 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 01:43:44.565 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=3563 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 01:43:44.565 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=3563 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 01:43:44.565 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=3563 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 01:43:44.565 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=3563 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 01:43:44.565 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=3563 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 01:43:44.565 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=3563 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 01:43:44.565 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=3563 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 01:43:44.565 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=3563 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 01:43:49.566 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.28.20:5700) Recv POWEROFF cmd
2026-01-29 01:43:49.567 [INFO] ctrl_if_trx.py:117 (BTS@172.18.28.20:5700) Stopping transceiver...
2026-01-29 01:43:49.569 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 01:43:49.569 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 01:43:49.570 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 01:43:49.570 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 01:43:49.573 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 01:43:49.574 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.28.20:5700) Recv SETFORMAT cmd
2026-01-29 01:43:49.574 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.28.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 01:43:49.574 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.28.20:5700) Recv SETFORMAT cmd
2026-01-29 01:43:49.574 [INFO] ctrl_if_trx.py:201 (BTS@172.18.28.20:5700) TRXD header version 1 -> 1
2026-01-29 01:43:49.576 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.28.20:5700/1) Recv RXTUNE cmd
2026-01-29 01:43:49.576 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.28.20:5700/1) Recv TXTUNE cmd
2026-01-29 01:43:49.576 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.28.20:5700/1) Recv SETFORMAT cmd
2026-01-29 01:43:49.576 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.28.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 01:43:49.576 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 01:43:49.576 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.28.20:5700/1) Recv NOMTXPOWER cmd
2026-01-29 01:43:49.576 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.28.20:5700/1) Recv SETFORMAT cmd
2026-01-29 01:43:49.576 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.28.20:5700/1) TRXD header version 1 -> 1
2026-01-29 01:43:49.578 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.28.20:5700/2) Recv RXTUNE cmd
2026-01-29 01:43:49.578 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.28.20:5700/2) Recv TXTUNE cmd
2026-01-29 01:43:49.578 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.28.20:5700/2) Recv SETFORMAT cmd
2026-01-29 01:43:49.578 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.28.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 01:43:49.578 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 01:43:49.578 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.28.20:5700/2) Recv NOMTXPOWER cmd
2026-01-29 01:43:49.578 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.28.20:5700/2) Recv SETFORMAT cmd
2026-01-29 01:43:49.578 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.28.20:5700/2) TRXD header version 1 -> 1
2026-01-29 01:43:49.580 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.28.20:5700/3) Recv RXTUNE cmd
2026-01-29 01:43:49.580 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.28.20:5700/3) Recv TXTUNE cmd
2026-01-29 01:43:49.580 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.28.20:5700/3) Recv SETFORMAT cmd
2026-01-29 01:43:49.580 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.28.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 01:43:49.580 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 01:43:49.580 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.28.20:5700/3) Recv NOMTXPOWER cmd
2026-01-29 01:43:49.580 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.28.20:5700/3) Recv SETFORMAT cmd
2026-01-29 01:43:49.580 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.28.20:5700/3) TRXD header version 1 -> 1
2026-01-29 01:43:49.582 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.28.20:5700) Recv RXTUNE cmd
2026-01-29 01:43:49.582 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETTSC
2026-01-29 01:43:49.582 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETTSC
2026-01-29 01:43:49.582 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETTSC
2026-01-29 01:43:49.582 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.28.20:5700) Recv TXTUNE cmd
2026-01-29 01:43:49.582 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETRXGAIN
2026-01-29 01:43:49.582 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETRXGAIN
2026-01-29 01:43:49.582 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETRXGAIN
2026-01-29 01:43:49.582 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETTSC
2026-01-29 01:43:49.582 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:43:49.582 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:43:49.582 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:43:49.582 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.28.20:5700) Recv NOMTXPOWER cmd
2026-01-29 01:43:49.582 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:43:49.582 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:43:49.582 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:43:49.582 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.28.20:5700) Recv POWERON CMD
2026-01-29 01:43:49.582 [INFO] ctrl_if_trx.py:109 (BTS@172.18.28.20:5700) Starting transceiver...
2026-01-29 01:43:49.582 [INFO] transceiver.py:243 Starting clock generator
2026-01-29 01:43:49.582 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-01-29 01:43:49.582 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:43:49.582 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:43:49.582 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:43:49.582 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETRXGAIN
2026-01-29 01:43:49.583 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:43:49.583 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:43:49.583 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:43:49.583 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 01:43:49.583 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:43:49.583 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:43:49.583 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:43:49.583 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 01:43:49.583 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:43:49.583 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:43:49.583 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:43:49.583 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 01:43:49.583 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:43:49.583 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:43:49.583 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:43:49.583 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 01:43:49.583 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:43:49.583 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:43:49.583 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:43:49.583 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 01:43:49.583 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 01:43:49.583 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 01:43:49.583 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 01:43:49.587 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-01-29 01:43:50.070 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-01-29 01:43:50.105 [DEBUG] fake_trx.py:278 (BTS@172.18.28.20:5700) Recv FAKE_TOA cmd
2026-01-29 01:43:50.106 [DEBUG] fake_trx.py:297 (BTS@172.18.28.20:5700) Recv FAKE_RSSI cmd
2026-01-29 01:43:50.107 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:43:50.108 [DEBUG] fake_trx.py:322 (BTS@172.18.28.20:5700) Recv FAKE_CI cmd
2026-01-29 01:43:50.122 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 01:43:50.122 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 01:43:50.122 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 01:43:50.128 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 01:43:50.129 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 01:43:50.129 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 01:43:50.129 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.28.22:6700) Recv POWERON CMD
2026-01-29 01:43:50.129 [INFO] ctrl_if_trx.py:109 (MS@172.18.28.22:6700) Starting transceiver...
2026-01-29 01:43:50.161 [DEBUG] fake_trx.py:297 (BTS@172.18.28.20:5700) Recv FAKE_RSSI cmd
2026-01-29 01:43:50.165 [DEBUG] fake_trx.py:278 (BTS@172.18.28.20:5700) Recv FAKE_TOA cmd
2026-01-29 01:43:50.173 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:43:50.178 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 01:43:50.178 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 01:43:50.178 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 01:43:50.178 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 01:43:50.546 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-01-29 01:43:50.584 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 01:43:50.585 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 01:43:50.585 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 01:43:50.588 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 01:43:51.024 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-01-29 01:43:51.502 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-01-29 01:43:51.585 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 01:43:51.586 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 01:43:51.586 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 01:43:51.589 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 01:43:51.981 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-01-29 01:43:52.459 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-01-29 01:43:52.587 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 01:43:52.587 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 01:43:52.587 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 01:43:52.589 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 01:43:52.936 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-01-29 01:43:53.414 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-01-29 01:43:53.588 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 01:43:53.588 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 01:43:53.588 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 01:43:53.590 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 01:43:53.893 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-01-29 01:43:54.371 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-01-29 01:43:54.588 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 01:43:54.589 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 01:43:54.589 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 01:43:54.591 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 01:43:54.849 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-01-29 01:43:55.327 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-01-29 01:43:55.805 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-01-29 01:43:56.283 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-01-29 01:43:56.759 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-01-29 01:43:57.237 [DEBUG] clck_gen.py:113 IND CLOCK 1632
2026-01-29 01:43:57.716 [DEBUG] clck_gen.py:113 IND CLOCK 1734
2026-01-29 01:43:58.181 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:43:58.184 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 01:43:58.184 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 01:43:58.185 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 01:43:58.193 [DEBUG] clck_gen.py:113 IND CLOCK 1836
2026-01-29 01:43:58.204 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 01:43:58.204 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 01:43:58.204 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 01:43:58.206 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 01:43:58.206 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 01:43:58.206 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 01:43:58.206 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.28.22:6700) Recv POWERON CMD
2026-01-29 01:43:58.206 [INFO] ctrl_if_trx.py:109 (MS@172.18.28.22:6700) Starting transceiver...
2026-01-29 01:43:58.239 [DEBUG] fake_trx.py:297 (BTS@172.18.28.20:5700) Recv FAKE_RSSI cmd
2026-01-29 01:43:58.243 [DEBUG] fake_trx.py:278 (BTS@172.18.28.20:5700) Recv FAKE_TOA cmd
2026-01-29 01:43:58.250 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:43:58.253 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 01:43:58.253 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 01:43:58.253 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 01:43:58.254 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 01:43:58.671 [DEBUG] clck_gen.py:113 IND CLOCK 1938
2026-01-29 01:43:59.149 [DEBUG] clck_gen.py:113 IND CLOCK 2040
2026-01-29 01:43:59.627 [DEBUG] clck_gen.py:113 IND CLOCK 2142
2026-01-29 01:44:00.105 [DEBUG] clck_gen.py:113 IND CLOCK 2244
2026-01-29 01:44:00.583 [DEBUG] clck_gen.py:113 IND CLOCK 2346
2026-01-29 01:44:01.061 [DEBUG] clck_gen.py:113 IND CLOCK 2448
2026-01-29 01:44:01.538 [DEBUG] clck_gen.py:113 IND CLOCK 2550
2026-01-29 01:44:02.016 [DEBUG] clck_gen.py:113 IND CLOCK 2652
2026-01-29 01:44:02.495 [DEBUG] clck_gen.py:113 IND CLOCK 2754
2026-01-29 01:44:02.969 [DEBUG] clck_gen.py:113 IND CLOCK 2856
2026-01-29 01:44:03.439 [DEBUG] clck_gen.py:113 IND CLOCK 2958
2026-01-29 01:44:03.909 [DEBUG] clck_gen.py:113 IND CLOCK 3060
2026-01-29 01:44:04.387 [DEBUG] clck_gen.py:113 IND CLOCK 3162
2026-01-29 01:44:04.865 [DEBUG] clck_gen.py:113 IND CLOCK 3264
2026-01-29 01:44:05.344 [DEBUG] clck_gen.py:113 IND CLOCK 3366
2026-01-29 01:44:05.822 [DEBUG] clck_gen.py:113 IND CLOCK 3468
2026-01-29 01:44:06.256 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:44:06.258 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 01:44:06.259 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 01:44:06.259 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 01:44:06.272 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 01:44:06.272 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 01:44:06.272 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 01:44:06.273 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 01:44:06.278 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 01:44:06.278 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 01:44:06.278 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 01:44:06.278 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 01:44:06.278 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.28.20:5700) Recv POWEROFF cmd
2026-01-29 01:44:06.279 [INFO] ctrl_if_trx.py:117 (BTS@172.18.28.20:5700) Stopping transceiver...
2026-01-29 01:44:06.279 [INFO] transceiver.py:246 Stopping clock generator
2026-01-29 01:44:06.279 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=3568 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 01:44:06.279 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=3568 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 01:44:06.279 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=3568 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 01:44:06.279 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=3568 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 01:44:06.279 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=3568 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 01:44:06.280 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=3568 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 01:44:06.280 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=3568 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 01:44:06.280 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=3568 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 01:44:06.280 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=3569 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 01:44:11.274 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.28.20:5700) Recv POWEROFF cmd
2026-01-29 01:44:11.275 [INFO] ctrl_if_trx.py:117 (BTS@172.18.28.20:5700) Stopping transceiver...
2026-01-29 01:44:11.276 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 01:44:11.277 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 01:44:11.277 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 01:44:11.277 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 01:44:11.285 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 01:44:11.286 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.28.20:5700) Recv SETFORMAT cmd
2026-01-29 01:44:11.287 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.28.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 01:44:11.287 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.28.20:5700) Recv SETFORMAT cmd
2026-01-29 01:44:11.287 [INFO] ctrl_if_trx.py:201 (BTS@172.18.28.20:5700) TRXD header version 1 -> 1
2026-01-29 01:44:11.291 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.28.20:5700/1) Recv RXTUNE cmd
2026-01-29 01:44:11.292 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.28.20:5700/1) Recv TXTUNE cmd
2026-01-29 01:44:11.292 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.28.20:5700/1) Recv SETFORMAT cmd
2026-01-29 01:44:11.292 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.28.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 01:44:11.293 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 01:44:11.293 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.28.20:5700/1) Recv NOMTXPOWER cmd
2026-01-29 01:44:11.294 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.28.20:5700/1) Recv SETFORMAT cmd
2026-01-29 01:44:11.294 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.28.20:5700/1) TRXD header version 1 -> 1
2026-01-29 01:44:11.295 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.28.20:5700/2) Recv RXTUNE cmd
2026-01-29 01:44:11.295 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.28.20:5700/2) Recv TXTUNE cmd
2026-01-29 01:44:11.295 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.28.20:5700/2) Recv SETFORMAT cmd
2026-01-29 01:44:11.295 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.28.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 01:44:11.296 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 01:44:11.296 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.28.20:5700/2) Recv NOMTXPOWER cmd
2026-01-29 01:44:11.296 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.28.20:5700/2) Recv SETFORMAT cmd
2026-01-29 01:44:11.296 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.28.20:5700/2) TRXD header version 1 -> 1
2026-01-29 01:44:11.299 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.28.20:5700/3) Recv RXTUNE cmd
2026-01-29 01:44:11.299 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.28.20:5700/3) Recv TXTUNE cmd
2026-01-29 01:44:11.299 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.28.20:5700/3) Recv SETFORMAT cmd
2026-01-29 01:44:11.299 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.28.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 01:44:11.299 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 01:44:11.299 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.28.20:5700/3) Recv NOMTXPOWER cmd
2026-01-29 01:44:11.299 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.28.20:5700/3) Recv SETFORMAT cmd
2026-01-29 01:44:11.299 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.28.20:5700/3) TRXD header version 1 -> 1
2026-01-29 01:44:11.303 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.28.20:5700) Recv RXTUNE cmd
2026-01-29 01:44:11.303 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETTSC
2026-01-29 01:44:11.303 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETTSC
2026-01-29 01:44:11.303 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETTSC
2026-01-29 01:44:11.303 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.28.20:5700) Recv TXTUNE cmd
2026-01-29 01:44:11.303 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETRXGAIN
2026-01-29 01:44:11.303 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETRXGAIN
2026-01-29 01:44:11.303 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETRXGAIN
2026-01-29 01:44:11.303 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETTSC
2026-01-29 01:44:11.303 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:44:11.303 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:44:11.303 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:44:11.303 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.28.20:5700) Recv NOMTXPOWER cmd
2026-01-29 01:44:11.303 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:44:11.303 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:44:11.303 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:44:11.303 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.28.20:5700) Recv POWERON CMD
2026-01-29 01:44:11.303 [INFO] ctrl_if_trx.py:109 (BTS@172.18.28.20:5700) Starting transceiver...
2026-01-29 01:44:11.303 [INFO] transceiver.py:243 Starting clock generator
2026-01-29 01:44:11.304 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-01-29 01:44:11.304 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:44:11.304 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:44:11.304 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:44:11.304 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETRXGAIN
2026-01-29 01:44:11.304 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:44:11.304 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:44:11.304 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:44:11.305 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 01:44:11.305 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:44:11.305 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:44:11.305 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:44:11.305 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 01:44:11.305 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:44:11.305 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:44:11.305 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:44:11.305 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 01:44:11.305 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:44:11.305 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:44:11.306 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:44:11.306 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 01:44:11.306 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:44:11.306 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:44:11.306 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:44:11.306 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 01:44:11.306 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 01:44:11.306 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 01:44:11.306 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 01:44:11.308 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-01-29 01:44:11.791 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-01-29 01:44:11.831 [DEBUG] fake_trx.py:278 (BTS@172.18.28.20:5700) Recv FAKE_TOA cmd
2026-01-29 01:44:11.832 [DEBUG] fake_trx.py:297 (BTS@172.18.28.20:5700) Recv FAKE_RSSI cmd
2026-01-29 01:44:11.835 [DEBUG] fake_trx.py:322 (BTS@172.18.28.20:5700) Recv FAKE_CI cmd
2026-01-29 01:44:11.835 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:44:11.852 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 01:44:11.852 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 01:44:11.853 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 01:44:11.859 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 01:44:11.860 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 01:44:11.860 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 01:44:11.861 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.28.22:6700) Recv POWERON CMD
2026-01-29 01:44:11.861 [INFO] ctrl_if_trx.py:109 (MS@172.18.28.22:6700) Starting transceiver...
2026-01-29 01:44:11.884 [DEBUG] fake_trx.py:297 (BTS@172.18.28.20:5700) Recv FAKE_RSSI cmd
2026-01-29 01:44:11.888 [DEBUG] fake_trx.py:278 (BTS@172.18.28.20:5700) Recv FAKE_TOA cmd
2026-01-29 01:44:11.895 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:44:11.900 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 01:44:11.900 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 01:44:11.900 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 01:44:11.900 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 01:44:12.269 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-01-29 01:44:12.307 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 01:44:12.308 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 01:44:12.310 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 01:44:12.313 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 01:44:12.747 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-01-29 01:44:12.770 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 01:44:12.771 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 01:44:12.775 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 01:44:12.775 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 01:44:12.775 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 01:44:12.775 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 01:44:12.776 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 01:44:12.776 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 01:44:12.776 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 01:44:12.776 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 01:44:12.776 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.28.20:5700) Recv POWEROFF cmd
2026-01-29 01:44:12.776 [INFO] ctrl_if_trx.py:117 (BTS@172.18.28.20:5700) Stopping transceiver...
2026-01-29 01:44:12.776 [INFO] transceiver.py:246 Stopping clock generator
2026-01-29 01:44:12.776 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=314 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 01:44:12.776 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=314 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 01:44:12.776 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=314 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 01:44:12.776 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=314 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 01:44:12.776 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=314 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 01:44:12.776 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=314 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 01:44:12.776 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=314 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 01:44:12.776 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=314 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 01:44:17.779 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.28.20:5700) Recv POWEROFF cmd
2026-01-29 01:44:17.779 [INFO] ctrl_if_trx.py:117 (BTS@172.18.28.20:5700) Stopping transceiver...
2026-01-29 01:44:17.781 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 01:44:17.782 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 01:44:17.782 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 01:44:17.783 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 01:44:17.790 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 01:44:17.791 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.28.20:5700) Recv SETFORMAT cmd
2026-01-29 01:44:17.791 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.28.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 01:44:17.791 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.28.20:5700) Recv SETFORMAT cmd
2026-01-29 01:44:17.791 [INFO] ctrl_if_trx.py:201 (BTS@172.18.28.20:5700) TRXD header version 1 -> 1
2026-01-29 01:44:17.793 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.28.20:5700/1) Recv RXTUNE cmd
2026-01-29 01:44:17.794 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.28.20:5700/1) Recv TXTUNE cmd
2026-01-29 01:44:17.794 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.28.20:5700/1) Recv SETFORMAT cmd
2026-01-29 01:44:17.794 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.28.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 01:44:17.794 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 01:44:17.795 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.28.20:5700/1) Recv NOMTXPOWER cmd
2026-01-29 01:44:17.795 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.28.20:5700/1) Recv SETFORMAT cmd
2026-01-29 01:44:17.795 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.28.20:5700/1) TRXD header version 1 -> 1
2026-01-29 01:44:17.796 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.28.20:5700/2) Recv RXTUNE cmd
2026-01-29 01:44:17.796 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.28.20:5700/2) Recv TXTUNE cmd
2026-01-29 01:44:17.796 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.28.20:5700/2) Recv SETFORMAT cmd
2026-01-29 01:44:17.796 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.28.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 01:44:17.796 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 01:44:17.797 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.28.20:5700/2) Recv NOMTXPOWER cmd
2026-01-29 01:44:17.797 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.28.20:5700/2) Recv SETFORMAT cmd
2026-01-29 01:44:17.797 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.28.20:5700/2) TRXD header version 1 -> 1
2026-01-29 01:44:17.798 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.28.20:5700/3) Recv RXTUNE cmd
2026-01-29 01:44:17.798 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.28.20:5700/3) Recv TXTUNE cmd
2026-01-29 01:44:17.798 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.28.20:5700/3) Recv SETFORMAT cmd
2026-01-29 01:44:17.798 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.28.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 01:44:17.798 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 01:44:17.798 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.28.20:5700/3) Recv NOMTXPOWER cmd
2026-01-29 01:44:17.798 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.28.20:5700/3) Recv SETFORMAT cmd
2026-01-29 01:44:17.798 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.28.20:5700/3) TRXD header version 1 -> 1
2026-01-29 01:44:17.801 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.28.20:5700) Recv RXTUNE cmd
2026-01-29 01:44:17.801 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETTSC
2026-01-29 01:44:17.801 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETTSC
2026-01-29 01:44:17.801 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETTSC
2026-01-29 01:44:17.801 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.28.20:5700) Recv TXTUNE cmd
2026-01-29 01:44:17.801 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETRXGAIN
2026-01-29 01:44:17.801 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETRXGAIN
2026-01-29 01:44:17.801 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETRXGAIN
2026-01-29 01:44:17.801 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETTSC
2026-01-29 01:44:17.801 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:44:17.801 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:44:17.801 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.28.20:5700) Recv NOMTXPOWER cmd
2026-01-29 01:44:17.801 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:44:17.801 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:44:17.801 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:44:17.801 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.28.20:5700) Recv POWERON CMD
2026-01-29 01:44:17.801 [INFO] ctrl_if_trx.py:109 (BTS@172.18.28.20:5700) Starting transceiver...
2026-01-29 01:44:17.801 [INFO] transceiver.py:243 Starting clock generator
2026-01-29 01:44:17.801 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-01-29 01:44:17.802 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:44:17.802 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:44:17.802 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:44:17.802 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETRXGAIN
2026-01-29 01:44:17.802 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:44:17.802 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:44:17.802 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:44:17.802 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 01:44:17.802 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:44:17.802 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:44:17.802 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:44:17.802 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 01:44:17.802 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:44:17.803 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:44:17.803 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:44:17.803 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 01:44:17.803 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:44:17.803 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:44:17.803 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:44:17.803 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 01:44:17.803 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:44:17.803 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:44:17.803 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:44:17.803 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 01:44:17.803 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:44:17.803 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 01:44:17.803 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 01:44:17.803 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 01:44:17.806 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-01-29 01:44:18.288 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-01-29 01:44:18.327 [DEBUG] fake_trx.py:278 (BTS@172.18.28.20:5700) Recv FAKE_TOA cmd
2026-01-29 01:44:18.329 [DEBUG] fake_trx.py:297 (BTS@172.18.28.20:5700) Recv FAKE_RSSI cmd
2026-01-29 01:44:18.330 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:44:18.331 [DEBUG] fake_trx.py:322 (BTS@172.18.28.20:5700) Recv FAKE_CI cmd
2026-01-29 01:44:18.356 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 01:44:18.356 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 01:44:18.356 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 01:44:18.361 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 01:44:18.361 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 01:44:18.361 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 01:44:18.361 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.28.22:6700) Recv POWERON CMD
2026-01-29 01:44:18.361 [INFO] ctrl_if_trx.py:109 (MS@172.18.28.22:6700) Starting transceiver...
2026-01-29 01:44:18.380 [DEBUG] fake_trx.py:297 (BTS@172.18.28.20:5700) Recv FAKE_RSSI cmd
2026-01-29 01:44:18.384 [DEBUG] fake_trx.py:278 (BTS@172.18.28.20:5700) Recv FAKE_TOA cmd
2026-01-29 01:44:18.392 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:44:18.398 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 01:44:18.398 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 01:44:18.398 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 01:44:18.399 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 01:44:18.766 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-01-29 01:44:18.804 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 01:44:18.805 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 01:44:18.806 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 01:44:18.809 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 01:44:19.244 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-01-29 01:44:19.722 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-01-29 01:44:19.806 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 01:44:19.824 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 01:44:19.825 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 01:44:19.825 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 01:44:20.200 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-01-29 01:44:20.678 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-01-29 01:44:20.825 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 01:44:20.825 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 01:44:20.825 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 01:44:20.825 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 01:44:21.156 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-01-29 01:44:21.634 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-01-29 01:44:21.826 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 01:44:21.826 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 01:44:21.826 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 01:44:21.826 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 01:44:22.112 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-01-29 01:44:22.590 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-01-29 01:44:22.826 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 01:44:22.827 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 01:44:22.827 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 01:44:22.827 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 01:44:23.068 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-01-29 01:44:23.543 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-01-29 01:44:24.015 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-01-29 01:44:24.493 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-01-29 01:44:24.971 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-01-29 01:44:25.449 [DEBUG] clck_gen.py:113 IND CLOCK 1632
2026-01-29 01:44:25.927 [DEBUG] clck_gen.py:113 IND CLOCK 1734
2026-01-29 01:44:26.400 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:44:26.403 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 01:44:26.403 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 01:44:26.404 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 01:44:26.405 [DEBUG] clck_gen.py:113 IND CLOCK 1836
2026-01-29 01:44:26.420 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 01:44:26.420 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 01:44:26.420 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 01:44:26.422 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 01:44:26.422 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 01:44:26.422 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 01:44:26.422 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.28.22:6700) Recv POWERON CMD
2026-01-29 01:44:26.422 [INFO] ctrl_if_trx.py:109 (MS@172.18.28.22:6700) Starting transceiver...
2026-01-29 01:44:26.450 [DEBUG] fake_trx.py:297 (BTS@172.18.28.20:5700) Recv FAKE_RSSI cmd
2026-01-29 01:44:26.454 [DEBUG] fake_trx.py:278 (BTS@172.18.28.20:5700) Recv FAKE_TOA cmd
2026-01-29 01:44:26.460 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:44:26.465 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 01:44:26.465 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 01:44:26.466 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 01:44:26.466 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 01:44:26.881 [DEBUG] clck_gen.py:113 IND CLOCK 1938
2026-01-29 01:44:27.358 [DEBUG] clck_gen.py:113 IND CLOCK 2040
2026-01-29 01:44:27.836 [DEBUG] clck_gen.py:113 IND CLOCK 2142
2026-01-29 01:44:28.314 [DEBUG] clck_gen.py:113 IND CLOCK 2244
2026-01-29 01:44:28.792 [DEBUG] clck_gen.py:113 IND CLOCK 2346
2026-01-29 01:44:29.270 [DEBUG] clck_gen.py:113 IND CLOCK 2448
2026-01-29 01:44:29.748 [DEBUG] clck_gen.py:113 IND CLOCK 2550
2026-01-29 01:44:30.226 [DEBUG] clck_gen.py:113 IND CLOCK 2652
2026-01-29 01:44:30.704 [DEBUG] clck_gen.py:113 IND CLOCK 2754
2026-01-29 01:44:31.182 [DEBUG] clck_gen.py:113 IND CLOCK 2856
2026-01-29 01:44:31.660 [DEBUG] clck_gen.py:113 IND CLOCK 2958
2026-01-29 01:44:32.138 [DEBUG] clck_gen.py:113 IND CLOCK 3060
2026-01-29 01:44:32.616 [DEBUG] clck_gen.py:113 IND CLOCK 3162
2026-01-29 01:44:33.094 [DEBUG] clck_gen.py:113 IND CLOCK 3264
2026-01-29 01:44:33.573 [DEBUG] clck_gen.py:113 IND CLOCK 3366
2026-01-29 01:44:34.051 [DEBUG] clck_gen.py:113 IND CLOCK 3468
2026-01-29 01:44:34.468 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:44:34.471 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 01:44:34.471 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 01:44:34.471 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 01:44:34.482 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 01:44:34.482 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 01:44:34.482 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 01:44:34.482 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 01:44:34.488 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 01:44:34.488 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 01:44:34.489 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 01:44:34.489 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 01:44:34.489 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.28.20:5700) Recv POWEROFF cmd
2026-01-29 01:44:34.489 [INFO] ctrl_if_trx.py:117 (BTS@172.18.28.20:5700) Stopping transceiver...
2026-01-29 01:44:34.489 [INFO] transceiver.py:246 Stopping clock generator
2026-01-29 01:44:34.489 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=3563 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 01:44:34.489 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=3563 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 01:44:39.486 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.28.20:5700) Recv POWEROFF cmd
2026-01-29 01:44:39.487 [INFO] ctrl_if_trx.py:117 (BTS@172.18.28.20:5700) Stopping transceiver...
2026-01-29 01:44:39.488 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 01:44:39.490 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 01:44:39.494 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 01:44:39.494 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 01:44:39.504 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 01:44:39.505 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.28.20:5700) Recv SETFORMAT cmd
2026-01-29 01:44:39.505 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.28.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 01:44:39.505 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.28.20:5700) Recv SETFORMAT cmd
2026-01-29 01:44:39.505 [INFO] ctrl_if_trx.py:201 (BTS@172.18.28.20:5700) TRXD header version 1 -> 1
2026-01-29 01:44:39.507 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.28.20:5700/1) Recv RXTUNE cmd
2026-01-29 01:44:39.507 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.28.20:5700/1) Recv TXTUNE cmd
2026-01-29 01:44:39.507 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.28.20:5700/1) Recv SETFORMAT cmd
2026-01-29 01:44:39.507 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.28.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 01:44:39.508 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 01:44:39.508 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.28.20:5700/1) Recv NOMTXPOWER cmd
2026-01-29 01:44:39.508 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.28.20:5700/1) Recv SETFORMAT cmd
2026-01-29 01:44:39.508 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.28.20:5700/1) TRXD header version 1 -> 1
2026-01-29 01:44:39.508 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.28.20:5700/2) Recv RXTUNE cmd
2026-01-29 01:44:39.509 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.28.20:5700/2) Recv TXTUNE cmd
2026-01-29 01:44:39.509 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.28.20:5700/2) Recv SETFORMAT cmd
2026-01-29 01:44:39.509 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.28.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 01:44:39.509 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 01:44:39.509 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.28.20:5700/2) Recv NOMTXPOWER cmd
2026-01-29 01:44:39.509 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.28.20:5700/2) Recv SETFORMAT cmd
2026-01-29 01:44:39.509 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.28.20:5700/2) TRXD header version 1 -> 1
2026-01-29 01:44:39.510 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.28.20:5700/3) Recv RXTUNE cmd
2026-01-29 01:44:39.510 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.28.20:5700/3) Recv TXTUNE cmd
2026-01-29 01:44:39.510 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.28.20:5700/3) Recv SETFORMAT cmd
2026-01-29 01:44:39.510 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.28.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 01:44:39.510 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 01:44:39.510 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.28.20:5700/3) Recv NOMTXPOWER cmd
2026-01-29 01:44:39.510 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.28.20:5700/3) Recv SETFORMAT cmd
2026-01-29 01:44:39.510 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.28.20:5700/3) TRXD header version 1 -> 1
2026-01-29 01:44:39.511 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.28.20:5700) Recv RXTUNE cmd
2026-01-29 01:44:39.511 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETTSC
2026-01-29 01:44:39.511 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETTSC
2026-01-29 01:44:39.511 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETTSC
2026-01-29 01:44:39.511 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.28.20:5700) Recv TXTUNE cmd
2026-01-29 01:44:39.512 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETRXGAIN
2026-01-29 01:44:39.512 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETRXGAIN
2026-01-29 01:44:39.512 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETRXGAIN
2026-01-29 01:44:39.512 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETTSC
2026-01-29 01:44:39.512 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:44:39.512 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:44:39.512 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:44:39.512 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.28.20:5700) Recv NOMTXPOWER cmd
2026-01-29 01:44:39.512 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:44:39.512 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:44:39.512 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:44:39.512 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.28.20:5700) Recv POWERON CMD
2026-01-29 01:44:39.512 [INFO] ctrl_if_trx.py:109 (BTS@172.18.28.20:5700) Starting transceiver...
2026-01-29 01:44:39.512 [INFO] transceiver.py:243 Starting clock generator
2026-01-29 01:44:39.512 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-01-29 01:44:39.512 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:44:39.512 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:44:39.512 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:44:39.512 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETRXGAIN
2026-01-29 01:44:39.512 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:44:39.512 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:44:39.512 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:44:39.512 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 01:44:39.512 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:44:39.512 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:44:39.512 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:44:39.512 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 01:44:39.512 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:44:39.512 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:44:39.513 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:44:39.513 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 01:44:39.513 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:44:39.513 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:44:39.513 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:44:39.513 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 01:44:39.513 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:44:39.513 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:44:39.513 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:44:39.513 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 01:44:39.513 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 01:44:39.513 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 01:44:39.513 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 01:44:39.517 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-01-29 01:44:40.000 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-01-29 01:44:40.036 [DEBUG] fake_trx.py:278 (BTS@172.18.28.20:5700) Recv FAKE_TOA cmd
2026-01-29 01:44:40.039 [DEBUG] fake_trx.py:297 (BTS@172.18.28.20:5700) Recv FAKE_RSSI cmd
2026-01-29 01:44:40.041 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:44:40.041 [DEBUG] fake_trx.py:322 (BTS@172.18.28.20:5700) Recv FAKE_CI cmd
2026-01-29 01:44:40.051 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 01:44:40.051 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 01:44:40.051 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 01:44:40.056 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 01:44:40.056 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 01:44:40.056 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 01:44:40.056 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.28.22:6700) Recv POWERON CMD
2026-01-29 01:44:40.056 [INFO] ctrl_if_trx.py:109 (MS@172.18.28.22:6700) Starting transceiver...
2026-01-29 01:44:40.092 [DEBUG] fake_trx.py:297 (BTS@172.18.28.20:5700) Recv FAKE_RSSI cmd
2026-01-29 01:44:40.096 [DEBUG] fake_trx.py:278 (BTS@172.18.28.20:5700) Recv FAKE_TOA cmd
2026-01-29 01:44:40.105 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:44:40.111 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 01:44:40.112 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 01:44:40.112 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 01:44:40.112 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 01:44:40.477 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-01-29 01:44:40.514 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 01:44:40.515 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 01:44:40.515 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 01:44:40.517 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 01:44:40.955 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-01-29 01:44:41.433 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-01-29 01:44:41.515 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 01:44:41.516 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 01:44:41.516 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 01:44:41.519 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 01:44:41.911 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-01-29 01:44:42.388 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-01-29 01:44:42.517 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 01:44:42.517 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 01:44:42.517 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 01:44:42.520 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 01:44:42.866 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-01-29 01:44:43.344 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-01-29 01:44:43.518 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 01:44:43.518 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 01:44:43.518 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 01:44:43.521 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 01:44:43.822 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-01-29 01:44:44.300 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-01-29 01:44:44.518 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 01:44:44.519 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 01:44:44.519 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 01:44:44.522 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 01:44:44.778 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-01-29 01:44:45.256 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-01-29 01:44:45.734 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-01-29 01:44:46.219 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-01-29 01:44:46.696 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-01-29 01:44:47.174 [DEBUG] clck_gen.py:113 IND CLOCK 1632
2026-01-29 01:44:47.652 [DEBUG] clck_gen.py:113 IND CLOCK 1734
2026-01-29 01:44:48.113 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:44:48.116 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 01:44:48.117 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 01:44:48.117 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 01:44:48.129 [DEBUG] clck_gen.py:113 IND CLOCK 1836
2026-01-29 01:44:48.131 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 01:44:48.131 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 01:44:48.131 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 01:44:48.133 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 01:44:48.133 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 01:44:48.133 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 01:44:48.133 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.28.22:6700) Recv POWERON CMD
2026-01-29 01:44:48.133 [INFO] ctrl_if_trx.py:109 (MS@172.18.28.22:6700) Starting transceiver...
2026-01-29 01:44:48.175 [DEBUG] fake_trx.py:297 (BTS@172.18.28.20:5700) Recv FAKE_RSSI cmd
2026-01-29 01:44:48.179 [DEBUG] fake_trx.py:278 (BTS@172.18.28.20:5700) Recv FAKE_TOA cmd
2026-01-29 01:44:48.186 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:44:48.190 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 01:44:48.190 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 01:44:48.191 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 01:44:48.191 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 01:44:48.606 [DEBUG] clck_gen.py:113 IND CLOCK 1938
2026-01-29 01:44:49.084 [DEBUG] clck_gen.py:113 IND CLOCK 2040
2026-01-29 01:44:49.562 [DEBUG] clck_gen.py:113 IND CLOCK 2142
2026-01-29 01:44:50.039 [DEBUG] clck_gen.py:113 IND CLOCK 2244
2026-01-29 01:44:50.517 [DEBUG] clck_gen.py:113 IND CLOCK 2346
2026-01-29 01:44:50.995 [DEBUG] clck_gen.py:113 IND CLOCK 2448
2026-01-29 01:44:51.473 [DEBUG] clck_gen.py:113 IND CLOCK 2550
2026-01-29 01:44:51.950 [DEBUG] clck_gen.py:113 IND CLOCK 2652
2026-01-29 01:44:52.428 [DEBUG] clck_gen.py:113 IND CLOCK 2754
2026-01-29 01:44:52.906 [DEBUG] clck_gen.py:113 IND CLOCK 2856
2026-01-29 01:44:53.384 [DEBUG] clck_gen.py:113 IND CLOCK 2958
2026-01-29 01:44:53.861 [DEBUG] clck_gen.py:113 IND CLOCK 3060
2026-01-29 01:44:54.338 [DEBUG] clck_gen.py:113 IND CLOCK 3162
2026-01-29 01:44:54.816 [DEBUG] clck_gen.py:113 IND CLOCK 3264
2026-01-29 01:44:55.294 [DEBUG] clck_gen.py:113 IND CLOCK 3366
2026-01-29 01:44:55.772 [DEBUG] clck_gen.py:113 IND CLOCK 3468
2026-01-29 01:44:56.192 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:44:56.195 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 01:44:56.195 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 01:44:56.195 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 01:44:56.209 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 01:44:56.209 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 01:44:56.209 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 01:44:56.211 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 01:44:56.211 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 01:44:56.211 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 01:44:56.211 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.28.22:6700) Recv POWERON CMD
2026-01-29 01:44:56.211 [INFO] ctrl_if_trx.py:109 (MS@172.18.28.22:6700) Starting transceiver...
2026-01-29 01:44:56.242 [DEBUG] fake_trx.py:297 (BTS@172.18.28.20:5700) Recv FAKE_RSSI cmd
2026-01-29 01:44:56.245 [DEBUG] fake_trx.py:278 (BTS@172.18.28.20:5700) Recv FAKE_TOA cmd
2026-01-29 01:44:56.249 [DEBUG] clck_gen.py:113 IND CLOCK 3570
2026-01-29 01:44:56.252 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:44:56.257 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 01:44:56.257 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 01:44:56.257 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 01:44:56.258 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 01:44:56.726 [DEBUG] clck_gen.py:113 IND CLOCK 3672
2026-01-29 01:44:57.204 [DEBUG] clck_gen.py:113 IND CLOCK 3774
2026-01-29 01:44:57.682 [DEBUG] clck_gen.py:113 IND CLOCK 3876
2026-01-29 01:44:58.159 [DEBUG] clck_gen.py:113 IND CLOCK 3978
2026-01-29 01:44:58.637 [DEBUG] clck_gen.py:113 IND CLOCK 4080
2026-01-29 01:44:59.114 [DEBUG] clck_gen.py:113 IND CLOCK 4182
2026-01-29 01:44:59.591 [DEBUG] clck_gen.py:113 IND CLOCK 4284
2026-01-29 01:45:00.069 [DEBUG] clck_gen.py:113 IND CLOCK 4386
2026-01-29 01:45:00.547 [DEBUG] clck_gen.py:113 IND CLOCK 4488
2026-01-29 01:45:01.025 [DEBUG] clck_gen.py:113 IND CLOCK 4590
2026-01-29 01:45:01.503 [DEBUG] clck_gen.py:113 IND CLOCK 4692
2026-01-29 01:45:01.980 [DEBUG] clck_gen.py:113 IND CLOCK 4794
2026-01-29 01:45:02.458 [DEBUG] clck_gen.py:113 IND CLOCK 4896
2026-01-29 01:45:02.936 [DEBUG] clck_gen.py:113 IND CLOCK 4998
2026-01-29 01:45:03.414 [DEBUG] clck_gen.py:113 IND CLOCK 5100
2026-01-29 01:45:03.892 [DEBUG] clck_gen.py:113 IND CLOCK 5202
2026-01-29 01:45:04.260 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:45:04.262 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 01:45:04.263 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 01:45:04.263 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 01:45:04.282 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 01:45:04.282 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 01:45:04.282 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 01:45:04.284 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 01:45:04.284 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 01:45:04.284 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 01:45:04.284 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.28.22:6700) Recv POWERON CMD
2026-01-29 01:45:04.284 [INFO] ctrl_if_trx.py:109 (MS@172.18.28.22:6700) Starting transceiver...
2026-01-29 01:45:04.313 [DEBUG] fake_trx.py:297 (BTS@172.18.28.20:5700) Recv FAKE_RSSI cmd
2026-01-29 01:45:04.317 [DEBUG] fake_trx.py:278 (BTS@172.18.28.20:5700) Recv FAKE_TOA cmd
2026-01-29 01:45:04.323 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:45:04.328 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 01:45:04.328 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 01:45:04.328 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 01:45:04.328 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 01:45:04.370 [DEBUG] clck_gen.py:113 IND CLOCK 5304
2026-01-29 01:45:04.848 [DEBUG] clck_gen.py:113 IND CLOCK 5406
2026-01-29 01:45:05.327 [DEBUG] clck_gen.py:113 IND CLOCK 5508
2026-01-29 01:45:05.805 [DEBUG] clck_gen.py:113 IND CLOCK 5610
2026-01-29 01:45:06.282 [DEBUG] clck_gen.py:113 IND CLOCK 5712
2026-01-29 01:45:06.760 [DEBUG] clck_gen.py:113 IND CLOCK 5814
2026-01-29 01:45:07.239 [DEBUG] clck_gen.py:113 IND CLOCK 5916
2026-01-29 01:45:07.716 [DEBUG] clck_gen.py:113 IND CLOCK 6018
2026-01-29 01:45:08.194 [DEBUG] clck_gen.py:113 IND CLOCK 6120
2026-01-29 01:45:08.671 [DEBUG] clck_gen.py:113 IND CLOCK 6222
2026-01-29 01:45:09.148 [DEBUG] clck_gen.py:113 IND CLOCK 6324
2026-01-29 01:45:09.626 [DEBUG] clck_gen.py:113 IND CLOCK 6426
2026-01-29 01:45:10.103 [DEBUG] clck_gen.py:113 IND CLOCK 6528
2026-01-29 01:45:10.581 [DEBUG] clck_gen.py:113 IND CLOCK 6630
2026-01-29 01:45:11.058 [DEBUG] clck_gen.py:113 IND CLOCK 6732
2026-01-29 01:45:11.536 [DEBUG] clck_gen.py:113 IND CLOCK 6834
2026-01-29 01:45:12.013 [DEBUG] clck_gen.py:113 IND CLOCK 6936
2026-01-29 01:45:12.330 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:45:12.332 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 01:45:12.333 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 01:45:12.333 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 01:45:12.344 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 01:45:12.344 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 01:45:12.344 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 01:45:12.344 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 01:45:12.345 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 01:45:12.345 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 01:45:12.345 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 01:45:12.345 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.28.20:5700) Recv POWEROFF cmd
2026-01-29 01:45:12.345 [INFO] ctrl_if_trx.py:117 (BTS@172.18.28.20:5700) Stopping transceiver...
2026-01-29 01:45:12.345 [INFO] transceiver.py:246 Stopping clock generator
2026-01-29 01:45:12.345 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 01:45:12.345 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=7009 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 01:45:12.345 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=7009 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 01:45:12.345 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=7009 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 01:45:12.345 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=7009 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 01:45:12.345 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=7010 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 01:45:12.345 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=7010 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 01:45:12.345 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=7010 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 01:45:12.345 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=7010 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 01:45:12.345 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=7010 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 01:45:12.345 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=7010 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 01:45:12.346 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=7010 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 01:45:12.346 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=7010 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 01:45:17.348 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.28.20:5700) Recv POWEROFF cmd
2026-01-29 01:45:17.348 [INFO] ctrl_if_trx.py:117 (BTS@172.18.28.20:5700) Stopping transceiver...
2026-01-29 01:45:17.349 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 01:45:17.351 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 01:45:17.351 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 01:45:17.351 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 01:45:17.365 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 01:45:17.367 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.28.20:5700) Recv SETFORMAT cmd
2026-01-29 01:45:17.367 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.28.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 01:45:17.368 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.28.20:5700) Recv SETFORMAT cmd
2026-01-29 01:45:17.368 [INFO] ctrl_if_trx.py:201 (BTS@172.18.28.20:5700) TRXD header version 1 -> 1
2026-01-29 01:45:17.372 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.28.20:5700/1) Recv RXTUNE cmd
2026-01-29 01:45:17.372 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.28.20:5700/1) Recv TXTUNE cmd
2026-01-29 01:45:17.373 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.28.20:5700/1) Recv SETFORMAT cmd
2026-01-29 01:45:17.373 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.28.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 01:45:17.373 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 01:45:17.373 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.28.20:5700/1) Recv NOMTXPOWER cmd
2026-01-29 01:45:17.374 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.28.20:5700/1) Recv SETFORMAT cmd
2026-01-29 01:45:17.374 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.28.20:5700/1) TRXD header version 1 -> 1
2026-01-29 01:45:17.375 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.28.20:5700/2) Recv RXTUNE cmd
2026-01-29 01:45:17.375 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.28.20:5700/2) Recv TXTUNE cmd
2026-01-29 01:45:17.376 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.28.20:5700/2) Recv SETFORMAT cmd
2026-01-29 01:45:17.376 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.28.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 01:45:17.376 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 01:45:17.376 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.28.20:5700/2) Recv NOMTXPOWER cmd
2026-01-29 01:45:17.376 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.28.20:5700/2) Recv SETFORMAT cmd
2026-01-29 01:45:17.376 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.28.20:5700/2) TRXD header version 1 -> 1
2026-01-29 01:45:17.378 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.28.20:5700/3) Recv RXTUNE cmd
2026-01-29 01:45:17.378 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.28.20:5700/3) Recv TXTUNE cmd
2026-01-29 01:45:17.378 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.28.20:5700/3) Recv SETFORMAT cmd
2026-01-29 01:45:17.378 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.28.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 01:45:17.378 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 01:45:17.378 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.28.20:5700/3) Recv NOMTXPOWER cmd
2026-01-29 01:45:17.378 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.28.20:5700/3) Recv SETFORMAT cmd
2026-01-29 01:45:17.378 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.28.20:5700/3) TRXD header version 1 -> 1
2026-01-29 01:45:17.381 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.28.20:5700) Recv RXTUNE cmd
2026-01-29 01:45:17.381 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETTSC
2026-01-29 01:45:17.381 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETTSC
2026-01-29 01:45:17.381 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETTSC
2026-01-29 01:45:17.381 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.28.20:5700) Recv TXTUNE cmd
2026-01-29 01:45:17.381 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETRXGAIN
2026-01-29 01:45:17.381 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETRXGAIN
2026-01-29 01:45:17.381 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETRXGAIN
2026-01-29 01:45:17.381 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETTSC
2026-01-29 01:45:17.381 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:45:17.381 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:45:17.381 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:45:17.381 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.28.20:5700) Recv NOMTXPOWER cmd
2026-01-29 01:45:17.381 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:45:17.382 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:45:17.382 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:45:17.382 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.28.20:5700) Recv POWERON CMD
2026-01-29 01:45:17.382 [INFO] ctrl_if_trx.py:109 (BTS@172.18.28.20:5700) Starting transceiver...
2026-01-29 01:45:17.382 [INFO] transceiver.py:243 Starting clock generator
2026-01-29 01:45:17.382 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-01-29 01:45:17.382 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:45:17.382 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:45:17.382 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:45:17.382 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETRXGAIN
2026-01-29 01:45:17.382 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:45:17.383 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:45:17.383 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:45:17.383 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 01:45:17.383 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:45:17.383 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:45:17.383 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:45:17.383 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 01:45:17.383 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:45:17.383 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:45:17.383 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:45:17.383 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 01:45:17.383 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:45:17.384 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:45:17.384 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:45:17.384 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 01:45:17.384 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:45:17.384 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:45:17.384 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:45:17.384 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 01:45:17.384 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 01:45:17.384 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 01:45:17.384 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 01:45:17.387 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-01-29 01:45:17.869 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-01-29 01:45:17.909 [DEBUG] fake_trx.py:278 (BTS@172.18.28.20:5700) Recv FAKE_TOA cmd
2026-01-29 01:45:17.910 [DEBUG] fake_trx.py:297 (BTS@172.18.28.20:5700) Recv FAKE_RSSI cmd
2026-01-29 01:45:17.912 [DEBUG] fake_trx.py:322 (BTS@172.18.28.20:5700) Recv FAKE_CI cmd
2026-01-29 01:45:17.912 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:45:17.927 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 01:45:17.927 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 01:45:17.928 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 01:45:17.933 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 01:45:17.933 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 01:45:17.934 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 01:45:17.934 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.28.22:6700) Recv POWERON CMD
2026-01-29 01:45:17.934 [INFO] ctrl_if_trx.py:109 (MS@172.18.28.22:6700) Starting transceiver...
2026-01-29 01:45:17.961 [DEBUG] fake_trx.py:297 (BTS@172.18.28.20:5700) Recv FAKE_RSSI cmd
2026-01-29 01:45:17.965 [DEBUG] fake_trx.py:278 (BTS@172.18.28.20:5700) Recv FAKE_TOA cmd
2026-01-29 01:45:17.973 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:45:17.978 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 01:45:17.979 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 01:45:17.979 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 01:45:17.979 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 01:45:18.346 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-01-29 01:45:18.385 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 01:45:18.387 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 01:45:18.388 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 01:45:18.392 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 01:45:18.823 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-01-29 01:45:19.302 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-01-29 01:45:19.386 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 01:45:19.388 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 01:45:19.389 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 01:45:19.393 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 01:45:19.780 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-01-29 01:45:20.258 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-01-29 01:45:20.387 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 01:45:20.388 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 01:45:20.390 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 01:45:20.394 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 01:45:20.736 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-01-29 01:45:21.214 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-01-29 01:45:21.388 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 01:45:21.389 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 01:45:21.391 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 01:45:21.395 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 01:45:21.692 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-01-29 01:45:22.170 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-01-29 01:45:22.390 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 01:45:22.390 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 01:45:22.391 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 01:45:22.396 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 01:45:22.648 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-01-29 01:45:23.126 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-01-29 01:45:23.603 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-01-29 01:45:24.082 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-01-29 01:45:24.560 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-01-29 01:45:25.038 [DEBUG] clck_gen.py:113 IND CLOCK 1632
2026-01-29 01:45:25.516 [DEBUG] clck_gen.py:113 IND CLOCK 1734
2026-01-29 01:45:25.981 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:45:25.983 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 01:45:25.984 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 01:45:25.984 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 01:45:25.993 [DEBUG] clck_gen.py:113 IND CLOCK 1836
2026-01-29 01:45:26.005 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 01:45:26.005 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 01:45:26.005 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 01:45:26.007 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 01:45:26.007 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 01:45:26.007 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 01:45:26.007 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.28.22:6700) Recv POWERON CMD
2026-01-29 01:45:26.007 [INFO] ctrl_if_trx.py:109 (MS@172.18.28.22:6700) Starting transceiver...
2026-01-29 01:45:26.039 [DEBUG] fake_trx.py:297 (BTS@172.18.28.20:5700) Recv FAKE_RSSI cmd
2026-01-29 01:45:26.043 [DEBUG] fake_trx.py:278 (BTS@172.18.28.20:5700) Recv FAKE_TOA cmd
2026-01-29 01:45:26.050 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:45:26.053 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 01:45:26.053 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 01:45:26.054 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 01:45:26.054 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 01:45:26.470 [DEBUG] clck_gen.py:113 IND CLOCK 1938
2026-01-29 01:45:26.948 [DEBUG] clck_gen.py:113 IND CLOCK 2040
2026-01-29 01:45:27.426 [DEBUG] clck_gen.py:113 IND CLOCK 2142
2026-01-29 01:45:27.904 [DEBUG] clck_gen.py:113 IND CLOCK 2244
2026-01-29 01:45:28.382 [DEBUG] clck_gen.py:113 IND CLOCK 2346
2026-01-29 01:45:28.859 [DEBUG] clck_gen.py:113 IND CLOCK 2448
2026-01-29 01:45:29.337 [DEBUG] clck_gen.py:113 IND CLOCK 2550
2026-01-29 01:45:29.815 [DEBUG] clck_gen.py:113 IND CLOCK 2652
2026-01-29 01:45:30.293 [DEBUG] clck_gen.py:113 IND CLOCK 2754
2026-01-29 01:45:30.771 [DEBUG] clck_gen.py:113 IND CLOCK 2856
2026-01-29 01:45:31.250 [DEBUG] clck_gen.py:113 IND CLOCK 2958
2026-01-29 01:45:31.727 [DEBUG] clck_gen.py:113 IND CLOCK 3060
2026-01-29 01:45:32.205 [DEBUG] clck_gen.py:113 IND CLOCK 3162
2026-01-29 01:45:32.683 [DEBUG] clck_gen.py:113 IND CLOCK 3264
2026-01-29 01:45:33.162 [DEBUG] clck_gen.py:113 IND CLOCK 3366
2026-01-29 01:45:33.640 [DEBUG] clck_gen.py:113 IND CLOCK 3468
2026-01-29 01:45:34.056 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:45:34.058 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 01:45:34.059 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 01:45:34.059 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 01:45:34.079 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 01:45:34.079 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 01:45:34.079 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 01:45:34.081 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 01:45:34.081 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 01:45:34.081 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 01:45:34.081 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.28.22:6700) Recv POWERON CMD
2026-01-29 01:45:34.081 [INFO] ctrl_if_trx.py:109 (MS@172.18.28.22:6700) Starting transceiver...
2026-01-29 01:45:34.110 [DEBUG] fake_trx.py:297 (BTS@172.18.28.20:5700) Recv FAKE_RSSI cmd
2026-01-29 01:45:34.114 [DEBUG] fake_trx.py:278 (BTS@172.18.28.20:5700) Recv FAKE_TOA cmd
2026-01-29 01:45:34.117 [DEBUG] clck_gen.py:113 IND CLOCK 3570
2026-01-29 01:45:34.121 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:45:34.124 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 01:45:34.124 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 01:45:34.125 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 01:45:34.125 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 01:45:34.595 [DEBUG] clck_gen.py:113 IND CLOCK 3672
2026-01-29 01:45:35.073 [DEBUG] clck_gen.py:113 IND CLOCK 3774
2026-01-29 01:45:35.550 [DEBUG] clck_gen.py:113 IND CLOCK 3876
2026-01-29 01:45:36.028 [DEBUG] clck_gen.py:113 IND CLOCK 3978
2026-01-29 01:45:36.506 [DEBUG] clck_gen.py:113 IND CLOCK 4080
2026-01-29 01:45:36.984 [DEBUG] clck_gen.py:113 IND CLOCK 4182
2026-01-29 01:45:37.462 [DEBUG] clck_gen.py:113 IND CLOCK 4284
2026-01-29 01:45:37.940 [DEBUG] clck_gen.py:113 IND CLOCK 4386
2026-01-29 01:45:38.417 [DEBUG] clck_gen.py:113 IND CLOCK 4488
2026-01-29 01:45:38.895 [DEBUG] clck_gen.py:113 IND CLOCK 4590
2026-01-29 01:45:39.373 [DEBUG] clck_gen.py:113 IND CLOCK 4692
2026-01-29 01:45:39.851 [DEBUG] clck_gen.py:113 IND CLOCK 4794
2026-01-29 01:45:40.328 [DEBUG] clck_gen.py:113 IND CLOCK 4896
2026-01-29 01:45:40.805 [DEBUG] clck_gen.py:113 IND CLOCK 4998
2026-01-29 01:45:41.283 [DEBUG] clck_gen.py:113 IND CLOCK 5100
2026-01-29 01:45:41.761 [DEBUG] clck_gen.py:113 IND CLOCK 5202
2026-01-29 01:45:42.127 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:45:42.130 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 01:45:42.131 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 01:45:42.131 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 01:45:42.150 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 01:45:42.150 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 01:45:42.150 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 01:45:42.152 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 01:45:42.152 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 01:45:42.152 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 01:45:42.152 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.28.22:6700) Recv POWERON CMD
2026-01-29 01:45:42.152 [INFO] ctrl_if_trx.py:109 (MS@172.18.28.22:6700) Starting transceiver...
2026-01-29 01:45:42.180 [DEBUG] fake_trx.py:297 (BTS@172.18.28.20:5700) Recv FAKE_RSSI cmd
2026-01-29 01:45:42.184 [DEBUG] fake_trx.py:278 (BTS@172.18.28.20:5700) Recv FAKE_TOA cmd
2026-01-29 01:45:42.191 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:45:42.195 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 01:45:42.196 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 01:45:42.196 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 01:45:42.196 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 01:45:42.238 [DEBUG] clck_gen.py:113 IND CLOCK 5304
2026-01-29 01:45:42.715 [DEBUG] clck_gen.py:113 IND CLOCK 5406
2026-01-29 01:45:43.194 [DEBUG] clck_gen.py:113 IND CLOCK 5508
2026-01-29 01:45:43.671 [DEBUG] clck_gen.py:113 IND CLOCK 5610
2026-01-29 01:45:44.150 [DEBUG] clck_gen.py:113 IND CLOCK 5712
2026-01-29 01:45:44.628 [DEBUG] clck_gen.py:113 IND CLOCK 5814
2026-01-29 01:45:45.105 [DEBUG] clck_gen.py:113 IND CLOCK 5916
2026-01-29 01:45:45.582 [DEBUG] clck_gen.py:113 IND CLOCK 6018
2026-01-29 01:45:46.061 [DEBUG] clck_gen.py:113 IND CLOCK 6120
2026-01-29 01:45:46.538 [DEBUG] clck_gen.py:113 IND CLOCK 6222
2026-01-29 01:45:47.016 [DEBUG] clck_gen.py:113 IND CLOCK 6324
2026-01-29 01:45:47.494 [DEBUG] clck_gen.py:113 IND CLOCK 6426
2026-01-29 01:45:47.972 [DEBUG] clck_gen.py:113 IND CLOCK 6528
2026-01-29 01:45:48.449 [DEBUG] clck_gen.py:113 IND CLOCK 6630
2026-01-29 01:45:48.927 [DEBUG] clck_gen.py:113 IND CLOCK 6732
2026-01-29 01:45:49.404 [DEBUG] clck_gen.py:113 IND CLOCK 6834
2026-01-29 01:45:49.882 [DEBUG] clck_gen.py:113 IND CLOCK 6936
2026-01-29 01:45:50.197 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:45:50.200 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 01:45:50.201 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 01:45:50.201 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 01:45:50.210 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 01:45:50.210 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 01:45:50.210 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 01:45:50.211 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 01:45:50.211 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 01:45:50.212 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 01:45:50.212 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.28.22:6700) Recv POWERON CMD
2026-01-29 01:45:50.212 [INFO] ctrl_if_trx.py:109 (MS@172.18.28.22:6700) Starting transceiver...
2026-01-29 01:45:50.255 [DEBUG] fake_trx.py:297 (BTS@172.18.28.20:5700) Recv FAKE_RSSI cmd
2026-01-29 01:45:50.259 [DEBUG] fake_trx.py:278 (BTS@172.18.28.20:5700) Recv FAKE_TOA cmd
2026-01-29 01:45:50.265 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:45:50.269 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 01:45:50.269 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 01:45:50.270 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 01:45:50.270 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 01:45:50.359 [DEBUG] clck_gen.py:113 IND CLOCK 7038
2026-01-29 01:45:50.838 [DEBUG] clck_gen.py:113 IND CLOCK 7140
2026-01-29 01:45:51.316 [DEBUG] clck_gen.py:113 IND CLOCK 7242
2026-01-29 01:45:51.793 [DEBUG] clck_gen.py:113 IND CLOCK 7344
2026-01-29 01:45:52.271 [DEBUG] clck_gen.py:113 IND CLOCK 7446
2026-01-29 01:45:52.750 [DEBUG] clck_gen.py:113 IND CLOCK 7548
2026-01-29 01:45:53.227 [DEBUG] clck_gen.py:113 IND CLOCK 7650
2026-01-29 01:45:53.704 [DEBUG] clck_gen.py:113 IND CLOCK 7752
2026-01-29 01:45:54.183 [DEBUG] clck_gen.py:113 IND CLOCK 7854
2026-01-29 01:45:54.661 [DEBUG] clck_gen.py:113 IND CLOCK 7956
2026-01-29 01:45:55.139 [DEBUG] clck_gen.py:113 IND CLOCK 8058
2026-01-29 01:45:55.617 [DEBUG] clck_gen.py:113 IND CLOCK 8160
2026-01-29 01:45:56.094 [DEBUG] clck_gen.py:113 IND CLOCK 8262
2026-01-29 01:45:56.573 [DEBUG] clck_gen.py:113 IND CLOCK 8364
2026-01-29 01:45:57.050 [DEBUG] clck_gen.py:113 IND CLOCK 8466
2026-01-29 01:45:57.528 [DEBUG] clck_gen.py:113 IND CLOCK 8568
2026-01-29 01:45:58.006 [DEBUG] clck_gen.py:113 IND CLOCK 8670
2026-01-29 01:45:58.271 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:45:58.273 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 01:45:58.274 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 01:45:58.274 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 01:45:58.294 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 01:45:58.294 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 01:45:58.294 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 01:45:58.296 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 01:45:58.296 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 01:45:58.296 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 01:45:58.296 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.28.22:6700) Recv POWERON CMD
2026-01-29 01:45:58.296 [INFO] ctrl_if_trx.py:109 (MS@172.18.28.22:6700) Starting transceiver...
2026-01-29 01:45:58.333 [DEBUG] fake_trx.py:297 (BTS@172.18.28.20:5700) Recv FAKE_RSSI cmd
2026-01-29 01:45:58.337 [DEBUG] fake_trx.py:278 (BTS@172.18.28.20:5700) Recv FAKE_TOA cmd
2026-01-29 01:45:58.343 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:45:58.347 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 01:45:58.347 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 01:45:58.348 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 01:45:58.348 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 01:45:58.483 [DEBUG] clck_gen.py:113 IND CLOCK 8772
2026-01-29 01:45:58.961 [DEBUG] clck_gen.py:113 IND CLOCK 8874
2026-01-29 01:45:59.438 [DEBUG] clck_gen.py:113 IND CLOCK 8976
2026-01-29 01:45:59.915 [DEBUG] clck_gen.py:113 IND CLOCK 9078
2026-01-29 01:46:00.394 [DEBUG] clck_gen.py:113 IND CLOCK 9180
2026-01-29 01:46:00.872 [DEBUG] clck_gen.py:113 IND CLOCK 9282
2026-01-29 01:46:01.350 [DEBUG] clck_gen.py:113 IND CLOCK 9384
2026-01-29 01:46:01.828 [DEBUG] clck_gen.py:113 IND CLOCK 9486
2026-01-29 01:46:02.306 [DEBUG] clck_gen.py:113 IND CLOCK 9588
2026-01-29 01:46:02.784 [DEBUG] clck_gen.py:113 IND CLOCK 9690
2026-01-29 01:46:03.261 [DEBUG] clck_gen.py:113 IND CLOCK 9792
2026-01-29 01:46:03.739 [DEBUG] clck_gen.py:113 IND CLOCK 9894
2026-01-29 01:46:04.217 [DEBUG] clck_gen.py:113 IND CLOCK 9996
2026-01-29 01:46:04.695 [DEBUG] clck_gen.py:113 IND CLOCK 10098
2026-01-29 01:46:05.173 [DEBUG] clck_gen.py:113 IND CLOCK 10200
2026-01-29 01:46:05.651 [DEBUG] clck_gen.py:113 IND CLOCK 10302
2026-01-29 01:46:06.128 [DEBUG] clck_gen.py:113 IND CLOCK 10404
2026-01-29 01:46:06.349 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:46:06.351 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 01:46:06.352 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 01:46:06.352 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 01:46:06.369 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 01:46:06.369 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 01:46:06.370 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 01:46:06.371 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 01:46:06.371 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 01:46:06.371 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 01:46:06.371 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.28.22:6700) Recv POWERON CMD
2026-01-29 01:46:06.371 [INFO] ctrl_if_trx.py:109 (MS@172.18.28.22:6700) Starting transceiver...
2026-01-29 01:46:06.409 [DEBUG] fake_trx.py:297 (BTS@172.18.28.20:5700) Recv FAKE_RSSI cmd
2026-01-29 01:46:06.413 [DEBUG] fake_trx.py:278 (BTS@172.18.28.20:5700) Recv FAKE_TOA cmd
2026-01-29 01:46:06.419 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:46:06.422 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 01:46:06.423 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 01:46:06.423 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 01:46:06.423 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 01:46:06.601 [DEBUG] clck_gen.py:113 IND CLOCK 10506
2026-01-29 01:46:07.079 [DEBUG] clck_gen.py:113 IND CLOCK 10608
2026-01-29 01:46:07.557 [DEBUG] clck_gen.py:113 IND CLOCK 10710
2026-01-29 01:46:08.036 [DEBUG] clck_gen.py:113 IND CLOCK 10812
2026-01-29 01:46:08.513 [DEBUG] clck_gen.py:113 IND CLOCK 10914
2026-01-29 01:46:08.990 [DEBUG] clck_gen.py:113 IND CLOCK 11016
2026-01-29 01:46:09.468 [DEBUG] clck_gen.py:113 IND CLOCK 11118
2026-01-29 01:46:09.946 [DEBUG] clck_gen.py:113 IND CLOCK 11220
2026-01-29 01:46:10.424 [DEBUG] clck_gen.py:113 IND CLOCK 11322
2026-01-29 01:46:10.902 [DEBUG] clck_gen.py:113 IND CLOCK 11424
2026-01-29 01:46:11.380 [DEBUG] clck_gen.py:113 IND CLOCK 11526
2026-01-29 01:46:11.858 [DEBUG] clck_gen.py:113 IND CLOCK 11628
2026-01-29 01:46:12.336 [DEBUG] clck_gen.py:113 IND CLOCK 11730
2026-01-29 01:46:12.814 [DEBUG] clck_gen.py:113 IND CLOCK 11832
2026-01-29 01:46:13.291 [DEBUG] clck_gen.py:113 IND CLOCK 11934
2026-01-29 01:46:13.768 [DEBUG] clck_gen.py:113 IND CLOCK 12036
2026-01-29 01:46:14.245 [DEBUG] clck_gen.py:113 IND CLOCK 12138
2026-01-29 01:46:14.424 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:46:14.427 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 01:46:14.427 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 01:46:14.428 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 01:46:14.447 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 01:46:14.447 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 01:46:14.448 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 01:46:14.449 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 01:46:14.449 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 01:46:14.449 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 01:46:14.450 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.28.22:6700) Recv POWERON CMD
2026-01-29 01:46:14.450 [INFO] ctrl_if_trx.py:109 (MS@172.18.28.22:6700) Starting transceiver...
2026-01-29 01:46:14.480 [DEBUG] fake_trx.py:297 (BTS@172.18.28.20:5700) Recv FAKE_RSSI cmd
2026-01-29 01:46:14.484 [DEBUG] fake_trx.py:278 (BTS@172.18.28.20:5700) Recv FAKE_TOA cmd
2026-01-29 01:46:14.490 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:46:14.494 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 01:46:14.494 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 01:46:14.494 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 01:46:14.494 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 01:46:14.723 [DEBUG] clck_gen.py:113 IND CLOCK 12240
2026-01-29 01:46:15.201 [DEBUG] clck_gen.py:113 IND CLOCK 12342
2026-01-29 01:46:15.678 [DEBUG] clck_gen.py:113 IND CLOCK 12444
2026-01-29 01:46:16.156 [DEBUG] clck_gen.py:113 IND CLOCK 12546
2026-01-29 01:46:16.634 [DEBUG] clck_gen.py:113 IND CLOCK 12648
2026-01-29 01:46:17.111 [DEBUG] clck_gen.py:113 IND CLOCK 12750
2026-01-29 01:46:17.589 [DEBUG] clck_gen.py:113 IND CLOCK 12852
2026-01-29 01:46:18.067 [DEBUG] clck_gen.py:113 IND CLOCK 12954
2026-01-29 01:46:18.544 [DEBUG] clck_gen.py:113 IND CLOCK 13056
2026-01-29 01:46:19.022 [DEBUG] clck_gen.py:113 IND CLOCK 13158
2026-01-29 01:46:19.500 [DEBUG] clck_gen.py:113 IND CLOCK 13260
2026-01-29 01:46:19.977 [DEBUG] clck_gen.py:113 IND CLOCK 13362
2026-01-29 01:46:20.455 [DEBUG] clck_gen.py:113 IND CLOCK 13464
2026-01-29 01:46:20.933 [DEBUG] clck_gen.py:113 IND CLOCK 13566
2026-01-29 01:46:21.411 [DEBUG] clck_gen.py:113 IND CLOCK 13668
2026-01-29 01:46:21.889 [DEBUG] clck_gen.py:113 IND CLOCK 13770
2026-01-29 01:46:22.366 [DEBUG] clck_gen.py:113 IND CLOCK 13872
2026-01-29 01:46:22.496 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:46:22.499 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 01:46:22.499 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 01:46:22.499 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 01:46:22.513 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 01:46:22.513 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 01:46:22.513 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 01:46:22.513 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 01:46:22.515 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 01:46:22.516 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 01:46:22.516 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 01:46:22.516 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 01:46:22.516 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.28.20:5700) Recv POWEROFF cmd
2026-01-29 01:46:22.516 [INFO] ctrl_if_trx.py:117 (BTS@172.18.28.20:5700) Stopping transceiver...
2026-01-29 01:46:22.516 [INFO] transceiver.py:246 Stopping clock generator
2026-01-29 01:46:22.516 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=13905 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 01:46:22.516 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=13905 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 01:46:22.516 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=13905 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 01:46:22.516 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=13905 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 01:46:22.516 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=13905 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 01:46:22.516 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=13905 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 01:46:22.516 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=13905 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 01:46:22.516 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=13906 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 01:46:22.516 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=13906 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 01:46:22.516 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=13906 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 01:46:22.516 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=13906 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 01:46:22.516 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=13906 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 01:46:22.516 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=13906 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 01:46:22.516 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=13906 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 01:46:22.516 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=13906 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 01:46:27.517 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.28.20:5700) Recv POWEROFF cmd
2026-01-29 01:46:27.517 [INFO] ctrl_if_trx.py:117 (BTS@172.18.28.20:5700) Stopping transceiver...
2026-01-29 01:46:27.518 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 01:46:27.520 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 01:46:27.520 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 01:46:27.521 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 01:46:27.525 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 01:46:27.526 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.28.20:5700) Recv SETFORMAT cmd
2026-01-29 01:46:27.526 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.28.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 01:46:27.526 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.28.20:5700) Recv SETFORMAT cmd
2026-01-29 01:46:27.526 [INFO] ctrl_if_trx.py:201 (BTS@172.18.28.20:5700) TRXD header version 1 -> 1
2026-01-29 01:46:27.528 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.28.20:5700/1) Recv RXTUNE cmd
2026-01-29 01:46:27.529 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.28.20:5700/1) Recv TXTUNE cmd
2026-01-29 01:46:27.529 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.28.20:5700/1) Recv SETFORMAT cmd
2026-01-29 01:46:27.529 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.28.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 01:46:27.529 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 01:46:27.529 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.28.20:5700/1) Recv NOMTXPOWER cmd
2026-01-29 01:46:27.529 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.28.20:5700/1) Recv SETFORMAT cmd
2026-01-29 01:46:27.529 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.28.20:5700/1) TRXD header version 1 -> 1
2026-01-29 01:46:27.531 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.28.20:5700/2) Recv RXTUNE cmd
2026-01-29 01:46:27.531 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.28.20:5700/2) Recv TXTUNE cmd
2026-01-29 01:46:27.531 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.28.20:5700/2) Recv SETFORMAT cmd
2026-01-29 01:46:27.531 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.28.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 01:46:27.531 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 01:46:27.531 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.28.20:5700/2) Recv NOMTXPOWER cmd
2026-01-29 01:46:27.532 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.28.20:5700/2) Recv SETFORMAT cmd
2026-01-29 01:46:27.532 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.28.20:5700/2) TRXD header version 1 -> 1
2026-01-29 01:46:27.533 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.28.20:5700/3) Recv RXTUNE cmd
2026-01-29 01:46:27.533 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.28.20:5700/3) Recv TXTUNE cmd
2026-01-29 01:46:27.533 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.28.20:5700/3) Recv SETFORMAT cmd
2026-01-29 01:46:27.533 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.28.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 01:46:27.533 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 01:46:27.533 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.28.20:5700/3) Recv NOMTXPOWER cmd
2026-01-29 01:46:27.533 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.28.20:5700/3) Recv SETFORMAT cmd
2026-01-29 01:46:27.533 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.28.20:5700/3) TRXD header version 1 -> 1
2026-01-29 01:46:27.535 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.28.20:5700) Recv RXTUNE cmd
2026-01-29 01:46:27.535 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETTSC
2026-01-29 01:46:27.535 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETTSC
2026-01-29 01:46:27.535 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETTSC
2026-01-29 01:46:27.535 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.28.20:5700) Recv TXTUNE cmd
2026-01-29 01:46:27.536 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETRXGAIN
2026-01-29 01:46:27.536 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETRXGAIN
2026-01-29 01:46:27.536 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETRXGAIN
2026-01-29 01:46:27.536 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETTSC
2026-01-29 01:46:27.536 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:46:27.536 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:46:27.536 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:46:27.536 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.28.20:5700) Recv NOMTXPOWER cmd
2026-01-29 01:46:27.536 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:46:27.536 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:46:27.536 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:46:27.536 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.28.20:5700) Recv POWERON CMD
2026-01-29 01:46:27.536 [INFO] ctrl_if_trx.py:109 (BTS@172.18.28.20:5700) Starting transceiver...
2026-01-29 01:46:27.536 [INFO] transceiver.py:243 Starting clock generator
2026-01-29 01:46:27.536 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-01-29 01:46:27.536 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:46:27.536 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:46:27.536 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:46:27.536 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETRXGAIN
2026-01-29 01:46:27.537 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:46:27.537 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:46:27.537 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:46:27.537 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 01:46:27.537 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:46:27.537 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:46:27.537 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:46:27.537 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 01:46:27.537 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:46:27.537 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:46:27.537 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 01:46:27.537 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:46:27.537 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:46:27.537 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:46:27.537 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 01:46:27.537 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:46:27.537 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:46:27.537 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:46:27.537 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 01:46:27.537 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:46:27.537 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 01:46:27.537 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 01:46:27.537 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 01:46:27.541 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-01-29 01:46:28.023 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-01-29 01:46:28.055 [DEBUG] fake_trx.py:278 (BTS@172.18.28.20:5700) Recv FAKE_TOA cmd
2026-01-29 01:46:28.056 [DEBUG] fake_trx.py:297 (BTS@172.18.28.20:5700) Recv FAKE_RSSI cmd
2026-01-29 01:46:28.057 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:46:28.057 [DEBUG] fake_trx.py:322 (BTS@172.18.28.20:5700) Recv FAKE_CI cmd
2026-01-29 01:46:28.079 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 01:46:28.079 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 01:46:28.080 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 01:46:28.086 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 01:46:28.086 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 01:46:28.086 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 01:46:28.086 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.28.22:6700) Recv POWERON CMD
2026-01-29 01:46:28.086 [INFO] ctrl_if_trx.py:109 (MS@172.18.28.22:6700) Starting transceiver...
2026-01-29 01:46:28.115 [DEBUG] fake_trx.py:297 (BTS@172.18.28.20:5700) Recv FAKE_RSSI cmd
2026-01-29 01:46:28.119 [DEBUG] fake_trx.py:278 (BTS@172.18.28.20:5700) Recv FAKE_TOA cmd
2026-01-29 01:46:28.127 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:46:28.132 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 01:46:28.132 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 01:46:28.132 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 01:46:28.133 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 01:46:28.501 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-01-29 01:46:28.539 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 01:46:28.539 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 01:46:28.539 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 01:46:28.542 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 01:46:28.979 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-01-29 01:46:29.457 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-01-29 01:46:29.540 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 01:46:29.540 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 01:46:29.540 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 01:46:29.543 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 01:46:29.935 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-01-29 01:46:30.413 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-01-29 01:46:30.540 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 01:46:30.541 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 01:46:30.541 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 01:46:30.543 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 01:46:30.892 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-01-29 01:46:31.370 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-01-29 01:46:31.541 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 01:46:31.542 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 01:46:31.542 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 01:46:31.545 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 01:46:31.848 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-01-29 01:46:32.326 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-01-29 01:46:32.542 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 01:46:32.543 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 01:46:32.543 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 01:46:32.546 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 01:46:32.804 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-01-29 01:46:33.282 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-01-29 01:46:33.761 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-01-29 01:46:34.239 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-01-29 01:46:34.717 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-01-29 01:46:35.196 [DEBUG] clck_gen.py:113 IND CLOCK 1632
2026-01-29 01:46:35.674 [DEBUG] clck_gen.py:113 IND CLOCK 1734
2026-01-29 01:46:36.136 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:46:36.152 [DEBUG] clck_gen.py:113 IND CLOCK 1836
2026-01-29 01:46:36.164 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 01:46:36.164 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 01:46:36.164 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 01:46:36.180 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 01:46:36.180 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 01:46:36.180 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 01:46:36.182 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 01:46:36.182 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 01:46:36.182 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 01:46:36.182 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.28.22:6700) Recv POWERON CMD
2026-01-29 01:46:36.182 [INFO] ctrl_if_trx.py:109 (MS@172.18.28.22:6700) Starting transceiver...
2026-01-29 01:46:36.209 [DEBUG] fake_trx.py:297 (BTS@172.18.28.20:5700) Recv FAKE_RSSI cmd
2026-01-29 01:46:36.212 [DEBUG] fake_trx.py:278 (BTS@172.18.28.20:5700) Recv FAKE_TOA cmd
2026-01-29 01:46:36.219 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:46:36.223 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 01:46:36.224 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 01:46:36.224 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 01:46:36.224 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 01:46:36.641 [DEBUG] clck_gen.py:113 IND CLOCK 1938
2026-01-29 01:46:37.119 [DEBUG] clck_gen.py:113 IND CLOCK 2040
2026-01-29 01:46:37.597 [DEBUG] clck_gen.py:113 IND CLOCK 2142
2026-01-29 01:46:38.076 [DEBUG] clck_gen.py:113 IND CLOCK 2244
2026-01-29 01:46:38.553 [DEBUG] clck_gen.py:113 IND CLOCK 2346
2026-01-29 01:46:39.031 [DEBUG] clck_gen.py:113 IND CLOCK 2448
2026-01-29 01:46:39.510 [DEBUG] clck_gen.py:113 IND CLOCK 2550
2026-01-29 01:46:39.988 [DEBUG] clck_gen.py:113 IND CLOCK 2652
2026-01-29 01:46:40.466 [DEBUG] clck_gen.py:113 IND CLOCK 2754
2026-01-29 01:46:40.944 [DEBUG] clck_gen.py:113 IND CLOCK 2856
2026-01-29 01:46:41.422 [DEBUG] clck_gen.py:113 IND CLOCK 2958
2026-01-29 01:46:41.900 [DEBUG] clck_gen.py:113 IND CLOCK 3060
2026-01-29 01:46:42.378 [DEBUG] clck_gen.py:113 IND CLOCK 3162
2026-01-29 01:46:42.856 [DEBUG] clck_gen.py:113 IND CLOCK 3264
2026-01-29 01:46:43.334 [DEBUG] clck_gen.py:113 IND CLOCK 3366
2026-01-29 01:46:43.813 [DEBUG] clck_gen.py:113 IND CLOCK 3468
2026-01-29 01:46:44.226 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:46:44.229 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 01:46:44.230 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 01:46:44.230 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 01:46:44.240 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 01:46:44.240 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 01:46:44.240 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 01:46:44.240 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 01:46:44.241 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 01:46:44.241 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 01:46:44.241 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 01:46:44.241 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 01:46:44.241 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.28.20:5700) Recv POWEROFF cmd
2026-01-29 01:46:44.241 [INFO] ctrl_if_trx.py:117 (BTS@172.18.28.20:5700) Stopping transceiver...
2026-01-29 01:46:44.241 [INFO] transceiver.py:246 Stopping clock generator
2026-01-29 01:46:44.241 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=3562 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 01:46:44.241 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=3562 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 01:46:44.241 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=3562 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 01:46:44.241 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=3562 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 01:46:44.241 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=3562 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 01:46:44.241 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=3562 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 01:46:44.241 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=3562 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 01:46:44.241 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=3562 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 01:46:49.246 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.28.20:5700) Recv POWEROFF cmd
2026-01-29 01:46:49.246 [INFO] ctrl_if_trx.py:117 (BTS@172.18.28.20:5700) Stopping transceiver...
2026-01-29 01:46:49.246 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 01:46:49.246 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 01:46:49.246 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 01:46:49.246 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 01:46:49.255 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 01:46:49.257 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.28.20:5700) Recv SETFORMAT cmd
2026-01-29 01:46:49.257 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.28.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 01:46:49.258 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.28.20:5700) Recv SETFORMAT cmd
2026-01-29 01:46:49.258 [INFO] ctrl_if_trx.py:201 (BTS@172.18.28.20:5700) TRXD header version 1 -> 1
2026-01-29 01:46:49.263 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.28.20:5700/1) Recv RXTUNE cmd
2026-01-29 01:46:49.264 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.28.20:5700/1) Recv TXTUNE cmd
2026-01-29 01:46:49.264 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.28.20:5700/1) Recv SETFORMAT cmd
2026-01-29 01:46:49.265 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.28.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 01:46:49.265 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 01:46:49.265 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.28.20:5700/1) Recv NOMTXPOWER cmd
2026-01-29 01:46:49.266 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.28.20:5700/1) Recv SETFORMAT cmd
2026-01-29 01:46:49.266 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.28.20:5700/1) TRXD header version 1 -> 1
2026-01-29 01:46:49.267 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.28.20:5700/2) Recv RXTUNE cmd
2026-01-29 01:46:49.268 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.28.20:5700/2) Recv TXTUNE cmd
2026-01-29 01:46:49.268 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.28.20:5700/2) Recv SETFORMAT cmd
2026-01-29 01:46:49.268 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.28.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 01:46:49.268 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 01:46:49.268 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.28.20:5700/2) Recv NOMTXPOWER cmd
2026-01-29 01:46:49.268 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.28.20:5700/2) Recv SETFORMAT cmd
2026-01-29 01:46:49.268 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.28.20:5700/2) TRXD header version 1 -> 1
2026-01-29 01:46:49.270 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.28.20:5700/3) Recv RXTUNE cmd
2026-01-29 01:46:49.270 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.28.20:5700/3) Recv TXTUNE cmd
2026-01-29 01:46:49.270 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.28.20:5700/3) Recv SETFORMAT cmd
2026-01-29 01:46:49.270 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.28.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 01:46:49.270 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 01:46:49.271 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.28.20:5700/3) Recv NOMTXPOWER cmd
2026-01-29 01:46:49.271 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.28.20:5700/3) Recv SETFORMAT cmd
2026-01-29 01:46:49.271 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.28.20:5700/3) TRXD header version 1 -> 1
2026-01-29 01:46:49.273 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.28.20:5700) Recv RXTUNE cmd
2026-01-29 01:46:49.273 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETTSC
2026-01-29 01:46:49.273 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETTSC
2026-01-29 01:46:49.273 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETTSC
2026-01-29 01:46:49.273 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.28.20:5700) Recv TXTUNE cmd
2026-01-29 01:46:49.273 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETRXGAIN
2026-01-29 01:46:49.273 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETRXGAIN
2026-01-29 01:46:49.273 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETRXGAIN
2026-01-29 01:46:49.274 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETTSC
2026-01-29 01:46:49.274 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:46:49.274 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:46:49.274 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:46:49.274 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.28.20:5700) Recv NOMTXPOWER cmd
2026-01-29 01:46:49.274 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:46:49.274 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:46:49.274 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:46:49.274 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.28.20:5700) Recv POWERON CMD
2026-01-29 01:46:49.274 [INFO] ctrl_if_trx.py:109 (BTS@172.18.28.20:5700) Starting transceiver...
2026-01-29 01:46:49.274 [INFO] transceiver.py:243 Starting clock generator
2026-01-29 01:46:49.274 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-01-29 01:46:49.274 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:46:49.274 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:46:49.274 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:46:49.274 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETRXGAIN
2026-01-29 01:46:49.274 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:46:49.274 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:46:49.274 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 01:46:49.274 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:46:49.275 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:46:49.275 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:46:49.275 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 01:46:49.275 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:46:49.275 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:46:49.275 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:46:49.275 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 01:46:49.275 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:46:49.275 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:46:49.275 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:46:49.275 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 01:46:49.275 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:46:49.275 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:46:49.275 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:46:49.275 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 01:46:49.275 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:46:49.275 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 01:46:49.275 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 01:46:49.275 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 01:46:49.279 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-01-29 01:46:49.763 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-01-29 01:46:49.800 [DEBUG] fake_trx.py:278 (BTS@172.18.28.20:5700) Recv FAKE_TOA cmd
2026-01-29 01:46:49.803 [DEBUG] fake_trx.py:297 (BTS@172.18.28.20:5700) Recv FAKE_RSSI cmd
2026-01-29 01:46:49.804 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:46:49.805 [DEBUG] fake_trx.py:322 (BTS@172.18.28.20:5700) Recv FAKE_CI cmd
2026-01-29 01:46:49.831 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 01:46:49.831 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 01:46:49.832 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 01:46:49.837 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 01:46:49.837 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 01:46:49.837 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 01:46:49.837 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.28.22:6700) Recv POWERON CMD
2026-01-29 01:46:49.837 [INFO] ctrl_if_trx.py:109 (MS@172.18.28.22:6700) Starting transceiver...
2026-01-29 01:46:49.859 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:46:49.865 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 01:46:49.865 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 01:46:49.866 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 01:46:49.866 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 01:46:50.240 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-01-29 01:46:50.277 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 01:46:50.278 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 01:46:50.278 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 01:46:50.281 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 01:46:50.718 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-01-29 01:46:51.196 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-01-29 01:46:51.278 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 01:46:51.279 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 01:46:51.279 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 01:46:51.282 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 01:46:51.674 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-01-29 01:46:52.152 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-01-29 01:46:52.279 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 01:46:52.279 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 01:46:52.279 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 01:46:52.282 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 01:46:52.630 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-01-29 01:46:53.107 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-01-29 01:46:53.280 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 01:46:53.280 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 01:46:53.280 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 01:46:53.283 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 01:46:53.585 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-01-29 01:46:54.063 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-01-29 01:46:54.280 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 01:46:54.281 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 01:46:54.281 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 01:46:54.284 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 01:46:54.542 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-01-29 01:46:55.020 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-01-29 01:46:55.498 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-01-29 01:46:55.976 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-01-29 01:46:56.454 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-01-29 01:46:56.932 [DEBUG] clck_gen.py:113 IND CLOCK 1632
2026-01-29 01:46:57.410 [DEBUG] clck_gen.py:113 IND CLOCK 1734
2026-01-29 01:46:57.871 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:46:57.874 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 01:46:57.876 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 01:46:57.876 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 01:46:57.888 [DEBUG] clck_gen.py:113 IND CLOCK 1836
2026-01-29 01:46:57.891 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 01:46:57.891 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 01:46:57.891 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 01:46:57.891 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 01:46:57.892 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 01:46:57.892 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 01:46:57.892 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 01:46:57.892 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 01:46:57.892 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.28.20:5700) Recv POWEROFF cmd
2026-01-29 01:46:57.892 [INFO] ctrl_if_trx.py:117 (BTS@172.18.28.20:5700) Stopping transceiver...
2026-01-29 01:46:57.892 [INFO] transceiver.py:246 Stopping clock generator
2026-01-29 01:47:02.894 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.28.20:5700) Recv POWEROFF cmd
2026-01-29 01:47:02.895 [INFO] ctrl_if_trx.py:117 (BTS@172.18.28.20:5700) Stopping transceiver...
2026-01-29 01:47:02.896 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 01:47:02.897 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 01:47:02.897 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 01:47:02.897 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 01:47:02.906 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 01:47:02.908 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.28.20:5700) Recv SETFORMAT cmd
2026-01-29 01:47:02.908 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.28.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 01:47:02.909 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.28.20:5700) Recv SETFORMAT cmd
2026-01-29 01:47:02.909 [INFO] ctrl_if_trx.py:201 (BTS@172.18.28.20:5700) TRXD header version 1 -> 1
2026-01-29 01:47:02.914 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.28.20:5700/1) Recv RXTUNE cmd
2026-01-29 01:47:02.914 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.28.20:5700/1) Recv TXTUNE cmd
2026-01-29 01:47:02.915 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.28.20:5700/1) Recv SETFORMAT cmd
2026-01-29 01:47:02.915 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.28.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 01:47:02.915 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 01:47:02.916 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.28.20:5700/1) Recv NOMTXPOWER cmd
2026-01-29 01:47:02.916 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.28.20:5700/1) Recv SETFORMAT cmd
2026-01-29 01:47:02.916 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.28.20:5700/1) TRXD header version 1 -> 1
2026-01-29 01:47:02.918 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.28.20:5700/2) Recv RXTUNE cmd
2026-01-29 01:47:02.918 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.28.20:5700/2) Recv TXTUNE cmd
2026-01-29 01:47:02.918 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.28.20:5700/2) Recv SETFORMAT cmd
2026-01-29 01:47:02.919 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.28.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 01:47:02.919 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 01:47:02.919 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.28.20:5700/2) Recv NOMTXPOWER cmd
2026-01-29 01:47:02.919 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.28.20:5700/2) Recv SETFORMAT cmd
2026-01-29 01:47:02.919 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.28.20:5700/2) TRXD header version 1 -> 1
2026-01-29 01:47:02.921 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.28.20:5700/3) Recv RXTUNE cmd
2026-01-29 01:47:02.921 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.28.20:5700/3) Recv TXTUNE cmd
2026-01-29 01:47:02.921 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.28.20:5700/3) Recv SETFORMAT cmd
2026-01-29 01:47:02.921 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.28.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 01:47:02.921 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 01:47:02.922 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.28.20:5700/3) Recv NOMTXPOWER cmd
2026-01-29 01:47:02.922 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.28.20:5700/3) Recv SETFORMAT cmd
2026-01-29 01:47:02.922 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.28.20:5700/3) TRXD header version 1 -> 1
2026-01-29 01:47:02.925 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.28.20:5700) Recv RXTUNE cmd
2026-01-29 01:47:02.925 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETTSC
2026-01-29 01:47:02.925 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETTSC
2026-01-29 01:47:02.925 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETTSC
2026-01-29 01:47:02.925 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.28.20:5700) Recv TXTUNE cmd
2026-01-29 01:47:02.925 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETRXGAIN
2026-01-29 01:47:02.925 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETRXGAIN
2026-01-29 01:47:02.925 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETRXGAIN
2026-01-29 01:47:02.925 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETTSC
2026-01-29 01:47:02.925 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:47:02.925 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:47:02.925 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:47:02.925 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.28.20:5700) Recv NOMTXPOWER cmd
2026-01-29 01:47:02.925 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:47:02.925 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:47:02.925 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:47:02.925 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.28.20:5700) Recv POWERON CMD
2026-01-29 01:47:02.925 [INFO] ctrl_if_trx.py:109 (BTS@172.18.28.20:5700) Starting transceiver...
2026-01-29 01:47:02.925 [INFO] transceiver.py:243 Starting clock generator
2026-01-29 01:47:02.926 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-01-29 01:47:02.926 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:47:02.926 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:47:02.926 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:47:02.926 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETRXGAIN
2026-01-29 01:47:02.926 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:47:02.926 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:47:02.926 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 01:47:02.926 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:47:02.926 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:47:02.926 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:47:02.926 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 01:47:02.926 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:47:02.926 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:47:02.927 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:47:02.927 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 01:47:02.927 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:47:02.927 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:47:02.927 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:47:02.927 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 01:47:02.927 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:47:02.927 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:47:02.927 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:47:02.927 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 01:47:02.927 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:47:02.927 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 01:47:02.927 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 01:47:02.927 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 01:47:02.930 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-01-29 01:47:03.414 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-01-29 01:47:03.454 [DEBUG] fake_trx.py:278 (BTS@172.18.28.20:5700) Recv FAKE_TOA cmd
2026-01-29 01:47:03.454 [DEBUG] fake_trx.py:297 (BTS@172.18.28.20:5700) Recv FAKE_RSSI cmd
2026-01-29 01:47:03.455 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:47:03.455 [DEBUG] fake_trx.py:322 (BTS@172.18.28.20:5700) Recv FAKE_CI cmd
2026-01-29 01:47:03.475 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 01:47:03.475 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 01:47:03.476 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 01:47:03.480 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 01:47:03.481 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 01:47:03.481 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 01:47:03.481 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.28.22:6700) Recv POWERON CMD
2026-01-29 01:47:03.481 [INFO] ctrl_if_trx.py:109 (MS@172.18.28.22:6700) Starting transceiver...
2026-01-29 01:47:03.510 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:47:03.516 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 01:47:03.516 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 01:47:03.517 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 01:47:03.517 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 01:47:03.891 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-01-29 01:47:03.928 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 01:47:03.929 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 01:47:03.931 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 01:47:03.936 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 01:47:04.370 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-01-29 01:47:04.848 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-01-29 01:47:04.930 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 01:47:04.930 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 01:47:04.932 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 01:47:04.936 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 01:47:05.325 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-01-29 01:47:05.804 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-01-29 01:47:05.930 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 01:47:05.931 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 01:47:05.932 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 01:47:05.938 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 01:47:06.281 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-01-29 01:47:06.760 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-01-29 01:47:06.931 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 01:47:06.931 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 01:47:06.933 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 01:47:06.939 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 01:47:07.238 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-01-29 01:47:07.716 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-01-29 01:47:07.932 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 01:47:07.932 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 01:47:07.934 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 01:47:07.939 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 01:47:08.194 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-01-29 01:47:08.672 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-01-29 01:47:09.150 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-01-29 01:47:09.629 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-01-29 01:47:10.107 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-01-29 01:47:10.585 [DEBUG] clck_gen.py:113 IND CLOCK 1632
2026-01-29 01:47:11.063 [DEBUG] clck_gen.py:113 IND CLOCK 1734
2026-01-29 01:47:11.521 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:47:11.524 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 01:47:11.527 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 01:47:11.527 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 01:47:11.541 [DEBUG] clck_gen.py:113 IND CLOCK 1836
2026-01-29 01:47:11.545 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 01:47:11.546 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 01:47:11.546 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 01:47:11.546 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 01:47:11.552 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 01:47:11.552 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 01:47:11.552 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 01:47:11.552 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 01:47:11.553 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.28.20:5700) Recv POWEROFF cmd
2026-01-29 01:47:11.553 [INFO] ctrl_if_trx.py:117 (BTS@172.18.28.20:5700) Stopping transceiver...
2026-01-29 01:47:11.553 [INFO] transceiver.py:246 Stopping clock generator
2026-01-29 01:47:16.550 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.28.20:5700) Recv POWEROFF cmd
2026-01-29 01:47:16.550 [INFO] ctrl_if_trx.py:117 (BTS@172.18.28.20:5700) Stopping transceiver...
2026-01-29 01:47:16.552 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 01:47:16.552 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 01:47:16.553 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 01:47:16.553 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 01:47:16.556 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 01:47:16.557 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.28.20:5700) Recv SETFORMAT cmd
2026-01-29 01:47:16.557 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.28.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 01:47:16.557 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.28.20:5700) Recv SETFORMAT cmd
2026-01-29 01:47:16.557 [INFO] ctrl_if_trx.py:201 (BTS@172.18.28.20:5700) TRXD header version 1 -> 1
2026-01-29 01:47:16.559 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.28.20:5700/1) Recv RXTUNE cmd
2026-01-29 01:47:16.559 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.28.20:5700/1) Recv TXTUNE cmd
2026-01-29 01:47:16.559 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.28.20:5700/1) Recv SETFORMAT cmd
2026-01-29 01:47:16.560 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.28.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 01:47:16.560 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 01:47:16.560 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.28.20:5700/1) Recv NOMTXPOWER cmd
2026-01-29 01:47:16.560 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.28.20:5700/1) Recv SETFORMAT cmd
2026-01-29 01:47:16.560 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.28.20:5700/1) TRXD header version 1 -> 1
2026-01-29 01:47:16.561 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.28.20:5700/2) Recv RXTUNE cmd
2026-01-29 01:47:16.561 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.28.20:5700/2) Recv TXTUNE cmd
2026-01-29 01:47:16.561 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.28.20:5700/2) Recv SETFORMAT cmd
2026-01-29 01:47:16.561 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.28.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 01:47:16.561 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 01:47:16.561 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.28.20:5700/2) Recv NOMTXPOWER cmd
2026-01-29 01:47:16.561 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.28.20:5700/2) Recv SETFORMAT cmd
2026-01-29 01:47:16.561 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.28.20:5700/2) TRXD header version 1 -> 1
2026-01-29 01:47:16.563 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.28.20:5700/3) Recv RXTUNE cmd
2026-01-29 01:47:16.563 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.28.20:5700/3) Recv TXTUNE cmd
2026-01-29 01:47:16.563 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.28.20:5700/3) Recv SETFORMAT cmd
2026-01-29 01:47:16.563 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.28.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 01:47:16.563 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 01:47:16.563 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.28.20:5700/3) Recv NOMTXPOWER cmd
2026-01-29 01:47:16.563 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.28.20:5700/3) Recv SETFORMAT cmd
2026-01-29 01:47:16.563 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.28.20:5700/3) TRXD header version 1 -> 1
2026-01-29 01:47:16.565 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.28.20:5700) Recv RXTUNE cmd
2026-01-29 01:47:16.565 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETTSC
2026-01-29 01:47:16.565 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETTSC
2026-01-29 01:47:16.565 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETTSC
2026-01-29 01:47:16.565 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.28.20:5700) Recv TXTUNE cmd
2026-01-29 01:47:16.565 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETRXGAIN
2026-01-29 01:47:16.565 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETRXGAIN
2026-01-29 01:47:16.565 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETRXGAIN
2026-01-29 01:47:16.565 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETTSC
2026-01-29 01:47:16.565 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:47:16.565 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:47:16.565 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:47:16.565 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.28.20:5700) Recv NOMTXPOWER cmd
2026-01-29 01:47:16.565 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:47:16.565 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:47:16.565 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:47:16.565 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.28.20:5700) Recv POWERON CMD
2026-01-29 01:47:16.565 [INFO] ctrl_if_trx.py:109 (BTS@172.18.28.20:5700) Starting transceiver...
2026-01-29 01:47:16.565 [INFO] transceiver.py:243 Starting clock generator
2026-01-29 01:47:16.566 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-01-29 01:47:16.566 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:47:16.566 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:47:16.566 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:47:16.566 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETRXGAIN
2026-01-29 01:47:16.566 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:47:16.566 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 01:47:16.566 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:47:16.566 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:47:16.566 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:47:16.566 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 01:47:16.566 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:47:16.566 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:47:16.566 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:47:16.566 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 01:47:16.566 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:47:16.566 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:47:16.566 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:47:16.566 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 01:47:16.566 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:47:16.566 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:47:16.566 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:47:16.566 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 01:47:16.566 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:47:16.566 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:47:16.566 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 01:47:16.566 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 01:47:16.566 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 01:47:16.570 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-01-29 01:47:17.053 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-01-29 01:47:17.093 [DEBUG] fake_trx.py:278 (BTS@172.18.28.20:5700) Recv FAKE_TOA cmd
2026-01-29 01:47:17.095 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:47:17.096 [DEBUG] fake_trx.py:297 (BTS@172.18.28.20:5700) Recv FAKE_RSSI cmd
2026-01-29 01:47:17.100 [DEBUG] fake_trx.py:322 (BTS@172.18.28.20:5700) Recv FAKE_CI cmd
2026-01-29 01:47:17.122 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 01:47:17.122 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 01:47:17.123 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 01:47:17.129 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 01:47:17.130 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 01:47:17.130 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 01:47:17.130 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.28.22:6700) Recv POWERON CMD
2026-01-29 01:47:17.130 [INFO] ctrl_if_trx.py:109 (MS@172.18.28.22:6700) Starting transceiver...
2026-01-29 01:47:17.306 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 01:47:17.307 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 01:47:17.310 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 01:47:17.310 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 01:47:17.310 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 01:47:17.310 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 01:47:17.311 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 01:47:17.311 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 01:47:17.311 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 01:47:17.311 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 01:47:17.311 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.28.20:5700) Recv POWEROFF cmd
2026-01-29 01:47:17.311 [INFO] ctrl_if_trx.py:117 (BTS@172.18.28.20:5700) Stopping transceiver...
2026-01-29 01:47:17.311 [INFO] transceiver.py:246 Stopping clock generator
2026-01-29 01:47:17.311 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=159 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 01:47:17.311 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=159 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 01:47:17.311 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=159 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 01:47:17.311 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=159 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 01:47:17.311 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=159 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 01:47:17.311 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=159 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 01:47:22.313 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.28.20:5700) Recv POWEROFF cmd
2026-01-29 01:47:22.313 [INFO] ctrl_if_trx.py:117 (BTS@172.18.28.20:5700) Stopping transceiver...
2026-01-29 01:47:22.315 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 01:47:22.316 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 01:47:22.317 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 01:47:22.318 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 01:47:22.326 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 01:47:22.327 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.28.20:5700) Recv SETFORMAT cmd
2026-01-29 01:47:22.327 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.28.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 01:47:22.328 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.28.20:5700) Recv SETFORMAT cmd
2026-01-29 01:47:22.328 [INFO] ctrl_if_trx.py:201 (BTS@172.18.28.20:5700) TRXD header version 1 -> 1
2026-01-29 01:47:22.332 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.28.20:5700/1) Recv RXTUNE cmd
2026-01-29 01:47:22.333 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.28.20:5700/1) Recv TXTUNE cmd
2026-01-29 01:47:22.333 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.28.20:5700/1) Recv SETFORMAT cmd
2026-01-29 01:47:22.333 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.28.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 01:47:22.334 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 01:47:22.334 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.28.20:5700/1) Recv NOMTXPOWER cmd
2026-01-29 01:47:22.334 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.28.20:5700/1) Recv SETFORMAT cmd
2026-01-29 01:47:22.334 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.28.20:5700/1) TRXD header version 1 -> 1
2026-01-29 01:47:22.336 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.28.20:5700/2) Recv RXTUNE cmd
2026-01-29 01:47:22.336 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.28.20:5700/2) Recv TXTUNE cmd
2026-01-29 01:47:22.337 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.28.20:5700/2) Recv SETFORMAT cmd
2026-01-29 01:47:22.337 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.28.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 01:47:22.337 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 01:47:22.337 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.28.20:5700/2) Recv NOMTXPOWER cmd
2026-01-29 01:47:22.337 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.28.20:5700/2) Recv SETFORMAT cmd
2026-01-29 01:47:22.337 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.28.20:5700/2) TRXD header version 1 -> 1
2026-01-29 01:47:22.338 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.28.20:5700/3) Recv RXTUNE cmd
2026-01-29 01:47:22.339 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.28.20:5700/3) Recv TXTUNE cmd
2026-01-29 01:47:22.339 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.28.20:5700/3) Recv SETFORMAT cmd
2026-01-29 01:47:22.339 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.28.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 01:47:22.339 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 01:47:22.339 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.28.20:5700/3) Recv NOMTXPOWER cmd
2026-01-29 01:47:22.339 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.28.20:5700/3) Recv SETFORMAT cmd
2026-01-29 01:47:22.339 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.28.20:5700/3) TRXD header version 1 -> 1
2026-01-29 01:47:22.342 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.28.20:5700) Recv RXTUNE cmd
2026-01-29 01:47:22.342 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETTSC
2026-01-29 01:47:22.342 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETTSC
2026-01-29 01:47:22.342 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETTSC
2026-01-29 01:47:22.342 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.28.20:5700) Recv TXTUNE cmd
2026-01-29 01:47:22.342 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETRXGAIN
2026-01-29 01:47:22.342 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETRXGAIN
2026-01-29 01:47:22.342 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETTSC
2026-01-29 01:47:22.342 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:47:22.342 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETRXGAIN
2026-01-29 01:47:22.342 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.28.20:5700) Recv NOMTXPOWER cmd
2026-01-29 01:47:22.342 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:47:22.342 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:47:22.342 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:47:22.342 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.28.20:5700) Recv POWERON CMD
2026-01-29 01:47:22.342 [INFO] ctrl_if_trx.py:109 (BTS@172.18.28.20:5700) Starting transceiver...
2026-01-29 01:47:22.342 [INFO] transceiver.py:243 Starting clock generator
2026-01-29 01:47:22.342 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-01-29 01:47:22.342 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:47:22.343 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:47:22.343 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:47:22.343 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETRXGAIN
2026-01-29 01:47:22.343 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:47:22.343 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:47:22.343 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:47:22.343 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 01:47:22.343 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:47:22.343 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:47:22.343 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:47:22.343 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 01:47:22.343 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:47:22.343 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:47:22.343 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:47:22.343 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 01:47:22.343 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:47:22.343 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:47:22.343 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:47:22.343 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 01:47:22.343 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:47:22.343 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:47:22.343 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 01:47:22.343 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:47:22.343 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 01:47:22.344 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:47:22.344 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 01:47:22.344 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:47:22.344 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 01:47:22.347 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-01-29 01:47:22.831 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-01-29 01:47:22.873 [DEBUG] fake_trx.py:278 (BTS@172.18.28.20:5700) Recv FAKE_TOA cmd
2026-01-29 01:47:22.875 [DEBUG] fake_trx.py:297 (BTS@172.18.28.20:5700) Recv FAKE_RSSI cmd
2026-01-29 01:47:22.876 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:47:22.877 [DEBUG] fake_trx.py:322 (BTS@172.18.28.20:5700) Recv FAKE_CI cmd
2026-01-29 01:47:22.906 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 01:47:22.906 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 01:47:22.906 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 01:47:22.916 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 01:47:22.917 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 01:47:22.917 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 01:47:22.917 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.28.22:6700) Recv POWERON CMD
2026-01-29 01:47:22.917 [INFO] ctrl_if_trx.py:109 (MS@172.18.28.22:6700) Starting transceiver...
2026-01-29 01:47:23.309 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-01-29 01:47:23.345 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 01:47:23.346 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 01:47:23.346 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 01:47:23.350 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 01:47:23.786 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-01-29 01:47:24.263 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-01-29 01:47:24.345 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 01:47:24.347 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 01:47:24.347 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 01:47:24.351 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 01:47:24.741 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-01-29 01:47:25.219 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-01-29 01:47:25.346 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 01:47:25.347 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 01:47:25.348 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 01:47:25.351 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 01:47:25.696 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-01-29 01:47:26.173 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-01-29 01:47:26.347 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 01:47:26.348 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 01:47:26.349 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 01:47:26.352 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 01:47:26.651 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-01-29 01:47:27.128 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-01-29 01:47:27.348 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 01:47:27.349 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 01:47:27.350 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 01:47:27.353 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 01:47:27.386 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 01:47:27.386 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 01:47:27.386 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 01:47:27.386 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 01:47:27.387 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 01:47:27.387 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 01:47:27.387 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 01:47:27.387 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.28.20:5700) Recv POWEROFF cmd
2026-01-29 01:47:27.387 [INFO] ctrl_if_trx.py:117 (BTS@172.18.28.20:5700) Stopping transceiver...
2026-01-29 01:47:27.387 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 01:47:27.387 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=1078 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 01:47:27.387 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=1078 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 01:47:27.387 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=1078 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 01:47:27.387 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=1078 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 01:47:27.387 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=1078 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 01:47:27.387 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=1078 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 01:47:27.387 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=1078 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 01:47:27.609 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-01-29 01:47:28.093 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-01-29 01:47:28.579 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-01-29 01:47:29.066 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-01-29 01:47:29.552 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-01-29 01:47:30.039 [DEBUG] clck_gen.py:113 IND CLOCK 1632
2026-01-29 01:47:30.525 [DEBUG] clck_gen.py:113 IND CLOCK 1734
2026-01-29 01:47:31.012 [DEBUG] clck_gen.py:113 IND CLOCK 1836
2026-01-29 01:47:31.498 [DEBUG] clck_gen.py:113 IND CLOCK 1938
2026-01-29 01:47:31.984 [DEBUG] clck_gen.py:113 IND CLOCK 2040
2026-01-29 01:47:32.390 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.28.20:5700) Recv POWEROFF cmd
2026-01-29 01:47:32.406 [INFO] ctrl_if_trx.py:117 (BTS@172.18.28.20:5700) Stopping transceiver...
2026-01-29 01:47:32.407 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 01:47:32.407 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 01:47:32.407 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 01:47:32.407 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 01:47:32.408 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 01:47:32.408 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 01:47:32.408 [INFO] transceiver.py:246 Stopping clock generator
2026-01-29 01:47:32.410 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 01:47:32.411 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.28.20:5700) Recv SETFORMAT cmd
2026-01-29 01:47:32.412 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.28.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 01:47:32.412 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.28.20:5700) Recv SETFORMAT cmd
2026-01-29 01:47:32.412 [INFO] ctrl_if_trx.py:201 (BTS@172.18.28.20:5700) TRXD header version 1 -> 1
2026-01-29 01:47:32.413 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.28.20:5700/1) Recv RXTUNE cmd
2026-01-29 01:47:32.414 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.28.20:5700/1) Recv TXTUNE cmd
2026-01-29 01:47:32.414 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.28.20:5700/1) Recv SETFORMAT cmd
2026-01-29 01:47:32.414 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.28.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 01:47:32.414 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 01:47:32.414 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.28.20:5700/1) Recv NOMTXPOWER cmd
2026-01-29 01:47:32.414 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.28.20:5700/1) Recv SETFORMAT cmd
2026-01-29 01:47:32.414 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.28.20:5700/1) TRXD header version 1 -> 1
2026-01-29 01:47:32.416 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.28.20:5700/2) Recv RXTUNE cmd
2026-01-29 01:47:32.416 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.28.20:5700/2) Recv TXTUNE cmd
2026-01-29 01:47:32.416 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.28.20:5700/2) Recv SETFORMAT cmd
2026-01-29 01:47:32.416 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.28.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 01:47:32.416 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 01:47:32.416 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.28.20:5700/2) Recv NOMTXPOWER cmd
2026-01-29 01:47:32.416 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.28.20:5700/2) Recv SETFORMAT cmd
2026-01-29 01:47:32.416 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.28.20:5700/2) TRXD header version 1 -> 1
2026-01-29 01:47:32.417 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.28.20:5700/3) Recv RXTUNE cmd
2026-01-29 01:47:32.417 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.28.20:5700/3) Recv TXTUNE cmd
2026-01-29 01:47:32.417 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.28.20:5700/3) Recv SETFORMAT cmd
2026-01-29 01:47:32.417 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.28.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 01:47:32.417 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 01:47:32.418 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.28.20:5700/3) Recv NOMTXPOWER cmd
2026-01-29 01:47:32.418 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.28.20:5700/3) Recv SETFORMAT cmd
2026-01-29 01:47:32.418 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.28.20:5700/3) TRXD header version 1 -> 1
2026-01-29 01:47:32.420 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.28.20:5700) Recv RXTUNE cmd
2026-01-29 01:47:32.420 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETTSC
2026-01-29 01:47:32.420 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETTSC
2026-01-29 01:47:32.420 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETTSC
2026-01-29 01:47:32.420 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.28.20:5700) Recv TXTUNE cmd
2026-01-29 01:47:32.420 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETRXGAIN
2026-01-29 01:47:32.420 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETRXGAIN
2026-01-29 01:47:32.420 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETRXGAIN
2026-01-29 01:47:32.420 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETTSC
2026-01-29 01:47:32.420 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:47:32.420 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:47:32.420 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:47:32.420 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.28.20:5700) Recv NOMTXPOWER cmd
2026-01-29 01:47:32.420 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:47:32.421 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:47:32.421 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:47:32.421 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.28.20:5700) Recv POWERON CMD
2026-01-29 01:47:32.421 [INFO] ctrl_if_trx.py:109 (BTS@172.18.28.20:5700) Starting transceiver...
2026-01-29 01:47:32.421 [INFO] transceiver.py:243 Starting clock generator
2026-01-29 01:47:32.421 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-01-29 01:47:32.421 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:47:32.421 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:47:32.421 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:47:32.421 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETRXGAIN
2026-01-29 01:47:32.421 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:47:32.421 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:47:32.421 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:47:32.421 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 01:47:32.421 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:47:32.421 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:47:32.421 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:47:32.421 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 01:47:32.421 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:47:32.421 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:47:32.421 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:47:32.422 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 01:47:32.422 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:47:32.422 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:47:32.422 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 01:47:32.422 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:47:32.422 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:47:32.422 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 01:47:32.422 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 01:47:32.422 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:47:32.422 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 01:47:32.422 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:47:32.422 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 01:47:32.422 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 01:47:32.422 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 01:47:32.422 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 01:47:32.422 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 01:47:32.422 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.28.20:5700) Recv POWEROFF cmd
2026-01-29 01:47:32.422 [INFO] ctrl_if_trx.py:117 (BTS@172.18.28.20:5700) Stopping transceiver...
2026-01-29 01:47:32.422 [INFO] transceiver.py:246 Stopping clock generator
2026-01-29 01:47:37.425 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.28.20:5700) Recv POWEROFF cmd
2026-01-29 01:47:37.425 [INFO] ctrl_if_trx.py:117 (BTS@172.18.28.20:5700) Stopping transceiver...
2026-01-29 01:47:37.427 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 01:47:37.428 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 01:47:37.428 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 01:47:37.428 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 01:47:37.431 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 01:47:37.431 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.28.20:5700) Recv SETFORMAT cmd
2026-01-29 01:47:37.431 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.28.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 01:47:37.431 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.28.20:5700) Recv SETFORMAT cmd
2026-01-29 01:47:37.431 [INFO] ctrl_if_trx.py:201 (BTS@172.18.28.20:5700) TRXD header version 1 -> 1
2026-01-29 01:47:37.432 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.28.20:5700/1) Recv RXTUNE cmd
2026-01-29 01:47:37.432 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.28.20:5700/1) Recv TXTUNE cmd
2026-01-29 01:47:37.432 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.28.20:5700/1) Recv SETFORMAT cmd
2026-01-29 01:47:37.432 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.28.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 01:47:37.432 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 01:47:37.433 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.28.20:5700/1) Recv NOMTXPOWER cmd
2026-01-29 01:47:37.433 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.28.20:5700/1) Recv SETFORMAT cmd
2026-01-29 01:47:37.433 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.28.20:5700/1) TRXD header version 1 -> 1
2026-01-29 01:47:37.433 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.28.20:5700/2) Recv RXTUNE cmd
2026-01-29 01:47:37.433 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.28.20:5700/2) Recv TXTUNE cmd
2026-01-29 01:47:37.433 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.28.20:5700/2) Recv SETFORMAT cmd
2026-01-29 01:47:37.433 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.28.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 01:47:37.433 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 01:47:37.433 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.28.20:5700/2) Recv NOMTXPOWER cmd
2026-01-29 01:47:37.433 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.28.20:5700/2) Recv SETFORMAT cmd
2026-01-29 01:47:37.433 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.28.20:5700/2) TRXD header version 1 -> 1
2026-01-29 01:47:37.434 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.28.20:5700/3) Recv RXTUNE cmd
2026-01-29 01:47:37.434 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.28.20:5700/3) Recv TXTUNE cmd
2026-01-29 01:47:37.434 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.28.20:5700/3) Recv SETFORMAT cmd
2026-01-29 01:47:37.434 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.28.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 01:47:37.434 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 01:47:37.434 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.28.20:5700/3) Recv NOMTXPOWER cmd
2026-01-29 01:47:37.434 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.28.20:5700/3) Recv SETFORMAT cmd
2026-01-29 01:47:37.434 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.28.20:5700/3) TRXD header version 1 -> 1
2026-01-29 01:47:37.436 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.28.20:5700) Recv RXTUNE cmd
2026-01-29 01:47:37.436 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETTSC
2026-01-29 01:47:37.436 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETTSC
2026-01-29 01:47:37.436 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETTSC
2026-01-29 01:47:37.436 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.28.20:5700) Recv TXTUNE cmd
2026-01-29 01:47:37.436 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETRXGAIN
2026-01-29 01:47:37.436 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETRXGAIN
2026-01-29 01:47:37.436 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETRXGAIN
2026-01-29 01:47:37.436 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETTSC
2026-01-29 01:47:37.436 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:47:37.436 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:47:37.436 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.28.20:5700) Recv NOMTXPOWER cmd
2026-01-29 01:47:37.436 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:47:37.436 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:47:37.436 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:47:37.436 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.28.20:5700) Recv POWERON CMD
2026-01-29 01:47:37.436 [INFO] ctrl_if_trx.py:109 (BTS@172.18.28.20:5700) Starting transceiver...
2026-01-29 01:47:37.436 [INFO] transceiver.py:243 Starting clock generator
2026-01-29 01:47:37.436 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-01-29 01:47:37.436 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:47:37.436 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:47:37.436 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:47:37.436 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETRXGAIN
2026-01-29 01:47:37.436 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:47:37.436 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:47:37.436 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:47:37.436 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 01:47:37.436 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:47:37.436 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:47:37.436 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:47:37.436 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 01:47:37.436 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:47:37.437 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:47:37.437 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:47:37.437 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 01:47:37.437 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:47:37.437 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:47:37.437 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:47:37.437 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 01:47:37.437 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:47:37.437 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:47:37.437 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:47:37.437 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 01:47:37.437 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:47:37.437 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 01:47:37.437 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 01:47:37.437 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 01:47:37.441 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-01-29 01:47:37.922 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-01-29 01:47:37.963 [DEBUG] fake_trx.py:278 (BTS@172.18.28.20:5700) Recv FAKE_TOA cmd
2026-01-29 01:47:37.965 [DEBUG] fake_trx.py:297 (BTS@172.18.28.20:5700) Recv FAKE_RSSI cmd
2026-01-29 01:47:37.967 [DEBUG] fake_trx.py:322 (BTS@172.18.28.20:5700) Recv FAKE_CI cmd
2026-01-29 01:47:37.967 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:47:37.992 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 01:47:37.992 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 01:47:37.993 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 01:47:37.998 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 01:47:37.998 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 01:47:37.998 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 01:47:37.999 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.28.22:6700) Recv POWERON CMD
2026-01-29 01:47:37.999 [INFO] ctrl_if_trx.py:109 (MS@172.18.28.22:6700) Starting transceiver...
2026-01-29 01:47:38.399 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-01-29 01:47:38.438 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 01:47:38.439 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 01:47:38.440 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 01:47:38.441 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 01:47:38.876 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-01-29 01:47:39.354 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-01-29 01:47:39.439 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 01:47:39.439 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 01:47:39.441 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 01:47:39.442 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 01:47:39.832 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-01-29 01:47:40.309 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-01-29 01:47:40.439 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 01:47:40.440 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 01:47:40.442 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 01:47:40.443 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 01:47:40.787 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-01-29 01:47:41.264 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-01-29 01:47:41.440 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 01:47:41.441 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 01:47:41.443 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 01:47:41.444 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 01:47:41.742 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-01-29 01:47:42.220 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-01-29 01:47:42.441 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 01:47:42.442 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 01:47:42.444 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 01:47:42.446 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 01:47:42.697 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-01-29 01:47:43.175 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-01-29 01:47:43.475 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 01:47:43.654 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-01-29 01:47:44.131 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-01-29 01:47:44.476 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 01:47:44.609 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-01-29 01:47:45.086 [DEBUG] clck_gen.py:113 IND CLOCK 1632
2026-01-29 01:47:45.478 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 01:47:45.564 [DEBUG] clck_gen.py:113 IND CLOCK 1734
2026-01-29 01:47:46.042 [DEBUG] clck_gen.py:113 IND CLOCK 1836
2026-01-29 01:47:46.478 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 01:47:46.519 [DEBUG] clck_gen.py:113 IND CLOCK 1938
2026-01-29 01:47:46.997 [DEBUG] clck_gen.py:113 IND CLOCK 2040
2026-01-29 01:47:47.475 [DEBUG] clck_gen.py:113 IND CLOCK 2142
2026-01-29 01:47:47.479 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 01:47:47.480 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 01:47:47.953 [DEBUG] clck_gen.py:113 IND CLOCK 2244
2026-01-29 01:47:48.430 [DEBUG] clck_gen.py:113 IND CLOCK 2346
2026-01-29 01:47:48.908 [DEBUG] clck_gen.py:113 IND CLOCK 2448
2026-01-29 01:47:49.388 [DEBUG] clck_gen.py:113 IND CLOCK 2550
2026-01-29 01:47:49.866 [DEBUG] clck_gen.py:113 IND CLOCK 2652
2026-01-29 01:47:50.345 [DEBUG] clck_gen.py:113 IND CLOCK 2754
2026-01-29 01:47:50.539 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 01:47:50.824 [DEBUG] clck_gen.py:113 IND CLOCK 2856
2026-01-29 01:47:51.302 [DEBUG] clck_gen.py:113 IND CLOCK 2958
2026-01-29 01:47:51.539 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 01:47:51.780 [DEBUG] clck_gen.py:113 IND CLOCK 3060
2026-01-29 01:47:52.258 [DEBUG] clck_gen.py:113 IND CLOCK 3162
2026-01-29 01:47:52.540 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 01:47:52.736 [DEBUG] clck_gen.py:113 IND CLOCK 3264
2026-01-29 01:47:53.214 [DEBUG] clck_gen.py:113 IND CLOCK 3366
2026-01-29 01:47:53.540 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 01:47:53.691 [DEBUG] clck_gen.py:113 IND CLOCK 3468
2026-01-29 01:47:54.169 [DEBUG] clck_gen.py:113 IND CLOCK 3570
2026-01-29 01:47:54.542 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 01:47:54.647 [DEBUG] clck_gen.py:113 IND CLOCK 3672
2026-01-29 01:47:55.125 [DEBUG] clck_gen.py:113 IND CLOCK 3774
2026-01-29 01:47:55.543 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 01:47:55.602 [DEBUG] clck_gen.py:113 IND CLOCK 3876
2026-01-29 01:47:56.080 [DEBUG] clck_gen.py:113 IND CLOCK 3978
2026-01-29 01:47:56.558 [DEBUG] clck_gen.py:113 IND CLOCK 4080
2026-01-29 01:47:57.036 [DEBUG] clck_gen.py:113 IND CLOCK 4182
2026-01-29 01:47:57.514 [DEBUG] clck_gen.py:113 IND CLOCK 4284
2026-01-29 01:47:57.619 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 01:47:57.619 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 01:47:57.625 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 01:47:57.625 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 01:47:57.625 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 01:47:57.625 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 01:47:57.626 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 01:47:57.626 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 01:47:57.626 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 01:47:57.626 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 01:47:57.626 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.28.20:5700) Recv POWEROFF cmd
2026-01-29 01:47:57.626 [INFO] ctrl_if_trx.py:117 (BTS@172.18.28.20:5700) Stopping transceiver...
2026-01-29 01:47:57.626 [INFO] transceiver.py:246 Stopping clock generator
2026-01-29 01:47:57.626 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=4310 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 01:47:57.626 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=4310 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 01:47:57.626 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=4310 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 01:47:57.626 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=4310 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 01:47:57.626 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=4310 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 01:47:57.626 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=4310 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 01:47:57.626 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=4310 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 01:47:57.626 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=4310 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 01:48:02.629 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.28.20:5700) Recv POWEROFF cmd
2026-01-29 01:48:02.629 [INFO] ctrl_if_trx.py:117 (BTS@172.18.28.20:5700) Stopping transceiver...
2026-01-29 01:48:02.631 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 01:48:02.632 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 01:48:02.632 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 01:48:02.632 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 01:48:02.642 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 01:48:02.644 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.28.20:5700) Recv SETFORMAT cmd
2026-01-29 01:48:02.644 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.28.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 01:48:02.645 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.28.20:5700) Recv SETFORMAT cmd
2026-01-29 01:48:02.645 [INFO] ctrl_if_trx.py:201 (BTS@172.18.28.20:5700) TRXD header version 1 -> 1
2026-01-29 01:48:02.652 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.28.20:5700/1) Recv RXTUNE cmd
2026-01-29 01:48:02.652 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.28.20:5700/1) Recv TXTUNE cmd
2026-01-29 01:48:02.653 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.28.20:5700/1) Recv SETFORMAT cmd
2026-01-29 01:48:02.653 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.28.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 01:48:02.653 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 01:48:02.654 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.28.20:5700/1) Recv NOMTXPOWER cmd
2026-01-29 01:48:02.654 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.28.20:5700/1) Recv SETFORMAT cmd
2026-01-29 01:48:02.654 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.28.20:5700/1) TRXD header version 1 -> 1
2026-01-29 01:48:02.656 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.28.20:5700/2) Recv RXTUNE cmd
2026-01-29 01:48:02.656 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.28.20:5700/2) Recv TXTUNE cmd
2026-01-29 01:48:02.656 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.28.20:5700/2) Recv SETFORMAT cmd
2026-01-29 01:48:02.656 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.28.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 01:48:02.657 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 01:48:02.657 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.28.20:5700/2) Recv NOMTXPOWER cmd
2026-01-29 01:48:02.657 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.28.20:5700/2) Recv SETFORMAT cmd
2026-01-29 01:48:02.657 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.28.20:5700/2) TRXD header version 1 -> 1
2026-01-29 01:48:02.659 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.28.20:5700/3) Recv RXTUNE cmd
2026-01-29 01:48:02.659 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.28.20:5700/3) Recv TXTUNE cmd
2026-01-29 01:48:02.659 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.28.20:5700/3) Recv SETFORMAT cmd
2026-01-29 01:48:02.659 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.28.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 01:48:02.659 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 01:48:02.659 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.28.20:5700/3) Recv NOMTXPOWER cmd
2026-01-29 01:48:02.659 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.28.20:5700/3) Recv SETFORMAT cmd
2026-01-29 01:48:02.659 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.28.20:5700/3) TRXD header version 1 -> 1
2026-01-29 01:48:02.662 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.28.20:5700) Recv RXTUNE cmd
2026-01-29 01:48:02.662 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETTSC
2026-01-29 01:48:02.662 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETTSC
2026-01-29 01:48:02.663 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETTSC
2026-01-29 01:48:02.663 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.28.20:5700) Recv TXTUNE cmd
2026-01-29 01:48:02.663 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETRXGAIN
2026-01-29 01:48:02.663 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETRXGAIN
2026-01-29 01:48:02.663 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETRXGAIN
2026-01-29 01:48:02.663 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETTSC
2026-01-29 01:48:02.663 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:48:02.663 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:48:02.663 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:48:02.663 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.28.20:5700) Recv NOMTXPOWER cmd
2026-01-29 01:48:02.663 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:48:02.663 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:48:02.663 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:48:02.663 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.28.20:5700) Recv POWERON CMD
2026-01-29 01:48:02.663 [INFO] ctrl_if_trx.py:109 (BTS@172.18.28.20:5700) Starting transceiver...
2026-01-29 01:48:02.663 [INFO] transceiver.py:243 Starting clock generator
2026-01-29 01:48:02.663 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-01-29 01:48:02.664 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:48:02.664 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:48:02.664 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:48:02.664 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETRXGAIN
2026-01-29 01:48:02.664 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:48:02.664 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:48:02.664 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:48:02.664 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 01:48:02.664 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:48:02.665 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:48:02.665 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:48:02.665 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 01:48:02.665 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:48:02.665 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:48:02.665 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:48:02.665 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 01:48:02.665 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:48:02.665 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:48:02.665 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:48:02.665 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 01:48:02.665 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:48:02.666 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:48:02.666 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:48:02.666 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 01:48:02.666 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 01:48:02.666 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 01:48:02.666 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 01:48:02.668 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-01-29 01:48:03.151 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-01-29 01:48:03.193 [DEBUG] fake_trx.py:278 (BTS@172.18.28.20:5700) Recv FAKE_TOA cmd
2026-01-29 01:48:03.195 [DEBUG] fake_trx.py:297 (BTS@172.18.28.20:5700) Recv FAKE_RSSI cmd
2026-01-29 01:48:03.197 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:48:03.198 [DEBUG] fake_trx.py:322 (BTS@172.18.28.20:5700) Recv FAKE_CI cmd
2026-01-29 01:48:03.222 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 01:48:03.222 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 01:48:03.223 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 01:48:03.228 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 01:48:03.229 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 01:48:03.229 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 01:48:03.229 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.28.22:6700) Recv POWERON CMD
2026-01-29 01:48:03.229 [INFO] ctrl_if_trx.py:109 (MS@172.18.28.22:6700) Starting transceiver...
2026-01-29 01:48:03.244 [DEBUG] fake_trx.py:297 (BTS@172.18.28.20:5700) Recv FAKE_RSSI cmd
2026-01-29 01:48:03.247 [DEBUG] fake_trx.py:278 (BTS@172.18.28.20:5700) Recv FAKE_TOA cmd
2026-01-29 01:48:03.256 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD NOHANDOVER
2026-01-29 01:48:03.262 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 01:48:03.262 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 01:48:03.262 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 01:48:03.263 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 01:48:03.629 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-01-29 01:48:03.667 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 01:48:03.668 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 01:48:03.670 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 01:48:03.672 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 01:48:04.064 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD NOHANDOVER
2026-01-29 01:48:04.067 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 01:48:04.067 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 01:48:04.067 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 01:48:04.078 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 01:48:04.078 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 01:48:04.078 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 01:48:04.078 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 01:48:04.079 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 01:48:04.079 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 01:48:04.079 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 01:48:04.079 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.28.20:5700) Recv POWEROFF cmd
2026-01-29 01:48:04.080 [INFO] ctrl_if_trx.py:117 (BTS@172.18.28.20:5700) Stopping transceiver...
2026-01-29 01:48:04.080 [INFO] transceiver.py:246 Stopping clock generator
2026-01-29 01:48:04.080 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 01:48:09.079 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.28.20:5700) Recv POWEROFF cmd
2026-01-29 01:48:09.079 [INFO] ctrl_if_trx.py:117 (BTS@172.18.28.20:5700) Stopping transceiver...
2026-01-29 01:48:09.080 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 01:48:09.082 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 01:48:09.083 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 01:48:09.086 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 01:48:09.100 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 01:48:09.102 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.28.20:5700) Recv SETFORMAT cmd
2026-01-29 01:48:09.102 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.28.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 01:48:09.103 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.28.20:5700) Recv SETFORMAT cmd
2026-01-29 01:48:09.103 [INFO] ctrl_if_trx.py:201 (BTS@172.18.28.20:5700) TRXD header version 1 -> 1
2026-01-29 01:48:09.107 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.28.20:5700/1) Recv RXTUNE cmd
2026-01-29 01:48:09.108 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.28.20:5700/1) Recv TXTUNE cmd
2026-01-29 01:48:09.108 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.28.20:5700/1) Recv SETFORMAT cmd
2026-01-29 01:48:09.109 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.28.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 01:48:09.109 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 01:48:09.109 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.28.20:5700/1) Recv NOMTXPOWER cmd
2026-01-29 01:48:09.110 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.28.20:5700/1) Recv SETFORMAT cmd
2026-01-29 01:48:09.110 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.28.20:5700/1) TRXD header version 1 -> 1
2026-01-29 01:48:09.111 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.28.20:5700/2) Recv RXTUNE cmd
2026-01-29 01:48:09.111 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.28.20:5700/2) Recv TXTUNE cmd
2026-01-29 01:48:09.111 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.28.20:5700/2) Recv SETFORMAT cmd
2026-01-29 01:48:09.112 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.28.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 01:48:09.112 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 01:48:09.112 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.28.20:5700/2) Recv NOMTXPOWER cmd
2026-01-29 01:48:09.112 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.28.20:5700/2) Recv SETFORMAT cmd
2026-01-29 01:48:09.112 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.28.20:5700/2) TRXD header version 1 -> 1
2026-01-29 01:48:09.113 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.28.20:5700/3) Recv RXTUNE cmd
2026-01-29 01:48:09.113 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.28.20:5700/3) Recv TXTUNE cmd
2026-01-29 01:48:09.113 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.28.20:5700/3) Recv SETFORMAT cmd
2026-01-29 01:48:09.113 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.28.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 01:48:09.114 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 01:48:09.114 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.28.20:5700/3) Recv NOMTXPOWER cmd
2026-01-29 01:48:09.114 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.28.20:5700/3) Recv SETFORMAT cmd
2026-01-29 01:48:09.114 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.28.20:5700/3) TRXD header version 1 -> 1
2026-01-29 01:48:09.116 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.28.20:5700) Recv RXTUNE cmd
2026-01-29 01:48:09.116 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETTSC
2026-01-29 01:48:09.116 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETTSC
2026-01-29 01:48:09.116 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETTSC
2026-01-29 01:48:09.116 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.28.20:5700) Recv TXTUNE cmd
2026-01-29 01:48:09.116 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETRXGAIN
2026-01-29 01:48:09.116 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETRXGAIN
2026-01-29 01:48:09.117 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETRXGAIN
2026-01-29 01:48:09.117 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETTSC
2026-01-29 01:48:09.117 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:48:09.117 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:48:09.117 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.28.20:5700) Recv NOMTXPOWER cmd
2026-01-29 01:48:09.117 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:48:09.117 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:48:09.117 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:48:09.117 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.28.20:5700) Recv POWERON CMD
2026-01-29 01:48:09.117 [INFO] ctrl_if_trx.py:109 (BTS@172.18.28.20:5700) Starting transceiver...
2026-01-29 01:48:09.117 [INFO] transceiver.py:243 Starting clock generator
2026-01-29 01:48:09.117 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-01-29 01:48:09.117 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:48:09.117 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:48:09.117 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:48:09.117 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETRXGAIN
2026-01-29 01:48:09.117 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:48:09.117 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:48:09.117 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:48:09.117 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 01:48:09.117 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:48:09.117 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:48:09.118 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:48:09.118 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 01:48:09.118 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:48:09.118 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:48:09.118 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:48:09.118 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 01:48:09.118 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:48:09.118 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:48:09.118 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:48:09.118 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 01:48:09.118 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:48:09.118 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:48:09.118 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:48:09.118 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 01:48:09.118 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:48:09.118 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 01:48:09.118 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 01:48:09.118 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 01:48:09.122 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-01-29 01:48:09.605 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-01-29 01:48:09.645 [DEBUG] fake_trx.py:278 (BTS@172.18.28.20:5700) Recv FAKE_TOA cmd
2026-01-29 01:48:09.647 [DEBUG] fake_trx.py:297 (BTS@172.18.28.20:5700) Recv FAKE_RSSI cmd
2026-01-29 01:48:09.648 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:48:09.649 [DEBUG] fake_trx.py:322 (BTS@172.18.28.20:5700) Recv FAKE_CI cmd
2026-01-29 01:48:09.667 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 01:48:09.667 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 01:48:09.668 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 01:48:09.673 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 01:48:09.673 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 01:48:09.674 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 01:48:09.674 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.28.22:6700) Recv POWERON CMD
2026-01-29 01:48:09.674 [INFO] ctrl_if_trx.py:109 (MS@172.18.28.22:6700) Starting transceiver...
2026-01-29 01:48:09.697 [DEBUG] fake_trx.py:297 (BTS@172.18.28.20:5700) Recv FAKE_RSSI cmd
2026-01-29 01:48:09.701 [DEBUG] fake_trx.py:278 (BTS@172.18.28.20:5700) Recv FAKE_TOA cmd
2026-01-29 01:48:09.708 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD NOHANDOVER
2026-01-29 01:48:09.712 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 01:48:09.712 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 01:48:09.713 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 01:48:09.713 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 01:48:10.078 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-01-29 01:48:10.120 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 01:48:10.120 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 01:48:10.120 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 01:48:10.122 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 01:48:10.511 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD NOHANDOVER
2026-01-29 01:48:10.514 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 01:48:10.514 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 01:48:10.514 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 01:48:10.526 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 01:48:10.526 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 01:48:10.526 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 01:48:10.526 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 01:48:10.528 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 01:48:10.528 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 01:48:10.528 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 01:48:10.528 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 01:48:10.528 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.28.20:5700) Recv POWEROFF cmd
2026-01-29 01:48:10.528 [INFO] ctrl_if_trx.py:117 (BTS@172.18.28.20:5700) Stopping transceiver...
2026-01-29 01:48:10.528 [INFO] transceiver.py:246 Stopping clock generator
2026-01-29 01:48:15.527 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.28.20:5700) Recv POWEROFF cmd
2026-01-29 01:48:15.528 [INFO] ctrl_if_trx.py:117 (BTS@172.18.28.20:5700) Stopping transceiver...
2026-01-29 01:48:15.529 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 01:48:15.530 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 01:48:15.531 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 01:48:15.531 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 01:48:15.538 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 01:48:15.539 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.28.20:5700) Recv SETFORMAT cmd
2026-01-29 01:48:15.539 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.28.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 01:48:15.539 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.28.20:5700) Recv SETFORMAT cmd
2026-01-29 01:48:15.539 [INFO] ctrl_if_trx.py:201 (BTS@172.18.28.20:5700) TRXD header version 1 -> 1
2026-01-29 01:48:15.542 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.28.20:5700/1) Recv RXTUNE cmd
2026-01-29 01:48:15.542 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.28.20:5700/1) Recv TXTUNE cmd
2026-01-29 01:48:15.542 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.28.20:5700/1) Recv SETFORMAT cmd
2026-01-29 01:48:15.543 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.28.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 01:48:15.543 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 01:48:15.543 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.28.20:5700/1) Recv NOMTXPOWER cmd
2026-01-29 01:48:15.544 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.28.20:5700/1) Recv SETFORMAT cmd
2026-01-29 01:48:15.544 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.28.20:5700/1) TRXD header version 1 -> 1
2026-01-29 01:48:15.545 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.28.20:5700/2) Recv RXTUNE cmd
2026-01-29 01:48:15.545 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.28.20:5700/2) Recv TXTUNE cmd
2026-01-29 01:48:15.545 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.28.20:5700/2) Recv SETFORMAT cmd
2026-01-29 01:48:15.545 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.28.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 01:48:15.545 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 01:48:15.545 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.28.20:5700/2) Recv NOMTXPOWER cmd
2026-01-29 01:48:15.546 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.28.20:5700/2) Recv SETFORMAT cmd
2026-01-29 01:48:15.546 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.28.20:5700/2) TRXD header version 1 -> 1
2026-01-29 01:48:15.547 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.28.20:5700/3) Recv RXTUNE cmd
2026-01-29 01:48:15.547 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.28.20:5700/3) Recv TXTUNE cmd
2026-01-29 01:48:15.547 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.28.20:5700/3) Recv SETFORMAT cmd
2026-01-29 01:48:15.547 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.28.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 01:48:15.547 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 01:48:15.547 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.28.20:5700/3) Recv NOMTXPOWER cmd
2026-01-29 01:48:15.547 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.28.20:5700/3) Recv SETFORMAT cmd
2026-01-29 01:48:15.547 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.28.20:5700/3) TRXD header version 1 -> 1
2026-01-29 01:48:15.550 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.28.20:5700) Recv RXTUNE cmd
2026-01-29 01:48:15.550 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETTSC
2026-01-29 01:48:15.550 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETTSC
2026-01-29 01:48:15.550 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETTSC
2026-01-29 01:48:15.550 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.28.20:5700) Recv TXTUNE cmd
2026-01-29 01:48:15.550 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETRXGAIN
2026-01-29 01:48:15.551 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETRXGAIN
2026-01-29 01:48:15.551 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETRXGAIN
2026-01-29 01:48:15.551 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETTSC
2026-01-29 01:48:15.551 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:48:15.551 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:48:15.551 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.28.20:5700) Recv NOMTXPOWER cmd
2026-01-29 01:48:15.551 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:48:15.551 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:48:15.551 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:48:15.551 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.28.20:5700) Recv POWERON CMD
2026-01-29 01:48:15.551 [INFO] ctrl_if_trx.py:109 (BTS@172.18.28.20:5700) Starting transceiver...
2026-01-29 01:48:15.551 [INFO] transceiver.py:243 Starting clock generator
2026-01-29 01:48:15.551 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-01-29 01:48:15.551 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:48:15.551 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:48:15.551 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:48:15.552 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETRXGAIN
2026-01-29 01:48:15.552 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:48:15.552 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:48:15.552 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:48:15.552 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 01:48:15.552 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:48:15.552 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:48:15.552 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:48:15.552 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 01:48:15.552 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:48:15.552 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:48:15.552 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:48:15.552 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 01:48:15.552 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:48:15.552 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:48:15.552 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:48:15.552 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 01:48:15.552 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:48:15.552 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:48:15.552 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 01:48:15.552 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:48:15.552 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:48:15.553 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 01:48:15.553 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 01:48:15.553 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 01:48:15.556 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-01-29 01:48:16.037 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-01-29 01:48:16.079 [DEBUG] fake_trx.py:278 (BTS@172.18.28.20:5700) Recv FAKE_TOA cmd
2026-01-29 01:48:16.081 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:48:16.082 [DEBUG] fake_trx.py:297 (BTS@172.18.28.20:5700) Recv FAKE_RSSI cmd
2026-01-29 01:48:16.085 [DEBUG] fake_trx.py:322 (BTS@172.18.28.20:5700) Recv FAKE_CI cmd
2026-01-29 01:48:16.105 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 01:48:16.106 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 01:48:16.106 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 01:48:16.111 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 01:48:16.111 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 01:48:16.111 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 01:48:16.112 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.28.22:6700) Recv POWERON CMD
2026-01-29 01:48:16.112 [INFO] ctrl_if_trx.py:109 (MS@172.18.28.22:6700) Starting transceiver...
2026-01-29 01:48:16.133 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:48:16.139 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 01:48:16.140 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 01:48:16.140 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 01:48:16.140 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 01:48:16.511 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-01-29 01:48:16.555 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 01:48:16.555 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 01:48:16.556 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 01:48:16.559 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 01:48:16.989 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-01-29 01:48:17.467 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-01-29 01:48:17.555 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 01:48:17.556 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 01:48:17.556 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 01:48:17.560 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 01:48:17.945 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-01-29 01:48:18.423 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-01-29 01:48:18.556 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 01:48:18.557 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 01:48:18.557 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 01:48:18.561 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 01:48:18.900 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-01-29 01:48:19.379 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-01-29 01:48:19.557 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 01:48:19.559 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 01:48:19.559 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 01:48:19.562 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 01:48:19.857 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-01-29 01:48:20.334 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-01-29 01:48:20.557 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 01:48:20.560 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 01:48:20.560 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 01:48:20.563 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 01:48:20.812 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-01-29 01:48:21.290 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-01-29 01:48:21.768 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-01-29 01:48:22.245 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-01-29 01:48:22.723 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-01-29 01:48:23.201 [DEBUG] clck_gen.py:113 IND CLOCK 1632
2026-01-29 01:48:23.678 [DEBUG] clck_gen.py:113 IND CLOCK 1734
2026-01-29 01:48:24.156 [DEBUG] clck_gen.py:113 IND CLOCK 1836
2026-01-29 01:48:24.634 [DEBUG] clck_gen.py:113 IND CLOCK 1938
2026-01-29 01:48:25.111 [DEBUG] clck_gen.py:113 IND CLOCK 2040
2026-01-29 01:48:25.589 [DEBUG] clck_gen.py:113 IND CLOCK 2142
2026-01-29 01:48:26.062 [DEBUG] clck_gen.py:113 IND CLOCK 2244
2026-01-29 01:48:26.540 [DEBUG] clck_gen.py:113 IND CLOCK 2346
2026-01-29 01:48:27.018 [DEBUG] clck_gen.py:113 IND CLOCK 2448
2026-01-29 01:48:27.495 [DEBUG] clck_gen.py:113 IND CLOCK 2550
2026-01-29 01:48:27.972 [DEBUG] clck_gen.py:113 IND CLOCK 2652
2026-01-29 01:48:28.450 [DEBUG] clck_gen.py:113 IND CLOCK 2754
2026-01-29 01:48:28.927 [DEBUG] clck_gen.py:113 IND CLOCK 2856
2026-01-29 01:48:29.405 [DEBUG] clck_gen.py:113 IND CLOCK 2958
2026-01-29 01:48:29.883 [DEBUG] clck_gen.py:113 IND CLOCK 3060
2026-01-29 01:48:30.361 [DEBUG] clck_gen.py:113 IND CLOCK 3162
2026-01-29 01:48:30.839 [DEBUG] clck_gen.py:113 IND CLOCK 3264
2026-01-29 01:48:31.317 [DEBUG] clck_gen.py:113 IND CLOCK 3366
2026-01-29 01:48:31.795 [DEBUG] clck_gen.py:113 IND CLOCK 3468
2026-01-29 01:48:32.098 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:48:32.104 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 01:48:32.104 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 01:48:32.105 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 01:48:32.119 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 01:48:32.119 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 01:48:32.119 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 01:48:32.120 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 01:48:32.120 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 01:48:32.120 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 01:48:32.120 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.28.22:6700) Recv POWERON CMD
2026-01-29 01:48:32.120 [INFO] ctrl_if_trx.py:109 (MS@172.18.28.22:6700) Starting transceiver...
2026-01-29 01:48:32.170 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:48:32.171 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 01:48:32.172 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 01:48:32.172 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 01:48:32.173 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 01:48:32.272 [DEBUG] clck_gen.py:113 IND CLOCK 3570
2026-01-29 01:48:32.750 [DEBUG] clck_gen.py:113 IND CLOCK 3672
2026-01-29 01:48:33.228 [DEBUG] clck_gen.py:113 IND CLOCK 3774
2026-01-29 01:48:33.706 [DEBUG] clck_gen.py:113 IND CLOCK 3876
2026-01-29 01:48:34.183 [DEBUG] clck_gen.py:113 IND CLOCK 3978
2026-01-29 01:48:34.662 [DEBUG] clck_gen.py:113 IND CLOCK 4080
2026-01-29 01:48:35.139 [DEBUG] clck_gen.py:113 IND CLOCK 4182
2026-01-29 01:48:35.617 [DEBUG] clck_gen.py:113 IND CLOCK 4284
2026-01-29 01:48:36.095 [DEBUG] clck_gen.py:113 IND CLOCK 4386
2026-01-29 01:48:36.573 [DEBUG] clck_gen.py:113 IND CLOCK 4488
2026-01-29 01:48:37.052 [DEBUG] clck_gen.py:113 IND CLOCK 4590
2026-01-29 01:48:37.530 [DEBUG] clck_gen.py:113 IND CLOCK 4692
2026-01-29 01:48:38.008 [DEBUG] clck_gen.py:113 IND CLOCK 4794
2026-01-29 01:48:38.485 [DEBUG] clck_gen.py:113 IND CLOCK 4896
2026-01-29 01:48:38.963 [DEBUG] clck_gen.py:113 IND CLOCK 4998
2026-01-29 01:48:39.441 [DEBUG] clck_gen.py:113 IND CLOCK 5100
2026-01-29 01:48:39.918 [DEBUG] clck_gen.py:113 IND CLOCK 5202
2026-01-29 01:48:40.396 [DEBUG] clck_gen.py:113 IND CLOCK 5304
2026-01-29 01:48:40.874 [DEBUG] clck_gen.py:113 IND CLOCK 5406
2026-01-29 01:48:41.352 [DEBUG] clck_gen.py:113 IND CLOCK 5508
2026-01-29 01:48:41.830 [DEBUG] clck_gen.py:113 IND CLOCK 5610
2026-01-29 01:48:42.308 [DEBUG] clck_gen.py:113 IND CLOCK 5712
2026-01-29 01:48:42.785 [DEBUG] clck_gen.py:113 IND CLOCK 5814
2026-01-29 01:48:43.263 [DEBUG] clck_gen.py:113 IND CLOCK 5916
2026-01-29 01:48:43.741 [DEBUG] clck_gen.py:113 IND CLOCK 6018
2026-01-29 01:48:44.220 [DEBUG] clck_gen.py:113 IND CLOCK 6120
2026-01-29 01:48:44.698 [DEBUG] clck_gen.py:113 IND CLOCK 6222
2026-01-29 01:48:45.176 [DEBUG] clck_gen.py:113 IND CLOCK 6324
2026-01-29 01:48:45.654 [DEBUG] clck_gen.py:113 IND CLOCK 6426
2026-01-29 01:48:46.132 [DEBUG] clck_gen.py:113 IND CLOCK 6528
2026-01-29 01:48:46.610 [DEBUG] clck_gen.py:113 IND CLOCK 6630
2026-01-29 01:48:47.088 [DEBUG] clck_gen.py:113 IND CLOCK 6732
2026-01-29 01:48:47.566 [DEBUG] clck_gen.py:113 IND CLOCK 6834
2026-01-29 01:48:47.754 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:48:47.758 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 01:48:47.758 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 01:48:47.758 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 01:48:47.772 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 01:48:47.772 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 01:48:47.772 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 01:48:47.774 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 01:48:47.774 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 01:48:47.774 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 01:48:47.774 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.28.22:6700) Recv POWERON CMD
2026-01-29 01:48:47.774 [INFO] ctrl_if_trx.py:109 (MS@172.18.28.22:6700) Starting transceiver...
2026-01-29 01:48:47.803 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:48:47.807 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 01:48:47.808 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 01:48:47.808 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 01:48:47.808 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 01:48:48.044 [DEBUG] clck_gen.py:113 IND CLOCK 6936
2026-01-29 01:48:48.522 [DEBUG] clck_gen.py:113 IND CLOCK 7038
2026-01-29 01:48:49.000 [DEBUG] clck_gen.py:113 IND CLOCK 7140
2026-01-29 01:48:49.478 [DEBUG] clck_gen.py:113 IND CLOCK 7242
2026-01-29 01:48:49.956 [DEBUG] clck_gen.py:113 IND CLOCK 7344
2026-01-29 01:48:50.434 [DEBUG] clck_gen.py:113 IND CLOCK 7446
2026-01-29 01:48:50.912 [DEBUG] clck_gen.py:113 IND CLOCK 7548
2026-01-29 01:48:51.390 [DEBUG] clck_gen.py:113 IND CLOCK 7650
2026-01-29 01:48:51.867 [DEBUG] clck_gen.py:113 IND CLOCK 7752
2026-01-29 01:48:52.345 [DEBUG] clck_gen.py:113 IND CLOCK 7854
2026-01-29 01:48:52.823 [DEBUG] clck_gen.py:113 IND CLOCK 7956
2026-01-29 01:48:53.300 [DEBUG] clck_gen.py:113 IND CLOCK 8058
2026-01-29 01:48:53.778 [DEBUG] clck_gen.py:113 IND CLOCK 8160
2026-01-29 01:48:54.256 [DEBUG] clck_gen.py:113 IND CLOCK 8262
2026-01-29 01:48:54.733 [DEBUG] clck_gen.py:113 IND CLOCK 8364
2026-01-29 01:48:55.212 [DEBUG] clck_gen.py:113 IND CLOCK 8466
2026-01-29 01:48:55.690 [DEBUG] clck_gen.py:113 IND CLOCK 8568
2026-01-29 01:48:56.168 [DEBUG] clck_gen.py:113 IND CLOCK 8670
2026-01-29 01:48:56.645 [DEBUG] clck_gen.py:113 IND CLOCK 8772
2026-01-29 01:48:57.124 [DEBUG] clck_gen.py:113 IND CLOCK 8874
2026-01-29 01:48:57.602 [DEBUG] clck_gen.py:113 IND CLOCK 8976
2026-01-29 01:48:58.080 [DEBUG] clck_gen.py:113 IND CLOCK 9078
2026-01-29 01:48:58.558 [DEBUG] clck_gen.py:113 IND CLOCK 9180
2026-01-29 01:48:59.036 [DEBUG] clck_gen.py:113 IND CLOCK 9282
2026-01-29 01:48:59.513 [DEBUG] clck_gen.py:113 IND CLOCK 9384
2026-01-29 01:48:59.991 [DEBUG] clck_gen.py:113 IND CLOCK 9486
2026-01-29 01:49:00.469 [DEBUG] clck_gen.py:113 IND CLOCK 9588
2026-01-29 01:49:00.947 [DEBUG] clck_gen.py:113 IND CLOCK 9690
2026-01-29 01:49:01.424 [DEBUG] clck_gen.py:113 IND CLOCK 9792
2026-01-29 01:49:01.903 [DEBUG] clck_gen.py:113 IND CLOCK 9894
2026-01-29 01:49:02.381 [DEBUG] clck_gen.py:113 IND CLOCK 9996
2026-01-29 01:49:02.859 [DEBUG] clck_gen.py:113 IND CLOCK 10098
2026-01-29 01:49:03.337 [DEBUG] clck_gen.py:113 IND CLOCK 10200
2026-01-29 01:49:03.410 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:49:03.416 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 01:49:03.416 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 01:49:03.416 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 01:49:03.431 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 01:49:03.431 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 01:49:03.431 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 01:49:03.432 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 01:49:03.432 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 01:49:03.432 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 01:49:03.432 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.28.22:6700) Recv POWERON CMD
2026-01-29 01:49:03.432 [INFO] ctrl_if_trx.py:109 (MS@172.18.28.22:6700) Starting transceiver...
2026-01-29 01:49:03.477 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 01:49:03.478 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:49:03.483 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 01:49:03.483 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 01:49:03.483 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 01:49:03.483 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 01:49:03.812 [DEBUG] clck_gen.py:113 IND CLOCK 10302
2026-01-29 01:49:04.290 [DEBUG] clck_gen.py:113 IND CLOCK 10404
2026-01-29 01:49:04.767 [DEBUG] clck_gen.py:113 IND CLOCK 10506
2026-01-29 01:49:05.245 [DEBUG] clck_gen.py:113 IND CLOCK 10608
2026-01-29 01:49:05.723 [DEBUG] clck_gen.py:113 IND CLOCK 10710
2026-01-29 01:49:06.202 [DEBUG] clck_gen.py:113 IND CLOCK 10812
2026-01-29 01:49:06.680 [DEBUG] clck_gen.py:113 IND CLOCK 10914
2026-01-29 01:49:07.158 [DEBUG] clck_gen.py:113 IND CLOCK 11016
2026-01-29 01:49:07.635 [DEBUG] clck_gen.py:113 IND CLOCK 11118
2026-01-29 01:49:08.113 [DEBUG] clck_gen.py:113 IND CLOCK 11220
2026-01-29 01:49:08.590 [DEBUG] clck_gen.py:113 IND CLOCK 11322
2026-01-29 01:49:09.068 [DEBUG] clck_gen.py:113 IND CLOCK 11424
2026-01-29 01:49:09.546 [DEBUG] clck_gen.py:113 IND CLOCK 11526
2026-01-29 01:49:10.024 [DEBUG] clck_gen.py:113 IND CLOCK 11628
2026-01-29 01:49:10.502 [DEBUG] clck_gen.py:113 IND CLOCK 11730
2026-01-29 01:49:10.980 [DEBUG] clck_gen.py:113 IND CLOCK 11832
2026-01-29 01:49:11.458 [DEBUG] clck_gen.py:113 IND CLOCK 11934
2026-01-29 01:49:11.936 [DEBUG] clck_gen.py:113 IND CLOCK 12036
2026-01-29 01:49:12.414 [DEBUG] clck_gen.py:113 IND CLOCK 12138
2026-01-29 01:49:12.893 [DEBUG] clck_gen.py:113 IND CLOCK 12240
2026-01-29 01:49:13.370 [DEBUG] clck_gen.py:113 IND CLOCK 12342
2026-01-29 01:49:13.848 [DEBUG] clck_gen.py:113 IND CLOCK 12444
2026-01-29 01:49:14.326 [DEBUG] clck_gen.py:113 IND CLOCK 12546
2026-01-29 01:49:14.804 [DEBUG] clck_gen.py:113 IND CLOCK 12648
2026-01-29 01:49:15.281 [DEBUG] clck_gen.py:113 IND CLOCK 12750
2026-01-29 01:49:15.759 [DEBUG] clck_gen.py:113 IND CLOCK 12852
2026-01-29 01:49:16.238 [DEBUG] clck_gen.py:113 IND CLOCK 12954
2026-01-29 01:49:16.715 [DEBUG] clck_gen.py:113 IND CLOCK 13056
2026-01-29 01:49:17.193 [DEBUG] clck_gen.py:113 IND CLOCK 13158
2026-01-29 01:49:17.672 [DEBUG] clck_gen.py:113 IND CLOCK 13260
2026-01-29 01:49:18.149 [DEBUG] clck_gen.py:113 IND CLOCK 13362
2026-01-29 01:49:18.626 [DEBUG] clck_gen.py:113 IND CLOCK 13464
2026-01-29 01:49:19.055 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:49:19.060 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 01:49:19.061 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 01:49:19.061 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 01:49:19.072 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 01:49:19.072 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 01:49:19.072 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 01:49:19.072 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 01:49:19.076 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 01:49:19.076 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 01:49:19.076 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 01:49:19.076 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 01:49:19.076 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.28.20:5700) Recv POWEROFF cmd
2026-01-29 01:49:19.076 [INFO] ctrl_if_trx.py:117 (BTS@172.18.28.20:5700) Stopping transceiver...
2026-01-29 01:49:19.076 [INFO] transceiver.py:246 Stopping clock generator
2026-01-29 01:49:19.076 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=13562 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 01:49:19.076 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=13562 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 01:49:24.075 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.28.20:5700) Recv POWEROFF cmd
2026-01-29 01:49:24.075 [INFO] ctrl_if_trx.py:117 (BTS@172.18.28.20:5700) Stopping transceiver...
2026-01-29 01:49:24.077 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 01:49:24.078 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 01:49:24.079 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 01:49:24.080 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 01:49:24.087 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 01:49:24.089 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.28.20:5700) Recv SETFORMAT cmd
2026-01-29 01:49:24.089 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.28.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 01:49:24.089 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.28.20:5700) Recv SETFORMAT cmd
2026-01-29 01:49:24.089 [INFO] ctrl_if_trx.py:201 (BTS@172.18.28.20:5700) TRXD header version 1 -> 1
2026-01-29 01:49:24.095 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.28.20:5700/1) Recv RXTUNE cmd
2026-01-29 01:49:24.095 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.28.20:5700/1) Recv TXTUNE cmd
2026-01-29 01:49:24.096 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.28.20:5700/1) Recv SETFORMAT cmd
2026-01-29 01:49:24.096 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.28.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 01:49:24.097 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 01:49:24.097 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.28.20:5700/1) Recv NOMTXPOWER cmd
2026-01-29 01:49:24.097 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.28.20:5700/1) Recv SETFORMAT cmd
2026-01-29 01:49:24.098 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.28.20:5700/1) TRXD header version 1 -> 1
2026-01-29 01:49:24.098 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.28.20:5700/2) Recv RXTUNE cmd
2026-01-29 01:49:24.099 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.28.20:5700/2) Recv TXTUNE cmd
2026-01-29 01:49:24.099 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.28.20:5700/2) Recv SETFORMAT cmd
2026-01-29 01:49:24.099 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.28.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 01:49:24.100 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 01:49:24.100 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.28.20:5700/2) Recv NOMTXPOWER cmd
2026-01-29 01:49:24.100 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.28.20:5700/2) Recv SETFORMAT cmd
2026-01-29 01:49:24.100 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.28.20:5700/2) TRXD header version 1 -> 1
2026-01-29 01:49:24.101 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.28.20:5700/3) Recv RXTUNE cmd
2026-01-29 01:49:24.101 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.28.20:5700/3) Recv TXTUNE cmd
2026-01-29 01:49:24.102 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.28.20:5700/3) Recv SETFORMAT cmd
2026-01-29 01:49:24.102 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.28.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 01:49:24.102 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 01:49:24.102 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.28.20:5700/3) Recv NOMTXPOWER cmd
2026-01-29 01:49:24.102 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.28.20:5700/3) Recv SETFORMAT cmd
2026-01-29 01:49:24.102 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.28.20:5700/3) TRXD header version 1 -> 1
2026-01-29 01:49:24.104 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.28.20:5700) Recv RXTUNE cmd
2026-01-29 01:49:24.104 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETTSC
2026-01-29 01:49:24.105 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETTSC
2026-01-29 01:49:24.105 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETTSC
2026-01-29 01:49:24.105 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.28.20:5700) Recv TXTUNE cmd
2026-01-29 01:49:24.105 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETRXGAIN
2026-01-29 01:49:24.105 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETRXGAIN
2026-01-29 01:49:24.105 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETRXGAIN
2026-01-29 01:49:24.105 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETTSC
2026-01-29 01:49:24.105 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:49:24.105 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:49:24.105 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:49:24.105 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.28.20:5700) Recv NOMTXPOWER cmd
2026-01-29 01:49:24.105 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:49:24.105 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:49:24.105 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:49:24.105 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.28.20:5700) Recv POWERON CMD
2026-01-29 01:49:24.105 [INFO] ctrl_if_trx.py:109 (BTS@172.18.28.20:5700) Starting transceiver...
2026-01-29 01:49:24.105 [INFO] transceiver.py:243 Starting clock generator
2026-01-29 01:49:24.105 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-01-29 01:49:24.105 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:49:24.105 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:49:24.106 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:49:24.106 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETRXGAIN
2026-01-29 01:49:24.107 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:49:24.107 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:49:24.107 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:49:24.107 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 01:49:24.107 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:49:24.107 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:49:24.107 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:49:24.107 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 01:49:24.107 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:49:24.107 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:49:24.107 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 01:49:24.107 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:49:24.107 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:49:24.107 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 01:49:24.107 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:49:24.107 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:49:24.107 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 01:49:24.107 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 01:49:24.107 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:49:24.107 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 01:49:24.107 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:49:24.107 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 01:49:24.107 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:49:24.107 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 01:49:24.107 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 01:49:24.107 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 01:49:24.107 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 01:49:24.107 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.28.20:5700) Recv POWEROFF cmd
2026-01-29 01:49:24.107 [INFO] ctrl_if_trx.py:117 (BTS@172.18.28.20:5700) Stopping transceiver...
2026-01-29 01:49:24.107 [INFO] transceiver.py:246 Stopping clock generator
2026-01-29 01:49:29.110 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.28.20:5700) Recv POWEROFF cmd
2026-01-29 01:49:29.110 [INFO] ctrl_if_trx.py:117 (BTS@172.18.28.20:5700) Stopping transceiver...
2026-01-29 01:49:29.112 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 01:49:29.113 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 01:49:29.115 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 01:49:29.115 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 01:49:29.128 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 01:49:29.130 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.28.20:5700) Recv SETFORMAT cmd
2026-01-29 01:49:29.130 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.28.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 01:49:29.131 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.28.20:5700) Recv SETFORMAT cmd
2026-01-29 01:49:29.131 [INFO] ctrl_if_trx.py:201 (BTS@172.18.28.20:5700) TRXD header version 1 -> 1
2026-01-29 01:49:29.136 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.28.20:5700/1) Recv RXTUNE cmd
2026-01-29 01:49:29.136 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.28.20:5700/1) Recv TXTUNE cmd
2026-01-29 01:49:29.136 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.28.20:5700/1) Recv SETFORMAT cmd
2026-01-29 01:49:29.137 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.28.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 01:49:29.137 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 01:49:29.137 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.28.20:5700/1) Recv NOMTXPOWER cmd
2026-01-29 01:49:29.138 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.28.20:5700/1) Recv SETFORMAT cmd
2026-01-29 01:49:29.138 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.28.20:5700/1) TRXD header version 1 -> 1
2026-01-29 01:49:29.139 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.28.20:5700/2) Recv RXTUNE cmd
2026-01-29 01:49:29.139 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.28.20:5700/2) Recv TXTUNE cmd
2026-01-29 01:49:29.140 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.28.20:5700/2) Recv SETFORMAT cmd
2026-01-29 01:49:29.140 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.28.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 01:49:29.140 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 01:49:29.140 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.28.20:5700/2) Recv NOMTXPOWER cmd
2026-01-29 01:49:29.140 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.28.20:5700/2) Recv SETFORMAT cmd
2026-01-29 01:49:29.140 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.28.20:5700/2) TRXD header version 1 -> 1
2026-01-29 01:49:29.142 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.28.20:5700/3) Recv RXTUNE cmd
2026-01-29 01:49:29.142 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.28.20:5700/3) Recv TXTUNE cmd
2026-01-29 01:49:29.142 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.28.20:5700/3) Recv SETFORMAT cmd
2026-01-29 01:49:29.142 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.28.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 01:49:29.142 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 01:49:29.142 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.28.20:5700/3) Recv NOMTXPOWER cmd
2026-01-29 01:49:29.142 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.28.20:5700/3) Recv SETFORMAT cmd
2026-01-29 01:49:29.142 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.28.20:5700/3) TRXD header version 1 -> 1
2026-01-29 01:49:29.145 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.28.20:5700) Recv RXTUNE cmd
2026-01-29 01:49:29.145 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETTSC
2026-01-29 01:49:29.145 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETTSC
2026-01-29 01:49:29.145 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETTSC
2026-01-29 01:49:29.145 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.28.20:5700) Recv TXTUNE cmd
2026-01-29 01:49:29.145 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETRXGAIN
2026-01-29 01:49:29.145 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETRXGAIN
2026-01-29 01:49:29.145 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETRXGAIN
2026-01-29 01:49:29.145 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETTSC
2026-01-29 01:49:29.145 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:49:29.145 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:49:29.145 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.28.20:5700) Recv NOMTXPOWER cmd
2026-01-29 01:49:29.145 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:49:29.145 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:49:29.145 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:49:29.145 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.28.20:5700) Recv POWERON CMD
2026-01-29 01:49:29.145 [INFO] ctrl_if_trx.py:109 (BTS@172.18.28.20:5700) Starting transceiver...
2026-01-29 01:49:29.145 [INFO] transceiver.py:243 Starting clock generator
2026-01-29 01:49:29.145 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-01-29 01:49:29.145 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:49:29.146 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:49:29.146 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:49:29.146 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETRXGAIN
2026-01-29 01:49:29.146 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:49:29.146 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:49:29.146 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:49:29.146 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 01:49:29.146 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:49:29.146 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:49:29.146 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:49:29.146 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 01:49:29.146 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:49:29.146 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:49:29.146 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:49:29.146 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 01:49:29.146 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:49:29.146 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:49:29.146 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 01:49:29.146 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:49:29.146 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:49:29.146 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 01:49:29.146 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:49:29.146 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 01:49:29.146 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:49:29.146 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 01:49:29.147 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:49:29.147 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 01:49:29.150 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-01-29 01:49:29.635 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-01-29 01:49:29.674 [DEBUG] fake_trx.py:278 (BTS@172.18.28.20:5700) Recv FAKE_TOA cmd
2026-01-29 01:49:29.675 [DEBUG] fake_trx.py:297 (BTS@172.18.28.20:5700) Recv FAKE_RSSI cmd
2026-01-29 01:49:29.678 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:49:29.678 [DEBUG] fake_trx.py:322 (BTS@172.18.28.20:5700) Recv FAKE_CI cmd
2026-01-29 01:49:29.704 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 01:49:29.704 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 01:49:29.704 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 01:49:29.707 [DEBUG] fake_trx.py:297 (BTS@172.18.28.20:5700) Recv FAKE_RSSI cmd
2026-01-29 01:49:29.708 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 01:49:29.708 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 01:49:29.708 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 01:49:29.708 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.28.22:6700) Recv POWERON CMD
2026-01-29 01:49:29.708 [INFO] ctrl_if_trx.py:109 (MS@172.18.28.22:6700) Starting transceiver...
2026-01-29 01:49:29.731 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:49:29.736 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 01:49:29.736 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 01:49:29.736 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 01:49:29.736 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 01:49:30.112 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-01-29 01:49:30.149 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 01:49:30.149 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 01:49:30.149 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 01:49:30.153 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 01:49:30.590 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-01-29 01:49:31.069 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-01-29 01:49:31.150 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 01:49:31.150 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 01:49:31.150 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 01:49:31.154 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 01:49:31.546 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-01-29 01:49:32.024 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-01-29 01:49:32.151 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 01:49:32.152 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 01:49:32.152 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 01:49:32.155 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 01:49:32.502 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-01-29 01:49:32.979 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-01-29 01:49:33.152 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 01:49:33.152 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 01:49:33.153 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 01:49:33.156 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 01:49:33.458 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-01-29 01:49:33.936 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-01-29 01:49:34.153 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 01:49:34.153 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 01:49:34.153 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 01:49:34.157 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 01:49:34.413 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-01-29 01:49:34.891 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-01-29 01:49:35.369 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-01-29 01:49:35.847 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-01-29 01:49:36.325 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-01-29 01:49:36.803 [DEBUG] clck_gen.py:113 IND CLOCK 1632
2026-01-29 01:49:37.281 [DEBUG] clck_gen.py:113 IND CLOCK 1734
2026-01-29 01:49:37.758 [DEBUG] clck_gen.py:113 IND CLOCK 1836
2026-01-29 01:49:38.236 [DEBUG] clck_gen.py:113 IND CLOCK 1938
2026-01-29 01:49:38.714 [DEBUG] clck_gen.py:113 IND CLOCK 2040
2026-01-29 01:49:39.192 [DEBUG] clck_gen.py:113 IND CLOCK 2142
2026-01-29 01:49:39.669 [DEBUG] clck_gen.py:113 IND CLOCK 2244
2026-01-29 01:49:40.115 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:49:40.119 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 01:49:40.119 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 01:49:40.119 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 01:49:40.131 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 01:49:40.131 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 01:49:40.131 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 01:49:40.132 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 01:49:40.134 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 01:49:40.134 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 01:49:40.134 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 01:49:40.134 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 01:49:40.134 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.28.20:5700) Recv POWEROFF cmd
2026-01-29 01:49:40.134 [INFO] ctrl_if_trx.py:117 (BTS@172.18.28.20:5700) Stopping transceiver...
2026-01-29 01:49:40.134 [INFO] transceiver.py:246 Stopping clock generator
2026-01-29 01:49:40.134 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=2346 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 01:49:40.134 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=2346 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 01:49:40.134 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=2346 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 01:49:40.134 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=2346 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 01:49:40.134 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=2346 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 01:49:40.134 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=2346 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 01:49:40.134 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=2346 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 01:49:40.134 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=2346 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 01:49:45.134 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.28.20:5700) Recv POWEROFF cmd
2026-01-29 01:49:45.135 [INFO] ctrl_if_trx.py:117 (BTS@172.18.28.20:5700) Stopping transceiver...
2026-01-29 01:49:45.136 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 01:49:45.138 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 01:49:45.139 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 01:49:45.139 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 01:49:45.146 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 01:49:45.146 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.28.20:5700) Recv SETFORMAT cmd
2026-01-29 01:49:45.146 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.28.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 01:49:45.146 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.28.20:5700) Recv SETFORMAT cmd
2026-01-29 01:49:45.146 [INFO] ctrl_if_trx.py:201 (BTS@172.18.28.20:5700) TRXD header version 1 -> 1
2026-01-29 01:49:45.147 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.28.20:5700/1) Recv RXTUNE cmd
2026-01-29 01:49:45.147 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.28.20:5700/1) Recv TXTUNE cmd
2026-01-29 01:49:45.148 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.28.20:5700/1) Recv SETFORMAT cmd
2026-01-29 01:49:45.148 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.28.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 01:49:45.148 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 01:49:45.149 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.28.20:5700/1) Recv NOMTXPOWER cmd
2026-01-29 01:49:45.149 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.28.20:5700/1) Recv SETFORMAT cmd
2026-01-29 01:49:45.149 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.28.20:5700/1) TRXD header version 1 -> 1
2026-01-29 01:49:45.150 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.28.20:5700/2) Recv RXTUNE cmd
2026-01-29 01:49:45.150 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.28.20:5700/2) Recv TXTUNE cmd
2026-01-29 01:49:45.150 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.28.20:5700/2) Recv SETFORMAT cmd
2026-01-29 01:49:45.150 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.28.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 01:49:45.150 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 01:49:45.150 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.28.20:5700/2) Recv NOMTXPOWER cmd
2026-01-29 01:49:45.151 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.28.20:5700/2) Recv SETFORMAT cmd
2026-01-29 01:49:45.151 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.28.20:5700/2) TRXD header version 1 -> 1
2026-01-29 01:49:45.152 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.28.20:5700/3) Recv RXTUNE cmd
2026-01-29 01:49:45.152 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.28.20:5700/3) Recv TXTUNE cmd
2026-01-29 01:49:45.152 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.28.20:5700/3) Recv SETFORMAT cmd
2026-01-29 01:49:45.152 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.28.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 01:49:45.152 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 01:49:45.152 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.28.20:5700/3) Recv NOMTXPOWER cmd
2026-01-29 01:49:45.152 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.28.20:5700/3) Recv SETFORMAT cmd
2026-01-29 01:49:45.152 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.28.20:5700/3) TRXD header version 1 -> 1
2026-01-29 01:49:45.154 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.28.20:5700) Recv RXTUNE cmd
2026-01-29 01:49:45.154 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETTSC
2026-01-29 01:49:45.154 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETTSC
2026-01-29 01:49:45.154 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETTSC
2026-01-29 01:49:45.154 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.28.20:5700) Recv TXTUNE cmd
2026-01-29 01:49:45.155 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETRXGAIN
2026-01-29 01:49:45.155 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETRXGAIN
2026-01-29 01:49:45.155 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETRXGAIN
2026-01-29 01:49:45.155 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETTSC
2026-01-29 01:49:45.155 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:49:45.155 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:49:45.155 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:49:45.155 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.28.20:5700) Recv NOMTXPOWER cmd
2026-01-29 01:49:45.155 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:49:45.155 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:49:45.155 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:49:45.155 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.28.20:5700) Recv POWERON CMD
2026-01-29 01:49:45.155 [INFO] ctrl_if_trx.py:109 (BTS@172.18.28.20:5700) Starting transceiver...
2026-01-29 01:49:45.155 [INFO] transceiver.py:243 Starting clock generator
2026-01-29 01:49:45.155 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-01-29 01:49:45.155 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:49:45.155 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:49:45.155 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:49:45.155 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETRXGAIN
2026-01-29 01:49:45.155 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:49:45.155 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:49:45.155 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 01:49:45.155 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:49:45.156 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:49:45.156 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:49:45.156 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 01:49:45.156 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:49:45.156 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:49:45.156 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:49:45.156 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 01:49:45.156 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:49:45.156 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:49:45.156 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:49:45.156 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 01:49:45.156 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:49:45.156 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:49:45.156 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:49:45.156 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 01:49:45.156 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:49:45.156 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 01:49:45.156 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 01:49:45.156 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 01:49:45.160 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-01-29 01:49:45.643 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-01-29 01:49:45.682 [DEBUG] fake_trx.py:278 (BTS@172.18.28.20:5700) Recv FAKE_TOA cmd
2026-01-29 01:49:45.684 [DEBUG] fake_trx.py:297 (BTS@172.18.28.20:5700) Recv FAKE_RSSI cmd
2026-01-29 01:49:45.686 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:49:45.686 [DEBUG] fake_trx.py:322 (BTS@172.18.28.20:5700) Recv FAKE_CI cmd
2026-01-29 01:49:45.722 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 01:49:45.722 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 01:49:45.722 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 01:49:45.728 [DEBUG] fake_trx.py:297 (BTS@172.18.28.20:5700) Recv FAKE_RSSI cmd
2026-01-29 01:49:45.730 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 01:49:45.730 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 01:49:45.730 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 01:49:45.730 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.28.22:6700) Recv POWERON CMD
2026-01-29 01:49:45.730 [INFO] ctrl_if_trx.py:109 (MS@172.18.28.22:6700) Starting transceiver...
2026-01-29 01:49:45.734 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:49:45.736 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 01:49:45.736 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 01:49:45.736 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 01:49:45.736 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 01:49:46.119 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-01-29 01:49:46.157 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 01:49:46.158 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 01:49:46.159 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 01:49:46.162 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 01:49:46.597 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-01-29 01:49:47.075 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-01-29 01:49:47.158 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 01:49:47.158 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 01:49:47.160 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 01:49:47.162 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 01:49:47.552 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-01-29 01:49:48.030 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-01-29 01:49:48.159 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 01:49:48.159 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 01:49:48.161 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 01:49:48.164 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 01:49:48.508 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-01-29 01:49:48.985 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-01-29 01:49:49.160 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 01:49:49.160 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 01:49:49.161 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 01:49:49.165 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 01:49:49.463 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-01-29 01:49:49.941 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-01-29 01:49:50.161 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 01:49:50.162 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 01:49:50.162 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 01:49:50.166 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 01:49:50.418 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-01-29 01:49:50.896 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-01-29 01:49:51.373 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-01-29 01:49:51.851 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-01-29 01:49:52.329 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-01-29 01:49:52.807 [DEBUG] clck_gen.py:113 IND CLOCK 1632
2026-01-29 01:49:53.284 [DEBUG] clck_gen.py:113 IND CLOCK 1734
2026-01-29 01:49:53.762 [DEBUG] clck_gen.py:113 IND CLOCK 1836
2026-01-29 01:49:54.239 [DEBUG] clck_gen.py:113 IND CLOCK 1938
2026-01-29 01:49:54.717 [DEBUG] clck_gen.py:113 IND CLOCK 2040
2026-01-29 01:49:55.195 [DEBUG] clck_gen.py:113 IND CLOCK 2142
2026-01-29 01:49:55.673 [DEBUG] clck_gen.py:113 IND CLOCK 2244
2026-01-29 01:49:56.123 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:49:56.127 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 01:49:56.128 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 01:49:56.128 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 01:49:56.140 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 01:49:56.140 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 01:49:56.141 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 01:49:56.141 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 01:49:56.143 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 01:49:56.143 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 01:49:56.143 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 01:49:56.143 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 01:49:56.143 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.28.20:5700) Recv POWEROFF cmd
2026-01-29 01:49:56.143 [INFO] ctrl_if_trx.py:117 (BTS@172.18.28.20:5700) Stopping transceiver...
2026-01-29 01:49:56.143 [INFO] transceiver.py:246 Stopping clock generator
2026-01-29 01:49:56.143 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=2347 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 01:49:56.143 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=2347 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 01:49:56.143 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=2347 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 01:49:56.143 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=2347 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 01:49:56.143 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=2347 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 01:49:56.143 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=2347 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 01:49:56.143 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=2347 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 01:50:01.145 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.28.20:5700) Recv POWEROFF cmd
2026-01-29 01:50:01.145 [INFO] ctrl_if_trx.py:117 (BTS@172.18.28.20:5700) Stopping transceiver...
2026-01-29 01:50:01.146 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 01:50:01.147 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 01:50:01.147 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 01:50:01.148 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 01:50:01.161 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 01:50:01.162 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.28.20:5700) Recv SETFORMAT cmd
2026-01-29 01:50:01.162 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.28.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 01:50:01.163 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.28.20:5700) Recv SETFORMAT cmd
2026-01-29 01:50:01.163 [INFO] ctrl_if_trx.py:201 (BTS@172.18.28.20:5700) TRXD header version 1 -> 1
2026-01-29 01:50:01.165 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.28.20:5700/1) Recv RXTUNE cmd
2026-01-29 01:50:01.166 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.28.20:5700/1) Recv TXTUNE cmd
2026-01-29 01:50:01.166 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.28.20:5700/1) Recv SETFORMAT cmd
2026-01-29 01:50:01.166 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.28.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 01:50:01.167 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 01:50:01.167 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.28.20:5700/1) Recv NOMTXPOWER cmd
2026-01-29 01:50:01.167 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.28.20:5700/1) Recv SETFORMAT cmd
2026-01-29 01:50:01.167 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.28.20:5700/1) TRXD header version 1 -> 1
2026-01-29 01:50:01.168 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.28.20:5700/2) Recv RXTUNE cmd
2026-01-29 01:50:01.169 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.28.20:5700/2) Recv TXTUNE cmd
2026-01-29 01:50:01.169 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.28.20:5700/2) Recv SETFORMAT cmd
2026-01-29 01:50:01.169 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.28.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 01:50:01.169 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 01:50:01.169 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.28.20:5700/2) Recv NOMTXPOWER cmd
2026-01-29 01:50:01.169 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.28.20:5700/2) Recv SETFORMAT cmd
2026-01-29 01:50:01.169 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.28.20:5700/2) TRXD header version 1 -> 1
2026-01-29 01:50:01.171 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.28.20:5700/3) Recv RXTUNE cmd
2026-01-29 01:50:01.171 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.28.20:5700/3) Recv TXTUNE cmd
2026-01-29 01:50:01.171 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.28.20:5700/3) Recv SETFORMAT cmd
2026-01-29 01:50:01.171 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.28.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 01:50:01.171 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 01:50:01.171 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.28.20:5700/3) Recv NOMTXPOWER cmd
2026-01-29 01:50:01.171 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.28.20:5700/3) Recv SETFORMAT cmd
2026-01-29 01:50:01.171 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.28.20:5700/3) TRXD header version 1 -> 1
2026-01-29 01:50:01.173 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.28.20:5700) Recv RXTUNE cmd
2026-01-29 01:50:01.173 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETTSC
2026-01-29 01:50:01.173 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETTSC
2026-01-29 01:50:01.173 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETTSC
2026-01-29 01:50:01.173 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.28.20:5700) Recv TXTUNE cmd
2026-01-29 01:50:01.174 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETRXGAIN
2026-01-29 01:50:01.174 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETRXGAIN
2026-01-29 01:50:01.174 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETRXGAIN
2026-01-29 01:50:01.174 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETTSC
2026-01-29 01:50:01.174 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:50:01.174 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:50:01.174 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:50:01.174 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.28.20:5700) Recv NOMTXPOWER cmd
2026-01-29 01:50:01.174 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:50:01.174 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:50:01.174 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:50:01.174 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.28.20:5700) Recv POWERON CMD
2026-01-29 01:50:01.174 [INFO] ctrl_if_trx.py:109 (BTS@172.18.28.20:5700) Starting transceiver...
2026-01-29 01:50:01.174 [INFO] transceiver.py:243 Starting clock generator
2026-01-29 01:50:01.174 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-01-29 01:50:01.174 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:50:01.174 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:50:01.174 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:50:01.175 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETRXGAIN
2026-01-29 01:50:01.175 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:50:01.175 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:50:01.175 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:50:01.175 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 01:50:01.175 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:50:01.175 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:50:01.175 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:50:01.175 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 01:50:01.175 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:50:01.175 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:50:01.175 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:50:01.175 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 01:50:01.175 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:50:01.175 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:50:01.176 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:50:01.176 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 01:50:01.176 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:50:01.176 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:50:01.176 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:50:01.176 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 01:50:01.176 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 01:50:01.176 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 01:50:01.176 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 01:50:01.179 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-01-29 01:50:01.663 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-01-29 01:50:01.699 [DEBUG] fake_trx.py:278 (BTS@172.18.28.20:5700) Recv FAKE_TOA cmd
2026-01-29 01:50:01.701 [DEBUG] fake_trx.py:297 (BTS@172.18.28.20:5700) Recv FAKE_RSSI cmd
2026-01-29 01:50:01.702 [DEBUG] fake_trx.py:322 (BTS@172.18.28.20:5700) Recv FAKE_CI cmd
2026-01-29 01:50:01.702 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:50:01.727 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 01:50:01.727 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 01:50:01.727 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 01:50:01.734 [DEBUG] fake_trx.py:297 (BTS@172.18.28.20:5700) Recv FAKE_RSSI cmd
2026-01-29 01:50:01.737 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 01:50:01.737 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 01:50:01.737 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 01:50:01.737 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.28.22:6700) Recv POWERON CMD
2026-01-29 01:50:01.737 [INFO] ctrl_if_trx.py:109 (MS@172.18.28.22:6700) Starting transceiver...
2026-01-29 01:50:01.759 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:50:01.765 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 01:50:01.765 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 01:50:01.766 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 01:50:01.766 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 01:50:02.140 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-01-29 01:50:02.178 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 01:50:02.178 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 01:50:02.179 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 01:50:02.182 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 01:50:02.618 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-01-29 01:50:02.634 [DEBUG] fake_trx.py:269 (MS@172.18.28.22:6700) Recv SETTA cmd
2026-01-29 01:50:03.096 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-01-29 01:50:03.178 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 01:50:03.179 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 01:50:03.179 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 01:50:03.183 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 01:50:03.573 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-01-29 01:50:04.051 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-01-29 01:50:04.179 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 01:50:04.180 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 01:50:04.180 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 01:50:04.184 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 01:50:04.528 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-01-29 01:50:05.006 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-01-29 01:50:05.180 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 01:50:05.181 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 01:50:05.181 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 01:50:05.185 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 01:50:05.484 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-01-29 01:50:05.961 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-01-29 01:50:06.181 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 01:50:06.181 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 01:50:06.181 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 01:50:06.186 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 01:50:06.439 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-01-29 01:50:06.917 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-01-29 01:50:07.395 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-01-29 01:50:07.873 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-01-29 01:50:08.351 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-01-29 01:50:08.828 [DEBUG] clck_gen.py:113 IND CLOCK 1632
2026-01-29 01:50:09.306 [DEBUG] clck_gen.py:113 IND CLOCK 1734
2026-01-29 01:50:09.784 [DEBUG] clck_gen.py:113 IND CLOCK 1836
2026-01-29 01:50:10.262 [DEBUG] clck_gen.py:113 IND CLOCK 1938
2026-01-29 01:50:10.740 [DEBUG] clck_gen.py:113 IND CLOCK 2040
2026-01-29 01:50:11.218 [DEBUG] clck_gen.py:113 IND CLOCK 2142
2026-01-29 01:50:11.695 [DEBUG] clck_gen.py:113 IND CLOCK 2244
2026-01-29 01:50:12.173 [DEBUG] clck_gen.py:113 IND CLOCK 2346
2026-01-29 01:50:12.651 [DEBUG] clck_gen.py:113 IND CLOCK 2448
2026-01-29 01:50:13.129 [DEBUG] clck_gen.py:113 IND CLOCK 2550
2026-01-29 01:50:13.606 [DEBUG] clck_gen.py:113 IND CLOCK 2652
2026-01-29 01:50:14.084 [DEBUG] clck_gen.py:113 IND CLOCK 2754
2026-01-29 01:50:14.562 [DEBUG] clck_gen.py:113 IND CLOCK 2856
2026-01-29 01:50:15.040 [DEBUG] clck_gen.py:113 IND CLOCK 2958
2026-01-29 01:50:15.518 [DEBUG] clck_gen.py:113 IND CLOCK 3060
2026-01-29 01:50:15.996 [DEBUG] clck_gen.py:113 IND CLOCK 3162
2026-01-29 01:50:16.474 [DEBUG] clck_gen.py:113 IND CLOCK 3264
2026-01-29 01:50:16.952 [DEBUG] clck_gen.py:113 IND CLOCK 3366
2026-01-29 01:50:17.430 [DEBUG] clck_gen.py:113 IND CLOCK 3468
2026-01-29 01:50:17.907 [DEBUG] clck_gen.py:113 IND CLOCK 3570
2026-01-29 01:50:18.385 [DEBUG] clck_gen.py:113 IND CLOCK 3672
2026-01-29 01:50:18.863 [DEBUG] clck_gen.py:113 IND CLOCK 3774
2026-01-29 01:50:19.341 [DEBUG] clck_gen.py:113 IND CLOCK 3876
2026-01-29 01:50:19.819 [DEBUG] clck_gen.py:113 IND CLOCK 3978
2026-01-29 01:50:20.297 [DEBUG] clck_gen.py:113 IND CLOCK 4080
2026-01-29 01:50:20.775 [DEBUG] clck_gen.py:113 IND CLOCK 4182
2026-01-29 01:50:21.253 [DEBUG] clck_gen.py:113 IND CLOCK 4284
2026-01-29 01:50:21.344 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:50:21.351 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 01:50:21.352 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 01:50:21.352 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 01:50:21.352 [WARNING] transceiver.py:257 (MS@172.18.28.22:6700) RX TRXD message (fn=4307 tn=5 pwr=0), but transceiver is not running => dropping...
2026-01-29 01:50:21.362 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 01:50:21.362 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 01:50:21.362 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 01:50:21.362 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 01:50:21.366 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 01:50:21.366 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 01:50:21.366 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 01:50:21.366 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 01:50:21.366 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.28.20:5700) Recv POWEROFF cmd
2026-01-29 01:50:21.366 [INFO] ctrl_if_trx.py:117 (BTS@172.18.28.20:5700) Stopping transceiver...
2026-01-29 01:50:21.366 [INFO] transceiver.py:246 Stopping clock generator
2026-01-29 01:50:21.367 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=4309 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 01:50:21.367 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=4309 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 01:50:21.367 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=4309 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 01:50:21.367 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=4309 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 01:50:21.367 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=4309 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 01:50:21.367 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=4309 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 01:50:21.367 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=4310 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 01:50:21.367 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=4310 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 01:50:21.368 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=4310 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 01:50:21.368 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=4310 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 01:50:21.368 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=4310 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 01:50:21.368 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=4310 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 01:50:21.368 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=4310 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 01:50:21.368 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=4310 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 01:50:26.365 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.28.20:5700) Recv POWEROFF cmd
2026-01-29 01:50:26.365 [INFO] ctrl_if_trx.py:117 (BTS@172.18.28.20:5700) Stopping transceiver...
2026-01-29 01:50:26.369 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 01:50:26.369 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 01:50:26.369 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 01:50:26.369 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 01:50:26.380 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 01:50:26.381 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.28.20:5700) Recv SETFORMAT cmd
2026-01-29 01:50:26.381 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.28.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 01:50:26.381 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.28.20:5700) Recv SETFORMAT cmd
2026-01-29 01:50:26.381 [INFO] ctrl_if_trx.py:201 (BTS@172.18.28.20:5700) TRXD header version 1 -> 1
2026-01-29 01:50:26.384 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.28.20:5700/1) Recv RXTUNE cmd
2026-01-29 01:50:26.384 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.28.20:5700/1) Recv TXTUNE cmd
2026-01-29 01:50:26.384 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.28.20:5700/1) Recv SETFORMAT cmd
2026-01-29 01:50:26.384 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.28.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 01:50:26.384 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 01:50:26.385 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.28.20:5700/1) Recv NOMTXPOWER cmd
2026-01-29 01:50:26.385 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.28.20:5700/1) Recv SETFORMAT cmd
2026-01-29 01:50:26.385 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.28.20:5700/1) TRXD header version 1 -> 1
2026-01-29 01:50:26.386 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.28.20:5700/2) Recv RXTUNE cmd
2026-01-29 01:50:26.386 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.28.20:5700/2) Recv TXTUNE cmd
2026-01-29 01:50:26.386 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.28.20:5700/2) Recv SETFORMAT cmd
2026-01-29 01:50:26.386 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.28.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 01:50:26.386 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 01:50:26.386 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.28.20:5700/2) Recv NOMTXPOWER cmd
2026-01-29 01:50:26.386 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.28.20:5700/2) Recv SETFORMAT cmd
2026-01-29 01:50:26.386 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.28.20:5700/2) TRXD header version 1 -> 1
2026-01-29 01:50:26.388 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.28.20:5700/3) Recv RXTUNE cmd
2026-01-29 01:50:26.388 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.28.20:5700/3) Recv TXTUNE cmd
2026-01-29 01:50:26.388 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.28.20:5700/3) Recv SETFORMAT cmd
2026-01-29 01:50:26.388 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.28.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 01:50:26.389 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 01:50:26.389 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.28.20:5700/3) Recv NOMTXPOWER cmd
2026-01-29 01:50:26.389 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.28.20:5700/3) Recv SETFORMAT cmd
2026-01-29 01:50:26.389 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.28.20:5700/3) TRXD header version 1 -> 1
2026-01-29 01:50:26.392 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.28.20:5700) Recv RXTUNE cmd
2026-01-29 01:50:26.393 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETTSC
2026-01-29 01:50:26.393 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETTSC
2026-01-29 01:50:26.393 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETTSC
2026-01-29 01:50:26.393 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.28.20:5700) Recv TXTUNE cmd
2026-01-29 01:50:26.393 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETRXGAIN
2026-01-29 01:50:26.393 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETRXGAIN
2026-01-29 01:50:26.393 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETRXGAIN
2026-01-29 01:50:26.393 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETTSC
2026-01-29 01:50:26.393 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:50:26.393 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:50:26.393 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:50:26.393 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.28.20:5700) Recv NOMTXPOWER cmd
2026-01-29 01:50:26.393 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:50:26.393 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:50:26.393 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:50:26.393 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.28.20:5700) Recv POWERON CMD
2026-01-29 01:50:26.393 [INFO] ctrl_if_trx.py:109 (BTS@172.18.28.20:5700) Starting transceiver...
2026-01-29 01:50:26.393 [INFO] transceiver.py:243 Starting clock generator
2026-01-29 01:50:26.394 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-01-29 01:50:26.394 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:50:26.394 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:50:26.394 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:50:26.394 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETRXGAIN
2026-01-29 01:50:26.394 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:50:26.395 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:50:26.395 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:50:26.395 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 01:50:26.395 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:50:26.395 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:50:26.395 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:50:26.395 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 01:50:26.395 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:50:26.396 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:50:26.396 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:50:26.396 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 01:50:26.396 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:50:26.396 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:50:26.396 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:50:26.396 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 01:50:26.396 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:50:26.396 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:50:26.396 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:50:26.396 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 01:50:26.396 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 01:50:26.396 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 01:50:26.397 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 01:50:26.398 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-01-29 01:50:26.882 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-01-29 01:50:26.921 [DEBUG] fake_trx.py:278 (BTS@172.18.28.20:5700) Recv FAKE_TOA cmd
2026-01-29 01:50:26.922 [DEBUG] fake_trx.py:297 (BTS@172.18.28.20:5700) Recv FAKE_RSSI cmd
2026-01-29 01:50:26.923 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:50:26.923 [DEBUG] fake_trx.py:322 (BTS@172.18.28.20:5700) Recv FAKE_CI cmd
2026-01-29 01:50:26.951 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 01:50:26.951 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 01:50:26.952 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 01:50:26.958 [DEBUG] fake_trx.py:297 (BTS@172.18.28.20:5700) Recv FAKE_RSSI cmd
2026-01-29 01:50:26.961 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 01:50:26.961 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 01:50:26.961 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 01:50:26.961 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.28.22:6700) Recv POWERON CMD
2026-01-29 01:50:26.961 [INFO] ctrl_if_trx.py:109 (MS@172.18.28.22:6700) Starting transceiver...
2026-01-29 01:50:26.978 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:50:26.983 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 01:50:26.983 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 01:50:26.983 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 01:50:26.983 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 01:50:27.360 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-01-29 01:50:27.398 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 01:50:27.400 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 01:50:27.400 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 01:50:27.403 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 01:50:27.838 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-01-29 01:50:27.854 [DEBUG] fake_trx.py:269 (MS@172.18.28.22:6700) Recv SETTA cmd
2026-01-29 01:50:28.315 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-01-29 01:50:28.399 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 01:50:28.400 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 01:50:28.400 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 01:50:28.403 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 01:50:28.793 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-01-29 01:50:28.828 [DEBUG] fake_trx.py:269 (MS@172.18.28.22:6700) Recv SETTA cmd
2026-01-29 01:50:29.271 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-01-29 01:50:29.400 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 01:50:29.401 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 01:50:29.401 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 01:50:29.404 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 01:50:29.749 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-01-29 01:50:29.802 [DEBUG] fake_trx.py:269 (MS@172.18.28.22:6700) Recv SETTA cmd
2026-01-29 01:50:30.227 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-01-29 01:50:30.401 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 01:50:30.402 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 01:50:30.402 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 01:50:30.405 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 01:50:30.705 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-01-29 01:50:30.776 [DEBUG] fake_trx.py:269 (MS@172.18.28.22:6700) Recv SETTA cmd
2026-01-29 01:50:31.183 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-01-29 01:50:31.403 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 01:50:31.403 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 01:50:31.403 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 01:50:31.406 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 01:50:31.660 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-01-29 01:50:31.750 [DEBUG] fake_trx.py:269 (MS@172.18.28.22:6700) Recv SETTA cmd
2026-01-29 01:50:32.138 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-01-29 01:50:32.615 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-01-29 01:50:32.723 [DEBUG] fake_trx.py:269 (MS@172.18.28.22:6700) Recv SETTA cmd
2026-01-29 01:50:33.093 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-01-29 01:50:33.570 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-01-29 01:50:33.697 [DEBUG] fake_trx.py:269 (MS@172.18.28.22:6700) Recv SETTA cmd
2026-01-29 01:50:34.048 [DEBUG] clck_gen.py:113 IND CLOCK 1632
2026-01-29 01:50:34.525 [DEBUG] clck_gen.py:113 IND CLOCK 1734
2026-01-29 01:50:34.670 [DEBUG] fake_trx.py:269 (MS@172.18.28.22:6700) Recv SETTA cmd
2026-01-29 01:50:35.003 [DEBUG] clck_gen.py:113 IND CLOCK 1836
2026-01-29 01:50:35.481 [DEBUG] clck_gen.py:113 IND CLOCK 1938
2026-01-29 01:50:35.644 [DEBUG] fake_trx.py:269 (MS@172.18.28.22:6700) Recv SETTA cmd
2026-01-29 01:50:35.959 [DEBUG] clck_gen.py:113 IND CLOCK 2040
2026-01-29 01:50:36.437 [DEBUG] clck_gen.py:113 IND CLOCK 2142
2026-01-29 01:50:36.619 [DEBUG] fake_trx.py:269 (MS@172.18.28.22:6700) Recv SETTA cmd
2026-01-29 01:50:36.914 [DEBUG] clck_gen.py:113 IND CLOCK 2244
2026-01-29 01:50:37.365 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:50:37.370 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 01:50:37.370 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 01:50:37.370 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 01:50:37.382 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 01:50:37.382 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 01:50:37.382 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 01:50:37.382 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 01:50:37.388 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 01:50:37.388 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 01:50:37.388 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 01:50:37.388 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 01:50:37.388 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.28.20:5700) Recv POWEROFF cmd
2026-01-29 01:50:37.388 [INFO] ctrl_if_trx.py:117 (BTS@172.18.28.20:5700) Stopping transceiver...
2026-01-29 01:50:37.389 [INFO] transceiver.py:246 Stopping clock generator
2026-01-29 01:50:37.389 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=2347 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 01:50:37.389 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=2347 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 01:50:42.387 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.28.20:5700) Recv POWEROFF cmd
2026-01-29 01:50:42.387 [INFO] ctrl_if_trx.py:117 (BTS@172.18.28.20:5700) Stopping transceiver...
2026-01-29 01:50:42.389 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 01:50:42.389 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 01:50:42.390 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 01:50:42.391 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 01:50:42.393 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 01:50:42.393 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.28.20:5700) Recv SETFORMAT cmd
2026-01-29 01:50:42.393 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.28.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 01:50:42.393 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.28.20:5700) Recv SETFORMAT cmd
2026-01-29 01:50:42.393 [INFO] ctrl_if_trx.py:201 (BTS@172.18.28.20:5700) TRXD header version 1 -> 1
2026-01-29 01:50:42.394 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.28.20:5700/1) Recv RXTUNE cmd
2026-01-29 01:50:42.394 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.28.20:5700/1) Recv TXTUNE cmd
2026-01-29 01:50:42.394 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.28.20:5700/1) Recv SETFORMAT cmd
2026-01-29 01:50:42.394 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.28.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 01:50:42.394 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 01:50:42.395 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.28.20:5700/1) Recv NOMTXPOWER cmd
2026-01-29 01:50:42.395 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.28.20:5700/1) Recv SETFORMAT cmd
2026-01-29 01:50:42.395 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.28.20:5700/1) TRXD header version 1 -> 1
2026-01-29 01:50:42.395 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.28.20:5700/2) Recv RXTUNE cmd
2026-01-29 01:50:42.395 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.28.20:5700/2) Recv TXTUNE cmd
2026-01-29 01:50:42.395 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.28.20:5700/2) Recv SETFORMAT cmd
2026-01-29 01:50:42.395 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.28.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 01:50:42.395 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 01:50:42.395 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.28.20:5700/2) Recv NOMTXPOWER cmd
2026-01-29 01:50:42.395 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.28.20:5700/2) Recv SETFORMAT cmd
2026-01-29 01:50:42.395 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.28.20:5700/2) TRXD header version 1 -> 1
2026-01-29 01:50:42.396 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.28.20:5700/3) Recv RXTUNE cmd
2026-01-29 01:50:42.396 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.28.20:5700/3) Recv TXTUNE cmd
2026-01-29 01:50:42.396 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.28.20:5700/3) Recv SETFORMAT cmd
2026-01-29 01:50:42.396 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.28.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 01:50:42.396 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 01:50:42.396 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.28.20:5700/3) Recv NOMTXPOWER cmd
2026-01-29 01:50:42.396 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.28.20:5700/3) Recv SETFORMAT cmd
2026-01-29 01:50:42.396 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.28.20:5700/3) TRXD header version 1 -> 1
2026-01-29 01:50:42.398 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.28.20:5700) Recv RXTUNE cmd
2026-01-29 01:50:42.398 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETTSC
2026-01-29 01:50:42.398 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETTSC
2026-01-29 01:50:42.398 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETTSC
2026-01-29 01:50:42.398 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.28.20:5700) Recv TXTUNE cmd
2026-01-29 01:50:42.398 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETRXGAIN
2026-01-29 01:50:42.398 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETRXGAIN
2026-01-29 01:50:42.398 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETRXGAIN
2026-01-29 01:50:42.398 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETTSC
2026-01-29 01:50:42.398 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:50:42.398 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:50:42.398 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:50:42.398 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.28.20:5700) Recv NOMTXPOWER cmd
2026-01-29 01:50:42.398 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:50:42.398 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:50:42.398 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:50:42.398 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.28.20:5700) Recv POWERON CMD
2026-01-29 01:50:42.398 [INFO] ctrl_if_trx.py:109 (BTS@172.18.28.20:5700) Starting transceiver...
2026-01-29 01:50:42.398 [INFO] transceiver.py:243 Starting clock generator
2026-01-29 01:50:42.398 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-01-29 01:50:42.398 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:50:42.398 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:50:42.398 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:50:42.398 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETRXGAIN
2026-01-29 01:50:42.398 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:50:42.398 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 01:50:42.398 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:50:42.398 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:50:42.398 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:50:42.399 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 01:50:42.399 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:50:42.399 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:50:42.399 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 01:50:42.399 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:50:42.399 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:50:42.399 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:50:42.399 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 01:50:42.399 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:50:42.399 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:50:42.399 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:50:42.399 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 01:50:42.399 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:50:42.399 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:50:42.399 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 01:50:42.399 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:50:42.399 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 01:50:42.399 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 01:50:42.403 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-01-29 01:50:42.886 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-01-29 01:50:42.923 [DEBUG] fake_trx.py:278 (BTS@172.18.28.20:5700) Recv FAKE_TOA cmd
2026-01-29 01:50:42.925 [DEBUG] fake_trx.py:297 (BTS@172.18.28.20:5700) Recv FAKE_RSSI cmd
2026-01-29 01:50:42.926 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:50:42.928 [DEBUG] fake_trx.py:322 (BTS@172.18.28.20:5700) Recv FAKE_CI cmd
2026-01-29 01:50:42.962 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 01:50:42.962 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 01:50:42.962 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 01:50:42.969 [DEBUG] fake_trx.py:297 (BTS@172.18.28.20:5700) Recv FAKE_RSSI cmd
2026-01-29 01:50:42.972 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 01:50:42.972 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 01:50:42.972 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 01:50:42.972 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.28.22:6700) Recv POWERON CMD
2026-01-29 01:50:42.972 [INFO] ctrl_if_trx.py:109 (MS@172.18.28.22:6700) Starting transceiver...
2026-01-29 01:50:42.980 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:50:42.983 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 01:50:42.983 [DEBUG] fake_trx.py:297 (BTS@172.18.28.20:5700) Recv FAKE_RSSI cmd
2026-01-29 01:50:42.983 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 01:50:42.983 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 01:50:42.983 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 01:50:43.363 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-01-29 01:50:43.401 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 01:50:43.401 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 01:50:43.402 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 01:50:43.402 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 01:50:43.842 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-01-29 01:50:43.858 [DEBUG] fake_trx.py:269 (MS@172.18.28.22:6700) Recv SETTA cmd
2026-01-29 01:50:43.859 [DEBUG] fake_trx.py:297 (BTS@172.18.28.20:5700) Recv FAKE_RSSI cmd
2026-01-29 01:50:44.320 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-01-29 01:50:44.402 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 01:50:44.402 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 01:50:44.402 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 01:50:44.403 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 01:50:44.798 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-01-29 01:50:45.276 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-01-29 01:50:45.403 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 01:50:45.404 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 01:50:45.404 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 01:50:45.404 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 01:50:45.754 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-01-29 01:50:46.231 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-01-29 01:50:46.404 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 01:50:46.404 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 01:50:46.404 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 01:50:46.404 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 01:50:46.709 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-01-29 01:50:47.187 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-01-29 01:50:47.405 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 01:50:47.405 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 01:50:47.405 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 01:50:47.405 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 01:50:47.665 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-01-29 01:50:48.143 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-01-29 01:50:48.621 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-01-29 01:50:49.099 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-01-29 01:50:49.578 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-01-29 01:50:49.706 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:50:49.709 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 01:50:49.710 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 01:50:49.710 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 01:50:49.718 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 01:50:49.718 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 01:50:49.718 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 01:50:49.718 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 01:50:49.719 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 01:50:49.719 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 01:50:49.719 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 01:50:49.719 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 01:50:49.719 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.28.20:5700) Recv POWEROFF cmd
2026-01-29 01:50:49.719 [INFO] ctrl_if_trx.py:117 (BTS@172.18.28.20:5700) Stopping transceiver...
2026-01-29 01:50:49.719 [INFO] transceiver.py:246 Stopping clock generator
2026-01-29 01:50:54.747 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.28.20:5700) Recv POWEROFF cmd
2026-01-29 01:50:54.748 [INFO] ctrl_if_trx.py:117 (BTS@172.18.28.20:5700) Stopping transceiver...
2026-01-29 01:50:54.749 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 01:50:54.750 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 01:50:54.751 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 01:50:54.752 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 01:50:54.758 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 01:50:54.759 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.28.20:5700) Recv SETFORMAT cmd
2026-01-29 01:50:54.759 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.28.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 01:50:54.759 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.28.20:5700) Recv SETFORMAT cmd
2026-01-29 01:50:54.759 [INFO] ctrl_if_trx.py:201 (BTS@172.18.28.20:5700) TRXD header version 1 -> 1
2026-01-29 01:50:54.761 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.28.20:5700/1) Recv RXTUNE cmd
2026-01-29 01:50:54.762 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.28.20:5700/1) Recv TXTUNE cmd
2026-01-29 01:50:54.762 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.28.20:5700/1) Recv SETFORMAT cmd
2026-01-29 01:50:54.762 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.28.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 01:50:54.763 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 01:50:54.763 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.28.20:5700/1) Recv NOMTXPOWER cmd
2026-01-29 01:50:54.764 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.28.20:5700/1) Recv SETFORMAT cmd
2026-01-29 01:50:54.764 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.28.20:5700/1) TRXD header version 1 -> 1
2026-01-29 01:50:54.764 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.28.20:5700/2) Recv RXTUNE cmd
2026-01-29 01:50:54.764 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.28.20:5700/2) Recv TXTUNE cmd
2026-01-29 01:50:54.764 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.28.20:5700/2) Recv SETFORMAT cmd
2026-01-29 01:50:54.765 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.28.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 01:50:54.765 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 01:50:54.765 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.28.20:5700/2) Recv NOMTXPOWER cmd
2026-01-29 01:50:54.765 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.28.20:5700/2) Recv SETFORMAT cmd
2026-01-29 01:50:54.765 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.28.20:5700/2) TRXD header version 1 -> 1
2026-01-29 01:50:54.767 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.28.20:5700/3) Recv RXTUNE cmd
2026-01-29 01:50:54.767 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.28.20:5700/3) Recv TXTUNE cmd
2026-01-29 01:50:54.767 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.28.20:5700/3) Recv SETFORMAT cmd
2026-01-29 01:50:54.767 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.28.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 01:50:54.767 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 01:50:54.767 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.28.20:5700/3) Recv NOMTXPOWER cmd
2026-01-29 01:50:54.767 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.28.20:5700/3) Recv SETFORMAT cmd
2026-01-29 01:50:54.767 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.28.20:5700/3) TRXD header version 1 -> 1
2026-01-29 01:50:54.770 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.28.20:5700) Recv RXTUNE cmd
2026-01-29 01:50:54.770 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETTSC
2026-01-29 01:50:54.770 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETTSC
2026-01-29 01:50:54.770 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETTSC
2026-01-29 01:50:54.770 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.28.20:5700) Recv TXTUNE cmd
2026-01-29 01:50:54.770 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETRXGAIN
2026-01-29 01:50:54.770 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETRXGAIN
2026-01-29 01:50:54.770 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETTSC
2026-01-29 01:50:54.770 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:50:54.770 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETRXGAIN
2026-01-29 01:50:54.770 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.28.20:5700) Recv NOMTXPOWER cmd
2026-01-29 01:50:54.770 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:50:54.770 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:50:54.770 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:50:54.770 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.28.20:5700) Recv POWERON CMD
2026-01-29 01:50:54.770 [INFO] ctrl_if_trx.py:109 (BTS@172.18.28.20:5700) Starting transceiver...
2026-01-29 01:50:54.770 [INFO] transceiver.py:243 Starting clock generator
2026-01-29 01:50:54.770 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-01-29 01:50:54.770 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:50:54.770 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:50:54.771 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:50:54.771 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETRXGAIN
2026-01-29 01:50:54.771 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:50:54.771 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:50:54.771 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:50:54.771 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 01:50:54.771 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:50:54.771 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:50:54.771 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:50:54.771 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 01:50:54.771 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:50:54.771 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:50:54.771 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:50:54.771 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 01:50:54.771 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:50:54.771 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:50:54.771 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:50:54.771 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 01:50:54.771 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:50:54.771 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:50:54.771 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:50:54.771 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 01:50:54.771 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:50:54.771 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 01:50:54.771 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:50:54.771 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 01:50:54.771 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 01:50:54.775 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-01-29 01:50:55.259 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-01-29 01:50:55.297 [DEBUG] fake_trx.py:278 (BTS@172.18.28.20:5700) Recv FAKE_TOA cmd
2026-01-29 01:50:55.298 [DEBUG] fake_trx.py:297 (BTS@172.18.28.20:5700) Recv FAKE_RSSI cmd
2026-01-29 01:50:55.299 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:50:55.299 [DEBUG] fake_trx.py:322 (BTS@172.18.28.20:5700) Recv FAKE_CI cmd
2026-01-29 01:50:55.331 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 01:50:55.331 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 01:50:55.332 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 01:50:55.338 [DEBUG] fake_trx.py:297 (BTS@172.18.28.20:5700) Recv FAKE_RSSI cmd
2026-01-29 01:50:55.340 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 01:50:55.340 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 01:50:55.341 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 01:50:55.341 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.28.22:6700) Recv POWERON CMD
2026-01-29 01:50:55.341 [INFO] ctrl_if_trx.py:109 (MS@172.18.28.22:6700) Starting transceiver...
2026-01-29 01:50:55.354 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:50:55.357 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 01:50:55.357 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 01:50:55.357 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 01:50:55.357 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 01:50:55.736 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-01-29 01:50:55.774 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 01:50:55.774 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 01:50:55.774 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 01:50:55.775 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 01:50:56.214 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-01-29 01:50:56.230 [DEBUG] fake_trx.py:269 (MS@172.18.28.22:6700) Recv SETTA cmd
2026-01-29 01:50:56.691 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-01-29 01:50:56.774 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 01:50:56.775 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 01:50:56.775 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 01:50:56.775 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 01:50:57.169 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-01-29 01:50:57.647 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-01-29 01:50:57.775 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 01:50:57.775 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 01:50:57.776 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 01:50:57.776 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 01:50:58.125 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-01-29 01:50:58.603 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-01-29 01:50:58.776 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 01:50:58.776 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 01:50:58.776 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 01:50:58.776 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 01:50:59.082 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-01-29 01:50:59.559 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-01-29 01:50:59.776 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 01:50:59.777 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 01:50:59.777 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 01:50:59.777 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 01:51:00.037 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-01-29 01:51:00.515 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-01-29 01:51:00.993 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-01-29 01:51:01.471 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-01-29 01:51:01.949 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-01-29 01:51:02.427 [DEBUG] clck_gen.py:113 IND CLOCK 1632
2026-01-29 01:51:02.905 [DEBUG] clck_gen.py:113 IND CLOCK 1734
2026-01-29 01:51:03.383 [DEBUG] clck_gen.py:113 IND CLOCK 1836
2026-01-29 01:51:03.861 [DEBUG] clck_gen.py:113 IND CLOCK 1938
2026-01-29 01:51:04.339 [DEBUG] clck_gen.py:113 IND CLOCK 2040
2026-01-29 01:51:04.817 [DEBUG] clck_gen.py:113 IND CLOCK 2142
2026-01-29 01:51:05.295 [DEBUG] clck_gen.py:113 IND CLOCK 2244
2026-01-29 01:51:05.359 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:51:05.363 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 01:51:05.363 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 01:51:05.363 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 01:51:05.377 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 01:51:05.377 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 01:51:05.377 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 01:51:05.377 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 01:51:05.379 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 01:51:05.379 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 01:51:05.379 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 01:51:05.379 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 01:51:05.379 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.28.20:5700) Recv POWEROFF cmd
2026-01-29 01:51:05.379 [INFO] ctrl_if_trx.py:117 (BTS@172.18.28.20:5700) Stopping transceiver...
2026-01-29 01:51:05.379 [INFO] transceiver.py:246 Stopping clock generator
2026-01-29 01:51:05.380 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=2263 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 01:51:05.380 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=2263 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 01:51:05.380 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=2263 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 01:51:05.380 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=2263 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 01:51:05.380 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=2263 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 01:51:05.380 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=2263 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 01:51:05.380 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=2264 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 01:51:05.380 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=2264 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 01:51:05.380 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=2264 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 01:51:05.380 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=2264 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 01:51:05.380 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=2264 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 01:51:05.380 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=2264 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 01:51:05.380 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=2264 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 01:51:05.380 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=2264 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 01:51:10.382 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.28.20:5700) Recv POWEROFF cmd
2026-01-29 01:51:10.382 [INFO] ctrl_if_trx.py:117 (BTS@172.18.28.20:5700) Stopping transceiver...
2026-01-29 01:51:10.384 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 01:51:10.384 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 01:51:10.385 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 01:51:10.385 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 01:51:10.388 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 01:51:10.389 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.28.20:5700) Recv SETFORMAT cmd
2026-01-29 01:51:10.389 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.28.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 01:51:10.389 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.28.20:5700) Recv SETFORMAT cmd
2026-01-29 01:51:10.389 [INFO] ctrl_if_trx.py:201 (BTS@172.18.28.20:5700) TRXD header version 1 -> 1
2026-01-29 01:51:10.392 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.28.20:5700/1) Recv RXTUNE cmd
2026-01-29 01:51:10.392 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.28.20:5700/1) Recv TXTUNE cmd
2026-01-29 01:51:10.392 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.28.20:5700/1) Recv SETFORMAT cmd
2026-01-29 01:51:10.392 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.28.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 01:51:10.392 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 01:51:10.392 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.28.20:5700/1) Recv NOMTXPOWER cmd
2026-01-29 01:51:10.392 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.28.20:5700/1) Recv SETFORMAT cmd
2026-01-29 01:51:10.392 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.28.20:5700/1) TRXD header version 1 -> 1
2026-01-29 01:51:10.394 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.28.20:5700/2) Recv RXTUNE cmd
2026-01-29 01:51:10.394 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.28.20:5700/2) Recv TXTUNE cmd
2026-01-29 01:51:10.394 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.28.20:5700/2) Recv SETFORMAT cmd
2026-01-29 01:51:10.394 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.28.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 01:51:10.394 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 01:51:10.394 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.28.20:5700/2) Recv NOMTXPOWER cmd
2026-01-29 01:51:10.394 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.28.20:5700/2) Recv SETFORMAT cmd
2026-01-29 01:51:10.394 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.28.20:5700/2) TRXD header version 1 -> 1
2026-01-29 01:51:10.396 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.28.20:5700/3) Recv RXTUNE cmd
2026-01-29 01:51:10.396 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.28.20:5700/3) Recv TXTUNE cmd
2026-01-29 01:51:10.396 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.28.20:5700/3) Recv SETFORMAT cmd
2026-01-29 01:51:10.396 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.28.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 01:51:10.396 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 01:51:10.396 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.28.20:5700/3) Recv NOMTXPOWER cmd
2026-01-29 01:51:10.396 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.28.20:5700/3) Recv SETFORMAT cmd
2026-01-29 01:51:10.396 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.28.20:5700/3) TRXD header version 1 -> 1
2026-01-29 01:51:10.398 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.28.20:5700) Recv RXTUNE cmd
2026-01-29 01:51:10.398 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETTSC
2026-01-29 01:51:10.398 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETTSC
2026-01-29 01:51:10.398 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETTSC
2026-01-29 01:51:10.398 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.28.20:5700) Recv TXTUNE cmd
2026-01-29 01:51:10.398 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETRXGAIN
2026-01-29 01:51:10.398 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETRXGAIN
2026-01-29 01:51:10.398 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETRXGAIN
2026-01-29 01:51:10.398 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETTSC
2026-01-29 01:51:10.398 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:51:10.398 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:51:10.398 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:51:10.398 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.28.20:5700) Recv NOMTXPOWER cmd
2026-01-29 01:51:10.398 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:51:10.398 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:51:10.398 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:51:10.398 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.28.20:5700) Recv POWERON CMD
2026-01-29 01:51:10.398 [INFO] ctrl_if_trx.py:109 (BTS@172.18.28.20:5700) Starting transceiver...
2026-01-29 01:51:10.398 [INFO] transceiver.py:243 Starting clock generator
2026-01-29 01:51:10.398 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-01-29 01:51:10.399 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:51:10.399 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:51:10.399 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:51:10.399 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETRXGAIN
2026-01-29 01:51:10.399 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:51:10.399 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:51:10.399 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 01:51:10.399 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:51:10.399 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:51:10.399 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:51:10.399 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 01:51:10.399 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:51:10.399 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:51:10.399 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:51:10.399 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 01:51:10.399 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:51:10.399 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:51:10.399 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:51:10.399 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 01:51:10.399 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:51:10.399 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:51:10.399 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:51:10.399 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 01:51:10.399 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:51:10.399 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 01:51:10.399 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 01:51:10.399 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 01:51:10.403 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-01-29 01:51:10.887 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-01-29 01:51:10.927 [DEBUG] fake_trx.py:278 (BTS@172.18.28.20:5700) Recv FAKE_TOA cmd
2026-01-29 01:51:10.929 [DEBUG] fake_trx.py:297 (BTS@172.18.28.20:5700) Recv FAKE_RSSI cmd
2026-01-29 01:51:10.930 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:51:10.931 [DEBUG] fake_trx.py:322 (BTS@172.18.28.20:5700) Recv FAKE_CI cmd
2026-01-29 01:51:10.952 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 01:51:10.953 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 01:51:10.953 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 01:51:10.957 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 01:51:10.958 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 01:51:10.958 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 01:51:10.958 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.28.22:6700) Recv POWERON CMD
2026-01-29 01:51:10.958 [INFO] ctrl_if_trx.py:109 (MS@172.18.28.22:6700) Starting transceiver...
2026-01-29 01:51:10.984 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:51:10.990 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 01:51:10.990 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 01:51:10.991 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 01:51:10.991 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 01:51:11.365 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-01-29 01:51:11.368 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:51:11.370 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 01:51:11.371 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 01:51:11.371 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 01:51:11.389 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 01:51:11.389 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 01:51:11.389 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 01:51:11.391 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 01:51:11.391 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 01:51:11.391 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 01:51:11.391 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.28.22:6700) Recv POWERON CMD
2026-01-29 01:51:11.391 [INFO] ctrl_if_trx.py:109 (MS@172.18.28.22:6700) Starting transceiver...
2026-01-29 01:51:11.401 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 01:51:11.401 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 01:51:11.402 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 01:51:11.404 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 01:51:11.411 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:51:11.416 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 01:51:11.416 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 01:51:11.416 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 01:51:11.417 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 01:51:11.843 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-01-29 01:51:12.103 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:51:12.106 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 01:51:12.107 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 01:51:12.107 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 01:51:12.125 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 01:51:12.125 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 01:51:12.125 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 01:51:12.126 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 01:51:12.127 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 01:51:12.127 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 01:51:12.127 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.28.22:6700) Recv POWERON CMD
2026-01-29 01:51:12.127 [INFO] ctrl_if_trx.py:109 (MS@172.18.28.22:6700) Starting transceiver...
2026-01-29 01:51:12.173 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:51:12.178 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 01:51:12.179 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 01:51:12.179 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 01:51:12.179 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 01:51:12.281 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:51:12.284 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 01:51:12.284 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 01:51:12.285 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 01:51:12.306 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 01:51:12.307 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 01:51:12.307 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 01:51:12.308 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 01:51:12.309 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 01:51:12.309 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 01:51:12.309 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.28.22:6700) Recv POWERON CMD
2026-01-29 01:51:12.309 [INFO] ctrl_if_trx.py:109 (MS@172.18.28.22:6700) Starting transceiver...
2026-01-29 01:51:12.311 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:51:12.312 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 01:51:12.312 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 01:51:12.312 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 01:51:12.312 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 01:51:12.320 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-01-29 01:51:12.402 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 01:51:12.402 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 01:51:12.402 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 01:51:12.404 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 01:51:12.712 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:51:12.715 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 01:51:12.716 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 01:51:12.716 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 01:51:12.723 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 01:51:12.723 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 01:51:12.723 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 01:51:12.723 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 01:51:12.724 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 01:51:12.724 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 01:51:12.724 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 01:51:12.724 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.28.20:5700) Recv POWEROFF cmd
2026-01-29 01:51:12.724 [INFO] ctrl_if_trx.py:117 (BTS@172.18.28.20:5700) Stopping transceiver...
2026-01-29 01:51:12.724 [INFO] transceiver.py:246 Stopping clock generator
2026-01-29 01:51:12.724 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 01:51:17.726 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.28.20:5700) Recv POWEROFF cmd
2026-01-29 01:51:17.726 [INFO] ctrl_if_trx.py:117 (BTS@172.18.28.20:5700) Stopping transceiver...
2026-01-29 01:51:17.728 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 01:51:17.729 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 01:51:17.730 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 01:51:17.730 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 01:51:17.739 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 01:51:17.740 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.28.20:5700) Recv SETFORMAT cmd
2026-01-29 01:51:17.741 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.28.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 01:51:17.741 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.28.20:5700) Recv SETFORMAT cmd
2026-01-29 01:51:17.741 [INFO] ctrl_if_trx.py:201 (BTS@172.18.28.20:5700) TRXD header version 1 -> 1
2026-01-29 01:51:17.745 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.28.20:5700/1) Recv RXTUNE cmd
2026-01-29 01:51:17.745 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.28.20:5700/1) Recv TXTUNE cmd
2026-01-29 01:51:17.745 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.28.20:5700/1) Recv SETFORMAT cmd
2026-01-29 01:51:17.745 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.28.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 01:51:17.745 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 01:51:17.745 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.28.20:5700/1) Recv NOMTXPOWER cmd
2026-01-29 01:51:17.745 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.28.20:5700/1) Recv SETFORMAT cmd
2026-01-29 01:51:17.745 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.28.20:5700/1) TRXD header version 1 -> 1
2026-01-29 01:51:17.748 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.28.20:5700/2) Recv RXTUNE cmd
2026-01-29 01:51:17.748 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.28.20:5700/2) Recv TXTUNE cmd
2026-01-29 01:51:17.748 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.28.20:5700/2) Recv SETFORMAT cmd
2026-01-29 01:51:17.748 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.28.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 01:51:17.748 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 01:51:17.748 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.28.20:5700/2) Recv NOMTXPOWER cmd
2026-01-29 01:51:17.748 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.28.20:5700/2) Recv SETFORMAT cmd
2026-01-29 01:51:17.748 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.28.20:5700/2) TRXD header version 1 -> 1
2026-01-29 01:51:17.750 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.28.20:5700/3) Recv RXTUNE cmd
2026-01-29 01:51:17.750 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.28.20:5700/3) Recv TXTUNE cmd
2026-01-29 01:51:17.750 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.28.20:5700/3) Recv SETFORMAT cmd
2026-01-29 01:51:17.750 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.28.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 01:51:17.750 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 01:51:17.750 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.28.20:5700/3) Recv NOMTXPOWER cmd
2026-01-29 01:51:17.750 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.28.20:5700/3) Recv SETFORMAT cmd
2026-01-29 01:51:17.750 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.28.20:5700/3) TRXD header version 1 -> 1
2026-01-29 01:51:17.753 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.28.20:5700) Recv RXTUNE cmd
2026-01-29 01:51:17.753 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETTSC
2026-01-29 01:51:17.753 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETTSC
2026-01-29 01:51:17.753 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETTSC
2026-01-29 01:51:17.753 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.28.20:5700) Recv TXTUNE cmd
2026-01-29 01:51:17.753 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETRXGAIN
2026-01-29 01:51:17.753 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETRXGAIN
2026-01-29 01:51:17.753 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETRXGAIN
2026-01-29 01:51:17.753 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETTSC
2026-01-29 01:51:17.753 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:51:17.753 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:51:17.753 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:51:17.753 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.28.20:5700) Recv NOMTXPOWER cmd
2026-01-29 01:51:17.753 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:51:17.753 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:51:17.753 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:51:17.753 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.28.20:5700) Recv POWERON CMD
2026-01-29 01:51:17.754 [INFO] ctrl_if_trx.py:109 (BTS@172.18.28.20:5700) Starting transceiver...
2026-01-29 01:51:17.754 [INFO] transceiver.py:243 Starting clock generator
2026-01-29 01:51:17.754 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-01-29 01:51:17.754 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:51:17.754 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:51:17.754 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:51:17.754 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETRXGAIN
2026-01-29 01:51:17.754 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:51:17.754 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:51:17.754 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 01:51:17.754 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:51:17.754 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:51:17.754 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:51:17.754 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 01:51:17.754 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:51:17.754 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:51:17.754 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:51:17.754 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 01:51:17.754 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:51:17.754 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:51:17.755 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:51:17.755 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 01:51:17.755 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:51:17.755 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 01:51:17.755 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:51:17.755 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:51:17.755 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 01:51:17.755 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:51:17.755 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 01:51:17.755 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 01:51:17.758 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-01-29 01:51:18.242 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-01-29 01:51:18.279 [DEBUG] fake_trx.py:278 (BTS@172.18.28.20:5700) Recv FAKE_TOA cmd
2026-01-29 01:51:18.281 [DEBUG] fake_trx.py:297 (BTS@172.18.28.20:5700) Recv FAKE_RSSI cmd
2026-01-29 01:51:18.282 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:51:18.282 [DEBUG] fake_trx.py:322 (BTS@172.18.28.20:5700) Recv FAKE_CI cmd
2026-01-29 01:51:18.305 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 01:51:18.305 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 01:51:18.305 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 01:51:18.311 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 01:51:18.311 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 01:51:18.312 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 01:51:18.312 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.28.22:6700) Recv POWERON CMD
2026-01-29 01:51:18.312 [INFO] ctrl_if_trx.py:109 (MS@172.18.28.22:6700) Starting transceiver...
2026-01-29 01:51:18.334 [DEBUG] fake_trx.py:278 (BTS@172.18.28.20:5700) Recv FAKE_TOA cmd
2026-01-29 01:51:18.338 [DEBUG] fake_trx.py:269 (MS@172.18.28.22:6700) Recv SETTA cmd
2026-01-29 01:51:18.346 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:51:18.350 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 01:51:18.350 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 01:51:18.350 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 01:51:18.350 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 01:51:18.719 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-01-29 01:51:18.756 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 01:51:18.756 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 01:51:18.758 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 01:51:18.760 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 01:51:19.197 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-01-29 01:51:19.215 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:51:19.217 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 01:51:19.218 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 01:51:19.218 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 01:51:19.227 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 01:51:19.227 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 01:51:19.227 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 01:51:19.227 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 01:51:19.230 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 01:51:19.230 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 01:51:19.230 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 01:51:19.230 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 01:51:19.230 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.28.20:5700) Recv POWEROFF cmd
2026-01-29 01:51:19.230 [INFO] ctrl_if_trx.py:117 (BTS@172.18.28.20:5700) Stopping transceiver...
2026-01-29 01:51:19.230 [INFO] transceiver.py:246 Stopping clock generator
2026-01-29 01:51:19.230 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=314 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 01:51:19.230 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=314 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 01:51:19.230 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=314 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 01:51:19.230 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=314 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 01:51:19.230 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=314 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 01:51:19.230 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=314 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 01:51:19.230 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=314 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 01:51:19.230 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=315 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 01:51:19.230 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=315 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 01:51:19.230 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=315 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 01:51:19.230 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=315 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 01:51:19.230 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=315 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 01:51:19.230 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=315 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 01:51:19.230 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=315 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 01:51:19.230 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=315 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 01:51:24.232 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.28.20:5700) Recv POWEROFF cmd
2026-01-29 01:51:24.232 [INFO] ctrl_if_trx.py:117 (BTS@172.18.28.20:5700) Stopping transceiver...
2026-01-29 01:51:24.234 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 01:51:24.236 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 01:51:24.236 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 01:51:24.236 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 01:51:24.238 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 01:51:24.239 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.28.20:5700) Recv SETFORMAT cmd
2026-01-29 01:51:24.239 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.28.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 01:51:24.239 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.28.20:5700) Recv SETFORMAT cmd
2026-01-29 01:51:24.239 [INFO] ctrl_if_trx.py:201 (BTS@172.18.28.20:5700) TRXD header version 1 -> 1
2026-01-29 01:51:24.240 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.28.20:5700/1) Recv RXTUNE cmd
2026-01-29 01:51:24.240 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.28.20:5700/1) Recv TXTUNE cmd
2026-01-29 01:51:24.240 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.28.20:5700/1) Recv SETFORMAT cmd
2026-01-29 01:51:24.240 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.28.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 01:51:24.240 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 01:51:24.240 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.28.20:5700/1) Recv NOMTXPOWER cmd
2026-01-29 01:51:24.241 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.28.20:5700/1) Recv SETFORMAT cmd
2026-01-29 01:51:24.241 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.28.20:5700/1) TRXD header version 1 -> 1
2026-01-29 01:51:24.241 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.28.20:5700/2) Recv RXTUNE cmd
2026-01-29 01:51:24.241 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.28.20:5700/2) Recv TXTUNE cmd
2026-01-29 01:51:24.241 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.28.20:5700/2) Recv SETFORMAT cmd
2026-01-29 01:51:24.241 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.28.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 01:51:24.241 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 01:51:24.241 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.28.20:5700/2) Recv NOMTXPOWER cmd
2026-01-29 01:51:24.241 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.28.20:5700/2) Recv SETFORMAT cmd
2026-01-29 01:51:24.241 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.28.20:5700/2) TRXD header version 1 -> 1
2026-01-29 01:51:24.242 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.28.20:5700/3) Recv RXTUNE cmd
2026-01-29 01:51:24.242 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.28.20:5700/3) Recv TXTUNE cmd
2026-01-29 01:51:24.242 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.28.20:5700/3) Recv SETFORMAT cmd
2026-01-29 01:51:24.242 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.28.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 01:51:24.242 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 01:51:24.242 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.28.20:5700/3) Recv NOMTXPOWER cmd
2026-01-29 01:51:24.242 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.28.20:5700/3) Recv SETFORMAT cmd
2026-01-29 01:51:24.242 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.28.20:5700/3) TRXD header version 1 -> 1
2026-01-29 01:51:24.244 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.28.20:5700) Recv RXTUNE cmd
2026-01-29 01:51:24.244 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETTSC
2026-01-29 01:51:24.244 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETTSC
2026-01-29 01:51:24.244 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETTSC
2026-01-29 01:51:24.244 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.28.20:5700) Recv TXTUNE cmd
2026-01-29 01:51:24.244 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETRXGAIN
2026-01-29 01:51:24.244 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETRXGAIN
2026-01-29 01:51:24.244 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETRXGAIN
2026-01-29 01:51:24.244 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETTSC
2026-01-29 01:51:24.244 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:51:24.244 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:51:24.244 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:51:24.244 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.28.20:5700) Recv NOMTXPOWER cmd
2026-01-29 01:51:24.244 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:51:24.244 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:51:24.244 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:51:24.244 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.28.20:5700) Recv POWERON CMD
2026-01-29 01:51:24.244 [INFO] ctrl_if_trx.py:109 (BTS@172.18.28.20:5700) Starting transceiver...
2026-01-29 01:51:24.244 [INFO] transceiver.py:243 Starting clock generator
2026-01-29 01:51:24.244 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-01-29 01:51:24.244 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:51:24.244 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:51:24.244 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:51:24.244 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETRXGAIN
2026-01-29 01:51:24.244 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:51:24.244 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:51:24.244 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:51:24.244 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 01:51:24.244 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:51:24.244 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:51:24.244 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:51:24.244 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 01:51:24.245 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:51:24.245 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:51:24.245 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:51:24.245 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 01:51:24.245 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:51:24.245 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:51:24.245 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:51:24.245 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 01:51:24.245 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:51:24.245 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:51:24.245 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:51:24.245 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 01:51:24.245 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 01:51:24.245 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 01:51:24.245 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 01:51:24.249 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-01-29 01:51:24.732 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-01-29 01:51:24.765 [DEBUG] fake_trx.py:278 (BTS@172.18.28.20:5700) Recv FAKE_TOA cmd
2026-01-29 01:51:24.766 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:51:24.767 [DEBUG] fake_trx.py:297 (BTS@172.18.28.20:5700) Recv FAKE_RSSI cmd
2026-01-29 01:51:24.768 [DEBUG] fake_trx.py:322 (BTS@172.18.28.20:5700) Recv FAKE_CI cmd
2026-01-29 01:51:24.789 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 01:51:24.789 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 01:51:24.790 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 01:51:24.795 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 01:51:24.795 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 01:51:24.795 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 01:51:24.795 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.28.22:6700) Recv POWERON CMD
2026-01-29 01:51:24.795 [INFO] ctrl_if_trx.py:109 (MS@172.18.28.22:6700) Starting transceiver...
2026-01-29 01:51:24.829 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:51:24.835 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 01:51:24.835 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 01:51:24.836 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 01:51:24.836 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 01:51:24.933 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:51:25.206 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-01-29 01:51:25.246 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 01:51:25.247 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 01:51:25.248 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 01:51:25.250 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 01:51:25.684 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-01-29 01:51:26.162 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-01-29 01:51:26.247 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 01:51:26.247 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 01:51:26.250 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 01:51:26.250 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 01:51:26.640 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-01-29 01:51:27.118 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-01-29 01:51:27.248 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 01:51:27.248 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 01:51:27.251 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 01:51:27.251 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 01:51:27.596 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-01-29 01:51:27.938 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:51:27.942 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 01:51:27.944 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 01:51:27.944 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 01:51:27.964 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 01:51:27.964 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 01:51:27.965 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 01:51:27.966 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 01:51:27.966 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 01:51:27.966 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 01:51:27.966 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.28.22:6700) Recv POWERON CMD
2026-01-29 01:51:27.966 [INFO] ctrl_if_trx.py:109 (MS@172.18.28.22:6700) Starting transceiver...
2026-01-29 01:51:28.021 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:51:28.027 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 01:51:28.027 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 01:51:28.027 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 01:51:28.028 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 01:51:28.074 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-01-29 01:51:28.196 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:51:28.248 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 01:51:28.249 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 01:51:28.251 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 01:51:28.252 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 01:51:28.552 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-01-29 01:51:29.030 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-01-29 01:51:29.249 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 01:51:29.250 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 01:51:29.252 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 01:51:29.253 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 01:51:29.509 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-01-29 01:51:29.988 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-01-29 01:51:30.466 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-01-29 01:51:30.943 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-01-29 01:51:31.201 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:51:31.204 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 01:51:31.206 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 01:51:31.206 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 01:51:31.235 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 01:51:31.235 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 01:51:31.236 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 01:51:31.237 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 01:51:31.237 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 01:51:31.237 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 01:51:31.237 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.28.22:6700) Recv POWERON CMD
2026-01-29 01:51:31.237 [INFO] ctrl_if_trx.py:109 (MS@172.18.28.22:6700) Starting transceiver...
2026-01-29 01:51:31.274 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:51:31.279 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 01:51:31.280 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 01:51:31.280 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 01:51:31.281 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 01:51:31.407 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:51:31.421 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-01-29 01:51:31.898 [DEBUG] clck_gen.py:113 IND CLOCK 1632
2026-01-29 01:51:32.376 [DEBUG] clck_gen.py:113 IND CLOCK 1734
2026-01-29 01:51:32.853 [DEBUG] clck_gen.py:113 IND CLOCK 1836
2026-01-29 01:51:33.330 [DEBUG] clck_gen.py:113 IND CLOCK 1938
2026-01-29 01:51:33.808 [DEBUG] clck_gen.py:113 IND CLOCK 2040
2026-01-29 01:51:34.286 [DEBUG] clck_gen.py:113 IND CLOCK 2142
2026-01-29 01:51:34.412 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:51:34.415 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 01:51:34.416 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 01:51:34.416 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 01:51:34.435 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 01:51:34.435 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 01:51:34.436 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 01:51:34.437 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 01:51:34.437 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 01:51:34.437 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 01:51:34.437 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.28.22:6700) Recv POWERON CMD
2026-01-29 01:51:34.437 [INFO] ctrl_if_trx.py:109 (MS@172.18.28.22:6700) Starting transceiver...
2026-01-29 01:51:34.473 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:51:34.479 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 01:51:34.479 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 01:51:34.479 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 01:51:34.480 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 01:51:34.676 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:51:34.762 [DEBUG] clck_gen.py:113 IND CLOCK 2244
2026-01-29 01:51:35.239 [DEBUG] clck_gen.py:113 IND CLOCK 2346
2026-01-29 01:51:35.717 [DEBUG] clck_gen.py:113 IND CLOCK 2448
2026-01-29 01:51:36.195 [DEBUG] clck_gen.py:113 IND CLOCK 2550
2026-01-29 01:51:36.673 [DEBUG] clck_gen.py:113 IND CLOCK 2652
2026-01-29 01:51:37.151 [DEBUG] clck_gen.py:113 IND CLOCK 2754
2026-01-29 01:51:37.628 [DEBUG] clck_gen.py:113 IND CLOCK 2856
2026-01-29 01:51:37.681 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:51:37.684 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 01:51:37.685 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 01:51:37.685 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 01:51:37.697 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 01:51:37.697 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 01:51:37.697 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 01:51:37.697 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 01:51:37.703 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 01:51:37.703 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 01:51:37.703 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 01:51:37.703 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.28.20:5700) Recv POWEROFF cmd
2026-01-29 01:51:37.704 [INFO] ctrl_if_trx.py:117 (BTS@172.18.28.20:5700) Stopping transceiver...
2026-01-29 01:51:37.704 [INFO] transceiver.py:246 Stopping clock generator
2026-01-29 01:51:37.704 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 01:51:37.704 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=2872 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 01:51:37.704 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=2872 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 01:51:42.701 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.28.20:5700) Recv POWEROFF cmd
2026-01-29 01:51:42.701 [INFO] ctrl_if_trx.py:117 (BTS@172.18.28.20:5700) Stopping transceiver...
2026-01-29 01:51:42.703 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 01:51:42.704 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 01:51:42.704 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 01:51:42.704 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 01:51:42.709 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 01:51:42.710 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.28.20:5700) Recv SETFORMAT cmd
2026-01-29 01:51:42.710 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.28.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 01:51:42.710 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.28.20:5700) Recv SETFORMAT cmd
2026-01-29 01:51:42.710 [INFO] ctrl_if_trx.py:201 (BTS@172.18.28.20:5700) TRXD header version 1 -> 1
2026-01-29 01:51:42.711 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.28.20:5700/1) Recv RXTUNE cmd
2026-01-29 01:51:42.712 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.28.20:5700/1) Recv TXTUNE cmd
2026-01-29 01:51:42.712 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.28.20:5700/1) Recv SETFORMAT cmd
2026-01-29 01:51:42.712 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.28.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 01:51:42.712 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 01:51:42.712 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.28.20:5700/1) Recv NOMTXPOWER cmd
2026-01-29 01:51:42.712 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.28.20:5700/1) Recv SETFORMAT cmd
2026-01-29 01:51:42.712 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.28.20:5700/1) TRXD header version 1 -> 1
2026-01-29 01:51:42.714 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.28.20:5700/2) Recv RXTUNE cmd
2026-01-29 01:51:42.714 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.28.20:5700/2) Recv TXTUNE cmd
2026-01-29 01:51:42.714 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.28.20:5700/2) Recv SETFORMAT cmd
2026-01-29 01:51:42.714 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.28.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 01:51:42.714 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 01:51:42.714 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.28.20:5700/2) Recv NOMTXPOWER cmd
2026-01-29 01:51:42.715 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.28.20:5700/2) Recv SETFORMAT cmd
2026-01-29 01:51:42.715 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.28.20:5700/2) TRXD header version 1 -> 1
2026-01-29 01:51:42.717 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.28.20:5700/3) Recv RXTUNE cmd
2026-01-29 01:51:42.717 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.28.20:5700/3) Recv TXTUNE cmd
2026-01-29 01:51:42.717 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.28.20:5700/3) Recv SETFORMAT cmd
2026-01-29 01:51:42.717 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.28.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 01:51:42.717 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 01:51:42.717 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.28.20:5700/3) Recv NOMTXPOWER cmd
2026-01-29 01:51:42.717 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.28.20:5700/3) Recv SETFORMAT cmd
2026-01-29 01:51:42.717 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.28.20:5700/3) TRXD header version 1 -> 1
2026-01-29 01:51:42.719 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.28.20:5700) Recv RXTUNE cmd
2026-01-29 01:51:42.719 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETTSC
2026-01-29 01:51:42.719 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETTSC
2026-01-29 01:51:42.719 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETTSC
2026-01-29 01:51:42.720 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.28.20:5700) Recv TXTUNE cmd
2026-01-29 01:51:42.720 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETRXGAIN
2026-01-29 01:51:42.720 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETRXGAIN
2026-01-29 01:51:42.720 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETRXGAIN
2026-01-29 01:51:42.720 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETTSC
2026-01-29 01:51:42.720 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:51:42.720 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:51:42.720 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:51:42.720 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.28.20:5700) Recv NOMTXPOWER cmd
2026-01-29 01:51:42.720 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:51:42.720 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:51:42.720 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:51:42.720 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.28.20:5700) Recv POWERON CMD
2026-01-29 01:51:42.720 [INFO] ctrl_if_trx.py:109 (BTS@172.18.28.20:5700) Starting transceiver...
2026-01-29 01:51:42.720 [INFO] transceiver.py:243 Starting clock generator
2026-01-29 01:51:42.720 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-01-29 01:51:42.720 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:51:42.721 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:51:42.721 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:51:42.721 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETRXGAIN
2026-01-29 01:51:42.721 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:51:42.721 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 01:51:42.721 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:51:42.721 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:51:42.721 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 01:51:42.721 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:51:42.721 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:51:42.721 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 01:51:42.721 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:51:42.721 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:51:42.721 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 01:51:42.721 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:51:42.721 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:51:42.721 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 01:51:42.721 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:51:42.721 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:51:42.721 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 01:51:42.721 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:51:42.721 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 01:51:42.721 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:51:42.722 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 01:51:42.722 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:51:42.722 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:51:42.725 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-01-29 01:51:43.208 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-01-29 01:51:43.246 [DEBUG] fake_trx.py:278 (BTS@172.18.28.20:5700) Recv FAKE_TOA cmd
2026-01-29 01:51:43.248 [DEBUG] fake_trx.py:297 (BTS@172.18.28.20:5700) Recv FAKE_RSSI cmd
2026-01-29 01:51:43.248 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:51:43.249 [DEBUG] fake_trx.py:322 (BTS@172.18.28.20:5700) Recv FAKE_CI cmd
2026-01-29 01:51:43.251 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 01:51:43.251 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 01:51:43.251 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 01:51:43.251 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 01:51:43.252 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 01:51:43.252 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 01:51:43.252 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.28.22:6700) Recv POWERON CMD
2026-01-29 01:51:43.252 [INFO] ctrl_if_trx.py:109 (MS@172.18.28.22:6700) Starting transceiver...
2026-01-29 01:51:43.686 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-01-29 01:51:43.723 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 01:51:43.724 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 01:51:43.724 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 01:51:43.726 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 01:51:44.164 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-01-29 01:51:44.642 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-01-29 01:51:44.724 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 01:51:44.725 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 01:51:44.725 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 01:51:44.727 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 01:51:45.120 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-01-29 01:51:45.597 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-01-29 01:51:45.725 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 01:51:45.726 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 01:51:45.726 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 01:51:45.728 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 01:51:46.075 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-01-29 01:51:46.561 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-01-29 01:51:46.726 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 01:51:46.727 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 01:51:46.727 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 01:51:46.728 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 01:51:47.039 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-01-29 01:51:47.517 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-01-29 01:51:47.728 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 01:51:47.728 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 01:51:47.728 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 01:51:47.729 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 01:51:47.994 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-01-29 01:51:48.472 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-01-29 01:51:48.946 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-01-29 01:51:49.424 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-01-29 01:51:49.902 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-01-29 01:51:50.379 [DEBUG] clck_gen.py:113 IND CLOCK 1632
2026-01-29 01:51:50.857 [DEBUG] clck_gen.py:113 IND CLOCK 1734
2026-01-29 01:51:51.334 [DEBUG] clck_gen.py:113 IND CLOCK 1836
2026-01-29 01:51:51.812 [DEBUG] clck_gen.py:113 IND CLOCK 1938
2026-01-29 01:51:52.290 [DEBUG] clck_gen.py:113 IND CLOCK 2040
2026-01-29 01:51:52.767 [DEBUG] clck_gen.py:113 IND CLOCK 2142
2026-01-29 01:51:53.245 [DEBUG] clck_gen.py:113 IND CLOCK 2244
2026-01-29 01:51:53.722 [DEBUG] clck_gen.py:113 IND CLOCK 2346
2026-01-29 01:51:54.200 [DEBUG] clck_gen.py:113 IND CLOCK 2448
2026-01-29 01:51:54.677 [DEBUG] clck_gen.py:113 IND CLOCK 2550
2026-01-29 01:51:55.155 [DEBUG] clck_gen.py:113 IND CLOCK 2652
2026-01-29 01:51:55.633 [DEBUG] clck_gen.py:113 IND CLOCK 2754
2026-01-29 01:51:56.111 [DEBUG] clck_gen.py:113 IND CLOCK 2856
2026-01-29 01:51:56.614 [DEBUG] clck_gen.py:113 IND CLOCK 2958
2026-01-29 01:51:57.091 [DEBUG] clck_gen.py:113 IND CLOCK 3060
2026-01-29 01:51:57.377 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 01:51:57.377 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 01:51:57.388 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 01:51:57.389 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 01:51:57.389 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 01:51:57.389 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 01:51:57.394 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 01:51:57.394 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 01:51:57.394 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 01:51:57.394 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 01:51:57.394 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.28.20:5700) Recv POWEROFF cmd
2026-01-29 01:51:57.394 [INFO] ctrl_if_trx.py:117 (BTS@172.18.28.20:5700) Stopping transceiver...
2026-01-29 01:51:57.395 [INFO] transceiver.py:246 Stopping clock generator
2026-01-29 01:51:57.395 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=3127 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 01:51:57.395 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=3127 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 01:51:57.395 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=3127 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 01:51:57.395 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=3127 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 01:51:57.395 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=3127 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 01:51:57.395 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=3127 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 01:51:57.395 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=3127 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 01:51:57.395 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=3127 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 01:52:02.390 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.28.20:5700) Recv POWEROFF cmd
2026-01-29 01:52:02.390 [INFO] ctrl_if_trx.py:117 (BTS@172.18.28.20:5700) Stopping transceiver...
2026-01-29 01:52:02.392 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 01:52:02.393 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 01:52:02.394 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 01:52:02.395 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 01:52:02.402 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 01:52:02.402 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.28.20:5700) Recv SETFORMAT cmd
2026-01-29 01:52:02.402 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.28.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 01:52:02.402 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.28.20:5700) Recv SETFORMAT cmd
2026-01-29 01:52:02.402 [INFO] ctrl_if_trx.py:201 (BTS@172.18.28.20:5700) TRXD header version 1 -> 1
2026-01-29 01:52:02.403 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.28.20:5700/1) Recv RXTUNE cmd
2026-01-29 01:52:02.404 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.28.20:5700/1) Recv TXTUNE cmd
2026-01-29 01:52:02.404 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.28.20:5700/1) Recv SETFORMAT cmd
2026-01-29 01:52:02.404 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.28.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 01:52:02.404 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 01:52:02.404 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.28.20:5700/1) Recv NOMTXPOWER cmd
2026-01-29 01:52:02.405 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.28.20:5700/1) Recv SETFORMAT cmd
2026-01-29 01:52:02.405 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.28.20:5700/1) TRXD header version 1 -> 1
2026-01-29 01:52:02.405 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.28.20:5700/2) Recv RXTUNE cmd
2026-01-29 01:52:02.405 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.28.20:5700/2) Recv TXTUNE cmd
2026-01-29 01:52:02.405 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.28.20:5700/2) Recv SETFORMAT cmd
2026-01-29 01:52:02.406 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.28.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 01:52:02.406 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 01:52:02.406 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.28.20:5700/2) Recv NOMTXPOWER cmd
2026-01-29 01:52:02.406 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.28.20:5700/2) Recv SETFORMAT cmd
2026-01-29 01:52:02.406 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.28.20:5700/2) TRXD header version 1 -> 1
2026-01-29 01:52:02.407 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.28.20:5700/3) Recv RXTUNE cmd
2026-01-29 01:52:02.407 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.28.20:5700/3) Recv TXTUNE cmd
2026-01-29 01:52:02.407 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.28.20:5700/3) Recv SETFORMAT cmd
2026-01-29 01:52:02.407 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.28.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 01:52:02.407 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 01:52:02.407 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.28.20:5700/3) Recv NOMTXPOWER cmd
2026-01-29 01:52:02.407 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.28.20:5700/3) Recv SETFORMAT cmd
2026-01-29 01:52:02.407 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.28.20:5700/3) TRXD header version 1 -> 1
2026-01-29 01:52:02.409 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.28.20:5700) Recv RXTUNE cmd
2026-01-29 01:52:02.409 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETTSC
2026-01-29 01:52:02.409 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETTSC
2026-01-29 01:52:02.409 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETTSC
2026-01-29 01:52:02.409 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.28.20:5700) Recv TXTUNE cmd
2026-01-29 01:52:02.409 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETRXGAIN
2026-01-29 01:52:02.410 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETRXGAIN
2026-01-29 01:52:02.410 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETRXGAIN
2026-01-29 01:52:02.410 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETTSC
2026-01-29 01:52:02.410 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:52:02.410 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:52:02.410 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:52:02.410 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.28.20:5700) Recv NOMTXPOWER cmd
2026-01-29 01:52:02.410 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:52:02.410 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:52:02.410 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:52:02.410 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.28.20:5700) Recv POWERON CMD
2026-01-29 01:52:02.410 [INFO] ctrl_if_trx.py:109 (BTS@172.18.28.20:5700) Starting transceiver...
2026-01-29 01:52:02.410 [INFO] transceiver.py:243 Starting clock generator
2026-01-29 01:52:02.410 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-01-29 01:52:02.410 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:52:02.410 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:52:02.410 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:52:02.410 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETRXGAIN
2026-01-29 01:52:02.410 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:52:02.410 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:52:02.410 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:52:02.410 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 01:52:02.410 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:52:02.410 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:52:02.410 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:52:02.410 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 01:52:02.411 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:52:02.411 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:52:02.411 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:52:02.411 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 01:52:02.411 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:52:02.411 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:52:02.411 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 01:52:02.411 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:52:02.411 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 01:52:02.411 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:52:02.411 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:52:02.411 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 01:52:02.411 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:52:02.411 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 01:52:02.411 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 01:52:02.415 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-01-29 01:52:02.895 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-01-29 01:52:02.943 [DEBUG] fake_trx.py:278 (BTS@172.18.28.20:5700) Recv FAKE_TOA cmd
2026-01-29 01:52:02.944 [DEBUG] fake_trx.py:297 (BTS@172.18.28.20:5700) Recv FAKE_RSSI cmd
2026-01-29 01:52:02.944 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:52:02.945 [DEBUG] fake_trx.py:322 (BTS@172.18.28.20:5700) Recv FAKE_CI cmd
2026-01-29 01:52:02.953 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 01:52:02.953 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 01:52:02.954 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 01:52:02.955 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 01:52:02.955 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 01:52:02.955 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 01:52:02.955 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.28.22:6700) Recv POWERON CMD
2026-01-29 01:52:02.955 [INFO] ctrl_if_trx.py:109 (MS@172.18.28.22:6700) Starting transceiver...
2026-01-29 01:52:02.990 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:52:02.996 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 01:52:02.997 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 01:52:02.997 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 01:52:02.997 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 01:52:03.371 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-01-29 01:52:03.413 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 01:52:03.413 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 01:52:03.414 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 01:52:03.417 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 01:52:03.849 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-01-29 01:52:04.327 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-01-29 01:52:04.415 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 01:52:04.415 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 01:52:04.415 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 01:52:04.419 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 01:52:04.804 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-01-29 01:52:04.997 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 01:52:04.998 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 01:52:04.998 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 01:52:04.998 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 01:52:05.002 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 01:52:05.002 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 01:52:05.002 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 01:52:05.002 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.28.22:6700) Recv POWERON CMD
2026-01-29 01:52:05.002 [INFO] ctrl_if_trx.py:109 (MS@172.18.28.22:6700) Starting transceiver...
2026-01-29 01:52:05.281 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-01-29 01:52:05.415 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 01:52:05.416 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 01:52:05.416 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 01:52:05.419 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 01:52:05.758 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-01-29 01:52:06.236 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-01-29 01:52:06.416 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 01:52:06.417 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 01:52:06.417 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 01:52:06.420 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 01:52:06.714 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-01-29 01:52:07.191 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-01-29 01:52:07.418 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 01:52:07.418 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 01:52:07.418 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 01:52:07.422 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 01:52:07.669 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-01-29 01:52:08.146 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-01-29 01:52:08.624 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-01-29 01:52:09.101 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-01-29 01:52:09.579 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-01-29 01:52:10.057 [DEBUG] clck_gen.py:113 IND CLOCK 1632
2026-01-29 01:52:10.535 [DEBUG] clck_gen.py:113 IND CLOCK 1734
2026-01-29 01:52:11.012 [DEBUG] clck_gen.py:113 IND CLOCK 1836
2026-01-29 01:52:11.490 [DEBUG] clck_gen.py:113 IND CLOCK 1938
2026-01-29 01:52:11.968 [DEBUG] clck_gen.py:113 IND CLOCK 2040
2026-01-29 01:52:12.446 [DEBUG] clck_gen.py:113 IND CLOCK 2142
2026-01-29 01:52:12.923 [DEBUG] clck_gen.py:113 IND CLOCK 2244
2026-01-29 01:52:13.402 [DEBUG] clck_gen.py:113 IND CLOCK 2346
2026-01-29 01:52:13.880 [DEBUG] clck_gen.py:113 IND CLOCK 2448
2026-01-29 01:52:14.358 [DEBUG] clck_gen.py:113 IND CLOCK 2550
2026-01-29 01:52:14.835 [DEBUG] clck_gen.py:113 IND CLOCK 2652
2026-01-29 01:52:15.312 [DEBUG] clck_gen.py:113 IND CLOCK 2754
2026-01-29 01:52:15.790 [DEBUG] clck_gen.py:113 IND CLOCK 2856
2026-01-29 01:52:16.268 [DEBUG] clck_gen.py:113 IND CLOCK 2958
2026-01-29 01:52:16.746 [DEBUG] clck_gen.py:113 IND CLOCK 3060
2026-01-29 01:52:17.223 [DEBUG] clck_gen.py:113 IND CLOCK 3162
2026-01-29 01:52:17.701 [DEBUG] clck_gen.py:113 IND CLOCK 3264
2026-01-29 01:52:18.179 [DEBUG] clck_gen.py:113 IND CLOCK 3366
2026-01-29 01:52:18.657 [DEBUG] clck_gen.py:113 IND CLOCK 3468
2026-01-29 01:52:19.134 [DEBUG] clck_gen.py:113 IND CLOCK 3570
2026-01-29 01:52:19.612 [DEBUG] clck_gen.py:113 IND CLOCK 3672
2026-01-29 01:52:19.896 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:52:19.899 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 01:52:19.899 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 01:52:19.915 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 01:52:19.915 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 01:52:19.915 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 01:52:19.915 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 01:52:19.921 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 01:52:19.921 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 01:52:19.921 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 01:52:19.921 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 01:52:19.921 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.28.20:5700) Recv POWEROFF cmd
2026-01-29 01:52:19.921 [INFO] ctrl_if_trx.py:117 (BTS@172.18.28.20:5700) Stopping transceiver...
2026-01-29 01:52:19.922 [INFO] transceiver.py:246 Stopping clock generator
2026-01-29 01:52:19.922 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=3740 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 01:52:19.922 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=3740 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 01:52:19.922 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=3740 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 01:52:19.922 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=3740 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 01:52:19.922 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=3740 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 01:52:19.922 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=3740 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 01:52:19.922 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=3740 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 01:52:19.922 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=3740 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 01:52:19.923 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=3741 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 01:52:19.923 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=3741 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 01:52:24.916 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.28.20:5700) Recv POWEROFF cmd
2026-01-29 01:52:24.916 [INFO] ctrl_if_trx.py:117 (BTS@172.18.28.20:5700) Stopping transceiver...
2026-01-29 01:52:24.917 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 01:52:24.919 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 01:52:24.920 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 01:52:24.920 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 01:52:24.926 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 01:52:24.927 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.28.20:5700) Recv SETFORMAT cmd
2026-01-29 01:52:24.927 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.28.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 01:52:24.927 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.28.20:5700) Recv SETFORMAT cmd
2026-01-29 01:52:24.927 [INFO] ctrl_if_trx.py:201 (BTS@172.18.28.20:5700) TRXD header version 1 -> 1
2026-01-29 01:52:24.931 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.28.20:5700/1) Recv RXTUNE cmd
2026-01-29 01:52:24.931 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.28.20:5700/1) Recv TXTUNE cmd
2026-01-29 01:52:24.931 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.28.20:5700/1) Recv SETFORMAT cmd
2026-01-29 01:52:24.932 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.28.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 01:52:24.932 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 01:52:24.932 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.28.20:5700/1) Recv NOMTXPOWER cmd
2026-01-29 01:52:24.932 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.28.20:5700/1) Recv SETFORMAT cmd
2026-01-29 01:52:24.932 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.28.20:5700/1) TRXD header version 1 -> 1
2026-01-29 01:52:24.935 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.28.20:5700/2) Recv RXTUNE cmd
2026-01-29 01:52:24.935 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.28.20:5700/2) Recv TXTUNE cmd
2026-01-29 01:52:24.935 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.28.20:5700/2) Recv SETFORMAT cmd
2026-01-29 01:52:24.935 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.28.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 01:52:24.935 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 01:52:24.936 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.28.20:5700/2) Recv NOMTXPOWER cmd
2026-01-29 01:52:24.936 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.28.20:5700/2) Recv SETFORMAT cmd
2026-01-29 01:52:24.936 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.28.20:5700/2) TRXD header version 1 -> 1
2026-01-29 01:52:24.937 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.28.20:5700/3) Recv RXTUNE cmd
2026-01-29 01:52:24.938 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.28.20:5700/3) Recv TXTUNE cmd
2026-01-29 01:52:24.938 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.28.20:5700/3) Recv SETFORMAT cmd
2026-01-29 01:52:24.938 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.28.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 01:52:24.938 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 01:52:24.938 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.28.20:5700/3) Recv NOMTXPOWER cmd
2026-01-29 01:52:24.938 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.28.20:5700/3) Recv SETFORMAT cmd
2026-01-29 01:52:24.938 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.28.20:5700/3) TRXD header version 1 -> 1
2026-01-29 01:52:24.940 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.28.20:5700) Recv RXTUNE cmd
2026-01-29 01:52:24.940 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETTSC
2026-01-29 01:52:24.940 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETTSC
2026-01-29 01:52:24.941 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETTSC
2026-01-29 01:52:24.941 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.28.20:5700) Recv TXTUNE cmd
2026-01-29 01:52:24.941 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETRXGAIN
2026-01-29 01:52:24.941 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETRXGAIN
2026-01-29 01:52:24.941 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETRXGAIN
2026-01-29 01:52:24.941 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETTSC
2026-01-29 01:52:24.941 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:52:24.941 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:52:24.941 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.28.20:5700) Recv NOMTXPOWER cmd
2026-01-29 01:52:24.941 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:52:24.941 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:52:24.941 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:52:24.941 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.28.20:5700) Recv POWERON CMD
2026-01-29 01:52:24.941 [INFO] ctrl_if_trx.py:109 (BTS@172.18.28.20:5700) Starting transceiver...
2026-01-29 01:52:24.941 [INFO] transceiver.py:243 Starting clock generator
2026-01-29 01:52:24.941 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-01-29 01:52:24.941 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:52:24.941 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:52:24.941 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:52:24.942 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETRXGAIN
2026-01-29 01:52:24.942 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:52:24.942 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:52:24.942 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:52:24.942 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 01:52:24.942 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:52:24.942 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:52:24.942 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 01:52:24.942 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:52:24.942 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:52:24.942 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:52:24.942 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 01:52:24.942 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:52:24.942 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:52:24.942 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:52:24.942 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 01:52:24.942 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:52:24.942 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:52:24.942 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:52:24.942 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 01:52:24.942 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:52:24.942 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 01:52:24.942 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:52:24.942 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 01:52:24.943 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 01:52:24.946 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-01-29 01:52:25.430 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-01-29 01:52:25.469 [DEBUG] fake_trx.py:278 (BTS@172.18.28.20:5700) Recv FAKE_TOA cmd
2026-01-29 01:52:25.471 [DEBUG] fake_trx.py:297 (BTS@172.18.28.20:5700) Recv FAKE_RSSI cmd
2026-01-29 01:52:25.472 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:52:25.473 [DEBUG] fake_trx.py:322 (BTS@172.18.28.20:5700) Recv FAKE_CI cmd
2026-01-29 01:52:25.475 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 01:52:25.476 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 01:52:25.476 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 01:52:25.476 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 01:52:25.476 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 01:52:25.477 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 01:52:25.477 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.28.22:6700) Recv POWERON CMD
2026-01-29 01:52:25.477 [INFO] ctrl_if_trx.py:109 (MS@172.18.28.22:6700) Starting transceiver...
2026-01-29 01:52:25.908 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-01-29 01:52:25.945 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 01:52:25.945 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 01:52:25.946 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 01:52:25.949 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 01:52:26.385 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-01-29 01:52:26.863 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-01-29 01:52:26.947 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 01:52:26.947 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 01:52:26.947 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 01:52:26.950 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 01:52:27.341 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-01-29 01:52:27.819 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-01-29 01:52:27.948 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 01:52:27.948 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 01:52:27.949 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 01:52:27.951 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 01:52:28.296 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-01-29 01:52:28.774 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-01-29 01:52:28.949 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 01:52:28.950 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 01:52:28.950 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 01:52:28.952 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 01:52:29.252 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-01-29 01:52:29.730 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-01-29 01:52:29.951 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 01:52:29.951 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 01:52:29.951 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 01:52:29.953 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 01:52:30.208 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-01-29 01:52:30.685 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-01-29 01:52:31.164 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-01-29 01:52:31.641 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-01-29 01:52:32.119 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-01-29 01:52:32.597 [DEBUG] clck_gen.py:113 IND CLOCK 1632
2026-01-29 01:52:33.075 [DEBUG] clck_gen.py:113 IND CLOCK 1734
2026-01-29 01:52:33.552 [DEBUG] clck_gen.py:113 IND CLOCK 1836
2026-01-29 01:52:34.030 [DEBUG] clck_gen.py:113 IND CLOCK 1938
2026-01-29 01:52:34.508 [DEBUG] clck_gen.py:113 IND CLOCK 2040
2026-01-29 01:52:34.985 [DEBUG] clck_gen.py:113 IND CLOCK 2142
2026-01-29 01:52:35.462 [DEBUG] clck_gen.py:113 IND CLOCK 2244
2026-01-29 01:52:35.940 [DEBUG] clck_gen.py:113 IND CLOCK 2346
2026-01-29 01:52:36.418 [DEBUG] clck_gen.py:113 IND CLOCK 2448
2026-01-29 01:52:36.896 [DEBUG] clck_gen.py:113 IND CLOCK 2550
2026-01-29 01:52:37.373 [DEBUG] clck_gen.py:113 IND CLOCK 2652
2026-01-29 01:52:37.851 [DEBUG] clck_gen.py:113 IND CLOCK 2754
2026-01-29 01:52:38.328 [DEBUG] clck_gen.py:113 IND CLOCK 2856
2026-01-29 01:52:38.805 [DEBUG] clck_gen.py:113 IND CLOCK 2958
2026-01-29 01:52:39.283 [DEBUG] clck_gen.py:113 IND CLOCK 3060
2026-01-29 01:52:39.761 [DEBUG] clck_gen.py:113 IND CLOCK 3162
2026-01-29 01:52:40.239 [DEBUG] clck_gen.py:113 IND CLOCK 3264
2026-01-29 01:52:40.716 [DEBUG] clck_gen.py:113 IND CLOCK 3366
2026-01-29 01:52:41.194 [DEBUG] clck_gen.py:113 IND CLOCK 3468
2026-01-29 01:52:41.672 [DEBUG] clck_gen.py:113 IND CLOCK 3570
2026-01-29 01:52:42.149 [DEBUG] clck_gen.py:113 IND CLOCK 3672
2026-01-29 01:52:42.627 [DEBUG] clck_gen.py:113 IND CLOCK 3774
2026-01-29 01:52:43.105 [DEBUG] clck_gen.py:113 IND CLOCK 3876
2026-01-29 01:52:43.583 [DEBUG] clck_gen.py:113 IND CLOCK 3978
2026-01-29 01:52:44.060 [DEBUG] clck_gen.py:113 IND CLOCK 4080
2026-01-29 01:52:44.538 [DEBUG] clck_gen.py:113 IND CLOCK 4182
2026-01-29 01:52:45.016 [DEBUG] clck_gen.py:113 IND CLOCK 4284
2026-01-29 01:52:45.494 [DEBUG] clck_gen.py:113 IND CLOCK 4386
2026-01-29 01:52:45.972 [DEBUG] clck_gen.py:113 IND CLOCK 4488
2026-01-29 01:52:46.449 [DEBUG] clck_gen.py:113 IND CLOCK 4590
2026-01-29 01:52:46.926 [DEBUG] clck_gen.py:113 IND CLOCK 4692
2026-01-29 01:52:46.961 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 01:52:46.961 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 01:52:46.967 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 01:52:46.968 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 01:52:46.968 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 01:52:46.968 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 01:52:46.974 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 01:52:46.974 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 01:52:46.974 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 01:52:46.974 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 01:52:46.974 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.28.20:5700) Recv POWEROFF cmd
2026-01-29 01:52:46.975 [INFO] ctrl_if_trx.py:117 (BTS@172.18.28.20:5700) Stopping transceiver...
2026-01-29 01:52:46.975 [INFO] transceiver.py:246 Stopping clock generator
2026-01-29 01:52:46.975 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=4702 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 01:52:46.975 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=4702 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 01:52:51.971 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.28.20:5700) Recv POWEROFF cmd
2026-01-29 01:52:51.971 [INFO] ctrl_if_trx.py:117 (BTS@172.18.28.20:5700) Stopping transceiver...
2026-01-29 01:52:51.973 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 01:52:51.978 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 01:52:51.978 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 01:52:51.979 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 01:52:51.987 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 01:52:51.987 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.28.20:5700) Recv SETFORMAT cmd
2026-01-29 01:52:51.987 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.28.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 01:52:51.987 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.28.20:5700) Recv SETFORMAT cmd
2026-01-29 01:52:51.987 [INFO] ctrl_if_trx.py:201 (BTS@172.18.28.20:5700) TRXD header version 1 -> 1
2026-01-29 01:52:51.991 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.28.20:5700/1) Recv RXTUNE cmd
2026-01-29 01:52:51.991 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.28.20:5700/1) Recv TXTUNE cmd
2026-01-29 01:52:51.991 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.28.20:5700/1) Recv SETFORMAT cmd
2026-01-29 01:52:51.991 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.28.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 01:52:51.992 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 01:52:51.992 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.28.20:5700/1) Recv NOMTXPOWER cmd
2026-01-29 01:52:51.992 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.28.20:5700/1) Recv SETFORMAT cmd
2026-01-29 01:52:51.993 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.28.20:5700/1) TRXD header version 1 -> 1
2026-01-29 01:52:51.997 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.28.20:5700/2) Recv RXTUNE cmd
2026-01-29 01:52:51.998 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.28.20:5700/2) Recv TXTUNE cmd
2026-01-29 01:52:51.998 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.28.20:5700/2) Recv SETFORMAT cmd
2026-01-29 01:52:51.998 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.28.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 01:52:51.998 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 01:52:51.998 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.28.20:5700/2) Recv NOMTXPOWER cmd
2026-01-29 01:52:51.999 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.28.20:5700/2) Recv SETFORMAT cmd
2026-01-29 01:52:51.999 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.28.20:5700/2) TRXD header version 1 -> 1
2026-01-29 01:52:52.001 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.28.20:5700/3) Recv RXTUNE cmd
2026-01-29 01:52:52.001 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.28.20:5700/3) Recv TXTUNE cmd
2026-01-29 01:52:52.002 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.28.20:5700/3) Recv SETFORMAT cmd
2026-01-29 01:52:52.002 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.28.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 01:52:52.002 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 01:52:52.002 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.28.20:5700/3) Recv NOMTXPOWER cmd
2026-01-29 01:52:52.002 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.28.20:5700/3) Recv SETFORMAT cmd
2026-01-29 01:52:52.002 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.28.20:5700/3) TRXD header version 1 -> 1
2026-01-29 01:52:52.005 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.28.20:5700) Recv RXTUNE cmd
2026-01-29 01:52:52.005 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETTSC
2026-01-29 01:52:52.005 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETTSC
2026-01-29 01:52:52.005 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETTSC
2026-01-29 01:52:52.005 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.28.20:5700) Recv TXTUNE cmd
2026-01-29 01:52:52.005 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETRXGAIN
2026-01-29 01:52:52.005 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETRXGAIN
2026-01-29 01:52:52.006 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETRXGAIN
2026-01-29 01:52:52.006 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETTSC
2026-01-29 01:52:52.006 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:52:52.006 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:52:52.006 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:52:52.006 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.28.20:5700) Recv NOMTXPOWER cmd
2026-01-29 01:52:52.006 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:52:52.006 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:52:52.006 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:52:52.006 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.28.20:5700) Recv POWERON CMD
2026-01-29 01:52:52.006 [INFO] ctrl_if_trx.py:109 (BTS@172.18.28.20:5700) Starting transceiver...
2026-01-29 01:52:52.006 [INFO] transceiver.py:243 Starting clock generator
2026-01-29 01:52:52.006 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-01-29 01:52:52.006 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:52:52.006 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:52:52.006 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:52:52.006 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETRXGAIN
2026-01-29 01:52:52.007 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:52:52.007 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:52:52.007 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 01:52:52.007 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:52:52.007 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:52:52.007 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:52:52.007 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 01:52:52.007 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:52:52.007 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:52:52.007 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:52:52.007 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 01:52:52.007 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:52:52.007 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:52:52.007 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:52:52.007 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 01:52:52.007 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:52:52.007 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:52:52.007 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:52:52.007 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 01:52:52.007 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:52:52.007 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 01:52:52.007 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 01:52:52.007 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 01:52:52.011 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-01-29 01:52:52.490 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-01-29 01:52:52.523 [DEBUG] fake_trx.py:278 (BTS@172.18.28.20:5700) Recv FAKE_TOA cmd
2026-01-29 01:52:52.523 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:52:52.524 [DEBUG] fake_trx.py:297 (BTS@172.18.28.20:5700) Recv FAKE_RSSI cmd
2026-01-29 01:52:52.525 [DEBUG] fake_trx.py:322 (BTS@172.18.28.20:5700) Recv FAKE_CI cmd
2026-01-29 01:52:52.526 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 01:52:52.526 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 01:52:52.526 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 01:52:52.526 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 01:52:52.526 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 01:52:52.526 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 01:52:52.526 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.28.22:6700) Recv POWERON CMD
2026-01-29 01:52:52.526 [INFO] ctrl_if_trx.py:109 (MS@172.18.28.22:6700) Starting transceiver...
2026-01-29 01:52:52.965 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-01-29 01:52:53.010 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 01:52:53.010 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 01:52:53.011 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 01:52:53.015 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 01:52:53.442 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-01-29 01:52:53.919 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-01-29 01:52:54.011 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 01:52:54.011 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 01:52:54.012 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 01:52:54.016 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 01:52:54.397 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-01-29 01:52:54.875 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-01-29 01:52:55.012 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 01:52:55.012 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 01:52:55.013 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 01:52:55.017 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 01:52:55.353 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-01-29 01:52:55.829 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-01-29 01:52:56.013 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 01:52:56.013 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 01:52:56.014 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 01:52:56.019 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 01:52:56.306 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-01-29 01:52:56.784 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-01-29 01:52:57.014 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 01:52:57.014 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 01:52:57.015 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 01:52:57.020 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 01:52:57.261 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-01-29 01:52:57.739 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-01-29 01:52:58.217 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-01-29 01:52:58.694 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-01-29 01:52:59.172 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-01-29 01:52:59.650 [DEBUG] clck_gen.py:113 IND CLOCK 1632
2026-01-29 01:53:00.128 [DEBUG] clck_gen.py:113 IND CLOCK 1734
2026-01-29 01:53:00.606 [DEBUG] clck_gen.py:113 IND CLOCK 1836
2026-01-29 01:53:01.083 [DEBUG] clck_gen.py:113 IND CLOCK 1938
2026-01-29 01:53:01.561 [DEBUG] clck_gen.py:113 IND CLOCK 2040
2026-01-29 01:53:02.039 [DEBUG] clck_gen.py:113 IND CLOCK 2142
2026-01-29 01:53:02.517 [DEBUG] clck_gen.py:113 IND CLOCK 2244
2026-01-29 01:53:02.995 [DEBUG] clck_gen.py:113 IND CLOCK 2346
2026-01-29 01:53:03.473 [DEBUG] clck_gen.py:113 IND CLOCK 2448
2026-01-29 01:53:03.951 [DEBUG] clck_gen.py:113 IND CLOCK 2550
2026-01-29 01:53:04.428 [DEBUG] clck_gen.py:113 IND CLOCK 2652
2026-01-29 01:53:04.905 [DEBUG] clck_gen.py:113 IND CLOCK 2754
2026-01-29 01:53:05.383 [DEBUG] clck_gen.py:113 IND CLOCK 2856
2026-01-29 01:53:05.861 [DEBUG] clck_gen.py:113 IND CLOCK 2958
2026-01-29 01:53:06.339 [DEBUG] clck_gen.py:113 IND CLOCK 3060
2026-01-29 01:53:06.816 [DEBUG] clck_gen.py:113 IND CLOCK 3162
2026-01-29 01:53:07.289 [DEBUG] clck_gen.py:113 IND CLOCK 3264
2026-01-29 01:53:07.768 [DEBUG] clck_gen.py:113 IND CLOCK 3366
2026-01-29 01:53:08.246 [DEBUG] clck_gen.py:113 IND CLOCK 3468
2026-01-29 01:53:08.720 [DEBUG] clck_gen.py:113 IND CLOCK 3570
2026-01-29 01:53:09.198 [DEBUG] clck_gen.py:113 IND CLOCK 3672
2026-01-29 01:53:09.675 [DEBUG] clck_gen.py:113 IND CLOCK 3774
2026-01-29 01:53:10.153 [DEBUG] clck_gen.py:113 IND CLOCK 3876
2026-01-29 01:53:10.631 [DEBUG] clck_gen.py:113 IND CLOCK 3978
2026-01-29 01:53:11.108 [DEBUG] clck_gen.py:113 IND CLOCK 4080
2026-01-29 01:53:11.586 [DEBUG] clck_gen.py:113 IND CLOCK 4182
2026-01-29 01:53:12.063 [DEBUG] clck_gen.py:113 IND CLOCK 4284
2026-01-29 01:53:12.541 [DEBUG] clck_gen.py:113 IND CLOCK 4386
2026-01-29 01:53:13.018 [DEBUG] clck_gen.py:113 IND CLOCK 4488
2026-01-29 01:53:13.495 [DEBUG] clck_gen.py:113 IND CLOCK 4590
2026-01-29 01:53:13.973 [DEBUG] clck_gen.py:113 IND CLOCK 4692
2026-01-29 01:53:14.027 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 01:53:14.027 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 01:53:14.033 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 01:53:14.033 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 01:53:14.033 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 01:53:14.033 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 01:53:14.034 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 01:53:14.034 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 01:53:14.034 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 01:53:14.034 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.28.20:5700) Recv POWEROFF cmd
2026-01-29 01:53:14.034 [INFO] ctrl_if_trx.py:117 (BTS@172.18.28.20:5700) Stopping transceiver...
2026-01-29 01:53:14.034 [INFO] transceiver.py:246 Stopping clock generator
2026-01-29 01:53:14.034 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 01:53:14.034 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=4707 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 01:53:14.034 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=4707 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 01:53:14.034 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=4707 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 01:53:14.034 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=4707 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 01:53:14.034 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=4707 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 01:53:14.034 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=4707 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 01:53:14.034 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=4707 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 01:53:14.034 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=4707 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 01:53:19.038 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.28.20:5700) Recv POWEROFF cmd
2026-01-29 01:53:19.038 [INFO] ctrl_if_trx.py:117 (BTS@172.18.28.20:5700) Stopping transceiver...
2026-01-29 01:53:19.038 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 01:53:19.038 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 01:53:19.038 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 01:53:19.038 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 01:53:19.047 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 01:53:19.048 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.28.20:5700) Recv SETFORMAT cmd
2026-01-29 01:53:19.048 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.28.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 01:53:19.049 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.28.20:5700) Recv SETFORMAT cmd
2026-01-29 01:53:19.049 [INFO] ctrl_if_trx.py:201 (BTS@172.18.28.20:5700) TRXD header version 1 -> 1
2026-01-29 01:53:19.053 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.28.20:5700/1) Recv RXTUNE cmd
2026-01-29 01:53:19.053 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.28.20:5700/1) Recv TXTUNE cmd
2026-01-29 01:53:19.054 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.28.20:5700/1) Recv SETFORMAT cmd
2026-01-29 01:53:19.054 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.28.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 01:53:19.054 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 01:53:19.055 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.28.20:5700/1) Recv NOMTXPOWER cmd
2026-01-29 01:53:19.055 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.28.20:5700/1) Recv SETFORMAT cmd
2026-01-29 01:53:19.055 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.28.20:5700/1) TRXD header version 1 -> 1
2026-01-29 01:53:19.057 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.28.20:5700/2) Recv RXTUNE cmd
2026-01-29 01:53:19.057 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.28.20:5700/2) Recv TXTUNE cmd
2026-01-29 01:53:19.057 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.28.20:5700/2) Recv SETFORMAT cmd
2026-01-29 01:53:19.057 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.28.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 01:53:19.058 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 01:53:19.058 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.28.20:5700/2) Recv NOMTXPOWER cmd
2026-01-29 01:53:19.058 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.28.20:5700/2) Recv SETFORMAT cmd
2026-01-29 01:53:19.058 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.28.20:5700/2) TRXD header version 1 -> 1
2026-01-29 01:53:19.060 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.28.20:5700/3) Recv RXTUNE cmd
2026-01-29 01:53:19.060 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.28.20:5700/3) Recv TXTUNE cmd
2026-01-29 01:53:19.060 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.28.20:5700/3) Recv SETFORMAT cmd
2026-01-29 01:53:19.060 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.28.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 01:53:19.061 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 01:53:19.061 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.28.20:5700/3) Recv NOMTXPOWER cmd
2026-01-29 01:53:19.061 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.28.20:5700/3) Recv SETFORMAT cmd
2026-01-29 01:53:19.061 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.28.20:5700/3) TRXD header version 1 -> 1
2026-01-29 01:53:19.063 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.28.20:5700) Recv RXTUNE cmd
2026-01-29 01:53:19.063 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETTSC
2026-01-29 01:53:19.063 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETTSC
2026-01-29 01:53:19.063 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETTSC
2026-01-29 01:53:19.063 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.28.20:5700) Recv TXTUNE cmd
2026-01-29 01:53:19.063 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETRXGAIN
2026-01-29 01:53:19.063 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETRXGAIN
2026-01-29 01:53:19.063 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETRXGAIN
2026-01-29 01:53:19.063 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETTSC
2026-01-29 01:53:19.063 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:53:19.063 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:53:19.063 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:53:19.063 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.28.20:5700) Recv NOMTXPOWER cmd
2026-01-29 01:53:19.063 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:53:19.063 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:53:19.063 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:53:19.063 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.28.20:5700) Recv POWERON CMD
2026-01-29 01:53:19.063 [INFO] ctrl_if_trx.py:109 (BTS@172.18.28.20:5700) Starting transceiver...
2026-01-29 01:53:19.063 [INFO] transceiver.py:243 Starting clock generator
2026-01-29 01:53:19.064 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-01-29 01:53:19.064 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:53:19.064 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:53:19.064 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:53:19.064 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETRXGAIN
2026-01-29 01:53:19.064 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:53:19.064 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:53:19.064 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:53:19.064 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 01:53:19.064 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:53:19.064 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:53:19.064 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:53:19.065 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 01:53:19.065 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:53:19.065 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:53:19.065 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:53:19.065 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 01:53:19.065 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:53:19.065 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:53:19.065 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:53:19.065 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 01:53:19.065 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:53:19.065 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:53:19.065 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:53:19.065 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 01:53:19.065 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 01:53:19.065 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 01:53:19.065 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 01:53:19.068 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-01-29 01:53:19.552 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-01-29 01:53:19.586 [DEBUG] fake_trx.py:278 (BTS@172.18.28.20:5700) Recv FAKE_TOA cmd
2026-01-29 01:53:19.587 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:53:19.588 [DEBUG] fake_trx.py:297 (BTS@172.18.28.20:5700) Recv FAKE_RSSI cmd
2026-01-29 01:53:19.590 [DEBUG] fake_trx.py:322 (BTS@172.18.28.20:5700) Recv FAKE_CI cmd
2026-01-29 01:53:19.591 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 01:53:19.591 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 01:53:19.592 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 01:53:19.593 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 01:53:19.593 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 01:53:19.593 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 01:53:19.593 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.28.22:6700) Recv POWERON CMD
2026-01-29 01:53:19.593 [INFO] ctrl_if_trx.py:109 (MS@172.18.28.22:6700) Starting transceiver...
2026-01-29 01:53:20.029 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-01-29 01:53:20.066 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 01:53:20.066 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 01:53:20.067 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 01:53:20.070 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 01:53:20.507 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-01-29 01:53:20.984 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-01-29 01:53:21.067 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 01:53:21.067 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 01:53:21.068 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 01:53:21.071 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 01:53:21.462 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-01-29 01:53:21.940 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-01-29 01:53:22.068 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 01:53:22.069 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 01:53:22.069 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 01:53:22.073 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 01:53:22.417 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-01-29 01:53:22.895 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-01-29 01:53:23.069 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 01:53:23.069 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 01:53:23.069 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 01:53:23.074 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 01:53:23.372 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-01-29 01:53:23.849 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-01-29 01:53:24.070 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 01:53:24.071 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 01:53:24.071 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 01:53:24.074 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 01:53:24.326 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-01-29 01:53:24.804 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-01-29 01:53:25.281 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-01-29 01:53:25.759 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-01-29 01:53:26.236 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-01-29 01:53:26.714 [DEBUG] clck_gen.py:113 IND CLOCK 1632
2026-01-29 01:53:27.192 [DEBUG] clck_gen.py:113 IND CLOCK 1734
2026-01-29 01:53:27.669 [DEBUG] clck_gen.py:113 IND CLOCK 1836
2026-01-29 01:53:28.148 [DEBUG] clck_gen.py:113 IND CLOCK 1938
2026-01-29 01:53:28.625 [DEBUG] clck_gen.py:113 IND CLOCK 2040
2026-01-29 01:53:29.104 [DEBUG] clck_gen.py:113 IND CLOCK 2142
2026-01-29 01:53:29.581 [DEBUG] clck_gen.py:113 IND CLOCK 2244
2026-01-29 01:53:30.059 [DEBUG] clck_gen.py:113 IND CLOCK 2346
2026-01-29 01:53:30.537 [DEBUG] clck_gen.py:113 IND CLOCK 2448
2026-01-29 01:53:31.014 [DEBUG] clck_gen.py:113 IND CLOCK 2550
2026-01-29 01:53:31.492 [DEBUG] clck_gen.py:113 IND CLOCK 2652
2026-01-29 01:53:31.969 [DEBUG] clck_gen.py:113 IND CLOCK 2754
2026-01-29 01:53:32.447 [DEBUG] clck_gen.py:113 IND CLOCK 2856
2026-01-29 01:53:32.925 [DEBUG] clck_gen.py:113 IND CLOCK 2958
2026-01-29 01:53:33.402 [DEBUG] clck_gen.py:113 IND CLOCK 3060
2026-01-29 01:53:33.880 [DEBUG] clck_gen.py:113 IND CLOCK 3162
2026-01-29 01:53:34.358 [DEBUG] clck_gen.py:113 IND CLOCK 3264
2026-01-29 01:53:34.836 [DEBUG] clck_gen.py:113 IND CLOCK 3366
2026-01-29 01:53:35.313 [DEBUG] clck_gen.py:113 IND CLOCK 3468
2026-01-29 01:53:35.791 [DEBUG] clck_gen.py:113 IND CLOCK 3570
2026-01-29 01:53:36.269 [DEBUG] clck_gen.py:113 IND CLOCK 3672
2026-01-29 01:53:36.747 [DEBUG] clck_gen.py:113 IND CLOCK 3774
2026-01-29 01:53:37.224 [DEBUG] clck_gen.py:113 IND CLOCK 3876
2026-01-29 01:53:37.702 [DEBUG] clck_gen.py:113 IND CLOCK 3978
2026-01-29 01:53:38.180 [DEBUG] clck_gen.py:113 IND CLOCK 4080
2026-01-29 01:53:38.657 [DEBUG] clck_gen.py:113 IND CLOCK 4182
2026-01-29 01:53:39.135 [DEBUG] clck_gen.py:113 IND CLOCK 4284
2026-01-29 01:53:39.612 [DEBUG] clck_gen.py:113 IND CLOCK 4386
2026-01-29 01:53:40.090 [DEBUG] clck_gen.py:113 IND CLOCK 4488
2026-01-29 01:53:40.567 [DEBUG] clck_gen.py:113 IND CLOCK 4590
2026-01-29 01:53:41.045 [DEBUG] clck_gen.py:113 IND CLOCK 4692
2026-01-29 01:53:41.523 [DEBUG] clck_gen.py:113 IND CLOCK 4794
2026-01-29 01:53:42.000 [DEBUG] clck_gen.py:113 IND CLOCK 4896
2026-01-29 01:53:42.478 [DEBUG] clck_gen.py:113 IND CLOCK 4998
2026-01-29 01:53:42.956 [DEBUG] clck_gen.py:113 IND CLOCK 5100
2026-01-29 01:53:43.434 [DEBUG] clck_gen.py:113 IND CLOCK 5202
2026-01-29 01:53:43.911 [DEBUG] clck_gen.py:113 IND CLOCK 5304
2026-01-29 01:53:44.389 [DEBUG] clck_gen.py:113 IND CLOCK 5406
2026-01-29 01:53:44.867 [DEBUG] clck_gen.py:113 IND CLOCK 5508
2026-01-29 01:53:45.345 [DEBUG] clck_gen.py:113 IND CLOCK 5610
2026-01-29 01:53:45.822 [DEBUG] clck_gen.py:113 IND CLOCK 5712
2026-01-29 01:53:46.300 [DEBUG] clck_gen.py:113 IND CLOCK 5814
2026-01-29 01:53:46.778 [DEBUG] clck_gen.py:113 IND CLOCK 5916
2026-01-29 01:53:47.256 [DEBUG] clck_gen.py:113 IND CLOCK 6018
2026-01-29 01:53:47.734 [DEBUG] clck_gen.py:113 IND CLOCK 6120
2026-01-29 01:53:48.211 [DEBUG] clck_gen.py:113 IND CLOCK 6222
2026-01-29 01:53:48.689 [DEBUG] clck_gen.py:113 IND CLOCK 6324
2026-01-29 01:53:49.167 [DEBUG] clck_gen.py:113 IND CLOCK 6426
2026-01-29 01:53:49.645 [DEBUG] clck_gen.py:113 IND CLOCK 6528
2026-01-29 01:53:50.123 [DEBUG] clck_gen.py:113 IND CLOCK 6630
2026-01-29 01:53:50.600 [DEBUG] clck_gen.py:113 IND CLOCK 6732
2026-01-29 01:53:51.078 [DEBUG] clck_gen.py:113 IND CLOCK 6834
2026-01-29 01:53:51.556 [DEBUG] clck_gen.py:113 IND CLOCK 6936
2026-01-29 01:53:52.034 [DEBUG] clck_gen.py:113 IND CLOCK 7038
2026-01-29 01:53:52.509 [DEBUG] clck_gen.py:113 IND CLOCK 7140
2026-01-29 01:53:52.987 [DEBUG] clck_gen.py:113 IND CLOCK 7242
2026-01-29 01:53:53.087 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 01:53:53.088 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 01:53:53.091 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 01:53:53.091 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 01:53:53.091 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 01:53:53.091 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 01:53:53.092 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 01:53:53.092 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 01:53:53.092 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 01:53:53.092 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 01:53:53.092 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.28.20:5700) Recv POWEROFF cmd
2026-01-29 01:53:53.092 [INFO] ctrl_if_trx.py:117 (BTS@172.18.28.20:5700) Stopping transceiver...
2026-01-29 01:53:53.092 [INFO] transceiver.py:246 Stopping clock generator
2026-01-29 01:53:58.095 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.28.20:5700) Recv POWEROFF cmd
2026-01-29 01:53:58.095 [INFO] ctrl_if_trx.py:117 (BTS@172.18.28.20:5700) Stopping transceiver...
2026-01-29 01:53:58.096 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 01:53:58.098 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 01:53:58.099 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 01:53:58.099 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 01:53:58.107 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 01:53:58.108 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.28.20:5700) Recv SETFORMAT cmd
2026-01-29 01:53:58.108 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.28.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 01:53:58.108 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.28.20:5700) Recv SETFORMAT cmd
2026-01-29 01:53:58.108 [INFO] ctrl_if_trx.py:201 (BTS@172.18.28.20:5700) TRXD header version 1 -> 1
2026-01-29 01:53:58.111 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.28.20:5700/1) Recv RXTUNE cmd
2026-01-29 01:53:58.111 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.28.20:5700/1) Recv TXTUNE cmd
2026-01-29 01:53:58.112 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.28.20:5700/1) Recv SETFORMAT cmd
2026-01-29 01:53:58.112 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.28.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 01:53:58.112 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 01:53:58.112 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.28.20:5700/1) Recv NOMTXPOWER cmd
2026-01-29 01:53:58.113 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.28.20:5700/1) Recv SETFORMAT cmd
2026-01-29 01:53:58.113 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.28.20:5700/1) TRXD header version 1 -> 1
2026-01-29 01:53:58.114 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.28.20:5700/2) Recv RXTUNE cmd
2026-01-29 01:53:58.114 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.28.20:5700/2) Recv TXTUNE cmd
2026-01-29 01:53:58.114 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.28.20:5700/2) Recv SETFORMAT cmd
2026-01-29 01:53:58.114 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.28.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 01:53:58.114 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 01:53:58.115 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.28.20:5700/2) Recv NOMTXPOWER cmd
2026-01-29 01:53:58.115 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.28.20:5700/2) Recv SETFORMAT cmd
2026-01-29 01:53:58.115 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.28.20:5700/2) TRXD header version 1 -> 1
2026-01-29 01:53:58.116 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.28.20:5700/3) Recv RXTUNE cmd
2026-01-29 01:53:58.117 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.28.20:5700/3) Recv TXTUNE cmd
2026-01-29 01:53:58.117 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.28.20:5700/3) Recv SETFORMAT cmd
2026-01-29 01:53:58.117 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.28.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 01:53:58.117 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 01:53:58.117 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.28.20:5700/3) Recv NOMTXPOWER cmd
2026-01-29 01:53:58.117 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.28.20:5700/3) Recv SETFORMAT cmd
2026-01-29 01:53:58.117 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.28.20:5700/3) TRXD header version 1 -> 1
2026-01-29 01:53:58.119 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.28.20:5700) Recv RXTUNE cmd
2026-01-29 01:53:58.119 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETTSC
2026-01-29 01:53:58.119 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETTSC
2026-01-29 01:53:58.119 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETTSC
2026-01-29 01:53:58.119 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.28.20:5700) Recv TXTUNE cmd
2026-01-29 01:53:58.120 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETRXGAIN
2026-01-29 01:53:58.120 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETRXGAIN
2026-01-29 01:53:58.120 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETRXGAIN
2026-01-29 01:53:58.120 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETTSC
2026-01-29 01:53:58.120 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:53:58.120 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:53:58.120 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:53:58.120 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.28.20:5700) Recv NOMTXPOWER cmd
2026-01-29 01:53:58.120 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:53:58.120 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:53:58.120 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:53:58.120 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.28.20:5700) Recv POWERON CMD
2026-01-29 01:53:58.120 [INFO] ctrl_if_trx.py:109 (BTS@172.18.28.20:5700) Starting transceiver...
2026-01-29 01:53:58.120 [INFO] transceiver.py:243 Starting clock generator
2026-01-29 01:53:58.120 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-01-29 01:53:58.120 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:53:58.120 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:53:58.120 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:53:58.120 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETRXGAIN
2026-01-29 01:53:58.121 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:53:58.121 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:53:58.121 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:53:58.121 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 01:53:58.121 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:53:58.121 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:53:58.121 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:53:58.121 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 01:53:58.121 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:53:58.121 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:53:58.121 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:53:58.121 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 01:53:58.121 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:53:58.121 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:53:58.121 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:53:58.121 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 01:53:58.121 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:53:58.121 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:53:58.121 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 01:53:58.121 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:53:58.121 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 01:53:58.121 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 01:53:58.121 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 01:53:58.125 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-01-29 01:53:58.597 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-01-29 01:53:58.648 [DEBUG] fake_trx.py:278 (BTS@172.18.28.20:5700) Recv FAKE_TOA cmd
2026-01-29 01:53:58.651 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:53:58.652 [DEBUG] fake_trx.py:297 (BTS@172.18.28.20:5700) Recv FAKE_RSSI cmd
2026-01-29 01:53:58.655 [DEBUG] fake_trx.py:322 (BTS@172.18.28.20:5700) Recv FAKE_CI cmd
2026-01-29 01:53:58.658 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 01:53:58.659 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 01:53:58.659 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 01:53:58.660 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 01:53:58.660 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 01:53:58.660 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 01:53:58.661 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.28.22:6700) Recv POWERON CMD
2026-01-29 01:53:58.661 [INFO] ctrl_if_trx.py:109 (MS@172.18.28.22:6700) Starting transceiver...
2026-01-29 01:53:59.075 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-01-29 01:53:59.122 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 01:53:59.123 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 01:53:59.125 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 01:53:59.126 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 01:53:59.553 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-01-29 01:54:00.031 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-01-29 01:54:00.123 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 01:54:00.124 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 01:54:00.126 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 01:54:00.127 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 01:54:00.509 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-01-29 01:54:00.987 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-01-29 01:54:01.124 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 01:54:01.124 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 01:54:01.126 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 01:54:01.128 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 01:54:01.464 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-01-29 01:54:01.942 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-01-29 01:54:02.125 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 01:54:02.125 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 01:54:02.127 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 01:54:02.128 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 01:54:02.420 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-01-29 01:54:02.898 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-01-29 01:54:03.125 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 01:54:03.126 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 01:54:03.128 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 01:54:03.129 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 01:54:03.375 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-01-29 01:54:03.853 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-01-29 01:54:04.331 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-01-29 01:54:04.808 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-01-29 01:54:05.286 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-01-29 01:54:05.764 [DEBUG] clck_gen.py:113 IND CLOCK 1632
2026-01-29 01:54:06.242 [DEBUG] clck_gen.py:113 IND CLOCK 1734
2026-01-29 01:54:06.720 [DEBUG] clck_gen.py:113 IND CLOCK 1836
2026-01-29 01:54:07.197 [DEBUG] clck_gen.py:113 IND CLOCK 1938
2026-01-29 01:54:07.676 [DEBUG] clck_gen.py:113 IND CLOCK 2040
2026-01-29 01:54:08.152 [DEBUG] clck_gen.py:113 IND CLOCK 2142
2026-01-29 01:54:08.629 [DEBUG] clck_gen.py:113 IND CLOCK 2244
2026-01-29 01:54:09.107 [DEBUG] clck_gen.py:113 IND CLOCK 2346
2026-01-29 01:54:09.585 [DEBUG] clck_gen.py:113 IND CLOCK 2448
2026-01-29 01:54:10.062 [DEBUG] clck_gen.py:113 IND CLOCK 2550
2026-01-29 01:54:10.540 [DEBUG] clck_gen.py:113 IND CLOCK 2652
2026-01-29 01:54:11.018 [DEBUG] clck_gen.py:113 IND CLOCK 2754
2026-01-29 01:54:11.496 [DEBUG] clck_gen.py:113 IND CLOCK 2856
2026-01-29 01:54:11.973 [DEBUG] clck_gen.py:113 IND CLOCK 2958
2026-01-29 01:54:12.451 [DEBUG] clck_gen.py:113 IND CLOCK 3060
2026-01-29 01:54:12.929 [DEBUG] clck_gen.py:113 IND CLOCK 3162
2026-01-29 01:54:13.407 [DEBUG] clck_gen.py:113 IND CLOCK 3264
2026-01-29 01:54:13.884 [DEBUG] clck_gen.py:113 IND CLOCK 3366
2026-01-29 01:54:14.362 [DEBUG] clck_gen.py:113 IND CLOCK 3468
2026-01-29 01:54:14.840 [DEBUG] clck_gen.py:113 IND CLOCK 3570
2026-01-29 01:54:15.318 [DEBUG] clck_gen.py:113 IND CLOCK 3672
2026-01-29 01:54:15.796 [DEBUG] clck_gen.py:113 IND CLOCK 3774
2026-01-29 01:54:16.274 [DEBUG] clck_gen.py:113 IND CLOCK 3876
2026-01-29 01:54:16.751 [DEBUG] clck_gen.py:113 IND CLOCK 3978
2026-01-29 01:54:17.224 [DEBUG] clck_gen.py:113 IND CLOCK 4080
2026-01-29 01:54:17.702 [DEBUG] clck_gen.py:113 IND CLOCK 4182
2026-01-29 01:54:18.180 [DEBUG] clck_gen.py:113 IND CLOCK 4284
2026-01-29 01:54:18.658 [DEBUG] clck_gen.py:113 IND CLOCK 4386
2026-01-29 01:54:19.135 [DEBUG] clck_gen.py:113 IND CLOCK 4488
2026-01-29 01:54:19.613 [DEBUG] clck_gen.py:113 IND CLOCK 4590
2026-01-29 01:54:20.090 [DEBUG] clck_gen.py:113 IND CLOCK 4692
2026-01-29 01:54:20.568 [DEBUG] clck_gen.py:113 IND CLOCK 4794
2026-01-29 01:54:21.046 [DEBUG] clck_gen.py:113 IND CLOCK 4896
2026-01-29 01:54:21.522 [DEBUG] clck_gen.py:113 IND CLOCK 4998
2026-01-29 01:54:22.000 [DEBUG] clck_gen.py:113 IND CLOCK 5100
2026-01-29 01:54:22.477 [DEBUG] clck_gen.py:113 IND CLOCK 5202
2026-01-29 01:54:22.955 [DEBUG] clck_gen.py:113 IND CLOCK 5304
2026-01-29 01:54:23.433 [DEBUG] clck_gen.py:113 IND CLOCK 5406
2026-01-29 01:54:23.910 [DEBUG] clck_gen.py:113 IND CLOCK 5508
2026-01-29 01:54:24.389 [DEBUG] clck_gen.py:113 IND CLOCK 5610
2026-01-29 01:54:24.866 [DEBUG] clck_gen.py:113 IND CLOCK 5712
2026-01-29 01:54:25.344 [DEBUG] clck_gen.py:113 IND CLOCK 5814
2026-01-29 01:54:25.821 [DEBUG] clck_gen.py:113 IND CLOCK 5916
2026-01-29 01:54:26.140 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 01:54:26.141 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 01:54:26.146 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 01:54:26.146 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 01:54:26.146 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 01:54:26.146 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 01:54:26.149 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 01:54:26.150 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 01:54:26.150 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 01:54:26.150 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.28.20:5700) Recv POWEROFF cmd
2026-01-29 01:54:26.150 [INFO] ctrl_if_trx.py:117 (BTS@172.18.28.20:5700) Stopping transceiver...
2026-01-29 01:54:26.150 [INFO] transceiver.py:246 Stopping clock generator
2026-01-29 01:54:26.150 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 01:54:26.150 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=5988 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 01:54:26.151 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=5988 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 01:54:26.151 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=5988 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 01:54:26.151 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=5988 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 01:54:26.151 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=5988 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 01:54:26.151 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=5988 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 01:54:26.151 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=5988 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 01:54:26.151 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=5988 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 01:54:26.151 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=5989 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 01:54:26.151 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=5989 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 01:54:26.151 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=5989 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 01:54:26.152 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=5989 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 01:54:26.152 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=5989 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 01:54:26.152 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=5989 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 01:54:26.152 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=5989 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 01:54:26.152 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=5989 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 01:54:31.149 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.28.20:5700) Recv POWEROFF cmd
2026-01-29 01:54:31.150 [INFO] ctrl_if_trx.py:117 (BTS@172.18.28.20:5700) Stopping transceiver...
2026-01-29 01:54:31.153 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 01:54:31.153 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 01:54:31.153 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 01:54:31.153 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 01:54:31.161 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 01:54:31.162 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.28.20:5700) Recv SETFORMAT cmd
2026-01-29 01:54:31.163 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.28.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 01:54:31.163 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.28.20:5700) Recv SETFORMAT cmd
2026-01-29 01:54:31.163 [INFO] ctrl_if_trx.py:201 (BTS@172.18.28.20:5700) TRXD header version 1 -> 1
2026-01-29 01:54:31.166 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.28.20:5700/1) Recv RXTUNE cmd
2026-01-29 01:54:31.166 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.28.20:5700/1) Recv TXTUNE cmd
2026-01-29 01:54:31.166 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.28.20:5700/1) Recv SETFORMAT cmd
2026-01-29 01:54:31.166 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.28.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 01:54:31.167 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 01:54:31.167 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.28.20:5700/1) Recv NOMTXPOWER cmd
2026-01-29 01:54:31.168 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.28.20:5700/1) Recv SETFORMAT cmd
2026-01-29 01:54:31.168 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.28.20:5700/1) TRXD header version 1 -> 1
2026-01-29 01:54:31.170 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.28.20:5700/2) Recv RXTUNE cmd
2026-01-29 01:54:31.170 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.28.20:5700/2) Recv TXTUNE cmd
2026-01-29 01:54:31.170 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.28.20:5700/2) Recv SETFORMAT cmd
2026-01-29 01:54:31.170 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.28.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 01:54:31.170 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 01:54:31.170 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.28.20:5700/2) Recv NOMTXPOWER cmd
2026-01-29 01:54:31.170 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.28.20:5700/2) Recv SETFORMAT cmd
2026-01-29 01:54:31.170 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.28.20:5700/2) TRXD header version 1 -> 1
2026-01-29 01:54:31.172 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.28.20:5700/3) Recv RXTUNE cmd
2026-01-29 01:54:31.172 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.28.20:5700/3) Recv TXTUNE cmd
2026-01-29 01:54:31.172 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.28.20:5700/3) Recv SETFORMAT cmd
2026-01-29 01:54:31.172 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.28.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 01:54:31.173 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 01:54:31.173 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.28.20:5700/3) Recv NOMTXPOWER cmd
2026-01-29 01:54:31.173 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.28.20:5700/3) Recv SETFORMAT cmd
2026-01-29 01:54:31.173 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.28.20:5700/3) TRXD header version 1 -> 1
2026-01-29 01:54:31.175 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.28.20:5700) Recv RXTUNE cmd
2026-01-29 01:54:31.175 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETTSC
2026-01-29 01:54:31.175 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETTSC
2026-01-29 01:54:31.175 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETTSC
2026-01-29 01:54:31.175 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.28.20:5700) Recv TXTUNE cmd
2026-01-29 01:54:31.175 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETRXGAIN
2026-01-29 01:54:31.176 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETRXGAIN
2026-01-29 01:54:31.176 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETRXGAIN
2026-01-29 01:54:31.176 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETTSC
2026-01-29 01:54:31.176 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:54:31.176 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:54:31.176 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:54:31.176 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.28.20:5700) Recv NOMTXPOWER cmd
2026-01-29 01:54:31.176 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:54:31.176 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:54:31.176 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:54:31.176 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.28.20:5700) Recv POWERON CMD
2026-01-29 01:54:31.176 [INFO] ctrl_if_trx.py:109 (BTS@172.18.28.20:5700) Starting transceiver...
2026-01-29 01:54:31.176 [INFO] transceiver.py:243 Starting clock generator
2026-01-29 01:54:31.176 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-01-29 01:54:31.176 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:54:31.176 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:54:31.176 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:54:31.176 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETRXGAIN
2026-01-29 01:54:31.176 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:54:31.177 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:54:31.177 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 01:54:31.177 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:54:31.177 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:54:31.177 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:54:31.177 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 01:54:31.177 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:54:31.177 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:54:31.177 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:54:31.177 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 01:54:31.177 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:54:31.177 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:54:31.177 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:54:31.177 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 01:54:31.177 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:54:31.177 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:54:31.177 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:54:31.177 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 01:54:31.177 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:54:31.177 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 01:54:31.177 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 01:54:31.177 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 01:54:31.181 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-01-29 01:54:31.665 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-01-29 01:54:31.702 [DEBUG] fake_trx.py:278 (BTS@172.18.28.20:5700) Recv FAKE_TOA cmd
2026-01-29 01:54:31.703 [DEBUG] fake_trx.py:297 (BTS@172.18.28.20:5700) Recv FAKE_RSSI cmd
2026-01-29 01:54:31.704 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:54:31.705 [DEBUG] fake_trx.py:322 (BTS@172.18.28.20:5700) Recv FAKE_CI cmd
2026-01-29 01:54:31.714 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 01:54:31.714 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 01:54:31.715 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 01:54:31.715 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 01:54:31.719 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 01:54:31.719 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 01:54:31.719 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 01:54:31.719 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.28.20:5700) Recv POWEROFF cmd
2026-01-29 01:54:31.719 [INFO] ctrl_if_trx.py:117 (BTS@172.18.28.20:5700) Stopping transceiver...
2026-01-29 01:54:31.719 [INFO] transceiver.py:246 Stopping clock generator
2026-01-29 01:54:31.719 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 01:54:31.719 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=114 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 01:54:31.719 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=114 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 01:54:36.718 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.28.20:5700) Recv POWEROFF cmd
2026-01-29 01:54:36.718 [INFO] ctrl_if_trx.py:117 (BTS@172.18.28.20:5700) Stopping transceiver...
2026-01-29 01:54:36.720 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 01:54:36.721 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 01:54:36.723 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 01:54:36.725 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 01:54:36.733 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 01:54:36.734 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.28.20:5700) Recv SETFORMAT cmd
2026-01-29 01:54:36.734 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.28.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 01:54:36.735 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.28.20:5700) Recv SETFORMAT cmd
2026-01-29 01:54:36.735 [INFO] ctrl_if_trx.py:201 (BTS@172.18.28.20:5700) TRXD header version 1 -> 1
2026-01-29 01:54:36.737 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.28.20:5700/1) Recv RXTUNE cmd
2026-01-29 01:54:36.737 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.28.20:5700/1) Recv TXTUNE cmd
2026-01-29 01:54:36.737 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.28.20:5700/1) Recv SETFORMAT cmd
2026-01-29 01:54:36.738 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.28.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 01:54:36.738 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 01:54:36.738 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.28.20:5700/1) Recv NOMTXPOWER cmd
2026-01-29 01:54:36.738 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.28.20:5700/1) Recv SETFORMAT cmd
2026-01-29 01:54:36.739 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.28.20:5700/1) TRXD header version 1 -> 1
2026-01-29 01:54:36.739 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.28.20:5700/2) Recv RXTUNE cmd
2026-01-29 01:54:36.739 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.28.20:5700/2) Recv TXTUNE cmd
2026-01-29 01:54:36.739 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.28.20:5700/2) Recv SETFORMAT cmd
2026-01-29 01:54:36.739 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.28.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 01:54:36.739 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 01:54:36.739 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.28.20:5700/2) Recv NOMTXPOWER cmd
2026-01-29 01:54:36.740 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.28.20:5700/2) Recv SETFORMAT cmd
2026-01-29 01:54:36.740 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.28.20:5700/2) TRXD header version 1 -> 1
2026-01-29 01:54:36.741 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.28.20:5700/3) Recv RXTUNE cmd
2026-01-29 01:54:36.741 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.28.20:5700/3) Recv TXTUNE cmd
2026-01-29 01:54:36.741 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.28.20:5700/3) Recv SETFORMAT cmd
2026-01-29 01:54:36.742 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.28.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 01:54:36.742 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 01:54:36.742 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.28.20:5700/3) Recv NOMTXPOWER cmd
2026-01-29 01:54:36.742 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.28.20:5700/3) Recv SETFORMAT cmd
2026-01-29 01:54:36.742 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.28.20:5700/3) TRXD header version 1 -> 1
2026-01-29 01:54:36.744 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.28.20:5700) Recv RXTUNE cmd
2026-01-29 01:54:36.744 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETTSC
2026-01-29 01:54:36.744 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETTSC
2026-01-29 01:54:36.744 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETTSC
2026-01-29 01:54:36.744 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.28.20:5700) Recv TXTUNE cmd
2026-01-29 01:54:36.744 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETRXGAIN
2026-01-29 01:54:36.744 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETRXGAIN
2026-01-29 01:54:36.744 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETRXGAIN
2026-01-29 01:54:36.744 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETTSC
2026-01-29 01:54:36.744 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:54:36.744 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:54:36.744 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:54:36.744 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.28.20:5700) Recv NOMTXPOWER cmd
2026-01-29 01:54:36.744 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:54:36.744 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:54:36.744 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:54:36.744 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.28.20:5700) Recv POWERON CMD
2026-01-29 01:54:36.744 [INFO] ctrl_if_trx.py:109 (BTS@172.18.28.20:5700) Starting transceiver...
2026-01-29 01:54:36.744 [INFO] transceiver.py:243 Starting clock generator
2026-01-29 01:54:36.744 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-01-29 01:54:36.745 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:54:36.745 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:54:36.745 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:54:36.745 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETRXGAIN
2026-01-29 01:54:36.745 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:54:36.745 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:54:36.745 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:54:36.745 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 01:54:36.745 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:54:36.745 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:54:36.745 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:54:36.745 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 01:54:36.745 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:54:36.745 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:54:36.745 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:54:36.745 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 01:54:36.745 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:54:36.745 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:54:36.745 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:54:36.745 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 01:54:36.745 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:54:36.745 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:54:36.745 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 01:54:36.745 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:54:36.745 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 01:54:36.745 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 01:54:36.745 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 01:54:36.749 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-01-29 01:54:37.233 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-01-29 01:54:37.273 [DEBUG] fake_trx.py:278 (BTS@172.18.28.20:5700) Recv FAKE_TOA cmd
2026-01-29 01:54:37.275 [DEBUG] fake_trx.py:297 (BTS@172.18.28.20:5700) Recv FAKE_RSSI cmd
2026-01-29 01:54:37.276 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:54:37.277 [DEBUG] fake_trx.py:322 (BTS@172.18.28.20:5700) Recv FAKE_CI cmd
2026-01-29 01:54:37.285 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 01:54:37.285 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 01:54:37.285 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 01:54:37.285 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 01:54:37.288 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 01:54:37.288 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 01:54:37.288 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 01:54:37.288 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.28.20:5700) Recv POWEROFF cmd
2026-01-29 01:54:37.288 [INFO] ctrl_if_trx.py:117 (BTS@172.18.28.20:5700) Stopping transceiver...
2026-01-29 01:54:37.288 [INFO] transceiver.py:246 Stopping clock generator
2026-01-29 01:54:37.288 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 01:54:37.288 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=115 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 01:54:37.288 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=115 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 01:54:37.288 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=115 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 01:54:37.288 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=115 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 01:54:37.288 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=115 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 01:54:37.288 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=115 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 01:54:37.288 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=115 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 01:54:37.288 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=115 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 01:54:42.288 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.28.20:5700) Recv POWEROFF cmd
2026-01-29 01:54:42.289 [INFO] ctrl_if_trx.py:117 (BTS@172.18.28.20:5700) Stopping transceiver...
2026-01-29 01:54:42.290 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 01:54:42.292 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 01:54:42.292 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 01:54:42.292 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 01:54:42.299 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 01:54:42.300 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.28.20:5700) Recv SETFORMAT cmd
2026-01-29 01:54:42.300 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.28.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 01:54:42.300 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.28.20:5700) Recv SETFORMAT cmd
2026-01-29 01:54:42.300 [INFO] ctrl_if_trx.py:201 (BTS@172.18.28.20:5700) TRXD header version 1 -> 1
2026-01-29 01:54:42.303 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.28.20:5700/1) Recv RXTUNE cmd
2026-01-29 01:54:42.304 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.28.20:5700/1) Recv TXTUNE cmd
2026-01-29 01:54:42.304 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.28.20:5700/1) Recv SETFORMAT cmd
2026-01-29 01:54:42.305 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.28.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 01:54:42.305 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 01:54:42.305 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.28.20:5700/1) Recv NOMTXPOWER cmd
2026-01-29 01:54:42.306 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.28.20:5700/1) Recv SETFORMAT cmd
2026-01-29 01:54:42.306 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.28.20:5700/1) TRXD header version 1 -> 1
2026-01-29 01:54:42.307 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.28.20:5700/2) Recv RXTUNE cmd
2026-01-29 01:54:42.307 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.28.20:5700/2) Recv TXTUNE cmd
2026-01-29 01:54:42.307 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.28.20:5700/2) Recv SETFORMAT cmd
2026-01-29 01:54:42.307 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.28.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 01:54:42.308 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 01:54:42.308 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.28.20:5700/2) Recv NOMTXPOWER cmd
2026-01-29 01:54:42.308 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.28.20:5700/2) Recv SETFORMAT cmd
2026-01-29 01:54:42.308 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.28.20:5700/2) TRXD header version 1 -> 1
2026-01-29 01:54:42.309 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.28.20:5700/3) Recv RXTUNE cmd
2026-01-29 01:54:42.310 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.28.20:5700/3) Recv TXTUNE cmd
2026-01-29 01:54:42.310 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.28.20:5700/3) Recv SETFORMAT cmd
2026-01-29 01:54:42.310 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.28.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 01:54:42.310 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 01:54:42.310 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.28.20:5700/3) Recv NOMTXPOWER cmd
2026-01-29 01:54:42.310 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.28.20:5700/3) Recv SETFORMAT cmd
2026-01-29 01:54:42.310 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.28.20:5700/3) TRXD header version 1 -> 1
2026-01-29 01:54:42.313 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.28.20:5700) Recv RXTUNE cmd
2026-01-29 01:54:42.313 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETTSC
2026-01-29 01:54:42.313 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETTSC
2026-01-29 01:54:42.313 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETTSC
2026-01-29 01:54:42.313 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.28.20:5700) Recv TXTUNE cmd
2026-01-29 01:54:42.313 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETRXGAIN
2026-01-29 01:54:42.313 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETRXGAIN
2026-01-29 01:54:42.313 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETRXGAIN
2026-01-29 01:54:42.313 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETTSC
2026-01-29 01:54:42.313 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:54:42.313 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:54:42.313 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:54:42.313 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.28.20:5700) Recv NOMTXPOWER cmd
2026-01-29 01:54:42.313 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:54:42.313 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:54:42.313 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:54:42.313 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.28.20:5700) Recv POWERON CMD
2026-01-29 01:54:42.313 [INFO] ctrl_if_trx.py:109 (BTS@172.18.28.20:5700) Starting transceiver...
2026-01-29 01:54:42.313 [INFO] transceiver.py:243 Starting clock generator
2026-01-29 01:54:42.314 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-01-29 01:54:42.314 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:54:42.314 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:54:42.314 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:54:42.314 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETRXGAIN
2026-01-29 01:54:42.314 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:54:42.314 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:54:42.314 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:54:42.314 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 01:54:42.314 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:54:42.314 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:54:42.314 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:54:42.314 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 01:54:42.314 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:54:42.314 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:54:42.314 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:54:42.314 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 01:54:42.314 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:54:42.314 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:54:42.315 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:54:42.315 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 01:54:42.315 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:54:42.315 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:54:42.315 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:54:42.315 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 01:54:42.315 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 01:54:42.315 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 01:54:42.315 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 01:54:42.318 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-01-29 01:54:42.803 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-01-29 01:54:42.842 [DEBUG] fake_trx.py:278 (BTS@172.18.28.20:5700) Recv FAKE_TOA cmd
2026-01-29 01:54:42.844 [DEBUG] fake_trx.py:297 (BTS@172.18.28.20:5700) Recv FAKE_RSSI cmd
2026-01-29 01:54:42.845 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:54:42.846 [DEBUG] fake_trx.py:322 (BTS@172.18.28.20:5700) Recv FAKE_CI cmd
2026-01-29 01:54:42.858 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 01:54:42.858 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 01:54:42.858 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 01:54:42.859 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 01:54:42.864 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 01:54:42.864 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 01:54:42.864 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 01:54:42.864 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.28.20:5700) Recv POWEROFF cmd
2026-01-29 01:54:42.864 [INFO] ctrl_if_trx.py:117 (BTS@172.18.28.20:5700) Stopping transceiver...
2026-01-29 01:54:42.865 [INFO] transceiver.py:246 Stopping clock generator
2026-01-29 01:54:42.865 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 01:54:42.865 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=115 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 01:54:42.865 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=115 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 01:54:47.862 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.28.20:5700) Recv POWEROFF cmd
2026-01-29 01:54:47.862 [INFO] ctrl_if_trx.py:117 (BTS@172.18.28.20:5700) Stopping transceiver...
2026-01-29 01:54:47.864 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 01:54:47.865 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 01:54:47.866 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 01:54:47.866 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 01:54:47.872 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 01:54:47.873 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.28.20:5700) Recv SETFORMAT cmd
2026-01-29 01:54:47.873 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.28.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 01:54:47.874 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.28.20:5700) Recv SETFORMAT cmd
2026-01-29 01:54:47.874 [INFO] ctrl_if_trx.py:201 (BTS@172.18.28.20:5700) TRXD header version 1 -> 1
2026-01-29 01:54:47.877 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.28.20:5700/1) Recv RXTUNE cmd
2026-01-29 01:54:47.877 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.28.20:5700/1) Recv TXTUNE cmd
2026-01-29 01:54:47.877 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.28.20:5700/1) Recv SETFORMAT cmd
2026-01-29 01:54:47.877 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.28.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 01:54:47.877 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 01:54:47.877 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.28.20:5700/1) Recv NOMTXPOWER cmd
2026-01-29 01:54:47.878 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.28.20:5700/1) Recv SETFORMAT cmd
2026-01-29 01:54:47.878 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.28.20:5700/1) TRXD header version 1 -> 1
2026-01-29 01:54:47.880 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.28.20:5700/2) Recv RXTUNE cmd
2026-01-29 01:54:47.880 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.28.20:5700/2) Recv TXTUNE cmd
2026-01-29 01:54:47.880 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.28.20:5700/2) Recv SETFORMAT cmd
2026-01-29 01:54:47.880 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.28.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 01:54:47.881 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 01:54:47.881 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.28.20:5700/2) Recv NOMTXPOWER cmd
2026-01-29 01:54:47.881 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.28.20:5700/2) Recv SETFORMAT cmd
2026-01-29 01:54:47.881 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.28.20:5700/2) TRXD header version 1 -> 1
2026-01-29 01:54:47.883 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.28.20:5700/3) Recv RXTUNE cmd
2026-01-29 01:54:47.883 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.28.20:5700/3) Recv TXTUNE cmd
2026-01-29 01:54:47.883 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.28.20:5700/3) Recv SETFORMAT cmd
2026-01-29 01:54:47.883 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.28.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 01:54:47.883 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 01:54:47.883 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.28.20:5700/3) Recv NOMTXPOWER cmd
2026-01-29 01:54:47.884 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.28.20:5700/3) Recv SETFORMAT cmd
2026-01-29 01:54:47.884 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.28.20:5700/3) TRXD header version 1 -> 1
2026-01-29 01:54:47.887 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.28.20:5700) Recv RXTUNE cmd
2026-01-29 01:54:47.887 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETTSC
2026-01-29 01:54:47.887 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETTSC
2026-01-29 01:54:47.887 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.28.20:5700) Recv TXTUNE cmd
2026-01-29 01:54:47.887 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETTSC
2026-01-29 01:54:47.887 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETRXGAIN
2026-01-29 01:54:47.887 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETRXGAIN
2026-01-29 01:54:47.887 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETTSC
2026-01-29 01:54:47.887 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETRXGAIN
2026-01-29 01:54:47.887 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:54:47.887 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:54:47.887 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.28.20:5700) Recv NOMTXPOWER cmd
2026-01-29 01:54:47.887 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:54:47.887 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:54:47.887 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:54:47.887 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.28.20:5700) Recv POWERON CMD
2026-01-29 01:54:47.887 [INFO] ctrl_if_trx.py:109 (BTS@172.18.28.20:5700) Starting transceiver...
2026-01-29 01:54:47.887 [INFO] transceiver.py:243 Starting clock generator
2026-01-29 01:54:47.888 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-01-29 01:54:47.888 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:54:47.888 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:54:47.888 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:54:47.888 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETRXGAIN
2026-01-29 01:54:47.888 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:54:47.888 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:54:47.888 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:54:47.888 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 01:54:47.888 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:54:47.888 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:54:47.888 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:54:47.888 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 01:54:47.888 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:54:47.888 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:54:47.888 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 01:54:47.888 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:54:47.888 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:54:47.889 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 01:54:47.889 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:54:47.889 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:54:47.889 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 01:54:47.889 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:54:47.889 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 01:54:47.889 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:54:47.889 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 01:54:47.889 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:54:47.889 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 01:54:47.889 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:54:47.892 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-01-29 01:54:48.376 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-01-29 01:54:48.420 [DEBUG] fake_trx.py:278 (BTS@172.18.28.20:5700) Recv FAKE_TOA cmd
2026-01-29 01:54:48.423 [DEBUG] fake_trx.py:297 (BTS@172.18.28.20:5700) Recv FAKE_RSSI cmd
2026-01-29 01:54:48.424 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:54:48.424 [DEBUG] fake_trx.py:322 (BTS@172.18.28.20:5700) Recv FAKE_CI cmd
2026-01-29 01:54:48.428 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 01:54:48.428 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 01:54:48.429 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 01:54:48.429 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 01:54:48.429 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 01:54:48.430 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 01:54:48.430 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.28.22:6700) Recv POWERON CMD
2026-01-29 01:54:48.430 [INFO] ctrl_if_trx.py:109 (MS@172.18.28.22:6700) Starting transceiver...
2026-01-29 01:54:48.853 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-01-29 01:54:48.890 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 01:54:48.891 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 01:54:48.892 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 01:54:48.896 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 01:54:49.331 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-01-29 01:54:49.809 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-01-29 01:54:49.891 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 01:54:49.892 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 01:54:49.892 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 01:54:49.897 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 01:54:50.286 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-01-29 01:54:50.764 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-01-29 01:54:50.892 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 01:54:50.893 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 01:54:50.893 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 01:54:50.898 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 01:54:51.242 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-01-29 01:54:51.720 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-01-29 01:54:51.893 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 01:54:51.893 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 01:54:51.894 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 01:54:51.899 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 01:54:52.197 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-01-29 01:54:52.676 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-01-29 01:54:52.894 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 01:54:52.894 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 01:54:52.894 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 01:54:52.900 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 01:54:53.152 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-01-29 01:54:53.629 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-01-29 01:54:54.107 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-01-29 01:54:54.585 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-01-29 01:54:55.063 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-01-29 01:54:55.539 [DEBUG] clck_gen.py:113 IND CLOCK 1632
2026-01-29 01:54:56.017 [DEBUG] clck_gen.py:113 IND CLOCK 1734
2026-01-29 01:54:56.475 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 01:54:56.475 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 01:54:56.481 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 01:54:56.482 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 01:54:56.482 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 01:54:56.482 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 01:54:56.487 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 01:54:56.487 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 01:54:56.487 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 01:54:56.488 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 01:54:56.488 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.28.20:5700) Recv POWEROFF cmd
2026-01-29 01:54:56.488 [INFO] ctrl_if_trx.py:117 (BTS@172.18.28.20:5700) Stopping transceiver...
2026-01-29 01:54:56.488 [INFO] transceiver.py:246 Stopping clock generator
2026-01-29 01:54:56.488 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=1837 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 01:54:56.488 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=1837 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 01:54:56.488 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=1837 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 01:54:56.489 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=1837 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 01:54:56.489 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=1837 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 01:54:56.489 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=1837 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 01:54:56.489 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=1837 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 01:54:56.489 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=1837 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 01:54:56.489 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=1838 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 01:55:01.483 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.28.20:5700) Recv POWEROFF cmd
2026-01-29 01:55:01.484 [INFO] ctrl_if_trx.py:117 (BTS@172.18.28.20:5700) Stopping transceiver...
2026-01-29 01:55:01.485 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 01:55:01.486 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 01:55:01.487 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 01:55:01.488 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 01:55:01.496 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 01:55:01.498 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.28.20:5700) Recv SETFORMAT cmd
2026-01-29 01:55:01.498 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.28.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 01:55:01.499 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.28.20:5700) Recv SETFORMAT cmd
2026-01-29 01:55:01.499 [INFO] ctrl_if_trx.py:201 (BTS@172.18.28.20:5700) TRXD header version 1 -> 1
2026-01-29 01:55:01.502 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.28.20:5700/1) Recv RXTUNE cmd
2026-01-29 01:55:01.503 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.28.20:5700/1) Recv TXTUNE cmd
2026-01-29 01:55:01.503 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.28.20:5700/1) Recv SETFORMAT cmd
2026-01-29 01:55:01.503 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.28.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 01:55:01.504 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 01:55:01.504 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.28.20:5700/1) Recv NOMTXPOWER cmd
2026-01-29 01:55:01.504 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.28.20:5700/1) Recv SETFORMAT cmd
2026-01-29 01:55:01.505 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.28.20:5700/1) TRXD header version 1 -> 1
2026-01-29 01:55:01.505 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.28.20:5700/2) Recv RXTUNE cmd
2026-01-29 01:55:01.506 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.28.20:5700/2) Recv TXTUNE cmd
2026-01-29 01:55:01.506 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.28.20:5700/2) Recv SETFORMAT cmd
2026-01-29 01:55:01.506 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.28.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 01:55:01.506 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 01:55:01.506 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.28.20:5700/2) Recv NOMTXPOWER cmd
2026-01-29 01:55:01.507 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.28.20:5700/2) Recv SETFORMAT cmd
2026-01-29 01:55:01.507 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.28.20:5700/2) TRXD header version 1 -> 1
2026-01-29 01:55:01.508 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.28.20:5700/3) Recv RXTUNE cmd
2026-01-29 01:55:01.508 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.28.20:5700/3) Recv TXTUNE cmd
2026-01-29 01:55:01.508 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.28.20:5700/3) Recv SETFORMAT cmd
2026-01-29 01:55:01.508 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.28.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 01:55:01.509 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 01:55:01.509 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.28.20:5700/3) Recv NOMTXPOWER cmd
2026-01-29 01:55:01.509 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.28.20:5700/3) Recv SETFORMAT cmd
2026-01-29 01:55:01.509 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.28.20:5700/3) TRXD header version 1 -> 1
2026-01-29 01:55:01.511 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.28.20:5700) Recv RXTUNE cmd
2026-01-29 01:55:01.511 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETTSC
2026-01-29 01:55:01.511 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETTSC
2026-01-29 01:55:01.511 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETTSC
2026-01-29 01:55:01.511 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.28.20:5700) Recv TXTUNE cmd
2026-01-29 01:55:01.511 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETRXGAIN
2026-01-29 01:55:01.511 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETRXGAIN
2026-01-29 01:55:01.511 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETRXGAIN
2026-01-29 01:55:01.512 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETTSC
2026-01-29 01:55:01.512 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:55:01.512 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:55:01.512 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:55:01.512 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.28.20:5700) Recv NOMTXPOWER cmd
2026-01-29 01:55:01.512 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:55:01.512 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:55:01.512 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:55:01.512 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.28.20:5700) Recv POWERON CMD
2026-01-29 01:55:01.512 [INFO] ctrl_if_trx.py:109 (BTS@172.18.28.20:5700) Starting transceiver...
2026-01-29 01:55:01.512 [INFO] transceiver.py:243 Starting clock generator
2026-01-29 01:55:01.512 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-01-29 01:55:01.512 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:55:01.512 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:55:01.512 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:55:01.512 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETRXGAIN
2026-01-29 01:55:01.512 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:55:01.512 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:55:01.512 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:55:01.512 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 01:55:01.512 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:55:01.512 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:55:01.513 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:55:01.513 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 01:55:01.513 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:55:01.513 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:55:01.513 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:55:01.513 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 01:55:01.513 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:55:01.513 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:55:01.513 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 01:55:01.513 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:55:01.513 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:55:01.513 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:55:01.513 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 01:55:01.513 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:55:01.513 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 01:55:01.513 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 01:55:01.513 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 01:55:01.517 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-01-29 01:55:02.001 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-01-29 01:55:02.034 [DEBUG] fake_trx.py:278 (BTS@172.18.28.20:5700) Recv FAKE_TOA cmd
2026-01-29 01:55:02.037 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:55:02.037 [DEBUG] fake_trx.py:297 (BTS@172.18.28.20:5700) Recv FAKE_RSSI cmd
2026-01-29 01:55:02.040 [DEBUG] fake_trx.py:322 (BTS@172.18.28.20:5700) Recv FAKE_CI cmd
2026-01-29 01:55:02.045 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 01:55:02.045 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 01:55:02.045 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 01:55:02.046 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 01:55:02.046 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 01:55:02.047 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 01:55:02.047 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.28.22:6700) Recv POWERON CMD
2026-01-29 01:55:02.047 [INFO] ctrl_if_trx.py:109 (MS@172.18.28.22:6700) Starting transceiver...
2026-01-29 01:55:02.478 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-01-29 01:55:02.515 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 01:55:02.516 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 01:55:02.516 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 01:55:02.516 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 01:55:02.956 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-01-29 01:55:03.434 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-01-29 01:55:03.516 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 01:55:03.516 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 01:55:03.517 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 01:55:03.517 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 01:55:03.912 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-01-29 01:55:04.389 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-01-29 01:55:04.517 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 01:55:04.517 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 01:55:04.517 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 01:55:04.518 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 01:55:04.867 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-01-29 01:55:05.345 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-01-29 01:55:05.517 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 01:55:05.518 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 01:55:05.518 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 01:55:05.518 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 01:55:05.823 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-01-29 01:55:06.300 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-01-29 01:55:06.518 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 01:55:06.518 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 01:55:06.519 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 01:55:06.519 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 01:55:06.778 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-01-29 01:55:07.256 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-01-29 01:55:07.734 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-01-29 01:55:08.211 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-01-29 01:55:08.688 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-01-29 01:55:09.166 [DEBUG] clck_gen.py:113 IND CLOCK 1632
2026-01-29 01:55:09.643 [DEBUG] clck_gen.py:113 IND CLOCK 1734
2026-01-29 01:55:10.100 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 01:55:10.101 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 01:55:10.107 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 01:55:10.108 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 01:55:10.108 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 01:55:10.108 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 01:55:10.114 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 01:55:10.114 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 01:55:10.114 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 01:55:10.114 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 01:55:10.115 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.28.20:5700) Recv POWEROFF cmd
2026-01-29 01:55:10.115 [INFO] ctrl_if_trx.py:117 (BTS@172.18.28.20:5700) Stopping transceiver...
2026-01-29 01:55:10.115 [INFO] transceiver.py:246 Stopping clock generator
2026-01-29 01:55:10.115 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=1836 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 01:55:10.115 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=1836 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 01:55:10.115 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=1836 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 01:55:10.115 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=1836 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 01:55:10.115 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=1836 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 01:55:10.115 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=1836 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 01:55:10.115 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=1837 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 01:55:10.116 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=1837 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 01:55:10.116 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=1837 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 01:55:10.116 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=1837 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 01:55:10.116 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=1837 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 01:55:10.116 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=1837 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 01:55:10.116 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=1837 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 01:55:10.116 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=1837 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 01:55:10.116 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=1838 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 01:55:10.116 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=1838 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 01:55:10.116 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=1838 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 01:55:10.116 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=1838 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 01:55:10.116 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=1838 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 01:55:10.116 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=1838 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 01:55:10.116 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=1838 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 01:55:10.116 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=1838 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 01:55:15.111 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.28.20:5700) Recv POWEROFF cmd
2026-01-29 01:55:15.111 [INFO] ctrl_if_trx.py:117 (BTS@172.18.28.20:5700) Stopping transceiver...
2026-01-29 01:55:15.113 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 01:55:15.114 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 01:55:15.114 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 01:55:15.114 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 01:55:15.121 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 01:55:15.122 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.28.20:5700) Recv SETFORMAT cmd
2026-01-29 01:55:15.122 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.28.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 01:55:15.122 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.28.20:5700) Recv SETFORMAT cmd
2026-01-29 01:55:15.122 [INFO] ctrl_if_trx.py:201 (BTS@172.18.28.20:5700) TRXD header version 1 -> 1
2026-01-29 01:55:15.125 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.28.20:5700/1) Recv RXTUNE cmd
2026-01-29 01:55:15.125 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.28.20:5700/1) Recv TXTUNE cmd
2026-01-29 01:55:15.126 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.28.20:5700/1) Recv SETFORMAT cmd
2026-01-29 01:55:15.126 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.28.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 01:55:15.126 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 01:55:15.126 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.28.20:5700/1) Recv NOMTXPOWER cmd
2026-01-29 01:55:15.126 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.28.20:5700/1) Recv SETFORMAT cmd
2026-01-29 01:55:15.126 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.28.20:5700/1) TRXD header version 1 -> 1
2026-01-29 01:55:15.129 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.28.20:5700/2) Recv RXTUNE cmd
2026-01-29 01:55:15.129 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.28.20:5700/2) Recv TXTUNE cmd
2026-01-29 01:55:15.129 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.28.20:5700/2) Recv SETFORMAT cmd
2026-01-29 01:55:15.129 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.28.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 01:55:15.129 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 01:55:15.129 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.28.20:5700/2) Recv NOMTXPOWER cmd
2026-01-29 01:55:15.129 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.28.20:5700/2) Recv SETFORMAT cmd
2026-01-29 01:55:15.129 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.28.20:5700/2) TRXD header version 1 -> 1
2026-01-29 01:55:15.132 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.28.20:5700/3) Recv RXTUNE cmd
2026-01-29 01:55:15.132 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.28.20:5700/3) Recv TXTUNE cmd
2026-01-29 01:55:15.132 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.28.20:5700/3) Recv SETFORMAT cmd
2026-01-29 01:55:15.133 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.28.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 01:55:15.133 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 01:55:15.133 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.28.20:5700/3) Recv NOMTXPOWER cmd
2026-01-29 01:55:15.133 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.28.20:5700/3) Recv SETFORMAT cmd
2026-01-29 01:55:15.133 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.28.20:5700/3) TRXD header version 1 -> 1
2026-01-29 01:55:15.137 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.28.20:5700) Recv RXTUNE cmd
2026-01-29 01:55:15.137 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETTSC
2026-01-29 01:55:15.137 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETTSC
2026-01-29 01:55:15.137 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETTSC
2026-01-29 01:55:15.137 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.28.20:5700) Recv TXTUNE cmd
2026-01-29 01:55:15.137 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETRXGAIN
2026-01-29 01:55:15.137 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETRXGAIN
2026-01-29 01:55:15.137 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETRXGAIN
2026-01-29 01:55:15.137 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETTSC
2026-01-29 01:55:15.137 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:55:15.137 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:55:15.137 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.28.20:5700) Recv NOMTXPOWER cmd
2026-01-29 01:55:15.137 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:55:15.137 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:55:15.137 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:55:15.137 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.28.20:5700) Recv POWERON CMD
2026-01-29 01:55:15.138 [INFO] ctrl_if_trx.py:109 (BTS@172.18.28.20:5700) Starting transceiver...
2026-01-29 01:55:15.138 [INFO] transceiver.py:243 Starting clock generator
2026-01-29 01:55:15.138 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-01-29 01:55:15.138 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:55:15.138 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:55:15.138 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:55:15.138 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETRXGAIN
2026-01-29 01:55:15.138 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:55:15.138 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:55:15.138 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 01:55:15.138 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:55:15.139 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:55:15.139 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:55:15.139 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 01:55:15.139 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:55:15.139 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:55:15.139 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:55:15.139 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 01:55:15.139 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:55:15.139 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:55:15.139 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:55:15.139 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 01:55:15.139 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:55:15.139 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:55:15.139 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 01:55:15.139 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:55:15.139 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:55:15.139 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 01:55:15.139 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:55:15.140 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 01:55:15.140 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 01:55:15.143 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-01-29 01:55:15.619 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-01-29 01:55:15.672 [DEBUG] fake_trx.py:278 (BTS@172.18.28.20:5700) Recv FAKE_TOA cmd
2026-01-29 01:55:15.674 [DEBUG] fake_trx.py:297 (BTS@172.18.28.20:5700) Recv FAKE_RSSI cmd
2026-01-29 01:55:15.675 [DEBUG] fake_trx.py:322 (BTS@172.18.28.20:5700) Recv FAKE_CI cmd
2026-01-29 01:55:15.677 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:55:15.678 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 01:55:15.678 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 01:55:15.678 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 01:55:15.679 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 01:55:15.679 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 01:55:15.679 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 01:55:15.679 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.28.22:6700) Recv POWERON CMD
2026-01-29 01:55:15.679 [INFO] ctrl_if_trx.py:109 (MS@172.18.28.22:6700) Starting transceiver...
2026-01-29 01:55:16.097 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-01-29 01:55:16.141 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 01:55:16.141 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 01:55:16.146 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 01:55:16.150 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 01:55:16.574 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-01-29 01:55:17.052 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-01-29 01:55:17.141 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 01:55:17.142 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 01:55:17.147 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 01:55:17.151 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 01:55:17.530 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-01-29 01:55:18.008 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-01-29 01:55:18.142 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 01:55:18.143 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 01:55:18.148 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 01:55:18.152 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 01:55:18.486 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-01-29 01:55:18.962 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-01-29 01:55:19.143 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 01:55:19.143 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 01:55:19.149 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 01:55:19.152 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 01:55:19.439 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-01-29 01:55:19.915 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-01-29 01:55:20.144 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 01:55:20.145 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 01:55:20.150 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 01:55:20.152 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 01:55:20.393 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-01-29 01:55:20.870 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-01-29 01:55:21.348 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-01-29 01:55:21.826 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-01-29 01:55:22.304 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-01-29 01:55:22.782 [DEBUG] clck_gen.py:113 IND CLOCK 1632
2026-01-29 01:55:23.260 [DEBUG] clck_gen.py:113 IND CLOCK 1734
2026-01-29 01:55:23.719 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 01:55:23.720 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 01:55:23.724 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 01:55:23.725 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 01:55:23.725 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 01:55:23.725 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 01:55:23.728 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 01:55:23.729 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 01:55:23.729 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 01:55:23.729 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 01:55:23.729 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.28.20:5700) Recv POWEROFF cmd
2026-01-29 01:55:23.729 [INFO] ctrl_if_trx.py:117 (BTS@172.18.28.20:5700) Stopping transceiver...
2026-01-29 01:55:23.729 [INFO] transceiver.py:246 Stopping clock generator
2026-01-29 01:55:23.730 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=1837 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 01:55:23.730 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=1837 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 01:55:23.730 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=1837 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 01:55:23.730 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=1837 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 01:55:23.730 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=1837 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 01:55:23.730 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=1837 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 01:55:28.727 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.28.20:5700) Recv POWEROFF cmd
2026-01-29 01:55:28.727 [INFO] ctrl_if_trx.py:117 (BTS@172.18.28.20:5700) Stopping transceiver...
2026-01-29 01:55:28.729 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 01:55:28.730 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 01:55:28.732 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 01:55:28.734 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 01:55:28.742 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 01:55:28.742 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.28.20:5700) Recv SETFORMAT cmd
2026-01-29 01:55:28.742 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.28.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 01:55:28.743 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.28.20:5700) Recv SETFORMAT cmd
2026-01-29 01:55:28.743 [INFO] ctrl_if_trx.py:201 (BTS@172.18.28.20:5700) TRXD header version 1 -> 1
2026-01-29 01:55:28.744 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.28.20:5700/1) Recv RXTUNE cmd
2026-01-29 01:55:28.744 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.28.20:5700/1) Recv TXTUNE cmd
2026-01-29 01:55:28.744 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.28.20:5700/1) Recv SETFORMAT cmd
2026-01-29 01:55:28.745 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.28.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 01:55:28.745 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 01:55:28.745 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.28.20:5700/1) Recv NOMTXPOWER cmd
2026-01-29 01:55:28.745 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.28.20:5700/1) Recv SETFORMAT cmd
2026-01-29 01:55:28.745 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.28.20:5700/1) TRXD header version 1 -> 1
2026-01-29 01:55:28.746 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.28.20:5700/2) Recv RXTUNE cmd
2026-01-29 01:55:28.746 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.28.20:5700/2) Recv TXTUNE cmd
2026-01-29 01:55:28.747 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.28.20:5700/2) Recv SETFORMAT cmd
2026-01-29 01:55:28.747 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.28.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 01:55:28.747 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 01:55:28.747 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.28.20:5700/2) Recv NOMTXPOWER cmd
2026-01-29 01:55:28.747 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.28.20:5700/2) Recv SETFORMAT cmd
2026-01-29 01:55:28.747 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.28.20:5700/2) TRXD header version 1 -> 1
2026-01-29 01:55:28.748 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.28.20:5700/3) Recv RXTUNE cmd
2026-01-29 01:55:28.748 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.28.20:5700/3) Recv TXTUNE cmd
2026-01-29 01:55:28.748 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.28.20:5700/3) Recv SETFORMAT cmd
2026-01-29 01:55:28.748 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.28.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 01:55:28.748 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 01:55:28.748 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.28.20:5700/3) Recv NOMTXPOWER cmd
2026-01-29 01:55:28.749 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.28.20:5700/3) Recv SETFORMAT cmd
2026-01-29 01:55:28.749 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.28.20:5700/3) TRXD header version 1 -> 1
2026-01-29 01:55:28.750 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.28.20:5700) Recv RXTUNE cmd
2026-01-29 01:55:28.751 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETTSC
2026-01-29 01:55:28.751 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETTSC
2026-01-29 01:55:28.751 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETTSC
2026-01-29 01:55:28.751 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.28.20:5700) Recv TXTUNE cmd
2026-01-29 01:55:28.751 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETRXGAIN
2026-01-29 01:55:28.751 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETRXGAIN
2026-01-29 01:55:28.751 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETRXGAIN
2026-01-29 01:55:28.751 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETTSC
2026-01-29 01:55:28.751 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:55:28.751 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:55:28.751 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:55:28.751 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.28.20:5700) Recv NOMTXPOWER cmd
2026-01-29 01:55:28.751 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:55:28.751 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:55:28.751 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:55:28.751 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.28.20:5700) Recv POWERON CMD
2026-01-29 01:55:28.751 [INFO] ctrl_if_trx.py:109 (BTS@172.18.28.20:5700) Starting transceiver...
2026-01-29 01:55:28.751 [INFO] transceiver.py:243 Starting clock generator
2026-01-29 01:55:28.751 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-01-29 01:55:28.751 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:55:28.751 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:55:28.751 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:55:28.751 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETRXGAIN
2026-01-29 01:55:28.751 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:55:28.751 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:55:28.752 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:55:28.752 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 01:55:28.752 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:55:28.752 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:55:28.752 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:55:28.752 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 01:55:28.752 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:55:28.752 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:55:28.752 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:55:28.752 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 01:55:28.752 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:55:28.752 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:55:28.752 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:55:28.752 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 01:55:28.752 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:55:28.752 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:55:28.752 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:55:28.752 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 01:55:28.752 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 01:55:28.752 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 01:55:28.753 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 01:55:28.756 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-01-29 01:55:29.238 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-01-29 01:55:29.272 [DEBUG] fake_trx.py:278 (BTS@172.18.28.20:5700) Recv FAKE_TOA cmd
2026-01-29 01:55:29.274 [DEBUG] fake_trx.py:297 (BTS@172.18.28.20:5700) Recv FAKE_RSSI cmd
2026-01-29 01:55:29.275 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:55:29.275 [DEBUG] fake_trx.py:322 (BTS@172.18.28.20:5700) Recv FAKE_CI cmd
2026-01-29 01:55:29.277 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 01:55:29.277 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 01:55:29.277 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 01:55:29.278 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 01:55:29.278 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 01:55:29.278 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 01:55:29.278 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.28.22:6700) Recv POWERON CMD
2026-01-29 01:55:29.278 [INFO] ctrl_if_trx.py:109 (MS@172.18.28.22:6700) Starting transceiver...
2026-01-29 01:55:29.715 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-01-29 01:55:29.754 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 01:55:29.754 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 01:55:29.756 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 01:55:29.757 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 01:55:30.192 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-01-29 01:55:30.670 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-01-29 01:55:30.756 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 01:55:30.756 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 01:55:30.757 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 01:55:30.758 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 01:55:31.147 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-01-29 01:55:31.625 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-01-29 01:55:31.757 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 01:55:31.757 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 01:55:31.759 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 01:55:31.759 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 01:55:32.103 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-01-29 01:55:32.581 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-01-29 01:55:32.757 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 01:55:32.758 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 01:55:32.760 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 01:55:32.760 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 01:55:33.058 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-01-29 01:55:33.536 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-01-29 01:55:33.758 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 01:55:33.758 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 01:55:33.761 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 01:55:33.761 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 01:55:34.014 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-01-29 01:55:34.492 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-01-29 01:55:34.970 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-01-29 01:55:35.448 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-01-29 01:55:35.925 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-01-29 01:55:36.403 [DEBUG] clck_gen.py:113 IND CLOCK 1632
2026-01-29 01:55:36.881 [DEBUG] clck_gen.py:113 IND CLOCK 1734
2026-01-29 01:55:37.289 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 01:55:37.289 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 01:55:37.296 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 01:55:37.296 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 01:55:37.296 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 01:55:37.296 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 01:55:37.302 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 01:55:37.302 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 01:55:37.303 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 01:55:37.303 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 01:55:37.303 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.28.20:5700) Recv POWEROFF cmd
2026-01-29 01:55:37.303 [INFO] ctrl_if_trx.py:117 (BTS@172.18.28.20:5700) Stopping transceiver...
2026-01-29 01:55:37.303 [INFO] transceiver.py:246 Stopping clock generator
2026-01-29 01:55:37.303 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=1826 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 01:55:37.303 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=1826 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 01:55:37.303 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=1826 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 01:55:37.303 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=1826 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 01:55:37.303 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=1827 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 01:55:37.304 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=1827 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 01:55:37.304 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=1827 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 01:55:37.304 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=1827 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 01:55:37.304 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=1827 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 01:55:37.304 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=1827 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 01:55:37.304 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=1827 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 01:55:37.304 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=1827 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 01:55:42.299 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.28.20:5700) Recv POWEROFF cmd
2026-01-29 01:55:42.299 [INFO] ctrl_if_trx.py:117 (BTS@172.18.28.20:5700) Stopping transceiver...
2026-01-29 01:55:42.300 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 01:55:42.302 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 01:55:42.302 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 01:55:42.303 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 01:55:42.312 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 01:55:42.313 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.28.20:5700) Recv SETFORMAT cmd
2026-01-29 01:55:42.314 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.28.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 01:55:42.314 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.28.20:5700) Recv SETFORMAT cmd
2026-01-29 01:55:42.314 [INFO] ctrl_if_trx.py:201 (BTS@172.18.28.20:5700) TRXD header version 1 -> 1
2026-01-29 01:55:42.320 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.28.20:5700/1) Recv RXTUNE cmd
2026-01-29 01:55:42.320 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.28.20:5700/1) Recv TXTUNE cmd
2026-01-29 01:55:42.321 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.28.20:5700/1) Recv SETFORMAT cmd
2026-01-29 01:55:42.321 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.28.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 01:55:42.321 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 01:55:42.321 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.28.20:5700/1) Recv NOMTXPOWER cmd
2026-01-29 01:55:42.322 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.28.20:5700/1) Recv SETFORMAT cmd
2026-01-29 01:55:42.322 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.28.20:5700/1) TRXD header version 1 -> 1
2026-01-29 01:55:42.327 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.28.20:5700/2) Recv RXTUNE cmd
2026-01-29 01:55:42.328 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.28.20:5700/2) Recv TXTUNE cmd
2026-01-29 01:55:42.328 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.28.20:5700/2) Recv SETFORMAT cmd
2026-01-29 01:55:42.328 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.28.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 01:55:42.328 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 01:55:42.329 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.28.20:5700/2) Recv NOMTXPOWER cmd
2026-01-29 01:55:42.329 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.28.20:5700/2) Recv SETFORMAT cmd
2026-01-29 01:55:42.329 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.28.20:5700/2) TRXD header version 1 -> 1
2026-01-29 01:55:42.332 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.28.20:5700/3) Recv RXTUNE cmd
2026-01-29 01:55:42.332 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.28.20:5700/3) Recv TXTUNE cmd
2026-01-29 01:55:42.332 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.28.20:5700/3) Recv SETFORMAT cmd
2026-01-29 01:55:42.332 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.28.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 01:55:42.332 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 01:55:42.333 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.28.20:5700/3) Recv NOMTXPOWER cmd
2026-01-29 01:55:42.333 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.28.20:5700/3) Recv SETFORMAT cmd
2026-01-29 01:55:42.333 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.28.20:5700/3) TRXD header version 1 -> 1
2026-01-29 01:55:42.337 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.28.20:5700) Recv RXTUNE cmd
2026-01-29 01:55:42.337 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETTSC
2026-01-29 01:55:42.337 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETTSC
2026-01-29 01:55:42.337 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETTSC
2026-01-29 01:55:42.337 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.28.20:5700) Recv TXTUNE cmd
2026-01-29 01:55:42.337 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETRXGAIN
2026-01-29 01:55:42.337 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETRXGAIN
2026-01-29 01:55:42.338 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETRXGAIN
2026-01-29 01:55:42.338 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETTSC
2026-01-29 01:55:42.338 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:55:42.338 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:55:42.338 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:55:42.338 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.28.20:5700) Recv NOMTXPOWER cmd
2026-01-29 01:55:42.338 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:55:42.338 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:55:42.338 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:55:42.338 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.28.20:5700) Recv POWERON CMD
2026-01-29 01:55:42.338 [INFO] ctrl_if_trx.py:109 (BTS@172.18.28.20:5700) Starting transceiver...
2026-01-29 01:55:42.338 [INFO] transceiver.py:243 Starting clock generator
2026-01-29 01:55:42.338 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-01-29 01:55:42.338 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:55:42.338 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:55:42.339 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:55:42.339 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETRXGAIN
2026-01-29 01:55:42.339 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:55:42.339 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:55:42.339 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:55:42.339 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 01:55:42.339 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:55:42.339 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:55:42.339 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:55:42.339 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 01:55:42.339 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:55:42.339 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:55:42.339 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:55:42.339 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 01:55:42.340 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:55:42.340 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:55:42.340 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:55:42.340 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 01:55:42.340 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:55:42.340 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:55:42.340 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 01:55:42.340 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:55:42.340 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 01:55:42.340 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 01:55:42.340 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 01:55:42.343 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-01-29 01:55:42.824 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-01-29 01:55:42.868 [DEBUG] fake_trx.py:278 (BTS@172.18.28.20:5700) Recv FAKE_TOA cmd
2026-01-29 01:55:42.871 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:55:42.871 [DEBUG] fake_trx.py:297 (BTS@172.18.28.20:5700) Recv FAKE_RSSI cmd
2026-01-29 01:55:42.872 [DEBUG] fake_trx.py:322 (BTS@172.18.28.20:5700) Recv FAKE_CI cmd
2026-01-29 01:55:42.875 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 01:55:42.875 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 01:55:42.875 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 01:55:42.876 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 01:55:42.876 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 01:55:42.876 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 01:55:42.876 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.28.22:6700) Recv POWERON CMD
2026-01-29 01:55:42.876 [INFO] ctrl_if_trx.py:109 (MS@172.18.28.22:6700) Starting transceiver...
2026-01-29 01:55:43.301 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-01-29 01:55:43.342 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 01:55:43.342 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 01:55:43.344 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 01:55:43.347 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 01:55:43.779 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-01-29 01:55:44.257 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-01-29 01:55:44.343 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 01:55:44.343 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 01:55:44.345 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 01:55:44.348 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 01:55:44.735 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-01-29 01:55:45.213 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-01-29 01:55:45.343 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 01:55:45.344 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 01:55:45.346 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 01:55:45.349 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 01:55:45.690 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-01-29 01:55:46.167 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-01-29 01:55:46.344 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 01:55:46.344 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 01:55:46.347 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 01:55:46.350 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 01:55:46.645 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-01-29 01:55:47.123 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-01-29 01:55:47.345 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 01:55:47.345 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 01:55:47.348 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 01:55:47.351 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 01:55:47.600 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-01-29 01:55:48.078 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-01-29 01:55:48.555 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-01-29 01:55:49.033 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-01-29 01:55:49.511 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-01-29 01:55:49.989 [DEBUG] clck_gen.py:113 IND CLOCK 1632
2026-01-29 01:55:50.467 [DEBUG] clck_gen.py:113 IND CLOCK 1734
2026-01-29 01:55:50.919 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 01:55:50.919 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 01:55:50.925 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 01:55:50.925 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 01:55:50.925 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 01:55:50.925 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 01:55:50.926 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 01:55:50.926 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 01:55:50.926 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 01:55:50.926 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 01:55:50.926 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.28.20:5700) Recv POWEROFF cmd
2026-01-29 01:55:50.926 [INFO] ctrl_if_trx.py:117 (BTS@172.18.28.20:5700) Stopping transceiver...
2026-01-29 01:55:50.926 [INFO] transceiver.py:246 Stopping clock generator
2026-01-29 01:55:55.927 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.28.20:5700) Recv POWEROFF cmd
2026-01-29 01:55:55.927 [INFO] ctrl_if_trx.py:117 (BTS@172.18.28.20:5700) Stopping transceiver...
2026-01-29 01:55:55.928 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 01:55:55.930 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 01:55:55.930 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 01:55:55.930 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 01:55:55.935 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 01:55:55.935 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.28.20:5700) Recv SETFORMAT cmd
2026-01-29 01:55:55.936 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.28.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 01:55:55.936 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.28.20:5700) Recv SETFORMAT cmd
2026-01-29 01:55:55.936 [INFO] ctrl_if_trx.py:201 (BTS@172.18.28.20:5700) TRXD header version 1 -> 1
2026-01-29 01:55:55.939 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.28.20:5700/1) Recv RXTUNE cmd
2026-01-29 01:55:55.939 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.28.20:5700/1) Recv TXTUNE cmd
2026-01-29 01:55:55.939 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.28.20:5700/1) Recv SETFORMAT cmd
2026-01-29 01:55:55.939 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.28.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 01:55:55.939 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 01:55:55.939 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.28.20:5700/1) Recv NOMTXPOWER cmd
2026-01-29 01:55:55.940 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.28.20:5700/1) Recv SETFORMAT cmd
2026-01-29 01:55:55.940 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.28.20:5700/1) TRXD header version 1 -> 1
2026-01-29 01:55:55.942 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.28.20:5700/2) Recv RXTUNE cmd
2026-01-29 01:55:55.942 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.28.20:5700/2) Recv TXTUNE cmd
2026-01-29 01:55:55.942 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.28.20:5700/2) Recv SETFORMAT cmd
2026-01-29 01:55:55.942 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.28.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 01:55:55.942 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 01:55:55.942 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.28.20:5700/2) Recv NOMTXPOWER cmd
2026-01-29 01:55:55.942 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.28.20:5700/2) Recv SETFORMAT cmd
2026-01-29 01:55:55.943 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.28.20:5700/2) TRXD header version 1 -> 1
2026-01-29 01:55:55.944 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.28.20:5700/3) Recv RXTUNE cmd
2026-01-29 01:55:55.944 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.28.20:5700/3) Recv TXTUNE cmd
2026-01-29 01:55:55.944 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.28.20:5700/3) Recv SETFORMAT cmd
2026-01-29 01:55:55.944 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.28.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 01:55:55.945 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 01:55:55.945 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.28.20:5700/3) Recv NOMTXPOWER cmd
2026-01-29 01:55:55.945 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.28.20:5700/3) Recv SETFORMAT cmd
2026-01-29 01:55:55.945 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.28.20:5700/3) TRXD header version 1 -> 1
2026-01-29 01:55:55.947 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.28.20:5700) Recv RXTUNE cmd
2026-01-29 01:55:55.947 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETTSC
2026-01-29 01:55:55.947 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETTSC
2026-01-29 01:55:55.947 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETTSC
2026-01-29 01:55:55.947 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.28.20:5700) Recv TXTUNE cmd
2026-01-29 01:55:55.947 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETRXGAIN
2026-01-29 01:55:55.947 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETRXGAIN
2026-01-29 01:55:55.947 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETRXGAIN
2026-01-29 01:55:55.947 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETTSC
2026-01-29 01:55:55.947 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:55:55.947 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:55:55.947 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:55:55.947 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.28.20:5700) Recv NOMTXPOWER cmd
2026-01-29 01:55:55.947 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:55:55.947 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:55:55.947 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:55:55.947 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.28.20:5700) Recv POWERON CMD
2026-01-29 01:55:55.947 [INFO] ctrl_if_trx.py:109 (BTS@172.18.28.20:5700) Starting transceiver...
2026-01-29 01:55:55.947 [INFO] transceiver.py:243 Starting clock generator
2026-01-29 01:55:55.947 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-01-29 01:55:55.948 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:55:55.948 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:55:55.948 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:55:55.948 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETRXGAIN
2026-01-29 01:55:55.948 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:55:55.948 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:55:55.948 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:55:55.948 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 01:55:55.948 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:55:55.948 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:55:55.948 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:55:55.948 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 01:55:55.948 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:55:55.948 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:55:55.948 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:55:55.948 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 01:55:55.948 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:55:55.948 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:55:55.948 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:55:55.948 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 01:55:55.948 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:55:55.948 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:55:55.948 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:55:55.948 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 01:55:55.948 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 01:55:55.948 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 01:55:55.948 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 01:55:55.952 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-01-29 01:55:56.434 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-01-29 01:55:56.474 [DEBUG] fake_trx.py:278 (BTS@172.18.28.20:5700) Recv FAKE_TOA cmd
2026-01-29 01:55:56.476 [DEBUG] fake_trx.py:297 (BTS@172.18.28.20:5700) Recv FAKE_RSSI cmd
2026-01-29 01:55:56.478 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:55:56.479 [DEBUG] fake_trx.py:322 (BTS@172.18.28.20:5700) Recv FAKE_CI cmd
2026-01-29 01:55:56.482 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 01:55:56.483 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 01:55:56.483 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 01:55:56.483 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 01:55:56.484 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 01:55:56.484 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 01:55:56.484 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.28.22:6700) Recv POWERON CMD
2026-01-29 01:55:56.484 [INFO] ctrl_if_trx.py:109 (MS@172.18.28.22:6700) Starting transceiver...
2026-01-29 01:55:56.911 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-01-29 01:55:56.949 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 01:55:56.950 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 01:55:56.950 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 01:55:56.952 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 01:55:57.389 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-01-29 01:55:57.867 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-01-29 01:55:57.950 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 01:55:57.951 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 01:55:57.951 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 01:55:57.953 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 01:55:58.345 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-01-29 01:55:58.823 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-01-29 01:55:58.951 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 01:55:58.952 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 01:55:58.952 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 01:55:58.953 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 01:55:59.300 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-01-29 01:55:59.773 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-01-29 01:55:59.952 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 01:55:59.952 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 01:55:59.953 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 01:55:59.954 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 01:56:00.251 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-01-29 01:56:00.729 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-01-29 01:56:00.953 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 01:56:00.953 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 01:56:00.953 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 01:56:00.955 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 01:56:01.207 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-01-29 01:56:01.684 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-01-29 01:56:02.162 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-01-29 01:56:02.639 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-01-29 01:56:03.117 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-01-29 01:56:03.594 [DEBUG] clck_gen.py:113 IND CLOCK 1632
2026-01-29 01:56:04.072 [DEBUG] clck_gen.py:113 IND CLOCK 1734
2026-01-29 01:56:04.550 [DEBUG] clck_gen.py:113 IND CLOCK 1836
2026-01-29 01:56:05.027 [DEBUG] clck_gen.py:113 IND CLOCK 1938
2026-01-29 01:56:05.505 [DEBUG] clck_gen.py:113 IND CLOCK 2040
2026-01-29 01:56:05.983 [DEBUG] clck_gen.py:113 IND CLOCK 2142
2026-01-29 01:56:06.461 [DEBUG] clck_gen.py:113 IND CLOCK 2244
2026-01-29 01:56:06.939 [DEBUG] clck_gen.py:113 IND CLOCK 2346
2026-01-29 01:56:07.417 [DEBUG] clck_gen.py:113 IND CLOCK 2448
2026-01-29 01:56:07.894 [DEBUG] clck_gen.py:113 IND CLOCK 2550
2026-01-29 01:56:08.371 [DEBUG] clck_gen.py:113 IND CLOCK 2652
2026-01-29 01:56:08.849 [DEBUG] clck_gen.py:113 IND CLOCK 2754
2026-01-29 01:56:09.326 [DEBUG] clck_gen.py:113 IND CLOCK 2856
2026-01-29 01:56:09.804 [DEBUG] clck_gen.py:113 IND CLOCK 2958
2026-01-29 01:56:10.282 [DEBUG] clck_gen.py:113 IND CLOCK 3060
2026-01-29 01:56:10.760 [DEBUG] clck_gen.py:113 IND CLOCK 3162
2026-01-29 01:56:11.238 [DEBUG] clck_gen.py:113 IND CLOCK 3264
2026-01-29 01:56:11.716 [DEBUG] clck_gen.py:113 IND CLOCK 3366
2026-01-29 01:56:12.194 [DEBUG] clck_gen.py:113 IND CLOCK 3468
2026-01-29 01:56:12.536 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 01:56:12.536 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 01:56:12.540 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 01:56:12.540 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 01:56:12.541 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 01:56:12.541 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 01:56:12.544 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 01:56:12.544 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 01:56:12.544 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 01:56:12.544 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 01:56:12.544 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.28.20:5700) Recv POWEROFF cmd
2026-01-29 01:56:12.544 [INFO] ctrl_if_trx.py:117 (BTS@172.18.28.20:5700) Stopping transceiver...
2026-01-29 01:56:12.544 [INFO] transceiver.py:246 Stopping clock generator
2026-01-29 01:56:12.544 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=3545 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 01:56:12.544 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=3545 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 01:56:12.544 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=3545 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 01:56:12.544 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=3545 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 01:56:12.544 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=3545 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 01:56:12.544 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=3545 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 01:56:12.544 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=3545 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 01:56:17.544 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.28.20:5700) Recv POWEROFF cmd
2026-01-29 01:56:17.544 [INFO] ctrl_if_trx.py:117 (BTS@172.18.28.20:5700) Stopping transceiver...
2026-01-29 01:56:17.546 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 01:56:17.547 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 01:56:17.548 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 01:56:17.548 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 01:56:17.552 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 01:56:17.553 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.28.20:5700) Recv SETFORMAT cmd
2026-01-29 01:56:17.553 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.28.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 01:56:17.553 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.28.20:5700) Recv SETFORMAT cmd
2026-01-29 01:56:17.553 [INFO] ctrl_if_trx.py:201 (BTS@172.18.28.20:5700) TRXD header version 1 -> 1
2026-01-29 01:56:17.555 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.28.20:5700/1) Recv RXTUNE cmd
2026-01-29 01:56:17.555 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.28.20:5700/1) Recv TXTUNE cmd
2026-01-29 01:56:17.556 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.28.20:5700/1) Recv SETFORMAT cmd
2026-01-29 01:56:17.556 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.28.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 01:56:17.556 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 01:56:17.556 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.28.20:5700/1) Recv NOMTXPOWER cmd
2026-01-29 01:56:17.557 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.28.20:5700/1) Recv SETFORMAT cmd
2026-01-29 01:56:17.557 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.28.20:5700/1) TRXD header version 1 -> 1
2026-01-29 01:56:17.558 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.28.20:5700/2) Recv RXTUNE cmd
2026-01-29 01:56:17.558 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.28.20:5700/2) Recv TXTUNE cmd
2026-01-29 01:56:17.558 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.28.20:5700/2) Recv SETFORMAT cmd
2026-01-29 01:56:17.558 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.28.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 01:56:17.558 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 01:56:17.558 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.28.20:5700/2) Recv NOMTXPOWER cmd
2026-01-29 01:56:17.558 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.28.20:5700/2) Recv SETFORMAT cmd
2026-01-29 01:56:17.558 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.28.20:5700/2) TRXD header version 1 -> 1
2026-01-29 01:56:17.560 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.28.20:5700/3) Recv RXTUNE cmd
2026-01-29 01:56:17.560 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.28.20:5700/3) Recv TXTUNE cmd
2026-01-29 01:56:17.560 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.28.20:5700/3) Recv SETFORMAT cmd
2026-01-29 01:56:17.560 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.28.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 01:56:17.560 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 01:56:17.560 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.28.20:5700/3) Recv NOMTXPOWER cmd
2026-01-29 01:56:17.560 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.28.20:5700/3) Recv SETFORMAT cmd
2026-01-29 01:56:17.560 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.28.20:5700/3) TRXD header version 1 -> 1
2026-01-29 01:56:17.562 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.28.20:5700) Recv RXTUNE cmd
2026-01-29 01:56:17.562 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETTSC
2026-01-29 01:56:17.562 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETTSC
2026-01-29 01:56:17.562 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETTSC
2026-01-29 01:56:17.562 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.28.20:5700) Recv TXTUNE cmd
2026-01-29 01:56:17.562 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETRXGAIN
2026-01-29 01:56:17.562 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETRXGAIN
2026-01-29 01:56:17.562 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETRXGAIN
2026-01-29 01:56:17.562 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETTSC
2026-01-29 01:56:17.562 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:56:17.562 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:56:17.562 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:56:17.562 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.28.20:5700) Recv NOMTXPOWER cmd
2026-01-29 01:56:17.562 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:56:17.562 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:56:17.562 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:56:17.562 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.28.20:5700) Recv POWERON CMD
2026-01-29 01:56:17.562 [INFO] ctrl_if_trx.py:109 (BTS@172.18.28.20:5700) Starting transceiver...
2026-01-29 01:56:17.562 [INFO] transceiver.py:243 Starting clock generator
2026-01-29 01:56:17.563 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-01-29 01:56:17.563 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:56:17.563 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:56:17.563 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:56:17.563 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETRXGAIN
2026-01-29 01:56:17.563 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:56:17.563 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:56:17.563 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 01:56:17.563 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:56:17.563 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:56:17.563 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:56:17.563 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 01:56:17.563 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:56:17.563 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:56:17.563 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:56:17.563 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 01:56:17.563 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:56:17.563 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:56:17.563 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:56:17.563 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 01:56:17.563 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:56:17.563 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:56:17.563 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:56:17.563 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 01:56:17.563 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:56:17.563 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 01:56:17.563 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 01:56:17.563 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 01:56:17.567 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-01-29 01:56:18.052 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-01-29 01:56:18.091 [DEBUG] fake_trx.py:278 (BTS@172.18.28.20:5700) Recv FAKE_TOA cmd
2026-01-29 01:56:18.094 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:56:18.095 [DEBUG] fake_trx.py:297 (BTS@172.18.28.20:5700) Recv FAKE_RSSI cmd
2026-01-29 01:56:18.098 [DEBUG] fake_trx.py:322 (BTS@172.18.28.20:5700) Recv FAKE_CI cmd
2026-01-29 01:56:18.112 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 01:56:18.112 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 01:56:18.113 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 01:56:18.113 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 01:56:18.114 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 01:56:18.114 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 01:56:18.115 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.28.22:6700) Recv POWERON CMD
2026-01-29 01:56:18.115 [INFO] ctrl_if_trx.py:109 (MS@172.18.28.22:6700) Starting transceiver...
2026-01-29 01:56:18.529 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-01-29 01:56:18.565 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 01:56:18.565 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 01:56:18.566 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 01:56:18.567 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 01:56:19.007 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-01-29 01:56:19.485 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-01-29 01:56:19.566 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 01:56:19.566 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 01:56:19.566 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 01:56:19.568 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 01:56:19.962 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-01-29 01:56:20.437 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-01-29 01:56:20.567 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 01:56:20.567 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 01:56:20.568 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 01:56:20.569 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 01:56:20.914 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-01-29 01:56:21.391 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-01-29 01:56:21.568 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 01:56:21.568 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 01:56:21.568 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 01:56:21.570 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 01:56:21.868 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-01-29 01:56:22.343 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-01-29 01:56:22.569 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 01:56:22.569 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 01:56:22.570 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 01:56:22.571 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 01:56:22.821 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-01-29 01:56:23.298 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-01-29 01:56:23.775 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-01-29 01:56:24.252 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-01-29 01:56:24.730 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-01-29 01:56:25.207 [DEBUG] clck_gen.py:113 IND CLOCK 1632
2026-01-29 01:56:25.684 [DEBUG] clck_gen.py:113 IND CLOCK 1734
2026-01-29 01:56:26.148 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 01:56:26.148 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 01:56:26.161 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 01:56:26.161 [DEBUG] clck_gen.py:113 IND CLOCK 1836
2026-01-29 01:56:26.161 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 01:56:26.162 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 01:56:26.162 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 01:56:26.164 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 01:56:26.164 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 01:56:26.164 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 01:56:26.164 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.28.20:5700) Recv POWEROFF cmd
2026-01-29 01:56:26.164 [INFO] ctrl_if_trx.py:117 (BTS@172.18.28.20:5700) Stopping transceiver...
2026-01-29 01:56:26.164 [INFO] transceiver.py:246 Stopping clock generator
2026-01-29 01:56:26.164 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 01:56:26.164 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=1839 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 01:56:26.164 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=1839 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 01:56:26.164 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=1839 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 01:56:26.164 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=1839 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 01:56:26.164 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=1839 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 01:56:26.164 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=1839 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 01:56:26.164 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=1839 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 01:56:26.164 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=1839 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 01:56:26.164 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=1840 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 01:56:31.165 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.28.20:5700) Recv POWEROFF cmd
2026-01-29 01:56:31.165 [INFO] ctrl_if_trx.py:117 (BTS@172.18.28.20:5700) Stopping transceiver...
2026-01-29 01:56:31.170 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 01:56:31.171 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 01:56:31.171 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 01:56:31.171 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 01:56:31.179 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 01:56:31.180 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.28.20:5700) Recv SETFORMAT cmd
2026-01-29 01:56:31.180 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.28.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 01:56:31.180 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.28.20:5700) Recv SETFORMAT cmd
2026-01-29 01:56:31.180 [INFO] ctrl_if_trx.py:201 (BTS@172.18.28.20:5700) TRXD header version 1 -> 1
2026-01-29 01:56:31.181 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.28.20:5700/1) Recv RXTUNE cmd
2026-01-29 01:56:31.181 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.28.20:5700/1) Recv TXTUNE cmd
2026-01-29 01:56:31.182 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.28.20:5700/1) Recv SETFORMAT cmd
2026-01-29 01:56:31.182 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.28.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 01:56:31.182 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 01:56:31.182 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.28.20:5700/1) Recv NOMTXPOWER cmd
2026-01-29 01:56:31.182 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.28.20:5700/1) Recv SETFORMAT cmd
2026-01-29 01:56:31.182 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.28.20:5700/1) TRXD header version 1 -> 1
2026-01-29 01:56:31.183 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.28.20:5700/2) Recv RXTUNE cmd
2026-01-29 01:56:31.183 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.28.20:5700/2) Recv TXTUNE cmd
2026-01-29 01:56:31.183 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.28.20:5700/2) Recv SETFORMAT cmd
2026-01-29 01:56:31.183 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.28.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 01:56:31.183 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 01:56:31.183 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.28.20:5700/2) Recv NOMTXPOWER cmd
2026-01-29 01:56:31.183 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.28.20:5700/2) Recv SETFORMAT cmd
2026-01-29 01:56:31.183 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.28.20:5700/2) TRXD header version 1 -> 1
2026-01-29 01:56:31.184 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.28.20:5700/3) Recv RXTUNE cmd
2026-01-29 01:56:31.184 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.28.20:5700/3) Recv TXTUNE cmd
2026-01-29 01:56:31.184 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.28.20:5700/3) Recv SETFORMAT cmd
2026-01-29 01:56:31.184 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.28.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 01:56:31.184 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 01:56:31.184 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.28.20:5700/3) Recv NOMTXPOWER cmd
2026-01-29 01:56:31.184 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.28.20:5700/3) Recv SETFORMAT cmd
2026-01-29 01:56:31.184 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.28.20:5700/3) TRXD header version 1 -> 1
2026-01-29 01:56:31.185 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.28.20:5700) Recv RXTUNE cmd
2026-01-29 01:56:31.185 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETTSC
2026-01-29 01:56:31.185 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETTSC
2026-01-29 01:56:31.185 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETTSC
2026-01-29 01:56:31.185 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.28.20:5700) Recv TXTUNE cmd
2026-01-29 01:56:31.186 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETRXGAIN
2026-01-29 01:56:31.186 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETRXGAIN
2026-01-29 01:56:31.186 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETRXGAIN
2026-01-29 01:56:31.186 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETTSC
2026-01-29 01:56:31.186 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:56:31.186 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:56:31.186 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:56:31.186 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.28.20:5700) Recv NOMTXPOWER cmd
2026-01-29 01:56:31.186 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:56:31.186 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:56:31.186 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:56:31.186 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.28.20:5700) Recv POWERON CMD
2026-01-29 01:56:31.186 [INFO] ctrl_if_trx.py:109 (BTS@172.18.28.20:5700) Starting transceiver...
2026-01-29 01:56:31.186 [INFO] transceiver.py:243 Starting clock generator
2026-01-29 01:56:31.186 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-01-29 01:56:31.186 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:56:31.186 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:56:31.186 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:56:31.186 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETRXGAIN
2026-01-29 01:56:31.186 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:56:31.186 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:56:31.186 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:56:31.186 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 01:56:31.186 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:56:31.186 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:56:31.186 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:56:31.186 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 01:56:31.186 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:56:31.186 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:56:31.186 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:56:31.186 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 01:56:31.186 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:56:31.186 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:56:31.186 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:56:31.186 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 01:56:31.187 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:56:31.187 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:56:31.187 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:56:31.187 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 01:56:31.187 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 01:56:31.187 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 01:56:31.187 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 01:56:31.191 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-01-29 01:56:31.673 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-01-29 01:56:31.706 [DEBUG] fake_trx.py:278 (BTS@172.18.28.20:5700) Recv FAKE_TOA cmd
2026-01-29 01:56:31.707 [DEBUG] fake_trx.py:297 (BTS@172.18.28.20:5700) Recv FAKE_RSSI cmd
2026-01-29 01:56:31.708 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:56:31.709 [DEBUG] fake_trx.py:322 (BTS@172.18.28.20:5700) Recv FAKE_CI cmd
2026-01-29 01:56:31.715 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 01:56:31.715 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 01:56:31.715 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 01:56:31.716 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 01:56:31.716 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 01:56:31.716 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 01:56:31.716 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.28.22:6700) Recv POWERON CMD
2026-01-29 01:56:31.716 [INFO] ctrl_if_trx.py:109 (MS@172.18.28.22:6700) Starting transceiver...
2026-01-29 01:56:32.150 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-01-29 01:56:32.188 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 01:56:32.188 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 01:56:32.189 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 01:56:32.190 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 01:56:32.627 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-01-29 01:56:33.105 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-01-29 01:56:33.189 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 01:56:33.189 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 01:56:33.189 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 01:56:33.191 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 01:56:33.583 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-01-29 01:56:34.061 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-01-29 01:56:34.190 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 01:56:34.191 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 01:56:34.191 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 01:56:34.192 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 01:56:34.538 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-01-29 01:56:35.016 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-01-29 01:56:35.192 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 01:56:35.192 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 01:56:35.192 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 01:56:35.193 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 01:56:35.494 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-01-29 01:56:35.972 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-01-29 01:56:36.193 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 01:56:36.193 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 01:56:36.194 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 01:56:36.194 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 01:56:36.449 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-01-29 01:56:36.927 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-01-29 01:56:37.405 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-01-29 01:56:37.882 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-01-29 01:56:38.359 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-01-29 01:56:38.836 [DEBUG] clck_gen.py:113 IND CLOCK 1632
2026-01-29 01:56:39.314 [DEBUG] clck_gen.py:113 IND CLOCK 1734
2026-01-29 01:56:39.792 [DEBUG] clck_gen.py:113 IND CLOCK 1836
2026-01-29 01:56:40.269 [DEBUG] clck_gen.py:113 IND CLOCK 1938
2026-01-29 01:56:40.746 [DEBUG] clck_gen.py:113 IND CLOCK 2040
2026-01-29 01:56:41.224 [DEBUG] clck_gen.py:113 IND CLOCK 2142
2026-01-29 01:56:41.702 [DEBUG] clck_gen.py:113 IND CLOCK 2244
2026-01-29 01:56:42.180 [DEBUG] clck_gen.py:113 IND CLOCK 2346
2026-01-29 01:56:42.657 [DEBUG] clck_gen.py:113 IND CLOCK 2448
2026-01-29 01:56:43.133 [DEBUG] clck_gen.py:113 IND CLOCK 2550
2026-01-29 01:56:43.610 [DEBUG] clck_gen.py:113 IND CLOCK 2652
2026-01-29 01:56:44.088 [DEBUG] clck_gen.py:113 IND CLOCK 2754
2026-01-29 01:56:44.566 [DEBUG] clck_gen.py:113 IND CLOCK 2856
2026-01-29 01:56:45.044 [DEBUG] clck_gen.py:113 IND CLOCK 2958
2026-01-29 01:56:45.521 [DEBUG] clck_gen.py:113 IND CLOCK 3060
2026-01-29 01:56:45.999 [DEBUG] clck_gen.py:113 IND CLOCK 3162
2026-01-29 01:56:46.477 [DEBUG] clck_gen.py:113 IND CLOCK 3264
2026-01-29 01:56:46.954 [DEBUG] clck_gen.py:113 IND CLOCK 3366
2026-01-29 01:56:47.432 [DEBUG] clck_gen.py:113 IND CLOCK 3468
2026-01-29 01:56:47.781 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 01:56:47.781 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 01:56:47.799 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 01:56:47.799 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 01:56:47.799 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 01:56:47.799 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 01:56:47.803 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 01:56:47.803 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 01:56:47.803 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 01:56:47.803 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.28.20:5700) Recv POWEROFF cmd
2026-01-29 01:56:47.804 [INFO] ctrl_if_trx.py:117 (BTS@172.18.28.20:5700) Stopping transceiver...
2026-01-29 01:56:47.804 [INFO] transceiver.py:246 Stopping clock generator
2026-01-29 01:56:47.804 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 01:56:47.804 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=3549 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 01:56:47.804 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=3549 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 01:56:47.804 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=3549 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 01:56:47.804 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=3549 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 01:56:47.804 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=3549 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 01:56:47.804 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=3549 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 01:56:52.805 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.28.20:5700) Recv POWEROFF cmd
2026-01-29 01:56:52.806 [INFO] ctrl_if_trx.py:117 (BTS@172.18.28.20:5700) Stopping transceiver...
2026-01-29 01:56:52.806 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 01:56:52.806 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 01:56:52.806 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 01:56:52.806 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 01:56:52.819 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 01:56:52.821 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.28.20:5700) Recv SETFORMAT cmd
2026-01-29 01:56:52.821 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.28.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 01:56:52.822 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.28.20:5700) Recv SETFORMAT cmd
2026-01-29 01:56:52.822 [INFO] ctrl_if_trx.py:201 (BTS@172.18.28.20:5700) TRXD header version 1 -> 1
2026-01-29 01:56:52.825 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.28.20:5700/1) Recv RXTUNE cmd
2026-01-29 01:56:52.825 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.28.20:5700/1) Recv TXTUNE cmd
2026-01-29 01:56:52.825 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.28.20:5700/1) Recv SETFORMAT cmd
2026-01-29 01:56:52.825 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.28.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 01:56:52.825 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 01:56:52.825 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.28.20:5700/1) Recv NOMTXPOWER cmd
2026-01-29 01:56:52.826 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.28.20:5700/1) Recv SETFORMAT cmd
2026-01-29 01:56:52.826 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.28.20:5700/1) TRXD header version 1 -> 1
2026-01-29 01:56:52.828 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.28.20:5700/2) Recv RXTUNE cmd
2026-01-29 01:56:52.828 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.28.20:5700/2) Recv TXTUNE cmd
2026-01-29 01:56:52.828 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.28.20:5700/2) Recv SETFORMAT cmd
2026-01-29 01:56:52.829 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.28.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 01:56:52.829 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 01:56:52.829 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.28.20:5700/2) Recv NOMTXPOWER cmd
2026-01-29 01:56:52.829 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.28.20:5700/2) Recv SETFORMAT cmd
2026-01-29 01:56:52.829 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.28.20:5700/2) TRXD header version 1 -> 1
2026-01-29 01:56:52.831 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.28.20:5700/3) Recv RXTUNE cmd
2026-01-29 01:56:52.831 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.28.20:5700/3) Recv TXTUNE cmd
2026-01-29 01:56:52.831 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.28.20:5700/3) Recv SETFORMAT cmd
2026-01-29 01:56:52.831 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.28.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 01:56:52.831 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 01:56:52.831 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.28.20:5700/3) Recv NOMTXPOWER cmd
2026-01-29 01:56:52.832 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.28.20:5700/3) Recv SETFORMAT cmd
2026-01-29 01:56:52.832 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.28.20:5700/3) TRXD header version 1 -> 1
2026-01-29 01:56:52.834 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.28.20:5700) Recv RXTUNE cmd
2026-01-29 01:56:52.834 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETTSC
2026-01-29 01:56:52.834 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETTSC
2026-01-29 01:56:52.834 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETTSC
2026-01-29 01:56:52.834 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.28.20:5700) Recv TXTUNE cmd
2026-01-29 01:56:52.834 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETRXGAIN
2026-01-29 01:56:52.834 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETRXGAIN
2026-01-29 01:56:52.835 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETRXGAIN
2026-01-29 01:56:52.835 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETTSC
2026-01-29 01:56:52.835 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:56:52.835 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:56:52.835 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:56:52.835 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.28.20:5700) Recv NOMTXPOWER cmd
2026-01-29 01:56:52.835 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:56:52.835 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:56:52.835 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:56:52.835 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.28.20:5700) Recv POWERON CMD
2026-01-29 01:56:52.835 [INFO] ctrl_if_trx.py:109 (BTS@172.18.28.20:5700) Starting transceiver...
2026-01-29 01:56:52.835 [INFO] transceiver.py:243 Starting clock generator
2026-01-29 01:56:52.835 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-01-29 01:56:52.835 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:56:52.835 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:56:52.835 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:56:52.835 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETRXGAIN
2026-01-29 01:56:52.836 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:56:52.836 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:56:52.836 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:56:52.836 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 01:56:52.836 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:56:52.836 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:56:52.836 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:56:52.836 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 01:56:52.836 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:56:52.836 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:56:52.836 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:56:52.836 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 01:56:52.836 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:56:52.836 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:56:52.837 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 01:56:52.837 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:56:52.837 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:56:52.837 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:56:52.837 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 01:56:52.837 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:56:52.837 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 01:56:52.837 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 01:56:52.837 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 01:56:52.840 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-01-29 01:56:53.323 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-01-29 01:56:53.353 [DEBUG] fake_trx.py:278 (BTS@172.18.28.20:5700) Recv FAKE_TOA cmd
2026-01-29 01:56:53.354 [DEBUG] fake_trx.py:297 (BTS@172.18.28.20:5700) Recv FAKE_RSSI cmd
2026-01-29 01:56:53.354 [DEBUG] fake_trx.py:322 (BTS@172.18.28.20:5700) Recv FAKE_CI cmd
2026-01-29 01:56:53.355 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:56:53.361 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 01:56:53.361 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 01:56:53.361 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 01:56:53.365 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 01:56:53.365 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 01:56:53.365 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 01:56:53.365 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 01:56:53.367 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 01:56:53.367 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 01:56:53.367 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 01:56:53.367 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 01:56:53.367 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.28.20:5700) Recv POWEROFF cmd
2026-01-29 01:56:53.367 [INFO] ctrl_if_trx.py:117 (BTS@172.18.28.20:5700) Stopping transceiver...
2026-01-29 01:56:53.367 [INFO] transceiver.py:246 Stopping clock generator
2026-01-29 01:56:53.367 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=113 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 01:56:53.367 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=113 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 01:56:53.367 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=113 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 01:56:53.367 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=113 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 01:56:53.368 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=113 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 01:56:53.368 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=113 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 01:56:58.369 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.28.20:5700) Recv POWEROFF cmd
2026-01-29 01:56:58.370 [INFO] ctrl_if_trx.py:117 (BTS@172.18.28.20:5700) Stopping transceiver...
2026-01-29 01:56:58.372 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 01:56:58.372 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 01:56:58.372 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 01:56:58.372 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 01:56:58.381 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 01:56:58.382 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.28.20:5700) Recv SETFORMAT cmd
2026-01-29 01:56:58.382 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.28.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 01:56:58.383 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.28.20:5700) Recv SETFORMAT cmd
2026-01-29 01:56:58.383 [INFO] ctrl_if_trx.py:201 (BTS@172.18.28.20:5700) TRXD header version 1 -> 1
2026-01-29 01:56:58.386 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.28.20:5700/1) Recv RXTUNE cmd
2026-01-29 01:56:58.386 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.28.20:5700/1) Recv TXTUNE cmd
2026-01-29 01:56:58.387 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.28.20:5700/1) Recv SETFORMAT cmd
2026-01-29 01:56:58.387 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.28.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 01:56:58.387 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 01:56:58.387 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.28.20:5700/1) Recv NOMTXPOWER cmd
2026-01-29 01:56:58.388 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.28.20:5700/1) Recv SETFORMAT cmd
2026-01-29 01:56:58.388 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.28.20:5700/1) TRXD header version 1 -> 1
2026-01-29 01:56:58.389 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.28.20:5700/2) Recv RXTUNE cmd
2026-01-29 01:56:58.389 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.28.20:5700/2) Recv TXTUNE cmd
2026-01-29 01:56:58.389 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.28.20:5700/2) Recv SETFORMAT cmd
2026-01-29 01:56:58.389 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.28.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 01:56:58.389 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 01:56:58.389 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.28.20:5700/2) Recv NOMTXPOWER cmd
2026-01-29 01:56:58.390 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.28.20:5700/2) Recv SETFORMAT cmd
2026-01-29 01:56:58.390 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.28.20:5700/2) TRXD header version 1 -> 1
2026-01-29 01:56:58.392 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.28.20:5700/3) Recv RXTUNE cmd
2026-01-29 01:56:58.392 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.28.20:5700/3) Recv TXTUNE cmd
2026-01-29 01:56:58.392 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.28.20:5700/3) Recv SETFORMAT cmd
2026-01-29 01:56:58.392 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.28.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 01:56:58.392 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 01:56:58.392 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.28.20:5700/3) Recv NOMTXPOWER cmd
2026-01-29 01:56:58.393 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.28.20:5700/3) Recv SETFORMAT cmd
2026-01-29 01:56:58.393 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.28.20:5700/3) TRXD header version 1 -> 1
2026-01-29 01:56:58.395 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.28.20:5700) Recv RXTUNE cmd
2026-01-29 01:56:58.395 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETTSC
2026-01-29 01:56:58.395 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETTSC
2026-01-29 01:56:58.395 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETTSC
2026-01-29 01:56:58.395 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.28.20:5700) Recv TXTUNE cmd
2026-01-29 01:56:58.395 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETRXGAIN
2026-01-29 01:56:58.395 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETRXGAIN
2026-01-29 01:56:58.395 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETRXGAIN
2026-01-29 01:56:58.396 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETTSC
2026-01-29 01:56:58.396 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:56:58.396 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:56:58.396 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:56:58.396 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.28.20:5700) Recv NOMTXPOWER cmd
2026-01-29 01:56:58.396 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:56:58.396 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:56:58.396 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:56:58.396 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.28.20:5700) Recv POWERON CMD
2026-01-29 01:56:58.396 [INFO] ctrl_if_trx.py:109 (BTS@172.18.28.20:5700) Starting transceiver...
2026-01-29 01:56:58.396 [INFO] transceiver.py:243 Starting clock generator
2026-01-29 01:56:58.396 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-01-29 01:56:58.396 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:56:58.396 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:56:58.396 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:56:58.396 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETRXGAIN
2026-01-29 01:56:58.397 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:56:58.397 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:56:58.397 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:56:58.397 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 01:56:58.397 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:56:58.397 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:56:58.397 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:56:58.397 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 01:56:58.397 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:56:58.397 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:56:58.397 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:56:58.397 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 01:56:58.397 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:56:58.397 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:56:58.397 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 01:56:58.397 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:56:58.397 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:56:58.397 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 01:56:58.397 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:56:58.397 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 01:56:58.397 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:56:58.397 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 01:56:58.397 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 01:56:58.401 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-01-29 01:56:58.883 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-01-29 01:56:58.923 [DEBUG] fake_trx.py:278 (BTS@172.18.28.20:5700) Recv FAKE_TOA cmd
2026-01-29 01:56:58.925 [DEBUG] fake_trx.py:297 (BTS@172.18.28.20:5700) Recv FAKE_RSSI cmd
2026-01-29 01:56:58.926 [DEBUG] fake_trx.py:322 (BTS@172.18.28.20:5700) Recv FAKE_CI cmd
2026-01-29 01:56:58.926 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:56:58.946 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 01:56:58.946 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 01:56:58.946 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 01:56:58.981 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 01:56:58.981 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 01:56:58.981 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 01:56:58.982 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 01:56:58.983 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 01:56:58.983 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 01:56:58.983 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 01:56:58.983 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.28.20:5700) Recv POWEROFF cmd
2026-01-29 01:56:58.983 [INFO] ctrl_if_trx.py:117 (BTS@172.18.28.20:5700) Stopping transceiver...
2026-01-29 01:56:58.983 [INFO] transceiver.py:246 Stopping clock generator
2026-01-29 01:56:58.983 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 01:56:58.983 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=124 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 01:56:58.983 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=124 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 01:56:58.983 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=124 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 01:56:58.983 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=124 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 01:56:58.983 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=125 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 01:56:58.983 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=125 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 01:56:58.983 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=125 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 01:56:58.983 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=125 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 01:56:58.983 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=125 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 01:56:58.983 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=125 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 01:56:58.983 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=125 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 01:56:58.983 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=125 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 01:57:03.985 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.28.20:5700) Recv POWEROFF cmd
2026-01-29 01:57:03.985 [INFO] ctrl_if_trx.py:117 (BTS@172.18.28.20:5700) Stopping transceiver...
2026-01-29 01:57:03.987 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 01:57:03.988 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 01:57:03.990 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 01:57:03.992 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 01:57:03.999 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 01:57:03.999 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.28.20:5700) Recv SETFORMAT cmd
2026-01-29 01:57:03.999 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.28.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 01:57:04.000 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.28.20:5700) Recv SETFORMAT cmd
2026-01-29 01:57:04.000 [INFO] ctrl_if_trx.py:201 (BTS@172.18.28.20:5700) TRXD header version 1 -> 1
2026-01-29 01:57:04.001 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.28.20:5700/1) Recv RXTUNE cmd
2026-01-29 01:57:04.002 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.28.20:5700/1) Recv TXTUNE cmd
2026-01-29 01:57:04.002 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.28.20:5700/1) Recv SETFORMAT cmd
2026-01-29 01:57:04.002 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.28.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 01:57:04.002 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 01:57:04.002 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.28.20:5700/1) Recv NOMTXPOWER cmd
2026-01-29 01:57:04.002 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.28.20:5700/1) Recv SETFORMAT cmd
2026-01-29 01:57:04.002 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.28.20:5700/1) TRXD header version 1 -> 1
2026-01-29 01:57:04.004 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.28.20:5700/2) Recv RXTUNE cmd
2026-01-29 01:57:04.004 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.28.20:5700/2) Recv TXTUNE cmd
2026-01-29 01:57:04.004 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.28.20:5700/2) Recv SETFORMAT cmd
2026-01-29 01:57:04.004 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.28.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 01:57:04.004 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 01:57:04.004 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.28.20:5700/2) Recv NOMTXPOWER cmd
2026-01-29 01:57:04.004 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.28.20:5700/2) Recv SETFORMAT cmd
2026-01-29 01:57:04.004 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.28.20:5700/2) TRXD header version 1 -> 1
2026-01-29 01:57:04.005 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.28.20:5700/3) Recv RXTUNE cmd
2026-01-29 01:57:04.005 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.28.20:5700/3) Recv TXTUNE cmd
2026-01-29 01:57:04.005 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.28.20:5700/3) Recv SETFORMAT cmd
2026-01-29 01:57:04.005 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.28.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 01:57:04.005 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 01:57:04.006 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.28.20:5700/3) Recv NOMTXPOWER cmd
2026-01-29 01:57:04.006 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.28.20:5700/3) Recv SETFORMAT cmd
2026-01-29 01:57:04.006 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.28.20:5700/3) TRXD header version 1 -> 1
2026-01-29 01:57:04.007 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.28.20:5700) Recv RXTUNE cmd
2026-01-29 01:57:04.007 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETTSC
2026-01-29 01:57:04.007 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETTSC
2026-01-29 01:57:04.007 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETTSC
2026-01-29 01:57:04.007 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.28.20:5700) Recv TXTUNE cmd
2026-01-29 01:57:04.007 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETRXGAIN
2026-01-29 01:57:04.007 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETRXGAIN
2026-01-29 01:57:04.008 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETRXGAIN
2026-01-29 01:57:04.008 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETTSC
2026-01-29 01:57:04.008 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:57:04.008 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:57:04.008 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:57:04.008 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.28.20:5700) Recv NOMTXPOWER cmd
2026-01-29 01:57:04.008 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:57:04.008 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:57:04.008 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:57:04.008 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.28.20:5700) Recv POWERON CMD
2026-01-29 01:57:04.008 [INFO] ctrl_if_trx.py:109 (BTS@172.18.28.20:5700) Starting transceiver...
2026-01-29 01:57:04.008 [INFO] transceiver.py:243 Starting clock generator
2026-01-29 01:57:04.008 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-01-29 01:57:04.008 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:57:04.008 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:57:04.008 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:57:04.008 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETRXGAIN
2026-01-29 01:57:04.008 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:57:04.008 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:57:04.008 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:57:04.008 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 01:57:04.008 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:57:04.008 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:57:04.008 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:57:04.008 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 01:57:04.008 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:57:04.008 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:57:04.008 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:57:04.008 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 01:57:04.008 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:57:04.008 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:57:04.008 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:57:04.009 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 01:57:04.009 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:57:04.009 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:57:04.009 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:57:04.009 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 01:57:04.009 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 01:57:04.009 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 01:57:04.009 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 01:57:04.012 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-01-29 01:57:04.495 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-01-29 01:57:04.534 [DEBUG] fake_trx.py:278 (BTS@172.18.28.20:5700) Recv FAKE_TOA cmd
2026-01-29 01:57:04.537 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:57:04.538 [DEBUG] fake_trx.py:297 (BTS@172.18.28.20:5700) Recv FAKE_RSSI cmd
2026-01-29 01:57:04.541 [DEBUG] fake_trx.py:322 (BTS@172.18.28.20:5700) Recv FAKE_CI cmd
2026-01-29 01:57:04.568 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 01:57:04.568 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 01:57:04.568 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 01:57:04.589 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 01:57:04.590 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 01:57:04.590 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 01:57:04.590 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 01:57:04.593 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 01:57:04.594 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 01:57:04.594 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 01:57:04.594 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 01:57:04.594 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.28.20:5700) Recv POWEROFF cmd
2026-01-29 01:57:04.594 [INFO] ctrl_if_trx.py:117 (BTS@172.18.28.20:5700) Stopping transceiver...
2026-01-29 01:57:04.594 [INFO] transceiver.py:246 Stopping clock generator
2026-01-29 01:57:04.595 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=124 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 01:57:04.595 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=124 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 01:57:04.595 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=124 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 01:57:04.595 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=124 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 01:57:04.595 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=124 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 01:57:04.595 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=124 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 01:57:04.595 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=125 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 01:57:04.595 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=125 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 01:57:04.595 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=125 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 01:57:04.595 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=125 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 01:57:04.595 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=125 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 01:57:04.596 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=125 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 01:57:04.596 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=125 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 01:57:04.596 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=125 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 01:57:09.593 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.28.20:5700) Recv POWEROFF cmd
2026-01-29 01:57:09.593 [INFO] ctrl_if_trx.py:117 (BTS@172.18.28.20:5700) Stopping transceiver...
2026-01-29 01:57:09.595 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 01:57:09.596 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 01:57:09.596 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 01:57:09.597 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 01:57:09.606 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 01:57:09.608 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.28.20:5700) Recv SETFORMAT cmd
2026-01-29 01:57:09.608 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.28.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 01:57:09.609 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.28.20:5700) Recv SETFORMAT cmd
2026-01-29 01:57:09.609 [INFO] ctrl_if_trx.py:201 (BTS@172.18.28.20:5700) TRXD header version 1 -> 1
2026-01-29 01:57:09.613 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.28.20:5700/1) Recv RXTUNE cmd
2026-01-29 01:57:09.614 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.28.20:5700/1) Recv TXTUNE cmd
2026-01-29 01:57:09.615 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.28.20:5700/1) Recv SETFORMAT cmd
2026-01-29 01:57:09.615 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.28.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 01:57:09.615 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 01:57:09.616 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.28.20:5700/1) Recv NOMTXPOWER cmd
2026-01-29 01:57:09.616 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.28.20:5700/1) Recv SETFORMAT cmd
2026-01-29 01:57:09.616 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.28.20:5700/1) TRXD header version 1 -> 1
2026-01-29 01:57:09.618 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.28.20:5700/2) Recv RXTUNE cmd
2026-01-29 01:57:09.619 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.28.20:5700/2) Recv TXTUNE cmd
2026-01-29 01:57:09.619 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.28.20:5700/2) Recv SETFORMAT cmd
2026-01-29 01:57:09.619 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.28.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 01:57:09.620 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 01:57:09.620 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.28.20:5700/2) Recv NOMTXPOWER cmd
2026-01-29 01:57:09.620 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.28.20:5700/2) Recv SETFORMAT cmd
2026-01-29 01:57:09.620 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.28.20:5700/2) TRXD header version 1 -> 1
2026-01-29 01:57:09.622 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.28.20:5700/3) Recv RXTUNE cmd
2026-01-29 01:57:09.622 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.28.20:5700/3) Recv TXTUNE cmd
2026-01-29 01:57:09.623 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.28.20:5700/3) Recv SETFORMAT cmd
2026-01-29 01:57:09.623 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.28.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 01:57:09.623 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 01:57:09.623 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.28.20:5700/3) Recv NOMTXPOWER cmd
2026-01-29 01:57:09.623 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.28.20:5700/3) Recv SETFORMAT cmd
2026-01-29 01:57:09.623 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.28.20:5700/3) TRXD header version 1 -> 1
2026-01-29 01:57:09.627 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.28.20:5700) Recv RXTUNE cmd
2026-01-29 01:57:09.627 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETTSC
2026-01-29 01:57:09.627 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETTSC
2026-01-29 01:57:09.627 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETTSC
2026-01-29 01:57:09.627 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.28.20:5700) Recv TXTUNE cmd
2026-01-29 01:57:09.627 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETRXGAIN
2026-01-29 01:57:09.628 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETRXGAIN
2026-01-29 01:57:09.628 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETRXGAIN
2026-01-29 01:57:09.628 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETTSC
2026-01-29 01:57:09.628 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:57:09.628 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:57:09.628 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.28.20:5700) Recv NOMTXPOWER cmd
2026-01-29 01:57:09.628 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:57:09.628 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:57:09.628 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:57:09.628 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.28.20:5700) Recv POWERON CMD
2026-01-29 01:57:09.628 [INFO] ctrl_if_trx.py:109 (BTS@172.18.28.20:5700) Starting transceiver...
2026-01-29 01:57:09.628 [INFO] transceiver.py:243 Starting clock generator
2026-01-29 01:57:09.628 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-01-29 01:57:09.628 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:57:09.629 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:57:09.629 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:57:09.629 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETRXGAIN
2026-01-29 01:57:09.629 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:57:09.629 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:57:09.629 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:57:09.629 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 01:57:09.629 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:57:09.629 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:57:09.629 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:57:09.629 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 01:57:09.630 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:57:09.630 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:57:09.630 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:57:09.630 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 01:57:09.630 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:57:09.630 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:57:09.630 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 01:57:09.631 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:57:09.631 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:57:09.631 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:57:09.631 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 01:57:09.631 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:57:09.631 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:57:09.631 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 01:57:09.631 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 01:57:09.631 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 01:57:09.633 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-01-29 01:57:10.116 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-01-29 01:57:10.157 [DEBUG] fake_trx.py:278 (BTS@172.18.28.20:5700) Recv FAKE_TOA cmd
2026-01-29 01:57:10.159 [DEBUG] fake_trx.py:297 (BTS@172.18.28.20:5700) Recv FAKE_RSSI cmd
2026-01-29 01:57:10.161 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:57:10.162 [DEBUG] fake_trx.py:322 (BTS@172.18.28.20:5700) Recv FAKE_CI cmd
2026-01-29 01:57:10.185 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 01:57:10.185 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 01:57:10.186 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 01:57:10.215 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 01:57:10.216 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 01:57:10.216 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 01:57:10.216 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 01:57:10.217 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 01:57:10.217 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 01:57:10.217 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 01:57:10.217 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.28.20:5700) Recv POWEROFF cmd
2026-01-29 01:57:10.217 [INFO] ctrl_if_trx.py:117 (BTS@172.18.28.20:5700) Stopping transceiver...
2026-01-29 01:57:10.217 [INFO] transceiver.py:246 Stopping clock generator
2026-01-29 01:57:10.217 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 01:57:10.218 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=125 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 01:57:10.218 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=125 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 01:57:10.218 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=125 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 01:57:10.218 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=125 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 01:57:10.218 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=125 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 01:57:10.218 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=125 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 01:57:10.218 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=125 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 01:57:10.218 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=125 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 01:57:15.219 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.28.20:5700) Recv POWEROFF cmd
2026-01-29 01:57:15.220 [INFO] ctrl_if_trx.py:117 (BTS@172.18.28.20:5700) Stopping transceiver...
2026-01-29 01:57:15.221 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 01:57:15.223 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 01:57:15.223 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 01:57:15.224 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 01:57:15.232 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 01:57:15.234 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.28.20:5700) Recv SETFORMAT cmd
2026-01-29 01:57:15.234 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.28.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 01:57:15.234 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.28.20:5700) Recv SETFORMAT cmd
2026-01-29 01:57:15.234 [INFO] ctrl_if_trx.py:201 (BTS@172.18.28.20:5700) TRXD header version 1 -> 1
2026-01-29 01:57:15.237 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.28.20:5700/1) Recv RXTUNE cmd
2026-01-29 01:57:15.238 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.28.20:5700/1) Recv TXTUNE cmd
2026-01-29 01:57:15.238 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.28.20:5700/1) Recv SETFORMAT cmd
2026-01-29 01:57:15.238 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.28.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 01:57:15.239 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 01:57:15.239 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.28.20:5700/1) Recv NOMTXPOWER cmd
2026-01-29 01:57:15.240 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.28.20:5700/1) Recv SETFORMAT cmd
2026-01-29 01:57:15.240 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.28.20:5700/1) TRXD header version 1 -> 1
2026-01-29 01:57:15.241 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.28.20:5700/2) Recv RXTUNE cmd
2026-01-29 01:57:15.241 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.28.20:5700/2) Recv TXTUNE cmd
2026-01-29 01:57:15.241 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.28.20:5700/2) Recv SETFORMAT cmd
2026-01-29 01:57:15.241 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.28.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 01:57:15.242 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 01:57:15.242 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.28.20:5700/2) Recv NOMTXPOWER cmd
2026-01-29 01:57:15.242 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.28.20:5700/2) Recv SETFORMAT cmd
2026-01-29 01:57:15.242 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.28.20:5700/2) TRXD header version 1 -> 1
2026-01-29 01:57:15.243 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.28.20:5700/3) Recv RXTUNE cmd
2026-01-29 01:57:15.243 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.28.20:5700/3) Recv TXTUNE cmd
2026-01-29 01:57:15.243 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.28.20:5700/3) Recv SETFORMAT cmd
2026-01-29 01:57:15.243 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.28.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 01:57:15.244 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 01:57:15.244 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.28.20:5700/3) Recv NOMTXPOWER cmd
2026-01-29 01:57:15.244 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.28.20:5700/3) Recv SETFORMAT cmd
2026-01-29 01:57:15.244 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.28.20:5700/3) TRXD header version 1 -> 1
2026-01-29 01:57:15.246 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.28.20:5700) Recv RXTUNE cmd
2026-01-29 01:57:15.246 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETTSC
2026-01-29 01:57:15.246 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETTSC
2026-01-29 01:57:15.246 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETTSC
2026-01-29 01:57:15.246 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.28.20:5700) Recv TXTUNE cmd
2026-01-29 01:57:15.246 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETRXGAIN
2026-01-29 01:57:15.246 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETRXGAIN
2026-01-29 01:57:15.246 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETRXGAIN
2026-01-29 01:57:15.246 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETTSC
2026-01-29 01:57:15.246 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:57:15.246 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:57:15.246 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:57:15.246 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.28.20:5700) Recv NOMTXPOWER cmd
2026-01-29 01:57:15.247 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:57:15.247 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:57:15.247 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:57:15.247 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.28.20:5700) Recv POWERON CMD
2026-01-29 01:57:15.247 [INFO] ctrl_if_trx.py:109 (BTS@172.18.28.20:5700) Starting transceiver...
2026-01-29 01:57:15.247 [INFO] transceiver.py:243 Starting clock generator
2026-01-29 01:57:15.247 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-01-29 01:57:15.247 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:57:15.247 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:57:15.247 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:57:15.247 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETRXGAIN
2026-01-29 01:57:15.247 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:57:15.247 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:57:15.247 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:57:15.247 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 01:57:15.247 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:57:15.247 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:57:15.247 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:57:15.247 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 01:57:15.247 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:57:15.247 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:57:15.247 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:57:15.247 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 01:57:15.247 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:57:15.247 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:57:15.247 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 01:57:15.247 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:57:15.248 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:57:15.248 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:57:15.248 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 01:57:15.248 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:57:15.248 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 01:57:15.248 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 01:57:15.248 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 01:57:15.252 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-01-29 01:57:15.735 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-01-29 01:57:15.778 [DEBUG] fake_trx.py:278 (BTS@172.18.28.20:5700) Recv FAKE_TOA cmd
2026-01-29 01:57:15.781 [DEBUG] fake_trx.py:297 (BTS@172.18.28.20:5700) Recv FAKE_RSSI cmd
2026-01-29 01:57:15.782 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:57:15.783 [DEBUG] fake_trx.py:322 (BTS@172.18.28.20:5700) Recv FAKE_CI cmd
2026-01-29 01:57:15.804 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 01:57:15.804 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 01:57:15.804 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 01:57:15.822 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 01:57:15.823 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 01:57:15.823 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 01:57:15.827 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 01:57:15.827 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 01:57:15.827 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 01:57:15.827 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 01:57:15.828 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 01:57:15.828 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 01:57:15.828 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 01:57:15.828 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 01:57:15.828 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.28.20:5700) Recv POWEROFF cmd
2026-01-29 01:57:15.828 [INFO] ctrl_if_trx.py:117 (BTS@172.18.28.20:5700) Stopping transceiver...
2026-01-29 01:57:15.828 [INFO] transceiver.py:246 Stopping clock generator
2026-01-29 01:57:15.828 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=124 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 01:57:15.828 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=124 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 01:57:15.828 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=124 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 01:57:15.828 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=124 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 01:57:15.828 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=124 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 01:57:15.828 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=124 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 01:57:20.830 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.28.20:5700) Recv POWEROFF cmd
2026-01-29 01:57:20.830 [INFO] ctrl_if_trx.py:117 (BTS@172.18.28.20:5700) Stopping transceiver...
2026-01-29 01:57:20.832 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 01:57:20.833 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 01:57:20.833 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 01:57:20.834 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 01:57:20.842 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 01:57:20.843 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.28.20:5700) Recv SETFORMAT cmd
2026-01-29 01:57:20.844 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.28.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 01:57:20.844 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.28.20:5700) Recv SETFORMAT cmd
2026-01-29 01:57:20.844 [INFO] ctrl_if_trx.py:201 (BTS@172.18.28.20:5700) TRXD header version 1 -> 1
2026-01-29 01:57:20.847 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.28.20:5700/1) Recv RXTUNE cmd
2026-01-29 01:57:20.848 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.28.20:5700/1) Recv TXTUNE cmd
2026-01-29 01:57:20.848 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.28.20:5700/1) Recv SETFORMAT cmd
2026-01-29 01:57:20.848 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.28.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 01:57:20.849 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 01:57:20.849 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.28.20:5700/1) Recv NOMTXPOWER cmd
2026-01-29 01:57:20.850 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.28.20:5700/1) Recv SETFORMAT cmd
2026-01-29 01:57:20.850 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.28.20:5700/1) TRXD header version 1 -> 1
2026-01-29 01:57:20.851 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.28.20:5700/2) Recv RXTUNE cmd
2026-01-29 01:57:20.851 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.28.20:5700/2) Recv TXTUNE cmd
2026-01-29 01:57:20.851 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.28.20:5700/2) Recv SETFORMAT cmd
2026-01-29 01:57:20.851 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.28.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 01:57:20.852 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 01:57:20.852 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.28.20:5700/2) Recv NOMTXPOWER cmd
2026-01-29 01:57:20.852 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.28.20:5700/2) Recv SETFORMAT cmd
2026-01-29 01:57:20.852 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.28.20:5700/2) TRXD header version 1 -> 1
2026-01-29 01:57:20.853 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.28.20:5700/3) Recv RXTUNE cmd
2026-01-29 01:57:20.853 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.28.20:5700/3) Recv TXTUNE cmd
2026-01-29 01:57:20.853 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.28.20:5700/3) Recv SETFORMAT cmd
2026-01-29 01:57:20.853 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.28.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 01:57:20.854 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 01:57:20.854 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.28.20:5700/3) Recv NOMTXPOWER cmd
2026-01-29 01:57:20.854 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.28.20:5700/3) Recv SETFORMAT cmd
2026-01-29 01:57:20.854 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.28.20:5700/3) TRXD header version 1 -> 1
2026-01-29 01:57:20.856 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.28.20:5700) Recv RXTUNE cmd
2026-01-29 01:57:20.856 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETTSC
2026-01-29 01:57:20.856 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETTSC
2026-01-29 01:57:20.856 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETTSC
2026-01-29 01:57:20.856 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.28.20:5700) Recv TXTUNE cmd
2026-01-29 01:57:20.856 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETRXGAIN
2026-01-29 01:57:20.857 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETRXGAIN
2026-01-29 01:57:20.857 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETRXGAIN
2026-01-29 01:57:20.857 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETTSC
2026-01-29 01:57:20.857 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:57:20.857 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:57:20.857 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:57:20.857 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.28.20:5700) Recv NOMTXPOWER cmd
2026-01-29 01:57:20.857 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:57:20.857 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:57:20.857 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:57:20.857 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.28.20:5700) Recv POWERON CMD
2026-01-29 01:57:20.857 [INFO] ctrl_if_trx.py:109 (BTS@172.18.28.20:5700) Starting transceiver...
2026-01-29 01:57:20.857 [INFO] transceiver.py:243 Starting clock generator
2026-01-29 01:57:20.857 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-01-29 01:57:20.857 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:57:20.857 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:57:20.857 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:57:20.857 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETRXGAIN
2026-01-29 01:57:20.857 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:57:20.857 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:57:20.858 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:57:20.858 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 01:57:20.858 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:57:20.858 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:57:20.858 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:57:20.858 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 01:57:20.858 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:57:20.858 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:57:20.858 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:57:20.858 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 01:57:20.858 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:57:20.858 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:57:20.858 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:57:20.858 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 01:57:20.858 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:57:20.858 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:57:20.858 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 01:57:20.858 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:57:20.858 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 01:57:20.858 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 01:57:20.858 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 01:57:20.862 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-01-29 01:57:21.345 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-01-29 01:57:21.381 [DEBUG] fake_trx.py:278 (BTS@172.18.28.20:5700) Recv FAKE_TOA cmd
2026-01-29 01:57:21.383 [DEBUG] fake_trx.py:297 (BTS@172.18.28.20:5700) Recv FAKE_RSSI cmd
2026-01-29 01:57:21.384 [DEBUG] fake_trx.py:322 (BTS@172.18.28.20:5700) Recv FAKE_CI cmd
2026-01-29 01:57:21.385 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:57:21.403 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 01:57:21.403 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 01:57:21.403 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 01:57:21.431 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 01:57:21.431 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 01:57:21.431 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 01:57:21.436 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 01:57:21.436 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 01:57:21.436 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 01:57:21.436 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 01:57:21.437 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 01:57:21.437 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 01:57:21.437 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 01:57:21.437 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 01:57:21.437 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.28.20:5700) Recv POWEROFF cmd
2026-01-29 01:57:21.437 [INFO] ctrl_if_trx.py:117 (BTS@172.18.28.20:5700) Stopping transceiver...
2026-01-29 01:57:21.437 [INFO] transceiver.py:246 Stopping clock generator
2026-01-29 01:57:26.444 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.28.20:5700) Recv POWEROFF cmd
2026-01-29 01:57:26.444 [INFO] ctrl_if_trx.py:117 (BTS@172.18.28.20:5700) Stopping transceiver...
2026-01-29 01:57:26.444 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 01:57:26.444 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 01:57:26.444 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 01:57:26.444 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 01:57:26.452 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 01:57:26.453 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.28.20:5700) Recv SETFORMAT cmd
2026-01-29 01:57:26.453 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.28.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 01:57:26.453 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.28.20:5700) Recv SETFORMAT cmd
2026-01-29 01:57:26.454 [INFO] ctrl_if_trx.py:201 (BTS@172.18.28.20:5700) TRXD header version 1 -> 1
2026-01-29 01:57:26.457 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.28.20:5700/1) Recv RXTUNE cmd
2026-01-29 01:57:26.457 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.28.20:5700/1) Recv TXTUNE cmd
2026-01-29 01:57:26.458 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.28.20:5700/1) Recv SETFORMAT cmd
2026-01-29 01:57:26.458 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.28.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 01:57:26.458 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 01:57:26.459 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.28.20:5700/1) Recv NOMTXPOWER cmd
2026-01-29 01:57:26.459 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.28.20:5700/1) Recv SETFORMAT cmd
2026-01-29 01:57:26.459 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.28.20:5700/1) TRXD header version 1 -> 1
2026-01-29 01:57:26.461 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.28.20:5700/2) Recv RXTUNE cmd
2026-01-29 01:57:26.461 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.28.20:5700/2) Recv TXTUNE cmd
2026-01-29 01:57:26.461 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.28.20:5700/2) Recv SETFORMAT cmd
2026-01-29 01:57:26.461 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.28.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 01:57:26.461 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 01:57:26.461 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.28.20:5700/2) Recv NOMTXPOWER cmd
2026-01-29 01:57:26.461 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.28.20:5700/2) Recv SETFORMAT cmd
2026-01-29 01:57:26.461 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.28.20:5700/2) TRXD header version 1 -> 1
2026-01-29 01:57:26.463 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.28.20:5700/3) Recv RXTUNE cmd
2026-01-29 01:57:26.464 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.28.20:5700/3) Recv TXTUNE cmd
2026-01-29 01:57:26.464 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.28.20:5700/3) Recv SETFORMAT cmd
2026-01-29 01:57:26.464 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.28.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 01:57:26.464 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 01:57:26.464 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.28.20:5700/3) Recv NOMTXPOWER cmd
2026-01-29 01:57:26.464 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.28.20:5700/3) Recv SETFORMAT cmd
2026-01-29 01:57:26.464 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.28.20:5700/3) TRXD header version 1 -> 1
2026-01-29 01:57:26.467 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.28.20:5700) Recv RXTUNE cmd
2026-01-29 01:57:26.467 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETTSC
2026-01-29 01:57:26.467 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETTSC
2026-01-29 01:57:26.467 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETTSC
2026-01-29 01:57:26.467 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.28.20:5700) Recv TXTUNE cmd
2026-01-29 01:57:26.467 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETRXGAIN
2026-01-29 01:57:26.467 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETRXGAIN
2026-01-29 01:57:26.467 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETRXGAIN
2026-01-29 01:57:26.467 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETTSC
2026-01-29 01:57:26.467 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:57:26.467 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:57:26.467 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:57:26.467 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.28.20:5700) Recv NOMTXPOWER cmd
2026-01-29 01:57:26.467 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:57:26.467 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:57:26.467 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:57:26.467 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.28.20:5700) Recv POWERON CMD
2026-01-29 01:57:26.467 [INFO] ctrl_if_trx.py:109 (BTS@172.18.28.20:5700) Starting transceiver...
2026-01-29 01:57:26.467 [INFO] transceiver.py:243 Starting clock generator
2026-01-29 01:57:26.467 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-01-29 01:57:26.467 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:57:26.468 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:57:26.468 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:57:26.468 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETRXGAIN
2026-01-29 01:57:26.468 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:57:26.468 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:57:26.468 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:57:26.468 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 01:57:26.468 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:57:26.468 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:57:26.468 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:57:26.468 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 01:57:26.468 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:57:26.468 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:57:26.468 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:57:26.468 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 01:57:26.468 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:57:26.468 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:57:26.468 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:57:26.469 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 01:57:26.469 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:57:26.469 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:57:26.469 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:57:26.469 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 01:57:26.469 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 01:57:26.469 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 01:57:26.469 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 01:57:26.472 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-01-29 01:57:26.954 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-01-29 01:57:26.997 [DEBUG] fake_trx.py:278 (BTS@172.18.28.20:5700) Recv FAKE_TOA cmd
2026-01-29 01:57:26.999 [DEBUG] fake_trx.py:297 (BTS@172.18.28.20:5700) Recv FAKE_RSSI cmd
2026-01-29 01:57:27.002 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:57:27.002 [DEBUG] fake_trx.py:322 (BTS@172.18.28.20:5700) Recv FAKE_CI cmd
2026-01-29 01:57:27.011 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 01:57:27.011 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 01:57:27.011 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 01:57:27.012 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 01:57:27.012 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 01:57:27.013 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 01:57:27.013 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.28.22:6700) Recv POWERON CMD
2026-01-29 01:57:27.014 [INFO] ctrl_if_trx.py:109 (MS@172.18.28.22:6700) Starting transceiver...
2026-01-29 01:57:27.432 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-01-29 01:57:27.470 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 01:57:27.470 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 01:57:27.472 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 01:57:27.473 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 01:57:27.909 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-01-29 01:57:28.387 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-01-29 01:57:28.471 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 01:57:28.471 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 01:57:28.472 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 01:57:28.475 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 01:57:28.865 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-01-29 01:57:29.343 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-01-29 01:57:29.472 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 01:57:29.472 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 01:57:29.473 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 01:57:29.476 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 01:57:29.821 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-01-29 01:57:30.298 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-01-29 01:57:30.473 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 01:57:30.473 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 01:57:30.474 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 01:57:30.477 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 01:57:30.776 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-01-29 01:57:31.253 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-01-29 01:57:31.474 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 01:57:31.474 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 01:57:31.474 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 01:57:31.478 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 01:57:31.731 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-01-29 01:57:32.209 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-01-29 01:57:32.687 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-01-29 01:57:33.164 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-01-29 01:57:33.641 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-01-29 01:57:34.119 [DEBUG] clck_gen.py:113 IND CLOCK 1632
2026-01-29 01:57:34.597 [DEBUG] clck_gen.py:113 IND CLOCK 1734
2026-01-29 01:57:35.075 [DEBUG] clck_gen.py:113 IND CLOCK 1836
2026-01-29 01:57:35.552 [DEBUG] clck_gen.py:113 IND CLOCK 1938
2026-01-29 01:57:36.031 [DEBUG] clck_gen.py:113 IND CLOCK 2040
2026-01-29 01:57:36.508 [DEBUG] clck_gen.py:113 IND CLOCK 2142
2026-01-29 01:57:36.986 [DEBUG] clck_gen.py:113 IND CLOCK 2244
2026-01-29 01:57:37.464 [DEBUG] clck_gen.py:113 IND CLOCK 2346
2026-01-29 01:57:37.941 [DEBUG] clck_gen.py:113 IND CLOCK 2448
2026-01-29 01:57:38.419 [DEBUG] clck_gen.py:113 IND CLOCK 2550
2026-01-29 01:57:38.896 [DEBUG] clck_gen.py:113 IND CLOCK 2652
2026-01-29 01:57:39.373 [DEBUG] clck_gen.py:113 IND CLOCK 2754
2026-01-29 01:57:39.851 [DEBUG] clck_gen.py:113 IND CLOCK 2856
2026-01-29 01:57:40.329 [DEBUG] clck_gen.py:113 IND CLOCK 2958
2026-01-29 01:57:40.807 [DEBUG] clck_gen.py:113 IND CLOCK 3060
2026-01-29 01:57:41.284 [DEBUG] clck_gen.py:113 IND CLOCK 3162
2026-01-29 01:57:41.762 [DEBUG] clck_gen.py:113 IND CLOCK 3264
2026-01-29 01:57:42.240 [DEBUG] clck_gen.py:113 IND CLOCK 3366
2026-01-29 01:57:42.718 [DEBUG] clck_gen.py:113 IND CLOCK 3468
2026-01-29 01:57:43.195 [DEBUG] clck_gen.py:113 IND CLOCK 3570
2026-01-29 01:57:43.673 [DEBUG] clck_gen.py:113 IND CLOCK 3672
2026-01-29 01:57:44.151 [DEBUG] clck_gen.py:113 IND CLOCK 3774
2026-01-29 01:57:44.628 [DEBUG] clck_gen.py:113 IND CLOCK 3876
2026-01-29 01:57:45.106 [DEBUG] clck_gen.py:113 IND CLOCK 3978
2026-01-29 01:57:45.584 [DEBUG] clck_gen.py:113 IND CLOCK 4080
2026-01-29 01:57:46.062 [DEBUG] clck_gen.py:113 IND CLOCK 4182
2026-01-29 01:57:46.540 [DEBUG] clck_gen.py:113 IND CLOCK 4284
2026-01-29 01:57:47.017 [DEBUG] clck_gen.py:113 IND CLOCK 4386
2026-01-29 01:57:47.495 [DEBUG] clck_gen.py:113 IND CLOCK 4488
2026-01-29 01:57:47.972 [DEBUG] clck_gen.py:113 IND CLOCK 4590
2026-01-29 01:57:48.450 [DEBUG] clck_gen.py:113 IND CLOCK 4692
2026-01-29 01:57:48.928 [DEBUG] clck_gen.py:113 IND CLOCK 4794
2026-01-29 01:57:49.406 [DEBUG] clck_gen.py:113 IND CLOCK 4896
2026-01-29 01:57:49.883 [DEBUG] clck_gen.py:113 IND CLOCK 4998
2026-01-29 01:57:50.361 [DEBUG] clck_gen.py:113 IND CLOCK 5100
2026-01-29 01:57:50.839 [DEBUG] clck_gen.py:113 IND CLOCK 5202
2026-01-29 01:57:51.317 [DEBUG] clck_gen.py:113 IND CLOCK 5304
2026-01-29 01:57:51.795 [DEBUG] clck_gen.py:113 IND CLOCK 5406
2026-01-29 01:57:52.273 [DEBUG] clck_gen.py:113 IND CLOCK 5508
2026-01-29 01:57:52.750 [DEBUG] clck_gen.py:113 IND CLOCK 5610
2026-01-29 01:57:53.228 [DEBUG] clck_gen.py:113 IND CLOCK 5712
2026-01-29 01:57:53.705 [DEBUG] clck_gen.py:113 IND CLOCK 5814
2026-01-29 01:57:54.182 [DEBUG] clck_gen.py:113 IND CLOCK 5916
2026-01-29 01:57:54.659 [DEBUG] clck_gen.py:113 IND CLOCK 6018
2026-01-29 01:57:55.137 [DEBUG] clck_gen.py:113 IND CLOCK 6120
2026-01-29 01:57:55.614 [DEBUG] clck_gen.py:113 IND CLOCK 6222
2026-01-29 01:57:56.092 [DEBUG] clck_gen.py:113 IND CLOCK 6324
2026-01-29 01:57:56.570 [DEBUG] clck_gen.py:113 IND CLOCK 6426
2026-01-29 01:57:57.048 [DEBUG] clck_gen.py:113 IND CLOCK 6528
2026-01-29 01:57:57.525 [DEBUG] clck_gen.py:113 IND CLOCK 6630
2026-01-29 01:57:58.003 [DEBUG] clck_gen.py:113 IND CLOCK 6732
2026-01-29 01:57:58.481 [DEBUG] clck_gen.py:113 IND CLOCK 6834
2026-01-29 01:57:58.959 [DEBUG] clck_gen.py:113 IND CLOCK 6936
2026-01-29 01:57:59.437 [DEBUG] clck_gen.py:113 IND CLOCK 7038
2026-01-29 01:57:59.915 [DEBUG] clck_gen.py:113 IND CLOCK 7140
2026-01-29 01:58:00.393 [DEBUG] clck_gen.py:113 IND CLOCK 7242
2026-01-29 01:58:00.490 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 01:58:00.491 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 01:58:00.496 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 01:58:00.497 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 01:58:00.497 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 01:58:00.497 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 01:58:00.503 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 01:58:00.504 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 01:58:00.504 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 01:58:00.504 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 01:58:00.504 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.28.20:5700) Recv POWEROFF cmd
2026-01-29 01:58:00.504 [INFO] ctrl_if_trx.py:117 (BTS@172.18.28.20:5700) Stopping transceiver...
2026-01-29 01:58:00.504 [INFO] transceiver.py:246 Stopping clock generator
2026-01-29 01:58:00.504 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=7266 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 01:58:00.504 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=7266 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 01:58:00.505 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=7266 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 01:58:00.505 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=7266 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 01:58:00.505 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=7266 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 01:58:00.505 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=7266 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 01:58:00.505 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=7267 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 01:58:00.505 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=7267 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 01:58:00.505 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=7267 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 01:58:00.505 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=7267 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 01:58:00.505 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=7267 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 01:58:00.505 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=7267 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 01:58:00.505 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=7267 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 01:58:00.505 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=7267 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 01:58:00.505 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=7268 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 01:58:00.505 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=7268 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 01:58:00.505 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=7268 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 01:58:00.505 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=7268 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 01:58:00.505 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=7268 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 01:58:00.506 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=7268 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 01:58:00.506 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=7268 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 01:58:00.506 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=7268 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 01:58:05.500 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.28.20:5700) Recv POWEROFF cmd
2026-01-29 01:58:05.501 [INFO] ctrl_if_trx.py:117 (BTS@172.18.28.20:5700) Stopping transceiver...
2026-01-29 01:58:05.502 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 01:58:05.504 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 01:58:05.504 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 01:58:05.505 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 01:58:05.514 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 01:58:05.515 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.28.20:5700) Recv SETFORMAT cmd
2026-01-29 01:58:05.515 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.28.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 01:58:05.516 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.28.20:5700) Recv SETFORMAT cmd
2026-01-29 01:58:05.516 [INFO] ctrl_if_trx.py:201 (BTS@172.18.28.20:5700) TRXD header version 1 -> 1
2026-01-29 01:58:05.520 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.28.20:5700/1) Recv RXTUNE cmd
2026-01-29 01:58:05.520 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.28.20:5700/1) Recv TXTUNE cmd
2026-01-29 01:58:05.521 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.28.20:5700/1) Recv SETFORMAT cmd
2026-01-29 01:58:05.521 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.28.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 01:58:05.521 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 01:58:05.522 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.28.20:5700/1) Recv NOMTXPOWER cmd
2026-01-29 01:58:05.522 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.28.20:5700/1) Recv SETFORMAT cmd
2026-01-29 01:58:05.522 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.28.20:5700/1) TRXD header version 1 -> 1
2026-01-29 01:58:05.523 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.28.20:5700/2) Recv RXTUNE cmd
2026-01-29 01:58:05.524 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.28.20:5700/2) Recv TXTUNE cmd
2026-01-29 01:58:05.524 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.28.20:5700/2) Recv SETFORMAT cmd
2026-01-29 01:58:05.524 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.28.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 01:58:05.524 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 01:58:05.525 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.28.20:5700/2) Recv NOMTXPOWER cmd
2026-01-29 01:58:05.525 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.28.20:5700/2) Recv SETFORMAT cmd
2026-01-29 01:58:05.525 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.28.20:5700/2) TRXD header version 1 -> 1
2026-01-29 01:58:05.526 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.28.20:5700/3) Recv RXTUNE cmd
2026-01-29 01:58:05.526 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.28.20:5700/3) Recv TXTUNE cmd
2026-01-29 01:58:05.527 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.28.20:5700/3) Recv SETFORMAT cmd
2026-01-29 01:58:05.527 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.28.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 01:58:05.527 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 01:58:05.527 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.28.20:5700/3) Recv NOMTXPOWER cmd
2026-01-29 01:58:05.527 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.28.20:5700/3) Recv SETFORMAT cmd
2026-01-29 01:58:05.527 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.28.20:5700/3) TRXD header version 1 -> 1
2026-01-29 01:58:05.529 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.28.20:5700) Recv RXTUNE cmd
2026-01-29 01:58:05.529 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETTSC
2026-01-29 01:58:05.529 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETTSC
2026-01-29 01:58:05.529 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETTSC
2026-01-29 01:58:05.529 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.28.20:5700) Recv TXTUNE cmd
2026-01-29 01:58:05.529 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETRXGAIN
2026-01-29 01:58:05.529 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETRXGAIN
2026-01-29 01:58:05.530 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETRXGAIN
2026-01-29 01:58:05.530 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETTSC
2026-01-29 01:58:05.530 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:58:05.530 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:58:05.530 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.28.20:5700) Recv NOMTXPOWER cmd
2026-01-29 01:58:05.530 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:58:05.530 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:58:05.530 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:58:05.530 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.28.20:5700) Recv POWERON CMD
2026-01-29 01:58:05.530 [INFO] ctrl_if_trx.py:109 (BTS@172.18.28.20:5700) Starting transceiver...
2026-01-29 01:58:05.530 [INFO] transceiver.py:243 Starting clock generator
2026-01-29 01:58:05.530 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-01-29 01:58:05.530 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:58:05.530 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:58:05.530 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:58:05.530 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETRXGAIN
2026-01-29 01:58:05.530 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:58:05.530 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:58:05.530 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:58:05.531 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 01:58:05.531 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:58:05.531 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:58:05.531 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:58:05.531 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 01:58:05.531 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:58:05.531 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:58:05.531 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:58:05.531 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 01:58:05.531 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:58:05.531 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:58:05.531 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:58:05.531 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 01:58:05.531 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:58:05.531 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:58:05.531 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:58:05.531 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 01:58:05.531 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:58:05.531 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 01:58:05.531 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 01:58:05.531 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 01:58:05.535 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-01-29 01:58:06.018 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-01-29 01:58:06.063 [DEBUG] fake_trx.py:278 (BTS@172.18.28.20:5700) Recv FAKE_TOA cmd
2026-01-29 01:58:06.065 [DEBUG] fake_trx.py:297 (BTS@172.18.28.20:5700) Recv FAKE_RSSI cmd
2026-01-29 01:58:06.066 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:58:06.068 [DEBUG] fake_trx.py:322 (BTS@172.18.28.20:5700) Recv FAKE_CI cmd
2026-01-29 01:58:06.499 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-01-29 01:58:06.533 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 01:58:06.534 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 01:58:06.534 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 01:58:06.534 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 01:58:06.978 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-01-29 01:58:07.456 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-01-29 01:58:07.535 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 01:58:07.535 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 01:58:07.535 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 01:58:07.535 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 01:58:07.935 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-01-29 01:58:08.417 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-01-29 01:58:08.536 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 01:58:08.536 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 01:58:08.536 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 01:58:08.536 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 01:58:08.888 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-01-29 01:58:09.089 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:58:09.094 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 01:58:09.094 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 01:58:09.094 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 01:58:09.097 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 01:58:09.097 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 01:58:09.097 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 01:58:09.097 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 01:58:09.097 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 01:58:09.097 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.28.20:5700) Recv POWEROFF cmd
2026-01-29 01:58:09.097 [INFO] ctrl_if_trx.py:117 (BTS@172.18.28.20:5700) Stopping transceiver...
2026-01-29 01:58:09.098 [INFO] transceiver.py:246 Stopping clock generator
2026-01-29 01:58:09.098 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=761 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 01:58:09.098 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=761 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 01:58:09.098 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=761 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 01:58:14.098 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.28.20:5700) Recv POWEROFF cmd
2026-01-29 01:58:14.098 [INFO] ctrl_if_trx.py:117 (BTS@172.18.28.20:5700) Stopping transceiver...
2026-01-29 01:58:14.099 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 01:58:14.101 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 01:58:14.102 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 01:58:14.102 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 01:58:14.112 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 01:58:14.113 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.28.20:5700) Recv SETFORMAT cmd
2026-01-29 01:58:14.114 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.28.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 01:58:14.114 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.28.20:5700) Recv SETFORMAT cmd
2026-01-29 01:58:14.114 [INFO] ctrl_if_trx.py:201 (BTS@172.18.28.20:5700) TRXD header version 1 -> 1
2026-01-29 01:58:14.118 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.28.20:5700/1) Recv RXTUNE cmd
2026-01-29 01:58:14.118 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.28.20:5700/1) Recv TXTUNE cmd
2026-01-29 01:58:14.118 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.28.20:5700/1) Recv SETFORMAT cmd
2026-01-29 01:58:14.118 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.28.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 01:58:14.119 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 01:58:14.119 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.28.20:5700/1) Recv NOMTXPOWER cmd
2026-01-29 01:58:14.119 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.28.20:5700/1) Recv SETFORMAT cmd
2026-01-29 01:58:14.119 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.28.20:5700/1) TRXD header version 1 -> 1
2026-01-29 01:58:14.122 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.28.20:5700/2) Recv RXTUNE cmd
2026-01-29 01:58:14.122 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.28.20:5700/2) Recv TXTUNE cmd
2026-01-29 01:58:14.122 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.28.20:5700/2) Recv SETFORMAT cmd
2026-01-29 01:58:14.122 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.28.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 01:58:14.122 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 01:58:14.122 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.28.20:5700/2) Recv NOMTXPOWER cmd
2026-01-29 01:58:14.122 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.28.20:5700/2) Recv SETFORMAT cmd
2026-01-29 01:58:14.122 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.28.20:5700/2) TRXD header version 1 -> 1
2026-01-29 01:58:14.125 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.28.20:5700/3) Recv RXTUNE cmd
2026-01-29 01:58:14.125 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.28.20:5700/3) Recv TXTUNE cmd
2026-01-29 01:58:14.125 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.28.20:5700/3) Recv SETFORMAT cmd
2026-01-29 01:58:14.125 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.28.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 01:58:14.125 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 01:58:14.125 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.28.20:5700/3) Recv NOMTXPOWER cmd
2026-01-29 01:58:14.125 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.28.20:5700/3) Recv SETFORMAT cmd
2026-01-29 01:58:14.125 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.28.20:5700/3) TRXD header version 1 -> 1
2026-01-29 01:58:14.128 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.28.20:5700) Recv RXTUNE cmd
2026-01-29 01:58:14.128 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETTSC
2026-01-29 01:58:14.128 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETTSC
2026-01-29 01:58:14.129 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETTSC
2026-01-29 01:58:14.129 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.28.20:5700) Recv TXTUNE cmd
2026-01-29 01:58:14.129 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETRXGAIN
2026-01-29 01:58:14.129 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETRXGAIN
2026-01-29 01:58:14.129 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETRXGAIN
2026-01-29 01:58:14.129 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETTSC
2026-01-29 01:58:14.129 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:58:14.129 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:58:14.129 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:58:14.129 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.28.20:5700) Recv NOMTXPOWER cmd
2026-01-29 01:58:14.129 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:58:14.129 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:58:14.129 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:58:14.129 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.28.20:5700) Recv POWERON CMD
2026-01-29 01:58:14.129 [INFO] ctrl_if_trx.py:109 (BTS@172.18.28.20:5700) Starting transceiver...
2026-01-29 01:58:14.129 [INFO] transceiver.py:243 Starting clock generator
2026-01-29 01:58:14.129 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-01-29 01:58:14.129 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:58:14.130 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:58:14.130 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:58:14.130 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETRXGAIN
2026-01-29 01:58:14.130 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:58:14.130 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:58:14.130 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 01:58:14.130 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:58:14.130 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:58:14.130 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:58:14.130 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 01:58:14.130 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:58:14.130 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:58:14.130 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:58:14.130 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 01:58:14.130 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:58:14.130 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:58:14.130 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:58:14.130 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 01:58:14.131 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:58:14.131 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:58:14.131 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:58:14.131 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 01:58:14.131 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:58:14.131 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 01:58:14.131 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 01:58:14.131 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 01:58:14.134 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-01-29 01:58:14.616 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-01-29 01:58:14.661 [DEBUG] fake_trx.py:278 (BTS@172.18.28.20:5700) Recv FAKE_TOA cmd
2026-01-29 01:58:14.663 [DEBUG] fake_trx.py:297 (BTS@172.18.28.20:5700) Recv FAKE_RSSI cmd
2026-01-29 01:58:14.665 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:58:14.666 [DEBUG] fake_trx.py:322 (BTS@172.18.28.20:5700) Recv FAKE_CI cmd
2026-01-29 01:58:15.091 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-01-29 01:58:15.132 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 01:58:15.133 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 01:58:15.133 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 01:58:15.137 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 01:58:15.560 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-01-29 01:58:16.031 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-01-29 01:58:16.134 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 01:58:16.135 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 01:58:16.135 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 01:58:16.139 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 01:58:16.510 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-01-29 01:58:16.991 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-01-29 01:58:17.135 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 01:58:17.136 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 01:58:17.136 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 01:58:17.139 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 01:58:17.470 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-01-29 01:58:17.948 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-01-29 01:58:18.137 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 01:58:18.137 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 01:58:18.137 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 01:58:18.141 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 01:58:18.426 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-01-29 01:58:18.906 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-01-29 01:58:19.138 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 01:58:19.138 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 01:58:19.138 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 01:58:19.142 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 01:58:19.387 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-01-29 01:58:19.867 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-01-29 01:58:20.342 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-01-29 01:58:20.678 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 01:58:20.678 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 01:58:20.678 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 01:58:20.678 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 01:58:20.679 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 01:58:20.679 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 01:58:20.679 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 01:58:20.679 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 01:58:20.679 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.28.20:5700) Recv POWEROFF cmd
2026-01-29 01:58:20.679 [INFO] ctrl_if_trx.py:117 (BTS@172.18.28.20:5700) Stopping transceiver...
2026-01-29 01:58:20.679 [INFO] transceiver.py:246 Stopping clock generator
2026-01-29 01:58:20.679 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=1401 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 01:58:20.679 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=1401 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 01:58:20.679 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=1401 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 01:58:20.679 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=1401 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 01:58:20.679 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=1401 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 01:58:20.679 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=1401 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 01:58:25.682 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.28.20:5700) Recv POWEROFF cmd
2026-01-29 01:58:25.682 [INFO] ctrl_if_trx.py:117 (BTS@172.18.28.20:5700) Stopping transceiver...
2026-01-29 01:58:25.684 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 01:58:25.685 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 01:58:25.686 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 01:58:25.687 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 01:58:25.694 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 01:58:25.695 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.28.20:5700) Recv SETFORMAT cmd
2026-01-29 01:58:25.695 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.28.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 01:58:25.695 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.28.20:5700) Recv SETFORMAT cmd
2026-01-29 01:58:25.695 [INFO] ctrl_if_trx.py:201 (BTS@172.18.28.20:5700) TRXD header version 1 -> 1
2026-01-29 01:58:25.697 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.28.20:5700/1) Recv RXTUNE cmd
2026-01-29 01:58:25.697 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.28.20:5700/1) Recv TXTUNE cmd
2026-01-29 01:58:25.697 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.28.20:5700/1) Recv SETFORMAT cmd
2026-01-29 01:58:25.697 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.28.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 01:58:25.698 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 01:58:25.698 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.28.20:5700/1) Recv NOMTXPOWER cmd
2026-01-29 01:58:25.698 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.28.20:5700/1) Recv SETFORMAT cmd
2026-01-29 01:58:25.698 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.28.20:5700/1) TRXD header version 1 -> 1
2026-01-29 01:58:25.699 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.28.20:5700/2) Recv RXTUNE cmd
2026-01-29 01:58:25.699 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.28.20:5700/2) Recv TXTUNE cmd
2026-01-29 01:58:25.699 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.28.20:5700/2) Recv SETFORMAT cmd
2026-01-29 01:58:25.699 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.28.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 01:58:25.700 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 01:58:25.700 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.28.20:5700/2) Recv NOMTXPOWER cmd
2026-01-29 01:58:25.700 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.28.20:5700/2) Recv SETFORMAT cmd
2026-01-29 01:58:25.700 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.28.20:5700/2) TRXD header version 1 -> 1
2026-01-29 01:58:25.701 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.28.20:5700/3) Recv RXTUNE cmd
2026-01-29 01:58:25.701 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.28.20:5700/3) Recv TXTUNE cmd
2026-01-29 01:58:25.701 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.28.20:5700/3) Recv SETFORMAT cmd
2026-01-29 01:58:25.701 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.28.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 01:58:25.701 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 01:58:25.701 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.28.20:5700/3) Recv NOMTXPOWER cmd
2026-01-29 01:58:25.701 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.28.20:5700/3) Recv SETFORMAT cmd
2026-01-29 01:58:25.701 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.28.20:5700/3) TRXD header version 1 -> 1
2026-01-29 01:58:25.703 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.28.20:5700) Recv RXTUNE cmd
2026-01-29 01:58:25.703 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETTSC
2026-01-29 01:58:25.703 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETTSC
2026-01-29 01:58:25.703 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETTSC
2026-01-29 01:58:25.703 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.28.20:5700) Recv TXTUNE cmd
2026-01-29 01:58:25.704 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETRXGAIN
2026-01-29 01:58:25.704 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETRXGAIN
2026-01-29 01:58:25.704 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETRXGAIN
2026-01-29 01:58:25.704 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETTSC
2026-01-29 01:58:25.704 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:58:25.704 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:58:25.704 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:58:25.704 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.28.20:5700) Recv NOMTXPOWER cmd
2026-01-29 01:58:25.704 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:58:25.704 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:58:25.704 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:58:25.704 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.28.20:5700) Recv POWERON CMD
2026-01-29 01:58:25.704 [INFO] ctrl_if_trx.py:109 (BTS@172.18.28.20:5700) Starting transceiver...
2026-01-29 01:58:25.704 [INFO] transceiver.py:243 Starting clock generator
2026-01-29 01:58:25.704 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-01-29 01:58:25.704 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:58:25.704 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:58:25.704 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:58:25.704 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETRXGAIN
2026-01-29 01:58:25.704 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:58:25.705 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:58:25.705 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:58:25.705 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 01:58:25.705 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:58:25.705 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:58:25.705 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:58:25.705 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 01:58:25.705 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:58:25.705 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:58:25.705 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:58:25.705 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 01:58:25.705 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:58:25.705 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:58:25.706 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:58:25.706 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 01:58:25.706 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:58:25.706 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:58:25.706 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:58:25.706 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 01:58:25.706 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 01:58:25.706 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 01:58:25.706 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 01:58:25.709 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-01-29 01:58:26.191 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-01-29 01:58:26.238 [DEBUG] fake_trx.py:278 (BTS@172.18.28.20:5700) Recv FAKE_TOA cmd
2026-01-29 01:58:26.241 [DEBUG] fake_trx.py:297 (BTS@172.18.28.20:5700) Recv FAKE_RSSI cmd
2026-01-29 01:58:26.242 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:58:26.242 [DEBUG] fake_trx.py:322 (BTS@172.18.28.20:5700) Recv FAKE_CI cmd
2026-01-29 01:58:26.669 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-01-29 01:58:26.708 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 01:58:26.708 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 01:58:26.710 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 01:58:26.712 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 01:58:27.149 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-01-29 01:58:27.629 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-01-29 01:58:27.709 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 01:58:27.709 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 01:58:27.711 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 01:58:27.714 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 01:58:28.108 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-01-29 01:58:28.584 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-01-29 01:58:28.710 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 01:58:28.711 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 01:58:28.712 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 01:58:28.715 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 01:58:29.064 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-01-29 01:58:29.543 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-01-29 01:58:29.712 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 01:58:29.713 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 01:58:29.714 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 01:58:29.716 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 01:58:30.021 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-01-29 01:58:30.503 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-01-29 01:58:30.713 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 01:58:30.714 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 01:58:30.715 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 01:58:30.717 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 01:58:30.977 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-01-29 01:58:31.445 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-01-29 01:58:31.917 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-01-29 01:58:32.257 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 01:58:32.257 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 01:58:32.257 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 01:58:32.257 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 01:58:32.259 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 01:58:32.259 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 01:58:32.259 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 01:58:32.259 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 01:58:32.259 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.28.20:5700) Recv POWEROFF cmd
2026-01-29 01:58:32.259 [INFO] ctrl_if_trx.py:117 (BTS@172.18.28.20:5700) Stopping transceiver...
2026-01-29 01:58:32.259 [INFO] transceiver.py:246 Stopping clock generator
2026-01-29 01:58:32.259 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=1401 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 01:58:32.259 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=1401 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 01:58:37.260 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.28.20:5700) Recv POWEROFF cmd
2026-01-29 01:58:37.261 [INFO] ctrl_if_trx.py:117 (BTS@172.18.28.20:5700) Stopping transceiver...
2026-01-29 01:58:37.262 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 01:58:37.263 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 01:58:37.263 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 01:58:37.264 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 01:58:37.271 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 01:58:37.272 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.28.20:5700) Recv SETFORMAT cmd
2026-01-29 01:58:37.272 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.28.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 01:58:37.273 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.28.20:5700) Recv SETFORMAT cmd
2026-01-29 01:58:37.273 [INFO] ctrl_if_trx.py:201 (BTS@172.18.28.20:5700) TRXD header version 1 -> 1
2026-01-29 01:58:37.275 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.28.20:5700/1) Recv RXTUNE cmd
2026-01-29 01:58:37.276 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.28.20:5700/1) Recv TXTUNE cmd
2026-01-29 01:58:37.276 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.28.20:5700/1) Recv SETFORMAT cmd
2026-01-29 01:58:37.276 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.28.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 01:58:37.276 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 01:58:37.277 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.28.20:5700/1) Recv NOMTXPOWER cmd
2026-01-29 01:58:37.277 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.28.20:5700/1) Recv SETFORMAT cmd
2026-01-29 01:58:37.277 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.28.20:5700/1) TRXD header version 1 -> 1
2026-01-29 01:58:37.278 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.28.20:5700/2) Recv RXTUNE cmd
2026-01-29 01:58:37.278 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.28.20:5700/2) Recv TXTUNE cmd
2026-01-29 01:58:37.278 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.28.20:5700/2) Recv SETFORMAT cmd
2026-01-29 01:58:37.278 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.28.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 01:58:37.278 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 01:58:37.279 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.28.20:5700/2) Recv NOMTXPOWER cmd
2026-01-29 01:58:37.279 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.28.20:5700/2) Recv SETFORMAT cmd
2026-01-29 01:58:37.279 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.28.20:5700/2) TRXD header version 1 -> 1
2026-01-29 01:58:37.281 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.28.20:5700/3) Recv RXTUNE cmd
2026-01-29 01:58:37.281 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.28.20:5700/3) Recv TXTUNE cmd
2026-01-29 01:58:37.281 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.28.20:5700/3) Recv SETFORMAT cmd
2026-01-29 01:58:37.281 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.28.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 01:58:37.281 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 01:58:37.281 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.28.20:5700/3) Recv NOMTXPOWER cmd
2026-01-29 01:58:37.281 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.28.20:5700/3) Recv SETFORMAT cmd
2026-01-29 01:58:37.281 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.28.20:5700/3) TRXD header version 1 -> 1
2026-01-29 01:58:37.284 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.28.20:5700) Recv RXTUNE cmd
2026-01-29 01:58:37.284 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETTSC
2026-01-29 01:58:37.284 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETTSC
2026-01-29 01:58:37.284 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETTSC
2026-01-29 01:58:37.284 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.28.20:5700) Recv TXTUNE cmd
2026-01-29 01:58:37.284 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETRXGAIN
2026-01-29 01:58:37.284 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETRXGAIN
2026-01-29 01:58:37.284 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETRXGAIN
2026-01-29 01:58:37.284 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETTSC
2026-01-29 01:58:37.284 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:58:37.285 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:58:37.285 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.28.20:5700) Recv NOMTXPOWER cmd
2026-01-29 01:58:37.285 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:58:37.285 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:58:37.285 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:58:37.285 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.28.20:5700) Recv POWERON CMD
2026-01-29 01:58:37.285 [INFO] ctrl_if_trx.py:109 (BTS@172.18.28.20:5700) Starting transceiver...
2026-01-29 01:58:37.285 [INFO] transceiver.py:243 Starting clock generator
2026-01-29 01:58:37.285 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-01-29 01:58:37.285 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:58:37.285 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:58:37.285 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:58:37.285 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETRXGAIN
2026-01-29 01:58:37.285 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:58:37.285 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:58:37.286 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:58:37.286 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 01:58:37.286 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:58:37.286 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:58:37.286 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:58:37.286 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 01:58:37.286 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:58:37.286 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:58:37.286 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:58:37.286 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 01:58:37.286 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:58:37.286 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:58:37.286 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:58:37.286 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 01:58:37.286 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:58:37.286 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:58:37.286 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:58:37.286 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 01:58:37.286 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:58:37.286 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 01:58:37.286 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 01:58:37.287 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 01:58:37.290 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-01-29 01:58:37.772 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-01-29 01:58:37.814 [DEBUG] fake_trx.py:278 (BTS@172.18.28.20:5700) Recv FAKE_TOA cmd
2026-01-29 01:58:37.816 [DEBUG] fake_trx.py:297 (BTS@172.18.28.20:5700) Recv FAKE_RSSI cmd
2026-01-29 01:58:37.817 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:58:37.818 [DEBUG] fake_trx.py:322 (BTS@172.18.28.20:5700) Recv FAKE_CI cmd
2026-01-29 01:58:38.251 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-01-29 01:58:38.288 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 01:58:38.289 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 01:58:38.289 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 01:58:38.289 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 01:58:38.728 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-01-29 01:58:39.206 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-01-29 01:58:39.290 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 01:58:39.290 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 01:58:39.291 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 01:58:39.291 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 01:58:39.681 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-01-29 01:58:40.149 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-01-29 01:58:40.291 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 01:58:40.292 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 01:58:40.292 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 01:58:40.292 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 01:58:40.623 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-01-29 01:58:41.101 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-01-29 01:58:41.293 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 01:58:41.293 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 01:58:41.293 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 01:58:41.293 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 01:58:41.579 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-01-29 01:58:42.057 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-01-29 01:58:42.293 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 01:58:42.294 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 01:58:42.294 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 01:58:42.294 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 01:58:42.538 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-01-29 01:58:43.015 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-01-29 01:58:43.483 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-01-29 01:58:43.831 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 01:58:43.831 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 01:58:43.831 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 01:58:43.831 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 01:58:43.832 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 01:58:43.832 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 01:58:43.832 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 01:58:43.832 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 01:58:43.832 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.28.20:5700) Recv POWEROFF cmd
2026-01-29 01:58:43.832 [INFO] ctrl_if_trx.py:117 (BTS@172.18.28.20:5700) Stopping transceiver...
2026-01-29 01:58:43.832 [INFO] transceiver.py:246 Stopping clock generator
2026-01-29 01:58:43.833 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=1404 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 01:58:43.833 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=1404 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 01:58:43.833 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=1404 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 01:58:43.833 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=1404 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 01:58:43.833 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=1404 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 01:58:43.833 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=1404 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 01:58:43.833 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=1404 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 01:58:43.833 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=1404 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 01:58:48.835 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.28.20:5700) Recv POWEROFF cmd
2026-01-29 01:58:48.835 [INFO] ctrl_if_trx.py:117 (BTS@172.18.28.20:5700) Stopping transceiver...
2026-01-29 01:58:48.837 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 01:58:48.838 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 01:58:48.839 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 01:58:48.840 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 01:58:48.849 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 01:58:48.850 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.28.20:5700) Recv SETFORMAT cmd
2026-01-29 01:58:48.851 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.28.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 01:58:48.851 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.28.20:5700) Recv SETFORMAT cmd
2026-01-29 01:58:48.851 [INFO] ctrl_if_trx.py:201 (BTS@172.18.28.20:5700) TRXD header version 1 -> 1
2026-01-29 01:58:48.857 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.28.20:5700/1) Recv RXTUNE cmd
2026-01-29 01:58:48.858 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.28.20:5700/1) Recv TXTUNE cmd
2026-01-29 01:58:48.858 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.28.20:5700/1) Recv SETFORMAT cmd
2026-01-29 01:58:48.858 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.28.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 01:58:48.859 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 01:58:48.859 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.28.20:5700/1) Recv NOMTXPOWER cmd
2026-01-29 01:58:48.860 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.28.20:5700/1) Recv SETFORMAT cmd
2026-01-29 01:58:48.860 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.28.20:5700/1) TRXD header version 1 -> 1
2026-01-29 01:58:48.861 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.28.20:5700/2) Recv RXTUNE cmd
2026-01-29 01:58:48.862 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.28.20:5700/2) Recv TXTUNE cmd
2026-01-29 01:58:48.862 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.28.20:5700/2) Recv SETFORMAT cmd
2026-01-29 01:58:48.862 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.28.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 01:58:48.863 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 01:58:48.863 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.28.20:5700/2) Recv NOMTXPOWER cmd
2026-01-29 01:58:48.863 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.28.20:5700/2) Recv SETFORMAT cmd
2026-01-29 01:58:48.863 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.28.20:5700/2) TRXD header version 1 -> 1
2026-01-29 01:58:48.865 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.28.20:5700/3) Recv RXTUNE cmd
2026-01-29 01:58:48.865 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.28.20:5700/3) Recv TXTUNE cmd
2026-01-29 01:58:48.866 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.28.20:5700/3) Recv SETFORMAT cmd
2026-01-29 01:58:48.866 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.28.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 01:58:48.866 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 01:58:48.866 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.28.20:5700/3) Recv NOMTXPOWER cmd
2026-01-29 01:58:48.866 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.28.20:5700/3) Recv SETFORMAT cmd
2026-01-29 01:58:48.866 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.28.20:5700/3) TRXD header version 1 -> 1
2026-01-29 01:58:48.869 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.28.20:5700) Recv RXTUNE cmd
2026-01-29 01:58:48.869 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETTSC
2026-01-29 01:58:48.869 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETTSC
2026-01-29 01:58:48.869 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETTSC
2026-01-29 01:58:48.869 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.28.20:5700) Recv TXTUNE cmd
2026-01-29 01:58:48.869 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETRXGAIN
2026-01-29 01:58:48.869 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETRXGAIN
2026-01-29 01:58:48.869 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETRXGAIN
2026-01-29 01:58:48.869 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETTSC
2026-01-29 01:58:48.869 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:58:48.870 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:58:48.870 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:58:48.870 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.28.20:5700) Recv NOMTXPOWER cmd
2026-01-29 01:58:48.870 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:58:48.870 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:58:48.870 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:58:48.870 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.28.20:5700) Recv POWERON CMD
2026-01-29 01:58:48.870 [INFO] ctrl_if_trx.py:109 (BTS@172.18.28.20:5700) Starting transceiver...
2026-01-29 01:58:48.870 [INFO] transceiver.py:243 Starting clock generator
2026-01-29 01:58:48.870 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-01-29 01:58:48.870 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:58:48.870 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:58:48.870 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:58:48.870 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETRXGAIN
2026-01-29 01:58:48.870 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:58:48.870 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:58:48.871 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:58:48.871 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 01:58:48.871 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:58:48.871 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:58:48.871 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:58:48.871 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 01:58:48.871 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:58:48.871 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:58:48.871 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:58:48.871 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 01:58:48.871 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:58:48.871 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:58:48.871 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:58:48.871 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 01:58:48.871 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:58:48.871 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:58:48.871 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 01:58:48.871 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:58:48.871 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 01:58:48.871 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 01:58:48.872 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 01:58:48.875 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-01-29 01:58:49.358 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-01-29 01:58:49.398 [DEBUG] fake_trx.py:278 (BTS@172.18.28.20:5700) Recv FAKE_TOA cmd
2026-01-29 01:58:49.399 [DEBUG] fake_trx.py:297 (BTS@172.18.28.20:5700) Recv FAKE_RSSI cmd
2026-01-29 01:58:49.400 [DEBUG] fake_trx.py:322 (BTS@172.18.28.20:5700) Recv FAKE_CI cmd
2026-01-29 01:58:49.400 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:58:49.838 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-01-29 01:58:49.874 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 01:58:49.874 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 01:58:49.876 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 01:58:49.880 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 01:58:50.318 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-01-29 01:58:50.799 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-01-29 01:58:50.875 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 01:58:50.875 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 01:58:50.877 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 01:58:50.881 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 01:58:51.276 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-01-29 01:58:51.756 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-01-29 01:58:51.876 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 01:58:51.876 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 01:58:51.878 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 01:58:51.883 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 01:58:52.236 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-01-29 01:58:52.717 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-01-29 01:58:52.877 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 01:58:52.878 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 01:58:52.879 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 01:58:52.884 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 01:58:53.196 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-01-29 01:58:53.418 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:58:53.668 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-01-29 01:58:53.878 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 01:58:53.879 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 01:58:53.881 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 01:58:53.885 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 01:58:54.137 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-01-29 01:58:54.614 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-01-29 01:58:55.092 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-01-29 01:58:55.569 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-01-29 01:58:56.049 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-01-29 01:58:56.530 [DEBUG] clck_gen.py:113 IND CLOCK 1632
2026-01-29 01:58:57.009 [DEBUG] clck_gen.py:113 IND CLOCK 1734
2026-01-29 01:58:57.429 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 01:58:57.429 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 01:58:57.429 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 01:58:57.429 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 01:58:57.431 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 01:58:57.431 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 01:58:57.431 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 01:58:57.431 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.28.20:5700) Recv POWEROFF cmd
2026-01-29 01:58:57.431 [INFO] ctrl_if_trx.py:117 (BTS@172.18.28.20:5700) Stopping transceiver...
2026-01-29 01:58:57.431 [INFO] transceiver.py:246 Stopping clock generator
2026-01-29 01:58:57.431 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 01:58:57.431 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=1826 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 01:58:57.431 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=1826 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 01:58:57.431 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=1826 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 01:58:57.431 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=1826 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 01:58:57.431 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=1827 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 01:58:57.431 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=1827 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 01:58:57.431 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=1827 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 01:58:57.431 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=1827 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 01:58:57.431 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=1827 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 01:58:57.431 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=1827 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 01:58:57.431 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=1827 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 01:58:57.431 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=1827 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 01:59:02.433 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.28.20:5700) Recv POWEROFF cmd
2026-01-29 01:59:02.433 [INFO] ctrl_if_trx.py:117 (BTS@172.18.28.20:5700) Stopping transceiver...
2026-01-29 01:59:02.435 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 01:59:02.436 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 01:59:02.436 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 01:59:02.436 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 01:59:02.442 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 01:59:02.444 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.28.20:5700) Recv SETFORMAT cmd
2026-01-29 01:59:02.444 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.28.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 01:59:02.444 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.28.20:5700) Recv SETFORMAT cmd
2026-01-29 01:59:02.444 [INFO] ctrl_if_trx.py:201 (BTS@172.18.28.20:5700) TRXD header version 1 -> 1
2026-01-29 01:59:02.448 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.28.20:5700/1) Recv RXTUNE cmd
2026-01-29 01:59:02.448 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.28.20:5700/1) Recv TXTUNE cmd
2026-01-29 01:59:02.448 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.28.20:5700/1) Recv SETFORMAT cmd
2026-01-29 01:59:02.448 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.28.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 01:59:02.448 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 01:59:02.448 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.28.20:5700/1) Recv NOMTXPOWER cmd
2026-01-29 01:59:02.449 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.28.20:5700/1) Recv SETFORMAT cmd
2026-01-29 01:59:02.449 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.28.20:5700/1) TRXD header version 1 -> 1
2026-01-29 01:59:02.451 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.28.20:5700/2) Recv RXTUNE cmd
2026-01-29 01:59:02.451 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.28.20:5700/2) Recv TXTUNE cmd
2026-01-29 01:59:02.451 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.28.20:5700/2) Recv SETFORMAT cmd
2026-01-29 01:59:02.451 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.28.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 01:59:02.451 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 01:59:02.452 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.28.20:5700/2) Recv NOMTXPOWER cmd
2026-01-29 01:59:02.452 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.28.20:5700/2) Recv SETFORMAT cmd
2026-01-29 01:59:02.452 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.28.20:5700/2) TRXD header version 1 -> 1
2026-01-29 01:59:02.454 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.28.20:5700/3) Recv RXTUNE cmd
2026-01-29 01:59:02.454 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.28.20:5700/3) Recv TXTUNE cmd
2026-01-29 01:59:02.454 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.28.20:5700/3) Recv SETFORMAT cmd
2026-01-29 01:59:02.454 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.28.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 01:59:02.454 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 01:59:02.454 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.28.20:5700/3) Recv NOMTXPOWER cmd
2026-01-29 01:59:02.454 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.28.20:5700/3) Recv SETFORMAT cmd
2026-01-29 01:59:02.454 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.28.20:5700/3) TRXD header version 1 -> 1
2026-01-29 01:59:02.457 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.28.20:5700) Recv RXTUNE cmd
2026-01-29 01:59:02.457 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETTSC
2026-01-29 01:59:02.457 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETTSC
2026-01-29 01:59:02.457 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETTSC
2026-01-29 01:59:02.457 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.28.20:5700) Recv TXTUNE cmd
2026-01-29 01:59:02.457 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETRXGAIN
2026-01-29 01:59:02.457 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETRXGAIN
2026-01-29 01:59:02.457 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETRXGAIN
2026-01-29 01:59:02.457 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETTSC
2026-01-29 01:59:02.457 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:59:02.457 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:59:02.457 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:59:02.457 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.28.20:5700) Recv NOMTXPOWER cmd
2026-01-29 01:59:02.457 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:59:02.457 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:59:02.457 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:59:02.458 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.28.20:5700) Recv POWERON CMD
2026-01-29 01:59:02.458 [INFO] ctrl_if_trx.py:109 (BTS@172.18.28.20:5700) Starting transceiver...
2026-01-29 01:59:02.458 [INFO] transceiver.py:243 Starting clock generator
2026-01-29 01:59:02.458 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-01-29 01:59:02.458 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:59:02.458 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:59:02.458 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:59:02.458 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETRXGAIN
2026-01-29 01:59:02.458 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:59:02.458 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:59:02.458 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 01:59:02.458 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:59:02.458 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:59:02.458 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:59:02.458 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 01:59:02.458 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:59:02.458 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:59:02.459 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:59:02.459 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 01:59:02.459 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:59:02.459 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:59:02.459 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:59:02.459 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 01:59:02.459 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:59:02.459 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:59:02.459 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:59:02.459 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 01:59:02.459 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:59:02.459 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 01:59:02.459 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 01:59:02.459 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 01:59:02.463 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-01-29 01:59:02.946 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-01-29 01:59:02.979 [DEBUG] fake_trx.py:278 (BTS@172.18.28.20:5700) Recv FAKE_TOA cmd
2026-01-29 01:59:02.980 [DEBUG] fake_trx.py:297 (BTS@172.18.28.20:5700) Recv FAKE_RSSI cmd
2026-01-29 01:59:02.981 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:59:02.982 [DEBUG] fake_trx.py:322 (BTS@172.18.28.20:5700) Recv FAKE_CI cmd
2026-01-29 01:59:03.415 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-01-29 01:59:03.460 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 01:59:03.461 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 01:59:03.461 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 01:59:03.464 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 01:59:03.884 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-01-29 01:59:04.361 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-01-29 01:59:04.462 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 01:59:04.462 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 01:59:04.462 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 01:59:04.465 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 01:59:04.842 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-01-29 01:59:05.323 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-01-29 01:59:05.462 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 01:59:05.463 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 01:59:05.463 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 01:59:05.466 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 01:59:05.801 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-01-29 01:59:06.279 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-01-29 01:59:06.463 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 01:59:06.464 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 01:59:06.464 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 01:59:06.468 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 01:59:06.758 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-01-29 01:59:06.994 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 01:59:06.994 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 01:59:06.994 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 01:59:06.994 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 01:59:06.995 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 01:59:06.995 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 01:59:06.995 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 01:59:06.995 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 01:59:06.995 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.28.20:5700) Recv POWEROFF cmd
2026-01-29 01:59:06.995 [INFO] ctrl_if_trx.py:117 (BTS@172.18.28.20:5700) Stopping transceiver...
2026-01-29 01:59:06.995 [INFO] transceiver.py:246 Stopping clock generator
2026-01-29 01:59:06.995 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=971 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 01:59:06.995 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=971 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 01:59:06.995 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=971 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 01:59:06.995 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=971 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 01:59:06.995 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=971 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 01:59:06.995 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=971 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 01:59:06.995 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=971 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 01:59:11.998 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.28.20:5700) Recv POWEROFF cmd
2026-01-29 01:59:11.998 [INFO] ctrl_if_trx.py:117 (BTS@172.18.28.20:5700) Stopping transceiver...
2026-01-29 01:59:12.002 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 01:59:12.002 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 01:59:12.002 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 01:59:12.002 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 01:59:12.010 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 01:59:12.012 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.28.20:5700) Recv SETFORMAT cmd
2026-01-29 01:59:12.013 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.28.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 01:59:12.013 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.28.20:5700) Recv SETFORMAT cmd
2026-01-29 01:59:12.013 [INFO] ctrl_if_trx.py:201 (BTS@172.18.28.20:5700) TRXD header version 1 -> 1
2026-01-29 01:59:12.018 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.28.20:5700/1) Recv RXTUNE cmd
2026-01-29 01:59:12.018 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.28.20:5700/1) Recv TXTUNE cmd
2026-01-29 01:59:12.019 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.28.20:5700/1) Recv SETFORMAT cmd
2026-01-29 01:59:12.019 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.28.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 01:59:12.019 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 01:59:12.020 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.28.20:5700/1) Recv NOMTXPOWER cmd
2026-01-29 01:59:12.020 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.28.20:5700/1) Recv SETFORMAT cmd
2026-01-29 01:59:12.020 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.28.20:5700/1) TRXD header version 1 -> 1
2026-01-29 01:59:12.021 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.28.20:5700/2) Recv RXTUNE cmd
2026-01-29 01:59:12.022 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.28.20:5700/2) Recv TXTUNE cmd
2026-01-29 01:59:12.022 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.28.20:5700/2) Recv SETFORMAT cmd
2026-01-29 01:59:12.022 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.28.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 01:59:12.022 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 01:59:12.023 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.28.20:5700/2) Recv NOMTXPOWER cmd
2026-01-29 01:59:12.023 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.28.20:5700/2) Recv SETFORMAT cmd
2026-01-29 01:59:12.023 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.28.20:5700/2) TRXD header version 1 -> 1
2026-01-29 01:59:12.024 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.28.20:5700/3) Recv RXTUNE cmd
2026-01-29 01:59:12.025 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.28.20:5700/3) Recv TXTUNE cmd
2026-01-29 01:59:12.025 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.28.20:5700/3) Recv SETFORMAT cmd
2026-01-29 01:59:12.025 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.28.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 01:59:12.025 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 01:59:12.025 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.28.20:5700/3) Recv NOMTXPOWER cmd
2026-01-29 01:59:12.025 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.28.20:5700/3) Recv SETFORMAT cmd
2026-01-29 01:59:12.025 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.28.20:5700/3) TRXD header version 1 -> 1
2026-01-29 01:59:12.028 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.28.20:5700) Recv RXTUNE cmd
2026-01-29 01:59:12.028 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETTSC
2026-01-29 01:59:12.028 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETTSC
2026-01-29 01:59:12.028 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETTSC
2026-01-29 01:59:12.028 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.28.20:5700) Recv TXTUNE cmd
2026-01-29 01:59:12.028 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETRXGAIN
2026-01-29 01:59:12.028 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETRXGAIN
2026-01-29 01:59:12.029 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETRXGAIN
2026-01-29 01:59:12.029 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETTSC
2026-01-29 01:59:12.029 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:59:12.029 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:59:12.029 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.28.20:5700) Recv NOMTXPOWER cmd
2026-01-29 01:59:12.029 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:59:12.029 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:59:12.029 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:59:12.029 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.28.20:5700) Recv POWERON CMD
2026-01-29 01:59:12.029 [INFO] ctrl_if_trx.py:109 (BTS@172.18.28.20:5700) Starting transceiver...
2026-01-29 01:59:12.029 [INFO] transceiver.py:243 Starting clock generator
2026-01-29 01:59:12.029 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-01-29 01:59:12.029 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:59:12.029 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:59:12.029 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:59:12.030 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETRXGAIN
2026-01-29 01:59:12.030 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:59:12.030 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:59:12.030 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:59:12.030 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 01:59:12.030 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:59:12.030 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:59:12.030 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:59:12.030 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 01:59:12.030 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:59:12.030 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:59:12.030 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:59:12.030 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 01:59:12.030 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:59:12.030 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:59:12.030 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:59:12.030 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 01:59:12.031 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:59:12.031 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:59:12.031 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:59:12.031 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 01:59:12.031 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:59:12.031 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 01:59:12.031 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 01:59:12.031 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 01:59:12.034 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-01-29 01:59:12.518 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-01-29 01:59:12.558 [DEBUG] fake_trx.py:278 (BTS@172.18.28.20:5700) Recv FAKE_TOA cmd
2026-01-29 01:59:12.561 [DEBUG] fake_trx.py:297 (BTS@172.18.28.20:5700) Recv FAKE_RSSI cmd
2026-01-29 01:59:12.562 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:59:12.563 [DEBUG] fake_trx.py:322 (BTS@172.18.28.20:5700) Recv FAKE_CI cmd
2026-01-29 01:59:12.575 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 01:59:12.576 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 01:59:12.576 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 01:59:12.576 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 01:59:12.579 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 01:59:12.579 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 01:59:12.579 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 01:59:12.579 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.28.20:5700) Recv POWEROFF cmd
2026-01-29 01:59:12.579 [INFO] ctrl_if_trx.py:117 (BTS@172.18.28.20:5700) Stopping transceiver...
2026-01-29 01:59:12.579 [INFO] transceiver.py:246 Stopping clock generator
2026-01-29 01:59:12.579 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 01:59:12.579 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=116 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 01:59:12.579 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=116 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 01:59:12.579 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=116 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 01:59:12.579 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=116 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 01:59:12.579 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=116 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 01:59:12.579 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=116 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 01:59:12.579 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=116 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 01:59:12.579 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=116 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 01:59:17.582 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.28.20:5700) Recv POWEROFF cmd
2026-01-29 01:59:17.582 [INFO] ctrl_if_trx.py:117 (BTS@172.18.28.20:5700) Stopping transceiver...
2026-01-29 01:59:17.582 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 01:59:17.582 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 01:59:17.582 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 01:59:17.582 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 01:59:17.589 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 01:59:17.589 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.28.20:5700) Recv SETFORMAT cmd
2026-01-29 01:59:17.589 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.28.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 01:59:17.589 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.28.20:5700) Recv SETFORMAT cmd
2026-01-29 01:59:17.590 [INFO] ctrl_if_trx.py:201 (BTS@172.18.28.20:5700) TRXD header version 1 -> 1
2026-01-29 01:59:17.592 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.28.20:5700/1) Recv RXTUNE cmd
2026-01-29 01:59:17.592 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.28.20:5700/1) Recv TXTUNE cmd
2026-01-29 01:59:17.592 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.28.20:5700/1) Recv SETFORMAT cmd
2026-01-29 01:59:17.592 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.28.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 01:59:17.593 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 01:59:17.593 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.28.20:5700/1) Recv NOMTXPOWER cmd
2026-01-29 01:59:17.593 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.28.20:5700/1) Recv SETFORMAT cmd
2026-01-29 01:59:17.593 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.28.20:5700/1) TRXD header version 1 -> 1
2026-01-29 01:59:17.596 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.28.20:5700/2) Recv RXTUNE cmd
2026-01-29 01:59:17.596 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.28.20:5700/2) Recv TXTUNE cmd
2026-01-29 01:59:17.597 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.28.20:5700/2) Recv SETFORMAT cmd
2026-01-29 01:59:17.597 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.28.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 01:59:17.597 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 01:59:17.597 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.28.20:5700/2) Recv NOMTXPOWER cmd
2026-01-29 01:59:17.598 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.28.20:5700/2) Recv SETFORMAT cmd
2026-01-29 01:59:17.598 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.28.20:5700/2) TRXD header version 1 -> 1
2026-01-29 01:59:17.599 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.28.20:5700/3) Recv RXTUNE cmd
2026-01-29 01:59:17.599 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.28.20:5700/3) Recv TXTUNE cmd
2026-01-29 01:59:17.600 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.28.20:5700/3) Recv SETFORMAT cmd
2026-01-29 01:59:17.600 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.28.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 01:59:17.600 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 01:59:17.600 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.28.20:5700/3) Recv NOMTXPOWER cmd
2026-01-29 01:59:17.600 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.28.20:5700/3) Recv SETFORMAT cmd
2026-01-29 01:59:17.600 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.28.20:5700/3) TRXD header version 1 -> 1
2026-01-29 01:59:17.602 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.28.20:5700) Recv RXTUNE cmd
2026-01-29 01:59:17.603 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETTSC
2026-01-29 01:59:17.603 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.28.20:5700) Recv TXTUNE cmd
2026-01-29 01:59:17.603 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETTSC
2026-01-29 01:59:17.603 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETTSC
2026-01-29 01:59:17.603 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETRXGAIN
2026-01-29 01:59:17.603 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETTSC
2026-01-29 01:59:17.603 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETRXGAIN
2026-01-29 01:59:17.603 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETRXGAIN
2026-01-29 01:59:17.603 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.28.20:5700) Recv NOMTXPOWER cmd
2026-01-29 01:59:17.603 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:59:17.603 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:59:17.603 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:59:17.603 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.28.20:5700) Recv POWERON CMD
2026-01-29 01:59:17.603 [INFO] ctrl_if_trx.py:109 (BTS@172.18.28.20:5700) Starting transceiver...
2026-01-29 01:59:17.603 [INFO] transceiver.py:243 Starting clock generator
2026-01-29 01:59:17.603 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-01-29 01:59:17.604 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:59:17.604 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:59:17.604 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:59:17.604 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETRXGAIN
2026-01-29 01:59:17.604 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:59:17.604 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:59:17.604 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:59:17.604 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 01:59:17.604 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:59:17.604 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:59:17.604 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:59:17.604 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 01:59:17.605 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:59:17.605 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:59:17.605 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:59:17.605 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 01:59:17.605 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:59:17.605 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:59:17.605 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:59:17.605 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 01:59:17.605 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:59:17.605 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:59:17.605 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:59:17.605 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 01:59:17.605 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:59:17.605 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:59:17.605 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:59:17.605 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 01:59:17.605 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 01:59:17.606 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 01:59:17.608 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-01-29 01:59:18.093 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-01-29 01:59:18.134 [DEBUG] fake_trx.py:278 (BTS@172.18.28.20:5700) Recv FAKE_TOA cmd
2026-01-29 01:59:18.135 [DEBUG] fake_trx.py:297 (BTS@172.18.28.20:5700) Recv FAKE_RSSI cmd
2026-01-29 01:59:18.136 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:59:18.136 [DEBUG] fake_trx.py:322 (BTS@172.18.28.20:5700) Recv FAKE_CI cmd
2026-01-29 01:59:18.142 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:59:18.149 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 01:59:18.149 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 01:59:18.149 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 01:59:18.149 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 01:59:18.152 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 01:59:18.152 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 01:59:18.152 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 01:59:18.152 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.28.20:5700) Recv POWEROFF cmd
2026-01-29 01:59:18.152 [INFO] ctrl_if_trx.py:117 (BTS@172.18.28.20:5700) Stopping transceiver...
2026-01-29 01:59:18.152 [INFO] transceiver.py:246 Stopping clock generator
2026-01-29 01:59:18.153 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 01:59:18.153 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=116 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 01:59:18.153 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=116 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 01:59:23.153 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.28.20:5700) Recv POWEROFF cmd
2026-01-29 01:59:23.153 [INFO] ctrl_if_trx.py:117 (BTS@172.18.28.20:5700) Stopping transceiver...
2026-01-29 01:59:23.154 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 01:59:23.156 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 01:59:23.157 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 01:59:23.157 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 01:59:23.165 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 01:59:23.167 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.28.20:5700) Recv SETFORMAT cmd
2026-01-29 01:59:23.167 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.28.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 01:59:23.167 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.28.20:5700) Recv SETFORMAT cmd
2026-01-29 01:59:23.167 [INFO] ctrl_if_trx.py:201 (BTS@172.18.28.20:5700) TRXD header version 1 -> 1
2026-01-29 01:59:23.173 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.28.20:5700/1) Recv RXTUNE cmd
2026-01-29 01:59:23.173 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.28.20:5700/1) Recv TXTUNE cmd
2026-01-29 01:59:23.174 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.28.20:5700/1) Recv SETFORMAT cmd
2026-01-29 01:59:23.174 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.28.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 01:59:23.174 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 01:59:23.175 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.28.20:5700/1) Recv NOMTXPOWER cmd
2026-01-29 01:59:23.175 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.28.20:5700/1) Recv SETFORMAT cmd
2026-01-29 01:59:23.175 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.28.20:5700/1) TRXD header version 1 -> 1
2026-01-29 01:59:23.177 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.28.20:5700/2) Recv RXTUNE cmd
2026-01-29 01:59:23.177 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.28.20:5700/2) Recv TXTUNE cmd
2026-01-29 01:59:23.177 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.28.20:5700/2) Recv SETFORMAT cmd
2026-01-29 01:59:23.177 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.28.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 01:59:23.177 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 01:59:23.177 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.28.20:5700/2) Recv NOMTXPOWER cmd
2026-01-29 01:59:23.178 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.28.20:5700/2) Recv SETFORMAT cmd
2026-01-29 01:59:23.178 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.28.20:5700/2) TRXD header version 1 -> 1
2026-01-29 01:59:23.180 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.28.20:5700/3) Recv RXTUNE cmd
2026-01-29 01:59:23.180 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.28.20:5700/3) Recv TXTUNE cmd
2026-01-29 01:59:23.180 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.28.20:5700/3) Recv SETFORMAT cmd
2026-01-29 01:59:23.180 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.28.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 01:59:23.180 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 01:59:23.180 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.28.20:5700/3) Recv NOMTXPOWER cmd
2026-01-29 01:59:23.180 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.28.20:5700/3) Recv SETFORMAT cmd
2026-01-29 01:59:23.180 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.28.20:5700/3) TRXD header version 1 -> 1
2026-01-29 01:59:23.183 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.28.20:5700) Recv RXTUNE cmd
2026-01-29 01:59:23.183 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETTSC
2026-01-29 01:59:23.183 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETTSC
2026-01-29 01:59:23.183 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETTSC
2026-01-29 01:59:23.183 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.28.20:5700) Recv TXTUNE cmd
2026-01-29 01:59:23.183 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETRXGAIN
2026-01-29 01:59:23.183 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETRXGAIN
2026-01-29 01:59:23.183 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETRXGAIN
2026-01-29 01:59:23.183 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETTSC
2026-01-29 01:59:23.183 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:59:23.183 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:59:23.184 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:59:23.184 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.28.20:5700) Recv NOMTXPOWER cmd
2026-01-29 01:59:23.184 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:59:23.184 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:59:23.184 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:59:23.184 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.28.20:5700) Recv POWERON CMD
2026-01-29 01:59:23.184 [INFO] ctrl_if_trx.py:109 (BTS@172.18.28.20:5700) Starting transceiver...
2026-01-29 01:59:23.184 [INFO] transceiver.py:243 Starting clock generator
2026-01-29 01:59:23.184 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-01-29 01:59:23.184 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:59:23.184 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:59:23.184 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:59:23.184 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETRXGAIN
2026-01-29 01:59:23.184 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:59:23.184 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:59:23.184 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:59:23.184 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 01:59:23.184 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:59:23.184 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:59:23.185 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 01:59:23.185 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:59:23.185 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:59:23.185 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:59:23.185 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 01:59:23.185 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:59:23.185 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:59:23.185 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 01:59:23.185 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:59:23.185 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:59:23.185 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:59:23.185 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 01:59:23.185 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:59:23.185 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 01:59:23.185 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:59:23.185 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 01:59:23.185 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 01:59:23.189 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-01-29 01:59:23.670 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-01-29 01:59:23.711 [DEBUG] fake_trx.py:278 (BTS@172.18.28.20:5700) Recv FAKE_TOA cmd
2026-01-29 01:59:23.714 [DEBUG] fake_trx.py:297 (BTS@172.18.28.20:5700) Recv FAKE_RSSI cmd
2026-01-29 01:59:23.715 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:59:23.716 [DEBUG] fake_trx.py:322 (BTS@172.18.28.20:5700) Recv FAKE_CI cmd
2026-01-29 01:59:23.730 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 01:59:23.730 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 01:59:23.730 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 01:59:23.730 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 01:59:23.734 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 01:59:23.734 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 01:59:23.734 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 01:59:23.734 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 01:59:23.735 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.28.20:5700) Recv POWEROFF cmd
2026-01-29 01:59:23.735 [INFO] ctrl_if_trx.py:117 (BTS@172.18.28.20:5700) Stopping transceiver...
2026-01-29 01:59:23.735 [INFO] transceiver.py:246 Stopping clock generator
2026-01-29 01:59:23.735 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=117 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 01:59:23.735 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=117 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 01:59:23.735 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=117 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 01:59:23.735 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=117 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 01:59:23.736 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=117 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 01:59:23.736 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=117 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 01:59:28.733 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.28.20:5700) Recv POWEROFF cmd
2026-01-29 01:59:28.733 [INFO] ctrl_if_trx.py:117 (BTS@172.18.28.20:5700) Stopping transceiver...
2026-01-29 01:59:28.735 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 01:59:28.736 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 01:59:28.736 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 01:59:28.737 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 01:59:28.744 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 01:59:28.745 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.28.20:5700) Recv SETFORMAT cmd
2026-01-29 01:59:28.745 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.28.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 01:59:28.745 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.28.20:5700) Recv SETFORMAT cmd
2026-01-29 01:59:28.745 [INFO] ctrl_if_trx.py:201 (BTS@172.18.28.20:5700) TRXD header version 1 -> 1
2026-01-29 01:59:28.747 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.28.20:5700/1) Recv RXTUNE cmd
2026-01-29 01:59:28.748 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.28.20:5700/1) Recv TXTUNE cmd
2026-01-29 01:59:28.748 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.28.20:5700/1) Recv SETFORMAT cmd
2026-01-29 01:59:28.748 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.28.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 01:59:28.748 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 01:59:28.749 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.28.20:5700/1) Recv NOMTXPOWER cmd
2026-01-29 01:59:28.749 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.28.20:5700/1) Recv SETFORMAT cmd
2026-01-29 01:59:28.749 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.28.20:5700/1) TRXD header version 1 -> 1
2026-01-29 01:59:28.750 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.28.20:5700/2) Recv RXTUNE cmd
2026-01-29 01:59:28.750 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.28.20:5700/2) Recv TXTUNE cmd
2026-01-29 01:59:28.750 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.28.20:5700/2) Recv SETFORMAT cmd
2026-01-29 01:59:28.750 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.28.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 01:59:28.750 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 01:59:28.750 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.28.20:5700/2) Recv NOMTXPOWER cmd
2026-01-29 01:59:28.750 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.28.20:5700/2) Recv SETFORMAT cmd
2026-01-29 01:59:28.751 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.28.20:5700/2) TRXD header version 1 -> 1
2026-01-29 01:59:28.752 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.28.20:5700/3) Recv RXTUNE cmd
2026-01-29 01:59:28.752 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.28.20:5700/3) Recv TXTUNE cmd
2026-01-29 01:59:28.752 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.28.20:5700/3) Recv SETFORMAT cmd
2026-01-29 01:59:28.752 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.28.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 01:59:28.752 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 01:59:28.752 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.28.20:5700/3) Recv NOMTXPOWER cmd
2026-01-29 01:59:28.752 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.28.20:5700/3) Recv SETFORMAT cmd
2026-01-29 01:59:28.753 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.28.20:5700/3) TRXD header version 1 -> 1
2026-01-29 01:59:28.755 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.28.20:5700) Recv RXTUNE cmd
2026-01-29 01:59:28.755 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETTSC
2026-01-29 01:59:28.755 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETTSC
2026-01-29 01:59:28.755 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETTSC
2026-01-29 01:59:28.755 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.28.20:5700) Recv TXTUNE cmd
2026-01-29 01:59:28.755 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETRXGAIN
2026-01-29 01:59:28.755 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETRXGAIN
2026-01-29 01:59:28.755 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETRXGAIN
2026-01-29 01:59:28.755 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETTSC
2026-01-29 01:59:28.755 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:59:28.755 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:59:28.755 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:59:28.755 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.28.20:5700) Recv NOMTXPOWER cmd
2026-01-29 01:59:28.755 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:59:28.755 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:59:28.755 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:59:28.755 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.28.20:5700) Recv POWERON CMD
2026-01-29 01:59:28.755 [INFO] ctrl_if_trx.py:109 (BTS@172.18.28.20:5700) Starting transceiver...
2026-01-29 01:59:28.755 [INFO] transceiver.py:243 Starting clock generator
2026-01-29 01:59:28.756 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-01-29 01:59:28.756 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:59:28.756 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:59:28.756 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:59:28.756 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETRXGAIN
2026-01-29 01:59:28.756 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:59:28.756 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:59:28.756 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 01:59:28.756 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:59:28.756 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:59:28.756 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:59:28.756 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 01:59:28.756 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:59:28.756 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:59:28.756 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:59:28.756 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 01:59:28.756 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:59:28.756 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:59:28.756 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:59:28.756 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 01:59:28.756 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:59:28.756 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:59:28.756 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:59:28.756 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 01:59:28.756 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:59:28.756 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 01:59:28.757 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 01:59:28.757 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 01:59:28.760 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-01-29 01:59:29.244 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-01-29 01:59:29.280 [DEBUG] fake_trx.py:278 (BTS@172.18.28.20:5700) Recv FAKE_TOA cmd
2026-01-29 01:59:29.282 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:59:29.283 [DEBUG] fake_trx.py:297 (BTS@172.18.28.20:5700) Recv FAKE_RSSI cmd
2026-01-29 01:59:29.285 [DEBUG] fake_trx.py:322 (BTS@172.18.28.20:5700) Recv FAKE_CI cmd
2026-01-29 01:59:29.295 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 01:59:29.295 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 01:59:29.296 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 01:59:29.296 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 01:59:29.297 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 01:59:29.297 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 01:59:29.298 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.28.22:6700) Recv POWERON CMD
2026-01-29 01:59:29.298 [INFO] ctrl_if_trx.py:109 (MS@172.18.28.22:6700) Starting transceiver...
2026-01-29 01:59:29.718 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-01-29 01:59:29.757 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 01:59:29.758 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 01:59:29.760 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 01:59:29.761 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 01:59:30.192 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-01-29 01:59:30.670 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-01-29 01:59:30.758 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 01:59:30.759 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 01:59:30.761 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 01:59:30.762 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 01:59:31.147 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-01-29 01:59:31.624 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-01-29 01:59:31.759 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 01:59:31.760 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 01:59:31.762 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 01:59:31.763 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 01:59:32.102 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-01-29 01:59:32.345 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 01:59:32.345 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 01:59:32.345 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 01:59:32.345 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 01:59:32.391 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 01:59:32.391 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 01:59:32.392 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:59:32.397 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 01:59:32.397 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 01:59:32.398 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 01:59:32.398 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 01:59:32.400 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 01:59:32.400 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 01:59:32.400 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 01:59:32.400 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.28.20:5700) Recv POWEROFF cmd
2026-01-29 01:59:32.400 [INFO] ctrl_if_trx.py:117 (BTS@172.18.28.20:5700) Stopping transceiver...
2026-01-29 01:59:32.401 [INFO] transceiver.py:246 Stopping clock generator
2026-01-29 01:59:32.401 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 01:59:32.401 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=780 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 01:59:32.401 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=780 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 01:59:32.401 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=780 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 01:59:32.401 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=780 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 01:59:32.401 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=780 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 01:59:32.401 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=780 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 01:59:32.401 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=780 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 01:59:37.402 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.28.20:5700) Recv POWEROFF cmd
2026-01-29 01:59:37.402 [INFO] ctrl_if_trx.py:117 (BTS@172.18.28.20:5700) Stopping transceiver...
2026-01-29 01:59:37.404 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 01:59:37.404 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 01:59:37.404 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 01:59:37.405 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 01:59:37.408 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 01:59:37.409 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.28.20:5700) Recv SETFORMAT cmd
2026-01-29 01:59:37.409 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.28.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 01:59:37.409 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.28.20:5700) Recv SETFORMAT cmd
2026-01-29 01:59:37.409 [INFO] ctrl_if_trx.py:201 (BTS@172.18.28.20:5700) TRXD header version 1 -> 1
2026-01-29 01:59:37.411 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.28.20:5700/1) Recv RXTUNE cmd
2026-01-29 01:59:37.411 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.28.20:5700/1) Recv TXTUNE cmd
2026-01-29 01:59:37.411 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.28.20:5700/1) Recv SETFORMAT cmd
2026-01-29 01:59:37.411 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.28.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 01:59:37.411 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 01:59:37.412 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.28.20:5700/1) Recv NOMTXPOWER cmd
2026-01-29 01:59:37.412 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.28.20:5700/1) Recv SETFORMAT cmd
2026-01-29 01:59:37.412 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.28.20:5700/1) TRXD header version 1 -> 1
2026-01-29 01:59:37.413 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.28.20:5700/2) Recv RXTUNE cmd
2026-01-29 01:59:37.413 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.28.20:5700/2) Recv TXTUNE cmd
2026-01-29 01:59:37.413 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.28.20:5700/2) Recv SETFORMAT cmd
2026-01-29 01:59:37.413 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.28.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 01:59:37.413 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 01:59:37.413 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.28.20:5700/2) Recv NOMTXPOWER cmd
2026-01-29 01:59:37.413 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.28.20:5700/2) Recv SETFORMAT cmd
2026-01-29 01:59:37.413 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.28.20:5700/2) TRXD header version 1 -> 1
2026-01-29 01:59:37.414 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.28.20:5700/3) Recv RXTUNE cmd
2026-01-29 01:59:37.414 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.28.20:5700/3) Recv TXTUNE cmd
2026-01-29 01:59:37.414 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.28.20:5700/3) Recv SETFORMAT cmd
2026-01-29 01:59:37.415 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.28.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 01:59:37.415 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 01:59:37.415 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.28.20:5700/3) Recv NOMTXPOWER cmd
2026-01-29 01:59:37.415 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.28.20:5700/3) Recv SETFORMAT cmd
2026-01-29 01:59:37.415 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.28.20:5700/3) TRXD header version 1 -> 1
2026-01-29 01:59:37.416 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.28.20:5700) Recv RXTUNE cmd
2026-01-29 01:59:37.416 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETTSC
2026-01-29 01:59:37.416 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETTSC
2026-01-29 01:59:37.416 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETTSC
2026-01-29 01:59:37.417 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.28.20:5700) Recv TXTUNE cmd
2026-01-29 01:59:37.417 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETRXGAIN
2026-01-29 01:59:37.417 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETRXGAIN
2026-01-29 01:59:37.417 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETRXGAIN
2026-01-29 01:59:37.417 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETTSC
2026-01-29 01:59:37.417 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:59:37.417 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:59:37.417 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:59:37.417 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.28.20:5700) Recv NOMTXPOWER cmd
2026-01-29 01:59:37.417 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:59:37.417 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:59:37.417 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:59:37.417 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.28.20:5700) Recv POWERON CMD
2026-01-29 01:59:37.417 [INFO] ctrl_if_trx.py:109 (BTS@172.18.28.20:5700) Starting transceiver...
2026-01-29 01:59:37.417 [INFO] transceiver.py:243 Starting clock generator
2026-01-29 01:59:37.417 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-01-29 01:59:37.417 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:59:37.417 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:59:37.417 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:59:37.417 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETRXGAIN
2026-01-29 01:59:37.417 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:59:37.417 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:59:37.417 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:59:37.417 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 01:59:37.417 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:59:37.417 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:59:37.417 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:59:37.417 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 01:59:37.417 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:59:37.417 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:59:37.418 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:59:37.418 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 01:59:37.418 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:59:37.418 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:59:37.418 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:59:37.418 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 01:59:37.418 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:59:37.418 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:59:37.418 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:59:37.418 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 01:59:37.418 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 01:59:37.418 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 01:59:37.418 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 01:59:37.422 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-01-29 01:59:37.905 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-01-29 01:59:37.941 [DEBUG] fake_trx.py:278 (BTS@172.18.28.20:5700) Recv FAKE_TOA cmd
2026-01-29 01:59:37.943 [DEBUG] fake_trx.py:297 (BTS@172.18.28.20:5700) Recv FAKE_RSSI cmd
2026-01-29 01:59:37.945 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:59:37.945 [DEBUG] fake_trx.py:322 (BTS@172.18.28.20:5700) Recv FAKE_CI cmd
2026-01-29 01:59:37.953 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 01:59:37.953 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 01:59:37.953 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 01:59:37.955 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 01:59:37.955 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 01:59:37.955 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 01:59:37.955 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.28.22:6700) Recv POWERON CMD
2026-01-29 01:59:37.955 [INFO] ctrl_if_trx.py:109 (MS@172.18.28.22:6700) Starting transceiver...
2026-01-29 01:59:38.382 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-01-29 01:59:38.419 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 01:59:38.419 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 01:59:38.420 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 01:59:38.421 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 01:59:38.859 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-01-29 01:59:39.337 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-01-29 01:59:39.420 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 01:59:39.421 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 01:59:39.421 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 01:59:39.422 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 01:59:39.815 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-01-29 01:59:40.293 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-01-29 01:59:40.421 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 01:59:40.421 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 01:59:40.422 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 01:59:40.422 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 01:59:40.770 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-01-29 01:59:41.013 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 01:59:41.013 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 01:59:41.013 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 01:59:41.014 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 01:59:41.247 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-01-29 01:59:41.422 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 01:59:41.422 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 01:59:41.422 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 01:59:41.423 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 01:59:41.725 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-01-29 01:59:41.737 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 01:59:41.737 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 01:59:41.738 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:59:41.745 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 01:59:41.745 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 01:59:41.745 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 01:59:41.745 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 01:59:41.746 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 01:59:41.746 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 01:59:41.746 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 01:59:41.746 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 01:59:41.746 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.28.20:5700) Recv POWEROFF cmd
2026-01-29 01:59:41.746 [INFO] ctrl_if_trx.py:117 (BTS@172.18.28.20:5700) Stopping transceiver...
2026-01-29 01:59:41.746 [INFO] transceiver.py:246 Stopping clock generator
2026-01-29 01:59:46.747 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.28.20:5700) Recv POWEROFF cmd
2026-01-29 01:59:46.747 [INFO] ctrl_if_trx.py:117 (BTS@172.18.28.20:5700) Stopping transceiver...
2026-01-29 01:59:46.749 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 01:59:46.750 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 01:59:46.751 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 01:59:46.752 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 01:59:46.756 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 01:59:46.758 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.28.20:5700) Recv SETFORMAT cmd
2026-01-29 01:59:46.758 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.28.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 01:59:46.758 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.28.20:5700) Recv SETFORMAT cmd
2026-01-29 01:59:46.758 [INFO] ctrl_if_trx.py:201 (BTS@172.18.28.20:5700) TRXD header version 1 -> 1
2026-01-29 01:59:46.761 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.28.20:5700/1) Recv RXTUNE cmd
2026-01-29 01:59:46.762 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.28.20:5700/1) Recv TXTUNE cmd
2026-01-29 01:59:46.762 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.28.20:5700/1) Recv SETFORMAT cmd
2026-01-29 01:59:46.762 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.28.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 01:59:46.763 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 01:59:46.763 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.28.20:5700/1) Recv NOMTXPOWER cmd
2026-01-29 01:59:46.763 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.28.20:5700/1) Recv SETFORMAT cmd
2026-01-29 01:59:46.763 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.28.20:5700/1) TRXD header version 1 -> 1
2026-01-29 01:59:46.764 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.28.20:5700/2) Recv RXTUNE cmd
2026-01-29 01:59:46.764 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.28.20:5700/2) Recv TXTUNE cmd
2026-01-29 01:59:46.764 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.28.20:5700/2) Recv SETFORMAT cmd
2026-01-29 01:59:46.764 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.28.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 01:59:46.764 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 01:59:46.764 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.28.20:5700/2) Recv NOMTXPOWER cmd
2026-01-29 01:59:46.765 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.28.20:5700/2) Recv SETFORMAT cmd
2026-01-29 01:59:46.765 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.28.20:5700/2) TRXD header version 1 -> 1
2026-01-29 01:59:46.767 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.28.20:5700/3) Recv RXTUNE cmd
2026-01-29 01:59:46.767 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.28.20:5700/3) Recv TXTUNE cmd
2026-01-29 01:59:46.767 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.28.20:5700/3) Recv SETFORMAT cmd
2026-01-29 01:59:46.767 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.28.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 01:59:46.767 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 01:59:46.767 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.28.20:5700/3) Recv NOMTXPOWER cmd
2026-01-29 01:59:46.767 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.28.20:5700/3) Recv SETFORMAT cmd
2026-01-29 01:59:46.767 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.28.20:5700/3) TRXD header version 1 -> 1
2026-01-29 01:59:46.769 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.28.20:5700) Recv RXTUNE cmd
2026-01-29 01:59:46.769 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETTSC
2026-01-29 01:59:46.769 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETTSC
2026-01-29 01:59:46.770 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETTSC
2026-01-29 01:59:46.770 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.28.20:5700) Recv TXTUNE cmd
2026-01-29 01:59:46.770 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETRXGAIN
2026-01-29 01:59:46.770 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETRXGAIN
2026-01-29 01:59:46.770 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETRXGAIN
2026-01-29 01:59:46.770 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETTSC
2026-01-29 01:59:46.770 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:59:46.770 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:59:46.770 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.28.20:5700) Recv NOMTXPOWER cmd
2026-01-29 01:59:46.770 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:59:46.770 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:59:46.770 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:59:46.770 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.28.20:5700) Recv POWERON CMD
2026-01-29 01:59:46.770 [INFO] ctrl_if_trx.py:109 (BTS@172.18.28.20:5700) Starting transceiver...
2026-01-29 01:59:46.770 [INFO] transceiver.py:243 Starting clock generator
2026-01-29 01:59:46.770 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-01-29 01:59:46.770 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:59:46.771 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:59:46.771 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:59:46.771 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETRXGAIN
2026-01-29 01:59:46.771 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:59:46.771 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:59:46.771 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 01:59:46.771 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:59:46.771 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:59:46.771 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:59:46.771 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 01:59:46.771 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:59:46.771 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:59:46.771 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:59:46.771 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 01:59:46.771 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:59:46.771 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:59:46.771 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:59:46.771 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 01:59:46.771 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:59:46.771 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:59:46.771 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:59:46.771 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 01:59:46.771 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:59:46.771 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 01:59:46.771 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:59:46.771 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 01:59:46.771 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 01:59:46.775 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-01-29 01:59:47.259 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-01-29 01:59:47.295 [DEBUG] fake_trx.py:278 (BTS@172.18.28.20:5700) Recv FAKE_TOA cmd
2026-01-29 01:59:47.297 [DEBUG] fake_trx.py:297 (BTS@172.18.28.20:5700) Recv FAKE_RSSI cmd
2026-01-29 01:59:47.298 [DEBUG] fake_trx.py:322 (BTS@172.18.28.20:5700) Recv FAKE_CI cmd
2026-01-29 01:59:47.298 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:59:47.303 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 01:59:47.303 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 01:59:47.303 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 01:59:47.303 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 01:59:47.304 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 01:59:47.304 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 01:59:47.304 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.28.22:6700) Recv POWERON CMD
2026-01-29 01:59:47.304 [INFO] ctrl_if_trx.py:109 (MS@172.18.28.22:6700) Starting transceiver...
2026-01-29 01:59:47.736 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-01-29 01:59:47.773 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 01:59:47.774 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 01:59:47.774 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 01:59:47.777 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 01:59:48.214 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-01-29 01:59:48.692 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-01-29 01:59:48.774 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 01:59:48.775 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 01:59:48.775 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 01:59:48.778 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 01:59:49.170 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-01-29 01:59:49.647 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-01-29 01:59:49.776 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 01:59:49.776 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 01:59:49.776 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 01:59:49.779 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 01:59:50.125 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-01-29 01:59:50.367 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 01:59:50.367 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 01:59:50.367 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 01:59:50.368 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 01:59:50.602 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-01-29 01:59:50.777 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 01:59:50.777 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 01:59:50.778 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 01:59:50.781 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 01:59:51.080 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-01-29 01:59:51.557 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-01-29 01:59:51.778 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 01:59:51.779 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 01:59:51.779 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 01:59:51.782 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 01:59:52.035 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-01-29 01:59:52.512 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-01-29 01:59:52.990 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-01-29 01:59:53.466 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-01-29 01:59:53.944 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-01-29 01:59:54.421 [DEBUG] clck_gen.py:113 IND CLOCK 1632
2026-01-29 01:59:54.898 [DEBUG] clck_gen.py:113 IND CLOCK 1734
2026-01-29 01:59:55.370 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 01:59:55.370 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 01:59:55.371 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:59:55.375 [DEBUG] clck_gen.py:113 IND CLOCK 1836
2026-01-29 01:59:55.387 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 01:59:55.387 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 01:59:55.387 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 01:59:55.388 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 01:59:55.390 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 01:59:55.390 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 01:59:55.390 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 01:59:55.390 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 01:59:55.390 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.28.20:5700) Recv POWEROFF cmd
2026-01-29 01:59:55.390 [INFO] ctrl_if_trx.py:117 (BTS@172.18.28.20:5700) Stopping transceiver...
2026-01-29 01:59:55.390 [INFO] transceiver.py:246 Stopping clock generator
2026-01-29 01:59:55.391 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=1841 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 01:59:55.391 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=1841 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 01:59:55.391 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=1841 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 01:59:55.391 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=1841 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 01:59:55.391 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=1841 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 01:59:55.391 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=1841 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 01:59:55.391 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=1841 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:00:00.392 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.28.20:5700) Recv POWEROFF cmd
2026-01-29 02:00:00.392 [INFO] ctrl_if_trx.py:117 (BTS@172.18.28.20:5700) Stopping transceiver...
2026-01-29 02:00:00.394 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:00:00.395 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:00:00.395 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:00:00.395 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 02:00:00.398 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 02:00:00.398 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.28.20:5700) Recv SETFORMAT cmd
2026-01-29 02:00:00.398 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.28.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:00:00.398 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.28.20:5700) Recv SETFORMAT cmd
2026-01-29 02:00:00.399 [INFO] ctrl_if_trx.py:201 (BTS@172.18.28.20:5700) TRXD header version 1 -> 1
2026-01-29 02:00:00.400 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.28.20:5700/1) Recv RXTUNE cmd
2026-01-29 02:00:00.400 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.28.20:5700/1) Recv TXTUNE cmd
2026-01-29 02:00:00.401 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.28.20:5700/1) Recv SETFORMAT cmd
2026-01-29 02:00:00.401 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.28.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:00:00.401 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:00:00.401 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.28.20:5700/1) Recv NOMTXPOWER cmd
2026-01-29 02:00:00.401 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.28.20:5700/1) Recv SETFORMAT cmd
2026-01-29 02:00:00.401 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.28.20:5700/1) TRXD header version 1 -> 1
2026-01-29 02:00:00.402 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.28.20:5700/2) Recv RXTUNE cmd
2026-01-29 02:00:00.403 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.28.20:5700/2) Recv TXTUNE cmd
2026-01-29 02:00:00.403 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.28.20:5700/2) Recv SETFORMAT cmd
2026-01-29 02:00:00.403 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.28.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:00:00.403 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:00:00.403 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.28.20:5700/2) Recv NOMTXPOWER cmd
2026-01-29 02:00:00.403 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.28.20:5700/2) Recv SETFORMAT cmd
2026-01-29 02:00:00.403 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.28.20:5700/2) TRXD header version 1 -> 1
2026-01-29 02:00:00.404 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.28.20:5700/3) Recv RXTUNE cmd
2026-01-29 02:00:00.404 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.28.20:5700/3) Recv TXTUNE cmd
2026-01-29 02:00:00.404 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.28.20:5700/3) Recv SETFORMAT cmd
2026-01-29 02:00:00.404 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.28.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:00:00.404 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:00:00.404 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.28.20:5700/3) Recv NOMTXPOWER cmd
2026-01-29 02:00:00.404 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.28.20:5700/3) Recv SETFORMAT cmd
2026-01-29 02:00:00.404 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.28.20:5700/3) TRXD header version 1 -> 1
2026-01-29 02:00:00.406 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.28.20:5700) Recv RXTUNE cmd
2026-01-29 02:00:00.406 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETTSC
2026-01-29 02:00:00.406 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETTSC
2026-01-29 02:00:00.406 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETTSC
2026-01-29 02:00:00.406 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.28.20:5700) Recv TXTUNE cmd
2026-01-29 02:00:00.406 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETRXGAIN
2026-01-29 02:00:00.406 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETRXGAIN
2026-01-29 02:00:00.407 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETRXGAIN
2026-01-29 02:00:00.407 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETTSC
2026-01-29 02:00:00.407 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:00:00.407 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:00:00.407 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:00:00.407 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.28.20:5700) Recv NOMTXPOWER cmd
2026-01-29 02:00:00.407 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:00:00.407 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:00:00.407 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:00:00.407 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.28.20:5700) Recv POWERON CMD
2026-01-29 02:00:00.407 [INFO] ctrl_if_trx.py:109 (BTS@172.18.28.20:5700) Starting transceiver...
2026-01-29 02:00:00.407 [INFO] transceiver.py:243 Starting clock generator
2026-01-29 02:00:00.407 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-01-29 02:00:00.407 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:00:00.407 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:00:00.407 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:00:00.407 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETRXGAIN
2026-01-29 02:00:00.407 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:00:00.407 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:00:00.407 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:00:00.407 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:00:00.407 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:00:00.407 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:00:00.407 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:00:00.407 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:00:00.407 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:00:00.407 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:00:00.407 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:00:00.407 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:00:00.408 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:00:00.408 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:00:00.408 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:00:00.408 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:00:00.408 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:00:00.408 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:00:00.408 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:00:00.408 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:00:00.408 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:00:00.408 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:00:00.408 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:00:00.412 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-01-29 02:00:00.896 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-01-29 02:00:00.932 [DEBUG] fake_trx.py:278 (BTS@172.18.28.20:5700) Recv FAKE_TOA cmd
2026-01-29 02:00:00.934 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:00:00.934 [DEBUG] fake_trx.py:297 (BTS@172.18.28.20:5700) Recv FAKE_RSSI cmd
2026-01-29 02:00:00.935 [DEBUG] fake_trx.py:322 (BTS@172.18.28.20:5700) Recv FAKE_CI cmd
2026-01-29 02:00:00.938 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 02:00:00.938 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 02:00:00.938 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 02:00:00.940 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:00:00.940 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 02:00:00.940 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 02:00:00.940 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.28.22:6700) Recv POWERON CMD
2026-01-29 02:00:00.940 [INFO] ctrl_if_trx.py:109 (MS@172.18.28.22:6700) Starting transceiver...
2026-01-29 02:00:01.374 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-01-29 02:00:01.409 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:00:01.410 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 02:00:01.410 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:00:01.411 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:00:01.852 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-01-29 02:00:02.329 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-01-29 02:00:02.411 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 02:00:02.411 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:00:02.411 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:00:02.412 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:00:02.807 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-01-29 02:00:03.284 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-01-29 02:00:03.412 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:00:03.412 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:00:03.413 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 02:00:03.414 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:00:03.761 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-01-29 02:00:04.003 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 02:00:04.004 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 02:00:04.005 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:00:04.005 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:00:04.239 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-01-29 02:00:04.413 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 02:00:04.414 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:00:04.414 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:00:04.414 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:00:04.716 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-01-29 02:00:05.194 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-01-29 02:00:05.414 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 02:00:05.414 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:00:05.414 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:00:05.415 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:00:05.671 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-01-29 02:00:06.150 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-01-29 02:00:06.628 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-01-29 02:00:07.106 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-01-29 02:00:07.583 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-01-29 02:00:08.061 [DEBUG] clck_gen.py:113 IND CLOCK 1632
2026-01-29 02:00:08.538 [DEBUG] clck_gen.py:113 IND CLOCK 1734
2026-01-29 02:00:09.006 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 02:00:09.006 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 02:00:09.007 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:00:09.016 [DEBUG] clck_gen.py:113 IND CLOCK 1836
2026-01-29 02:00:09.023 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 02:00:09.024 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:00:09.024 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:00:09.024 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:00:09.027 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 02:00:09.027 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:00:09.027 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:00:09.027 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:00:09.027 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.28.20:5700) Recv POWEROFF cmd
2026-01-29 02:00:09.027 [INFO] ctrl_if_trx.py:117 (BTS@172.18.28.20:5700) Stopping transceiver...
2026-01-29 02:00:09.027 [INFO] transceiver.py:246 Stopping clock generator
2026-01-29 02:00:09.027 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=1840 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:00:09.027 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=1840 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:00:09.027 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=1840 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:00:09.027 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=1840 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:00:09.027 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=1840 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:00:09.027 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=1840 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:00:14.026 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.28.20:5700) Recv POWEROFF cmd
2026-01-29 02:00:14.027 [INFO] ctrl_if_trx.py:117 (BTS@172.18.28.20:5700) Stopping transceiver...
2026-01-29 02:00:14.028 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:00:14.029 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:00:14.030 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:00:14.031 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 02:00:14.042 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 02:00:14.042 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.28.20:5700) Recv SETFORMAT cmd
2026-01-29 02:00:14.042 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.28.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:00:14.043 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.28.20:5700) Recv SETFORMAT cmd
2026-01-29 02:00:14.043 [INFO] ctrl_if_trx.py:201 (BTS@172.18.28.20:5700) TRXD header version 1 -> 1
2026-01-29 02:00:14.045 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.28.20:5700/1) Recv RXTUNE cmd
2026-01-29 02:00:14.045 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.28.20:5700/1) Recv TXTUNE cmd
2026-01-29 02:00:14.045 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.28.20:5700/1) Recv SETFORMAT cmd
2026-01-29 02:00:14.045 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.28.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:00:14.045 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:00:14.045 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.28.20:5700/1) Recv NOMTXPOWER cmd
2026-01-29 02:00:14.045 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.28.20:5700/1) Recv SETFORMAT cmd
2026-01-29 02:00:14.045 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.28.20:5700/1) TRXD header version 1 -> 1
2026-01-29 02:00:14.047 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.28.20:5700/2) Recv RXTUNE cmd
2026-01-29 02:00:14.047 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.28.20:5700/2) Recv TXTUNE cmd
2026-01-29 02:00:14.047 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.28.20:5700/2) Recv SETFORMAT cmd
2026-01-29 02:00:14.047 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.28.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:00:14.048 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:00:14.048 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.28.20:5700/2) Recv NOMTXPOWER cmd
2026-01-29 02:00:14.048 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.28.20:5700/2) Recv SETFORMAT cmd
2026-01-29 02:00:14.048 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.28.20:5700/2) TRXD header version 1 -> 1
2026-01-29 02:00:14.049 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.28.20:5700/3) Recv RXTUNE cmd
2026-01-29 02:00:14.049 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.28.20:5700/3) Recv TXTUNE cmd
2026-01-29 02:00:14.050 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.28.20:5700/3) Recv SETFORMAT cmd
2026-01-29 02:00:14.050 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.28.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:00:14.050 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:00:14.050 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.28.20:5700/3) Recv NOMTXPOWER cmd
2026-01-29 02:00:14.050 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.28.20:5700/3) Recv SETFORMAT cmd
2026-01-29 02:00:14.050 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.28.20:5700/3) TRXD header version 1 -> 1
2026-01-29 02:00:14.052 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.28.20:5700) Recv RXTUNE cmd
2026-01-29 02:00:14.052 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETTSC
2026-01-29 02:00:14.052 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETTSC
2026-01-29 02:00:14.052 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETTSC
2026-01-29 02:00:14.052 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.28.20:5700) Recv TXTUNE cmd
2026-01-29 02:00:14.052 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETRXGAIN
2026-01-29 02:00:14.052 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETRXGAIN
2026-01-29 02:00:14.052 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETRXGAIN
2026-01-29 02:00:14.052 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETTSC
2026-01-29 02:00:14.053 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:00:14.053 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:00:14.053 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:00:14.053 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.28.20:5700) Recv NOMTXPOWER cmd
2026-01-29 02:00:14.053 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:00:14.053 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:00:14.053 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:00:14.053 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.28.20:5700) Recv POWERON CMD
2026-01-29 02:00:14.053 [INFO] ctrl_if_trx.py:109 (BTS@172.18.28.20:5700) Starting transceiver...
2026-01-29 02:00:14.053 [INFO] transceiver.py:243 Starting clock generator
2026-01-29 02:00:14.053 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-01-29 02:00:14.053 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:00:14.053 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:00:14.053 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:00:14.053 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETRXGAIN
2026-01-29 02:00:14.053 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:00:14.053 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:00:14.053 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:00:14.053 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:00:14.053 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:00:14.053 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:00:14.054 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:00:14.054 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:00:14.054 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:00:14.054 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:00:14.054 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:00:14.054 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:00:14.054 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:00:14.054 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:00:14.054 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:00:14.054 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:00:14.054 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:00:14.054 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:00:14.054 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:00:14.054 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:00:14.054 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:00:14.054 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:00:14.054 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:00:14.058 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-01-29 02:00:14.542 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-01-29 02:00:14.578 [DEBUG] fake_trx.py:278 (BTS@172.18.28.20:5700) Recv FAKE_TOA cmd
2026-01-29 02:00:14.580 [DEBUG] fake_trx.py:297 (BTS@172.18.28.20:5700) Recv FAKE_RSSI cmd
2026-01-29 02:00:14.580 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:00:14.582 [DEBUG] fake_trx.py:322 (BTS@172.18.28.20:5700) Recv FAKE_CI cmd
2026-01-29 02:00:14.587 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 02:00:14.587 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 02:00:14.587 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 02:00:14.587 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:00:14.587 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 02:00:14.587 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 02:00:14.587 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.28.22:6700) Recv POWERON CMD
2026-01-29 02:00:14.587 [INFO] ctrl_if_trx.py:109 (MS@172.18.28.22:6700) Starting transceiver...
2026-01-29 02:00:15.019 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-01-29 02:00:15.056 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:00:15.056 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 02:00:15.057 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:00:15.058 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:00:15.497 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-01-29 02:00:15.975 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-01-29 02:00:16.057 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:00:16.057 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 02:00:16.057 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:00:16.058 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:00:16.452 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-01-29 02:00:16.930 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-01-29 02:00:17.057 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:00:17.058 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 02:00:17.058 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:00:17.059 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:00:17.408 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-01-29 02:00:17.650 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 02:00:17.651 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 02:00:17.651 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:00:17.652 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:00:17.885 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-01-29 02:00:18.059 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 02:00:18.059 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:00:18.059 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:00:18.061 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:00:18.363 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-01-29 02:00:18.841 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-01-29 02:00:19.060 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 02:00:19.060 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:00:19.060 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:00:19.061 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:00:19.318 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-01-29 02:00:19.796 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-01-29 02:00:20.273 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-01-29 02:00:20.751 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-01-29 02:00:21.228 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-01-29 02:00:21.706 [DEBUG] clck_gen.py:113 IND CLOCK 1632
2026-01-29 02:00:22.184 [DEBUG] clck_gen.py:113 IND CLOCK 1734
2026-01-29 02:00:22.653 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 02:00:22.653 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 02:00:22.654 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:00:22.661 [DEBUG] clck_gen.py:113 IND CLOCK 1836
2026-01-29 02:00:22.671 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 02:00:22.672 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:00:22.672 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:00:22.672 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:00:22.674 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 02:00:22.674 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:00:22.674 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:00:22.674 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:00:22.674 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.28.20:5700) Recv POWEROFF cmd
2026-01-29 02:00:22.674 [INFO] ctrl_if_trx.py:117 (BTS@172.18.28.20:5700) Stopping transceiver...
2026-01-29 02:00:22.674 [INFO] transceiver.py:246 Stopping clock generator
2026-01-29 02:00:27.674 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.28.20:5700) Recv POWEROFF cmd
2026-01-29 02:00:27.674 [INFO] ctrl_if_trx.py:117 (BTS@172.18.28.20:5700) Stopping transceiver...
2026-01-29 02:00:27.676 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:00:27.677 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:00:27.678 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:00:27.678 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 02:00:27.686 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 02:00:27.686 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.28.20:5700) Recv SETFORMAT cmd
2026-01-29 02:00:27.686 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.28.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:00:27.686 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.28.20:5700) Recv SETFORMAT cmd
2026-01-29 02:00:27.686 [INFO] ctrl_if_trx.py:201 (BTS@172.18.28.20:5700) TRXD header version 1 -> 1
2026-01-29 02:00:27.687 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.28.20:5700/1) Recv RXTUNE cmd
2026-01-29 02:00:27.687 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.28.20:5700/1) Recv TXTUNE cmd
2026-01-29 02:00:27.687 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.28.20:5700/1) Recv SETFORMAT cmd
2026-01-29 02:00:27.687 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.28.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:00:27.687 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:00:27.687 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.28.20:5700/1) Recv NOMTXPOWER cmd
2026-01-29 02:00:27.687 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.28.20:5700/1) Recv SETFORMAT cmd
2026-01-29 02:00:27.687 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.28.20:5700/1) TRXD header version 1 -> 1
2026-01-29 02:00:27.687 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.28.20:5700/2) Recv RXTUNE cmd
2026-01-29 02:00:27.687 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.28.20:5700/2) Recv TXTUNE cmd
2026-01-29 02:00:27.687 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.28.20:5700/2) Recv SETFORMAT cmd
2026-01-29 02:00:27.687 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.28.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:00:27.687 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:00:27.687 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.28.20:5700/2) Recv NOMTXPOWER cmd
2026-01-29 02:00:27.688 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.28.20:5700/2) Recv SETFORMAT cmd
2026-01-29 02:00:27.688 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.28.20:5700/2) TRXD header version 1 -> 1
2026-01-29 02:00:27.688 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.28.20:5700/3) Recv RXTUNE cmd
2026-01-29 02:00:27.688 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.28.20:5700/3) Recv TXTUNE cmd
2026-01-29 02:00:27.688 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.28.20:5700/3) Recv SETFORMAT cmd
2026-01-29 02:00:27.688 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.28.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:00:27.688 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:00:27.688 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.28.20:5700/3) Recv NOMTXPOWER cmd
2026-01-29 02:00:27.688 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.28.20:5700/3) Recv SETFORMAT cmd
2026-01-29 02:00:27.688 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.28.20:5700/3) TRXD header version 1 -> 1
2026-01-29 02:00:27.689 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.28.20:5700) Recv RXTUNE cmd
2026-01-29 02:00:27.689 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETTSC
2026-01-29 02:00:27.689 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETTSC
2026-01-29 02:00:27.689 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETTSC
2026-01-29 02:00:27.689 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.28.20:5700) Recv TXTUNE cmd
2026-01-29 02:00:27.690 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETRXGAIN
2026-01-29 02:00:27.690 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETRXGAIN
2026-01-29 02:00:27.690 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETRXGAIN
2026-01-29 02:00:27.690 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETTSC
2026-01-29 02:00:27.690 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:00:27.690 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:00:27.690 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:00:27.690 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.28.20:5700) Recv NOMTXPOWER cmd
2026-01-29 02:00:27.690 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:00:27.690 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:00:27.690 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:00:27.690 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.28.20:5700) Recv POWERON CMD
2026-01-29 02:00:27.690 [INFO] ctrl_if_trx.py:109 (BTS@172.18.28.20:5700) Starting transceiver...
2026-01-29 02:00:27.690 [INFO] transceiver.py:243 Starting clock generator
2026-01-29 02:00:27.690 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-01-29 02:00:27.690 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:00:27.690 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:00:27.690 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:00:27.690 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETRXGAIN
2026-01-29 02:00:27.690 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:00:27.690 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:00:27.690 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:00:27.690 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:00:27.690 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:00:27.690 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:00:27.690 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:00:27.690 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:00:27.690 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:00:27.690 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:00:27.690 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:00:27.690 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:00:27.690 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:00:27.690 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:00:27.690 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:00:27.690 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:00:27.690 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:00:27.690 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:00:27.690 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:00:27.690 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:00:27.690 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:00:27.690 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:00:27.690 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:00:27.695 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-01-29 02:00:28.177 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-01-29 02:00:28.208 [DEBUG] fake_trx.py:278 (BTS@172.18.28.20:5700) Recv FAKE_TOA cmd
2026-01-29 02:00:28.210 [DEBUG] fake_trx.py:297 (BTS@172.18.28.20:5700) Recv FAKE_RSSI cmd
2026-01-29 02:00:28.210 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:00:28.213 [DEBUG] fake_trx.py:322 (BTS@172.18.28.20:5700) Recv FAKE_CI cmd
2026-01-29 02:00:28.225 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 02:00:28.225 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 02:00:28.225 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 02:00:28.226 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:00:28.226 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 02:00:28.226 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 02:00:28.227 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.28.22:6700) Recv POWERON CMD
2026-01-29 02:00:28.227 [INFO] ctrl_if_trx.py:109 (MS@172.18.28.22:6700) Starting transceiver...
2026-01-29 02:00:28.268 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 02:00:28.268 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 02:00:28.268 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:00:28.269 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:00:28.654 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-01-29 02:00:28.692 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 02:00:28.692 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:00:28.692 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:00:28.694 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:00:29.132 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-01-29 02:00:29.609 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-01-29 02:00:29.692 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 02:00:29.693 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:00:29.693 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:00:29.695 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:00:30.087 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-01-29 02:00:30.565 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-01-29 02:00:30.693 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 02:00:30.693 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:00:30.694 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:00:30.696 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:00:31.042 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-01-29 02:00:31.520 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-01-29 02:00:31.694 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 02:00:31.695 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:00:31.695 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:00:31.697 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:00:31.998 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-01-29 02:00:32.475 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-01-29 02:00:32.695 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 02:00:32.695 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:00:32.695 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:00:32.697 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:00:32.953 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-01-29 02:00:33.270 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 02:00:33.270 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 02:00:33.282 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 02:00:33.282 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:00:33.282 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:00:33.282 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:00:33.285 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 02:00:33.286 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:00:33.286 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:00:33.286 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:00:33.286 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.28.20:5700) Recv POWEROFF cmd
2026-01-29 02:00:33.286 [INFO] ctrl_if_trx.py:117 (BTS@172.18.28.20:5700) Stopping transceiver...
2026-01-29 02:00:33.286 [INFO] transceiver.py:246 Stopping clock generator
2026-01-29 02:00:33.287 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=1196 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:00:33.287 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=1196 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:00:33.287 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=1196 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:00:33.287 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=1196 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:00:33.287 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=1196 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:00:33.287 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=1196 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:00:38.283 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.28.20:5700) Recv POWEROFF cmd
2026-01-29 02:00:38.284 [INFO] ctrl_if_trx.py:117 (BTS@172.18.28.20:5700) Stopping transceiver...
2026-01-29 02:00:38.285 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:00:38.286 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:00:38.287 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:00:38.288 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 02:00:38.292 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 02:00:38.294 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.28.20:5700) Recv SETFORMAT cmd
2026-01-29 02:00:38.294 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.28.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:00:38.294 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.28.20:5700) Recv SETFORMAT cmd
2026-01-29 02:00:38.295 [INFO] ctrl_if_trx.py:201 (BTS@172.18.28.20:5700) TRXD header version 1 -> 1
2026-01-29 02:00:38.297 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.28.20:5700/1) Recv RXTUNE cmd
2026-01-29 02:00:38.297 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.28.20:5700/1) Recv TXTUNE cmd
2026-01-29 02:00:38.298 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.28.20:5700/1) Recv SETFORMAT cmd
2026-01-29 02:00:38.298 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.28.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:00:38.298 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:00:38.298 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.28.20:5700/1) Recv NOMTXPOWER cmd
2026-01-29 02:00:38.298 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.28.20:5700/1) Recv SETFORMAT cmd
2026-01-29 02:00:38.298 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.28.20:5700/1) TRXD header version 1 -> 1
2026-01-29 02:00:38.300 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.28.20:5700/2) Recv RXTUNE cmd
2026-01-29 02:00:38.300 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.28.20:5700/2) Recv TXTUNE cmd
2026-01-29 02:00:38.300 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.28.20:5700/2) Recv SETFORMAT cmd
2026-01-29 02:00:38.300 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.28.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:00:38.300 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:00:38.300 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.28.20:5700/2) Recv NOMTXPOWER cmd
2026-01-29 02:00:38.300 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.28.20:5700/2) Recv SETFORMAT cmd
2026-01-29 02:00:38.300 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.28.20:5700/2) TRXD header version 1 -> 1
2026-01-29 02:00:38.302 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.28.20:5700/3) Recv RXTUNE cmd
2026-01-29 02:00:38.302 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.28.20:5700/3) Recv TXTUNE cmd
2026-01-29 02:00:38.302 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.28.20:5700/3) Recv SETFORMAT cmd
2026-01-29 02:00:38.302 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.28.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:00:38.302 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:00:38.303 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.28.20:5700/3) Recv NOMTXPOWER cmd
2026-01-29 02:00:38.303 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.28.20:5700/3) Recv SETFORMAT cmd
2026-01-29 02:00:38.303 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.28.20:5700/3) TRXD header version 1 -> 1
2026-01-29 02:00:38.305 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.28.20:5700) Recv RXTUNE cmd
2026-01-29 02:00:38.305 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETTSC
2026-01-29 02:00:38.305 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETTSC
2026-01-29 02:00:38.305 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETTSC
2026-01-29 02:00:38.305 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.28.20:5700) Recv TXTUNE cmd
2026-01-29 02:00:38.305 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETRXGAIN
2026-01-29 02:00:38.305 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETRXGAIN
2026-01-29 02:00:38.305 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETRXGAIN
2026-01-29 02:00:38.305 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETTSC
2026-01-29 02:00:38.305 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:00:38.305 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:00:38.306 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:00:38.306 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.28.20:5700) Recv NOMTXPOWER cmd
2026-01-29 02:00:38.306 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:00:38.306 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:00:38.306 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:00:38.306 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.28.20:5700) Recv POWERON CMD
2026-01-29 02:00:38.306 [INFO] ctrl_if_trx.py:109 (BTS@172.18.28.20:5700) Starting transceiver...
2026-01-29 02:00:38.306 [INFO] transceiver.py:243 Starting clock generator
2026-01-29 02:00:38.306 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-01-29 02:00:38.306 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:00:38.306 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:00:38.306 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:00:38.306 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETRXGAIN
2026-01-29 02:00:38.306 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:00:38.306 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:00:38.306 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:00:38.306 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:00:38.306 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:00:38.306 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:00:38.306 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:00:38.306 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:00:38.306 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:00:38.306 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:00:38.306 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:00:38.307 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:00:38.307 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:00:38.307 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:00:38.307 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:00:38.307 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:00:38.307 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:00:38.307 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:00:38.307 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:00:38.307 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:00:38.307 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:00:38.307 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:00:38.307 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:00:38.311 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-01-29 02:00:38.794 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-01-29 02:00:38.833 [DEBUG] fake_trx.py:278 (BTS@172.18.28.20:5700) Recv FAKE_TOA cmd
2026-01-29 02:00:38.835 [DEBUG] fake_trx.py:297 (BTS@172.18.28.20:5700) Recv FAKE_RSSI cmd
2026-01-29 02:00:38.837 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:00:38.838 [DEBUG] fake_trx.py:322 (BTS@172.18.28.20:5700) Recv FAKE_CI cmd
2026-01-29 02:00:38.845 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 02:00:38.846 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 02:00:38.846 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 02:00:38.847 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:00:38.847 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 02:00:38.847 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 02:00:38.847 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.28.22:6700) Recv POWERON CMD
2026-01-29 02:00:38.847 [INFO] ctrl_if_trx.py:109 (MS@172.18.28.22:6700) Starting transceiver...
2026-01-29 02:00:39.271 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-01-29 02:00:39.308 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:00:39.309 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 02:00:39.309 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:00:39.311 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:00:39.749 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-01-29 02:00:40.227 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-01-29 02:00:40.310 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:00:40.310 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 02:00:40.310 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:00:40.313 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:00:40.704 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-01-29 02:00:41.182 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-01-29 02:00:41.311 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 02:00:41.311 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:00:41.312 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:00:41.314 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:00:41.659 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-01-29 02:00:41.902 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 02:00:41.902 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 02:00:41.902 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:00:41.902 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:00:42.137 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-01-29 02:00:42.312 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:00:42.313 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:00:42.313 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 02:00:42.314 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:00:42.614 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-01-29 02:00:43.092 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-01-29 02:00:43.314 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 02:00:43.314 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:00:43.314 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:00:43.315 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:00:43.569 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-01-29 02:00:44.046 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-01-29 02:00:44.524 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-01-29 02:00:44.573 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 02:00:44.573 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 02:00:44.574 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:00:44.582 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 02:00:44.582 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:00:44.582 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:00:44.583 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:00:44.584 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 02:00:44.584 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:00:44.584 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:00:44.584 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:00:44.584 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.28.20:5700) Recv POWEROFF cmd
2026-01-29 02:00:44.584 [INFO] ctrl_if_trx.py:117 (BTS@172.18.28.20:5700) Stopping transceiver...
2026-01-29 02:00:44.584 [INFO] transceiver.py:246 Stopping clock generator
2026-01-29 02:00:44.584 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=1341 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:00:49.583 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.28.20:5700) Recv POWEROFF cmd
2026-01-29 02:00:49.584 [INFO] ctrl_if_trx.py:117 (BTS@172.18.28.20:5700) Stopping transceiver...
2026-01-29 02:00:49.585 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:00:49.586 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:00:49.586 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:00:49.587 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 02:00:49.594 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 02:00:49.596 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.28.20:5700) Recv SETFORMAT cmd
2026-01-29 02:00:49.596 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.28.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:00:49.596 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.28.20:5700) Recv SETFORMAT cmd
2026-01-29 02:00:49.596 [INFO] ctrl_if_trx.py:201 (BTS@172.18.28.20:5700) TRXD header version 1 -> 1
2026-01-29 02:00:49.599 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.28.20:5700/1) Recv RXTUNE cmd
2026-01-29 02:00:49.599 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.28.20:5700/1) Recv TXTUNE cmd
2026-01-29 02:00:49.599 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.28.20:5700/1) Recv SETFORMAT cmd
2026-01-29 02:00:49.599 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.28.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:00:49.600 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:00:49.600 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.28.20:5700/1) Recv NOMTXPOWER cmd
2026-01-29 02:00:49.600 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.28.20:5700/1) Recv SETFORMAT cmd
2026-01-29 02:00:49.600 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.28.20:5700/1) TRXD header version 1 -> 1
2026-01-29 02:00:49.601 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.28.20:5700/2) Recv RXTUNE cmd
2026-01-29 02:00:49.601 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.28.20:5700/2) Recv TXTUNE cmd
2026-01-29 02:00:49.601 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.28.20:5700/2) Recv SETFORMAT cmd
2026-01-29 02:00:49.601 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.28.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:00:49.602 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:00:49.602 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.28.20:5700/2) Recv NOMTXPOWER cmd
2026-01-29 02:00:49.602 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.28.20:5700/2) Recv SETFORMAT cmd
2026-01-29 02:00:49.602 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.28.20:5700/2) TRXD header version 1 -> 1
2026-01-29 02:00:49.604 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.28.20:5700/3) Recv RXTUNE cmd
2026-01-29 02:00:49.604 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.28.20:5700/3) Recv TXTUNE cmd
2026-01-29 02:00:49.604 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.28.20:5700/3) Recv SETFORMAT cmd
2026-01-29 02:00:49.604 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.28.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:00:49.604 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:00:49.604 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.28.20:5700/3) Recv NOMTXPOWER cmd
2026-01-29 02:00:49.604 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.28.20:5700/3) Recv SETFORMAT cmd
2026-01-29 02:00:49.604 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.28.20:5700/3) TRXD header version 1 -> 1
2026-01-29 02:00:49.606 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.28.20:5700) Recv RXTUNE cmd
2026-01-29 02:00:49.606 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETTSC
2026-01-29 02:00:49.606 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETTSC
2026-01-29 02:00:49.606 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETTSC
2026-01-29 02:00:49.606 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.28.20:5700) Recv TXTUNE cmd
2026-01-29 02:00:49.607 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETRXGAIN
2026-01-29 02:00:49.607 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETRXGAIN
2026-01-29 02:00:49.607 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETRXGAIN
2026-01-29 02:00:49.607 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETTSC
2026-01-29 02:00:49.607 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:00:49.607 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:00:49.607 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:00:49.607 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.28.20:5700) Recv NOMTXPOWER cmd
2026-01-29 02:00:49.607 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:00:49.607 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:00:49.607 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:00:49.607 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.28.20:5700) Recv POWERON CMD
2026-01-29 02:00:49.607 [INFO] ctrl_if_trx.py:109 (BTS@172.18.28.20:5700) Starting transceiver...
2026-01-29 02:00:49.607 [INFO] transceiver.py:243 Starting clock generator
2026-01-29 02:00:49.607 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-01-29 02:00:49.607 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:00:49.607 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:00:49.607 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:00:49.607 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETRXGAIN
2026-01-29 02:00:49.607 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:00:49.607 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:00:49.608 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:00:49.608 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:00:49.608 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:00:49.608 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:00:49.608 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:00:49.608 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:00:49.608 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:00:49.608 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:00:49.608 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:00:49.608 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:00:49.608 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:00:49.608 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:00:49.608 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:00:49.608 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:00:49.608 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:00:49.608 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:00:49.608 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:00:49.608 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:00:49.608 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:00:49.608 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:00:49.608 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:00:49.612 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-01-29 02:00:50.095 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-01-29 02:00:50.138 [DEBUG] fake_trx.py:278 (BTS@172.18.28.20:5700) Recv FAKE_TOA cmd
2026-01-29 02:00:50.140 [DEBUG] fake_trx.py:297 (BTS@172.18.28.20:5700) Recv FAKE_RSSI cmd
2026-01-29 02:00:50.143 [DEBUG] fake_trx.py:322 (BTS@172.18.28.20:5700) Recv FAKE_CI cmd
2026-01-29 02:00:50.144 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:00:50.152 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 02:00:50.153 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 02:00:50.153 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 02:00:50.153 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:00:50.154 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 02:00:50.154 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 02:00:50.155 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.28.22:6700) Recv POWERON CMD
2026-01-29 02:00:50.155 [INFO] ctrl_if_trx.py:109 (MS@172.18.28.22:6700) Starting transceiver...
2026-01-29 02:00:50.572 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-01-29 02:00:50.609 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 02:00:50.610 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:00:50.611 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:00:50.614 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:00:51.050 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-01-29 02:00:51.527 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-01-29 02:00:51.610 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 02:00:51.611 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:00:51.611 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:00:51.614 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:00:52.004 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-01-29 02:00:52.482 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-01-29 02:00:52.612 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 02:00:52.612 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:00:52.612 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:00:52.615 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:00:52.960 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-01-29 02:00:53.257 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 02:00:53.258 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 02:00:53.258 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:00:53.263 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 02:00:53.263 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:00:53.263 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:00:53.263 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:00:53.265 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 02:00:53.265 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:00:53.265 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:00:53.265 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:00:53.265 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.28.20:5700) Recv POWEROFF cmd
2026-01-29 02:00:53.265 [INFO] ctrl_if_trx.py:117 (BTS@172.18.28.20:5700) Stopping transceiver...
2026-01-29 02:00:53.265 [INFO] transceiver.py:246 Stopping clock generator
2026-01-29 02:00:53.265 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=781 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:00:53.265 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=781 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:00:53.265 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=781 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:00:53.265 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=781 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:00:53.265 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=781 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:00:53.265 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=781 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:00:53.265 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=781 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:00:53.265 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=781 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:00:53.265 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=782 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:00:58.266 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.28.20:5700) Recv POWEROFF cmd
2026-01-29 02:00:58.267 [INFO] ctrl_if_trx.py:117 (BTS@172.18.28.20:5700) Stopping transceiver...
2026-01-29 02:00:58.268 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:00:58.270 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:00:58.271 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:00:58.271 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 02:00:58.286 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 02:00:58.287 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.28.20:5700) Recv SETFORMAT cmd
2026-01-29 02:00:58.287 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.28.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:00:58.287 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.28.20:5700) Recv SETFORMAT cmd
2026-01-29 02:00:58.287 [INFO] ctrl_if_trx.py:201 (BTS@172.18.28.20:5700) TRXD header version 1 -> 1
2026-01-29 02:00:58.289 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.28.20:5700/1) Recv RXTUNE cmd
2026-01-29 02:00:58.289 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.28.20:5700/1) Recv TXTUNE cmd
2026-01-29 02:00:58.289 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.28.20:5700/1) Recv SETFORMAT cmd
2026-01-29 02:00:58.289 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.28.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:00:58.289 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:00:58.290 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.28.20:5700/1) Recv NOMTXPOWER cmd
2026-01-29 02:00:58.290 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.28.20:5700/1) Recv SETFORMAT cmd
2026-01-29 02:00:58.290 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.28.20:5700/1) TRXD header version 1 -> 1
2026-01-29 02:00:58.290 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.28.20:5700/2) Recv RXTUNE cmd
2026-01-29 02:00:58.291 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.28.20:5700/2) Recv TXTUNE cmd
2026-01-29 02:00:58.291 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.28.20:5700/2) Recv SETFORMAT cmd
2026-01-29 02:00:58.291 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.28.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:00:58.291 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:00:58.291 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.28.20:5700/2) Recv NOMTXPOWER cmd
2026-01-29 02:00:58.291 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.28.20:5700/2) Recv SETFORMAT cmd
2026-01-29 02:00:58.291 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.28.20:5700/2) TRXD header version 1 -> 1
2026-01-29 02:00:58.292 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.28.20:5700/3) Recv RXTUNE cmd
2026-01-29 02:00:58.292 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.28.20:5700/3) Recv TXTUNE cmd
2026-01-29 02:00:58.292 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.28.20:5700/3) Recv SETFORMAT cmd
2026-01-29 02:00:58.292 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.28.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:00:58.292 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:00:58.292 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.28.20:5700/3) Recv NOMTXPOWER cmd
2026-01-29 02:00:58.292 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.28.20:5700/3) Recv SETFORMAT cmd
2026-01-29 02:00:58.292 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.28.20:5700/3) TRXD header version 1 -> 1
2026-01-29 02:00:58.294 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.28.20:5700) Recv RXTUNE cmd
2026-01-29 02:00:58.294 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETTSC
2026-01-29 02:00:58.294 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETTSC
2026-01-29 02:00:58.294 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETTSC
2026-01-29 02:00:58.294 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.28.20:5700) Recv TXTUNE cmd
2026-01-29 02:00:58.294 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETRXGAIN
2026-01-29 02:00:58.294 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETRXGAIN
2026-01-29 02:00:58.294 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETRXGAIN
2026-01-29 02:00:58.294 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETTSC
2026-01-29 02:00:58.294 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:00:58.294 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:00:58.294 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.28.20:5700) Recv NOMTXPOWER cmd
2026-01-29 02:00:58.294 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:00:58.294 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:00:58.294 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:00:58.294 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.28.20:5700) Recv POWERON CMD
2026-01-29 02:00:58.294 [INFO] ctrl_if_trx.py:109 (BTS@172.18.28.20:5700) Starting transceiver...
2026-01-29 02:00:58.294 [INFO] transceiver.py:243 Starting clock generator
2026-01-29 02:00:58.294 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-01-29 02:00:58.294 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:00:58.294 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:00:58.294 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:00:58.294 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETRXGAIN
2026-01-29 02:00:58.294 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:00:58.294 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:00:58.294 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:00:58.294 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:00:58.294 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:00:58.294 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:00:58.294 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:00:58.294 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:00:58.294 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:00:58.294 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:00:58.294 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:00:58.294 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:00:58.294 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:00:58.294 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:00:58.294 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:00:58.294 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:00:58.294 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:00:58.294 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:00:58.295 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:00:58.295 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:00:58.295 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:00:58.295 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:00:58.295 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:00:58.295 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:00:58.299 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-01-29 02:00:58.782 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-01-29 02:00:58.820 [DEBUG] fake_trx.py:278 (BTS@172.18.28.20:5700) Recv FAKE_TOA cmd
2026-01-29 02:00:58.823 [DEBUG] fake_trx.py:297 (BTS@172.18.28.20:5700) Recv FAKE_RSSI cmd
2026-01-29 02:00:58.824 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:00:58.825 [DEBUG] fake_trx.py:322 (BTS@172.18.28.20:5700) Recv FAKE_CI cmd
2026-01-29 02:00:58.833 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 02:00:58.833 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 02:00:58.834 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 02:00:58.834 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:00:58.834 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 02:00:58.835 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 02:00:58.835 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.28.22:6700) Recv POWERON CMD
2026-01-29 02:00:58.835 [INFO] ctrl_if_trx.py:109 (MS@172.18.28.22:6700) Starting transceiver...
2026-01-29 02:00:59.259 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-01-29 02:00:59.296 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 02:00:59.297 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:00:59.297 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:00:59.299 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:00:59.737 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-01-29 02:01:00.215 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-01-29 02:01:00.297 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 02:01:00.297 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:01:00.297 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:01:00.301 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:01:00.693 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-01-29 02:01:01.170 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-01-29 02:01:01.298 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 02:01:01.298 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:01:01.298 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:01:01.301 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:01:01.648 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-01-29 02:01:01.964 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 02:01:01.964 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 02:01:01.965 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:01:01.970 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 02:01:01.970 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:01:01.970 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:01:01.971 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:01:01.973 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 02:01:01.973 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:01:01.973 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:01:01.973 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:01:01.973 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.28.20:5700) Recv POWEROFF cmd
2026-01-29 02:01:01.973 [INFO] ctrl_if_trx.py:117 (BTS@172.18.28.20:5700) Stopping transceiver...
2026-01-29 02:01:01.973 [INFO] transceiver.py:246 Stopping clock generator
2026-01-29 02:01:01.973 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=785 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:01:01.973 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=785 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:01:01.973 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=785 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:01:01.973 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=785 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:01:01.973 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=785 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:01:01.973 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=785 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:01:01.973 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=785 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:01:01.973 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=786 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:01:01.974 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=786 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:01:01.974 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=786 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:01:01.974 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=786 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:01:01.974 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=786 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:01:01.974 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=786 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:01:01.974 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=786 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:01:01.974 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=786 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:01:06.979 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.28.20:5700) Recv POWEROFF cmd
2026-01-29 02:01:06.979 [INFO] ctrl_if_trx.py:117 (BTS@172.18.28.20:5700) Stopping transceiver...
2026-01-29 02:01:06.979 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:01:06.979 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:01:06.980 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:01:06.980 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 02:01:06.993 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 02:01:06.994 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.28.20:5700) Recv SETFORMAT cmd
2026-01-29 02:01:06.995 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.28.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:01:06.995 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.28.20:5700) Recv SETFORMAT cmd
2026-01-29 02:01:06.995 [INFO] ctrl_if_trx.py:201 (BTS@172.18.28.20:5700) TRXD header version 1 -> 1
2026-01-29 02:01:06.998 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.28.20:5700/1) Recv RXTUNE cmd
2026-01-29 02:01:06.998 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.28.20:5700/1) Recv TXTUNE cmd
2026-01-29 02:01:06.998 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.28.20:5700/1) Recv SETFORMAT cmd
2026-01-29 02:01:06.998 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.28.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:01:06.999 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:01:06.999 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.28.20:5700/1) Recv NOMTXPOWER cmd
2026-01-29 02:01:06.999 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.28.20:5700/1) Recv SETFORMAT cmd
2026-01-29 02:01:06.999 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.28.20:5700/1) TRXD header version 1 -> 1
2026-01-29 02:01:07.001 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.28.20:5700/2) Recv RXTUNE cmd
2026-01-29 02:01:07.001 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.28.20:5700/2) Recv TXTUNE cmd
2026-01-29 02:01:07.001 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.28.20:5700/2) Recv SETFORMAT cmd
2026-01-29 02:01:07.001 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.28.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:01:07.001 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:01:07.001 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.28.20:5700/2) Recv NOMTXPOWER cmd
2026-01-29 02:01:07.001 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.28.20:5700/2) Recv SETFORMAT cmd
2026-01-29 02:01:07.001 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.28.20:5700/2) TRXD header version 1 -> 1
2026-01-29 02:01:07.004 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.28.20:5700/3) Recv RXTUNE cmd
2026-01-29 02:01:07.004 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.28.20:5700/3) Recv TXTUNE cmd
2026-01-29 02:01:07.004 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.28.20:5700/3) Recv SETFORMAT cmd
2026-01-29 02:01:07.004 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.28.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:01:07.004 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:01:07.004 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.28.20:5700/3) Recv NOMTXPOWER cmd
2026-01-29 02:01:07.004 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.28.20:5700/3) Recv SETFORMAT cmd
2026-01-29 02:01:07.004 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.28.20:5700/3) TRXD header version 1 -> 1
2026-01-29 02:01:07.006 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.28.20:5700) Recv RXTUNE cmd
2026-01-29 02:01:07.007 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETTSC
2026-01-29 02:01:07.007 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETTSC
2026-01-29 02:01:07.007 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.28.20:5700) Recv TXTUNE cmd
2026-01-29 02:01:07.007 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETTSC
2026-01-29 02:01:07.007 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETRXGAIN
2026-01-29 02:01:07.007 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETRXGAIN
2026-01-29 02:01:07.007 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETTSC
2026-01-29 02:01:07.007 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETRXGAIN
2026-01-29 02:01:07.007 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:01:07.007 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:01:07.007 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.28.20:5700) Recv NOMTXPOWER cmd
2026-01-29 02:01:07.007 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:01:07.007 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:01:07.007 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:01:07.007 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.28.20:5700) Recv POWERON CMD
2026-01-29 02:01:07.007 [INFO] ctrl_if_trx.py:109 (BTS@172.18.28.20:5700) Starting transceiver...
2026-01-29 02:01:07.007 [INFO] transceiver.py:243 Starting clock generator
2026-01-29 02:01:07.007 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-01-29 02:01:07.007 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:01:07.007 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:01:07.007 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:01:07.008 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETRXGAIN
2026-01-29 02:01:07.008 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:01:07.008 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:01:07.008 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:01:07.008 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:01:07.008 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:01:07.008 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:01:07.008 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:01:07.008 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:01:07.008 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:01:07.008 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:01:07.008 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:01:07.008 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:01:07.008 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:01:07.008 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:01:07.008 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:01:07.008 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:01:07.008 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:01:07.008 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:01:07.008 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:01:07.008 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:01:07.008 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:01:07.008 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:01:07.008 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:01:07.008 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:01:07.012 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-01-29 02:01:07.489 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-01-29 02:01:07.526 [DEBUG] fake_trx.py:278 (BTS@172.18.28.20:5700) Recv FAKE_TOA cmd
2026-01-29 02:01:07.526 [DEBUG] fake_trx.py:297 (BTS@172.18.28.20:5700) Recv FAKE_RSSI cmd
2026-01-29 02:01:07.527 [DEBUG] fake_trx.py:322 (BTS@172.18.28.20:5700) Recv FAKE_CI cmd
2026-01-29 02:01:07.527 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:01:07.530 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 02:01:07.530 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 02:01:07.530 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 02:01:07.530 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:01:07.530 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 02:01:07.530 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 02:01:07.530 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.28.22:6700) Recv POWERON CMD
2026-01-29 02:01:07.530 [INFO] ctrl_if_trx.py:109 (MS@172.18.28.22:6700) Starting transceiver...
2026-01-29 02:01:07.805 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 02:01:07.805 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 02:01:07.813 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 02:01:07.813 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:01:07.813 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:01:07.813 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:01:07.816 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 02:01:07.816 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:01:07.816 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:01:07.816 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.28.20:5700) Recv POWEROFF cmd
2026-01-29 02:01:07.816 [INFO] ctrl_if_trx.py:117 (BTS@172.18.28.20:5700) Stopping transceiver...
2026-01-29 02:01:07.816 [INFO] transceiver.py:246 Stopping clock generator
2026-01-29 02:01:07.816 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:01:07.816 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=174 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:01:07.816 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=174 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:01:07.816 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=174 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:01:07.816 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=174 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:01:07.816 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=174 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:01:07.816 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=174 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:01:07.816 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=174 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:01:07.816 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=174 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:01:12.815 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.28.20:5700) Recv POWEROFF cmd
2026-01-29 02:01:12.815 [INFO] ctrl_if_trx.py:117 (BTS@172.18.28.20:5700) Stopping transceiver...
2026-01-29 02:01:12.815 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:01:12.816 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:01:12.816 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:01:12.817 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 02:01:12.823 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 02:01:12.823 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.28.20:5700) Recv SETFORMAT cmd
2026-01-29 02:01:12.823 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.28.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:01:12.823 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.28.20:5700) Recv SETFORMAT cmd
2026-01-29 02:01:12.823 [INFO] ctrl_if_trx.py:201 (BTS@172.18.28.20:5700) TRXD header version 1 -> 1
2026-01-29 02:01:12.825 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.28.20:5700/1) Recv RXTUNE cmd
2026-01-29 02:01:12.825 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.28.20:5700/1) Recv TXTUNE cmd
2026-01-29 02:01:12.825 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.28.20:5700/1) Recv SETFORMAT cmd
2026-01-29 02:01:12.825 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.28.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:01:12.825 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:01:12.825 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.28.20:5700/1) Recv NOMTXPOWER cmd
2026-01-29 02:01:12.825 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.28.20:5700/1) Recv SETFORMAT cmd
2026-01-29 02:01:12.825 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.28.20:5700/1) TRXD header version 1 -> 1
2026-01-29 02:01:12.827 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.28.20:5700/2) Recv RXTUNE cmd
2026-01-29 02:01:12.827 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.28.20:5700/2) Recv TXTUNE cmd
2026-01-29 02:01:12.827 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.28.20:5700/2) Recv SETFORMAT cmd
2026-01-29 02:01:12.827 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.28.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:01:12.827 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:01:12.827 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.28.20:5700/2) Recv NOMTXPOWER cmd
2026-01-29 02:01:12.827 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.28.20:5700/2) Recv SETFORMAT cmd
2026-01-29 02:01:12.827 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.28.20:5700/2) TRXD header version 1 -> 1
2026-01-29 02:01:12.828 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.28.20:5700/3) Recv RXTUNE cmd
2026-01-29 02:01:12.828 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.28.20:5700/3) Recv TXTUNE cmd
2026-01-29 02:01:12.828 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.28.20:5700/3) Recv SETFORMAT cmd
2026-01-29 02:01:12.828 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.28.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:01:12.828 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:01:12.828 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.28.20:5700/3) Recv NOMTXPOWER cmd
2026-01-29 02:01:12.828 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.28.20:5700/3) Recv SETFORMAT cmd
2026-01-29 02:01:12.828 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.28.20:5700/3) TRXD header version 1 -> 1
2026-01-29 02:01:12.830 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.28.20:5700) Recv RXTUNE cmd
2026-01-29 02:01:12.830 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETTSC
2026-01-29 02:01:12.830 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETTSC
2026-01-29 02:01:12.830 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETTSC
2026-01-29 02:01:12.830 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.28.20:5700) Recv TXTUNE cmd
2026-01-29 02:01:12.830 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETRXGAIN
2026-01-29 02:01:12.830 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETRXGAIN
2026-01-29 02:01:12.830 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETRXGAIN
2026-01-29 02:01:12.830 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETTSC
2026-01-29 02:01:12.830 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:01:12.830 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:01:12.830 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:01:12.830 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.28.20:5700) Recv NOMTXPOWER cmd
2026-01-29 02:01:12.830 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:01:12.830 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:01:12.830 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:01:12.830 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.28.20:5700) Recv POWERON CMD
2026-01-29 02:01:12.830 [INFO] ctrl_if_trx.py:109 (BTS@172.18.28.20:5700) Starting transceiver...
2026-01-29 02:01:12.830 [INFO] transceiver.py:243 Starting clock generator
2026-01-29 02:01:12.830 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-01-29 02:01:12.830 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:01:12.830 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:01:12.830 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:01:12.831 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETRXGAIN
2026-01-29 02:01:12.831 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:01:12.831 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:01:12.831 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:01:12.831 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:01:12.831 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:01:12.831 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:01:12.831 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:01:12.831 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:01:12.831 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:01:12.831 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:01:12.831 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:01:12.831 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:01:12.831 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:01:12.831 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:01:12.831 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:01:12.831 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:01:12.831 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:01:12.831 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:01:12.831 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:01:12.831 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:01:12.831 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:01:12.831 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:01:12.831 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:01:12.835 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-01-29 02:01:13.304 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-01-29 02:01:13.343 [DEBUG] fake_trx.py:278 (BTS@172.18.28.20:5700) Recv FAKE_TOA cmd
2026-01-29 02:01:13.343 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:01:13.343 [DEBUG] fake_trx.py:297 (BTS@172.18.28.20:5700) Recv FAKE_RSSI cmd
2026-01-29 02:01:13.344 [DEBUG] fake_trx.py:322 (BTS@172.18.28.20:5700) Recv FAKE_CI cmd
2026-01-29 02:01:13.345 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 02:01:13.345 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 02:01:13.345 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 02:01:13.346 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:01:13.346 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 02:01:13.346 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 02:01:13.346 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.28.22:6700) Recv POWERON CMD
2026-01-29 02:01:13.346 [INFO] ctrl_if_trx.py:109 (MS@172.18.28.22:6700) Starting transceiver...
2026-01-29 02:01:13.572 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 02:01:13.572 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 02:01:13.573 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 02:01:13.573 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:01:13.573 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:01:13.573 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:01:13.574 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 02:01:13.574 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:01:13.574 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:01:13.574 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:01:13.575 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.28.20:5700) Recv POWEROFF cmd
2026-01-29 02:01:13.575 [INFO] ctrl_if_trx.py:117 (BTS@172.18.28.20:5700) Stopping transceiver...
2026-01-29 02:01:13.575 [INFO] transceiver.py:246 Stopping clock generator
2026-01-29 02:01:18.575 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.28.20:5700) Recv POWEROFF cmd
2026-01-29 02:01:18.575 [INFO] ctrl_if_trx.py:117 (BTS@172.18.28.20:5700) Stopping transceiver...
2026-01-29 02:01:18.575 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:01:18.575 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:01:18.576 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:01:18.576 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 02:01:18.583 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 02:01:18.583 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.28.20:5700) Recv SETFORMAT cmd
2026-01-29 02:01:18.583 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.28.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:01:18.583 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.28.20:5700) Recv SETFORMAT cmd
2026-01-29 02:01:18.583 [INFO] ctrl_if_trx.py:201 (BTS@172.18.28.20:5700) TRXD header version 1 -> 1
2026-01-29 02:01:18.585 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.28.20:5700/1) Recv RXTUNE cmd
2026-01-29 02:01:18.585 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.28.20:5700/1) Recv TXTUNE cmd
2026-01-29 02:01:18.585 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.28.20:5700/1) Recv SETFORMAT cmd
2026-01-29 02:01:18.585 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.28.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:01:18.585 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:01:18.585 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.28.20:5700/1) Recv NOMTXPOWER cmd
2026-01-29 02:01:18.585 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.28.20:5700/1) Recv SETFORMAT cmd
2026-01-29 02:01:18.585 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.28.20:5700/1) TRXD header version 1 -> 1
2026-01-29 02:01:18.586 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.28.20:5700/2) Recv RXTUNE cmd
2026-01-29 02:01:18.586 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.28.20:5700/2) Recv TXTUNE cmd
2026-01-29 02:01:18.586 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.28.20:5700/2) Recv SETFORMAT cmd
2026-01-29 02:01:18.586 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.28.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:01:18.586 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.28.20:5700/2) Recv NOMTXPOWER cmd
2026-01-29 02:01:18.586 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:01:18.586 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.28.20:5700/2) Recv SETFORMAT cmd
2026-01-29 02:01:18.586 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.28.20:5700/2) TRXD header version 1 -> 1
2026-01-29 02:01:18.587 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.28.20:5700/3) Recv RXTUNE cmd
2026-01-29 02:01:18.587 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.28.20:5700/3) Recv TXTUNE cmd
2026-01-29 02:01:18.587 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.28.20:5700/3) Recv SETFORMAT cmd
2026-01-29 02:01:18.587 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.28.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:01:18.587 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:01:18.587 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.28.20:5700/3) Recv NOMTXPOWER cmd
2026-01-29 02:01:18.587 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.28.20:5700/3) Recv SETFORMAT cmd
2026-01-29 02:01:18.587 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.28.20:5700/3) TRXD header version 1 -> 1
2026-01-29 02:01:18.589 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.28.20:5700) Recv RXTUNE cmd
2026-01-29 02:01:18.589 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETTSC
2026-01-29 02:01:18.589 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETTSC
2026-01-29 02:01:18.589 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETTSC
2026-01-29 02:01:18.589 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.28.20:5700) Recv TXTUNE cmd
2026-01-29 02:01:18.589 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETRXGAIN
2026-01-29 02:01:18.589 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETRXGAIN
2026-01-29 02:01:18.589 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETRXGAIN
2026-01-29 02:01:18.589 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETTSC
2026-01-29 02:01:18.589 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:01:18.589 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:01:18.589 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:01:18.589 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.28.20:5700) Recv NOMTXPOWER cmd
2026-01-29 02:01:18.589 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:01:18.589 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:01:18.589 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:01:18.589 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.28.20:5700) Recv POWERON CMD
2026-01-29 02:01:18.589 [INFO] ctrl_if_trx.py:109 (BTS@172.18.28.20:5700) Starting transceiver...
2026-01-29 02:01:18.589 [INFO] transceiver.py:243 Starting clock generator
2026-01-29 02:01:18.589 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-01-29 02:01:18.589 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:01:18.589 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:01:18.589 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:01:18.589 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETRXGAIN
2026-01-29 02:01:18.589 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:01:18.589 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:01:18.589 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:01:18.589 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:01:18.589 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:01:18.589 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:01:18.589 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:01:18.589 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:01:18.589 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:01:18.589 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:01:18.589 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:01:18.589 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:01:18.589 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:01:18.589 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:01:18.590 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:01:18.590 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:01:18.590 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:01:18.590 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:01:18.590 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:01:18.590 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:01:18.590 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:01:18.590 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:01:18.590 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:01:18.594 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-01-29 02:01:19.065 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-01-29 02:01:19.102 [DEBUG] fake_trx.py:278 (BTS@172.18.28.20:5700) Recv FAKE_TOA cmd
2026-01-29 02:01:19.102 [DEBUG] fake_trx.py:297 (BTS@172.18.28.20:5700) Recv FAKE_RSSI cmd
2026-01-29 02:01:19.103 [DEBUG] fake_trx.py:322 (BTS@172.18.28.20:5700) Recv FAKE_CI cmd
2026-01-29 02:01:19.103 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:01:19.105 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 02:01:19.105 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 02:01:19.105 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 02:01:19.106 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:01:19.106 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 02:01:19.106 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 02:01:19.106 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.28.22:6700) Recv POWERON CMD
2026-01-29 02:01:19.106 [INFO] ctrl_if_trx.py:109 (MS@172.18.28.22:6700) Starting transceiver...
2026-01-29 02:01:19.533 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-01-29 02:01:19.591 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:01:19.591 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 02:01:19.591 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:01:19.593 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:01:20.000 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-01-29 02:01:20.467 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-01-29 02:01:20.592 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:01:20.592 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 02:01:20.592 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:01:20.593 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:01:20.934 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-01-29 02:01:21.402 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-01-29 02:01:21.592 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:01:21.592 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 02:01:21.592 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:01:21.594 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:01:21.869 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-01-29 02:01:22.336 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-01-29 02:01:22.593 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:01:22.593 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 02:01:22.593 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:01:22.594 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:01:22.803 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-01-29 02:01:23.270 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-01-29 02:01:23.593 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:01:23.593 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:01:23.593 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 02:01:23.595 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:01:23.737 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-01-29 02:01:24.205 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-01-29 02:01:24.673 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-01-29 02:01:25.144 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-01-29 02:01:25.615 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-01-29 02:01:26.085 [DEBUG] clck_gen.py:113 IND CLOCK 1632
2026-01-29 02:01:26.556 [DEBUG] clck_gen.py:113 IND CLOCK 1734
2026-01-29 02:01:27.027 [DEBUG] clck_gen.py:113 IND CLOCK 1836
2026-01-29 02:01:27.498 [DEBUG] clck_gen.py:113 IND CLOCK 1938
2026-01-29 02:01:27.808 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 02:01:27.808 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 02:01:27.809 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 02:01:27.809 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:01:27.809 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:01:27.809 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:01:27.810 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 02:01:27.810 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:01:27.810 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:01:27.810 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:01:27.810 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.28.20:5700) Recv POWEROFF cmd
2026-01-29 02:01:27.810 [INFO] ctrl_if_trx.py:117 (BTS@172.18.28.20:5700) Stopping transceiver...
2026-01-29 02:01:27.810 [INFO] transceiver.py:246 Stopping clock generator
2026-01-29 02:01:32.811 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.28.20:5700) Recv POWEROFF cmd
2026-01-29 02:01:32.811 [INFO] ctrl_if_trx.py:117 (BTS@172.18.28.20:5700) Stopping transceiver...
2026-01-29 02:01:32.811 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:01:32.811 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:01:32.812 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:01:32.812 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 02:01:32.815 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 02:01:32.816 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.28.20:5700) Recv SETFORMAT cmd
2026-01-29 02:01:32.816 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.28.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:01:32.816 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.28.20:5700) Recv SETFORMAT cmd
2026-01-29 02:01:32.816 [INFO] ctrl_if_trx.py:201 (BTS@172.18.28.20:5700) TRXD header version 1 -> 1
2026-01-29 02:01:32.816 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.28.20:5700/1) Recv RXTUNE cmd
2026-01-29 02:01:32.816 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.28.20:5700/1) Recv TXTUNE cmd
2026-01-29 02:01:32.816 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.28.20:5700/1) Recv SETFORMAT cmd
2026-01-29 02:01:32.816 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.28.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:01:32.816 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:01:32.817 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.28.20:5700/1) Recv NOMTXPOWER cmd
2026-01-29 02:01:32.817 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.28.20:5700/1) Recv SETFORMAT cmd
2026-01-29 02:01:32.817 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.28.20:5700/1) TRXD header version 1 -> 1
2026-01-29 02:01:32.817 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.28.20:5700/2) Recv RXTUNE cmd
2026-01-29 02:01:32.817 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.28.20:5700/2) Recv TXTUNE cmd
2026-01-29 02:01:32.817 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.28.20:5700/2) Recv SETFORMAT cmd
2026-01-29 02:01:32.817 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.28.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:01:32.818 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:01:32.818 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.28.20:5700/2) Recv NOMTXPOWER cmd
2026-01-29 02:01:32.818 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.28.20:5700/2) Recv SETFORMAT cmd
2026-01-29 02:01:32.818 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.28.20:5700/2) TRXD header version 1 -> 1
2026-01-29 02:01:32.818 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.28.20:5700/3) Recv RXTUNE cmd
2026-01-29 02:01:32.819 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.28.20:5700/3) Recv TXTUNE cmd
2026-01-29 02:01:32.819 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.28.20:5700/3) Recv SETFORMAT cmd
2026-01-29 02:01:32.819 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.28.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:01:32.819 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:01:32.819 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.28.20:5700/3) Recv NOMTXPOWER cmd
2026-01-29 02:01:32.819 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.28.20:5700/3) Recv SETFORMAT cmd
2026-01-29 02:01:32.819 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.28.20:5700/3) TRXD header version 1 -> 1
2026-01-29 02:01:32.820 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.28.20:5700) Recv RXTUNE cmd
2026-01-29 02:01:32.820 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETTSC
2026-01-29 02:01:32.820 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETTSC
2026-01-29 02:01:32.820 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETTSC
2026-01-29 02:01:32.820 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.28.20:5700) Recv TXTUNE cmd
2026-01-29 02:01:32.820 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETRXGAIN
2026-01-29 02:01:32.820 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETRXGAIN
2026-01-29 02:01:32.820 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETRXGAIN
2026-01-29 02:01:32.820 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETTSC
2026-01-29 02:01:32.820 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:01:32.820 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:01:32.820 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.28.20:5700) Recv NOMTXPOWER cmd
2026-01-29 02:01:32.820 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:01:32.820 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:01:32.820 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.28.20:5700) Recv POWERON CMD
2026-01-29 02:01:32.820 [INFO] ctrl_if_trx.py:109 (BTS@172.18.28.20:5700) Starting transceiver...
2026-01-29 02:01:32.820 [INFO] transceiver.py:243 Starting clock generator
2026-01-29 02:01:32.820 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-01-29 02:01:32.821 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:01:32.821 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:01:32.821 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:01:32.821 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETRXGAIN
2026-01-29 02:01:32.821 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:01:32.821 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:01:32.821 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:01:32.821 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:01:32.821 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:01:32.821 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:01:32.821 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:01:32.821 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:01:32.821 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:01:32.821 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:01:32.821 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:01:32.821 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:01:32.821 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:01:32.821 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:01:32.821 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:01:32.821 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:01:32.821 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:01:32.821 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:01:32.821 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:01:32.821 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:01:32.821 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:01:32.821 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:01:32.821 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:01:32.821 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:01:32.821 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:01:32.825 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-01-29 02:01:33.296 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-01-29 02:01:33.333 [DEBUG] fake_trx.py:278 (BTS@172.18.28.20:5700) Recv FAKE_TOA cmd
2026-01-29 02:01:33.333 [DEBUG] fake_trx.py:297 (BTS@172.18.28.20:5700) Recv FAKE_RSSI cmd
2026-01-29 02:01:33.333 [DEBUG] fake_trx.py:322 (BTS@172.18.28.20:5700) Recv FAKE_CI cmd
2026-01-29 02:01:33.334 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:01:33.335 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 02:01:33.335 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 02:01:33.335 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 02:01:33.335 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:01:33.335 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 02:01:33.335 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 02:01:33.335 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.28.22:6700) Recv POWERON CMD
2026-01-29 02:01:33.335 [INFO] ctrl_if_trx.py:109 (MS@172.18.28.22:6700) Starting transceiver...
2026-01-29 02:01:33.764 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-01-29 02:01:33.823 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 02:01:33.823 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:01:33.824 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:01:33.825 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:01:34.231 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-01-29 02:01:34.698 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-01-29 02:01:34.823 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 02:01:34.823 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:01:34.824 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:01:34.825 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:01:35.165 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-01-29 02:01:35.632 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-01-29 02:01:35.823 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 02:01:35.823 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:01:35.825 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:01:35.826 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:01:36.099 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-01-29 02:01:36.567 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-01-29 02:01:36.824 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 02:01:36.824 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:01:36.825 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:01:36.826 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:01:37.034 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-01-29 02:01:37.501 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-01-29 02:01:37.824 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:01:37.824 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 02:01:37.826 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:01:37.827 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:01:37.968 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-01-29 02:01:38.435 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-01-29 02:01:38.903 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-01-29 02:01:39.370 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-01-29 02:01:39.841 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-01-29 02:01:40.312 [DEBUG] clck_gen.py:113 IND CLOCK 1632
2026-01-29 02:01:40.781 [DEBUG] clck_gen.py:113 IND CLOCK 1734
2026-01-29 02:01:41.248 [DEBUG] clck_gen.py:113 IND CLOCK 1836
2026-01-29 02:01:41.715 [DEBUG] clck_gen.py:113 IND CLOCK 1938
2026-01-29 02:01:42.006 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 02:01:42.006 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 02:01:42.008 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 02:01:42.008 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:01:42.008 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:01:42.008 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:01:42.009 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 02:01:42.009 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:01:42.009 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:01:42.009 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:01:42.009 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.28.20:5700) Recv POWEROFF cmd
2026-01-29 02:01:42.009 [INFO] ctrl_if_trx.py:117 (BTS@172.18.28.20:5700) Stopping transceiver...
2026-01-29 02:01:42.009 [INFO] transceiver.py:246 Stopping clock generator
2026-01-29 02:01:47.009 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.28.20:5700) Recv POWEROFF cmd
2026-01-29 02:01:47.009 [INFO] ctrl_if_trx.py:117 (BTS@172.18.28.20:5700) Stopping transceiver...
2026-01-29 02:01:47.010 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:01:47.011 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:01:47.011 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:01:47.011 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 02:01:47.014 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 02:01:47.014 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.28.20:5700) Recv SETFORMAT cmd
2026-01-29 02:01:47.014 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.28.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:01:47.014 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.28.20:5700) Recv SETFORMAT cmd
2026-01-29 02:01:47.014 [INFO] ctrl_if_trx.py:201 (BTS@172.18.28.20:5700) TRXD header version 1 -> 1
2026-01-29 02:01:47.015 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.28.20:5700/1) Recv RXTUNE cmd
2026-01-29 02:01:47.015 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.28.20:5700/1) Recv TXTUNE cmd
2026-01-29 02:01:47.015 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.28.20:5700/1) Recv SETFORMAT cmd
2026-01-29 02:01:47.015 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.28.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:01:47.015 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:01:47.016 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.28.20:5700/1) Recv NOMTXPOWER cmd
2026-01-29 02:01:47.016 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.28.20:5700/1) Recv SETFORMAT cmd
2026-01-29 02:01:47.016 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.28.20:5700/1) TRXD header version 1 -> 1
2026-01-29 02:01:47.016 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.28.20:5700/2) Recv RXTUNE cmd
2026-01-29 02:01:47.016 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.28.20:5700/2) Recv TXTUNE cmd
2026-01-29 02:01:47.016 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.28.20:5700/2) Recv SETFORMAT cmd
2026-01-29 02:01:47.016 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.28.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:01:47.016 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:01:47.016 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.28.20:5700/2) Recv NOMTXPOWER cmd
2026-01-29 02:01:47.016 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.28.20:5700/2) Recv SETFORMAT cmd
2026-01-29 02:01:47.016 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.28.20:5700/2) TRXD header version 1 -> 1
2026-01-29 02:01:47.017 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.28.20:5700/3) Recv RXTUNE cmd
2026-01-29 02:01:47.017 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.28.20:5700/3) Recv TXTUNE cmd
2026-01-29 02:01:47.017 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.28.20:5700/3) Recv SETFORMAT cmd
2026-01-29 02:01:47.017 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.28.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:01:47.017 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:01:47.017 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.28.20:5700/3) Recv NOMTXPOWER cmd
2026-01-29 02:01:47.017 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.28.20:5700/3) Recv SETFORMAT cmd
2026-01-29 02:01:47.017 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.28.20:5700/3) TRXD header version 1 -> 1
2026-01-29 02:01:47.018 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.28.20:5700) Recv RXTUNE cmd
2026-01-29 02:01:47.018 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETTSC
2026-01-29 02:01:47.018 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETTSC
2026-01-29 02:01:47.018 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETTSC
2026-01-29 02:01:47.018 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.28.20:5700) Recv TXTUNE cmd
2026-01-29 02:01:47.019 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETRXGAIN
2026-01-29 02:01:47.019 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETRXGAIN
2026-01-29 02:01:47.019 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETRXGAIN
2026-01-29 02:01:47.019 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETTSC
2026-01-29 02:01:47.019 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:01:47.019 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:01:47.019 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:01:47.019 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.28.20:5700) Recv NOMTXPOWER cmd
2026-01-29 02:01:47.019 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:01:47.019 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:01:47.019 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:01:47.019 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.28.20:5700) Recv POWERON CMD
2026-01-29 02:01:47.019 [INFO] ctrl_if_trx.py:109 (BTS@172.18.28.20:5700) Starting transceiver...
2026-01-29 02:01:47.019 [INFO] transceiver.py:243 Starting clock generator
2026-01-29 02:01:47.019 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-01-29 02:01:47.019 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:01:47.019 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:01:47.019 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:01:47.019 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETRXGAIN
2026-01-29 02:01:47.019 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:01:47.019 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:01:47.019 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:01:47.019 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:01:47.019 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:01:47.019 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:01:47.019 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:01:47.019 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:01:47.019 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:01:47.019 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:01:47.019 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:01:47.019 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:01:47.020 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:01:47.020 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:01:47.020 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:01:47.020 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:01:47.020 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:01:47.020 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:01:47.020 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:01:47.020 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:01:47.020 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:01:47.020 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:01:47.020 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:01:47.024 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-01-29 02:01:47.495 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-01-29 02:01:47.532 [DEBUG] fake_trx.py:278 (BTS@172.18.28.20:5700) Recv FAKE_TOA cmd
2026-01-29 02:01:47.533 [DEBUG] fake_trx.py:297 (BTS@172.18.28.20:5700) Recv FAKE_RSSI cmd
2026-01-29 02:01:47.533 [DEBUG] fake_trx.py:322 (BTS@172.18.28.20:5700) Recv FAKE_CI cmd
2026-01-29 02:01:47.533 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:01:47.534 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 02:01:47.534 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 02:01:47.535 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 02:01:47.535 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:01:47.535 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 02:01:47.535 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 02:01:47.535 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.28.22:6700) Recv POWERON CMD
2026-01-29 02:01:47.535 [INFO] ctrl_if_trx.py:109 (MS@172.18.28.22:6700) Starting transceiver...
2026-01-29 02:01:47.963 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-01-29 02:01:48.021 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 02:01:48.021 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:01:48.022 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:01:48.024 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:01:48.432 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-01-29 02:01:48.903 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-01-29 02:01:49.022 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 02:01:49.022 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:01:49.022 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:01:49.024 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:01:49.374 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-01-29 02:01:49.844 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-01-29 02:01:50.022 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 02:01:50.022 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:01:50.022 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:01:50.024 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:01:50.315 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-01-29 02:01:50.556 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 02:01:50.556 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 02:01:50.556 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:01:50.556 [DEBUG] fake_trx.py:322 (BTS@172.18.28.20:5700) Recv FAKE_CI cmd
2026-01-29 02:01:50.556 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:01:50.602 [DEBUG] fake_trx.py:322 (BTS@172.18.28.20:5700) Recv FAKE_CI cmd
2026-01-29 02:01:50.643 [DEBUG] fake_trx.py:322 (BTS@172.18.28.20:5700) Recv FAKE_CI cmd
2026-01-29 02:01:50.685 [DEBUG] fake_trx.py:322 (BTS@172.18.28.20:5700) Recv FAKE_CI cmd
2026-01-29 02:01:50.722 [DEBUG] fake_trx.py:322 (BTS@172.18.28.20:5700) Recv FAKE_CI cmd
2026-01-29 02:01:50.763 [DEBUG] fake_trx.py:322 (BTS@172.18.28.20:5700) Recv FAKE_CI cmd
2026-01-29 02:01:50.785 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-01-29 02:01:50.800 [DEBUG] fake_trx.py:322 (BTS@172.18.28.20:5700) Recv FAKE_CI cmd
2026-01-29 02:01:50.837 [DEBUG] fake_trx.py:322 (BTS@172.18.28.20:5700) Recv FAKE_CI cmd
2026-01-29 02:01:50.879 [DEBUG] fake_trx.py:322 (BTS@172.18.28.20:5700) Recv FAKE_CI cmd
2026-01-29 02:01:50.920 [DEBUG] fake_trx.py:322 (BTS@172.18.28.20:5700) Recv FAKE_CI cmd
2026-01-29 02:01:50.957 [DEBUG] fake_trx.py:322 (BTS@172.18.28.20:5700) Recv FAKE_CI cmd
2026-01-29 02:01:50.999 [DEBUG] fake_trx.py:322 (BTS@172.18.28.20:5700) Recv FAKE_CI cmd
2026-01-29 02:01:51.022 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 02:01:51.023 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:01:51.023 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:01:51.025 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:01:51.040 [DEBUG] fake_trx.py:322 (BTS@172.18.28.20:5700) Recv FAKE_CI cmd
2026-01-29 02:01:51.077 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 02:01:51.077 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 02:01:51.078 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:01:51.079 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 02:01:51.079 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:01:51.079 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:01:51.079 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:01:51.080 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 02:01:51.080 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:01:51.080 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:01:51.080 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.28.20:5700) Recv POWEROFF cmd
2026-01-29 02:01:51.080 [INFO] ctrl_if_trx.py:117 (BTS@172.18.28.20:5700) Stopping transceiver...
2026-01-29 02:01:51.080 [INFO] transceiver.py:246 Stopping clock generator
2026-01-29 02:01:51.080 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:01:56.080 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.28.20:5700) Recv POWEROFF cmd
2026-01-29 02:01:56.080 [INFO] ctrl_if_trx.py:117 (BTS@172.18.28.20:5700) Stopping transceiver...
2026-01-29 02:01:56.081 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:01:56.081 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:01:56.081 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:01:56.082 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 02:01:56.085 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 02:01:56.085 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.28.20:5700) Recv SETFORMAT cmd
2026-01-29 02:01:56.085 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.28.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:01:56.085 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.28.20:5700) Recv SETFORMAT cmd
2026-01-29 02:01:56.085 [INFO] ctrl_if_trx.py:201 (BTS@172.18.28.20:5700) TRXD header version 1 -> 1
2026-01-29 02:01:56.086 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.28.20:5700/1) Recv RXTUNE cmd
2026-01-29 02:01:56.086 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.28.20:5700/1) Recv TXTUNE cmd
2026-01-29 02:01:56.086 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.28.20:5700/1) Recv SETFORMAT cmd
2026-01-29 02:01:56.086 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.28.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:01:56.086 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:01:56.087 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.28.20:5700/1) Recv NOMTXPOWER cmd
2026-01-29 02:01:56.087 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.28.20:5700/1) Recv SETFORMAT cmd
2026-01-29 02:01:56.087 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.28.20:5700/1) TRXD header version 1 -> 1
2026-01-29 02:01:56.087 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.28.20:5700/2) Recv RXTUNE cmd
2026-01-29 02:01:56.087 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.28.20:5700/2) Recv TXTUNE cmd
2026-01-29 02:01:56.087 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.28.20:5700/2) Recv SETFORMAT cmd
2026-01-29 02:01:56.087 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.28.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:01:56.087 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:01:56.087 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.28.20:5700/2) Recv NOMTXPOWER cmd
2026-01-29 02:01:56.087 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.28.20:5700/2) Recv SETFORMAT cmd
2026-01-29 02:01:56.087 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.28.20:5700/2) TRXD header version 1 -> 1
2026-01-29 02:01:56.088 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.28.20:5700/3) Recv RXTUNE cmd
2026-01-29 02:01:56.088 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.28.20:5700/3) Recv TXTUNE cmd
2026-01-29 02:01:56.088 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.28.20:5700/3) Recv SETFORMAT cmd
2026-01-29 02:01:56.088 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.28.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:01:56.088 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:01:56.088 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.28.20:5700/3) Recv NOMTXPOWER cmd
2026-01-29 02:01:56.088 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.28.20:5700/3) Recv SETFORMAT cmd
2026-01-29 02:01:56.088 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.28.20:5700/3) TRXD header version 1 -> 1
2026-01-29 02:01:56.089 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.28.20:5700) Recv RXTUNE cmd
2026-01-29 02:01:56.089 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETTSC
2026-01-29 02:01:56.089 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETTSC
2026-01-29 02:01:56.089 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETTSC
2026-01-29 02:01:56.089 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.28.20:5700) Recv TXTUNE cmd
2026-01-29 02:01:56.089 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETRXGAIN
2026-01-29 02:01:56.089 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETRXGAIN
2026-01-29 02:01:56.089 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETRXGAIN
2026-01-29 02:01:56.089 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETTSC
2026-01-29 02:01:56.089 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:01:56.089 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:01:56.089 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:01:56.089 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.28.20:5700) Recv NOMTXPOWER cmd
2026-01-29 02:01:56.089 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:01:56.089 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:01:56.090 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:01:56.090 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.28.20:5700) Recv POWERON CMD
2026-01-29 02:01:56.090 [INFO] ctrl_if_trx.py:109 (BTS@172.18.28.20:5700) Starting transceiver...
2026-01-29 02:01:56.090 [INFO] transceiver.py:243 Starting clock generator
2026-01-29 02:01:56.090 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-01-29 02:01:56.090 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:01:56.090 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:01:56.090 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:01:56.090 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETRXGAIN
2026-01-29 02:01:56.090 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:01:56.090 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:01:56.090 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:01:56.090 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:01:56.090 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:01:56.090 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:01:56.090 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:01:56.090 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:01:56.090 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:01:56.090 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:01:56.090 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:01:56.090 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:01:56.090 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:01:56.090 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:01:56.090 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:01:56.090 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:01:56.090 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:01:56.090 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:01:56.090 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:01:56.090 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:01:56.090 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:01:56.090 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:01:56.090 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:01:56.094 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-01-29 02:01:56.566 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-01-29 02:01:56.602 [DEBUG] fake_trx.py:278 (BTS@172.18.28.20:5700) Recv FAKE_TOA cmd
2026-01-29 02:01:56.603 [DEBUG] fake_trx.py:297 (BTS@172.18.28.20:5700) Recv FAKE_RSSI cmd
2026-01-29 02:01:56.603 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:01:56.603 [DEBUG] fake_trx.py:322 (BTS@172.18.28.20:5700) Recv FAKE_CI cmd
2026-01-29 02:01:56.638 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 02:01:56.638 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:01:56.638 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:01:56.638 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:01:56.639 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 02:01:56.639 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:01:56.640 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:01:56.640 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.28.20:5700) Recv POWEROFF cmd
2026-01-29 02:01:56.640 [INFO] ctrl_if_trx.py:117 (BTS@172.18.28.20:5700) Stopping transceiver...
2026-01-29 02:01:56.640 [INFO] transceiver.py:246 Stopping clock generator
2026-01-29 02:01:56.640 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:01:56.640 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=120 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:01:56.640 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=120 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:02:01.640 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.28.20:5700) Recv POWEROFF cmd
2026-01-29 02:02:01.640 [INFO] ctrl_if_trx.py:117 (BTS@172.18.28.20:5700) Stopping transceiver...
2026-01-29 02:02:01.640 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:02:01.641 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:02:01.641 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:02:01.642 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 02:02:01.647 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 02:02:01.647 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.28.20:5700) Recv SETFORMAT cmd
2026-01-29 02:02:01.647 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.28.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:02:01.647 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.28.20:5700) Recv SETFORMAT cmd
2026-01-29 02:02:01.647 [INFO] ctrl_if_trx.py:201 (BTS@172.18.28.20:5700) TRXD header version 1 -> 1
2026-01-29 02:02:01.648 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.28.20:5700/1) Recv RXTUNE cmd
2026-01-29 02:02:01.648 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.28.20:5700/1) Recv TXTUNE cmd
2026-01-29 02:02:01.648 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.28.20:5700/1) Recv SETFORMAT cmd
2026-01-29 02:02:01.648 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.28.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:02:01.648 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:02:01.648 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.28.20:5700/1) Recv NOMTXPOWER cmd
2026-01-29 02:02:01.649 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.28.20:5700/1) Recv SETFORMAT cmd
2026-01-29 02:02:01.649 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.28.20:5700/1) TRXD header version 1 -> 1
2026-01-29 02:02:01.649 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.28.20:5700/2) Recv RXTUNE cmd
2026-01-29 02:02:01.649 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.28.20:5700/2) Recv TXTUNE cmd
2026-01-29 02:02:01.649 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.28.20:5700/2) Recv SETFORMAT cmd
2026-01-29 02:02:01.649 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.28.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:02:01.649 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:02:01.649 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.28.20:5700/2) Recv NOMTXPOWER cmd
2026-01-29 02:02:01.649 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.28.20:5700/2) Recv SETFORMAT cmd
2026-01-29 02:02:01.649 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.28.20:5700/2) TRXD header version 1 -> 1
2026-01-29 02:02:01.650 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.28.20:5700/3) Recv RXTUNE cmd
2026-01-29 02:02:01.650 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.28.20:5700/3) Recv TXTUNE cmd
2026-01-29 02:02:01.650 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.28.20:5700/3) Recv SETFORMAT cmd
2026-01-29 02:02:01.650 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.28.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:02:01.650 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:02:01.650 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.28.20:5700/3) Recv NOMTXPOWER cmd
2026-01-29 02:02:01.650 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.28.20:5700/3) Recv SETFORMAT cmd
2026-01-29 02:02:01.650 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.28.20:5700/3) TRXD header version 1 -> 1
2026-01-29 02:02:01.652 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.28.20:5700) Recv RXTUNE cmd
2026-01-29 02:02:01.652 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETTSC
2026-01-29 02:02:01.652 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETTSC
2026-01-29 02:02:01.652 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETTSC
2026-01-29 02:02:01.652 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.28.20:5700) Recv TXTUNE cmd
2026-01-29 02:02:01.652 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETRXGAIN
2026-01-29 02:02:01.652 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETRXGAIN
2026-01-29 02:02:01.652 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETRXGAIN
2026-01-29 02:02:01.652 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETTSC
2026-01-29 02:02:01.652 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:02:01.652 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:02:01.652 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:02:01.652 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.28.20:5700) Recv NOMTXPOWER cmd
2026-01-29 02:02:01.652 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:02:01.652 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:02:01.652 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:02:01.652 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.28.20:5700) Recv POWERON CMD
2026-01-29 02:02:01.652 [INFO] ctrl_if_trx.py:109 (BTS@172.18.28.20:5700) Starting transceiver...
2026-01-29 02:02:01.652 [INFO] transceiver.py:243 Starting clock generator
2026-01-29 02:02:01.652 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-01-29 02:02:01.652 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:02:01.652 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:02:01.652 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:02:01.652 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETRXGAIN
2026-01-29 02:02:01.652 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:02:01.652 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:02:01.652 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:02:01.652 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:02:01.652 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:02:01.652 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:02:01.653 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:02:01.653 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:02:01.653 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:02:01.653 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:02:01.653 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:02:01.653 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:02:01.653 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:02:01.653 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:02:01.653 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:02:01.653 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:02:01.653 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:02:01.653 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:02:01.653 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:02:01.653 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:02:01.653 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:02:01.653 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:02:01.653 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:02:01.657 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-01-29 02:02:02.128 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-01-29 02:02:02.164 [DEBUG] fake_trx.py:278 (BTS@172.18.28.20:5700) Recv FAKE_TOA cmd
2026-01-29 02:02:02.164 [DEBUG] fake_trx.py:297 (BTS@172.18.28.20:5700) Recv FAKE_RSSI cmd
2026-01-29 02:02:02.165 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:02:02.165 [DEBUG] fake_trx.py:322 (BTS@172.18.28.20:5700) Recv FAKE_CI cmd
2026-01-29 02:02:02.599 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-01-29 02:02:02.654 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 02:02:02.654 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:02:02.655 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:02:02.657 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:02:03.070 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-01-29 02:02:03.541 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-01-29 02:02:03.654 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 02:02:03.655 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:02:03.656 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:02:03.658 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:02:04.011 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-01-29 02:02:04.482 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-01-29 02:02:04.655 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 02:02:04.655 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:02:04.656 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:02:04.659 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:02:04.953 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-01-29 02:02:05.424 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-01-29 02:02:05.656 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 02:02:05.656 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:02:05.657 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:02:05.659 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:02:05.894 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-01-29 02:02:06.365 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-01-29 02:02:06.656 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 02:02:06.656 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:02:06.657 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:02:06.660 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:02:06.836 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-01-29 02:02:07.307 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-01-29 02:02:07.777 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-01-29 02:02:08.248 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-01-29 02:02:08.716 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-01-29 02:02:09.184 [DEBUG] clck_gen.py:113 IND CLOCK 1632
2026-01-29 02:02:09.657 [DEBUG] clck_gen.py:113 IND CLOCK 1734
2026-01-29 02:02:10.135 [DEBUG] clck_gen.py:113 IND CLOCK 1836
2026-01-29 02:02:10.607 [DEBUG] clck_gen.py:113 IND CLOCK 1938
2026-01-29 02:02:11.076 [DEBUG] clck_gen.py:113 IND CLOCK 2040
2026-01-29 02:02:11.177 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:02:11.184 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 02:02:11.185 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:02:11.185 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:02:11.185 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:02:11.190 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 02:02:11.190 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:02:11.191 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:02:11.191 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:02:11.191 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.28.20:5700) Recv POWEROFF cmd
2026-01-29 02:02:11.191 [INFO] ctrl_if_trx.py:117 (BTS@172.18.28.20:5700) Stopping transceiver...
2026-01-29 02:02:11.191 [INFO] transceiver.py:246 Stopping clock generator
2026-01-29 02:02:11.191 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=2067 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:02:11.191 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=2067 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:02:11.192 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=2067 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:02:11.192 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=2067 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:02:11.192 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=2067 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:02:11.192 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=2067 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:02:16.185 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.28.20:5700) Recv POWEROFF cmd
2026-01-29 02:02:16.185 [INFO] ctrl_if_trx.py:117 (BTS@172.18.28.20:5700) Stopping transceiver...
2026-01-29 02:02:16.186 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:02:16.187 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:02:16.189 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:02:16.190 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 02:02:16.195 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 02:02:16.196 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.28.20:5700) Recv SETFORMAT cmd
2026-01-29 02:02:16.196 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.28.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:02:16.196 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.28.20:5700) Recv SETFORMAT cmd
2026-01-29 02:02:16.196 [INFO] ctrl_if_trx.py:201 (BTS@172.18.28.20:5700) TRXD header version 1 -> 1
2026-01-29 02:02:16.197 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.28.20:5700/1) Recv RXTUNE cmd
2026-01-29 02:02:16.197 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.28.20:5700/1) Recv TXTUNE cmd
2026-01-29 02:02:16.198 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.28.20:5700/1) Recv SETFORMAT cmd
2026-01-29 02:02:16.198 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.28.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:02:16.198 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:02:16.198 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.28.20:5700/1) Recv NOMTXPOWER cmd
2026-01-29 02:02:16.198 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.28.20:5700/1) Recv SETFORMAT cmd
2026-01-29 02:02:16.198 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.28.20:5700/1) TRXD header version 1 -> 1
2026-01-29 02:02:16.199 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.28.20:5700/2) Recv RXTUNE cmd
2026-01-29 02:02:16.199 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.28.20:5700/2) Recv TXTUNE cmd
2026-01-29 02:02:16.200 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.28.20:5700/2) Recv SETFORMAT cmd
2026-01-29 02:02:16.200 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.28.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:02:16.200 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:02:16.200 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.28.20:5700/2) Recv NOMTXPOWER cmd
2026-01-29 02:02:16.200 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.28.20:5700/2) Recv SETFORMAT cmd
2026-01-29 02:02:16.200 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.28.20:5700/2) TRXD header version 1 -> 1
2026-01-29 02:02:16.201 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.28.20:5700/3) Recv RXTUNE cmd
2026-01-29 02:02:16.201 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.28.20:5700/3) Recv TXTUNE cmd
2026-01-29 02:02:16.201 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.28.20:5700/3) Recv SETFORMAT cmd
2026-01-29 02:02:16.201 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.28.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:02:16.201 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:02:16.201 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.28.20:5700/3) Recv NOMTXPOWER cmd
2026-01-29 02:02:16.201 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.28.20:5700/3) Recv SETFORMAT cmd
2026-01-29 02:02:16.201 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.28.20:5700/3) TRXD header version 1 -> 1
2026-01-29 02:02:16.203 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.28.20:5700) Recv RXTUNE cmd
2026-01-29 02:02:16.203 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETTSC
2026-01-29 02:02:16.203 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETTSC
2026-01-29 02:02:16.203 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETTSC
2026-01-29 02:02:16.203 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.28.20:5700) Recv TXTUNE cmd
2026-01-29 02:02:16.203 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETRXGAIN
2026-01-29 02:02:16.203 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETRXGAIN
2026-01-29 02:02:16.203 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETRXGAIN
2026-01-29 02:02:16.203 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETTSC
2026-01-29 02:02:16.203 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:02:16.203 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:02:16.203 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:02:16.203 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.28.20:5700) Recv NOMTXPOWER cmd
2026-01-29 02:02:16.203 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:02:16.204 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:02:16.204 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:02:16.204 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.28.20:5700) Recv POWERON CMD
2026-01-29 02:02:16.204 [INFO] ctrl_if_trx.py:109 (BTS@172.18.28.20:5700) Starting transceiver...
2026-01-29 02:02:16.204 [INFO] transceiver.py:243 Starting clock generator
2026-01-29 02:02:16.204 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-01-29 02:02:16.204 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:02:16.204 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:02:16.204 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:02:16.204 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETRXGAIN
2026-01-29 02:02:16.204 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:02:16.204 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:02:16.204 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:02:16.204 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:02:16.204 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:02:16.204 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:02:16.204 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:02:16.204 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:02:16.204 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:02:16.204 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:02:16.204 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:02:16.204 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:02:16.205 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:02:16.205 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:02:16.205 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:02:16.205 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:02:16.205 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:02:16.205 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:02:16.205 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:02:16.205 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:02:16.205 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:02:16.205 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:02:16.205 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:02:16.208 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-01-29 02:02:16.681 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-01-29 02:02:16.719 [DEBUG] fake_trx.py:278 (BTS@172.18.28.20:5700) Recv FAKE_TOA cmd
2026-01-29 02:02:16.720 [DEBUG] fake_trx.py:297 (BTS@172.18.28.20:5700) Recv FAKE_RSSI cmd
2026-01-29 02:02:16.720 [DEBUG] fake_trx.py:322 (BTS@172.18.28.20:5700) Recv FAKE_CI cmd
2026-01-29 02:02:16.720 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:02:17.149 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-01-29 02:02:17.206 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 02:02:17.207 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:02:17.207 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:02:17.210 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:02:17.617 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-01-29 02:02:18.089 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-01-29 02:02:18.208 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:02:18.208 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 02:02:18.208 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:02:18.211 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:02:18.565 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-01-29 02:02:19.041 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-01-29 02:02:19.209 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 02:02:19.209 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:02:19.209 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:02:19.212 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:02:19.518 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-01-29 02:02:19.993 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-01-29 02:02:20.210 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:02:20.210 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 02:02:20.210 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:02:20.213 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:02:20.468 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-01-29 02:02:20.943 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-01-29 02:02:21.211 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:02:21.211 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 02:02:21.211 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:02:21.214 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:02:21.420 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-01-29 02:02:21.895 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-01-29 02:02:22.370 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-01-29 02:02:22.846 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-01-29 02:02:23.323 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-01-29 02:02:23.795 [DEBUG] clck_gen.py:113 IND CLOCK 1632
2026-01-29 02:02:24.272 [DEBUG] clck_gen.py:113 IND CLOCK 1734
2026-01-29 02:02:24.748 [DEBUG] clck_gen.py:113 IND CLOCK 1836
2026-01-29 02:02:25.226 [DEBUG] clck_gen.py:113 IND CLOCK 1938
2026-01-29 02:02:25.704 [DEBUG] clck_gen.py:113 IND CLOCK 2040
2026-01-29 02:02:25.744 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:02:25.749 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 02:02:25.749 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:02:25.749 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:02:25.749 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:02:25.750 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 02:02:25.750 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:02:25.750 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:02:25.750 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.28.20:5700) Recv POWEROFF cmd
2026-01-29 02:02:25.750 [INFO] ctrl_if_trx.py:117 (BTS@172.18.28.20:5700) Stopping transceiver...
2026-01-29 02:02:25.750 [INFO] transceiver.py:246 Stopping clock generator
2026-01-29 02:02:25.750 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:02:30.752 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.28.20:5700) Recv POWEROFF cmd
2026-01-29 02:02:30.752 [INFO] ctrl_if_trx.py:117 (BTS@172.18.28.20:5700) Stopping transceiver...
2026-01-29 02:02:30.754 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:02:30.755 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:02:30.756 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:02:30.756 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 02:02:30.766 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 02:02:30.767 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.28.20:5700) Recv SETFORMAT cmd
2026-01-29 02:02:30.767 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.28.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:02:30.767 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.28.20:5700) Recv SETFORMAT cmd
2026-01-29 02:02:30.767 [INFO] ctrl_if_trx.py:201 (BTS@172.18.28.20:5700) TRXD header version 1 -> 1
2026-01-29 02:02:30.769 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.28.20:5700/1) Recv RXTUNE cmd
2026-01-29 02:02:30.769 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.28.20:5700/1) Recv TXTUNE cmd
2026-01-29 02:02:30.769 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.28.20:5700/1) Recv SETFORMAT cmd
2026-01-29 02:02:30.769 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.28.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:02:30.769 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:02:30.770 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.28.20:5700/1) Recv NOMTXPOWER cmd
2026-01-29 02:02:30.770 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.28.20:5700/1) Recv SETFORMAT cmd
2026-01-29 02:02:30.770 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.28.20:5700/1) TRXD header version 1 -> 1
2026-01-29 02:02:30.771 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.28.20:5700/2) Recv RXTUNE cmd
2026-01-29 02:02:30.771 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.28.20:5700/2) Recv TXTUNE cmd
2026-01-29 02:02:30.771 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.28.20:5700/2) Recv SETFORMAT cmd
2026-01-29 02:02:30.771 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.28.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:02:30.771 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:02:30.771 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.28.20:5700/2) Recv NOMTXPOWER cmd
2026-01-29 02:02:30.772 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.28.20:5700/2) Recv SETFORMAT cmd
2026-01-29 02:02:30.772 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.28.20:5700/2) TRXD header version 1 -> 1
2026-01-29 02:02:30.773 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.28.20:5700/3) Recv RXTUNE cmd
2026-01-29 02:02:30.773 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.28.20:5700/3) Recv TXTUNE cmd
2026-01-29 02:02:30.773 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.28.20:5700/3) Recv SETFORMAT cmd
2026-01-29 02:02:30.773 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.28.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:02:30.773 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:02:30.773 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.28.20:5700/3) Recv NOMTXPOWER cmd
2026-01-29 02:02:30.773 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.28.20:5700/3) Recv SETFORMAT cmd
2026-01-29 02:02:30.773 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.28.20:5700/3) TRXD header version 1 -> 1
2026-01-29 02:02:30.775 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.28.20:5700) Recv RXTUNE cmd
2026-01-29 02:02:30.775 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETTSC
2026-01-29 02:02:30.775 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETTSC
2026-01-29 02:02:30.775 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETTSC
2026-01-29 02:02:30.775 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.28.20:5700) Recv TXTUNE cmd
2026-01-29 02:02:30.775 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETRXGAIN
2026-01-29 02:02:30.775 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETRXGAIN
2026-01-29 02:02:30.775 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETRXGAIN
2026-01-29 02:02:30.775 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETTSC
2026-01-29 02:02:30.775 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:02:30.775 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:02:30.775 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.28.20:5700) Recv NOMTXPOWER cmd
2026-01-29 02:02:30.775 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:02:30.775 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:02:30.775 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:02:30.775 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.28.20:5700) Recv POWERON CMD
2026-01-29 02:02:30.775 [INFO] ctrl_if_trx.py:109 (BTS@172.18.28.20:5700) Starting transceiver...
2026-01-29 02:02:30.775 [INFO] transceiver.py:243 Starting clock generator
2026-01-29 02:02:30.775 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-01-29 02:02:30.775 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:02:30.775 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:02:30.775 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:02:30.775 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETRXGAIN
2026-01-29 02:02:30.775 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:02:30.775 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:02:30.775 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:02:30.775 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:02:30.775 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:02:30.775 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:02:30.775 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:02:30.775 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:02:30.775 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:02:30.775 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:02:30.775 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:02:30.776 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:02:30.776 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:02:30.776 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:02:30.776 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:02:30.776 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:02:30.776 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:02:30.776 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:02:30.776 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:02:30.776 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:02:30.776 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:02:30.776 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:02:30.776 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:02:30.776 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:02:30.780 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-01-29 02:02:31.258 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-01-29 02:02:31.297 [DEBUG] fake_trx.py:278 (BTS@172.18.28.20:5700) Recv FAKE_TOA cmd
2026-01-29 02:02:31.299 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:02:31.300 [DEBUG] fake_trx.py:297 (BTS@172.18.28.20:5700) Recv FAKE_RSSI cmd
2026-01-29 02:02:31.301 [DEBUG] fake_trx.py:322 (BTS@172.18.28.20:5700) Recv FAKE_CI cmd
2026-01-29 02:02:31.735 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-01-29 02:02:31.777 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 02:02:31.778 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:02:31.778 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:02:31.779 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:02:32.211 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-01-29 02:02:32.680 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-01-29 02:02:32.778 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 02:02:32.779 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:02:32.779 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:02:32.780 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:02:33.155 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-01-29 02:02:33.632 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-01-29 02:02:33.778 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 02:02:33.780 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:02:33.780 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:02:33.781 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:02:34.099 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-01-29 02:02:34.333 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:02:34.335 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 02:02:34.335 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:02:34.335 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:02:34.335 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:02:34.336 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 02:02:34.336 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:02:34.336 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:02:34.336 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.28.20:5700) Recv POWEROFF cmd
2026-01-29 02:02:34.336 [INFO] ctrl_if_trx.py:117 (BTS@172.18.28.20:5700) Stopping transceiver...
2026-01-29 02:02:34.336 [INFO] transceiver.py:246 Stopping clock generator
2026-01-29 02:02:34.336 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:02:34.337 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=767 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:02:34.337 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=767 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:02:34.337 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=767 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:02:34.337 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=767 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:02:34.337 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=767 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:02:34.337 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=767 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:02:34.337 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=767 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:02:34.337 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=767 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:02:39.338 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.28.20:5700) Recv POWEROFF cmd
2026-01-29 02:02:39.338 [INFO] ctrl_if_trx.py:117 (BTS@172.18.28.20:5700) Stopping transceiver...
2026-01-29 02:02:39.340 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:02:39.341 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:02:39.342 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:02:39.343 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 02:02:39.347 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 02:02:39.349 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.28.20:5700) Recv SETFORMAT cmd
2026-01-29 02:02:39.349 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.28.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:02:39.349 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.28.20:5700) Recv SETFORMAT cmd
2026-01-29 02:02:39.350 [INFO] ctrl_if_trx.py:201 (BTS@172.18.28.20:5700) TRXD header version 1 -> 1
2026-01-29 02:02:39.353 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.28.20:5700/1) Recv RXTUNE cmd
2026-01-29 02:02:39.353 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.28.20:5700/1) Recv TXTUNE cmd
2026-01-29 02:02:39.353 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.28.20:5700/1) Recv SETFORMAT cmd
2026-01-29 02:02:39.353 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.28.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:02:39.353 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:02:39.354 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.28.20:5700/1) Recv NOMTXPOWER cmd
2026-01-29 02:02:39.354 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.28.20:5700/1) Recv SETFORMAT cmd
2026-01-29 02:02:39.354 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.28.20:5700/1) TRXD header version 1 -> 1
2026-01-29 02:02:39.358 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.28.20:5700/2) Recv RXTUNE cmd
2026-01-29 02:02:39.358 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.28.20:5700/2) Recv TXTUNE cmd
2026-01-29 02:02:39.358 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.28.20:5700/2) Recv SETFORMAT cmd
2026-01-29 02:02:39.358 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.28.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:02:39.359 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:02:39.359 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.28.20:5700/2) Recv NOMTXPOWER cmd
2026-01-29 02:02:39.359 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.28.20:5700/2) Recv SETFORMAT cmd
2026-01-29 02:02:39.359 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.28.20:5700/2) TRXD header version 1 -> 1
2026-01-29 02:02:39.362 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.28.20:5700/3) Recv RXTUNE cmd
2026-01-29 02:02:39.362 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.28.20:5700/3) Recv TXTUNE cmd
2026-01-29 02:02:39.362 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.28.20:5700/3) Recv SETFORMAT cmd
2026-01-29 02:02:39.362 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.28.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:02:39.362 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:02:39.362 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.28.20:5700/3) Recv NOMTXPOWER cmd
2026-01-29 02:02:39.362 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.28.20:5700/3) Recv SETFORMAT cmd
2026-01-29 02:02:39.362 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.28.20:5700/3) TRXD header version 1 -> 1
2026-01-29 02:02:39.365 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.28.20:5700) Recv RXTUNE cmd
2026-01-29 02:02:39.365 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETTSC
2026-01-29 02:02:39.365 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETTSC
2026-01-29 02:02:39.365 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETTSC
2026-01-29 02:02:39.365 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.28.20:5700) Recv TXTUNE cmd
2026-01-29 02:02:39.365 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETRXGAIN
2026-01-29 02:02:39.365 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETRXGAIN
2026-01-29 02:02:39.366 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETRXGAIN
2026-01-29 02:02:39.366 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETTSC
2026-01-29 02:02:39.366 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:02:39.366 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:02:39.366 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.28.20:5700) Recv NOMTXPOWER cmd
2026-01-29 02:02:39.366 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:02:39.366 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:02:39.366 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:02:39.366 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.28.20:5700) Recv POWERON CMD
2026-01-29 02:02:39.366 [INFO] ctrl_if_trx.py:109 (BTS@172.18.28.20:5700) Starting transceiver...
2026-01-29 02:02:39.366 [INFO] transceiver.py:243 Starting clock generator
2026-01-29 02:02:39.366 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-01-29 02:02:39.366 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:02:39.366 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:02:39.366 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:02:39.366 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETRXGAIN
2026-01-29 02:02:39.367 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:02:39.367 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:02:39.367 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:02:39.367 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:02:39.367 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:02:39.367 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:02:39.367 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:02:39.367 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:02:39.367 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:02:39.367 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:02:39.367 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:02:39.367 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:02:39.367 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:02:39.367 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:02:39.367 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:02:39.367 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:02:39.367 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:02:39.367 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:02:39.367 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:02:39.367 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:02:39.367 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:02:39.367 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:02:39.367 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:02:39.367 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:02:39.371 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-01-29 02:02:39.848 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-01-29 02:02:39.883 [DEBUG] fake_trx.py:278 (BTS@172.18.28.20:5700) Recv FAKE_TOA cmd
2026-01-29 02:02:39.883 [DEBUG] fake_trx.py:297 (BTS@172.18.28.20:5700) Recv FAKE_RSSI cmd
2026-01-29 02:02:39.884 [DEBUG] fake_trx.py:322 (BTS@172.18.28.20:5700) Recv FAKE_CI cmd
2026-01-29 02:02:39.884 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:02:39.891 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 02:02:39.891 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 02:02:39.891 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 02:02:39.894 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:02:39.894 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 02:02:39.894 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 02:02:39.894 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.28.22:6700) Recv POWERON CMD
2026-01-29 02:02:39.894 [INFO] ctrl_if_trx.py:109 (MS@172.18.28.22:6700) Starting transceiver...
2026-01-29 02:02:39.938 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:02:39.940 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 02:02:39.940 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 02:02:39.940 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:02:39.940 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:02:40.324 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-01-29 02:02:40.328 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:02:40.331 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:02:40.333 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 02:02:40.333 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 02:02:40.342 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 02:02:40.342 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:02:40.342 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:02:40.342 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:02:40.343 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 02:02:40.343 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:02:40.343 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:02:40.343 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:02:40.343 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.28.20:5700) Recv POWEROFF cmd
2026-01-29 02:02:40.343 [INFO] ctrl_if_trx.py:117 (BTS@172.18.28.20:5700) Stopping transceiver...
2026-01-29 02:02:40.343 [INFO] transceiver.py:246 Stopping clock generator
2026-01-29 02:02:40.343 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=211 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:02:40.343 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=211 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:02:40.343 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=211 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:02:40.343 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=211 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:02:40.343 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=211 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:02:40.343 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=211 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:02:40.343 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=211 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:02:40.343 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=211 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:02:45.344 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.28.20:5700) Recv POWEROFF cmd
2026-01-29 02:02:45.344 [INFO] ctrl_if_trx.py:117 (BTS@172.18.28.20:5700) Stopping transceiver...
2026-01-29 02:02:45.346 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:02:45.346 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:02:45.346 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:02:45.347 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 02:02:45.349 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 02:02:45.350 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.28.20:5700) Recv SETFORMAT cmd
2026-01-29 02:02:45.350 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.28.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:02:45.350 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.28.20:5700) Recv SETFORMAT cmd
2026-01-29 02:02:45.350 [INFO] ctrl_if_trx.py:201 (BTS@172.18.28.20:5700) TRXD header version 1 -> 1
2026-01-29 02:02:45.350 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.28.20:5700/1) Recv RXTUNE cmd
2026-01-29 02:02:45.351 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.28.20:5700/1) Recv TXTUNE cmd
2026-01-29 02:02:45.351 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.28.20:5700/1) Recv SETFORMAT cmd
2026-01-29 02:02:45.351 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.28.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:02:45.351 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:02:45.351 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.28.20:5700/1) Recv NOMTXPOWER cmd
2026-01-29 02:02:45.351 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.28.20:5700/1) Recv SETFORMAT cmd
2026-01-29 02:02:45.351 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.28.20:5700/1) TRXD header version 1 -> 1
2026-01-29 02:02:45.352 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.28.20:5700/2) Recv RXTUNE cmd
2026-01-29 02:02:45.352 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.28.20:5700/2) Recv TXTUNE cmd
2026-01-29 02:02:45.352 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.28.20:5700/2) Recv SETFORMAT cmd
2026-01-29 02:02:45.352 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.28.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:02:45.352 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:02:45.352 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.28.20:5700/2) Recv NOMTXPOWER cmd
2026-01-29 02:02:45.352 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.28.20:5700/2) Recv SETFORMAT cmd
2026-01-29 02:02:45.352 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.28.20:5700/2) TRXD header version 1 -> 1
2026-01-29 02:02:45.353 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.28.20:5700/3) Recv RXTUNE cmd
2026-01-29 02:02:45.353 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.28.20:5700/3) Recv TXTUNE cmd
2026-01-29 02:02:45.353 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.28.20:5700/3) Recv SETFORMAT cmd
2026-01-29 02:02:45.353 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.28.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:02:45.353 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:02:45.353 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.28.20:5700/3) Recv NOMTXPOWER cmd
2026-01-29 02:02:45.353 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.28.20:5700/3) Recv SETFORMAT cmd
2026-01-29 02:02:45.353 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.28.20:5700/3) TRXD header version 1 -> 1
2026-01-29 02:02:45.354 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.28.20:5700) Recv RXTUNE cmd
2026-01-29 02:02:45.354 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETTSC
2026-01-29 02:02:45.354 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETTSC
2026-01-29 02:02:45.354 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETTSC
2026-01-29 02:02:45.354 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.28.20:5700) Recv TXTUNE cmd
2026-01-29 02:02:45.354 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETRXGAIN
2026-01-29 02:02:45.354 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETRXGAIN
2026-01-29 02:02:45.354 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETRXGAIN
2026-01-29 02:02:45.354 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETTSC
2026-01-29 02:02:45.354 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:02:45.354 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:02:45.354 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:02:45.354 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.28.20:5700) Recv NOMTXPOWER cmd
2026-01-29 02:02:45.355 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:02:45.355 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:02:45.355 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:02:45.355 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.28.20:5700) Recv POWERON CMD
2026-01-29 02:02:45.355 [INFO] ctrl_if_trx.py:109 (BTS@172.18.28.20:5700) Starting transceiver...
2026-01-29 02:02:45.355 [INFO] transceiver.py:243 Starting clock generator
2026-01-29 02:02:45.355 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-01-29 02:02:45.355 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:02:45.355 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:02:45.355 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:02:45.355 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETRXGAIN
2026-01-29 02:02:45.355 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:02:45.355 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:02:45.355 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:02:45.355 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:02:45.355 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:02:45.355 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:02:45.355 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:02:45.355 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:02:45.355 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:02:45.355 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:02:45.355 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:02:45.355 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:02:45.355 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:02:45.355 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:02:45.356 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:02:45.356 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:02:45.356 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:02:45.356 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:02:45.356 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:02:45.356 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:02:45.356 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:02:45.356 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:02:45.356 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:02:45.359 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-01-29 02:02:45.840 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-01-29 02:02:45.869 [DEBUG] fake_trx.py:278 (BTS@172.18.28.20:5700) Recv FAKE_TOA cmd
2026-01-29 02:02:45.870 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:02:45.870 [DEBUG] fake_trx.py:297 (BTS@172.18.28.20:5700) Recv FAKE_RSSI cmd
2026-01-29 02:02:45.871 [DEBUG] fake_trx.py:322 (BTS@172.18.28.20:5700) Recv FAKE_CI cmd
2026-01-29 02:02:45.877 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 02:02:45.877 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:02:45.877 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:02:45.877 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:02:45.880 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 02:02:45.880 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:02:45.880 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:02:45.880 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:02:45.880 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.28.20:5700) Recv POWEROFF cmd
2026-01-29 02:02:45.880 [INFO] ctrl_if_trx.py:117 (BTS@172.18.28.20:5700) Stopping transceiver...
2026-01-29 02:02:45.880 [INFO] transceiver.py:246 Stopping clock generator
2026-01-29 02:02:45.881 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=112 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:02:45.881 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=112 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:02:45.881 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=112 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:02:45.881 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=112 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:02:45.881 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=112 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:02:45.881 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=112 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:02:50.878 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.28.20:5700) Recv POWEROFF cmd
2026-01-29 02:02:50.878 [INFO] ctrl_if_trx.py:117 (BTS@172.18.28.20:5700) Stopping transceiver...
2026-01-29 02:02:50.878 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:02:50.878 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:02:50.879 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:02:50.879 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 02:02:50.884 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 02:02:50.884 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.28.20:5700) Recv SETFORMAT cmd
2026-01-29 02:02:50.884 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.28.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:02:50.884 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.28.20:5700) Recv SETFORMAT cmd
2026-01-29 02:02:50.885 [INFO] ctrl_if_trx.py:201 (BTS@172.18.28.20:5700) TRXD header version 1 -> 1
2026-01-29 02:02:50.885 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.28.20:5700/1) Recv RXTUNE cmd
2026-01-29 02:02:50.885 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.28.20:5700/1) Recv TXTUNE cmd
2026-01-29 02:02:50.885 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.28.20:5700/1) Recv SETFORMAT cmd
2026-01-29 02:02:50.885 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.28.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:02:50.885 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:02:50.886 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.28.20:5700/1) Recv NOMTXPOWER cmd
2026-01-29 02:02:50.886 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.28.20:5700/1) Recv SETFORMAT cmd
2026-01-29 02:02:50.886 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.28.20:5700/1) TRXD header version 1 -> 1
2026-01-29 02:02:50.886 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.28.20:5700/2) Recv RXTUNE cmd
2026-01-29 02:02:50.886 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.28.20:5700/2) Recv TXTUNE cmd
2026-01-29 02:02:50.886 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.28.20:5700/2) Recv SETFORMAT cmd
2026-01-29 02:02:50.886 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.28.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:02:50.886 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:02:50.886 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.28.20:5700/2) Recv NOMTXPOWER cmd
2026-01-29 02:02:50.886 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.28.20:5700/2) Recv SETFORMAT cmd
2026-01-29 02:02:50.886 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.28.20:5700/2) TRXD header version 1 -> 1
2026-01-29 02:02:50.887 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.28.20:5700/3) Recv RXTUNE cmd
2026-01-29 02:02:50.887 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.28.20:5700/3) Recv TXTUNE cmd
2026-01-29 02:02:50.887 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.28.20:5700/3) Recv SETFORMAT cmd
2026-01-29 02:02:50.887 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.28.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:02:50.887 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:02:50.887 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.28.20:5700/3) Recv NOMTXPOWER cmd
2026-01-29 02:02:50.887 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.28.20:5700/3) Recv SETFORMAT cmd
2026-01-29 02:02:50.887 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.28.20:5700/3) TRXD header version 1 -> 1
2026-01-29 02:02:50.888 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.28.20:5700) Recv RXTUNE cmd
2026-01-29 02:02:50.888 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETTSC
2026-01-29 02:02:50.888 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETTSC
2026-01-29 02:02:50.888 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETTSC
2026-01-29 02:02:50.888 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.28.20:5700) Recv TXTUNE cmd
2026-01-29 02:02:50.888 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETRXGAIN
2026-01-29 02:02:50.888 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETRXGAIN
2026-01-29 02:02:50.888 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETRXGAIN
2026-01-29 02:02:50.888 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETTSC
2026-01-29 02:02:50.888 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:02:50.888 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:02:50.888 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:02:50.888 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.28.20:5700) Recv NOMTXPOWER cmd
2026-01-29 02:02:50.888 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:02:50.888 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:02:50.888 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:02:50.888 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.28.20:5700) Recv POWERON CMD
2026-01-29 02:02:50.888 [INFO] ctrl_if_trx.py:109 (BTS@172.18.28.20:5700) Starting transceiver...
2026-01-29 02:02:50.889 [INFO] transceiver.py:243 Starting clock generator
2026-01-29 02:02:50.889 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-01-29 02:02:50.889 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:02:50.889 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:02:50.889 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:02:50.889 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETRXGAIN
2026-01-29 02:02:50.889 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:02:50.889 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:02:50.889 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:02:50.889 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:02:50.889 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:02:50.889 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:02:50.889 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:02:50.889 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:02:50.889 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:02:50.889 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:02:50.889 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:02:50.889 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:02:50.889 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:02:50.889 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:02:50.889 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:02:50.889 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:02:50.889 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:02:50.889 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:02:50.889 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:02:50.889 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:02:50.889 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:02:50.889 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:02:50.889 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:02:50.893 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-01-29 02:02:51.368 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-01-29 02:02:51.400 [DEBUG] fake_trx.py:278 (BTS@172.18.28.20:5700) Recv FAKE_TOA cmd
2026-01-29 02:02:51.400 [DEBUG] fake_trx.py:297 (BTS@172.18.28.20:5700) Recv FAKE_RSSI cmd
2026-01-29 02:02:51.401 [DEBUG] fake_trx.py:322 (BTS@172.18.28.20:5700) Recv FAKE_CI cmd
2026-01-29 02:02:51.401 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:02:51.836 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-01-29 02:02:51.890 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 02:02:51.891 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:02:51.891 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:02:51.892 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:02:52.307 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-01-29 02:02:52.781 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-01-29 02:02:52.891 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 02:02:52.891 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:02:52.892 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:02:52.894 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:02:53.257 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-01-29 02:02:53.419 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 02:02:53.419 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:02:53.419 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:02:53.419 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:02:53.420 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 02:02:53.420 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:02:53.420 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:02:53.420 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:02:53.420 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.28.20:5700) Recv POWEROFF cmd
2026-01-29 02:02:53.420 [INFO] ctrl_if_trx.py:117 (BTS@172.18.28.20:5700) Stopping transceiver...
2026-01-29 02:02:53.420 [INFO] transceiver.py:246 Stopping clock generator
2026-01-29 02:02:53.420 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=547 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:02:53.420 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=547 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:02:53.420 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=547 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:02:53.420 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=547 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:02:53.420 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=547 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:02:53.420 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=547 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:02:53.420 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=547 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:02:58.419 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.28.20:5700) Recv POWEROFF cmd
2026-01-29 02:02:58.419 [INFO] ctrl_if_trx.py:117 (BTS@172.18.28.20:5700) Stopping transceiver...
2026-01-29 02:02:58.419 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:02:58.419 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:02:58.419 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 02:02:58.419 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:02:58.422 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 02:02:58.422 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.28.20:5700) Recv SETFORMAT cmd
2026-01-29 02:02:58.422 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.28.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:02:58.422 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.28.20:5700) Recv SETFORMAT cmd
2026-01-29 02:02:58.422 [INFO] ctrl_if_trx.py:201 (BTS@172.18.28.20:5700) TRXD header version 1 -> 1
2026-01-29 02:02:58.424 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.28.20:5700/1) Recv RXTUNE cmd
2026-01-29 02:02:58.424 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.28.20:5700/1) Recv TXTUNE cmd
2026-01-29 02:02:58.424 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.28.20:5700/1) Recv SETFORMAT cmd
2026-01-29 02:02:58.424 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.28.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:02:58.424 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:02:58.424 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.28.20:5700/1) Recv NOMTXPOWER cmd
2026-01-29 02:02:58.424 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.28.20:5700/1) Recv SETFORMAT cmd
2026-01-29 02:02:58.424 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.28.20:5700/1) TRXD header version 1 -> 1
2026-01-29 02:02:58.425 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.28.20:5700/2) Recv RXTUNE cmd
2026-01-29 02:02:58.425 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.28.20:5700/2) Recv TXTUNE cmd
2026-01-29 02:02:58.425 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.28.20:5700/2) Recv SETFORMAT cmd
2026-01-29 02:02:58.425 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.28.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:02:58.425 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:02:58.425 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.28.20:5700/2) Recv NOMTXPOWER cmd
2026-01-29 02:02:58.425 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.28.20:5700/2) Recv SETFORMAT cmd
2026-01-29 02:02:58.425 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.28.20:5700/2) TRXD header version 1 -> 1
2026-01-29 02:02:58.426 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.28.20:5700/3) Recv RXTUNE cmd
2026-01-29 02:02:58.426 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.28.20:5700/3) Recv TXTUNE cmd
2026-01-29 02:02:58.426 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.28.20:5700/3) Recv SETFORMAT cmd
2026-01-29 02:02:58.426 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.28.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:02:58.426 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:02:58.426 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.28.20:5700/3) Recv NOMTXPOWER cmd
2026-01-29 02:02:58.426 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.28.20:5700/3) Recv SETFORMAT cmd
2026-01-29 02:02:58.426 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.28.20:5700/3) TRXD header version 1 -> 1
2026-01-29 02:02:58.428 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.28.20:5700) Recv RXTUNE cmd
2026-01-29 02:02:58.428 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETTSC
2026-01-29 02:02:58.428 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETTSC
2026-01-29 02:02:58.428 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETTSC
2026-01-29 02:02:58.428 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.28.20:5700) Recv TXTUNE cmd
2026-01-29 02:02:58.428 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETRXGAIN
2026-01-29 02:02:58.428 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETRXGAIN
2026-01-29 02:02:58.428 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETRXGAIN
2026-01-29 02:02:58.428 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETTSC
2026-01-29 02:02:58.428 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:02:58.428 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:02:58.428 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:02:58.428 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.28.20:5700) Recv NOMTXPOWER cmd
2026-01-29 02:02:58.428 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:02:58.428 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:02:58.428 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:02:58.428 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.28.20:5700) Recv POWERON CMD
2026-01-29 02:02:58.428 [INFO] ctrl_if_trx.py:109 (BTS@172.18.28.20:5700) Starting transceiver...
2026-01-29 02:02:58.428 [INFO] transceiver.py:243 Starting clock generator
2026-01-29 02:02:58.428 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-01-29 02:02:58.428 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:02:58.428 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:02:58.428 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:02:58.428 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETRXGAIN
2026-01-29 02:02:58.428 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:02:58.428 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:02:58.428 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:02:58.428 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:02:58.428 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:02:58.428 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:02:58.428 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:02:58.429 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:02:58.429 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:02:58.429 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:02:58.429 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:02:58.429 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:02:58.429 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:02:58.429 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:02:58.429 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:02:58.429 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:02:58.429 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:02:58.429 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:02:58.429 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:02:58.429 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:02:58.429 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:02:58.429 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:02:58.429 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:02:58.433 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-01-29 02:02:58.910 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-01-29 02:02:58.944 [DEBUG] fake_trx.py:278 (BTS@172.18.28.20:5700) Recv FAKE_TOA cmd
2026-01-29 02:02:58.944 [DEBUG] fake_trx.py:297 (BTS@172.18.28.20:5700) Recv FAKE_RSSI cmd
2026-01-29 02:02:58.945 [DEBUG] fake_trx.py:322 (BTS@172.18.28.20:5700) Recv FAKE_CI cmd
2026-01-29 02:02:58.945 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:02:58.946 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 02:02:58.946 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 02:02:58.946 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 02:02:58.946 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:02:58.946 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 02:02:58.946 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 02:02:58.946 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.28.22:6700) Recv POWERON CMD
2026-01-29 02:02:58.946 [INFO] ctrl_if_trx.py:109 (MS@172.18.28.22:6700) Starting transceiver...
2026-01-29 02:02:59.383 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-01-29 02:02:59.430 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 02:02:59.430 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:02:59.432 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:02:59.434 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:02:59.851 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-01-29 02:03:00.326 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-01-29 02:03:00.432 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:03:00.432 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 02:03:00.432 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:03:00.435 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:03:00.798 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-01-29 02:03:01.271 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-01-29 02:03:01.433 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 02:03:01.433 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:03:01.433 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:03:01.436 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:03:01.746 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-01-29 02:03:01.765 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 02:03:01.766 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 02:03:01.768 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 02:03:01.769 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:03:01.769 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:03:01.769 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:03:01.770 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 02:03:01.770 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:03:01.770 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:03:01.770 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.28.20:5700) Recv POWEROFF cmd
2026-01-29 02:03:01.770 [INFO] ctrl_if_trx.py:117 (BTS@172.18.28.20:5700) Stopping transceiver...
2026-01-29 02:03:01.770 [INFO] transceiver.py:246 Stopping clock generator
2026-01-29 02:03:01.770 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:03:01.770 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=721 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:03:01.770 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=721 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:03:01.770 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=721 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:03:01.770 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=721 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:03:01.770 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=721 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:03:01.770 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=721 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:03:01.770 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=721 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:03:01.770 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=721 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:03:06.772 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.28.20:5700) Recv POWEROFF cmd
2026-01-29 02:03:06.772 [INFO] ctrl_if_trx.py:117 (BTS@172.18.28.20:5700) Stopping transceiver...
2026-01-29 02:03:06.774 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:03:06.774 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:03:06.775 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:03:06.775 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 02:03:06.777 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 02:03:06.778 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.28.20:5700) Recv SETFORMAT cmd
2026-01-29 02:03:06.778 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.28.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:03:06.778 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.28.20:5700) Recv SETFORMAT cmd
2026-01-29 02:03:06.778 [INFO] ctrl_if_trx.py:201 (BTS@172.18.28.20:5700) TRXD header version 1 -> 1
2026-01-29 02:03:06.778 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.28.20:5700/1) Recv RXTUNE cmd
2026-01-29 02:03:06.779 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.28.20:5700/1) Recv TXTUNE cmd
2026-01-29 02:03:06.779 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.28.20:5700/1) Recv SETFORMAT cmd
2026-01-29 02:03:06.779 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.28.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:03:06.779 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:03:06.779 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.28.20:5700/1) Recv NOMTXPOWER cmd
2026-01-29 02:03:06.779 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.28.20:5700/1) Recv SETFORMAT cmd
2026-01-29 02:03:06.779 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.28.20:5700/1) TRXD header version 1 -> 1
2026-01-29 02:03:06.780 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.28.20:5700/2) Recv RXTUNE cmd
2026-01-29 02:03:06.780 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.28.20:5700/2) Recv TXTUNE cmd
2026-01-29 02:03:06.780 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.28.20:5700/2) Recv SETFORMAT cmd
2026-01-29 02:03:06.780 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.28.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:03:06.780 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:03:06.780 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.28.20:5700/2) Recv NOMTXPOWER cmd
2026-01-29 02:03:06.780 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.28.20:5700/2) Recv SETFORMAT cmd
2026-01-29 02:03:06.780 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.28.20:5700/2) TRXD header version 1 -> 1
2026-01-29 02:03:06.781 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.28.20:5700/3) Recv RXTUNE cmd
2026-01-29 02:03:06.781 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.28.20:5700/3) Recv TXTUNE cmd
2026-01-29 02:03:06.781 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.28.20:5700/3) Recv SETFORMAT cmd
2026-01-29 02:03:06.781 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.28.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:03:06.781 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:03:06.781 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.28.20:5700/3) Recv NOMTXPOWER cmd
2026-01-29 02:03:06.781 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.28.20:5700/3) Recv SETFORMAT cmd
2026-01-29 02:03:06.781 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.28.20:5700/3) TRXD header version 1 -> 1
2026-01-29 02:03:06.782 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.28.20:5700) Recv RXTUNE cmd
2026-01-29 02:03:06.782 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETTSC
2026-01-29 02:03:06.782 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETTSC
2026-01-29 02:03:06.782 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETTSC
2026-01-29 02:03:06.782 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.28.20:5700) Recv TXTUNE cmd
2026-01-29 02:03:06.782 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETRXGAIN
2026-01-29 02:03:06.782 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETRXGAIN
2026-01-29 02:03:06.782 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETRXGAIN
2026-01-29 02:03:06.782 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETTSC
2026-01-29 02:03:06.782 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:03:06.782 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:03:06.782 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.28.20:5700) Recv NOMTXPOWER cmd
2026-01-29 02:03:06.782 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:03:06.782 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:03:06.783 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:03:06.783 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.28.20:5700) Recv POWERON CMD
2026-01-29 02:03:06.783 [INFO] ctrl_if_trx.py:109 (BTS@172.18.28.20:5700) Starting transceiver...
2026-01-29 02:03:06.783 [INFO] transceiver.py:243 Starting clock generator
2026-01-29 02:03:06.783 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-01-29 02:03:06.783 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:03:06.783 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:03:06.783 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:03:06.783 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETRXGAIN
2026-01-29 02:03:06.783 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:03:06.783 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:03:06.783 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:03:06.783 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:03:06.783 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:03:06.783 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:03:06.783 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:03:06.783 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:03:06.783 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:03:06.783 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:03:06.783 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:03:06.783 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:03:06.783 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:03:06.783 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:03:06.783 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:03:06.783 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:03:06.783 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:03:06.783 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:03:06.783 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:03:06.783 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:03:06.783 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:03:06.783 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:03:06.783 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:03:06.783 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:03:06.787 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-01-29 02:03:07.265 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-01-29 02:03:07.310 [DEBUG] fake_trx.py:278 (BTS@172.18.28.20:5700) Recv FAKE_TOA cmd
2026-01-29 02:03:07.313 [DEBUG] fake_trx.py:297 (BTS@172.18.28.20:5700) Recv FAKE_RSSI cmd
2026-01-29 02:03:07.315 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:03:07.315 [DEBUG] fake_trx.py:322 (BTS@172.18.28.20:5700) Recv FAKE_CI cmd
2026-01-29 02:03:07.318 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 02:03:07.318 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 02:03:07.319 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 02:03:07.319 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:03:07.320 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 02:03:07.320 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 02:03:07.320 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.28.22:6700) Recv POWERON CMD
2026-01-29 02:03:07.320 [INFO] ctrl_if_trx.py:109 (MS@172.18.28.22:6700) Starting transceiver...
2026-01-29 02:03:07.739 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-01-29 02:03:07.785 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:03:07.786 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 02:03:07.805 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:03:07.806 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:03:08.214 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-01-29 02:03:08.687 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-01-29 02:03:08.787 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:03:08.806 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 02:03:08.806 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:03:08.806 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:03:09.158 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-01-29 02:03:09.411 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 02:03:09.411 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 02:03:09.417 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 02:03:09.417 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:03:09.417 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:03:09.417 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:03:09.418 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 02:03:09.418 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:03:09.418 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:03:09.418 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:03:09.419 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.28.20:5700) Recv POWEROFF cmd
2026-01-29 02:03:09.419 [INFO] ctrl_if_trx.py:117 (BTS@172.18.28.20:5700) Stopping transceiver...
2026-01-29 02:03:09.419 [INFO] transceiver.py:246 Stopping clock generator
2026-01-29 02:03:09.419 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=569 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:03:14.417 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.28.20:5700) Recv POWEROFF cmd
2026-01-29 02:03:14.417 [INFO] ctrl_if_trx.py:117 (BTS@172.18.28.20:5700) Stopping transceiver...
2026-01-29 02:03:14.417 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:03:14.418 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:03:14.418 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:03:14.419 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 02:03:14.423 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 02:03:14.424 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.28.20:5700) Recv SETFORMAT cmd
2026-01-29 02:03:14.424 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.28.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:03:14.424 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.28.20:5700) Recv SETFORMAT cmd
2026-01-29 02:03:14.424 [INFO] ctrl_if_trx.py:201 (BTS@172.18.28.20:5700) TRXD header version 1 -> 1
2026-01-29 02:03:14.425 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.28.20:5700/1) Recv RXTUNE cmd
2026-01-29 02:03:14.425 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.28.20:5700/1) Recv TXTUNE cmd
2026-01-29 02:03:14.426 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.28.20:5700/1) Recv SETFORMAT cmd
2026-01-29 02:03:14.426 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.28.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:03:14.426 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.28.20:5700/1) Recv NOMTXPOWER cmd
2026-01-29 02:03:14.426 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:03:14.426 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.28.20:5700/1) Recv SETFORMAT cmd
2026-01-29 02:03:14.426 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.28.20:5700/1) TRXD header version 1 -> 1
2026-01-29 02:03:14.427 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.28.20:5700/2) Recv RXTUNE cmd
2026-01-29 02:03:14.427 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.28.20:5700/2) Recv TXTUNE cmd
2026-01-29 02:03:14.427 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.28.20:5700/2) Recv SETFORMAT cmd
2026-01-29 02:03:14.427 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.28.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:03:14.427 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:03:14.427 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.28.20:5700/2) Recv NOMTXPOWER cmd
2026-01-29 02:03:14.427 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.28.20:5700/2) Recv SETFORMAT cmd
2026-01-29 02:03:14.427 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.28.20:5700/2) TRXD header version 1 -> 1
2026-01-29 02:03:14.428 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.28.20:5700/3) Recv RXTUNE cmd
2026-01-29 02:03:14.428 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.28.20:5700/3) Recv TXTUNE cmd
2026-01-29 02:03:14.428 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.28.20:5700/3) Recv SETFORMAT cmd
2026-01-29 02:03:14.428 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.28.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:03:14.428 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:03:14.428 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.28.20:5700/3) Recv NOMTXPOWER cmd
2026-01-29 02:03:14.428 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.28.20:5700/3) Recv SETFORMAT cmd
2026-01-29 02:03:14.428 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.28.20:5700/3) TRXD header version 1 -> 1
2026-01-29 02:03:14.430 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.28.20:5700) Recv RXTUNE cmd
2026-01-29 02:03:14.430 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETTSC
2026-01-29 02:03:14.430 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETTSC
2026-01-29 02:03:14.430 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETTSC
2026-01-29 02:03:14.430 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.28.20:5700) Recv TXTUNE cmd
2026-01-29 02:03:14.430 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETRXGAIN
2026-01-29 02:03:14.430 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETRXGAIN
2026-01-29 02:03:14.430 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETRXGAIN
2026-01-29 02:03:14.430 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETTSC
2026-01-29 02:03:14.430 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:03:14.430 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:03:14.430 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.28.20:5700) Recv NOMTXPOWER cmd
2026-01-29 02:03:14.430 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:03:14.430 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:03:14.430 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:03:14.430 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.28.20:5700) Recv POWERON CMD
2026-01-29 02:03:14.430 [INFO] ctrl_if_trx.py:109 (BTS@172.18.28.20:5700) Starting transceiver...
2026-01-29 02:03:14.430 [INFO] transceiver.py:243 Starting clock generator
2026-01-29 02:03:14.430 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-01-29 02:03:14.430 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:03:14.430 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:03:14.430 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:03:14.430 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETRXGAIN
2026-01-29 02:03:14.430 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:03:14.430 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:03:14.430 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:03:14.431 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:03:14.431 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:03:14.431 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:03:14.431 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:03:14.431 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:03:14.431 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:03:14.431 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:03:14.431 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:03:14.431 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:03:14.431 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:03:14.431 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:03:14.431 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:03:14.431 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:03:14.431 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:03:14.431 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:03:14.431 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:03:14.431 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:03:14.431 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:03:14.431 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:03:14.431 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:03:14.431 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:03:14.435 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-01-29 02:03:14.918 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-01-29 02:03:14.949 [DEBUG] fake_trx.py:278 (BTS@172.18.28.20:5700) Recv FAKE_TOA cmd
2026-01-29 02:03:14.950 [DEBUG] fake_trx.py:297 (BTS@172.18.28.20:5700) Recv FAKE_RSSI cmd
2026-01-29 02:03:14.951 [DEBUG] fake_trx.py:322 (BTS@172.18.28.20:5700) Recv FAKE_CI cmd
2026-01-29 02:03:14.951 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:03:14.955 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 02:03:14.955 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 02:03:14.955 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 02:03:14.956 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:03:14.956 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 02:03:14.956 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 02:03:14.956 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.28.22:6700) Recv POWERON CMD
2026-01-29 02:03:14.956 [INFO] ctrl_if_trx.py:109 (MS@172.18.28.22:6700) Starting transceiver...
2026-01-29 02:03:15.395 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-01-29 02:03:15.432 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 02:03:15.433 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:03:15.433 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:03:15.436 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:03:15.873 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-01-29 02:03:16.351 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-01-29 02:03:16.434 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 02:03:16.434 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:03:16.435 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:03:16.438 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:03:16.829 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-01-29 02:03:17.306 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-01-29 02:03:17.435 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 02:03:17.435 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:03:17.435 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:03:17.439 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:03:17.784 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-01-29 02:03:17.803 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 02:03:17.803 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 02:03:17.812 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 02:03:17.813 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:03:17.813 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:03:17.813 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:03:17.816 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 02:03:17.816 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:03:17.816 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:03:17.817 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:03:17.817 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.28.20:5700) Recv POWEROFF cmd
2026-01-29 02:03:17.817 [INFO] ctrl_if_trx.py:117 (BTS@172.18.28.20:5700) Stopping transceiver...
2026-01-29 02:03:17.817 [INFO] transceiver.py:246 Stopping clock generator
2026-01-29 02:03:17.817 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=721 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:03:17.817 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=721 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:03:17.817 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=721 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:03:17.817 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=721 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:03:17.817 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=722 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:03:17.817 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=722 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:03:22.816 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.28.20:5700) Recv POWEROFF cmd
2026-01-29 02:03:22.816 [INFO] ctrl_if_trx.py:117 (BTS@172.18.28.20:5700) Stopping transceiver...
2026-01-29 02:03:22.818 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:03:22.818 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:03:22.818 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:03:22.819 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 02:03:22.828 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 02:03:22.830 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.28.20:5700) Recv SETFORMAT cmd
2026-01-29 02:03:22.830 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.28.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:03:22.831 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.28.20:5700) Recv SETFORMAT cmd
2026-01-29 02:03:22.831 [INFO] ctrl_if_trx.py:201 (BTS@172.18.28.20:5700) TRXD header version 1 -> 1
2026-01-29 02:03:22.835 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.28.20:5700/1) Recv RXTUNE cmd
2026-01-29 02:03:22.835 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.28.20:5700/1) Recv TXTUNE cmd
2026-01-29 02:03:22.836 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.28.20:5700/1) Recv SETFORMAT cmd
2026-01-29 02:03:22.836 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.28.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:03:22.836 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:03:22.836 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.28.20:5700/1) Recv NOMTXPOWER cmd
2026-01-29 02:03:22.836 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.28.20:5700/1) Recv SETFORMAT cmd
2026-01-29 02:03:22.836 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.28.20:5700/1) TRXD header version 1 -> 1
2026-01-29 02:03:22.840 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.28.20:5700/2) Recv RXTUNE cmd
2026-01-29 02:03:22.840 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.28.20:5700/2) Recv TXTUNE cmd
2026-01-29 02:03:22.841 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.28.20:5700/2) Recv SETFORMAT cmd
2026-01-29 02:03:22.841 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.28.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:03:22.841 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:03:22.841 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.28.20:5700/2) Recv NOMTXPOWER cmd
2026-01-29 02:03:22.841 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.28.20:5700/2) Recv SETFORMAT cmd
2026-01-29 02:03:22.841 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.28.20:5700/2) TRXD header version 1 -> 1
2026-01-29 02:03:22.844 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.28.20:5700/3) Recv RXTUNE cmd
2026-01-29 02:03:22.844 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.28.20:5700/3) Recv TXTUNE cmd
2026-01-29 02:03:22.844 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.28.20:5700/3) Recv SETFORMAT cmd
2026-01-29 02:03:22.844 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.28.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:03:22.844 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.28.20:5700/3) Recv NOMTXPOWER cmd
2026-01-29 02:03:22.844 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:03:22.844 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.28.20:5700/3) Recv SETFORMAT cmd
2026-01-29 02:03:22.844 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.28.20:5700/3) TRXD header version 1 -> 1
2026-01-29 02:03:22.848 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.28.20:5700) Recv RXTUNE cmd
2026-01-29 02:03:22.848 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETTSC
2026-01-29 02:03:22.848 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETTSC
2026-01-29 02:03:22.848 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETTSC
2026-01-29 02:03:22.848 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.28.20:5700) Recv TXTUNE cmd
2026-01-29 02:03:22.848 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETRXGAIN
2026-01-29 02:03:22.848 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETRXGAIN
2026-01-29 02:03:22.848 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETRXGAIN
2026-01-29 02:03:22.848 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETTSC
2026-01-29 02:03:22.848 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:03:22.848 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:03:22.848 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.28.20:5700) Recv NOMTXPOWER cmd
2026-01-29 02:03:22.848 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:03:22.848 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:03:22.848 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:03:22.848 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.28.20:5700) Recv POWERON CMD
2026-01-29 02:03:22.848 [INFO] ctrl_if_trx.py:109 (BTS@172.18.28.20:5700) Starting transceiver...
2026-01-29 02:03:22.849 [INFO] transceiver.py:243 Starting clock generator
2026-01-29 02:03:22.849 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-01-29 02:03:22.849 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:03:22.849 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:03:22.849 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:03:22.849 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETRXGAIN
2026-01-29 02:03:22.849 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:03:22.849 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:03:22.849 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:03:22.850 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:03:22.850 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:03:22.850 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:03:22.850 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:03:22.850 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:03:22.850 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:03:22.850 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:03:22.850 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:03:22.850 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:03:22.850 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:03:22.850 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:03:22.850 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:03:22.850 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:03:22.850 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:03:22.850 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:03:22.851 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:03:22.851 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:03:22.851 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:03:22.851 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:03:22.851 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:03:22.851 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:03:22.853 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-01-29 02:03:23.337 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-01-29 02:03:23.368 [DEBUG] fake_trx.py:278 (BTS@172.18.28.20:5700) Recv FAKE_TOA cmd
2026-01-29 02:03:23.368 [DEBUG] fake_trx.py:297 (BTS@172.18.28.20:5700) Recv FAKE_RSSI cmd
2026-01-29 02:03:23.369 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:03:23.369 [DEBUG] fake_trx.py:322 (BTS@172.18.28.20:5700) Recv FAKE_CI cmd
2026-01-29 02:03:23.370 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 02:03:23.370 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 02:03:23.370 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 02:03:23.370 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:03:23.370 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 02:03:23.370 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 02:03:23.370 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.28.22:6700) Recv POWERON CMD
2026-01-29 02:03:23.370 [INFO] ctrl_if_trx.py:109 (MS@172.18.28.22:6700) Starting transceiver...
2026-01-29 02:03:23.806 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-01-29 02:03:23.852 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 02:03:23.854 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:03:23.855 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:03:23.859 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:03:24.283 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-01-29 02:03:24.761 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-01-29 02:03:24.853 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 02:03:24.856 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:03:24.856 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:03:24.860 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:03:25.238 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-01-29 02:03:25.492 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 02:03:25.493 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 02:03:25.496 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 02:03:25.496 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:03:25.496 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:03:25.496 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:03:25.496 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 02:03:25.496 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:03:25.496 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:03:25.496 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.28.20:5700) Recv POWEROFF cmd
2026-01-29 02:03:25.496 [INFO] ctrl_if_trx.py:117 (BTS@172.18.28.20:5700) Stopping transceiver...
2026-01-29 02:03:25.496 [INFO] transceiver.py:246 Stopping clock generator
2026-01-29 02:03:25.496 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:03:25.496 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=568 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:03:25.496 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=568 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:03:30.502 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.28.20:5700) Recv POWEROFF cmd
2026-01-29 02:03:30.502 [INFO] ctrl_if_trx.py:117 (BTS@172.18.28.20:5700) Stopping transceiver...
2026-01-29 02:03:30.502 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:03:30.502 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:03:30.502 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 02:03:30.502 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:03:30.511 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 02:03:30.513 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.28.20:5700) Recv SETFORMAT cmd
2026-01-29 02:03:30.513 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.28.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:03:30.513 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.28.20:5700) Recv SETFORMAT cmd
2026-01-29 02:03:30.514 [INFO] ctrl_if_trx.py:201 (BTS@172.18.28.20:5700) TRXD header version 1 -> 1
2026-01-29 02:03:30.517 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.28.20:5700/1) Recv RXTUNE cmd
2026-01-29 02:03:30.518 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.28.20:5700/1) Recv TXTUNE cmd
2026-01-29 02:03:30.518 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.28.20:5700/1) Recv SETFORMAT cmd
2026-01-29 02:03:30.518 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.28.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:03:30.518 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:03:30.519 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.28.20:5700/1) Recv NOMTXPOWER cmd
2026-01-29 02:03:30.519 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.28.20:5700/1) Recv SETFORMAT cmd
2026-01-29 02:03:30.519 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.28.20:5700/1) TRXD header version 1 -> 1
2026-01-29 02:03:30.522 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.28.20:5700/2) Recv RXTUNE cmd
2026-01-29 02:03:30.522 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.28.20:5700/2) Recv TXTUNE cmd
2026-01-29 02:03:30.522 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.28.20:5700/2) Recv SETFORMAT cmd
2026-01-29 02:03:30.523 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.28.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:03:30.523 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:03:30.523 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.28.20:5700/2) Recv NOMTXPOWER cmd
2026-01-29 02:03:30.524 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.28.20:5700/2) Recv SETFORMAT cmd
2026-01-29 02:03:30.524 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.28.20:5700/2) TRXD header version 1 -> 1
2026-01-29 02:03:30.525 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.28.20:5700/3) Recv RXTUNE cmd
2026-01-29 02:03:30.525 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.28.20:5700/3) Recv TXTUNE cmd
2026-01-29 02:03:30.525 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.28.20:5700/3) Recv SETFORMAT cmd
2026-01-29 02:03:30.525 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.28.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:03:30.525 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:03:30.525 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.28.20:5700/3) Recv NOMTXPOWER cmd
2026-01-29 02:03:30.525 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.28.20:5700/3) Recv SETFORMAT cmd
2026-01-29 02:03:30.526 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.28.20:5700/3) TRXD header version 1 -> 1
2026-01-29 02:03:30.529 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.28.20:5700) Recv RXTUNE cmd
2026-01-29 02:03:30.529 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETTSC
2026-01-29 02:03:30.529 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETTSC
2026-01-29 02:03:30.529 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETTSC
2026-01-29 02:03:30.529 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.28.20:5700) Recv TXTUNE cmd
2026-01-29 02:03:30.529 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETRXGAIN
2026-01-29 02:03:30.529 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETRXGAIN
2026-01-29 02:03:30.529 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETTSC
2026-01-29 02:03:30.530 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:03:30.530 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETRXGAIN
2026-01-29 02:03:30.530 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.28.20:5700) Recv NOMTXPOWER cmd
2026-01-29 02:03:30.530 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:03:30.530 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:03:30.530 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.28.20:5700) Recv POWERON CMD
2026-01-29 02:03:30.530 [INFO] ctrl_if_trx.py:109 (BTS@172.18.28.20:5700) Starting transceiver...
2026-01-29 02:03:30.530 [INFO] transceiver.py:243 Starting clock generator
2026-01-29 02:03:30.530 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-01-29 02:03:30.530 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:03:30.530 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:03:30.531 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:03:30.531 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETRXGAIN
2026-01-29 02:03:30.531 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:03:30.531 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:03:30.531 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:03:30.531 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:03:30.531 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:03:30.531 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:03:30.531 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:03:30.531 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:03:30.531 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:03:30.531 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:03:30.531 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:03:30.531 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:03:30.531 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:03:30.531 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:03:30.531 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:03:30.531 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:03:30.531 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:03:30.531 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:03:30.531 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:03:30.531 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:03:30.531 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:03:30.531 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:03:30.531 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:03:30.532 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:03:30.532 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:03:30.532 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:03:30.535 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-01-29 02:03:31.018 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-01-29 02:03:31.055 [DEBUG] fake_trx.py:278 (BTS@172.18.28.20:5700) Recv FAKE_TOA cmd
2026-01-29 02:03:31.057 [DEBUG] fake_trx.py:297 (BTS@172.18.28.20:5700) Recv FAKE_RSSI cmd
2026-01-29 02:03:31.058 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:03:31.059 [DEBUG] fake_trx.py:322 (BTS@172.18.28.20:5700) Recv FAKE_CI cmd
2026-01-29 02:03:31.067 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 02:03:31.067 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 02:03:31.068 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 02:03:31.068 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:03:31.069 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 02:03:31.069 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 02:03:31.069 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.28.22:6700) Recv POWERON CMD
2026-01-29 02:03:31.069 [INFO] ctrl_if_trx.py:109 (MS@172.18.28.22:6700) Starting transceiver...
2026-01-29 02:03:31.495 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-01-29 02:03:31.533 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 02:03:31.533 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:03:31.536 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:03:31.538 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:03:31.973 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-01-29 02:03:32.451 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-01-29 02:03:32.534 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 02:03:32.534 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:03:32.537 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:03:32.538 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:03:32.928 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-01-29 02:03:33.405 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-01-29 02:03:33.535 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 02:03:33.535 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:03:33.538 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:03:33.539 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:03:33.883 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-01-29 02:03:34.360 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-01-29 02:03:34.536 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 02:03:34.536 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:03:34.540 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:03:34.540 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:03:34.838 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-01-29 02:03:34.857 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 02:03:34.857 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 02:03:34.867 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 02:03:34.867 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:03:34.867 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:03:34.868 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:03:34.869 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 02:03:34.869 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:03:34.869 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:03:34.869 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:03:34.869 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.28.20:5700) Recv POWEROFF cmd
2026-01-29 02:03:34.869 [INFO] ctrl_if_trx.py:117 (BTS@172.18.28.20:5700) Stopping transceiver...
2026-01-29 02:03:34.870 [INFO] transceiver.py:246 Stopping clock generator
2026-01-29 02:03:39.868 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.28.20:5700) Recv POWEROFF cmd
2026-01-29 02:03:39.869 [INFO] ctrl_if_trx.py:117 (BTS@172.18.28.20:5700) Stopping transceiver...
2026-01-29 02:03:39.870 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:03:39.872 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:03:39.872 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:03:39.872 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 02:03:39.881 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 02:03:39.881 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.28.20:5700) Recv SETFORMAT cmd
2026-01-29 02:03:39.881 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.28.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:03:39.881 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.28.20:5700) Recv SETFORMAT cmd
2026-01-29 02:03:39.881 [INFO] ctrl_if_trx.py:201 (BTS@172.18.28.20:5700) TRXD header version 1 -> 1
2026-01-29 02:03:39.883 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.28.20:5700/1) Recv RXTUNE cmd
2026-01-29 02:03:39.883 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.28.20:5700/1) Recv TXTUNE cmd
2026-01-29 02:03:39.884 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.28.20:5700/1) Recv SETFORMAT cmd
2026-01-29 02:03:39.884 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.28.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:03:39.884 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:03:39.884 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.28.20:5700/1) Recv NOMTXPOWER cmd
2026-01-29 02:03:39.884 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.28.20:5700/1) Recv SETFORMAT cmd
2026-01-29 02:03:39.885 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.28.20:5700/1) TRXD header version 1 -> 1
2026-01-29 02:03:39.886 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.28.20:5700/2) Recv RXTUNE cmd
2026-01-29 02:03:39.886 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.28.20:5700/2) Recv TXTUNE cmd
2026-01-29 02:03:39.886 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.28.20:5700/2) Recv SETFORMAT cmd
2026-01-29 02:03:39.886 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.28.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:03:39.886 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:03:39.886 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.28.20:5700/2) Recv NOMTXPOWER cmd
2026-01-29 02:03:39.887 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.28.20:5700/2) Recv SETFORMAT cmd
2026-01-29 02:03:39.887 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.28.20:5700/2) TRXD header version 1 -> 1
2026-01-29 02:03:39.889 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.28.20:5700/3) Recv RXTUNE cmd
2026-01-29 02:03:39.889 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.28.20:5700/3) Recv TXTUNE cmd
2026-01-29 02:03:39.889 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.28.20:5700/3) Recv SETFORMAT cmd
2026-01-29 02:03:39.889 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.28.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:03:39.889 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:03:39.890 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.28.20:5700/3) Recv NOMTXPOWER cmd
2026-01-29 02:03:39.890 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.28.20:5700/3) Recv SETFORMAT cmd
2026-01-29 02:03:39.890 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.28.20:5700/3) TRXD header version 1 -> 1
2026-01-29 02:03:39.892 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.28.20:5700) Recv RXTUNE cmd
2026-01-29 02:03:39.892 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETTSC
2026-01-29 02:03:39.892 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETTSC
2026-01-29 02:03:39.892 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETTSC
2026-01-29 02:03:39.892 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.28.20:5700) Recv TXTUNE cmd
2026-01-29 02:03:39.892 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETRXGAIN
2026-01-29 02:03:39.892 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETRXGAIN
2026-01-29 02:03:39.893 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETRXGAIN
2026-01-29 02:03:39.893 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETTSC
2026-01-29 02:03:39.893 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:03:39.893 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:03:39.893 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:03:39.893 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.28.20:5700) Recv NOMTXPOWER cmd
2026-01-29 02:03:39.893 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:03:39.893 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:03:39.893 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:03:39.893 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.28.20:5700) Recv POWERON CMD
2026-01-29 02:03:39.893 [INFO] ctrl_if_trx.py:109 (BTS@172.18.28.20:5700) Starting transceiver...
2026-01-29 02:03:39.893 [INFO] transceiver.py:243 Starting clock generator
2026-01-29 02:03:39.893 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-01-29 02:03:39.893 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:03:39.893 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:03:39.893 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:03:39.894 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETRXGAIN
2026-01-29 02:03:39.894 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:03:39.894 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:03:39.894 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:03:39.894 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:03:39.894 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:03:39.894 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:03:39.894 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:03:39.894 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:03:39.894 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:03:39.894 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:03:39.894 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:03:39.894 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:03:39.894 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:03:39.894 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:03:39.894 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:03:39.894 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:03:39.894 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:03:39.894 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:03:39.894 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:03:39.894 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:03:39.894 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:03:39.895 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:03:39.895 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:03:39.898 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-01-29 02:03:40.381 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-01-29 02:03:40.416 [DEBUG] fake_trx.py:278 (BTS@172.18.28.20:5700) Recv FAKE_TOA cmd
2026-01-29 02:03:40.417 [DEBUG] fake_trx.py:297 (BTS@172.18.28.20:5700) Recv FAKE_RSSI cmd
2026-01-29 02:03:40.419 [DEBUG] fake_trx.py:322 (BTS@172.18.28.20:5700) Recv FAKE_CI cmd
2026-01-29 02:03:40.420 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:03:40.424 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 02:03:40.424 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 02:03:40.425 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 02:03:40.425 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:03:40.425 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 02:03:40.426 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 02:03:40.426 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.28.22:6700) Recv POWERON CMD
2026-01-29 02:03:40.426 [INFO] ctrl_if_trx.py:109 (MS@172.18.28.22:6700) Starting transceiver...
2026-01-29 02:03:40.858 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-01-29 02:03:40.896 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 02:03:40.896 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:03:40.897 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:03:40.901 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:03:41.335 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-01-29 02:03:41.813 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-01-29 02:03:41.897 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 02:03:41.897 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:03:41.898 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:03:41.901 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:03:42.290 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-01-29 02:03:42.768 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-01-29 02:03:42.897 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 02:03:42.898 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:03:42.898 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:03:42.902 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:03:43.246 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-01-29 02:03:43.500 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 02:03:43.500 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 02:03:43.507 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 02:03:43.507 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:03:43.507 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:03:43.507 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:03:43.508 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 02:03:43.508 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:03:43.508 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:03:43.508 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:03:43.508 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.28.20:5700) Recv POWEROFF cmd
2026-01-29 02:03:43.508 [INFO] ctrl_if_trx.py:117 (BTS@172.18.28.20:5700) Stopping transceiver...
2026-01-29 02:03:43.508 [INFO] transceiver.py:246 Stopping clock generator
2026-01-29 02:03:43.508 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=772 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:03:43.508 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=772 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:03:43.508 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=772 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:03:43.509 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=772 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:03:43.509 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=772 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:03:43.509 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=772 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:03:43.509 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=772 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:03:43.509 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=772 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:03:48.512 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.28.20:5700) Recv POWEROFF cmd
2026-01-29 02:03:48.512 [INFO] ctrl_if_trx.py:117 (BTS@172.18.28.20:5700) Stopping transceiver...
2026-01-29 02:03:48.515 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:03:48.516 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:03:48.516 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:03:48.516 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 02:03:48.519 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 02:03:48.519 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.28.20:5700) Recv SETFORMAT cmd
2026-01-29 02:03:48.519 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.28.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:03:48.519 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.28.20:5700) Recv SETFORMAT cmd
2026-01-29 02:03:48.519 [INFO] ctrl_if_trx.py:201 (BTS@172.18.28.20:5700) TRXD header version 1 -> 1
2026-01-29 02:03:48.521 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.28.20:5700/1) Recv RXTUNE cmd
2026-01-29 02:03:48.521 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.28.20:5700/1) Recv TXTUNE cmd
2026-01-29 02:03:48.521 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.28.20:5700/1) Recv SETFORMAT cmd
2026-01-29 02:03:48.522 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.28.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:03:48.522 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:03:48.522 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.28.20:5700/1) Recv NOMTXPOWER cmd
2026-01-29 02:03:48.522 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.28.20:5700/1) Recv SETFORMAT cmd
2026-01-29 02:03:48.522 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.28.20:5700/1) TRXD header version 1 -> 1
2026-01-29 02:03:48.523 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.28.20:5700/2) Recv RXTUNE cmd
2026-01-29 02:03:48.523 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.28.20:5700/2) Recv TXTUNE cmd
2026-01-29 02:03:48.523 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.28.20:5700/2) Recv SETFORMAT cmd
2026-01-29 02:03:48.523 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.28.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:03:48.523 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:03:48.523 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.28.20:5700/2) Recv NOMTXPOWER cmd
2026-01-29 02:03:48.523 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.28.20:5700/2) Recv SETFORMAT cmd
2026-01-29 02:03:48.523 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.28.20:5700/2) TRXD header version 1 -> 1
2026-01-29 02:03:48.525 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.28.20:5700/3) Recv RXTUNE cmd
2026-01-29 02:03:48.525 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.28.20:5700/3) Recv TXTUNE cmd
2026-01-29 02:03:48.525 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.28.20:5700/3) Recv SETFORMAT cmd
2026-01-29 02:03:48.525 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.28.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:03:48.525 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:03:48.525 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.28.20:5700/3) Recv NOMTXPOWER cmd
2026-01-29 02:03:48.526 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.28.20:5700/3) Recv SETFORMAT cmd
2026-01-29 02:03:48.526 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.28.20:5700/3) TRXD header version 1 -> 1
2026-01-29 02:03:48.527 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.28.20:5700) Recv RXTUNE cmd
2026-01-29 02:03:48.527 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETTSC
2026-01-29 02:03:48.527 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETTSC
2026-01-29 02:03:48.527 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETTSC
2026-01-29 02:03:48.528 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.28.20:5700) Recv TXTUNE cmd
2026-01-29 02:03:48.528 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETRXGAIN
2026-01-29 02:03:48.528 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETRXGAIN
2026-01-29 02:03:48.528 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETRXGAIN
2026-01-29 02:03:48.528 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETTSC
2026-01-29 02:03:48.528 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:03:48.528 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:03:48.528 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:03:48.528 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.28.20:5700) Recv NOMTXPOWER cmd
2026-01-29 02:03:48.528 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:03:48.528 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:03:48.528 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:03:48.528 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.28.20:5700) Recv POWERON CMD
2026-01-29 02:03:48.528 [INFO] ctrl_if_trx.py:109 (BTS@172.18.28.20:5700) Starting transceiver...
2026-01-29 02:03:48.528 [INFO] transceiver.py:243 Starting clock generator
2026-01-29 02:03:48.528 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-01-29 02:03:48.528 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:03:48.528 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:03:48.528 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:03:48.529 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETRXGAIN
2026-01-29 02:03:48.529 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:03:48.529 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:03:48.529 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:03:48.529 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:03:48.529 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:03:48.529 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:03:48.529 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:03:48.529 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:03:48.529 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:03:48.529 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:03:48.529 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:03:48.529 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:03:48.529 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:03:48.529 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:03:48.529 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:03:48.529 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:03:48.529 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:03:48.529 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:03:48.529 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:03:48.529 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:03:48.529 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:03:48.529 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:03:48.529 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:03:48.533 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-01-29 02:03:49.017 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-01-29 02:03:49.053 [DEBUG] fake_trx.py:278 (BTS@172.18.28.20:5700) Recv FAKE_TOA cmd
2026-01-29 02:03:49.055 [DEBUG] fake_trx.py:297 (BTS@172.18.28.20:5700) Recv FAKE_RSSI cmd
2026-01-29 02:03:49.057 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:03:49.057 [DEBUG] fake_trx.py:322 (BTS@172.18.28.20:5700) Recv FAKE_CI cmd
2026-01-29 02:03:49.495 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-01-29 02:03:49.531 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:03:49.532 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 02:03:49.532 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:03:49.534 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:03:49.973 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-01-29 02:03:50.460 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-01-29 02:03:50.533 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:03:50.533 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 02:03:50.533 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:03:50.535 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:03:50.942 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-01-29 02:03:51.072 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 02:03:51.072 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:03:51.072 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:03:51.072 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:03:51.073 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 02:03:51.073 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:03:51.073 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:03:51.073 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.28.20:5700) Recv POWEROFF cmd
2026-01-29 02:03:51.073 [INFO] ctrl_if_trx.py:117 (BTS@172.18.28.20:5700) Stopping transceiver...
2026-01-29 02:03:51.073 [INFO] transceiver.py:246 Stopping clock generator
2026-01-29 02:03:51.073 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:03:56.075 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.28.20:5700) Recv POWEROFF cmd
2026-01-29 02:03:56.075 [INFO] ctrl_if_trx.py:117 (BTS@172.18.28.20:5700) Stopping transceiver...
2026-01-29 02:03:56.077 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:03:56.078 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:03:56.079 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:03:56.079 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 02:03:56.088 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 02:03:56.089 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.28.20:5700) Recv SETFORMAT cmd
2026-01-29 02:03:56.089 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.28.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:03:56.090 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.28.20:5700) Recv SETFORMAT cmd
2026-01-29 02:03:56.090 [INFO] ctrl_if_trx.py:201 (BTS@172.18.28.20:5700) TRXD header version 1 -> 1
2026-01-29 02:03:56.094 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.28.20:5700/1) Recv RXTUNE cmd
2026-01-29 02:03:56.094 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.28.20:5700/1) Recv TXTUNE cmd
2026-01-29 02:03:56.095 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.28.20:5700/1) Recv SETFORMAT cmd
2026-01-29 02:03:56.095 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.28.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:03:56.095 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:03:56.096 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.28.20:5700/1) Recv NOMTXPOWER cmd
2026-01-29 02:03:56.096 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.28.20:5700/1) Recv SETFORMAT cmd
2026-01-29 02:03:56.096 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.28.20:5700/1) TRXD header version 1 -> 1
2026-01-29 02:03:56.097 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.28.20:5700/2) Recv RXTUNE cmd
2026-01-29 02:03:56.098 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.28.20:5700/2) Recv TXTUNE cmd
2026-01-29 02:03:56.098 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.28.20:5700/2) Recv SETFORMAT cmd
2026-01-29 02:03:56.098 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.28.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:03:56.098 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:03:56.098 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.28.20:5700/2) Recv NOMTXPOWER cmd
2026-01-29 02:03:56.098 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.28.20:5700/2) Recv SETFORMAT cmd
2026-01-29 02:03:56.098 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.28.20:5700/2) TRXD header version 1 -> 1
2026-01-29 02:03:56.100 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.28.20:5700/3) Recv RXTUNE cmd
2026-01-29 02:03:56.100 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.28.20:5700/3) Recv TXTUNE cmd
2026-01-29 02:03:56.100 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.28.20:5700/3) Recv SETFORMAT cmd
2026-01-29 02:03:56.100 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.28.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:03:56.100 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:03:56.100 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.28.20:5700/3) Recv NOMTXPOWER cmd
2026-01-29 02:03:56.100 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.28.20:5700/3) Recv SETFORMAT cmd
2026-01-29 02:03:56.100 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.28.20:5700/3) TRXD header version 1 -> 1
2026-01-29 02:03:56.103 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.28.20:5700) Recv RXTUNE cmd
2026-01-29 02:03:56.103 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETTSC
2026-01-29 02:03:56.103 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETTSC
2026-01-29 02:03:56.103 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETTSC
2026-01-29 02:03:56.103 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.28.20:5700) Recv TXTUNE cmd
2026-01-29 02:03:56.103 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETRXGAIN
2026-01-29 02:03:56.103 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETRXGAIN
2026-01-29 02:03:56.103 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETRXGAIN
2026-01-29 02:03:56.103 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETTSC
2026-01-29 02:03:56.103 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:03:56.103 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:03:56.103 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:03:56.103 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.28.20:5700) Recv NOMTXPOWER cmd
2026-01-29 02:03:56.103 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:03:56.104 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:03:56.104 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:03:56.104 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.28.20:5700) Recv POWERON CMD
2026-01-29 02:03:56.104 [INFO] ctrl_if_trx.py:109 (BTS@172.18.28.20:5700) Starting transceiver...
2026-01-29 02:03:56.104 [INFO] transceiver.py:243 Starting clock generator
2026-01-29 02:03:56.104 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-01-29 02:03:56.104 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:03:56.104 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:03:56.104 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:03:56.104 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETRXGAIN
2026-01-29 02:03:56.104 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:03:56.104 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:03:56.104 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:03:56.104 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:03:56.104 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:03:56.104 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:03:56.104 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:03:56.104 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:03:56.104 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:03:56.104 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:03:56.105 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:03:56.105 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:03:56.105 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:03:56.105 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:03:56.105 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:03:56.105 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:03:56.105 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:03:56.105 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:03:56.105 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:03:56.105 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:03:56.105 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:03:56.105 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:03:56.105 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:03:56.108 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-01-29 02:03:56.591 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-01-29 02:03:56.631 [DEBUG] fake_trx.py:278 (BTS@172.18.28.20:5700) Recv FAKE_TOA cmd
2026-01-29 02:03:56.632 [DEBUG] fake_trx.py:297 (BTS@172.18.28.20:5700) Recv FAKE_RSSI cmd
2026-01-29 02:03:56.634 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:03:56.634 [DEBUG] fake_trx.py:322 (BTS@172.18.28.20:5700) Recv FAKE_CI cmd
2026-01-29 02:03:56.655 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 02:03:56.655 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 02:03:56.655 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 02:03:56.667 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:03:56.670 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:03:57.060 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-01-29 02:03:57.107 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:03:57.107 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 02:03:57.107 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:03:57.107 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:03:57.529 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-01-29 02:03:58.007 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-01-29 02:03:58.108 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 02:03:58.108 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:03:58.108 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:03:58.108 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:03:58.489 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-01-29 02:03:58.969 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-01-29 02:03:59.109 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:03:59.109 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 02:03:59.109 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:03:59.109 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:03:59.450 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-01-29 02:03:59.680 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:03:59.692 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 02:03:59.693 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:03:59.693 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:03:59.693 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:03:59.694 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 02:03:59.694 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:03:59.694 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:03:59.694 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:03:59.694 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.28.20:5700) Recv POWEROFF cmd
2026-01-29 02:03:59.694 [INFO] ctrl_if_trx.py:117 (BTS@172.18.28.20:5700) Stopping transceiver...
2026-01-29 02:03:59.694 [INFO] transceiver.py:246 Stopping clock generator
2026-01-29 02:04:04.694 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.28.20:5700) Recv POWEROFF cmd
2026-01-29 02:04:04.694 [INFO] ctrl_if_trx.py:117 (BTS@172.18.28.20:5700) Stopping transceiver...
2026-01-29 02:04:04.696 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:04:04.697 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:04:04.698 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:04:04.698 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 02:04:04.706 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 02:04:04.706 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.28.20:5700) Recv SETFORMAT cmd
2026-01-29 02:04:04.706 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.28.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:04:04.707 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.28.20:5700) Recv SETFORMAT cmd
2026-01-29 02:04:04.707 [INFO] ctrl_if_trx.py:201 (BTS@172.18.28.20:5700) TRXD header version 1 -> 1
2026-01-29 02:04:04.709 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.28.20:5700/1) Recv RXTUNE cmd
2026-01-29 02:04:04.709 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.28.20:5700/1) Recv TXTUNE cmd
2026-01-29 02:04:04.709 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.28.20:5700/1) Recv SETFORMAT cmd
2026-01-29 02:04:04.709 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.28.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:04:04.710 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:04:04.710 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.28.20:5700/1) Recv NOMTXPOWER cmd
2026-01-29 02:04:04.710 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.28.20:5700/1) Recv SETFORMAT cmd
2026-01-29 02:04:04.711 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.28.20:5700/1) TRXD header version 1 -> 1
2026-01-29 02:04:04.711 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.28.20:5700/2) Recv RXTUNE cmd
2026-01-29 02:04:04.711 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.28.20:5700/2) Recv TXTUNE cmd
2026-01-29 02:04:04.711 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.28.20:5700/2) Recv SETFORMAT cmd
2026-01-29 02:04:04.711 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.28.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:04:04.711 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:04:04.711 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.28.20:5700/2) Recv NOMTXPOWER cmd
2026-01-29 02:04:04.712 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.28.20:5700/2) Recv SETFORMAT cmd
2026-01-29 02:04:04.712 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.28.20:5700/2) TRXD header version 1 -> 1
2026-01-29 02:04:04.713 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.28.20:5700/3) Recv RXTUNE cmd
2026-01-29 02:04:04.713 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.28.20:5700/3) Recv TXTUNE cmd
2026-01-29 02:04:04.713 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.28.20:5700/3) Recv SETFORMAT cmd
2026-01-29 02:04:04.713 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.28.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:04:04.713 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:04:04.713 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.28.20:5700/3) Recv NOMTXPOWER cmd
2026-01-29 02:04:04.714 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.28.20:5700/3) Recv SETFORMAT cmd
2026-01-29 02:04:04.714 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.28.20:5700/3) TRXD header version 1 -> 1
2026-01-29 02:04:04.716 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.28.20:5700) Recv RXTUNE cmd
2026-01-29 02:04:04.716 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETTSC
2026-01-29 02:04:04.716 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETTSC
2026-01-29 02:04:04.716 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETTSC
2026-01-29 02:04:04.716 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.28.20:5700) Recv TXTUNE cmd
2026-01-29 02:04:04.716 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETRXGAIN
2026-01-29 02:04:04.716 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETRXGAIN
2026-01-29 02:04:04.716 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETRXGAIN
2026-01-29 02:04:04.716 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETTSC
2026-01-29 02:04:04.716 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:04:04.716 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:04:04.716 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:04:04.716 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.28.20:5700) Recv NOMTXPOWER cmd
2026-01-29 02:04:04.716 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:04:04.716 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:04:04.716 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:04:04.716 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.28.20:5700) Recv POWERON CMD
2026-01-29 02:04:04.716 [INFO] ctrl_if_trx.py:109 (BTS@172.18.28.20:5700) Starting transceiver...
2026-01-29 02:04:04.716 [INFO] transceiver.py:243 Starting clock generator
2026-01-29 02:04:04.716 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-01-29 02:04:04.716 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:04:04.717 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:04:04.717 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:04:04.717 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETRXGAIN
2026-01-29 02:04:04.717 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:04:04.717 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:04:04.717 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:04:04.717 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:04:04.717 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:04:04.717 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:04:04.717 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:04:04.717 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:04:04.717 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:04:04.717 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:04:04.717 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:04:04.717 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:04:04.717 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:04:04.717 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:04:04.717 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:04:04.717 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:04:04.717 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:04:04.717 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:04:04.717 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:04:04.717 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:04:04.717 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:04:04.717 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:04:04.717 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:04:04.721 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-01-29 02:04:05.204 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-01-29 02:04:05.242 [DEBUG] fake_trx.py:278 (BTS@172.18.28.20:5700) Recv FAKE_TOA cmd
2026-01-29 02:04:05.244 [DEBUG] fake_trx.py:297 (BTS@172.18.28.20:5700) Recv FAKE_RSSI cmd
2026-01-29 02:04:05.245 [DEBUG] fake_trx.py:322 (BTS@172.18.28.20:5700) Recv FAKE_CI cmd
2026-01-29 02:04:05.246 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:04:05.263 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 02:04:05.263 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 02:04:05.263 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 02:04:05.276 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:04:05.279 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:04:05.281 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:04:05.283 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 02:04:05.283 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:04:05.284 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:04:05.284 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:04:05.286 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 02:04:05.287 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:04:05.287 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:04:05.287 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.28.20:5700) Recv POWEROFF cmd
2026-01-29 02:04:05.287 [INFO] ctrl_if_trx.py:117 (BTS@172.18.28.20:5700) Stopping transceiver...
2026-01-29 02:04:05.287 [INFO] transceiver.py:246 Stopping clock generator
2026-01-29 02:04:05.287 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:04:05.287 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=121 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:04:05.287 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=121 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:04:05.287 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=121 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:04:05.287 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=121 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:04:05.287 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=121 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:04:05.287 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=121 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:04:05.287 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=121 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:04:05.287 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=121 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:04:05.287 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=122 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:04:10.290 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.28.20:5700) Recv POWEROFF cmd
2026-01-29 02:04:10.290 [INFO] ctrl_if_trx.py:117 (BTS@172.18.28.20:5700) Stopping transceiver...
2026-01-29 02:04:10.290 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:04:10.290 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 02:04:10.290 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:04:10.290 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:04:10.299 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 02:04:10.301 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.28.20:5700) Recv SETFORMAT cmd
2026-01-29 02:04:10.301 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.28.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:04:10.302 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.28.20:5700) Recv SETFORMAT cmd
2026-01-29 02:04:10.302 [INFO] ctrl_if_trx.py:201 (BTS@172.18.28.20:5700) TRXD header version 1 -> 1
2026-01-29 02:04:10.306 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.28.20:5700/1) Recv RXTUNE cmd
2026-01-29 02:04:10.306 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.28.20:5700/1) Recv TXTUNE cmd
2026-01-29 02:04:10.307 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.28.20:5700/1) Recv SETFORMAT cmd
2026-01-29 02:04:10.307 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.28.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:04:10.307 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:04:10.307 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.28.20:5700/1) Recv NOMTXPOWER cmd
2026-01-29 02:04:10.308 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.28.20:5700/1) Recv SETFORMAT cmd
2026-01-29 02:04:10.308 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.28.20:5700/1) TRXD header version 1 -> 1
2026-01-29 02:04:10.309 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.28.20:5700/2) Recv RXTUNE cmd
2026-01-29 02:04:10.310 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.28.20:5700/2) Recv TXTUNE cmd
2026-01-29 02:04:10.310 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.28.20:5700/2) Recv SETFORMAT cmd
2026-01-29 02:04:10.310 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.28.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:04:10.310 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:04:10.310 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.28.20:5700/2) Recv NOMTXPOWER cmd
2026-01-29 02:04:10.311 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.28.20:5700/2) Recv SETFORMAT cmd
2026-01-29 02:04:10.311 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.28.20:5700/2) TRXD header version 1 -> 1
2026-01-29 02:04:10.312 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.28.20:5700/3) Recv RXTUNE cmd
2026-01-29 02:04:10.312 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.28.20:5700/3) Recv TXTUNE cmd
2026-01-29 02:04:10.312 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.28.20:5700/3) Recv SETFORMAT cmd
2026-01-29 02:04:10.313 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.28.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:04:10.313 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:04:10.313 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.28.20:5700/3) Recv NOMTXPOWER cmd
2026-01-29 02:04:10.313 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.28.20:5700/3) Recv SETFORMAT cmd
2026-01-29 02:04:10.313 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.28.20:5700/3) TRXD header version 1 -> 1
2026-01-29 02:04:10.315 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.28.20:5700) Recv RXTUNE cmd
2026-01-29 02:04:10.315 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETTSC
2026-01-29 02:04:10.315 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETTSC
2026-01-29 02:04:10.315 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETTSC
2026-01-29 02:04:10.315 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.28.20:5700) Recv TXTUNE cmd
2026-01-29 02:04:10.315 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETRXGAIN
2026-01-29 02:04:10.315 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETRXGAIN
2026-01-29 02:04:10.316 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETRXGAIN
2026-01-29 02:04:10.316 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETTSC
2026-01-29 02:04:10.316 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:04:10.316 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:04:10.316 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:04:10.316 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.28.20:5700) Recv NOMTXPOWER cmd
2026-01-29 02:04:10.316 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:04:10.316 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:04:10.316 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:04:10.316 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.28.20:5700) Recv POWERON CMD
2026-01-29 02:04:10.316 [INFO] ctrl_if_trx.py:109 (BTS@172.18.28.20:5700) Starting transceiver...
2026-01-29 02:04:10.316 [INFO] transceiver.py:243 Starting clock generator
2026-01-29 02:04:10.316 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-01-29 02:04:10.316 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:04:10.316 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:04:10.316 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:04:10.316 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETRXGAIN
2026-01-29 02:04:10.317 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:04:10.317 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:04:10.317 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:04:10.317 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:04:10.317 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:04:10.317 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:04:10.317 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:04:10.317 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:04:10.317 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:04:10.317 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:04:10.317 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:04:10.317 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:04:10.317 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:04:10.317 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:04:10.317 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:04:10.317 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:04:10.317 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:04:10.317 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:04:10.317 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:04:10.317 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:04:10.318 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:04:10.318 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:04:10.318 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:04:10.321 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-01-29 02:04:10.804 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-01-29 02:04:10.841 [DEBUG] fake_trx.py:278 (BTS@172.18.28.20:5700) Recv FAKE_TOA cmd
2026-01-29 02:04:10.843 [DEBUG] fake_trx.py:297 (BTS@172.18.28.20:5700) Recv FAKE_RSSI cmd
2026-01-29 02:04:10.844 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:04:10.845 [DEBUG] fake_trx.py:322 (BTS@172.18.28.20:5700) Recv FAKE_CI cmd
2026-01-29 02:04:10.862 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 02:04:10.862 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 02:04:10.863 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 02:04:10.872 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:04:10.874 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:04:11.286 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-01-29 02:04:11.319 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 02:04:11.319 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:04:11.320 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:04:11.322 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:04:11.767 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-01-29 02:04:12.248 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-01-29 02:04:12.320 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:04:12.320 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 02:04:12.321 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:04:12.324 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:04:12.730 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-01-29 02:04:13.207 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-01-29 02:04:13.322 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:04:13.322 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 02:04:13.322 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:04:13.326 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:04:13.675 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-01-29 02:04:13.881 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:04:13.881 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:04:13.893 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 02:04:13.893 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:04:13.893 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:04:13.893 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:04:13.895 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 02:04:13.895 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:04:13.895 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:04:13.895 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:04:13.895 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.28.20:5700) Recv POWEROFF cmd
2026-01-29 02:04:13.895 [INFO] ctrl_if_trx.py:117 (BTS@172.18.28.20:5700) Stopping transceiver...
2026-01-29 02:04:13.895 [INFO] transceiver.py:246 Stopping clock generator
2026-01-29 02:04:13.895 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=764 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:04:13.895 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=764 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:04:18.896 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.28.20:5700) Recv POWEROFF cmd
2026-01-29 02:04:18.896 [INFO] ctrl_if_trx.py:117 (BTS@172.18.28.20:5700) Stopping transceiver...
2026-01-29 02:04:18.899 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:04:18.899 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:04:18.899 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:04:18.899 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 02:04:18.901 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 02:04:18.902 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.28.20:5700) Recv SETFORMAT cmd
2026-01-29 02:04:18.902 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.28.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:04:18.902 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.28.20:5700) Recv SETFORMAT cmd
2026-01-29 02:04:18.902 [INFO] ctrl_if_trx.py:201 (BTS@172.18.28.20:5700) TRXD header version 1 -> 1
2026-01-29 02:04:18.903 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.28.20:5700/1) Recv RXTUNE cmd
2026-01-29 02:04:18.903 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.28.20:5700/1) Recv TXTUNE cmd
2026-01-29 02:04:18.903 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.28.20:5700/1) Recv SETFORMAT cmd
2026-01-29 02:04:18.903 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.28.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:04:18.903 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:04:18.903 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.28.20:5700/1) Recv NOMTXPOWER cmd
2026-01-29 02:04:18.903 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.28.20:5700/1) Recv SETFORMAT cmd
2026-01-29 02:04:18.903 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.28.20:5700/1) TRXD header version 1 -> 1
2026-01-29 02:04:18.904 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.28.20:5700/2) Recv RXTUNE cmd
2026-01-29 02:04:18.904 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.28.20:5700/2) Recv TXTUNE cmd
2026-01-29 02:04:18.904 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.28.20:5700/2) Recv SETFORMAT cmd
2026-01-29 02:04:18.904 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.28.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:04:18.904 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:04:18.904 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.28.20:5700/2) Recv NOMTXPOWER cmd
2026-01-29 02:04:18.904 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.28.20:5700/2) Recv SETFORMAT cmd
2026-01-29 02:04:18.904 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.28.20:5700/2) TRXD header version 1 -> 1
2026-01-29 02:04:18.905 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.28.20:5700/3) Recv RXTUNE cmd
2026-01-29 02:04:18.905 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.28.20:5700/3) Recv TXTUNE cmd
2026-01-29 02:04:18.905 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.28.20:5700/3) Recv SETFORMAT cmd
2026-01-29 02:04:18.905 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.28.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:04:18.905 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:04:18.905 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.28.20:5700/3) Recv NOMTXPOWER cmd
2026-01-29 02:04:18.905 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.28.20:5700/3) Recv SETFORMAT cmd
2026-01-29 02:04:18.905 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.28.20:5700/3) TRXD header version 1 -> 1
2026-01-29 02:04:18.907 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.28.20:5700) Recv RXTUNE cmd
2026-01-29 02:04:18.907 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETTSC
2026-01-29 02:04:18.907 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETTSC
2026-01-29 02:04:18.907 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETTSC
2026-01-29 02:04:18.907 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.28.20:5700) Recv TXTUNE cmd
2026-01-29 02:04:18.907 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETRXGAIN
2026-01-29 02:04:18.907 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETRXGAIN
2026-01-29 02:04:18.907 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETRXGAIN
2026-01-29 02:04:18.907 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETTSC
2026-01-29 02:04:18.907 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:04:18.907 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:04:18.907 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:04:18.907 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.28.20:5700) Recv NOMTXPOWER cmd
2026-01-29 02:04:18.907 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:04:18.907 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:04:18.907 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:04:18.907 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.28.20:5700) Recv POWERON CMD
2026-01-29 02:04:18.907 [INFO] ctrl_if_trx.py:109 (BTS@172.18.28.20:5700) Starting transceiver...
2026-01-29 02:04:18.907 [INFO] transceiver.py:243 Starting clock generator
2026-01-29 02:04:18.907 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-01-29 02:04:18.907 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:04:18.907 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:04:18.907 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:04:18.908 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETRXGAIN
2026-01-29 02:04:18.908 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:04:18.908 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:04:18.908 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:04:18.908 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:04:18.908 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:04:18.908 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:04:18.908 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:04:18.908 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:04:18.908 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:04:18.908 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:04:18.908 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:04:18.908 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:04:18.908 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:04:18.908 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:04:18.908 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:04:18.908 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:04:18.908 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:04:18.908 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:04:18.908 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:04:18.908 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:04:18.908 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:04:18.908 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:04:18.908 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:04:18.912 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-01-29 02:04:19.395 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-01-29 02:04:19.435 [DEBUG] fake_trx.py:278 (BTS@172.18.28.20:5700) Recv FAKE_TOA cmd
2026-01-29 02:04:19.437 [DEBUG] fake_trx.py:297 (BTS@172.18.28.20:5700) Recv FAKE_RSSI cmd
2026-01-29 02:04:19.438 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:04:19.439 [DEBUG] fake_trx.py:322 (BTS@172.18.28.20:5700) Recv FAKE_CI cmd
2026-01-29 02:04:19.463 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 02:04:19.463 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 02:04:19.464 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 02:04:19.471 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:04:19.472 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:04:19.476 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:04:19.476 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:04:19.479 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 02:04:19.479 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:04:19.479 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:04:19.479 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:04:19.482 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 02:04:19.482 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:04:19.482 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:04:19.482 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:04:19.482 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.28.20:5700) Recv POWEROFF cmd
2026-01-29 02:04:19.482 [INFO] ctrl_if_trx.py:117 (BTS@172.18.28.20:5700) Stopping transceiver...
2026-01-29 02:04:19.482 [INFO] transceiver.py:246 Stopping clock generator
2026-01-29 02:04:19.482 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=122 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:04:19.482 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=122 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:04:19.483 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=122 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:04:19.483 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=122 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:04:24.486 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.28.20:5700) Recv POWEROFF cmd
2026-01-29 02:04:24.486 [INFO] ctrl_if_trx.py:117 (BTS@172.18.28.20:5700) Stopping transceiver...
2026-01-29 02:04:24.486 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:04:24.486 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:04:24.486 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:04:24.486 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 02:04:24.495 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 02:04:24.497 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.28.20:5700) Recv SETFORMAT cmd
2026-01-29 02:04:24.497 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.28.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:04:24.498 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.28.20:5700) Recv SETFORMAT cmd
2026-01-29 02:04:24.498 [INFO] ctrl_if_trx.py:201 (BTS@172.18.28.20:5700) TRXD header version 1 -> 1
2026-01-29 02:04:24.502 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.28.20:5700/1) Recv RXTUNE cmd
2026-01-29 02:04:24.502 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.28.20:5700/1) Recv TXTUNE cmd
2026-01-29 02:04:24.503 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.28.20:5700/1) Recv SETFORMAT cmd
2026-01-29 02:04:24.503 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.28.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:04:24.503 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:04:24.503 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.28.20:5700/1) Recv NOMTXPOWER cmd
2026-01-29 02:04:24.503 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.28.20:5700/1) Recv SETFORMAT cmd
2026-01-29 02:04:24.503 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.28.20:5700/1) TRXD header version 1 -> 1
2026-01-29 02:04:24.506 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.28.20:5700/2) Recv RXTUNE cmd
2026-01-29 02:04:24.507 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.28.20:5700/2) Recv TXTUNE cmd
2026-01-29 02:04:24.507 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.28.20:5700/2) Recv SETFORMAT cmd
2026-01-29 02:04:24.507 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.28.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:04:24.508 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:04:24.508 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.28.20:5700/2) Recv NOMTXPOWER cmd
2026-01-29 02:04:24.509 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.28.20:5700/2) Recv SETFORMAT cmd
2026-01-29 02:04:24.509 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.28.20:5700/2) TRXD header version 1 -> 1
2026-01-29 02:04:24.510 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.28.20:5700/3) Recv RXTUNE cmd
2026-01-29 02:04:24.510 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.28.20:5700/3) Recv TXTUNE cmd
2026-01-29 02:04:24.510 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.28.20:5700/3) Recv SETFORMAT cmd
2026-01-29 02:04:24.510 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.28.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:04:24.510 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:04:24.510 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.28.20:5700/3) Recv NOMTXPOWER cmd
2026-01-29 02:04:24.510 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.28.20:5700/3) Recv SETFORMAT cmd
2026-01-29 02:04:24.510 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.28.20:5700/3) TRXD header version 1 -> 1
2026-01-29 02:04:24.513 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.28.20:5700) Recv RXTUNE cmd
2026-01-29 02:04:24.513 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETTSC
2026-01-29 02:04:24.513 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETTSC
2026-01-29 02:04:24.513 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETTSC
2026-01-29 02:04:24.513 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.28.20:5700) Recv TXTUNE cmd
2026-01-29 02:04:24.513 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETRXGAIN
2026-01-29 02:04:24.514 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETRXGAIN
2026-01-29 02:04:24.514 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETRXGAIN
2026-01-29 02:04:24.514 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETTSC
2026-01-29 02:04:24.514 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:04:24.514 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:04:24.514 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:04:24.514 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.28.20:5700) Recv NOMTXPOWER cmd
2026-01-29 02:04:24.514 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:04:24.514 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:04:24.514 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:04:24.514 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.28.20:5700) Recv POWERON CMD
2026-01-29 02:04:24.514 [INFO] ctrl_if_trx.py:109 (BTS@172.18.28.20:5700) Starting transceiver...
2026-01-29 02:04:24.514 [INFO] transceiver.py:243 Starting clock generator
2026-01-29 02:04:24.514 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-01-29 02:04:24.514 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:04:24.514 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:04:24.514 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:04:24.515 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETRXGAIN
2026-01-29 02:04:24.515 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:04:24.515 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:04:24.515 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:04:24.515 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:04:24.515 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:04:24.515 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:04:24.515 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:04:24.515 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:04:24.515 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:04:24.515 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:04:24.516 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:04:24.516 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:04:24.516 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:04:24.516 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:04:24.516 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:04:24.516 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:04:24.516 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:04:24.516 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:04:24.516 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:04:24.516 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:04:24.516 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:04:24.516 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:04:24.516 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:04:24.519 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-01-29 02:04:25.002 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-01-29 02:04:25.045 [DEBUG] fake_trx.py:278 (BTS@172.18.28.20:5700) Recv FAKE_TOA cmd
2026-01-29 02:04:25.047 [DEBUG] fake_trx.py:297 (BTS@172.18.28.20:5700) Recv FAKE_RSSI cmd
2026-01-29 02:04:25.048 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:04:25.050 [DEBUG] fake_trx.py:322 (BTS@172.18.28.20:5700) Recv FAKE_CI cmd
2026-01-29 02:04:25.061 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 02:04:25.061 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:04:25.062 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:04:25.062 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:04:25.066 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 02:04:25.066 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:04:25.066 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:04:25.066 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:04:25.066 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.28.20:5700) Recv POWEROFF cmd
2026-01-29 02:04:25.066 [INFO] ctrl_if_trx.py:117 (BTS@172.18.28.20:5700) Stopping transceiver...
2026-01-29 02:04:25.066 [INFO] transceiver.py:246 Stopping clock generator
2026-01-29 02:04:25.066 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=117 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:04:25.066 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=117 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:04:25.066 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=117 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:04:25.066 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=117 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:04:25.066 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=117 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:04:25.066 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=117 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:04:30.065 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.28.20:5700) Recv POWEROFF cmd
2026-01-29 02:04:30.065 [INFO] ctrl_if_trx.py:117 (BTS@172.18.28.20:5700) Stopping transceiver...
2026-01-29 02:04:30.067 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:04:30.067 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:04:30.068 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:04:30.068 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 02:04:30.074 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 02:04:30.076 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.28.20:5700) Recv SETFORMAT cmd
2026-01-29 02:04:30.076 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.28.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:04:30.076 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.28.20:5700) Recv SETFORMAT cmd
2026-01-29 02:04:30.076 [INFO] ctrl_if_trx.py:201 (BTS@172.18.28.20:5700) TRXD header version 1 -> 1
2026-01-29 02:04:30.080 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.28.20:5700/1) Recv RXTUNE cmd
2026-01-29 02:04:30.081 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.28.20:5700/1) Recv TXTUNE cmd
2026-01-29 02:04:30.081 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.28.20:5700/1) Recv SETFORMAT cmd
2026-01-29 02:04:30.081 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.28.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:04:30.082 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:04:30.082 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.28.20:5700/1) Recv NOMTXPOWER cmd
2026-01-29 02:04:30.082 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.28.20:5700/1) Recv SETFORMAT cmd
2026-01-29 02:04:30.082 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.28.20:5700/1) TRXD header version 1 -> 1
2026-01-29 02:04:30.084 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.28.20:5700/2) Recv RXTUNE cmd
2026-01-29 02:04:30.084 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.28.20:5700/2) Recv TXTUNE cmd
2026-01-29 02:04:30.084 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.28.20:5700/2) Recv SETFORMAT cmd
2026-01-29 02:04:30.085 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.28.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:04:30.085 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:04:30.085 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.28.20:5700/2) Recv NOMTXPOWER cmd
2026-01-29 02:04:30.086 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.28.20:5700/2) Recv SETFORMAT cmd
2026-01-29 02:04:30.086 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.28.20:5700/2) TRXD header version 1 -> 1
2026-01-29 02:04:30.086 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.28.20:5700/3) Recv RXTUNE cmd
2026-01-29 02:04:30.087 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.28.20:5700/3) Recv TXTUNE cmd
2026-01-29 02:04:30.087 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.28.20:5700/3) Recv SETFORMAT cmd
2026-01-29 02:04:30.087 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.28.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:04:30.087 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:04:30.087 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.28.20:5700/3) Recv NOMTXPOWER cmd
2026-01-29 02:04:30.087 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.28.20:5700/3) Recv SETFORMAT cmd
2026-01-29 02:04:30.087 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.28.20:5700/3) TRXD header version 1 -> 1
2026-01-29 02:04:30.090 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.28.20:5700) Recv RXTUNE cmd
2026-01-29 02:04:30.090 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETTSC
2026-01-29 02:04:30.090 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETTSC
2026-01-29 02:04:30.090 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.28.20:5700) Recv TXTUNE cmd
2026-01-29 02:04:30.090 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETRXGAIN
2026-01-29 02:04:30.090 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETTSC
2026-01-29 02:04:30.090 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETRXGAIN
2026-01-29 02:04:30.090 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETTSC
2026-01-29 02:04:30.090 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:04:30.090 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETRXGAIN
2026-01-29 02:04:30.090 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:04:30.090 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.28.20:5700) Recv NOMTXPOWER cmd
2026-01-29 02:04:30.090 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:04:30.090 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:04:30.090 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:04:30.090 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.28.20:5700) Recv POWERON CMD
2026-01-29 02:04:30.090 [INFO] ctrl_if_trx.py:109 (BTS@172.18.28.20:5700) Starting transceiver...
2026-01-29 02:04:30.090 [INFO] transceiver.py:243 Starting clock generator
2026-01-29 02:04:30.091 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-01-29 02:04:30.091 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:04:30.091 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:04:30.091 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:04:30.091 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETRXGAIN
2026-01-29 02:04:30.091 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:04:30.091 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:04:30.091 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:04:30.091 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:04:30.091 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:04:30.091 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:04:30.091 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:04:30.091 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:04:30.092 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:04:30.092 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:04:30.092 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:04:30.092 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:04:30.092 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:04:30.092 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:04:30.092 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:04:30.092 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:04:30.092 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:04:30.092 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:04:30.092 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:04:30.092 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:04:30.092 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:04:30.092 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:04:30.093 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:04:30.093 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:04:30.095 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-01-29 02:04:30.578 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-01-29 02:04:30.616 [DEBUG] fake_trx.py:278 (BTS@172.18.28.20:5700) Recv FAKE_TOA cmd
2026-01-29 02:04:30.617 [DEBUG] fake_trx.py:297 (BTS@172.18.28.20:5700) Recv FAKE_RSSI cmd
2026-01-29 02:04:30.619 [DEBUG] fake_trx.py:322 (BTS@172.18.28.20:5700) Recv FAKE_CI cmd
2026-01-29 02:04:30.619 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:04:30.630 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 02:04:30.630 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:04:30.630 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:04:30.630 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:04:30.633 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 02:04:30.633 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:04:30.633 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:04:30.633 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:04:30.633 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.28.20:5700) Recv POWEROFF cmd
2026-01-29 02:04:30.633 [INFO] ctrl_if_trx.py:117 (BTS@172.18.28.20:5700) Stopping transceiver...
2026-01-29 02:04:30.633 [INFO] transceiver.py:246 Stopping clock generator
2026-01-29 02:04:30.633 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=115 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:04:30.633 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=115 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:04:35.631 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.28.20:5700) Recv POWEROFF cmd
2026-01-29 02:04:35.631 [INFO] ctrl_if_trx.py:117 (BTS@172.18.28.20:5700) Stopping transceiver...
2026-01-29 02:04:35.631 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:04:35.631 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:04:35.632 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:04:35.632 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 02:04:35.636 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 02:04:35.636 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.28.20:5700) Recv SETFORMAT cmd
2026-01-29 02:04:35.636 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.28.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:04:35.637 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.28.20:5700) Recv SETFORMAT cmd
2026-01-29 02:04:35.637 [INFO] ctrl_if_trx.py:201 (BTS@172.18.28.20:5700) TRXD header version 1 -> 1
2026-01-29 02:04:35.638 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.28.20:5700/1) Recv RXTUNE cmd
2026-01-29 02:04:35.638 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.28.20:5700/1) Recv TXTUNE cmd
2026-01-29 02:04:35.638 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.28.20:5700/1) Recv SETFORMAT cmd
2026-01-29 02:04:35.638 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.28.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:04:35.638 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:04:35.638 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.28.20:5700/1) Recv NOMTXPOWER cmd
2026-01-29 02:04:35.638 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.28.20:5700/1) Recv SETFORMAT cmd
2026-01-29 02:04:35.638 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.28.20:5700/1) TRXD header version 1 -> 1
2026-01-29 02:04:35.639 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.28.20:5700/2) Recv RXTUNE cmd
2026-01-29 02:04:35.639 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.28.20:5700/2) Recv TXTUNE cmd
2026-01-29 02:04:35.639 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.28.20:5700/2) Recv SETFORMAT cmd
2026-01-29 02:04:35.639 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.28.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:04:35.639 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:04:35.639 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.28.20:5700/2) Recv NOMTXPOWER cmd
2026-01-29 02:04:35.639 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.28.20:5700/2) Recv SETFORMAT cmd
2026-01-29 02:04:35.639 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.28.20:5700/2) TRXD header version 1 -> 1
2026-01-29 02:04:35.640 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.28.20:5700/3) Recv RXTUNE cmd
2026-01-29 02:04:35.640 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.28.20:5700/3) Recv TXTUNE cmd
2026-01-29 02:04:35.640 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.28.20:5700/3) Recv SETFORMAT cmd
2026-01-29 02:04:35.640 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.28.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:04:35.640 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:04:35.640 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.28.20:5700/3) Recv NOMTXPOWER cmd
2026-01-29 02:04:35.640 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.28.20:5700/3) Recv SETFORMAT cmd
2026-01-29 02:04:35.640 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.28.20:5700/3) TRXD header version 1 -> 1
2026-01-29 02:04:35.641 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.28.20:5700) Recv RXTUNE cmd
2026-01-29 02:04:35.641 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETTSC
2026-01-29 02:04:35.642 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETTSC
2026-01-29 02:04:35.642 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETTSC
2026-01-29 02:04:35.642 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.28.20:5700) Recv TXTUNE cmd
2026-01-29 02:04:35.642 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETRXGAIN
2026-01-29 02:04:35.642 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETRXGAIN
2026-01-29 02:04:35.642 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETRXGAIN
2026-01-29 02:04:35.642 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETTSC
2026-01-29 02:04:35.642 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:04:35.642 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:04:35.642 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:04:35.642 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.28.20:5700) Recv NOMTXPOWER cmd
2026-01-29 02:04:35.642 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:04:35.642 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:04:35.642 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:04:35.642 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.28.20:5700) Recv POWERON CMD
2026-01-29 02:04:35.642 [INFO] ctrl_if_trx.py:109 (BTS@172.18.28.20:5700) Starting transceiver...
2026-01-29 02:04:35.642 [INFO] transceiver.py:243 Starting clock generator
2026-01-29 02:04:35.642 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-01-29 02:04:35.642 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:04:35.642 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:04:35.642 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:04:35.642 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETRXGAIN
2026-01-29 02:04:35.642 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:04:35.642 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:04:35.642 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:04:35.642 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:04:35.642 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:04:35.642 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:04:35.642 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:04:35.642 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:04:35.642 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:04:35.642 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:04:35.642 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:04:35.642 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:04:35.643 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:04:35.643 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:04:35.643 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:04:35.643 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:04:35.643 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:04:35.643 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:04:35.643 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:04:35.643 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:04:35.643 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:04:35.643 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:04:35.643 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:04:35.647 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-01-29 02:04:36.130 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-01-29 02:04:36.167 [DEBUG] fake_trx.py:278 (BTS@172.18.28.20:5700) Recv FAKE_TOA cmd
2026-01-29 02:04:36.169 [DEBUG] fake_trx.py:297 (BTS@172.18.28.20:5700) Recv FAKE_RSSI cmd
2026-01-29 02:04:36.171 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:04:36.171 [DEBUG] fake_trx.py:322 (BTS@172.18.28.20:5700) Recv FAKE_CI cmd
2026-01-29 02:04:36.181 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 02:04:36.181 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:04:36.181 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:04:36.182 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:04:36.185 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 02:04:36.185 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:04:36.185 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:04:36.185 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:04:36.185 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.28.20:5700) Recv POWEROFF cmd
2026-01-29 02:04:36.185 [INFO] ctrl_if_trx.py:117 (BTS@172.18.28.20:5700) Stopping transceiver...
2026-01-29 02:04:36.185 [INFO] transceiver.py:246 Stopping clock generator
2026-01-29 02:04:36.185 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=115 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:04:36.185 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=115 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:04:36.185 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=115 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:04:36.185 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=115 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:04:36.185 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=115 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:04:36.185 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=115 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:04:36.185 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=115 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:04:41.185 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.28.20:5700) Recv POWEROFF cmd
2026-01-29 02:04:41.185 [INFO] ctrl_if_trx.py:117 (BTS@172.18.28.20:5700) Stopping transceiver...
2026-01-29 02:04:41.187 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:04:41.188 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:04:41.188 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:04:41.188 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 02:04:41.196 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 02:04:41.197 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.28.20:5700) Recv SETFORMAT cmd
2026-01-29 02:04:41.197 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.28.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:04:41.198 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.28.20:5700) Recv SETFORMAT cmd
2026-01-29 02:04:41.198 [INFO] ctrl_if_trx.py:201 (BTS@172.18.28.20:5700) TRXD header version 1 -> 1
2026-01-29 02:04:41.202 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.28.20:5700/1) Recv RXTUNE cmd
2026-01-29 02:04:41.202 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.28.20:5700/1) Recv TXTUNE cmd
2026-01-29 02:04:41.203 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.28.20:5700/1) Recv SETFORMAT cmd
2026-01-29 02:04:41.203 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.28.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:04:41.203 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:04:41.204 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.28.20:5700/1) Recv NOMTXPOWER cmd
2026-01-29 02:04:41.204 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.28.20:5700/1) Recv SETFORMAT cmd
2026-01-29 02:04:41.205 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.28.20:5700/1) TRXD header version 1 -> 1
2026-01-29 02:04:41.206 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.28.20:5700/2) Recv RXTUNE cmd
2026-01-29 02:04:41.206 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.28.20:5700/2) Recv TXTUNE cmd
2026-01-29 02:04:41.207 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.28.20:5700/2) Recv SETFORMAT cmd
2026-01-29 02:04:41.207 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.28.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:04:41.207 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:04:41.207 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.28.20:5700/2) Recv NOMTXPOWER cmd
2026-01-29 02:04:41.207 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.28.20:5700/2) Recv SETFORMAT cmd
2026-01-29 02:04:41.208 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.28.20:5700/2) TRXD header version 1 -> 1
2026-01-29 02:04:41.210 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.28.20:5700/3) Recv RXTUNE cmd
2026-01-29 02:04:41.210 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.28.20:5700/3) Recv TXTUNE cmd
2026-01-29 02:04:41.210 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.28.20:5700/3) Recv SETFORMAT cmd
2026-01-29 02:04:41.210 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.28.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:04:41.210 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:04:41.210 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.28.20:5700/3) Recv NOMTXPOWER cmd
2026-01-29 02:04:41.210 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.28.20:5700/3) Recv SETFORMAT cmd
2026-01-29 02:04:41.210 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.28.20:5700/3) TRXD header version 1 -> 1
2026-01-29 02:04:41.214 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.28.20:5700) Recv RXTUNE cmd
2026-01-29 02:04:41.214 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETTSC
2026-01-29 02:04:41.214 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETTSC
2026-01-29 02:04:41.214 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETTSC
2026-01-29 02:04:41.214 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.28.20:5700) Recv TXTUNE cmd
2026-01-29 02:04:41.214 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETRXGAIN
2026-01-29 02:04:41.214 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETRXGAIN
2026-01-29 02:04:41.214 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETRXGAIN
2026-01-29 02:04:41.215 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETTSC
2026-01-29 02:04:41.215 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:04:41.215 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:04:41.215 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:04:41.215 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.28.20:5700) Recv NOMTXPOWER cmd
2026-01-29 02:04:41.215 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:04:41.215 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:04:41.215 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:04:41.215 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.28.20:5700) Recv POWERON CMD
2026-01-29 02:04:41.215 [INFO] ctrl_if_trx.py:109 (BTS@172.18.28.20:5700) Starting transceiver...
2026-01-29 02:04:41.215 [INFO] transceiver.py:243 Starting clock generator
2026-01-29 02:04:41.215 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-01-29 02:04:41.215 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:04:41.215 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:04:41.215 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:04:41.215 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETRXGAIN
2026-01-29 02:04:41.215 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:04:41.215 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:04:41.215 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:04:41.215 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:04:41.216 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:04:41.216 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:04:41.216 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:04:41.216 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:04:41.216 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:04:41.216 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:04:41.216 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:04:41.216 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:04:41.216 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:04:41.216 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:04:41.216 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:04:41.216 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:04:41.216 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:04:41.216 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:04:41.216 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:04:41.216 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:04:41.216 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:04:41.216 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:04:41.217 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:04:41.220 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-01-29 02:04:41.705 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-01-29 02:04:41.744 [DEBUG] fake_trx.py:278 (BTS@172.18.28.20:5700) Recv FAKE_TOA cmd
2026-01-29 02:04:41.747 [DEBUG] fake_trx.py:297 (BTS@172.18.28.20:5700) Recv FAKE_RSSI cmd
2026-01-29 02:04:41.748 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:04:41.749 [DEBUG] fake_trx.py:322 (BTS@172.18.28.20:5700) Recv FAKE_CI cmd
2026-01-29 02:04:41.765 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 02:04:41.765 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:04:41.765 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:04:41.765 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:04:41.771 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 02:04:41.771 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:04:41.771 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:04:41.772 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:04:41.772 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.28.20:5700) Recv POWEROFF cmd
2026-01-29 02:04:41.772 [INFO] ctrl_if_trx.py:117 (BTS@172.18.28.20:5700) Stopping transceiver...
2026-01-29 02:04:41.772 [INFO] transceiver.py:246 Stopping clock generator
2026-01-29 02:04:41.772 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=117 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:04:41.772 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=117 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:04:41.772 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=117 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:04:41.773 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=117 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:04:41.773 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=117 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:04:41.773 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=117 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:04:41.773 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=118 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:04:41.773 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=118 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:04:41.773 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=118 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:04:41.773 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=118 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:04:41.773 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=118 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:04:41.773 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=118 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:04:41.773 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=118 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:04:41.773 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=118 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:04:46.768 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.28.20:5700) Recv POWEROFF cmd
2026-01-29 02:04:46.768 [INFO] ctrl_if_trx.py:117 (BTS@172.18.28.20:5700) Stopping transceiver...
2026-01-29 02:04:46.772 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:04:46.772 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:04:46.772 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:04:46.772 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 02:04:46.775 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 02:04:46.775 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.28.20:5700) Recv SETFORMAT cmd
2026-01-29 02:04:46.775 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.28.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:04:46.775 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.28.20:5700) Recv SETFORMAT cmd
2026-01-29 02:04:46.775 [INFO] ctrl_if_trx.py:201 (BTS@172.18.28.20:5700) TRXD header version 1 -> 1
2026-01-29 02:04:46.778 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.28.20:5700/1) Recv RXTUNE cmd
2026-01-29 02:04:46.778 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.28.20:5700/1) Recv TXTUNE cmd
2026-01-29 02:04:46.778 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.28.20:5700/1) Recv SETFORMAT cmd
2026-01-29 02:04:46.778 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.28.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:04:46.778 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.28.20:5700/1) Recv NOMTXPOWER cmd
2026-01-29 02:04:46.779 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:04:46.779 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.28.20:5700/1) Recv SETFORMAT cmd
2026-01-29 02:04:46.779 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.28.20:5700/1) TRXD header version 1 -> 1
2026-01-29 02:04:46.781 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.28.20:5700/2) Recv RXTUNE cmd
2026-01-29 02:04:46.781 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.28.20:5700/2) Recv TXTUNE cmd
2026-01-29 02:04:46.781 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.28.20:5700/2) Recv SETFORMAT cmd
2026-01-29 02:04:46.781 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.28.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:04:46.781 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:04:46.781 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.28.20:5700/2) Recv NOMTXPOWER cmd
2026-01-29 02:04:46.781 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.28.20:5700/2) Recv SETFORMAT cmd
2026-01-29 02:04:46.781 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.28.20:5700/2) TRXD header version 1 -> 1
2026-01-29 02:04:46.783 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.28.20:5700/3) Recv RXTUNE cmd
2026-01-29 02:04:46.783 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.28.20:5700/3) Recv TXTUNE cmd
2026-01-29 02:04:46.783 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.28.20:5700/3) Recv SETFORMAT cmd
2026-01-29 02:04:46.783 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.28.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:04:46.783 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:04:46.783 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.28.20:5700/3) Recv NOMTXPOWER cmd
2026-01-29 02:04:46.783 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.28.20:5700/3) Recv SETFORMAT cmd
2026-01-29 02:04:46.783 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.28.20:5700/3) TRXD header version 1 -> 1
2026-01-29 02:04:46.785 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.28.20:5700) Recv RXTUNE cmd
2026-01-29 02:04:46.785 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETTSC
2026-01-29 02:04:46.785 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETTSC
2026-01-29 02:04:46.785 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETTSC
2026-01-29 02:04:46.785 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.28.20:5700) Recv TXTUNE cmd
2026-01-29 02:04:46.785 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETRXGAIN
2026-01-29 02:04:46.785 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETRXGAIN
2026-01-29 02:04:46.786 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETRXGAIN
2026-01-29 02:04:46.786 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETTSC
2026-01-29 02:04:46.786 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:04:46.786 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:04:46.786 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:04:46.786 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.28.20:5700) Recv NOMTXPOWER cmd
2026-01-29 02:04:46.786 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:04:46.786 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:04:46.786 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:04:46.786 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.28.20:5700) Recv POWERON CMD
2026-01-29 02:04:46.786 [INFO] ctrl_if_trx.py:109 (BTS@172.18.28.20:5700) Starting transceiver...
2026-01-29 02:04:46.786 [INFO] transceiver.py:243 Starting clock generator
2026-01-29 02:04:46.786 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-01-29 02:04:46.786 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:04:46.786 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:04:46.786 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:04:46.786 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETRXGAIN
2026-01-29 02:04:46.786 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:04:46.786 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:04:46.786 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:04:46.786 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:04:46.786 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:04:46.786 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:04:46.786 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:04:46.786 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:04:46.786 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:04:46.786 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:04:46.786 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:04:46.786 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:04:46.786 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:04:46.786 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:04:46.786 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:04:46.786 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:04:46.786 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:04:46.786 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:04:46.786 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:04:46.786 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:04:46.787 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:04:46.787 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:04:46.787 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:04:46.791 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-01-29 02:04:47.274 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-01-29 02:04:47.310 [DEBUG] fake_trx.py:278 (BTS@172.18.28.20:5700) Recv FAKE_TOA cmd
2026-01-29 02:04:47.312 [DEBUG] fake_trx.py:297 (BTS@172.18.28.20:5700) Recv FAKE_RSSI cmd
2026-01-29 02:04:47.312 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:04:47.314 [DEBUG] fake_trx.py:322 (BTS@172.18.28.20:5700) Recv FAKE_CI cmd
2026-01-29 02:04:47.743 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-01-29 02:04:47.789 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:04:47.789 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 02:04:47.789 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:04:47.789 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:04:48.212 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-01-29 02:04:48.689 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-01-29 02:04:48.790 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:04:48.790 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 02:04:48.790 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:04:48.790 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:04:49.167 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-01-29 02:04:49.645 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-01-29 02:04:49.791 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:04:49.791 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:04:49.791 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 02:04:49.791 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:04:50.123 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-01-29 02:04:50.324 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 02:04:50.325 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 02:04:50.325 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 02:04:50.326 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:04:50.326 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 02:04:50.326 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 02:04:50.326 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.28.22:6700) Recv POWERON CMD
2026-01-29 02:04:50.326 [INFO] ctrl_if_trx.py:109 (MS@172.18.28.22:6700) Starting transceiver...
2026-01-29 02:04:50.600 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-01-29 02:04:50.792 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 02:04:50.793 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:04:50.793 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:04:50.793 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:04:51.078 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-01-29 02:04:51.556 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-01-29 02:04:51.793 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 02:04:51.793 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:04:51.793 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:04:51.794 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:04:52.034 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-01-29 02:04:52.512 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-01-29 02:04:52.636 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 02:04:52.636 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 02:04:52.637 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:04:52.638 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 02:04:52.638 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:04:52.638 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:04:52.638 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:04:52.639 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 02:04:52.639 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:04:52.639 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:04:52.639 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.28.20:5700) Recv POWEROFF cmd
2026-01-29 02:04:52.639 [INFO] ctrl_if_trx.py:117 (BTS@172.18.28.20:5700) Stopping transceiver...
2026-01-29 02:04:52.639 [INFO] transceiver.py:246 Stopping clock generator
2026-01-29 02:04:52.639 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:04:57.643 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.28.20:5700) Recv POWEROFF cmd
2026-01-29 02:04:57.643 [INFO] ctrl_if_trx.py:117 (BTS@172.18.28.20:5700) Stopping transceiver...
2026-01-29 02:04:57.645 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:04:57.645 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:04:57.646 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:04:57.646 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 02:04:57.653 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 02:04:57.654 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.28.20:5700) Recv SETFORMAT cmd
2026-01-29 02:04:57.654 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.28.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:04:57.654 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.28.20:5700) Recv SETFORMAT cmd
2026-01-29 02:04:57.654 [INFO] ctrl_if_trx.py:201 (BTS@172.18.28.20:5700) TRXD header version 1 -> 1
2026-01-29 02:04:57.657 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.28.20:5700/1) Recv RXTUNE cmd
2026-01-29 02:04:57.657 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.28.20:5700/1) Recv TXTUNE cmd
2026-01-29 02:04:57.658 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.28.20:5700/1) Recv SETFORMAT cmd
2026-01-29 02:04:57.658 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.28.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:04:57.658 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:04:57.659 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.28.20:5700/1) Recv NOMTXPOWER cmd
2026-01-29 02:04:57.659 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.28.20:5700/1) Recv SETFORMAT cmd
2026-01-29 02:04:57.659 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.28.20:5700/1) TRXD header version 1 -> 1
2026-01-29 02:04:57.660 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.28.20:5700/2) Recv RXTUNE cmd
2026-01-29 02:04:57.661 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.28.20:5700/2) Recv TXTUNE cmd
2026-01-29 02:04:57.661 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.28.20:5700/2) Recv SETFORMAT cmd
2026-01-29 02:04:57.661 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.28.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:04:57.661 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.28.20:5700/2) Recv NOMTXPOWER cmd
2026-01-29 02:04:57.661 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:04:57.661 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.28.20:5700/2) Recv SETFORMAT cmd
2026-01-29 02:04:57.661 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.28.20:5700/2) TRXD header version 1 -> 1
2026-01-29 02:04:57.664 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.28.20:5700/3) Recv RXTUNE cmd
2026-01-29 02:04:57.664 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.28.20:5700/3) Recv TXTUNE cmd
2026-01-29 02:04:57.664 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.28.20:5700/3) Recv SETFORMAT cmd
2026-01-29 02:04:57.664 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.28.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:04:57.664 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:04:57.664 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.28.20:5700/3) Recv NOMTXPOWER cmd
2026-01-29 02:04:57.664 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.28.20:5700/3) Recv SETFORMAT cmd
2026-01-29 02:04:57.664 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.28.20:5700/3) TRXD header version 1 -> 1
2026-01-29 02:04:57.667 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.28.20:5700) Recv RXTUNE cmd
2026-01-29 02:04:57.667 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETTSC
2026-01-29 02:04:57.667 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETTSC
2026-01-29 02:04:57.667 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETTSC
2026-01-29 02:04:57.667 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.28.20:5700) Recv TXTUNE cmd
2026-01-29 02:04:57.667 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETRXGAIN
2026-01-29 02:04:57.667 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETRXGAIN
2026-01-29 02:04:57.667 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETRXGAIN
2026-01-29 02:04:57.667 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETTSC
2026-01-29 02:04:57.667 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:04:57.667 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:04:57.667 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:04:57.667 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.28.20:5700) Recv NOMTXPOWER cmd
2026-01-29 02:04:57.667 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:04:57.667 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:04:57.667 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:04:57.667 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.28.20:5700) Recv POWERON CMD
2026-01-29 02:04:57.667 [INFO] ctrl_if_trx.py:109 (BTS@172.18.28.20:5700) Starting transceiver...
2026-01-29 02:04:57.668 [INFO] transceiver.py:243 Starting clock generator
2026-01-29 02:04:57.668 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-01-29 02:04:57.668 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:04:57.668 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:04:57.668 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:04:57.668 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETRXGAIN
2026-01-29 02:04:57.668 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:04:57.668 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:04:57.668 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:04:57.668 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:04:57.668 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:04:57.668 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:04:57.668 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:04:57.668 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:04:57.668 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:04:57.668 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:04:57.668 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:04:57.668 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:04:57.668 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:04:57.668 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:04:57.668 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:04:57.668 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:04:57.669 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:04:57.669 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:04:57.669 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:04:57.669 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:04:57.669 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:04:57.669 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:04:57.669 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:04:57.672 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-01-29 02:04:58.155 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-01-29 02:04:58.194 [DEBUG] fake_trx.py:278 (BTS@172.18.28.20:5700) Recv FAKE_TOA cmd
2026-01-29 02:04:58.196 [DEBUG] fake_trx.py:297 (BTS@172.18.28.20:5700) Recv FAKE_RSSI cmd
2026-01-29 02:04:58.197 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:04:58.198 [DEBUG] fake_trx.py:322 (BTS@172.18.28.20:5700) Recv FAKE_CI cmd
2026-01-29 02:04:58.226 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 02:04:58.226 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 02:04:58.226 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 02:04:58.241 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 02:04:58.241 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:04:58.241 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:04:58.241 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:04:58.245 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 02:04:58.246 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:04:58.246 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:04:58.246 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:04:58.246 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.28.20:5700) Recv POWEROFF cmd
2026-01-29 02:04:58.246 [INFO] ctrl_if_trx.py:117 (BTS@172.18.28.20:5700) Stopping transceiver...
2026-01-29 02:04:58.246 [INFO] transceiver.py:246 Stopping clock generator
2026-01-29 02:04:58.246 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=122 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:04:58.246 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=122 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:04:58.246 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=122 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:04:58.246 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=122 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:04:58.246 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=122 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:04:58.246 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=122 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:04:58.246 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=123 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:04:58.246 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=123 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:04:58.246 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=123 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:04:58.246 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=123 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:04:58.246 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=123 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:04:58.246 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=123 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:04:58.246 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=123 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:04:58.246 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=123 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:05:03.244 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.28.20:5700) Recv POWEROFF cmd
2026-01-29 02:05:03.245 [INFO] ctrl_if_trx.py:117 (BTS@172.18.28.20:5700) Stopping transceiver...
2026-01-29 02:05:03.249 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:05:03.249 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:05:03.249 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:05:03.249 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 02:05:03.257 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 02:05:03.259 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.28.20:5700) Recv SETFORMAT cmd
2026-01-29 02:05:03.259 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.28.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:05:03.259 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.28.20:5700) Recv SETFORMAT cmd
2026-01-29 02:05:03.259 [INFO] ctrl_if_trx.py:201 (BTS@172.18.28.20:5700) TRXD header version 1 -> 1
2026-01-29 02:05:03.264 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.28.20:5700/1) Recv RXTUNE cmd
2026-01-29 02:05:03.264 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.28.20:5700/1) Recv TXTUNE cmd
2026-01-29 02:05:03.264 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.28.20:5700/1) Recv SETFORMAT cmd
2026-01-29 02:05:03.264 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.28.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:05:03.265 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:05:03.265 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.28.20:5700/1) Recv NOMTXPOWER cmd
2026-01-29 02:05:03.265 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.28.20:5700/1) Recv SETFORMAT cmd
2026-01-29 02:05:03.265 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.28.20:5700/1) TRXD header version 1 -> 1
2026-01-29 02:05:03.268 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.28.20:5700/2) Recv RXTUNE cmd
2026-01-29 02:05:03.268 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.28.20:5700/2) Recv TXTUNE cmd
2026-01-29 02:05:03.268 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.28.20:5700/2) Recv SETFORMAT cmd
2026-01-29 02:05:03.268 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.28.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:05:03.268 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:05:03.268 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.28.20:5700/2) Recv NOMTXPOWER cmd
2026-01-29 02:05:03.269 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.28.20:5700/2) Recv SETFORMAT cmd
2026-01-29 02:05:03.269 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.28.20:5700/2) TRXD header version 1 -> 1
2026-01-29 02:05:03.271 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.28.20:5700/3) Recv RXTUNE cmd
2026-01-29 02:05:03.271 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.28.20:5700/3) Recv TXTUNE cmd
2026-01-29 02:05:03.271 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.28.20:5700/3) Recv SETFORMAT cmd
2026-01-29 02:05:03.271 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.28.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:05:03.271 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:05:03.271 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.28.20:5700/3) Recv NOMTXPOWER cmd
2026-01-29 02:05:03.272 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.28.20:5700/3) Recv SETFORMAT cmd
2026-01-29 02:05:03.272 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.28.20:5700/3) TRXD header version 1 -> 1
2026-01-29 02:05:03.275 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.28.20:5700) Recv RXTUNE cmd
2026-01-29 02:05:03.275 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETTSC
2026-01-29 02:05:03.275 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETTSC
2026-01-29 02:05:03.275 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETTSC
2026-01-29 02:05:03.275 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.28.20:5700) Recv TXTUNE cmd
2026-01-29 02:05:03.275 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETRXGAIN
2026-01-29 02:05:03.275 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETRXGAIN
2026-01-29 02:05:03.276 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETRXGAIN
2026-01-29 02:05:03.276 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETTSC
2026-01-29 02:05:03.276 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:05:03.276 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:05:03.276 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:05:03.276 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.28.20:5700) Recv NOMTXPOWER cmd
2026-01-29 02:05:03.276 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:05:03.276 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:05:03.276 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:05:03.276 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.28.20:5700) Recv POWERON CMD
2026-01-29 02:05:03.276 [INFO] ctrl_if_trx.py:109 (BTS@172.18.28.20:5700) Starting transceiver...
2026-01-29 02:05:03.276 [INFO] transceiver.py:243 Starting clock generator
2026-01-29 02:05:03.276 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-01-29 02:05:03.276 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:05:03.276 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:05:03.276 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:05:03.276 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETRXGAIN
2026-01-29 02:05:03.276 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:05:03.277 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:05:03.277 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:05:03.277 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:05:03.277 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:05:03.277 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:05:03.277 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:05:03.277 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:05:03.277 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:05:03.277 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:05:03.277 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:05:03.277 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:05:03.277 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:05:03.278 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:05:03.278 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:05:03.278 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:05:03.278 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:05:03.278 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:05:03.278 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:05:03.278 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:05:03.278 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:05:03.278 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:05:03.279 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:05:03.281 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-01-29 02:05:03.764 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-01-29 02:05:03.806 [DEBUG] fake_trx.py:278 (BTS@172.18.28.20:5700) Recv FAKE_TOA cmd
2026-01-29 02:05:03.809 [DEBUG] fake_trx.py:297 (BTS@172.18.28.20:5700) Recv FAKE_RSSI cmd
2026-01-29 02:05:03.811 [DEBUG] fake_trx.py:322 (BTS@172.18.28.20:5700) Recv FAKE_CI cmd
2026-01-29 02:05:03.812 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:05:03.839 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 02:05:03.839 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 02:05:03.839 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 02:05:03.857 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:05:03.858 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:05:03.869 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 02:05:03.870 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:05:03.870 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:05:03.870 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:05:03.872 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 02:05:03.872 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:05:03.872 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:05:03.872 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:05:03.872 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.28.20:5700) Recv POWEROFF cmd
2026-01-29 02:05:03.872 [INFO] ctrl_if_trx.py:117 (BTS@172.18.28.20:5700) Stopping transceiver...
2026-01-29 02:05:03.872 [INFO] transceiver.py:246 Stopping clock generator
2026-01-29 02:05:03.872 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=127 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:05:03.872 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=127 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:05:03.872 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=127 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:05:03.872 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=127 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:05:03.872 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=127 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:05:03.872 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=127 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:05:08.871 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.28.20:5700) Recv POWEROFF cmd
2026-01-29 02:05:08.871 [INFO] ctrl_if_trx.py:117 (BTS@172.18.28.20:5700) Stopping transceiver...
2026-01-29 02:05:08.873 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:05:08.874 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:05:08.875 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:05:08.875 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 02:05:08.878 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 02:05:08.879 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.28.20:5700) Recv SETFORMAT cmd
2026-01-29 02:05:08.879 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.28.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:05:08.879 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.28.20:5700) Recv SETFORMAT cmd
2026-01-29 02:05:08.879 [INFO] ctrl_if_trx.py:201 (BTS@172.18.28.20:5700) TRXD header version 1 -> 1
2026-01-29 02:05:08.881 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.28.20:5700/1) Recv RXTUNE cmd
2026-01-29 02:05:08.881 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.28.20:5700/1) Recv TXTUNE cmd
2026-01-29 02:05:08.881 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.28.20:5700/1) Recv SETFORMAT cmd
2026-01-29 02:05:08.881 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.28.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:05:08.882 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:05:08.882 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.28.20:5700/1) Recv NOMTXPOWER cmd
2026-01-29 02:05:08.882 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.28.20:5700/1) Recv SETFORMAT cmd
2026-01-29 02:05:08.882 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.28.20:5700/1) TRXD header version 1 -> 1
2026-01-29 02:05:08.883 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.28.20:5700/2) Recv RXTUNE cmd
2026-01-29 02:05:08.883 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.28.20:5700/2) Recv TXTUNE cmd
2026-01-29 02:05:08.884 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.28.20:5700/2) Recv SETFORMAT cmd
2026-01-29 02:05:08.884 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.28.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:05:08.884 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:05:08.884 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.28.20:5700/2) Recv NOMTXPOWER cmd
2026-01-29 02:05:08.884 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.28.20:5700/2) Recv SETFORMAT cmd
2026-01-29 02:05:08.884 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.28.20:5700/2) TRXD header version 1 -> 1
2026-01-29 02:05:08.885 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.28.20:5700/3) Recv RXTUNE cmd
2026-01-29 02:05:08.885 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.28.20:5700/3) Recv TXTUNE cmd
2026-01-29 02:05:08.885 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.28.20:5700/3) Recv SETFORMAT cmd
2026-01-29 02:05:08.885 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.28.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:05:08.885 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:05:08.885 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.28.20:5700/3) Recv NOMTXPOWER cmd
2026-01-29 02:05:08.886 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.28.20:5700/3) Recv SETFORMAT cmd
2026-01-29 02:05:08.886 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.28.20:5700/3) TRXD header version 1 -> 1
2026-01-29 02:05:08.887 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.28.20:5700) Recv RXTUNE cmd
2026-01-29 02:05:08.887 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETTSC
2026-01-29 02:05:08.887 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETTSC
2026-01-29 02:05:08.887 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETTSC
2026-01-29 02:05:08.887 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.28.20:5700) Recv TXTUNE cmd
2026-01-29 02:05:08.888 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETRXGAIN
2026-01-29 02:05:08.888 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETRXGAIN
2026-01-29 02:05:08.888 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETRXGAIN
2026-01-29 02:05:08.888 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETTSC
2026-01-29 02:05:08.888 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:05:08.888 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:05:08.888 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:05:08.888 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.28.20:5700) Recv NOMTXPOWER cmd
2026-01-29 02:05:08.888 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:05:08.888 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:05:08.888 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:05:08.888 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.28.20:5700) Recv POWERON CMD
2026-01-29 02:05:08.888 [INFO] ctrl_if_trx.py:109 (BTS@172.18.28.20:5700) Starting transceiver...
2026-01-29 02:05:08.888 [INFO] transceiver.py:243 Starting clock generator
2026-01-29 02:05:08.888 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-01-29 02:05:08.888 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:05:08.888 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:05:08.888 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:05:08.888 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETRXGAIN
2026-01-29 02:05:08.888 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:05:08.888 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:05:08.888 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:05:08.888 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:05:08.888 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:05:08.888 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:05:08.888 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:05:08.888 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:05:08.888 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:05:08.888 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:05:08.888 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:05:08.889 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:05:08.889 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:05:08.889 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:05:08.889 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:05:08.889 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:05:08.889 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:05:08.889 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:05:08.889 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:05:08.889 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:05:08.889 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:05:08.889 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:05:08.889 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:05:08.893 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-01-29 02:05:09.377 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-01-29 02:05:09.412 [DEBUG] fake_trx.py:278 (BTS@172.18.28.20:5700) Recv FAKE_TOA cmd
2026-01-29 02:05:09.414 [DEBUG] fake_trx.py:297 (BTS@172.18.28.20:5700) Recv FAKE_RSSI cmd
2026-01-29 02:05:09.414 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:05:09.415 [DEBUG] fake_trx.py:322 (BTS@172.18.28.20:5700) Recv FAKE_CI cmd
2026-01-29 02:05:09.435 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 02:05:09.435 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 02:05:09.436 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 02:05:09.450 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:05:09.450 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:05:09.453 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:05:09.460 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 02:05:09.461 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:05:09.461 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:05:09.461 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:05:09.463 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 02:05:09.463 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:05:09.463 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:05:09.463 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:05:09.463 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.28.20:5700) Recv POWEROFF cmd
2026-01-29 02:05:09.463 [INFO] ctrl_if_trx.py:117 (BTS@172.18.28.20:5700) Stopping transceiver...
2026-01-29 02:05:09.463 [INFO] transceiver.py:246 Stopping clock generator
2026-01-29 02:05:09.463 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=122 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:05:09.464 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=122 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:05:09.464 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=122 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:05:09.464 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=122 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:05:14.467 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.28.20:5700) Recv POWEROFF cmd
2026-01-29 02:05:14.467 [INFO] ctrl_if_trx.py:117 (BTS@172.18.28.20:5700) Stopping transceiver...
2026-01-29 02:05:14.467 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:05:14.467 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:05:14.467 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:05:14.467 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 02:05:14.475 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 02:05:14.477 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.28.20:5700) Recv SETFORMAT cmd
2026-01-29 02:05:14.477 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.28.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:05:14.477 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.28.20:5700) Recv SETFORMAT cmd
2026-01-29 02:05:14.478 [INFO] ctrl_if_trx.py:201 (BTS@172.18.28.20:5700) TRXD header version 1 -> 1
2026-01-29 02:05:14.481 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.28.20:5700/1) Recv RXTUNE cmd
2026-01-29 02:05:14.481 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.28.20:5700/1) Recv TXTUNE cmd
2026-01-29 02:05:14.481 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.28.20:5700/1) Recv SETFORMAT cmd
2026-01-29 02:05:14.482 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.28.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:05:14.482 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:05:14.482 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.28.20:5700/1) Recv NOMTXPOWER cmd
2026-01-29 02:05:14.482 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.28.20:5700/1) Recv SETFORMAT cmd
2026-01-29 02:05:14.482 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.28.20:5700/1) TRXD header version 1 -> 1
2026-01-29 02:05:14.485 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.28.20:5700/2) Recv RXTUNE cmd
2026-01-29 02:05:14.485 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.28.20:5700/2) Recv TXTUNE cmd
2026-01-29 02:05:14.486 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.28.20:5700/2) Recv SETFORMAT cmd
2026-01-29 02:05:14.486 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.28.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:05:14.486 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:05:14.486 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.28.20:5700/2) Recv NOMTXPOWER cmd
2026-01-29 02:05:14.487 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.28.20:5700/2) Recv SETFORMAT cmd
2026-01-29 02:05:14.487 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.28.20:5700/2) TRXD header version 1 -> 1
2026-01-29 02:05:14.488 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.28.20:5700/3) Recv RXTUNE cmd
2026-01-29 02:05:14.488 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.28.20:5700/3) Recv TXTUNE cmd
2026-01-29 02:05:14.488 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.28.20:5700/3) Recv SETFORMAT cmd
2026-01-29 02:05:14.488 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.28.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:05:14.489 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:05:14.489 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.28.20:5700/3) Recv NOMTXPOWER cmd
2026-01-29 02:05:14.489 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.28.20:5700/3) Recv SETFORMAT cmd
2026-01-29 02:05:14.489 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.28.20:5700/3) TRXD header version 1 -> 1
2026-01-29 02:05:14.492 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.28.20:5700) Recv RXTUNE cmd
2026-01-29 02:05:14.492 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETTSC
2026-01-29 02:05:14.492 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETTSC
2026-01-29 02:05:14.492 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETTSC
2026-01-29 02:05:14.492 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.28.20:5700) Recv TXTUNE cmd
2026-01-29 02:05:14.492 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETRXGAIN
2026-01-29 02:05:14.492 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETRXGAIN
2026-01-29 02:05:14.492 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETRXGAIN
2026-01-29 02:05:14.492 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETTSC
2026-01-29 02:05:14.492 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:05:14.492 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:05:14.492 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.28.20:5700) Recv NOMTXPOWER cmd
2026-01-29 02:05:14.492 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:05:14.492 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:05:14.493 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:05:14.493 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.28.20:5700) Recv POWERON CMD
2026-01-29 02:05:14.493 [INFO] ctrl_if_trx.py:109 (BTS@172.18.28.20:5700) Starting transceiver...
2026-01-29 02:05:14.493 [INFO] transceiver.py:243 Starting clock generator
2026-01-29 02:05:14.493 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-01-29 02:05:14.493 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:05:14.493 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:05:14.493 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:05:14.493 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETRXGAIN
2026-01-29 02:05:14.493 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:05:14.493 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:05:14.493 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:05:14.493 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:05:14.493 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:05:14.493 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:05:14.494 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:05:14.494 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:05:14.494 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:05:14.494 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:05:14.494 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:05:14.494 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:05:14.494 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:05:14.494 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:05:14.494 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:05:14.494 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:05:14.494 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:05:14.494 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:05:14.494 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:05:14.494 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:05:14.494 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:05:14.494 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:05:14.494 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:05:14.494 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:05:14.498 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-01-29 02:05:14.981 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-01-29 02:05:15.022 [DEBUG] fake_trx.py:278 (BTS@172.18.28.20:5700) Recv FAKE_TOA cmd
2026-01-29 02:05:15.025 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:05:15.025 [DEBUG] fake_trx.py:297 (BTS@172.18.28.20:5700) Recv FAKE_RSSI cmd
2026-01-29 02:05:15.027 [DEBUG] fake_trx.py:322 (BTS@172.18.28.20:5700) Recv FAKE_CI cmd
2026-01-29 02:05:15.050 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 02:05:15.050 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 02:05:15.050 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 02:05:15.067 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:05:15.068 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:05:15.071 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:05:15.073 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:05:15.076 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:05:15.079 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:05:15.082 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:05:15.087 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:05:15.091 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:05:15.103 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 02:05:15.103 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:05:15.103 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:05:15.103 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:05:15.109 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 02:05:15.109 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:05:15.110 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:05:15.110 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:05:15.110 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.28.20:5700) Recv POWEROFF cmd
2026-01-29 02:05:15.110 [INFO] ctrl_if_trx.py:117 (BTS@172.18.28.20:5700) Stopping transceiver...
2026-01-29 02:05:15.110 [INFO] transceiver.py:246 Stopping clock generator
2026-01-29 02:05:15.110 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=130 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:05:15.111 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=130 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:05:20.107 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.28.20:5700) Recv POWEROFF cmd
2026-01-29 02:05:20.107 [INFO] ctrl_if_trx.py:117 (BTS@172.18.28.20:5700) Stopping transceiver...
2026-01-29 02:05:20.109 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:05:20.110 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:05:20.110 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:05:20.110 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 02:05:20.119 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 02:05:20.121 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.28.20:5700) Recv SETFORMAT cmd
2026-01-29 02:05:20.121 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.28.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:05:20.121 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.28.20:5700) Recv SETFORMAT cmd
2026-01-29 02:05:20.121 [INFO] ctrl_if_trx.py:201 (BTS@172.18.28.20:5700) TRXD header version 1 -> 1
2026-01-29 02:05:20.127 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.28.20:5700/1) Recv RXTUNE cmd
2026-01-29 02:05:20.127 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.28.20:5700/1) Recv TXTUNE cmd
2026-01-29 02:05:20.128 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.28.20:5700/1) Recv SETFORMAT cmd
2026-01-29 02:05:20.128 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.28.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:05:20.128 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:05:20.129 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.28.20:5700/1) Recv NOMTXPOWER cmd
2026-01-29 02:05:20.129 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.28.20:5700/1) Recv SETFORMAT cmd
2026-01-29 02:05:20.129 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.28.20:5700/1) TRXD header version 1 -> 1
2026-01-29 02:05:20.130 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.28.20:5700/2) Recv RXTUNE cmd
2026-01-29 02:05:20.131 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.28.20:5700/2) Recv TXTUNE cmd
2026-01-29 02:05:20.131 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.28.20:5700/2) Recv SETFORMAT cmd
2026-01-29 02:05:20.131 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.28.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:05:20.132 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:05:20.132 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.28.20:5700/2) Recv NOMTXPOWER cmd
2026-01-29 02:05:20.132 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.28.20:5700/2) Recv SETFORMAT cmd
2026-01-29 02:05:20.132 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.28.20:5700/2) TRXD header version 1 -> 1
2026-01-29 02:05:20.134 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.28.20:5700/3) Recv RXTUNE cmd
2026-01-29 02:05:20.134 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.28.20:5700/3) Recv TXTUNE cmd
2026-01-29 02:05:20.134 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.28.20:5700/3) Recv SETFORMAT cmd
2026-01-29 02:05:20.134 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.28.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:05:20.134 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:05:20.134 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.28.20:5700/3) Recv NOMTXPOWER cmd
2026-01-29 02:05:20.134 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.28.20:5700/3) Recv SETFORMAT cmd
2026-01-29 02:05:20.134 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.28.20:5700/3) TRXD header version 1 -> 1
2026-01-29 02:05:20.137 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.28.20:5700) Recv RXTUNE cmd
2026-01-29 02:05:20.137 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETTSC
2026-01-29 02:05:20.137 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETTSC
2026-01-29 02:05:20.137 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETTSC
2026-01-29 02:05:20.137 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.28.20:5700) Recv TXTUNE cmd
2026-01-29 02:05:20.137 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETRXGAIN
2026-01-29 02:05:20.137 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETRXGAIN
2026-01-29 02:05:20.138 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETRXGAIN
2026-01-29 02:05:20.138 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETTSC
2026-01-29 02:05:20.138 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:05:20.138 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:05:20.138 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:05:20.138 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.28.20:5700) Recv NOMTXPOWER cmd
2026-01-29 02:05:20.138 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:05:20.138 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:05:20.138 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:05:20.138 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.28.20:5700) Recv POWERON CMD
2026-01-29 02:05:20.138 [INFO] ctrl_if_trx.py:109 (BTS@172.18.28.20:5700) Starting transceiver...
2026-01-29 02:05:20.138 [INFO] transceiver.py:243 Starting clock generator
2026-01-29 02:05:20.138 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-01-29 02:05:20.138 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:05:20.138 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:05:20.138 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:05:20.138 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETRXGAIN
2026-01-29 02:05:20.138 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:05:20.139 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:05:20.139 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:05:20.139 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:05:20.139 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:05:20.139 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:05:20.139 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:05:20.139 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:05:20.139 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:05:20.139 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:05:20.139 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:05:20.139 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:05:20.139 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:05:20.139 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:05:20.139 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:05:20.139 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:05:20.139 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:05:20.139 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:05:20.139 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:05:20.139 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:05:20.139 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:05:20.139 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:05:20.139 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:05:20.143 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-01-29 02:05:20.625 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-01-29 02:05:20.663 [DEBUG] fake_trx.py:278 (BTS@172.18.28.20:5700) Recv FAKE_TOA cmd
2026-01-29 02:05:20.666 [DEBUG] fake_trx.py:297 (BTS@172.18.28.20:5700) Recv FAKE_RSSI cmd
2026-01-29 02:05:20.667 [DEBUG] fake_trx.py:322 (BTS@172.18.28.20:5700) Recv FAKE_CI cmd
2026-01-29 02:05:20.668 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:05:20.670 [DEBUG] fake_trx.py:382 (BTS@172.18.28.20:5700) Recv FAKE_TRXC_DELAY cmd
2026-01-29 02:05:20.670 [INFO] fake_trx.py:385 (BTS@172.18.28.20:5700) Artificial TRXC delay set to 200
2026-01-29 02:05:20.670 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD FAKE_TRXC_DELAY
2026-01-29 02:05:20.895 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:05:21.097 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:05:21.104 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-01-29 02:05:21.298 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:05:21.298 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:05:21.298 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:05:21.298 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:05:21.499 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 02:05:21.587 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-01-29 02:05:22.066 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-01-29 02:05:22.104 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:05:22.304 [DEBUG] fake_trx.py:382 (BTS@172.18.28.20:5700) Recv FAKE_TRXC_DELAY cmd
2026-01-29 02:05:22.305 [INFO] fake_trx.py:385 (BTS@172.18.28.20:5700) Artificial TRXC delay set to 0
2026-01-29 02:05:22.305 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD FAKE_TRXC_DELAY
2026-01-29 02:05:22.305 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:05:22.305 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:05:22.305 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:05:22.305 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:05:22.311 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 02:05:22.311 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:05:22.312 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:05:22.312 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:05:22.312 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 02:05:22.313 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:05:22.313 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:05:22.313 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:05:22.313 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.28.20:5700) Recv POWEROFF cmd
2026-01-29 02:05:22.313 [INFO] ctrl_if_trx.py:117 (BTS@172.18.28.20:5700) Stopping transceiver...
2026-01-29 02:05:22.313 [INFO] transceiver.py:246 Stopping clock generator
2026-01-29 02:05:22.313 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=463 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:05:22.313 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=463 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:05:22.313 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=463 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:05:22.313 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=463 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:05:22.313 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=463 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:05:22.313 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=463 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:05:22.313 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=463 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:05:22.313 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=463 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:05:27.318 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.28.20:5700) Recv POWEROFF cmd
2026-01-29 02:05:27.318 [INFO] ctrl_if_trx.py:117 (BTS@172.18.28.20:5700) Stopping transceiver...
2026-01-29 02:05:27.318 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:05:27.318 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:05:27.318 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:05:27.318 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 02:05:27.328 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 02:05:27.330 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.28.20:5700) Recv SETFORMAT cmd
2026-01-29 02:05:27.330 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.28.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:05:27.330 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.28.20:5700) Recv SETFORMAT cmd
2026-01-29 02:05:27.331 [INFO] ctrl_if_trx.py:201 (BTS@172.18.28.20:5700) TRXD header version 1 -> 1
2026-01-29 02:05:27.335 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.28.20:5700/1) Recv RXTUNE cmd
2026-01-29 02:05:27.335 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.28.20:5700/1) Recv TXTUNE cmd
2026-01-29 02:05:27.336 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.28.20:5700/1) Recv SETFORMAT cmd
2026-01-29 02:05:27.336 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.28.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:05:27.336 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:05:27.337 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.28.20:5700/1) Recv NOMTXPOWER cmd
2026-01-29 02:05:27.337 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.28.20:5700/1) Recv SETFORMAT cmd
2026-01-29 02:05:27.337 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.28.20:5700/1) TRXD header version 1 -> 1
2026-01-29 02:05:27.338 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.28.20:5700/2) Recv RXTUNE cmd
2026-01-29 02:05:27.339 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.28.20:5700/2) Recv TXTUNE cmd
2026-01-29 02:05:27.339 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.28.20:5700/2) Recv SETFORMAT cmd
2026-01-29 02:05:27.339 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.28.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:05:27.339 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:05:27.339 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.28.20:5700/2) Recv NOMTXPOWER cmd
2026-01-29 02:05:27.340 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.28.20:5700/2) Recv SETFORMAT cmd
2026-01-29 02:05:27.340 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.28.20:5700/2) TRXD header version 1 -> 1
2026-01-29 02:05:27.342 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.28.20:5700/3) Recv RXTUNE cmd
2026-01-29 02:05:27.342 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.28.20:5700/3) Recv TXTUNE cmd
2026-01-29 02:05:27.342 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.28.20:5700/3) Recv SETFORMAT cmd
2026-01-29 02:05:27.342 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.28.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:05:27.342 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:05:27.342 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.28.20:5700/3) Recv NOMTXPOWER cmd
2026-01-29 02:05:27.342 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.28.20:5700/3) Recv SETFORMAT cmd
2026-01-29 02:05:27.342 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.28.20:5700/3) TRXD header version 1 -> 1
2026-01-29 02:05:27.345 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.28.20:5700) Recv RXTUNE cmd
2026-01-29 02:05:27.345 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETTSC
2026-01-29 02:05:27.345 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETTSC
2026-01-29 02:05:27.346 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETTSC
2026-01-29 02:05:27.346 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.28.20:5700) Recv TXTUNE cmd
2026-01-29 02:05:27.346 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETRXGAIN
2026-01-29 02:05:27.346 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETRXGAIN
2026-01-29 02:05:27.346 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETRXGAIN
2026-01-29 02:05:27.346 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETTSC
2026-01-29 02:05:27.346 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:05:27.346 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:05:27.346 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.28.20:5700) Recv NOMTXPOWER cmd
2026-01-29 02:05:27.346 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:05:27.346 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:05:27.346 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:05:27.346 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.28.20:5700) Recv POWERON CMD
2026-01-29 02:05:27.346 [INFO] ctrl_if_trx.py:109 (BTS@172.18.28.20:5700) Starting transceiver...
2026-01-29 02:05:27.346 [INFO] transceiver.py:243 Starting clock generator
2026-01-29 02:05:27.346 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-01-29 02:05:27.347 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:05:27.347 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:05:27.347 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:05:27.347 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETRXGAIN
2026-01-29 02:05:27.347 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:05:27.347 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:05:27.347 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:05:27.347 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:05:27.347 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:05:27.347 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:05:27.347 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:05:27.347 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:05:27.347 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:05:27.347 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:05:27.347 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:05:27.347 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:05:27.347 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:05:27.347 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:05:27.348 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:05:27.348 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:05:27.348 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:05:27.348 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:05:27.348 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:05:27.348 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:05:27.348 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:05:27.348 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:05:27.348 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:05:27.348 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:05:27.351 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-01-29 02:05:27.836 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-01-29 02:05:27.878 [DEBUG] fake_trx.py:278 (BTS@172.18.28.20:5700) Recv FAKE_TOA cmd
2026-01-29 02:05:27.880 [DEBUG] fake_trx.py:297 (BTS@172.18.28.20:5700) Recv FAKE_RSSI cmd
2026-01-29 02:05:27.883 [DEBUG] fake_trx.py:322 (BTS@172.18.28.20:5700) Recv FAKE_CI cmd
2026-01-29 02:05:27.884 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:05:27.885 [DEBUG] fake_trx.py:382 (BTS@172.18.28.20:5700) Recv FAKE_TRXC_DELAY cmd
2026-01-29 02:05:27.885 [INFO] fake_trx.py:385 (BTS@172.18.28.20:5700) Artificial TRXC delay set to 200
2026-01-29 02:05:27.885 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD FAKE_TRXC_DELAY
2026-01-29 02:05:28.110 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:05:28.313 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:05:28.314 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-01-29 02:05:28.514 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:05:28.514 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:05:28.514 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:05:28.515 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:05:28.715 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:05:28.792 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-01-29 02:05:28.915 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:05:29.116 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:05:29.273 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-01-29 02:05:29.317 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:05:29.517 [DEBUG] fake_trx.py:382 (BTS@172.18.28.20:5700) Recv FAKE_TRXC_DELAY cmd
2026-01-29 02:05:29.518 [INFO] fake_trx.py:385 (BTS@172.18.28.20:5700) Artificial TRXC delay set to 0
2026-01-29 02:05:29.518 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD FAKE_TRXC_DELAY
2026-01-29 02:05:29.518 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:05:29.518 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:05:29.518 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:05:29.518 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:05:29.518 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:05:29.519 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 02:05:29.519 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:05:29.520 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:05:29.520 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:05:29.520 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:05:29.521 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:05:29.521 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:05:29.521 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:05:29.521 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:05:29.524 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 02:05:29.524 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:05:29.524 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:05:29.524 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:05:29.524 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 02:05:29.524 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:05:29.524 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:05:29.524 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.28.20:5700) Recv POWEROFF cmd
2026-01-29 02:05:29.524 [INFO] ctrl_if_trx.py:117 (BTS@172.18.28.20:5700) Stopping transceiver...
2026-01-29 02:05:29.524 [INFO] transceiver.py:246 Stopping clock generator
2026-01-29 02:05:29.525 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:05:29.525 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=464 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:05:29.525 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=464 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:05:29.525 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=464 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:05:29.525 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=464 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:05:29.525 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=464 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:05:29.525 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=464 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:05:29.525 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=464 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:05:34.531 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.28.20:5700) Recv POWEROFF cmd
2026-01-29 02:05:34.531 [INFO] ctrl_if_trx.py:117 (BTS@172.18.28.20:5700) Stopping transceiver...
2026-01-29 02:05:34.531 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:05:34.531 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:05:34.531 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:05:34.531 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 02:05:34.539 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 02:05:34.541 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.28.20:5700) Recv SETFORMAT cmd
2026-01-29 02:05:34.541 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.28.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:05:34.542 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.28.20:5700) Recv SETFORMAT cmd
2026-01-29 02:05:34.542 [INFO] ctrl_if_trx.py:201 (BTS@172.18.28.20:5700) TRXD header version 1 -> 1
2026-01-29 02:05:34.547 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.28.20:5700/1) Recv RXTUNE cmd
2026-01-29 02:05:34.547 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.28.20:5700/1) Recv TXTUNE cmd
2026-01-29 02:05:34.548 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.28.20:5700/1) Recv SETFORMAT cmd
2026-01-29 02:05:34.548 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.28.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:05:34.549 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:05:34.549 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.28.20:5700/1) Recv NOMTXPOWER cmd
2026-01-29 02:05:34.549 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.28.20:5700/1) Recv SETFORMAT cmd
2026-01-29 02:05:34.550 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.28.20:5700/1) TRXD header version 1 -> 1
2026-01-29 02:05:34.552 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.28.20:5700/2) Recv RXTUNE cmd
2026-01-29 02:05:34.552 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.28.20:5700/2) Recv TXTUNE cmd
2026-01-29 02:05:34.553 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.28.20:5700/2) Recv SETFORMAT cmd
2026-01-29 02:05:34.553 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.28.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:05:34.553 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:05:34.554 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.28.20:5700/2) Recv NOMTXPOWER cmd
2026-01-29 02:05:34.554 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.28.20:5700/2) Recv SETFORMAT cmd
2026-01-29 02:05:34.554 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.28.20:5700/2) TRXD header version 1 -> 1
2026-01-29 02:05:34.555 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.28.20:5700/3) Recv RXTUNE cmd
2026-01-29 02:05:34.555 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.28.20:5700/3) Recv TXTUNE cmd
2026-01-29 02:05:34.556 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.28.20:5700/3) Recv SETFORMAT cmd
2026-01-29 02:05:34.556 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.28.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:05:34.556 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:05:34.556 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.28.20:5700/3) Recv NOMTXPOWER cmd
2026-01-29 02:05:34.556 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.28.20:5700/3) Recv SETFORMAT cmd
2026-01-29 02:05:34.556 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.28.20:5700/3) TRXD header version 1 -> 1
2026-01-29 02:05:34.558 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.28.20:5700) Recv RXTUNE cmd
2026-01-29 02:05:34.559 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETTSC
2026-01-29 02:05:34.559 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETTSC
2026-01-29 02:05:34.559 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETTSC
2026-01-29 02:05:34.559 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.28.20:5700) Recv TXTUNE cmd
2026-01-29 02:05:34.559 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETRXGAIN
2026-01-29 02:05:34.559 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETRXGAIN
2026-01-29 02:05:34.559 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETRXGAIN
2026-01-29 02:05:34.559 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETTSC
2026-01-29 02:05:34.559 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:05:34.559 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:05:34.559 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:05:34.559 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.28.20:5700) Recv NOMTXPOWER cmd
2026-01-29 02:05:34.559 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:05:34.559 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:05:34.559 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:05:34.559 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.28.20:5700) Recv POWERON CMD
2026-01-29 02:05:34.559 [INFO] ctrl_if_trx.py:109 (BTS@172.18.28.20:5700) Starting transceiver...
2026-01-29 02:05:34.559 [INFO] transceiver.py:243 Starting clock generator
2026-01-29 02:05:34.559 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-01-29 02:05:34.559 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:05:34.559 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:05:34.559 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:05:34.560 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETRXGAIN
2026-01-29 02:05:34.560 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:05:34.560 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:05:34.560 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:05:34.560 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:05:34.560 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:05:34.560 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:05:34.560 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:05:34.560 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:05:34.560 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:05:34.560 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:05:34.560 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:05:34.560 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:05:34.560 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:05:34.560 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:05:34.560 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:05:34.560 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:05:34.560 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:05:34.560 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:05:34.560 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:05:34.560 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:05:34.560 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:05:34.560 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:05:34.561 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:05:34.564 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-01-29 02:05:35.047 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-01-29 02:05:35.086 [DEBUG] fake_trx.py:278 (BTS@172.18.28.20:5700) Recv FAKE_TOA cmd
2026-01-29 02:05:35.089 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:05:35.089 [DEBUG] fake_trx.py:297 (BTS@172.18.28.20:5700) Recv FAKE_RSSI cmd
2026-01-29 02:05:35.093 [DEBUG] fake_trx.py:322 (BTS@172.18.28.20:5700) Recv FAKE_CI cmd
2026-01-29 02:05:35.115 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 02:05:35.115 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 02:05:35.115 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 02:05:35.128 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:05:35.131 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:05:35.137 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 02:05:35.137 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:05:35.137 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:05:35.138 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:05:35.141 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 02:05:35.141 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:05:35.141 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:05:35.141 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.28.20:5700) Recv POWEROFF cmd
2026-01-29 02:05:35.141 [INFO] ctrl_if_trx.py:117 (BTS@172.18.28.20:5700) Stopping transceiver...
2026-01-29 02:05:35.142 [INFO] transceiver.py:246 Stopping clock generator
2026-01-29 02:05:35.142 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:05:35.142 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=123 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:05:35.142 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=123 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:05:35.142 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=123 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:05:35.142 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=123 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:05:35.143 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=123 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:05:35.143 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=123 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:05:35.143 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=123 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:05:35.143 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=123 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:05:35.143 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=124 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:05:35.143 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=124 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:05:35.143 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=124 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:05:35.143 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=124 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:05:35.143 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=124 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:05:35.143 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=124 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:05:40.141 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.28.20:5700) Recv POWEROFF cmd
2026-01-29 02:05:40.141 [INFO] ctrl_if_trx.py:117 (BTS@172.18.28.20:5700) Stopping transceiver...
2026-01-29 02:05:40.143 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:05:40.144 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:05:40.145 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:05:40.146 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 02:05:40.154 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 02:05:40.155 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.28.20:5700) Recv SETFORMAT cmd
2026-01-29 02:05:40.155 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.28.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:05:40.155 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.28.20:5700) Recv SETFORMAT cmd
2026-01-29 02:05:40.155 [INFO] ctrl_if_trx.py:201 (BTS@172.18.28.20:5700) TRXD header version 1 -> 1
2026-01-29 02:05:40.158 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.28.20:5700/1) Recv RXTUNE cmd
2026-01-29 02:05:40.159 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.28.20:5700/1) Recv TXTUNE cmd
2026-01-29 02:05:40.159 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.28.20:5700/1) Recv SETFORMAT cmd
2026-01-29 02:05:40.159 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.28.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:05:40.159 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:05:40.160 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.28.20:5700/1) Recv NOMTXPOWER cmd
2026-01-29 02:05:40.160 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.28.20:5700/1) Recv SETFORMAT cmd
2026-01-29 02:05:40.160 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.28.20:5700/1) TRXD header version 1 -> 1
2026-01-29 02:05:40.161 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.28.20:5700/2) Recv RXTUNE cmd
2026-01-29 02:05:40.161 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.28.20:5700/2) Recv TXTUNE cmd
2026-01-29 02:05:40.161 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.28.20:5700/2) Recv SETFORMAT cmd
2026-01-29 02:05:40.161 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.28.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:05:40.162 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:05:40.162 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.28.20:5700/2) Recv NOMTXPOWER cmd
2026-01-29 02:05:40.162 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.28.20:5700/2) Recv SETFORMAT cmd
2026-01-29 02:05:40.162 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.28.20:5700/2) TRXD header version 1 -> 1
2026-01-29 02:05:40.164 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.28.20:5700/3) Recv RXTUNE cmd
2026-01-29 02:05:40.164 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.28.20:5700/3) Recv TXTUNE cmd
2026-01-29 02:05:40.164 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.28.20:5700/3) Recv SETFORMAT cmd
2026-01-29 02:05:40.164 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.28.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:05:40.164 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:05:40.164 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.28.20:5700/3) Recv NOMTXPOWER cmd
2026-01-29 02:05:40.164 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.28.20:5700/3) Recv SETFORMAT cmd
2026-01-29 02:05:40.164 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.28.20:5700/3) TRXD header version 1 -> 1
2026-01-29 02:05:40.167 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.28.20:5700) Recv RXTUNE cmd
2026-01-29 02:05:40.167 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETTSC
2026-01-29 02:05:40.167 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETTSC
2026-01-29 02:05:40.167 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETTSC
2026-01-29 02:05:40.167 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.28.20:5700) Recv TXTUNE cmd
2026-01-29 02:05:40.167 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETRXGAIN
2026-01-29 02:05:40.167 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETRXGAIN
2026-01-29 02:05:40.167 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETRXGAIN
2026-01-29 02:05:40.167 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETTSC
2026-01-29 02:05:40.167 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:05:40.167 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:05:40.167 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:05:40.167 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.28.20:5700) Recv NOMTXPOWER cmd
2026-01-29 02:05:40.167 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:05:40.167 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:05:40.167 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:05:40.167 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.28.20:5700) Recv POWERON CMD
2026-01-29 02:05:40.167 [INFO] ctrl_if_trx.py:109 (BTS@172.18.28.20:5700) Starting transceiver...
2026-01-29 02:05:40.167 [INFO] transceiver.py:243 Starting clock generator
2026-01-29 02:05:40.167 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-01-29 02:05:40.167 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:05:40.167 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:05:40.167 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:05:40.167 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETRXGAIN
2026-01-29 02:05:40.168 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:05:40.168 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:05:40.168 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:05:40.168 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:05:40.168 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:05:40.168 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:05:40.168 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:05:40.168 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:05:40.168 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:05:40.168 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:05:40.168 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:05:40.168 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:05:40.168 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:05:40.168 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:05:40.168 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:05:40.168 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:05:40.168 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:05:40.168 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:05:40.168 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:05:40.168 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:05:40.168 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:05:40.168 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:05:40.168 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:05:40.172 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-01-29 02:05:40.657 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-01-29 02:05:40.698 [DEBUG] fake_trx.py:278 (BTS@172.18.28.20:5700) Recv FAKE_TOA cmd
2026-01-29 02:05:40.701 [DEBUG] fake_trx.py:297 (BTS@172.18.28.20:5700) Recv FAKE_RSSI cmd
2026-01-29 02:05:40.702 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:05:40.704 [DEBUG] fake_trx.py:322 (BTS@172.18.28.20:5700) Recv FAKE_CI cmd
2026-01-29 02:05:40.731 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 02:05:40.732 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 02:05:40.732 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 02:05:40.740 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:05:40.744 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:05:40.748 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 02:05:40.749 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:05:40.749 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:05:40.749 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:05:40.752 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 02:05:40.752 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:05:40.752 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:05:40.752 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.28.20:5700) Recv POWEROFF cmd
2026-01-29 02:05:40.752 [INFO] ctrl_if_trx.py:117 (BTS@172.18.28.20:5700) Stopping transceiver...
2026-01-29 02:05:40.752 [INFO] transceiver.py:246 Stopping clock generator
2026-01-29 02:05:40.752 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:05:40.752 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=124 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:05:40.752 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=124 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:05:40.752 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=124 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:05:40.752 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=124 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:05:40.752 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=124 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:05:40.752 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=124 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:05:40.752 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=124 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:05:40.752 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=124 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:05:45.752 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.28.20:5700) Recv POWEROFF cmd
2026-01-29 02:05:45.752 [INFO] ctrl_if_trx.py:117 (BTS@172.18.28.20:5700) Stopping transceiver...
2026-01-29 02:05:45.754 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:05:45.755 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:05:45.756 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:05:45.757 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 02:05:45.765 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 02:05:45.766 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.28.20:5700) Recv SETFORMAT cmd
2026-01-29 02:05:45.766 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.28.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:05:45.767 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.28.20:5700) Recv SETFORMAT cmd
2026-01-29 02:05:45.767 [INFO] ctrl_if_trx.py:201 (BTS@172.18.28.20:5700) TRXD header version 1 -> 1
2026-01-29 02:05:45.770 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.28.20:5700/1) Recv RXTUNE cmd
2026-01-29 02:05:45.771 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.28.20:5700/1) Recv TXTUNE cmd
2026-01-29 02:05:45.771 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.28.20:5700/1) Recv SETFORMAT cmd
2026-01-29 02:05:45.771 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.28.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:05:45.772 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:05:45.772 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.28.20:5700/1) Recv NOMTXPOWER cmd
2026-01-29 02:05:45.772 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.28.20:5700/1) Recv SETFORMAT cmd
2026-01-29 02:05:45.772 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.28.20:5700/1) TRXD header version 1 -> 1
2026-01-29 02:05:45.773 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.28.20:5700/2) Recv RXTUNE cmd
2026-01-29 02:05:45.773 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.28.20:5700/2) Recv TXTUNE cmd
2026-01-29 02:05:45.773 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.28.20:5700/2) Recv SETFORMAT cmd
2026-01-29 02:05:45.774 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.28.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:05:45.774 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:05:45.774 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.28.20:5700/2) Recv NOMTXPOWER cmd
2026-01-29 02:05:45.774 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.28.20:5700/2) Recv SETFORMAT cmd
2026-01-29 02:05:45.774 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.28.20:5700/2) TRXD header version 1 -> 1
2026-01-29 02:05:45.776 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.28.20:5700/3) Recv RXTUNE cmd
2026-01-29 02:05:45.776 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.28.20:5700/3) Recv TXTUNE cmd
2026-01-29 02:05:45.776 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.28.20:5700/3) Recv SETFORMAT cmd
2026-01-29 02:05:45.776 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.28.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:05:45.776 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:05:45.776 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.28.20:5700/3) Recv NOMTXPOWER cmd
2026-01-29 02:05:45.776 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.28.20:5700/3) Recv SETFORMAT cmd
2026-01-29 02:05:45.776 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.28.20:5700/3) TRXD header version 1 -> 1
2026-01-29 02:05:45.779 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.28.20:5700) Recv RXTUNE cmd
2026-01-29 02:05:45.779 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETTSC
2026-01-29 02:05:45.779 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETTSC
2026-01-29 02:05:45.779 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETTSC
2026-01-29 02:05:45.779 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.28.20:5700) Recv TXTUNE cmd
2026-01-29 02:05:45.779 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETRXGAIN
2026-01-29 02:05:45.779 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETRXGAIN
2026-01-29 02:05:45.779 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETRXGAIN
2026-01-29 02:05:45.779 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETTSC
2026-01-29 02:05:45.779 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:05:45.779 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:05:45.779 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.28.20:5700) Recv NOMTXPOWER cmd
2026-01-29 02:05:45.779 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:05:45.779 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:05:45.779 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:05:45.779 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.28.20:5700) Recv POWERON CMD
2026-01-29 02:05:45.779 [INFO] ctrl_if_trx.py:109 (BTS@172.18.28.20:5700) Starting transceiver...
2026-01-29 02:05:45.779 [INFO] transceiver.py:243 Starting clock generator
2026-01-29 02:05:45.780 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-01-29 02:05:45.780 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:05:45.780 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:05:45.780 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:05:45.780 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETRXGAIN
2026-01-29 02:05:45.780 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:05:45.780 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:05:45.780 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:05:45.780 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:05:45.780 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:05:45.780 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:05:45.780 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:05:45.780 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:05:45.780 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:05:45.780 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:05:45.780 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:05:45.780 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:05:45.780 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:05:45.780 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:05:45.780 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:05:45.780 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:05:45.780 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:05:45.780 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:05:45.780 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:05:45.781 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:05:45.781 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:05:45.781 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:05:45.781 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:05:45.781 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:05:45.784 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-01-29 02:05:46.268 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-01-29 02:05:46.310 [DEBUG] fake_trx.py:278 (BTS@172.18.28.20:5700) Recv FAKE_TOA cmd
2026-01-29 02:05:46.313 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:05:46.313 [DEBUG] fake_trx.py:297 (BTS@172.18.28.20:5700) Recv FAKE_RSSI cmd
2026-01-29 02:05:46.315 [DEBUG] fake_trx.py:322 (BTS@172.18.28.20:5700) Recv FAKE_CI cmd
2026-01-29 02:05:46.342 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 02:05:46.342 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 02:05:46.343 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 02:05:46.347 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:05:46.348 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 02:05:46.348 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 02:05:46.348 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.28.22:6700) Recv POWERON CMD
2026-01-29 02:05:46.348 [INFO] ctrl_if_trx.py:109 (MS@172.18.28.22:6700) Starting transceiver...
2026-01-29 02:05:46.363 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:05:46.369 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 02:05:46.369 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 02:05:46.369 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:05:46.370 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:05:46.427 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:05:46.430 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:05:46.431 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 02:05:46.431 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 02:05:46.444 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 02:05:46.444 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 02:05:46.444 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 02:05:46.445 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:05:46.445 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 02:05:46.445 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 02:05:46.446 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.28.22:6700) Recv POWERON CMD
2026-01-29 02:05:46.446 [INFO] ctrl_if_trx.py:109 (MS@172.18.28.22:6700) Starting transceiver...
2026-01-29 02:05:46.449 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:05:46.450 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 02:05:46.450 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 02:05:46.451 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:05:46.451 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:05:46.743 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-01-29 02:05:46.782 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 02:05:46.782 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:05:46.784 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:05:46.786 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:05:47.222 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-01-29 02:05:47.699 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-01-29 02:05:47.783 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 02:05:47.783 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:05:47.785 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:05:47.787 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:05:48.177 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-01-29 02:05:48.655 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-01-29 02:05:48.784 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 02:05:48.784 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:05:48.786 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:05:48.788 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:05:49.133 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-01-29 02:05:49.453 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:05:49.455 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:05:49.457 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 02:05:49.457 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 02:05:49.477 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 02:05:49.477 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 02:05:49.477 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 02:05:49.478 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:05:49.478 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 02:05:49.478 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 02:05:49.478 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.28.22:6700) Recv POWERON CMD
2026-01-29 02:05:49.478 [INFO] ctrl_if_trx.py:109 (MS@172.18.28.22:6700) Starting transceiver...
2026-01-29 02:05:49.507 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:05:49.511 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 02:05:49.511 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 02:05:49.511 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:05:49.511 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:05:49.567 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:05:49.570 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:05:49.571 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 02:05:49.571 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 02:05:49.583 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 02:05:49.583 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 02:05:49.583 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 02:05:49.585 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:05:49.585 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 02:05:49.585 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 02:05:49.585 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.28.22:6700) Recv POWERON CMD
2026-01-29 02:05:49.585 [INFO] ctrl_if_trx.py:109 (MS@172.18.28.22:6700) Starting transceiver...
2026-01-29 02:05:49.602 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:05:49.605 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 02:05:49.605 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 02:05:49.606 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:05:49.606 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:05:49.610 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-01-29 02:05:49.785 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 02:05:49.785 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:05:49.787 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:05:49.788 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:05:50.087 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-01-29 02:05:50.565 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-01-29 02:05:50.786 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 02:05:50.786 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:05:50.787 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:05:50.790 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:05:51.043 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-01-29 02:05:51.521 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-01-29 02:05:51.998 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-01-29 02:05:52.476 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-01-29 02:05:52.609 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:05:52.612 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:05:52.614 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 02:05:52.614 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 02:05:52.634 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 02:05:52.634 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 02:05:52.634 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 02:05:52.635 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:05:52.635 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 02:05:52.635 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 02:05:52.635 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.28.22:6700) Recv POWERON CMD
2026-01-29 02:05:52.635 [INFO] ctrl_if_trx.py:109 (MS@172.18.28.22:6700) Starting transceiver...
2026-01-29 02:05:52.662 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:05:52.665 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 02:05:52.666 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 02:05:52.666 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:05:52.666 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:05:52.953 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-01-29 02:05:53.431 [DEBUG] clck_gen.py:113 IND CLOCK 1632
2026-01-29 02:05:53.909 [DEBUG] clck_gen.py:113 IND CLOCK 1734
2026-01-29 02:05:54.386 [DEBUG] clck_gen.py:113 IND CLOCK 1836
2026-01-29 02:05:54.864 [DEBUG] clck_gen.py:113 IND CLOCK 1938
2026-01-29 02:05:55.342 [DEBUG] clck_gen.py:113 IND CLOCK 2040
2026-01-29 02:05:55.670 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:05:55.673 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:05:55.675 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 02:05:55.675 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 02:05:55.697 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 02:05:55.697 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 02:05:55.697 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 02:05:55.698 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:05:55.698 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 02:05:55.699 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 02:05:55.699 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.28.22:6700) Recv POWERON CMD
2026-01-29 02:05:55.699 [INFO] ctrl_if_trx.py:109 (MS@172.18.28.22:6700) Starting transceiver...
2026-01-29 02:05:55.715 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:05:55.717 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 02:05:55.718 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 02:05:55.718 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:05:55.718 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:05:55.778 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:05:55.780 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:05:55.782 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 02:05:55.782 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 02:05:55.801 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 02:05:55.801 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 02:05:55.801 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 02:05:55.802 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:05:55.802 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 02:05:55.802 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 02:05:55.802 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.28.22:6700) Recv POWERON CMD
2026-01-29 02:05:55.802 [INFO] ctrl_if_trx.py:109 (MS@172.18.28.22:6700) Starting transceiver...
2026-01-29 02:05:55.810 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:05:55.811 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 02:05:55.811 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 02:05:55.811 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:05:55.811 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:05:55.819 [DEBUG] clck_gen.py:113 IND CLOCK 2142
2026-01-29 02:05:56.297 [DEBUG] clck_gen.py:113 IND CLOCK 2244
2026-01-29 02:05:56.774 [DEBUG] clck_gen.py:113 IND CLOCK 2346
2026-01-29 02:05:56.979 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:05:56.981 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:05:56.983 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 02:05:56.983 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 02:05:57.001 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 02:05:57.001 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 02:05:57.001 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 02:05:57.002 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:05:57.002 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 02:05:57.003 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 02:05:57.003 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.28.22:6700) Recv POWERON CMD
2026-01-29 02:05:57.003 [INFO] ctrl_if_trx.py:109 (MS@172.18.28.22:6700) Starting transceiver...
2026-01-29 02:05:57.007 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:05:57.008 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 02:05:57.008 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 02:05:57.008 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:05:57.008 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:05:57.077 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:05:57.080 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:05:57.081 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 02:05:57.081 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 02:05:57.099 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 02:05:57.099 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 02:05:57.099 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 02:05:57.100 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:05:57.100 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 02:05:57.100 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 02:05:57.100 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.28.22:6700) Recv POWERON CMD
2026-01-29 02:05:57.100 [INFO] ctrl_if_trx.py:109 (MS@172.18.28.22:6700) Starting transceiver...
2026-01-29 02:05:57.151 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:05:57.156 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 02:05:57.157 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 02:05:57.158 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:05:57.158 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:05:57.252 [DEBUG] clck_gen.py:113 IND CLOCK 2448
2026-01-29 02:05:57.729 [DEBUG] clck_gen.py:113 IND CLOCK 2550
2026-01-29 02:05:58.208 [DEBUG] clck_gen.py:113 IND CLOCK 2652
2026-01-29 02:05:58.686 [DEBUG] clck_gen.py:113 IND CLOCK 2754
2026-01-29 02:05:59.164 [DEBUG] clck_gen.py:113 IND CLOCK 2856
2026-01-29 02:05:59.642 [DEBUG] clck_gen.py:113 IND CLOCK 2958
2026-01-29 02:06:00.120 [DEBUG] clck_gen.py:113 IND CLOCK 3060
2026-01-29 02:06:00.160 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:06:00.163 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:06:00.165 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 02:06:00.166 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 02:06:00.191 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 02:06:00.191 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 02:06:00.191 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 02:06:00.193 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:06:00.193 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 02:06:00.193 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 02:06:00.193 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.28.22:6700) Recv POWERON CMD
2026-01-29 02:06:00.193 [INFO] ctrl_if_trx.py:109 (MS@172.18.28.22:6700) Starting transceiver...
2026-01-29 02:06:00.212 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:06:00.214 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 02:06:00.214 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 02:06:00.214 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:06:00.214 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:06:00.287 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:06:00.290 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:06:00.291 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 02:06:00.292 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 02:06:00.311 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 02:06:00.311 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 02:06:00.311 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 02:06:00.312 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:06:00.312 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 02:06:00.312 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 02:06:00.312 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.28.22:6700) Recv POWERON CMD
2026-01-29 02:06:00.312 [INFO] ctrl_if_trx.py:109 (MS@172.18.28.22:6700) Starting transceiver...
2026-01-29 02:06:00.358 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:06:00.363 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 02:06:00.363 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 02:06:00.363 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:06:00.364 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:06:00.597 [DEBUG] clck_gen.py:113 IND CLOCK 3162
2026-01-29 02:06:01.075 [DEBUG] clck_gen.py:113 IND CLOCK 3264
2026-01-29 02:06:01.553 [DEBUG] clck_gen.py:113 IND CLOCK 3366
2026-01-29 02:06:02.030 [DEBUG] clck_gen.py:113 IND CLOCK 3468
2026-01-29 02:06:02.508 [DEBUG] clck_gen.py:113 IND CLOCK 3570
2026-01-29 02:06:02.986 [DEBUG] clck_gen.py:113 IND CLOCK 3672
2026-01-29 02:06:03.367 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:06:03.370 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:06:03.371 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 02:06:03.372 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 02:06:03.389 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 02:06:03.389 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 02:06:03.389 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 02:06:03.390 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:06:03.390 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 02:06:03.390 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 02:06:03.390 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.28.22:6700) Recv POWERON CMD
2026-01-29 02:06:03.390 [INFO] ctrl_if_trx.py:109 (MS@172.18.28.22:6700) Starting transceiver...
2026-01-29 02:06:03.404 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:06:03.407 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 02:06:03.407 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 02:06:03.407 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:06:03.407 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:06:03.463 [DEBUG] clck_gen.py:113 IND CLOCK 3774
2026-01-29 02:06:03.940 [DEBUG] clck_gen.py:113 IND CLOCK 3876
2026-01-29 02:06:04.417 [DEBUG] clck_gen.py:113 IND CLOCK 3978
2026-01-29 02:06:04.894 [DEBUG] clck_gen.py:113 IND CLOCK 4080
2026-01-29 02:06:05.372 [DEBUG] clck_gen.py:113 IND CLOCK 4182
2026-01-29 02:06:05.850 [DEBUG] clck_gen.py:113 IND CLOCK 4284
2026-01-29 02:06:06.328 [DEBUG] clck_gen.py:113 IND CLOCK 4386
2026-01-29 02:06:06.410 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:06:06.413 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:06:06.415 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 02:06:06.415 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 02:06:06.435 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 02:06:06.435 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 02:06:06.435 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 02:06:06.437 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:06:06.437 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 02:06:06.437 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 02:06:06.437 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.28.22:6700) Recv POWERON CMD
2026-01-29 02:06:06.437 [INFO] ctrl_if_trx.py:109 (MS@172.18.28.22:6700) Starting transceiver...
2026-01-29 02:06:06.469 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:06:06.474 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 02:06:06.474 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 02:06:06.475 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:06:06.475 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:06:06.532 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:06:06.535 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:06:06.537 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 02:06:06.537 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 02:06:06.550 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 02:06:06.550 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 02:06:06.550 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 02:06:06.552 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:06:06.552 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 02:06:06.552 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 02:06:06.552 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.28.22:6700) Recv POWERON CMD
2026-01-29 02:06:06.552 [INFO] ctrl_if_trx.py:109 (MS@172.18.28.22:6700) Starting transceiver...
2026-01-29 02:06:06.561 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:06:06.563 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 02:06:06.563 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 02:06:06.563 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:06:06.563 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:06:06.805 [DEBUG] clck_gen.py:113 IND CLOCK 4488
2026-01-29 02:06:07.283 [DEBUG] clck_gen.py:113 IND CLOCK 4590
2026-01-29 02:06:07.451 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:06:07.454 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:06:07.455 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 02:06:07.456 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 02:06:07.470 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 02:06:07.470 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 02:06:07.470 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 02:06:07.471 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:06:07.471 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 02:06:07.471 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 02:06:07.471 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.28.22:6700) Recv POWERON CMD
2026-01-29 02:06:07.471 [INFO] ctrl_if_trx.py:109 (MS@172.18.28.22:6700) Starting transceiver...
2026-01-29 02:06:07.521 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:06:07.526 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 02:06:07.527 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 02:06:07.527 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:06:07.528 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:06:07.746 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:06:07.749 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:06:07.750 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 02:06:07.750 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 02:06:07.761 [DEBUG] clck_gen.py:113 IND CLOCK 4692
2026-01-29 02:06:07.766 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 02:06:07.766 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 02:06:07.766 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 02:06:07.768 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:06:07.768 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 02:06:07.768 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 02:06:07.768 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.28.22:6700) Recv POWERON CMD
2026-01-29 02:06:07.768 [INFO] ctrl_if_trx.py:109 (MS@172.18.28.22:6700) Starting transceiver...
2026-01-29 02:06:07.809 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:06:07.814 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 02:06:07.814 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 02:06:07.815 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:06:07.816 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:06:08.238 [DEBUG] clck_gen.py:113 IND CLOCK 4794
2026-01-29 02:06:08.715 [DEBUG] clck_gen.py:113 IND CLOCK 4896
2026-01-29 02:06:09.193 [DEBUG] clck_gen.py:113 IND CLOCK 4998
2026-01-29 02:06:09.671 [DEBUG] clck_gen.py:113 IND CLOCK 5100
2026-01-29 02:06:10.149 [DEBUG] clck_gen.py:113 IND CLOCK 5202
2026-01-29 02:06:10.627 [DEBUG] clck_gen.py:113 IND CLOCK 5304
2026-01-29 02:06:10.818 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:06:10.820 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:06:10.821 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 02:06:10.821 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 02:06:10.830 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 02:06:10.830 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 02:06:10.830 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 02:06:10.832 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:06:10.832 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 02:06:10.832 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 02:06:10.832 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.28.22:6700) Recv POWERON CMD
2026-01-29 02:06:10.832 [INFO] ctrl_if_trx.py:109 (MS@172.18.28.22:6700) Starting transceiver...
2026-01-29 02:06:10.864 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:06:10.869 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 02:06:10.869 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 02:06:10.869 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:06:10.869 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:06:11.089 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:06:11.092 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:06:11.093 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 02:06:11.093 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 02:06:11.103 [DEBUG] clck_gen.py:113 IND CLOCK 5406
2026-01-29 02:06:11.113 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 02:06:11.113 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 02:06:11.113 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 02:06:11.114 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:06:11.115 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 02:06:11.115 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 02:06:11.115 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.28.22:6700) Recv POWERON CMD
2026-01-29 02:06:11.115 [INFO] ctrl_if_trx.py:109 (MS@172.18.28.22:6700) Starting transceiver...
2026-01-29 02:06:11.151 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:06:11.153 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 02:06:11.153 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 02:06:11.153 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:06:11.153 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:06:11.581 [DEBUG] clck_gen.py:113 IND CLOCK 5508
2026-01-29 02:06:12.058 [DEBUG] clck_gen.py:113 IND CLOCK 5610
2026-01-29 02:06:12.536 [DEBUG] clck_gen.py:113 IND CLOCK 5712
2026-01-29 02:06:13.014 [DEBUG] clck_gen.py:113 IND CLOCK 5814
2026-01-29 02:06:13.492 [DEBUG] clck_gen.py:113 IND CLOCK 5916
2026-01-29 02:06:13.970 [DEBUG] clck_gen.py:113 IND CLOCK 6018
2026-01-29 02:06:14.155 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:06:14.158 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:06:14.159 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 02:06:14.160 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 02:06:14.178 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 02:06:14.178 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 02:06:14.178 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 02:06:14.180 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:06:14.180 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 02:06:14.180 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 02:06:14.180 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.28.22:6700) Recv POWERON CMD
2026-01-29 02:06:14.180 [INFO] ctrl_if_trx.py:109 (MS@172.18.28.22:6700) Starting transceiver...
2026-01-29 02:06:14.207 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:06:14.212 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 02:06:14.212 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 02:06:14.213 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:06:14.213 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:06:14.447 [DEBUG] clck_gen.py:113 IND CLOCK 6120
2026-01-29 02:06:14.926 [DEBUG] clck_gen.py:113 IND CLOCK 6222
2026-01-29 02:06:15.403 [DEBUG] clck_gen.py:113 IND CLOCK 6324
2026-01-29 02:06:15.881 [DEBUG] clck_gen.py:113 IND CLOCK 6426
2026-01-29 02:06:16.359 [DEBUG] clck_gen.py:113 IND CLOCK 6528
2026-01-29 02:06:16.837 [DEBUG] clck_gen.py:113 IND CLOCK 6630
2026-01-29 02:06:17.215 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:06:17.215 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:06:17.216 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 02:06:17.216 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 02:06:17.225 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 02:06:17.225 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 02:06:17.225 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 02:06:17.227 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:06:17.227 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 02:06:17.227 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 02:06:17.227 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.28.22:6700) Recv POWERON CMD
2026-01-29 02:06:17.227 [INFO] ctrl_if_trx.py:109 (MS@172.18.28.22:6700) Starting transceiver...
2026-01-29 02:06:17.259 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:06:17.263 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 02:06:17.264 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 02:06:17.264 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:06:17.264 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:06:17.301 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:06:17.304 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:06:17.306 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 02:06:17.306 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 02:06:17.316 [DEBUG] clck_gen.py:113 IND CLOCK 6732
2026-01-29 02:06:17.328 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 02:06:17.328 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 02:06:17.329 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 02:06:17.330 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:06:17.330 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 02:06:17.331 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 02:06:17.331 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.28.22:6700) Recv POWERON CMD
2026-01-29 02:06:17.331 [INFO] ctrl_if_trx.py:109 (MS@172.18.28.22:6700) Starting transceiver...
2026-01-29 02:06:17.365 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:06:17.370 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 02:06:17.371 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 02:06:17.371 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:06:17.371 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:06:17.793 [DEBUG] clck_gen.py:113 IND CLOCK 6834
2026-01-29 02:06:18.271 [DEBUG] clck_gen.py:113 IND CLOCK 6936
2026-01-29 02:06:18.311 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:06:18.313 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:06:18.315 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 02:06:18.315 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 02:06:18.325 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 02:06:18.325 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 02:06:18.325 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 02:06:18.326 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:06:18.326 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 02:06:18.327 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 02:06:18.327 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.28.22:6700) Recv POWERON CMD
2026-01-29 02:06:18.327 [INFO] ctrl_if_trx.py:109 (MS@172.18.28.22:6700) Starting transceiver...
2026-01-29 02:06:18.365 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:06:18.366 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 02:06:18.366 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 02:06:18.366 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:06:18.366 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:06:18.424 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:06:18.427 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:06:18.429 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 02:06:18.429 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 02:06:18.448 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 02:06:18.448 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 02:06:18.448 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 02:06:18.449 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:06:18.449 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 02:06:18.449 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 02:06:18.449 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.28.22:6700) Recv POWERON CMD
2026-01-29 02:06:18.449 [INFO] ctrl_if_trx.py:109 (MS@172.18.28.22:6700) Starting transceiver...
2026-01-29 02:06:18.452 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:06:18.453 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 02:06:18.453 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 02:06:18.453 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:06:18.453 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:06:18.748 [DEBUG] clck_gen.py:113 IND CLOCK 7038
2026-01-29 02:06:19.225 [DEBUG] clck_gen.py:113 IND CLOCK 7140
2026-01-29 02:06:19.703 [DEBUG] clck_gen.py:113 IND CLOCK 7242
2026-01-29 02:06:20.180 [DEBUG] clck_gen.py:113 IND CLOCK 7344
2026-01-29 02:06:20.658 [DEBUG] clck_gen.py:113 IND CLOCK 7446
2026-01-29 02:06:21.136 [DEBUG] clck_gen.py:113 IND CLOCK 7548
2026-01-29 02:06:21.456 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:06:21.458 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:06:21.460 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 02:06:21.460 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 02:06:21.480 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 02:06:21.480 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 02:06:21.480 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 02:06:21.481 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:06:21.481 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 02:06:21.481 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 02:06:21.481 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.28.22:6700) Recv POWERON CMD
2026-01-29 02:06:21.481 [INFO] ctrl_if_trx.py:109 (MS@172.18.28.22:6700) Starting transceiver...
2026-01-29 02:06:21.512 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:06:21.517 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 02:06:21.517 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 02:06:21.517 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:06:21.518 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:06:21.613 [DEBUG] clck_gen.py:113 IND CLOCK 7650
2026-01-29 02:06:21.767 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:06:21.770 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:06:21.772 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 02:06:21.772 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 02:06:21.790 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 02:06:21.790 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 02:06:21.791 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 02:06:21.792 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:06:21.792 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 02:06:21.792 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 02:06:21.792 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.28.22:6700) Recv POWERON CMD
2026-01-29 02:06:21.792 [INFO] ctrl_if_trx.py:109 (MS@172.18.28.22:6700) Starting transceiver...
2026-01-29 02:06:21.795 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:06:21.796 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 02:06:21.796 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 02:06:21.796 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:06:21.796 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:06:22.091 [DEBUG] clck_gen.py:113 IND CLOCK 7752
2026-01-29 02:06:22.570 [DEBUG] clck_gen.py:113 IND CLOCK 7854
2026-01-29 02:06:23.048 [DEBUG] clck_gen.py:113 IND CLOCK 7956
2026-01-29 02:06:23.526 [DEBUG] clck_gen.py:113 IND CLOCK 8058
2026-01-29 02:06:24.004 [DEBUG] clck_gen.py:113 IND CLOCK 8160
2026-01-29 02:06:24.482 [DEBUG] clck_gen.py:113 IND CLOCK 8262
2026-01-29 02:06:24.799 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:06:24.801 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:06:24.802 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 02:06:24.803 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 02:06:24.821 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 02:06:24.821 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 02:06:24.821 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 02:06:24.822 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:06:24.823 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 02:06:24.823 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 02:06:24.823 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.28.22:6700) Recv POWERON CMD
2026-01-29 02:06:24.823 [INFO] ctrl_if_trx.py:109 (MS@172.18.28.22:6700) Starting transceiver...
2026-01-29 02:06:24.857 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:06:24.862 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 02:06:24.863 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 02:06:24.863 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:06:24.863 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:06:24.957 [DEBUG] clck_gen.py:113 IND CLOCK 8364
2026-01-29 02:06:25.435 [DEBUG] clck_gen.py:113 IND CLOCK 8466
2026-01-29 02:06:25.913 [DEBUG] clck_gen.py:113 IND CLOCK 8568
2026-01-29 02:06:26.391 [DEBUG] clck_gen.py:113 IND CLOCK 8670
2026-01-29 02:06:26.869 [DEBUG] clck_gen.py:113 IND CLOCK 8772
2026-01-29 02:06:27.348 [DEBUG] clck_gen.py:113 IND CLOCK 8874
2026-01-29 02:06:27.826 [DEBUG] clck_gen.py:113 IND CLOCK 8976
2026-01-29 02:06:27.867 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:06:27.870 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:06:27.872 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 02:06:27.872 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 02:06:27.891 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 02:06:27.891 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 02:06:27.891 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 02:06:27.892 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:06:27.892 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 02:06:27.893 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 02:06:27.893 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.28.22:6700) Recv POWERON CMD
2026-01-29 02:06:27.893 [INFO] ctrl_if_trx.py:109 (MS@172.18.28.22:6700) Starting transceiver...
2026-01-29 02:06:27.920 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:06:27.925 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 02:06:27.925 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 02:06:27.925 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:06:27.926 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:06:27.979 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:06:27.982 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:06:27.983 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 02:06:27.983 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 02:06:28.002 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 02:06:28.003 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 02:06:28.003 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 02:06:28.004 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:06:28.004 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 02:06:28.004 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 02:06:28.004 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.28.22:6700) Recv POWERON CMD
2026-01-29 02:06:28.004 [INFO] ctrl_if_trx.py:109 (MS@172.18.28.22:6700) Starting transceiver...
2026-01-29 02:06:28.007 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:06:28.008 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 02:06:28.008 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 02:06:28.008 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:06:28.008 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:06:28.302 [DEBUG] clck_gen.py:113 IND CLOCK 9078
2026-01-29 02:06:28.766 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:06:28.780 [DEBUG] clck_gen.py:113 IND CLOCK 9180
2026-01-29 02:06:28.781 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:06:28.782 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 02:06:28.782 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 02:06:28.793 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 02:06:28.793 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:06:28.793 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:06:28.793 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:06:28.797 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 02:06:28.797 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:06:28.797 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:06:28.797 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.28.20:5700) Recv POWEROFF cmd
2026-01-29 02:06:28.797 [INFO] ctrl_if_trx.py:117 (BTS@172.18.28.20:5700) Stopping transceiver...
2026-01-29 02:06:28.797 [INFO] transceiver.py:246 Stopping clock generator
2026-01-29 02:06:28.797 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:06:28.797 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=9184 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:06:28.797 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=9184 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:06:28.797 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=9184 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:06:28.797 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=9184 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:06:33.797 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.28.20:5700) Recv POWEROFF cmd
2026-01-29 02:06:33.797 [INFO] ctrl_if_trx.py:117 (BTS@172.18.28.20:5700) Stopping transceiver...
2026-01-29 02:06:33.799 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:06:33.801 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:06:33.801 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:06:33.802 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 02:06:33.810 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 02:06:33.811 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.28.20:5700) Recv SETFORMAT cmd
2026-01-29 02:06:33.811 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.28.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:06:33.811 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.28.20:5700) Recv SETFORMAT cmd
2026-01-29 02:06:33.811 [INFO] ctrl_if_trx.py:201 (BTS@172.18.28.20:5700) TRXD header version 1 -> 1
2026-01-29 02:06:33.812 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.28.20:5700/1) Recv RXTUNE cmd
2026-01-29 02:06:33.813 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.28.20:5700/1) Recv TXTUNE cmd
2026-01-29 02:06:33.813 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.28.20:5700/1) Recv SETFORMAT cmd
2026-01-29 02:06:33.813 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.28.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:06:33.813 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:06:33.813 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.28.20:5700/1) Recv NOMTXPOWER cmd
2026-01-29 02:06:33.814 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.28.20:5700/1) Recv SETFORMAT cmd
2026-01-29 02:06:33.814 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.28.20:5700/1) TRXD header version 1 -> 1
2026-01-29 02:06:33.814 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.28.20:5700/2) Recv RXTUNE cmd
2026-01-29 02:06:33.814 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.28.20:5700/2) Recv TXTUNE cmd
2026-01-29 02:06:33.814 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.28.20:5700/2) Recv SETFORMAT cmd
2026-01-29 02:06:33.814 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.28.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:06:33.814 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:06:33.814 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.28.20:5700/2) Recv NOMTXPOWER cmd
2026-01-29 02:06:33.814 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.28.20:5700/2) Recv SETFORMAT cmd
2026-01-29 02:06:33.815 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.28.20:5700/2) TRXD header version 1 -> 1
2026-01-29 02:06:33.815 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.28.20:5700/3) Recv RXTUNE cmd
2026-01-29 02:06:33.815 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.28.20:5700/3) Recv TXTUNE cmd
2026-01-29 02:06:33.816 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.28.20:5700/3) Recv SETFORMAT cmd
2026-01-29 02:06:33.816 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.28.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:06:33.816 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:06:33.816 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.28.20:5700/3) Recv NOMTXPOWER cmd
2026-01-29 02:06:33.816 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.28.20:5700/3) Recv SETFORMAT cmd
2026-01-29 02:06:33.816 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.28.20:5700/3) TRXD header version 1 -> 1
2026-01-29 02:06:33.817 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.28.20:5700) Recv RXTUNE cmd
2026-01-29 02:06:33.817 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETTSC
2026-01-29 02:06:33.817 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETTSC
2026-01-29 02:06:33.817 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.28.20:5700) Recv TXTUNE cmd
2026-01-29 02:06:33.817 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETTSC
2026-01-29 02:06:33.817 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETRXGAIN
2026-01-29 02:06:33.817 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETRXGAIN
2026-01-29 02:06:33.817 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETTSC
2026-01-29 02:06:33.817 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETRXGAIN
2026-01-29 02:06:33.817 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:06:33.817 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:06:33.817 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.28.20:5700) Recv NOMTXPOWER cmd
2026-01-29 02:06:33.817 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:06:33.817 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:06:33.817 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:06:33.818 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.28.20:5700) Recv POWERON CMD
2026-01-29 02:06:33.818 [INFO] ctrl_if_trx.py:109 (BTS@172.18.28.20:5700) Starting transceiver...
2026-01-29 02:06:33.818 [INFO] transceiver.py:243 Starting clock generator
2026-01-29 02:06:33.818 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-01-29 02:06:33.818 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:06:33.818 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:06:33.818 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:06:33.818 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETRXGAIN
2026-01-29 02:06:33.818 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:06:33.818 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:06:33.818 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:06:33.818 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:06:33.818 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:06:33.818 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:06:33.818 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:06:33.818 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:06:33.818 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:06:33.818 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:06:33.818 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:06:33.818 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:06:33.818 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:06:33.818 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:06:33.818 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:06:33.818 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:06:33.818 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:06:33.818 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:06:33.818 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:06:33.818 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:06:33.818 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:06:33.818 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:06:33.818 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:06:33.818 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:06:33.822 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-01-29 02:06:34.307 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-01-29 02:06:34.341 [DEBUG] fake_trx.py:278 (BTS@172.18.28.20:5700) Recv FAKE_TOA cmd
2026-01-29 02:06:34.343 [DEBUG] fake_trx.py:297 (BTS@172.18.28.20:5700) Recv FAKE_RSSI cmd
2026-01-29 02:06:34.344 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:06:34.345 [DEBUG] fake_trx.py:322 (BTS@172.18.28.20:5700) Recv FAKE_CI cmd
2026-01-29 02:06:34.371 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 02:06:34.371 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 02:06:34.372 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 02:06:34.375 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:06:34.376 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 02:06:34.376 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 02:06:34.377 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.28.22:6700) Recv POWERON CMD
2026-01-29 02:06:34.377 [INFO] ctrl_if_trx.py:109 (MS@172.18.28.22:6700) Starting transceiver...
2026-01-29 02:06:34.403 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:06:34.409 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 02:06:34.409 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 02:06:34.410 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:06:34.410 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:06:34.464 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:06:34.467 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:06:34.469 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 02:06:34.469 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 02:06:34.486 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 02:06:34.486 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 02:06:34.486 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 02:06:34.487 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:06:34.487 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 02:06:34.487 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 02:06:34.487 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.28.22:6700) Recv POWERON CMD
2026-01-29 02:06:34.487 [INFO] ctrl_if_trx.py:109 (MS@172.18.28.22:6700) Starting transceiver...
2026-01-29 02:06:34.546 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:06:34.551 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 02:06:34.551 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 02:06:34.551 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:06:34.552 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:06:34.626 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:06:34.629 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:06:34.630 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 02:06:34.630 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 02:06:34.647 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 02:06:34.647 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 02:06:34.647 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 02:06:34.648 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:06:34.648 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 02:06:34.648 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 02:06:34.648 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.28.22:6700) Recv POWERON CMD
2026-01-29 02:06:34.648 [INFO] ctrl_if_trx.py:109 (MS@172.18.28.22:6700) Starting transceiver...
2026-01-29 02:06:34.683 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:06:34.688 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 02:06:34.688 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 02:06:34.689 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:06:34.689 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:06:34.784 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-01-29 02:06:34.820 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 02:06:34.820 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:06:34.820 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:06:34.822 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:06:34.940 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:06:34.943 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:06:34.944 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 02:06:34.944 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 02:06:34.959 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 02:06:34.959 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 02:06:34.959 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 02:06:34.960 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:06:34.960 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 02:06:34.961 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 02:06:34.961 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.28.22:6700) Recv POWERON CMD
2026-01-29 02:06:34.961 [INFO] ctrl_if_trx.py:109 (MS@172.18.28.22:6700) Starting transceiver...
2026-01-29 02:06:34.965 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:06:34.966 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 02:06:34.966 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 02:06:34.966 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:06:34.966 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:06:35.104 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:06:35.107 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:06:35.108 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 02:06:35.109 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 02:06:35.119 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 02:06:35.119 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:06:35.119 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:06:35.119 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:06:35.125 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 02:06:35.125 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:06:35.125 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:06:35.125 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.28.20:5700) Recv POWEROFF cmd
2026-01-29 02:06:35.125 [INFO] ctrl_if_trx.py:117 (BTS@172.18.28.20:5700) Stopping transceiver...
2026-01-29 02:06:35.125 [INFO] transceiver.py:246 Stopping clock generator
2026-01-29 02:06:35.126 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:06:35.126 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=279 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:06:35.126 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=279 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:06:35.126 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=279 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:06:35.126 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=279 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:06:35.126 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=279 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:06:35.126 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=279 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:06:35.126 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=279 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:06:35.126 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=279 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:06:35.127 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=280 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:06:35.127 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=280 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:06:40.120 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.28.20:5700) Recv POWEROFF cmd
2026-01-29 02:06:40.120 [INFO] ctrl_if_trx.py:117 (BTS@172.18.28.20:5700) Stopping transceiver...
2026-01-29 02:06:40.121 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:06:40.122 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:06:40.122 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:06:40.123 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 02:06:40.125 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 02:06:40.125 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.28.20:5700) Recv SETFORMAT cmd
2026-01-29 02:06:40.125 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.28.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:06:40.126 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.28.20:5700) Recv SETFORMAT cmd
2026-01-29 02:06:40.126 [INFO] ctrl_if_trx.py:201 (BTS@172.18.28.20:5700) TRXD header version 1 -> 1
2026-01-29 02:06:40.126 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.28.20:5700/1) Recv RXTUNE cmd
2026-01-29 02:06:40.126 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.28.20:5700/1) Recv TXTUNE cmd
2026-01-29 02:06:40.126 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.28.20:5700/1) Recv SETFORMAT cmd
2026-01-29 02:06:40.127 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.28.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:06:40.127 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:06:40.127 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.28.20:5700/1) Recv NOMTXPOWER cmd
2026-01-29 02:06:40.127 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.28.20:5700/1) Recv SETFORMAT cmd
2026-01-29 02:06:40.127 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.28.20:5700/1) TRXD header version 1 -> 1
2026-01-29 02:06:40.127 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.28.20:5700/2) Recv RXTUNE cmd
2026-01-29 02:06:40.127 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.28.20:5700/2) Recv TXTUNE cmd
2026-01-29 02:06:40.127 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.28.20:5700/2) Recv SETFORMAT cmd
2026-01-29 02:06:40.127 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.28.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:06:40.127 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:06:40.127 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.28.20:5700/2) Recv NOMTXPOWER cmd
2026-01-29 02:06:40.127 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.28.20:5700/2) Recv SETFORMAT cmd
2026-01-29 02:06:40.128 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.28.20:5700/2) TRXD header version 1 -> 1
2026-01-29 02:06:40.128 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.28.20:5700/3) Recv RXTUNE cmd
2026-01-29 02:06:40.128 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.28.20:5700/3) Recv TXTUNE cmd
2026-01-29 02:06:40.128 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.28.20:5700/3) Recv SETFORMAT cmd
2026-01-29 02:06:40.128 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.28.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:06:40.128 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:06:40.128 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.28.20:5700/3) Recv NOMTXPOWER cmd
2026-01-29 02:06:40.129 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.28.20:5700/3) Recv SETFORMAT cmd
2026-01-29 02:06:40.129 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.28.20:5700/3) TRXD header version 1 -> 1
2026-01-29 02:06:40.130 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.28.20:5700) Recv RXTUNE cmd
2026-01-29 02:06:40.130 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETTSC
2026-01-29 02:06:40.130 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETTSC
2026-01-29 02:06:40.130 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETTSC
2026-01-29 02:06:40.130 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.28.20:5700) Recv TXTUNE cmd
2026-01-29 02:06:40.130 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETRXGAIN
2026-01-29 02:06:40.130 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETRXGAIN
2026-01-29 02:06:40.130 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETRXGAIN
2026-01-29 02:06:40.130 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETTSC
2026-01-29 02:06:40.130 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:06:40.130 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:06:40.130 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.28.20:5700) Recv NOMTXPOWER cmd
2026-01-29 02:06:40.130 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:06:40.130 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:06:40.130 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:06:40.130 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.28.20:5700) Recv POWERON CMD
2026-01-29 02:06:40.130 [INFO] ctrl_if_trx.py:109 (BTS@172.18.28.20:5700) Starting transceiver...
2026-01-29 02:06:40.130 [INFO] transceiver.py:243 Starting clock generator
2026-01-29 02:06:40.130 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-01-29 02:06:40.130 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:06:40.130 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:06:40.131 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:06:40.131 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETRXGAIN
2026-01-29 02:06:40.131 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:06:40.131 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:06:40.131 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:06:40.131 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:06:40.131 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:06:40.131 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:06:40.131 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:06:40.131 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:06:40.131 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:06:40.131 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:06:40.131 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:06:40.131 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:06:40.131 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:06:40.131 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:06:40.131 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:06:40.131 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:06:40.131 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:06:40.131 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:06:40.131 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:06:40.131 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:06:40.131 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:06:40.131 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:06:40.131 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:06:40.131 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:06:40.135 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-01-29 02:06:40.618 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-01-29 02:06:40.652 [DEBUG] fake_trx.py:278 (BTS@172.18.28.20:5700) Recv FAKE_TOA cmd
2026-01-29 02:06:40.653 [DEBUG] fake_trx.py:297 (BTS@172.18.28.20:5700) Recv FAKE_RSSI cmd
2026-01-29 02:06:40.654 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:06:40.655 [DEBUG] fake_trx.py:322 (BTS@172.18.28.20:5700) Recv FAKE_CI cmd
2026-01-29 02:06:40.682 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 02:06:40.682 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 02:06:40.682 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 02:06:40.687 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:06:40.688 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 02:06:40.688 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 02:06:40.689 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.28.22:6700) Recv POWERON CMD
2026-01-29 02:06:40.689 [INFO] ctrl_if_trx.py:109 (MS@172.18.28.22:6700) Starting transceiver...
2026-01-29 02:06:40.715 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:06:40.722 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 02:06:40.722 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 02:06:40.722 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:06:40.722 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:06:41.096 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-01-29 02:06:41.133 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:06:41.133 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 02:06:41.134 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:06:41.136 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:06:41.573 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-01-29 02:06:41.590 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:06:41.593 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:06:41.594 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 02:06:41.594 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 02:06:41.612 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 02:06:41.612 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 02:06:41.612 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 02:06:41.613 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:06:41.613 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 02:06:41.613 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 02:06:41.613 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.28.22:6700) Recv POWERON CMD
2026-01-29 02:06:41.613 [INFO] ctrl_if_trx.py:109 (MS@172.18.28.22:6700) Starting transceiver...
2026-01-29 02:06:41.616 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:06:41.617 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 02:06:41.618 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 02:06:41.618 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:06:41.618 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:06:42.051 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-01-29 02:06:42.134 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 02:06:42.135 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:06:42.135 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:06:42.137 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:06:42.318 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:06:42.322 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:06:42.324 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 02:06:42.324 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 02:06:42.341 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 02:06:42.341 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 02:06:42.341 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 02:06:42.342 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:06:42.342 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 02:06:42.342 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 02:06:42.342 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.28.22:6700) Recv POWERON CMD
2026-01-29 02:06:42.342 [INFO] ctrl_if_trx.py:109 (MS@172.18.28.22:6700) Starting transceiver...
2026-01-29 02:06:42.380 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:06:42.384 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 02:06:42.384 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 02:06:42.385 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:06:42.385 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:06:42.489 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:06:42.492 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:06:42.494 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 02:06:42.494 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 02:06:42.512 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 02:06:42.512 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 02:06:42.512 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 02:06:42.514 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:06:42.514 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 02:06:42.514 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 02:06:42.514 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.28.22:6700) Recv POWERON CMD
2026-01-29 02:06:42.514 [INFO] ctrl_if_trx.py:109 (MS@172.18.28.22:6700) Starting transceiver...
2026-01-29 02:06:42.519 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:06:42.520 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 02:06:42.520 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 02:06:42.520 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:06:42.520 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:06:42.528 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-01-29 02:06:42.920 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:06:42.924 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:06:42.926 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 02:06:42.926 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 02:06:42.936 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 02:06:42.937 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:06:42.937 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:06:42.937 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:06:42.938 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 02:06:42.938 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:06:42.938 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:06:42.939 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:06:42.939 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.28.20:5700) Recv POWEROFF cmd
2026-01-29 02:06:42.939 [INFO] ctrl_if_trx.py:117 (BTS@172.18.28.20:5700) Stopping transceiver...
2026-01-29 02:06:42.939 [INFO] transceiver.py:246 Stopping clock generator
2026-01-29 02:06:42.939 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=601 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:06:42.939 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=601 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:06:42.939 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=601 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:06:42.939 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=601 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:06:42.939 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=601 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:06:42.939 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=601 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:06:42.939 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=601 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:06:47.942 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.28.20:5700) Recv POWEROFF cmd
2026-01-29 02:06:47.942 [INFO] ctrl_if_trx.py:117 (BTS@172.18.28.20:5700) Stopping transceiver...
2026-01-29 02:06:47.942 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:06:47.942 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 02:06:47.942 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:06:47.942 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:06:47.944 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 02:06:47.945 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.28.20:5700) Recv SETFORMAT cmd
2026-01-29 02:06:47.945 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.28.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:06:47.945 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.28.20:5700) Recv SETFORMAT cmd
2026-01-29 02:06:47.945 [INFO] ctrl_if_trx.py:201 (BTS@172.18.28.20:5700) TRXD header version 1 -> 1
2026-01-29 02:06:47.946 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.28.20:5700/1) Recv RXTUNE cmd
2026-01-29 02:06:47.946 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.28.20:5700/1) Recv TXTUNE cmd
2026-01-29 02:06:47.946 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.28.20:5700/1) Recv SETFORMAT cmd
2026-01-29 02:06:47.946 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.28.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:06:47.946 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:06:47.946 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.28.20:5700/1) Recv NOMTXPOWER cmd
2026-01-29 02:06:47.946 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.28.20:5700/1) Recv SETFORMAT cmd
2026-01-29 02:06:47.946 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.28.20:5700/1) TRXD header version 1 -> 1
2026-01-29 02:06:47.947 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.28.20:5700/2) Recv RXTUNE cmd
2026-01-29 02:06:47.947 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.28.20:5700/2) Recv TXTUNE cmd
2026-01-29 02:06:47.947 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.28.20:5700/2) Recv SETFORMAT cmd
2026-01-29 02:06:47.947 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.28.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:06:47.947 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:06:47.947 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.28.20:5700/2) Recv NOMTXPOWER cmd
2026-01-29 02:06:47.947 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.28.20:5700/2) Recv SETFORMAT cmd
2026-01-29 02:06:47.947 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.28.20:5700/2) TRXD header version 1 -> 1
2026-01-29 02:06:47.948 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.28.20:5700/3) Recv RXTUNE cmd
2026-01-29 02:06:47.948 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.28.20:5700/3) Recv TXTUNE cmd
2026-01-29 02:06:47.948 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.28.20:5700/3) Recv SETFORMAT cmd
2026-01-29 02:06:47.948 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.28.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:06:47.948 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:06:47.948 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.28.20:5700/3) Recv NOMTXPOWER cmd
2026-01-29 02:06:47.948 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.28.20:5700/3) Recv SETFORMAT cmd
2026-01-29 02:06:47.948 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.28.20:5700/3) TRXD header version 1 -> 1
2026-01-29 02:06:47.949 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.28.20:5700) Recv RXTUNE cmd
2026-01-29 02:06:47.949 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETTSC
2026-01-29 02:06:47.949 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETTSC
2026-01-29 02:06:47.949 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETTSC
2026-01-29 02:06:47.949 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.28.20:5700) Recv TXTUNE cmd
2026-01-29 02:06:47.949 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETRXGAIN
2026-01-29 02:06:47.949 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETRXGAIN
2026-01-29 02:06:47.949 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETRXGAIN
2026-01-29 02:06:47.950 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETTSC
2026-01-29 02:06:47.950 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:06:47.950 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:06:47.950 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.28.20:5700) Recv NOMTXPOWER cmd
2026-01-29 02:06:47.950 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:06:47.950 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:06:47.950 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:06:47.950 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.28.20:5700) Recv POWERON CMD
2026-01-29 02:06:47.950 [INFO] ctrl_if_trx.py:109 (BTS@172.18.28.20:5700) Starting transceiver...
2026-01-29 02:06:47.950 [INFO] transceiver.py:243 Starting clock generator
2026-01-29 02:06:47.950 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-01-29 02:06:47.950 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:06:47.950 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:06:47.950 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:06:47.950 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETRXGAIN
2026-01-29 02:06:47.950 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:06:47.950 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:06:47.950 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:06:47.950 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:06:47.950 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:06:47.950 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:06:47.950 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:06:47.950 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:06:47.950 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:06:47.950 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:06:47.950 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:06:47.950 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:06:47.950 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:06:47.950 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:06:47.950 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:06:47.950 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:06:47.950 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:06:47.950 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:06:47.950 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:06:47.950 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:06:47.950 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:06:47.950 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:06:47.951 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:06:47.951 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:06:47.954 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-01-29 02:06:48.438 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-01-29 02:06:48.471 [DEBUG] fake_trx.py:278 (BTS@172.18.28.20:5700) Recv FAKE_TOA cmd
2026-01-29 02:06:48.473 [DEBUG] fake_trx.py:297 (BTS@172.18.28.20:5700) Recv FAKE_RSSI cmd
2026-01-29 02:06:48.474 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:06:48.475 [DEBUG] fake_trx.py:322 (BTS@172.18.28.20:5700) Recv FAKE_CI cmd
2026-01-29 02:06:48.491 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 02:06:48.491 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 02:06:48.492 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 02:06:48.495 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:06:48.495 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 02:06:48.495 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 02:06:48.495 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.28.22:6700) Recv POWERON CMD
2026-01-29 02:06:48.495 [INFO] ctrl_if_trx.py:109 (MS@172.18.28.22:6700) Starting transceiver...
2026-01-29 02:06:48.535 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:06:48.540 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 02:06:48.540 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 02:06:48.540 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:06:48.541 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:06:48.705 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:06:48.708 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:06:48.710 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 02:06:48.710 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 02:06:48.728 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 02:06:48.728 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 02:06:48.728 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 02:06:48.729 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:06:48.729 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 02:06:48.729 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 02:06:48.729 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.28.22:6700) Recv POWERON CMD
2026-01-29 02:06:48.729 [INFO] ctrl_if_trx.py:109 (MS@172.18.28.22:6700) Starting transceiver...
2026-01-29 02:06:48.769 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:06:48.774 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 02:06:48.775 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 02:06:48.775 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:06:48.775 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:06:48.915 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-01-29 02:06:48.952 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 02:06:48.952 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:06:48.953 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:06:48.955 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:06:49.057 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:06:49.059 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:06:49.060 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 02:06:49.060 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 02:06:49.078 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 02:06:49.078 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 02:06:49.078 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 02:06:49.079 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:06:49.079 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 02:06:49.079 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 02:06:49.079 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.28.22:6700) Recv POWERON CMD
2026-01-29 02:06:49.079 [INFO] ctrl_if_trx.py:109 (MS@172.18.28.22:6700) Starting transceiver...
2026-01-29 02:06:49.098 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:06:49.101 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 02:06:49.101 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 02:06:49.101 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:06:49.101 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:06:49.376 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:06:49.379 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:06:49.380 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 02:06:49.380 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 02:06:49.388 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 02:06:49.388 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 02:06:49.389 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 02:06:49.389 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:06:49.389 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 02:06:49.389 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 02:06:49.389 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.28.22:6700) Recv POWERON CMD
2026-01-29 02:06:49.389 [INFO] ctrl_if_trx.py:109 (MS@172.18.28.22:6700) Starting transceiver...
2026-01-29 02:06:49.391 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-01-29 02:06:49.438 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:06:49.439 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 02:06:49.439 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 02:06:49.439 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:06:49.439 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:06:49.779 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:06:49.781 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:06:49.783 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 02:06:49.783 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 02:06:49.793 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 02:06:49.793 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:06:49.793 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:06:49.794 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:06:49.799 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 02:06:49.799 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:06:49.799 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:06:49.799 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:06:49.799 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.28.20:5700) Recv POWEROFF cmd
2026-01-29 02:06:49.799 [INFO] ctrl_if_trx.py:117 (BTS@172.18.28.20:5700) Stopping transceiver...
2026-01-29 02:06:49.800 [INFO] transceiver.py:246 Stopping clock generator
2026-01-29 02:06:49.800 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=395 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:06:49.800 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=395 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:06:54.797 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.28.20:5700) Recv POWEROFF cmd
2026-01-29 02:06:54.797 [INFO] ctrl_if_trx.py:117 (BTS@172.18.28.20:5700) Stopping transceiver...
2026-01-29 02:06:54.799 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:06:54.800 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:06:54.802 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:06:54.804 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 02:06:54.812 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 02:06:54.813 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.28.20:5700) Recv SETFORMAT cmd
2026-01-29 02:06:54.813 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.28.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:06:54.813 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.28.20:5700) Recv SETFORMAT cmd
2026-01-29 02:06:54.813 [INFO] ctrl_if_trx.py:201 (BTS@172.18.28.20:5700) TRXD header version 1 -> 1
2026-01-29 02:06:54.815 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.28.20:5700/1) Recv RXTUNE cmd
2026-01-29 02:06:54.815 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.28.20:5700/1) Recv TXTUNE cmd
2026-01-29 02:06:54.816 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.28.20:5700/1) Recv SETFORMAT cmd
2026-01-29 02:06:54.816 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.28.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:06:54.816 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:06:54.816 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.28.20:5700/1) Recv NOMTXPOWER cmd
2026-01-29 02:06:54.816 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.28.20:5700/1) Recv SETFORMAT cmd
2026-01-29 02:06:54.816 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.28.20:5700/1) TRXD header version 1 -> 1
2026-01-29 02:06:54.818 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.28.20:5700/2) Recv RXTUNE cmd
2026-01-29 02:06:54.818 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.28.20:5700/2) Recv TXTUNE cmd
2026-01-29 02:06:54.818 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.28.20:5700/2) Recv SETFORMAT cmd
2026-01-29 02:06:54.818 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.28.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:06:54.818 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:06:54.818 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.28.20:5700/2) Recv NOMTXPOWER cmd
2026-01-29 02:06:54.818 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.28.20:5700/2) Recv SETFORMAT cmd
2026-01-29 02:06:54.818 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.28.20:5700/2) TRXD header version 1 -> 1
2026-01-29 02:06:54.820 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.28.20:5700/3) Recv RXTUNE cmd
2026-01-29 02:06:54.820 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.28.20:5700/3) Recv TXTUNE cmd
2026-01-29 02:06:54.820 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.28.20:5700/3) Recv SETFORMAT cmd
2026-01-29 02:06:54.820 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.28.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:06:54.820 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:06:54.820 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.28.20:5700/3) Recv NOMTXPOWER cmd
2026-01-29 02:06:54.820 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.28.20:5700/3) Recv SETFORMAT cmd
2026-01-29 02:06:54.820 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.28.20:5700/3) TRXD header version 1 -> 1
2026-01-29 02:06:54.822 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.28.20:5700) Recv RXTUNE cmd
2026-01-29 02:06:54.822 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETTSC
2026-01-29 02:06:54.822 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETTSC
2026-01-29 02:06:54.822 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETTSC
2026-01-29 02:06:54.822 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.28.20:5700) Recv TXTUNE cmd
2026-01-29 02:06:54.822 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETRXGAIN
2026-01-29 02:06:54.822 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETRXGAIN
2026-01-29 02:06:54.823 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETRXGAIN
2026-01-29 02:06:54.823 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETTSC
2026-01-29 02:06:54.823 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:06:54.823 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:06:54.823 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:06:54.823 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.28.20:5700) Recv NOMTXPOWER cmd
2026-01-29 02:06:54.823 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:06:54.823 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:06:54.823 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:06:54.823 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.28.20:5700) Recv POWERON CMD
2026-01-29 02:06:54.823 [INFO] ctrl_if_trx.py:109 (BTS@172.18.28.20:5700) Starting transceiver...
2026-01-29 02:06:54.823 [INFO] transceiver.py:243 Starting clock generator
2026-01-29 02:06:54.823 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-01-29 02:06:54.823 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:06:54.823 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:06:54.823 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:06:54.823 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETRXGAIN
2026-01-29 02:06:54.823 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:06:54.823 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:06:54.823 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:06:54.823 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:06:54.823 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:06:54.823 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:06:54.823 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:06:54.823 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:06:54.823 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:06:54.823 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:06:54.824 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:06:54.824 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:06:54.824 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:06:54.824 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:06:54.824 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:06:54.824 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:06:54.824 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:06:54.824 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:06:54.824 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:06:54.824 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:06:54.824 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:06:54.824 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:06:54.824 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:06:54.828 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-01-29 02:06:55.310 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-01-29 02:06:55.348 [DEBUG] fake_trx.py:278 (BTS@172.18.28.20:5700) Recv FAKE_TOA cmd
2026-01-29 02:06:55.350 [DEBUG] fake_trx.py:297 (BTS@172.18.28.20:5700) Recv FAKE_RSSI cmd
2026-01-29 02:06:55.352 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:06:55.352 [DEBUG] fake_trx.py:322 (BTS@172.18.28.20:5700) Recv FAKE_CI cmd
2026-01-29 02:06:55.375 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 02:06:55.375 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 02:06:55.376 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 02:06:55.380 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:06:55.380 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 02:06:55.380 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 02:06:55.381 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.28.22:6700) Recv POWERON CMD
2026-01-29 02:06:55.381 [INFO] ctrl_if_trx.py:109 (MS@172.18.28.22:6700) Starting transceiver...
2026-01-29 02:06:55.406 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:06:55.413 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 02:06:55.413 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 02:06:55.414 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:06:55.414 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:06:55.577 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:06:55.580 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:06:55.582 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 02:06:55.582 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 02:06:55.599 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 02:06:55.600 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 02:06:55.600 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 02:06:55.601 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:06:55.601 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 02:06:55.601 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 02:06:55.601 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.28.22:6700) Recv POWERON CMD
2026-01-29 02:06:55.601 [INFO] ctrl_if_trx.py:109 (MS@172.18.28.22:6700) Starting transceiver...
2026-01-29 02:06:55.639 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:06:55.641 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 02:06:55.642 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 02:06:55.642 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:06:55.642 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:06:55.787 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-01-29 02:06:55.826 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 02:06:55.826 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:06:55.827 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:06:55.829 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:06:55.929 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:06:55.932 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:06:55.933 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 02:06:55.933 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 02:06:55.951 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 02:06:55.951 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 02:06:55.951 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 02:06:55.952 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:06:55.953 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 02:06:55.953 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 02:06:55.953 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.28.22:6700) Recv POWERON CMD
2026-01-29 02:06:55.953 [INFO] ctrl_if_trx.py:109 (MS@172.18.28.22:6700) Starting transceiver...
2026-01-29 02:06:55.970 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:06:55.975 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 02:06:55.975 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 02:06:55.975 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:06:55.975 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:06:56.249 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:06:56.252 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:06:56.254 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 02:06:56.254 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 02:06:56.264 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-01-29 02:06:56.272 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 02:06:56.272 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 02:06:56.272 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 02:06:56.273 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:06:56.273 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 02:06:56.273 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 02:06:56.273 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.28.22:6700) Recv POWERON CMD
2026-01-29 02:06:56.273 [INFO] ctrl_if_trx.py:109 (MS@172.18.28.22:6700) Starting transceiver...
2026-01-29 02:06:56.312 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:06:56.317 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 02:06:56.318 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 02:06:56.318 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:06:56.318 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:06:56.653 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:06:56.657 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:06:56.658 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 02:06:56.658 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 02:06:56.665 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 02:06:56.665 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:06:56.665 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:06:56.665 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:06:56.666 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 02:06:56.666 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:06:56.666 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:06:56.666 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.28.20:5700) Recv POWEROFF cmd
2026-01-29 02:06:56.666 [INFO] ctrl_if_trx.py:117 (BTS@172.18.28.20:5700) Stopping transceiver...
2026-01-29 02:06:56.666 [INFO] transceiver.py:246 Stopping clock generator
2026-01-29 02:06:56.666 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:06:56.666 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=395 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:06:56.666 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=395 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:06:56.666 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=395 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:06:56.666 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=395 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:06:56.666 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=395 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:06:56.666 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=395 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:06:56.666 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=395 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:07:01.669 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.28.20:5700) Recv POWEROFF cmd
2026-01-29 02:07:01.670 [INFO] ctrl_if_trx.py:117 (BTS@172.18.28.20:5700) Stopping transceiver...
2026-01-29 02:07:01.672 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:07:01.672 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:07:01.673 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:07:01.673 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 02:07:01.683 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 02:07:01.683 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.28.20:5700) Recv SETFORMAT cmd
2026-01-29 02:07:01.683 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.28.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:07:01.683 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.28.20:5700) Recv SETFORMAT cmd
2026-01-29 02:07:01.683 [INFO] ctrl_if_trx.py:201 (BTS@172.18.28.20:5700) TRXD header version 1 -> 1
2026-01-29 02:07:01.685 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.28.20:5700/1) Recv RXTUNE cmd
2026-01-29 02:07:01.685 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.28.20:5700/1) Recv TXTUNE cmd
2026-01-29 02:07:01.685 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.28.20:5700/1) Recv SETFORMAT cmd
2026-01-29 02:07:01.685 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.28.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:07:01.685 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:07:01.686 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.28.20:5700/1) Recv NOMTXPOWER cmd
2026-01-29 02:07:01.686 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.28.20:5700/1) Recv SETFORMAT cmd
2026-01-29 02:07:01.686 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.28.20:5700/1) TRXD header version 1 -> 1
2026-01-29 02:07:01.687 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.28.20:5700/2) Recv RXTUNE cmd
2026-01-29 02:07:01.687 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.28.20:5700/2) Recv TXTUNE cmd
2026-01-29 02:07:01.687 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.28.20:5700/2) Recv SETFORMAT cmd
2026-01-29 02:07:01.687 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.28.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:07:01.687 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:07:01.687 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.28.20:5700/2) Recv NOMTXPOWER cmd
2026-01-29 02:07:01.688 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.28.20:5700/2) Recv SETFORMAT cmd
2026-01-29 02:07:01.688 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.28.20:5700/2) TRXD header version 1 -> 1
2026-01-29 02:07:01.689 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.28.20:5700/3) Recv RXTUNE cmd
2026-01-29 02:07:01.689 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.28.20:5700/3) Recv TXTUNE cmd
2026-01-29 02:07:01.689 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.28.20:5700/3) Recv SETFORMAT cmd
2026-01-29 02:07:01.689 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.28.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:07:01.689 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:07:01.689 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.28.20:5700/3) Recv NOMTXPOWER cmd
2026-01-29 02:07:01.689 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.28.20:5700/3) Recv SETFORMAT cmd
2026-01-29 02:07:01.689 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.28.20:5700/3) TRXD header version 1 -> 1
2026-01-29 02:07:01.691 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.28.20:5700) Recv RXTUNE cmd
2026-01-29 02:07:01.691 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETTSC
2026-01-29 02:07:01.691 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETTSC
2026-01-29 02:07:01.691 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETTSC
2026-01-29 02:07:01.691 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.28.20:5700) Recv TXTUNE cmd
2026-01-29 02:07:01.691 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETRXGAIN
2026-01-29 02:07:01.691 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETRXGAIN
2026-01-29 02:07:01.691 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETRXGAIN
2026-01-29 02:07:01.691 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETTSC
2026-01-29 02:07:01.691 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:07:01.691 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:07:01.691 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.28.20:5700) Recv NOMTXPOWER cmd
2026-01-29 02:07:01.691 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:07:01.691 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:07:01.691 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:07:01.691 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.28.20:5700) Recv POWERON CMD
2026-01-29 02:07:01.691 [INFO] ctrl_if_trx.py:109 (BTS@172.18.28.20:5700) Starting transceiver...
2026-01-29 02:07:01.691 [INFO] transceiver.py:243 Starting clock generator
2026-01-29 02:07:01.691 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-01-29 02:07:01.691 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:07:01.691 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:07:01.691 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:07:01.691 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETRXGAIN
2026-01-29 02:07:01.691 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:07:01.691 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:07:01.691 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:07:01.691 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:07:01.691 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:07:01.691 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:07:01.691 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:07:01.691 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:07:01.691 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:07:01.691 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:07:01.692 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:07:01.692 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:07:01.692 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:07:01.692 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:07:01.692 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:07:01.692 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:07:01.692 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:07:01.692 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:07:01.692 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:07:01.692 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:07:01.692 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:07:01.692 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:07:01.692 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:07:01.692 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:07:01.696 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-01-29 02:07:02.180 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-01-29 02:07:02.216 [DEBUG] fake_trx.py:278 (BTS@172.18.28.20:5700) Recv FAKE_TOA cmd
2026-01-29 02:07:02.217 [DEBUG] fake_trx.py:297 (BTS@172.18.28.20:5700) Recv FAKE_RSSI cmd
2026-01-29 02:07:02.218 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:07:02.219 [DEBUG] fake_trx.py:322 (BTS@172.18.28.20:5700) Recv FAKE_CI cmd
2026-01-29 02:07:02.232 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 02:07:02.232 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 02:07:02.232 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 02:07:02.235 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:07:02.235 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 02:07:02.235 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 02:07:02.235 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.28.22:6700) Recv POWERON CMD
2026-01-29 02:07:02.235 [INFO] ctrl_if_trx.py:109 (MS@172.18.28.22:6700) Starting transceiver...
2026-01-29 02:07:02.276 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:07:02.282 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 02:07:02.282 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 02:07:02.282 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:07:02.283 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:07:02.657 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-01-29 02:07:02.693 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 02:07:02.694 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:07:02.694 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:07:02.696 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:07:03.135 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-01-29 02:07:03.612 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-01-29 02:07:03.695 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 02:07:03.695 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:07:03.695 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:07:03.696 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:07:04.090 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-01-29 02:07:04.135 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:07:04.138 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:07:04.139 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 02:07:04.139 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 02:07:04.156 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 02:07:04.156 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 02:07:04.156 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 02:07:04.157 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:07:04.157 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 02:07:04.157 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 02:07:04.157 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.28.22:6700) Recv POWERON CMD
2026-01-29 02:07:04.157 [INFO] ctrl_if_trx.py:109 (MS@172.18.28.22:6700) Starting transceiver...
2026-01-29 02:07:04.182 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:07:04.186 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 02:07:04.186 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 02:07:04.186 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:07:04.187 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:07:04.568 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-01-29 02:07:04.696 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:07:04.696 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:07:04.696 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 02:07:04.697 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:07:05.046 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-01-29 02:07:05.523 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-01-29 02:07:05.697 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 02:07:05.697 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:07:05.697 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:07:05.698 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:07:06.001 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-01-29 02:07:06.328 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:07:06.330 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:07:06.331 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 02:07:06.331 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 02:07:06.349 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 02:07:06.349 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 02:07:06.349 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 02:07:06.350 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:07:06.350 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 02:07:06.350 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 02:07:06.350 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.28.22:6700) Recv POWERON CMD
2026-01-29 02:07:06.350 [INFO] ctrl_if_trx.py:109 (MS@172.18.28.22:6700) Starting transceiver...
2026-01-29 02:07:06.376 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:07:06.381 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 02:07:06.381 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 02:07:06.381 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:07:06.381 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:07:06.478 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-01-29 02:07:06.698 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 02:07:06.698 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:07:06.698 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:07:06.698 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:07:06.956 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-01-29 02:07:07.433 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-01-29 02:07:07.911 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-01-29 02:07:07.949 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:07:07.952 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:07:07.954 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 02:07:07.954 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 02:07:07.972 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 02:07:07.972 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 02:07:07.972 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 02:07:07.973 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:07:07.973 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 02:07:07.974 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 02:07:07.974 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.28.22:6700) Recv POWERON CMD
2026-01-29 02:07:07.974 [INFO] ctrl_if_trx.py:109 (MS@172.18.28.22:6700) Starting transceiver...
2026-01-29 02:07:08.005 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:07:08.010 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 02:07:08.010 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 02:07:08.011 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:07:08.011 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:07:08.387 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-01-29 02:07:08.864 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-01-29 02:07:09.343 [DEBUG] clck_gen.py:113 IND CLOCK 1632
2026-01-29 02:07:09.808 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:07:09.811 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:07:09.813 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 02:07:09.813 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 02:07:09.821 [DEBUG] clck_gen.py:113 IND CLOCK 1734
2026-01-29 02:07:09.822 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 02:07:09.825 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:07:09.825 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:07:09.825 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:07:09.826 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 02:07:09.826 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:07:09.826 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:07:09.826 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:07:09.826 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.28.20:5700) Recv POWEROFF cmd
2026-01-29 02:07:09.826 [INFO] ctrl_if_trx.py:117 (BTS@172.18.28.20:5700) Stopping transceiver...
2026-01-29 02:07:09.826 [INFO] transceiver.py:246 Stopping clock generator
2026-01-29 02:07:09.827 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=1737 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:07:14.825 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.28.20:5700) Recv POWEROFF cmd
2026-01-29 02:07:14.825 [INFO] ctrl_if_trx.py:117 (BTS@172.18.28.20:5700) Stopping transceiver...
2026-01-29 02:07:14.829 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:07:14.829 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:07:14.829 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 02:07:14.829 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:07:14.838 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 02:07:14.840 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.28.20:5700) Recv SETFORMAT cmd
2026-01-29 02:07:14.841 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.28.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:07:14.841 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.28.20:5700) Recv SETFORMAT cmd
2026-01-29 02:07:14.841 [INFO] ctrl_if_trx.py:201 (BTS@172.18.28.20:5700) TRXD header version 1 -> 1
2026-01-29 02:07:14.846 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.28.20:5700/1) Recv RXTUNE cmd
2026-01-29 02:07:14.846 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.28.20:5700/1) Recv TXTUNE cmd
2026-01-29 02:07:14.847 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.28.20:5700/1) Recv SETFORMAT cmd
2026-01-29 02:07:14.847 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.28.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:07:14.847 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:07:14.848 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.28.20:5700/1) Recv NOMTXPOWER cmd
2026-01-29 02:07:14.848 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.28.20:5700/1) Recv SETFORMAT cmd
2026-01-29 02:07:14.848 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.28.20:5700/1) TRXD header version 1 -> 1
2026-01-29 02:07:14.849 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.28.20:5700/2) Recv RXTUNE cmd
2026-01-29 02:07:14.850 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.28.20:5700/2) Recv TXTUNE cmd
2026-01-29 02:07:14.850 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.28.20:5700/2) Recv SETFORMAT cmd
2026-01-29 02:07:14.850 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.28.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:07:14.851 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:07:14.851 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.28.20:5700/2) Recv NOMTXPOWER cmd
2026-01-29 02:07:14.851 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.28.20:5700/2) Recv SETFORMAT cmd
2026-01-29 02:07:14.851 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.28.20:5700/2) TRXD header version 1 -> 1
2026-01-29 02:07:14.852 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.28.20:5700/3) Recv RXTUNE cmd
2026-01-29 02:07:14.853 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.28.20:5700/3) Recv TXTUNE cmd
2026-01-29 02:07:14.853 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.28.20:5700/3) Recv SETFORMAT cmd
2026-01-29 02:07:14.853 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.28.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:07:14.853 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:07:14.853 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.28.20:5700/3) Recv NOMTXPOWER cmd
2026-01-29 02:07:14.853 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.28.20:5700/3) Recv SETFORMAT cmd
2026-01-29 02:07:14.853 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.28.20:5700/3) TRXD header version 1 -> 1
2026-01-29 02:07:14.856 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.28.20:5700) Recv RXTUNE cmd
2026-01-29 02:07:14.856 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETTSC
2026-01-29 02:07:14.856 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETTSC
2026-01-29 02:07:14.856 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETTSC
2026-01-29 02:07:14.856 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.28.20:5700) Recv TXTUNE cmd
2026-01-29 02:07:14.856 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETRXGAIN
2026-01-29 02:07:14.856 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETRXGAIN
2026-01-29 02:07:14.857 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETRXGAIN
2026-01-29 02:07:14.857 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETTSC
2026-01-29 02:07:14.857 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:07:14.857 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:07:14.857 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:07:14.857 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.28.20:5700) Recv NOMTXPOWER cmd
2026-01-29 02:07:14.857 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:07:14.857 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:07:14.857 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:07:14.857 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.28.20:5700) Recv POWERON CMD
2026-01-29 02:07:14.857 [INFO] ctrl_if_trx.py:109 (BTS@172.18.28.20:5700) Starting transceiver...
2026-01-29 02:07:14.857 [INFO] transceiver.py:243 Starting clock generator
2026-01-29 02:07:14.857 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-01-29 02:07:14.857 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:07:14.857 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:07:14.857 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:07:14.857 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETRXGAIN
2026-01-29 02:07:14.857 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:07:14.858 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:07:14.858 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:07:14.858 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:07:14.858 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:07:14.858 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:07:14.858 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:07:14.858 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:07:14.858 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:07:14.858 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:07:14.858 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:07:14.858 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:07:14.858 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:07:14.858 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:07:14.858 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:07:14.858 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:07:14.858 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:07:14.858 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:07:14.858 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:07:14.858 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:07:14.858 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:07:14.858 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:07:14.858 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:07:14.862 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-01-29 02:07:15.346 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-01-29 02:07:15.386 [DEBUG] fake_trx.py:278 (BTS@172.18.28.20:5700) Recv FAKE_TOA cmd
2026-01-29 02:07:15.388 [DEBUG] fake_trx.py:297 (BTS@172.18.28.20:5700) Recv FAKE_RSSI cmd
2026-01-29 02:07:15.389 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:07:15.390 [DEBUG] fake_trx.py:322 (BTS@172.18.28.20:5700) Recv FAKE_CI cmd
2026-01-29 02:07:15.406 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 02:07:15.406 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 02:07:15.406 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 02:07:15.409 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:07:15.410 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 02:07:15.410 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 02:07:15.410 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.28.22:6700) Recv POWERON CMD
2026-01-29 02:07:15.411 [INFO] ctrl_if_trx.py:109 (MS@172.18.28.22:6700) Starting transceiver...
2026-01-29 02:07:15.442 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:07:15.448 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 02:07:15.448 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 02:07:15.448 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:07:15.448 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:07:15.824 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-01-29 02:07:15.860 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 02:07:15.860 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:07:15.861 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:07:15.863 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:07:16.301 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-01-29 02:07:16.779 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-01-29 02:07:16.861 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 02:07:16.861 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:07:16.861 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:07:16.864 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:07:17.257 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-01-29 02:07:17.303 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:07:17.305 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:07:17.307 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 02:07:17.307 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 02:07:17.324 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 02:07:17.324 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 02:07:17.324 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 02:07:17.325 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:07:17.325 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 02:07:17.325 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 02:07:17.325 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.28.22:6700) Recv POWERON CMD
2026-01-29 02:07:17.325 [INFO] ctrl_if_trx.py:109 (MS@172.18.28.22:6700) Starting transceiver...
2026-01-29 02:07:17.350 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:07:17.354 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 02:07:17.355 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 02:07:17.355 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:07:17.355 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:07:17.735 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-01-29 02:07:17.862 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:07:17.862 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 02:07:17.862 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:07:17.865 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:07:18.212 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-01-29 02:07:18.690 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-01-29 02:07:18.862 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:07:18.863 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 02:07:18.863 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:07:18.866 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:07:19.169 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-01-29 02:07:19.494 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:07:19.496 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:07:19.497 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 02:07:19.497 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 02:07:19.515 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 02:07:19.515 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 02:07:19.515 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 02:07:19.517 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:07:19.517 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 02:07:19.517 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 02:07:19.517 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.28.22:6700) Recv POWERON CMD
2026-01-29 02:07:19.517 [INFO] ctrl_if_trx.py:109 (MS@172.18.28.22:6700) Starting transceiver...
2026-01-29 02:07:19.544 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:07:19.549 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 02:07:19.550 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 02:07:19.550 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:07:19.550 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:07:19.646 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-01-29 02:07:19.863 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 02:07:19.863 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:07:19.864 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:07:19.867 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:07:20.124 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-01-29 02:07:20.601 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-01-29 02:07:21.080 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-01-29 02:07:21.118 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:07:21.121 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:07:21.122 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 02:07:21.123 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 02:07:21.140 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 02:07:21.140 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 02:07:21.140 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 02:07:21.141 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:07:21.141 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 02:07:21.141 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 02:07:21.141 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.28.22:6700) Recv POWERON CMD
2026-01-29 02:07:21.141 [INFO] ctrl_if_trx.py:109 (MS@172.18.28.22:6700) Starting transceiver...
2026-01-29 02:07:21.174 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:07:21.180 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 02:07:21.180 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 02:07:21.180 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:07:21.180 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:07:21.558 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-01-29 02:07:22.036 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-01-29 02:07:22.514 [DEBUG] clck_gen.py:113 IND CLOCK 1632
2026-01-29 02:07:22.977 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:07:22.980 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:07:22.981 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 02:07:22.981 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 02:07:22.992 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 02:07:22.992 [DEBUG] clck_gen.py:113 IND CLOCK 1734
2026-01-29 02:07:22.992 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:07:22.993 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:07:22.993 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:07:22.995 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 02:07:22.995 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:07:22.995 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:07:22.995 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:07:22.995 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.28.20:5700) Recv POWEROFF cmd
2026-01-29 02:07:22.995 [INFO] ctrl_if_trx.py:117 (BTS@172.18.28.20:5700) Stopping transceiver...
2026-01-29 02:07:22.995 [INFO] transceiver.py:246 Stopping clock generator
2026-01-29 02:07:22.995 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=1737 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:07:22.996 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=1737 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:07:27.996 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.28.20:5700) Recv POWEROFF cmd
2026-01-29 02:07:27.996 [INFO] ctrl_if_trx.py:117 (BTS@172.18.28.20:5700) Stopping transceiver...
2026-01-29 02:07:27.998 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:07:27.999 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:07:27.999 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:07:27.999 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 02:07:28.006 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 02:07:28.008 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.28.20:5700) Recv SETFORMAT cmd
2026-01-29 02:07:28.008 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.28.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:07:28.009 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.28.20:5700) Recv SETFORMAT cmd
2026-01-29 02:07:28.009 [INFO] ctrl_if_trx.py:201 (BTS@172.18.28.20:5700) TRXD header version 1 -> 1
2026-01-29 02:07:28.012 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.28.20:5700/1) Recv RXTUNE cmd
2026-01-29 02:07:28.013 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.28.20:5700/1) Recv TXTUNE cmd
2026-01-29 02:07:28.013 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.28.20:5700/1) Recv SETFORMAT cmd
2026-01-29 02:07:28.013 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.28.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:07:28.014 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:07:28.014 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.28.20:5700/1) Recv NOMTXPOWER cmd
2026-01-29 02:07:28.015 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.28.20:5700/1) Recv SETFORMAT cmd
2026-01-29 02:07:28.015 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.28.20:5700/1) TRXD header version 1 -> 1
2026-01-29 02:07:28.016 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.28.20:5700/2) Recv RXTUNE cmd
2026-01-29 02:07:28.016 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.28.20:5700/2) Recv TXTUNE cmd
2026-01-29 02:07:28.017 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.28.20:5700/2) Recv SETFORMAT cmd
2026-01-29 02:07:28.017 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.28.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:07:28.017 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:07:28.017 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.28.20:5700/2) Recv NOMTXPOWER cmd
2026-01-29 02:07:28.017 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.28.20:5700/2) Recv SETFORMAT cmd
2026-01-29 02:07:28.017 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.28.20:5700/2) TRXD header version 1 -> 1
2026-01-29 02:07:28.019 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.28.20:5700/3) Recv RXTUNE cmd
2026-01-29 02:07:28.019 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.28.20:5700/3) Recv TXTUNE cmd
2026-01-29 02:07:28.020 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.28.20:5700/3) Recv SETFORMAT cmd
2026-01-29 02:07:28.020 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.28.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:07:28.020 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:07:28.020 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.28.20:5700/3) Recv NOMTXPOWER cmd
2026-01-29 02:07:28.020 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.28.20:5700/3) Recv SETFORMAT cmd
2026-01-29 02:07:28.020 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.28.20:5700/3) TRXD header version 1 -> 1
2026-01-29 02:07:28.023 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.28.20:5700) Recv RXTUNE cmd
2026-01-29 02:07:28.023 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETTSC
2026-01-29 02:07:28.023 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETTSC
2026-01-29 02:07:28.023 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETTSC
2026-01-29 02:07:28.023 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.28.20:5700) Recv TXTUNE cmd
2026-01-29 02:07:28.023 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETRXGAIN
2026-01-29 02:07:28.023 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETRXGAIN
2026-01-29 02:07:28.023 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETRXGAIN
2026-01-29 02:07:28.023 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETTSC
2026-01-29 02:07:28.024 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:07:28.024 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:07:28.024 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:07:28.024 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.28.20:5700) Recv NOMTXPOWER cmd
2026-01-29 02:07:28.024 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:07:28.024 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:07:28.024 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:07:28.024 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.28.20:5700) Recv POWERON CMD
2026-01-29 02:07:28.024 [INFO] ctrl_if_trx.py:109 (BTS@172.18.28.20:5700) Starting transceiver...
2026-01-29 02:07:28.024 [INFO] transceiver.py:243 Starting clock generator
2026-01-29 02:07:28.024 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-01-29 02:07:28.024 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:07:28.024 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:07:28.024 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:07:28.024 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETRXGAIN
2026-01-29 02:07:28.024 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:07:28.024 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:07:28.024 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:07:28.024 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:07:28.024 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:07:28.025 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:07:28.025 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:07:28.025 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:07:28.025 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:07:28.025 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:07:28.025 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:07:28.025 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:07:28.025 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:07:28.025 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:07:28.025 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:07:28.025 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:07:28.025 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:07:28.025 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:07:28.025 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:07:28.025 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:07:28.025 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:07:28.025 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:07:28.025 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:07:28.029 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-01-29 02:07:28.510 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-01-29 02:07:28.556 [DEBUG] fake_trx.py:278 (BTS@172.18.28.20:5700) Recv FAKE_TOA cmd
2026-01-29 02:07:28.558 [DEBUG] fake_trx.py:297 (BTS@172.18.28.20:5700) Recv FAKE_RSSI cmd
2026-01-29 02:07:28.560 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:07:28.560 [DEBUG] fake_trx.py:322 (BTS@172.18.28.20:5700) Recv FAKE_CI cmd
2026-01-29 02:07:28.587 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 02:07:28.587 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 02:07:28.588 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 02:07:28.593 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:07:28.593 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 02:07:28.593 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 02:07:28.593 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.28.22:6700) Recv POWERON CMD
2026-01-29 02:07:28.593 [INFO] ctrl_if_trx.py:109 (MS@172.18.28.22:6700) Starting transceiver...
2026-01-29 02:07:28.607 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:07:28.612 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 02:07:28.613 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 02:07:28.613 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:07:28.613 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:07:28.787 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:07:28.791 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:07:28.793 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 02:07:28.793 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 02:07:28.808 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 02:07:28.808 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 02:07:28.809 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 02:07:28.810 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:07:28.810 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 02:07:28.810 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 02:07:28.810 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.28.22:6700) Recv POWERON CMD
2026-01-29 02:07:28.810 [INFO] ctrl_if_trx.py:109 (MS@172.18.28.22:6700) Starting transceiver...
2026-01-29 02:07:28.840 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:07:28.845 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 02:07:28.845 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 02:07:28.845 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:07:28.845 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:07:28.981 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-01-29 02:07:29.028 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:07:29.028 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 02:07:29.029 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:07:29.032 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:07:29.458 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-01-29 02:07:29.936 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-01-29 02:07:30.029 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 02:07:30.029 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:07:30.029 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:07:30.033 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:07:30.414 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-01-29 02:07:30.891 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-01-29 02:07:30.937 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:07:30.940 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:07:30.941 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 02:07:30.941 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 02:07:30.958 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 02:07:30.958 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 02:07:30.958 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 02:07:30.959 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:07:30.959 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 02:07:30.959 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 02:07:30.959 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.28.22:6700) Recv POWERON CMD
2026-01-29 02:07:30.959 [INFO] ctrl_if_trx.py:109 (MS@172.18.28.22:6700) Starting transceiver...
2026-01-29 02:07:30.985 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:07:30.990 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 02:07:30.991 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 02:07:30.991 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:07:30.991 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:07:31.030 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:07:31.031 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 02:07:31.031 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:07:31.034 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:07:31.154 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:07:31.157 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:07:31.158 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 02:07:31.158 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 02:07:31.176 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 02:07:31.176 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 02:07:31.176 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 02:07:31.178 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:07:31.178 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 02:07:31.178 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 02:07:31.178 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.28.22:6700) Recv POWERON CMD
2026-01-29 02:07:31.178 [INFO] ctrl_if_trx.py:109 (MS@172.18.28.22:6700) Starting transceiver...
2026-01-29 02:07:31.222 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:07:31.227 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 02:07:31.227 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 02:07:31.228 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:07:31.228 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:07:31.367 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-01-29 02:07:31.844 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-01-29 02:07:32.031 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:07:32.032 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 02:07:32.032 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:07:32.036 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:07:32.321 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-01-29 02:07:32.797 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-01-29 02:07:33.033 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 02:07:33.033 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:07:33.033 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:07:33.037 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:07:33.275 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-01-29 02:07:33.366 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:07:33.369 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:07:33.371 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 02:07:33.371 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 02:07:33.384 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 02:07:33.384 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 02:07:33.384 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 02:07:33.385 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:07:33.385 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 02:07:33.385 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 02:07:33.385 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.28.22:6700) Recv POWERON CMD
2026-01-29 02:07:33.385 [INFO] ctrl_if_trx.py:109 (MS@172.18.28.22:6700) Starting transceiver...
2026-01-29 02:07:33.413 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:07:33.417 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 02:07:33.417 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 02:07:33.418 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:07:33.418 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:07:33.685 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:07:33.688 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:07:33.689 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 02:07:33.689 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 02:07:33.707 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 02:07:33.707 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 02:07:33.707 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 02:07:33.709 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:07:33.709 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 02:07:33.709 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 02:07:33.709 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.28.22:6700) Recv POWERON CMD
2026-01-29 02:07:33.709 [INFO] ctrl_if_trx.py:109 (MS@172.18.28.22:6700) Starting transceiver...
2026-01-29 02:07:33.750 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:07:33.752 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-01-29 02:07:33.755 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 02:07:33.755 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 02:07:33.755 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:07:33.756 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:07:34.231 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-01-29 02:07:34.709 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-01-29 02:07:35.186 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-01-29 02:07:35.664 [DEBUG] clck_gen.py:113 IND CLOCK 1632
2026-01-29 02:07:36.042 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:07:36.044 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:07:36.046 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 02:07:36.046 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 02:07:36.063 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 02:07:36.063 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 02:07:36.063 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 02:07:36.064 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:07:36.064 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 02:07:36.064 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 02:07:36.064 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.28.22:6700) Recv POWERON CMD
2026-01-29 02:07:36.064 [INFO] ctrl_if_trx.py:109 (MS@172.18.28.22:6700) Starting transceiver...
2026-01-29 02:07:36.083 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:07:36.089 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 02:07:36.089 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 02:07:36.089 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:07:36.090 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:07:36.141 [DEBUG] clck_gen.py:113 IND CLOCK 1734
2026-01-29 02:07:36.367 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:07:36.370 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:07:36.372 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 02:07:36.372 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 02:07:36.390 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 02:07:36.390 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 02:07:36.390 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 02:07:36.391 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:07:36.391 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 02:07:36.392 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 02:07:36.392 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.28.22:6700) Recv POWERON CMD
2026-01-29 02:07:36.392 [INFO] ctrl_if_trx.py:109 (MS@172.18.28.22:6700) Starting transceiver...
2026-01-29 02:07:36.425 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:07:36.430 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 02:07:36.431 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 02:07:36.431 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:07:36.431 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:07:36.619 [DEBUG] clck_gen.py:113 IND CLOCK 1836
2026-01-29 02:07:37.097 [DEBUG] clck_gen.py:113 IND CLOCK 1938
2026-01-29 02:07:37.575 [DEBUG] clck_gen.py:113 IND CLOCK 2040
2026-01-29 02:07:38.053 [DEBUG] clck_gen.py:113 IND CLOCK 2142
2026-01-29 02:07:38.477 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:07:38.480 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:07:38.481 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 02:07:38.481 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 02:07:38.497 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 02:07:38.497 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 02:07:38.497 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 02:07:38.498 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:07:38.499 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 02:07:38.499 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 02:07:38.499 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.28.22:6700) Recv POWERON CMD
2026-01-29 02:07:38.499 [INFO] ctrl_if_trx.py:109 (MS@172.18.28.22:6700) Starting transceiver...
2026-01-29 02:07:38.524 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:07:38.529 [DEBUG] clck_gen.py:113 IND CLOCK 2244
2026-01-29 02:07:38.529 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 02:07:38.530 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 02:07:38.530 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:07:38.530 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:07:39.007 [DEBUG] clck_gen.py:113 IND CLOCK 2346
2026-01-29 02:07:39.163 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:07:39.167 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:07:39.168 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 02:07:39.168 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 02:07:39.186 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 02:07:39.186 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 02:07:39.187 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 02:07:39.188 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:07:39.188 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 02:07:39.188 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 02:07:39.188 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.28.22:6700) Recv POWERON CMD
2026-01-29 02:07:39.188 [INFO] ctrl_if_trx.py:109 (MS@172.18.28.22:6700) Starting transceiver...
2026-01-29 02:07:39.244 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:07:39.249 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 02:07:39.250 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 02:07:39.250 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:07:39.251 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:07:39.484 [DEBUG] clck_gen.py:113 IND CLOCK 2448
2026-01-29 02:07:39.962 [DEBUG] clck_gen.py:113 IND CLOCK 2550
2026-01-29 02:07:40.440 [DEBUG] clck_gen.py:113 IND CLOCK 2652
2026-01-29 02:07:40.878 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:07:40.881 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:07:40.882 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 02:07:40.882 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 02:07:40.900 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 02:07:40.900 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 02:07:40.900 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 02:07:40.901 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:07:40.902 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 02:07:40.902 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 02:07:40.902 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.28.22:6700) Recv POWERON CMD
2026-01-29 02:07:40.902 [INFO] ctrl_if_trx.py:109 (MS@172.18.28.22:6700) Starting transceiver...
2026-01-29 02:07:40.908 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:07:40.909 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 02:07:40.909 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 02:07:40.909 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:07:40.909 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:07:40.917 [DEBUG] clck_gen.py:113 IND CLOCK 2754
2026-01-29 02:07:41.394 [DEBUG] clck_gen.py:113 IND CLOCK 2856
2026-01-29 02:07:41.550 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:07:41.553 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:07:41.555 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 02:07:41.555 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 02:07:41.574 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 02:07:41.574 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 02:07:41.574 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 02:07:41.576 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:07:41.576 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 02:07:41.576 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 02:07:41.576 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.28.22:6700) Recv POWERON CMD
2026-01-29 02:07:41.576 [INFO] ctrl_if_trx.py:109 (MS@172.18.28.22:6700) Starting transceiver...
2026-01-29 02:07:41.631 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:07:41.633 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 02:07:41.634 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 02:07:41.634 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:07:41.634 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:07:41.871 [DEBUG] clck_gen.py:113 IND CLOCK 2958
2026-01-29 02:07:42.349 [DEBUG] clck_gen.py:113 IND CLOCK 3060
2026-01-29 02:07:42.827 [DEBUG] clck_gen.py:113 IND CLOCK 3162
2026-01-29 02:07:43.265 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:07:43.268 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:07:43.270 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 02:07:43.270 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 02:07:43.288 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 02:07:43.288 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 02:07:43.288 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 02:07:43.289 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:07:43.289 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 02:07:43.289 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 02:07:43.289 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.28.22:6700) Recv POWERON CMD
2026-01-29 02:07:43.289 [INFO] ctrl_if_trx.py:109 (MS@172.18.28.22:6700) Starting transceiver...
2026-01-29 02:07:43.295 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:07:43.296 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 02:07:43.296 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 02:07:43.296 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:07:43.296 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:07:43.305 [DEBUG] clck_gen.py:113 IND CLOCK 3264
2026-01-29 02:07:43.782 [DEBUG] clck_gen.py:113 IND CLOCK 3366
2026-01-29 02:07:43.864 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:07:43.867 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:07:43.869 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 02:07:43.869 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 02:07:43.877 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 02:07:43.877 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 02:07:43.877 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 02:07:43.878 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:07:43.878 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 02:07:43.878 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 02:07:43.878 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.28.22:6700) Recv POWERON CMD
2026-01-29 02:07:43.878 [INFO] ctrl_if_trx.py:109 (MS@172.18.28.22:6700) Starting transceiver...
2026-01-29 02:07:43.922 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:07:43.923 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 02:07:43.923 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 02:07:43.923 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:07:43.923 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:07:44.257 [DEBUG] clck_gen.py:113 IND CLOCK 3468
2026-01-29 02:07:44.735 [DEBUG] clck_gen.py:113 IND CLOCK 3570
2026-01-29 02:07:45.212 [DEBUG] clck_gen.py:113 IND CLOCK 3672
2026-01-29 02:07:45.604 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:07:45.607 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:07:45.609 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 02:07:45.609 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 02:07:45.622 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 02:07:45.622 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 02:07:45.622 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 02:07:45.623 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:07:45.623 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 02:07:45.623 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 02:07:45.623 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.28.22:6700) Recv POWERON CMD
2026-01-29 02:07:45.624 [INFO] ctrl_if_trx.py:109 (MS@172.18.28.22:6700) Starting transceiver...
2026-01-29 02:07:45.629 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:07:45.630 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 02:07:45.630 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 02:07:45.630 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:07:45.630 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:07:45.690 [DEBUG] clck_gen.py:113 IND CLOCK 3774
2026-01-29 02:07:46.169 [DEBUG] clck_gen.py:113 IND CLOCK 3876
2026-01-29 02:07:46.251 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:07:46.254 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:07:46.256 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 02:07:46.256 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 02:07:46.264 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 02:07:46.264 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 02:07:46.264 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 02:07:46.265 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:07:46.265 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 02:07:46.265 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 02:07:46.265 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.28.22:6700) Recv POWERON CMD
2026-01-29 02:07:46.265 [INFO] ctrl_if_trx.py:109 (MS@172.18.28.22:6700) Starting transceiver...
2026-01-29 02:07:46.310 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:07:46.315 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 02:07:46.315 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 02:07:46.315 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:07:46.315 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:07:46.646 [DEBUG] clck_gen.py:113 IND CLOCK 3978
2026-01-29 02:07:47.125 [DEBUG] clck_gen.py:113 IND CLOCK 4080
2026-01-29 02:07:47.603 [DEBUG] clck_gen.py:113 IND CLOCK 4182
2026-01-29 02:07:47.995 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:07:47.999 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:07:48.001 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 02:07:48.001 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 02:07:48.008 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 02:07:48.008 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:07:48.008 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:07:48.008 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:07:48.009 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 02:07:48.009 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:07:48.009 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:07:48.009 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.28.20:5700) Recv POWEROFF cmd
2026-01-29 02:07:48.009 [INFO] ctrl_if_trx.py:117 (BTS@172.18.28.20:5700) Stopping transceiver...
2026-01-29 02:07:48.009 [INFO] transceiver.py:246 Stopping clock generator
2026-01-29 02:07:48.009 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:07:53.012 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.28.20:5700) Recv POWEROFF cmd
2026-01-29 02:07:53.012 [INFO] ctrl_if_trx.py:117 (BTS@172.18.28.20:5700) Stopping transceiver...
2026-01-29 02:07:53.013 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:07:53.016 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:07:53.016 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:07:53.016 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 02:07:53.025 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 02:07:53.027 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.28.20:5700) Recv SETFORMAT cmd
2026-01-29 02:07:53.027 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.28.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:07:53.028 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.28.20:5700) Recv SETFORMAT cmd
2026-01-29 02:07:53.028 [INFO] ctrl_if_trx.py:201 (BTS@172.18.28.20:5700) TRXD header version 1 -> 1
2026-01-29 02:07:53.031 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.28.20:5700/1) Recv RXTUNE cmd
2026-01-29 02:07:53.032 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.28.20:5700/1) Recv TXTUNE cmd
2026-01-29 02:07:53.032 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.28.20:5700/1) Recv SETFORMAT cmd
2026-01-29 02:07:53.033 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.28.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:07:53.033 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:07:53.033 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.28.20:5700/1) Recv NOMTXPOWER cmd
2026-01-29 02:07:53.034 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.28.20:5700/1) Recv SETFORMAT cmd
2026-01-29 02:07:53.034 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.28.20:5700/1) TRXD header version 1 -> 1
2026-01-29 02:07:53.035 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.28.20:5700/2) Recv RXTUNE cmd
2026-01-29 02:07:53.035 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.28.20:5700/2) Recv TXTUNE cmd
2026-01-29 02:07:53.036 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.28.20:5700/2) Recv SETFORMAT cmd
2026-01-29 02:07:53.036 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.28.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:07:53.036 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:07:53.036 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.28.20:5700/2) Recv NOMTXPOWER cmd
2026-01-29 02:07:53.036 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.28.20:5700/2) Recv SETFORMAT cmd
2026-01-29 02:07:53.036 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.28.20:5700/2) TRXD header version 1 -> 1
2026-01-29 02:07:53.038 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.28.20:5700/3) Recv RXTUNE cmd
2026-01-29 02:07:53.038 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.28.20:5700/3) Recv TXTUNE cmd
2026-01-29 02:07:53.038 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.28.20:5700/3) Recv SETFORMAT cmd
2026-01-29 02:07:53.038 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.28.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:07:53.038 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:07:53.038 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.28.20:5700/3) Recv NOMTXPOWER cmd
2026-01-29 02:07:53.038 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.28.20:5700/3) Recv SETFORMAT cmd
2026-01-29 02:07:53.038 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.28.20:5700/3) TRXD header version 1 -> 1
2026-01-29 02:07:53.041 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.28.20:5700) Recv RXTUNE cmd
2026-01-29 02:07:53.041 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETTSC
2026-01-29 02:07:53.041 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETTSC
2026-01-29 02:07:53.041 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETTSC
2026-01-29 02:07:53.041 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.28.20:5700) Recv TXTUNE cmd
2026-01-29 02:07:53.041 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETRXGAIN
2026-01-29 02:07:53.041 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETRXGAIN
2026-01-29 02:07:53.041 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETRXGAIN
2026-01-29 02:07:53.041 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETTSC
2026-01-29 02:07:53.041 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:07:53.041 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:07:53.042 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:07:53.042 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.28.20:5700) Recv NOMTXPOWER cmd
2026-01-29 02:07:53.042 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:07:53.042 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:07:53.042 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:07:53.042 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.28.20:5700) Recv POWERON CMD
2026-01-29 02:07:53.042 [INFO] ctrl_if_trx.py:109 (BTS@172.18.28.20:5700) Starting transceiver...
2026-01-29 02:07:53.042 [INFO] transceiver.py:243 Starting clock generator
2026-01-29 02:07:53.042 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-01-29 02:07:53.042 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:07:53.042 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:07:53.042 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:07:53.042 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETRXGAIN
2026-01-29 02:07:53.042 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:07:53.042 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:07:53.042 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:07:53.042 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:07:53.042 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:07:53.042 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:07:53.042 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:07:53.043 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:07:53.043 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:07:53.043 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:07:53.043 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:07:53.043 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:07:53.043 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:07:53.043 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:07:53.043 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:07:53.043 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:07:53.043 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:07:53.043 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:07:53.043 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:07:53.043 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:07:53.043 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:07:53.043 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:07:53.043 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:07:53.047 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-01-29 02:07:53.528 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-01-29 02:07:53.572 [DEBUG] fake_trx.py:278 (BTS@172.18.28.20:5700) Recv FAKE_TOA cmd
2026-01-29 02:07:53.574 [DEBUG] fake_trx.py:297 (BTS@172.18.28.20:5700) Recv FAKE_RSSI cmd
2026-01-29 02:07:53.575 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:07:53.576 [DEBUG] fake_trx.py:322 (BTS@172.18.28.20:5700) Recv FAKE_CI cmd
2026-01-29 02:07:53.597 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 02:07:53.597 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 02:07:53.597 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 02:07:53.600 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:07:53.600 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 02:07:53.600 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 02:07:53.601 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.28.22:6700) Recv POWERON CMD
2026-01-29 02:07:53.601 [INFO] ctrl_if_trx.py:109 (MS@172.18.28.22:6700) Starting transceiver...
2026-01-29 02:07:53.624 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:07:53.629 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 02:07:53.630 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 02:07:53.630 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:07:53.630 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:07:53.685 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:07:53.688 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:07:53.690 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 02:07:53.690 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 02:07:53.708 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 02:07:53.708 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 02:07:53.709 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 02:07:53.710 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:07:53.710 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 02:07:53.710 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 02:07:53.710 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.28.22:6700) Recv POWERON CMD
2026-01-29 02:07:53.710 [INFO] ctrl_if_trx.py:109 (MS@172.18.28.22:6700) Starting transceiver...
2026-01-29 02:07:53.766 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:07:53.772 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 02:07:53.772 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 02:07:53.772 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:07:53.772 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:07:53.846 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:07:53.848 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:07:53.850 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 02:07:53.850 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 02:07:53.863 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 02:07:53.863 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 02:07:53.863 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 02:07:53.864 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:07:53.864 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 02:07:53.864 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 02:07:53.864 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.28.22:6700) Recv POWERON CMD
2026-01-29 02:07:53.864 [INFO] ctrl_if_trx.py:109 (MS@172.18.28.22:6700) Starting transceiver...
2026-01-29 02:07:53.904 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:07:53.910 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 02:07:53.910 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 02:07:53.911 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:07:53.912 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:07:54.003 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-01-29 02:07:54.003 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:07:54.006 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:07:54.007 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 02:07:54.008 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 02:07:54.026 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 02:07:54.027 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 02:07:54.027 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 02:07:54.028 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:07:54.028 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 02:07:54.028 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 02:07:54.028 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.28.22:6700) Recv POWERON CMD
2026-01-29 02:07:54.028 [INFO] ctrl_if_trx.py:109 (MS@172.18.28.22:6700) Starting transceiver...
2026-01-29 02:07:54.043 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:07:54.044 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 02:07:54.045 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:07:54.045 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 02:07:54.045 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 02:07:54.045 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:07:54.046 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:07:54.047 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:07:54.050 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:07:54.124 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:07:54.127 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:07:54.129 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 02:07:54.129 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 02:07:54.147 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 02:07:54.147 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 02:07:54.147 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 02:07:54.148 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:07:54.148 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 02:07:54.148 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 02:07:54.148 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.28.22:6700) Recv POWERON CMD
2026-01-29 02:07:54.148 [INFO] ctrl_if_trx.py:109 (MS@172.18.28.22:6700) Starting transceiver...
2026-01-29 02:07:54.185 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:07:54.190 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 02:07:54.190 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 02:07:54.191 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:07:54.191 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:07:54.391 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:07:54.394 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:07:54.396 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 02:07:54.396 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 02:07:54.408 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 02:07:54.408 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 02:07:54.409 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 02:07:54.410 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:07:54.410 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 02:07:54.411 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 02:07:54.411 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.28.22:6700) Recv POWERON CMD
2026-01-29 02:07:54.411 [INFO] ctrl_if_trx.py:109 (MS@172.18.28.22:6700) Starting transceiver...
2026-01-29 02:07:54.416 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:07:54.417 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 02:07:54.417 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 02:07:54.417 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:07:54.417 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:07:54.478 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-01-29 02:07:54.635 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:07:54.638 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:07:54.640 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 02:07:54.640 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 02:07:54.652 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 02:07:54.652 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 02:07:54.653 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 02:07:54.654 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:07:54.654 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 02:07:54.654 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 02:07:54.654 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.28.22:6700) Recv POWERON CMD
2026-01-29 02:07:54.654 [INFO] ctrl_if_trx.py:109 (MS@172.18.28.22:6700) Starting transceiver...
2026-01-29 02:07:54.660 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:07:54.661 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 02:07:54.661 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 02:07:54.661 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:07:54.661 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:07:54.797 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:07:54.800 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:07:54.802 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 02:07:54.802 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 02:07:54.820 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 02:07:54.821 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 02:07:54.821 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 02:07:54.822 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:07:54.822 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 02:07:54.822 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 02:07:54.822 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.28.22:6700) Recv POWERON CMD
2026-01-29 02:07:54.822 [INFO] ctrl_if_trx.py:109 (MS@172.18.28.22:6700) Starting transceiver...
2026-01-29 02:07:54.854 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:07:54.859 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 02:07:54.859 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 02:07:54.859 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:07:54.859 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:07:54.952 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-01-29 02:07:55.033 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:07:55.035 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:07:55.037 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 02:07:55.037 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 02:07:55.045 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 02:07:55.045 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:07:55.046 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:07:55.046 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:07:55.048 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 02:07:55.048 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:07:55.048 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:07:55.048 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:07:55.049 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.28.20:5700) Recv POWEROFF cmd
2026-01-29 02:07:55.049 [INFO] ctrl_if_trx.py:117 (BTS@172.18.28.20:5700) Stopping transceiver...
2026-01-29 02:07:55.049 [INFO] transceiver.py:246 Stopping clock generator
2026-01-29 02:07:55.049 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=431 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:07:55.049 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=431 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:07:55.049 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=431 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:07:55.049 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=431 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:07:55.049 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=431 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:07:55.049 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=431 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:08:00.047 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.28.20:5700) Recv POWEROFF cmd
2026-01-29 02:08:00.048 [INFO] ctrl_if_trx.py:117 (BTS@172.18.28.20:5700) Stopping transceiver...
2026-01-29 02:08:00.049 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:08:00.050 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:08:00.051 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:08:00.052 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 02:08:00.061 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 02:08:00.062 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.28.20:5700) Recv SETFORMAT cmd
2026-01-29 02:08:00.063 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.28.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:08:00.063 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.28.20:5700) Recv SETFORMAT cmd
2026-01-29 02:08:00.064 [INFO] ctrl_if_trx.py:201 (BTS@172.18.28.20:5700) TRXD header version 1 -> 1
2026-01-29 02:08:00.067 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.28.20:5700/1) Recv RXTUNE cmd
2026-01-29 02:08:00.068 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.28.20:5700/1) Recv TXTUNE cmd
2026-01-29 02:08:00.068 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.28.20:5700/1) Recv SETFORMAT cmd
2026-01-29 02:08:00.068 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.28.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:08:00.069 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:08:00.069 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.28.20:5700/1) Recv NOMTXPOWER cmd
2026-01-29 02:08:00.070 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.28.20:5700/1) Recv SETFORMAT cmd
2026-01-29 02:08:00.070 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.28.20:5700/1) TRXD header version 1 -> 1
2026-01-29 02:08:00.072 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.28.20:5700/2) Recv RXTUNE cmd
2026-01-29 02:08:00.072 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.28.20:5700/2) Recv TXTUNE cmd
2026-01-29 02:08:00.073 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.28.20:5700/2) Recv SETFORMAT cmd
2026-01-29 02:08:00.073 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.28.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:08:00.073 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:08:00.074 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.28.20:5700/2) Recv NOMTXPOWER cmd
2026-01-29 02:08:00.074 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.28.20:5700/2) Recv SETFORMAT cmd
2026-01-29 02:08:00.074 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.28.20:5700/2) TRXD header version 1 -> 1
2026-01-29 02:08:00.075 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.28.20:5700/3) Recv RXTUNE cmd
2026-01-29 02:08:00.075 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.28.20:5700/3) Recv TXTUNE cmd
2026-01-29 02:08:00.075 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.28.20:5700/3) Recv SETFORMAT cmd
2026-01-29 02:08:00.075 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.28.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:08:00.076 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:08:00.076 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.28.20:5700/3) Recv NOMTXPOWER cmd
2026-01-29 02:08:00.076 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.28.20:5700/3) Recv SETFORMAT cmd
2026-01-29 02:08:00.076 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.28.20:5700/3) TRXD header version 1 -> 1
2026-01-29 02:08:00.078 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.28.20:5700) Recv RXTUNE cmd
2026-01-29 02:08:00.078 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETTSC
2026-01-29 02:08:00.078 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETTSC
2026-01-29 02:08:00.078 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETTSC
2026-01-29 02:08:00.078 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.28.20:5700) Recv TXTUNE cmd
2026-01-29 02:08:00.079 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETRXGAIN
2026-01-29 02:08:00.079 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETRXGAIN
2026-01-29 02:08:00.079 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETRXGAIN
2026-01-29 02:08:00.079 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETTSC
2026-01-29 02:08:00.079 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:08:00.079 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:08:00.079 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:08:00.079 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.28.20:5700) Recv NOMTXPOWER cmd
2026-01-29 02:08:00.079 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:08:00.079 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:08:00.079 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:08:00.079 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.28.20:5700) Recv POWERON CMD
2026-01-29 02:08:00.079 [INFO] ctrl_if_trx.py:109 (BTS@172.18.28.20:5700) Starting transceiver...
2026-01-29 02:08:00.079 [INFO] transceiver.py:243 Starting clock generator
2026-01-29 02:08:00.079 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-01-29 02:08:00.079 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:08:00.079 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:08:00.079 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:08:00.079 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETRXGAIN
2026-01-29 02:08:00.080 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:08:00.080 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:08:00.080 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:08:00.080 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:08:00.080 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:08:00.080 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:08:00.080 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:08:00.080 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:08:00.080 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:08:00.080 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:08:00.080 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:08:00.080 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:08:00.080 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:08:00.080 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:08:00.080 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:08:00.080 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:08:00.080 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:08:00.080 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:08:00.080 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:08:00.080 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:08:00.080 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:08:00.080 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:08:00.080 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:08:00.084 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-01-29 02:08:00.567 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-01-29 02:08:00.598 [DEBUG] fake_trx.py:278 (BTS@172.18.28.20:5700) Recv FAKE_TOA cmd
2026-01-29 02:08:00.599 [DEBUG] fake_trx.py:297 (BTS@172.18.28.20:5700) Recv FAKE_RSSI cmd
2026-01-29 02:08:00.599 [DEBUG] fake_trx.py:322 (BTS@172.18.28.20:5700) Recv FAKE_CI cmd
2026-01-29 02:08:00.600 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:08:00.616 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 02:08:00.616 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 02:08:00.616 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 02:08:00.621 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:08:00.621 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 02:08:00.621 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 02:08:00.622 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.28.22:6700) Recv POWERON CMD
2026-01-29 02:08:00.622 [INFO] ctrl_if_trx.py:109 (MS@172.18.28.22:6700) Starting transceiver...
2026-01-29 02:08:00.662 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:08:00.668 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 02:08:00.668 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 02:08:00.668 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:08:00.668 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:08:01.041 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-01-29 02:08:01.082 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 02:08:01.083 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:08:01.084 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:08:01.086 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:08:01.515 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-01-29 02:08:01.533 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:08:01.535 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:08:01.537 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 02:08:01.537 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 02:08:01.548 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 02:08:01.548 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 02:08:01.548 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 02:08:01.549 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:08:01.549 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 02:08:01.549 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 02:08:01.549 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.28.22:6700) Recv POWERON CMD
2026-01-29 02:08:01.549 [INFO] ctrl_if_trx.py:109 (MS@172.18.28.22:6700) Starting transceiver...
2026-01-29 02:08:01.559 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:08:01.561 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 02:08:01.561 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 02:08:01.561 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:08:01.561 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:08:01.992 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-01-29 02:08:02.019 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:08:02.021 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:08:02.023 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 02:08:02.023 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 02:08:02.039 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 02:08:02.039 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 02:08:02.039 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 02:08:02.040 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:08:02.040 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 02:08:02.040 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 02:08:02.040 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.28.22:6700) Recv POWERON CMD
2026-01-29 02:08:02.040 [INFO] ctrl_if_trx.py:109 (MS@172.18.28.22:6700) Starting transceiver...
2026-01-29 02:08:02.084 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 02:08:02.084 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:08:02.085 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:08:02.086 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:08:02.088 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:08:02.093 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 02:08:02.093 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 02:08:02.093 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:08:02.093 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:08:02.470 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-01-29 02:08:02.746 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:08:02.749 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:08:02.751 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 02:08:02.751 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 02:08:02.768 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 02:08:02.768 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 02:08:02.768 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 02:08:02.770 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:08:02.770 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 02:08:02.770 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 02:08:02.770 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.28.22:6700) Recv POWERON CMD
2026-01-29 02:08:02.770 [INFO] ctrl_if_trx.py:109 (MS@172.18.28.22:6700) Starting transceiver...
2026-01-29 02:08:02.800 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:08:02.805 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 02:08:02.806 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 02:08:02.806 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:08:02.806 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:08:02.948 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-01-29 02:08:03.085 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 02:08:03.086 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:08:03.086 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:08:03.087 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:08:03.234 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:08:03.237 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:08:03.238 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 02:08:03.238 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 02:08:03.248 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 02:08:03.248 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 02:08:03.248 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 02:08:03.249 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:08:03.249 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 02:08:03.249 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 02:08:03.249 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.28.22:6700) Recv POWERON CMD
2026-01-29 02:08:03.249 [INFO] ctrl_if_trx.py:109 (MS@172.18.28.22:6700) Starting transceiver...
2026-01-29 02:08:03.277 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:08:03.282 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 02:08:03.283 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 02:08:03.284 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:08:03.284 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:08:03.386 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:08:03.389 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:08:03.391 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 02:08:03.391 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 02:08:03.405 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 02:08:03.405 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 02:08:03.405 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 02:08:03.407 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:08:03.407 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 02:08:03.407 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 02:08:03.407 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.28.22:6700) Recv POWERON CMD
2026-01-29 02:08:03.407 [INFO] ctrl_if_trx.py:109 (MS@172.18.28.22:6700) Starting transceiver...
2026-01-29 02:08:03.416 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:08:03.418 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 02:08:03.418 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 02:08:03.418 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:08:03.418 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:08:03.425 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-01-29 02:08:03.863 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:08:03.866 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:08:03.868 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 02:08:03.868 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 02:08:03.882 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 02:08:03.883 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 02:08:03.883 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 02:08:03.886 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:08:03.886 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 02:08:03.886 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 02:08:03.886 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.28.22:6700) Recv POWERON CMD
2026-01-29 02:08:03.886 [INFO] ctrl_if_trx.py:109 (MS@172.18.28.22:6700) Starting transceiver...
2026-01-29 02:08:03.893 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:08:03.895 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 02:08:03.895 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 02:08:03.895 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:08:03.895 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:08:03.903 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-01-29 02:08:04.086 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 02:08:04.086 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:08:04.087 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:08:04.088 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:08:04.295 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:08:04.298 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:08:04.300 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 02:08:04.300 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 02:08:04.317 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 02:08:04.317 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 02:08:04.317 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 02:08:04.318 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:08:04.318 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 02:08:04.318 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 02:08:04.318 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.28.22:6700) Recv POWERON CMD
2026-01-29 02:08:04.318 [INFO] ctrl_if_trx.py:109 (MS@172.18.28.22:6700) Starting transceiver...
2026-01-29 02:08:04.375 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:08:04.377 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 02:08:04.377 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 02:08:04.377 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:08:04.377 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:08:04.380 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-01-29 02:08:04.772 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:08:04.775 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:08:04.777 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 02:08:04.777 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 02:08:04.788 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 02:08:04.788 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:08:04.788 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:08:04.788 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:08:04.794 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 02:08:04.794 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:08:04.795 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:08:04.795 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.28.20:5700) Recv POWEROFF cmd
2026-01-29 02:08:04.795 [INFO] ctrl_if_trx.py:117 (BTS@172.18.28.20:5700) Stopping transceiver...
2026-01-29 02:08:04.795 [INFO] transceiver.py:246 Stopping clock generator
2026-01-29 02:08:04.795 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:08:04.795 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=1008 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:08:04.796 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=1008 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:08:04.796 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=1008 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:08:04.796 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=1008 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:08:04.796 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=1008 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:08:09.791 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.28.20:5700) Recv POWEROFF cmd
2026-01-29 02:08:09.791 [INFO] ctrl_if_trx.py:117 (BTS@172.18.28.20:5700) Stopping transceiver...
2026-01-29 02:08:09.793 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:08:09.794 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:08:09.794 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:08:09.795 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 02:08:09.802 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 02:08:09.803 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.28.20:5700) Recv SETFORMAT cmd
2026-01-29 02:08:09.803 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.28.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:08:09.803 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.28.20:5700) Recv SETFORMAT cmd
2026-01-29 02:08:09.803 [INFO] ctrl_if_trx.py:201 (BTS@172.18.28.20:5700) TRXD header version 1 -> 1
2026-01-29 02:08:09.806 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.28.20:5700/1) Recv RXTUNE cmd
2026-01-29 02:08:09.806 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.28.20:5700/1) Recv TXTUNE cmd
2026-01-29 02:08:09.806 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.28.20:5700/1) Recv SETFORMAT cmd
2026-01-29 02:08:09.807 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.28.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:08:09.807 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:08:09.807 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.28.20:5700/1) Recv NOMTXPOWER cmd
2026-01-29 02:08:09.807 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.28.20:5700/1) Recv SETFORMAT cmd
2026-01-29 02:08:09.807 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.28.20:5700/1) TRXD header version 1 -> 1
2026-01-29 02:08:09.809 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.28.20:5700/2) Recv RXTUNE cmd
2026-01-29 02:08:09.809 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.28.20:5700/2) Recv TXTUNE cmd
2026-01-29 02:08:09.809 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.28.20:5700/2) Recv SETFORMAT cmd
2026-01-29 02:08:09.809 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.28.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:08:09.809 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:08:09.810 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.28.20:5700/2) Recv NOMTXPOWER cmd
2026-01-29 02:08:09.810 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.28.20:5700/2) Recv SETFORMAT cmd
2026-01-29 02:08:09.810 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.28.20:5700/2) TRXD header version 1 -> 1
2026-01-29 02:08:09.812 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.28.20:5700/3) Recv RXTUNE cmd
2026-01-29 02:08:09.812 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.28.20:5700/3) Recv TXTUNE cmd
2026-01-29 02:08:09.812 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.28.20:5700/3) Recv SETFORMAT cmd
2026-01-29 02:08:09.813 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.28.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:08:09.813 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:08:09.813 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.28.20:5700/3) Recv NOMTXPOWER cmd
2026-01-29 02:08:09.813 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.28.20:5700/3) Recv SETFORMAT cmd
2026-01-29 02:08:09.813 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.28.20:5700/3) TRXD header version 1 -> 1
2026-01-29 02:08:09.816 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.28.20:5700) Recv RXTUNE cmd
2026-01-29 02:08:09.817 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETTSC
2026-01-29 02:08:09.817 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETTSC
2026-01-29 02:08:09.817 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETTSC
2026-01-29 02:08:09.817 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.28.20:5700) Recv TXTUNE cmd
2026-01-29 02:08:09.817 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETRXGAIN
2026-01-29 02:08:09.817 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETRXGAIN
2026-01-29 02:08:09.817 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETRXGAIN
2026-01-29 02:08:09.817 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETTSC
2026-01-29 02:08:09.817 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:08:09.817 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:08:09.817 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:08:09.817 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.28.20:5700) Recv NOMTXPOWER cmd
2026-01-29 02:08:09.817 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:08:09.817 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:08:09.817 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:08:09.817 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.28.20:5700) Recv POWERON CMD
2026-01-29 02:08:09.817 [INFO] ctrl_if_trx.py:109 (BTS@172.18.28.20:5700) Starting transceiver...
2026-01-29 02:08:09.817 [INFO] transceiver.py:243 Starting clock generator
2026-01-29 02:08:09.817 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-01-29 02:08:09.818 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:08:09.818 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:08:09.818 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:08:09.818 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETRXGAIN
2026-01-29 02:08:09.818 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:08:09.818 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:08:09.818 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:08:09.818 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:08:09.818 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:08:09.818 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:08:09.818 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:08:09.818 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:08:09.818 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:08:09.818 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:08:09.818 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:08:09.818 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:08:09.818 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:08:09.818 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:08:09.818 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:08:09.818 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:08:09.818 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:08:09.818 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:08:09.818 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:08:09.818 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:08:09.818 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:08:09.818 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:08:09.818 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:08:09.822 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-01-29 02:08:10.307 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-01-29 02:08:10.345 [DEBUG] fake_trx.py:278 (BTS@172.18.28.20:5700) Recv FAKE_TOA cmd
2026-01-29 02:08:10.347 [DEBUG] fake_trx.py:297 (BTS@172.18.28.20:5700) Recv FAKE_RSSI cmd
2026-01-29 02:08:10.349 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:08:10.350 [DEBUG] fake_trx.py:322 (BTS@172.18.28.20:5700) Recv FAKE_CI cmd
2026-01-29 02:08:10.371 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 02:08:10.371 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 02:08:10.372 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 02:08:10.376 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:08:10.376 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 02:08:10.376 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 02:08:10.376 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.28.22:6700) Recv POWERON CMD
2026-01-29 02:08:10.376 [INFO] ctrl_if_trx.py:109 (MS@172.18.28.22:6700) Starting transceiver...
2026-01-29 02:08:10.403 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:08:10.408 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 02:08:10.409 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 02:08:10.409 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:08:10.410 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:08:10.465 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:08:10.468 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:08:10.469 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 02:08:10.469 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 02:08:10.486 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 02:08:10.486 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 02:08:10.486 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 02:08:10.487 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:08:10.487 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 02:08:10.487 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 02:08:10.487 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.28.22:6700) Recv POWERON CMD
2026-01-29 02:08:10.487 [INFO] ctrl_if_trx.py:109 (MS@172.18.28.22:6700) Starting transceiver...
2026-01-29 02:08:10.544 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:08:10.549 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 02:08:10.549 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 02:08:10.549 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:08:10.550 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:08:10.603 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:08:10.607 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:08:10.608 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 02:08:10.608 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 02:08:10.625 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 02:08:10.625 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 02:08:10.625 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 02:08:10.626 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:08:10.626 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 02:08:10.627 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 02:08:10.627 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.28.22:6700) Recv POWERON CMD
2026-01-29 02:08:10.627 [INFO] ctrl_if_trx.py:109 (MS@172.18.28.22:6700) Starting transceiver...
2026-01-29 02:08:10.631 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:08:10.632 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 02:08:10.632 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 02:08:10.632 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:08:10.633 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:08:10.723 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:08:10.725 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:08:10.726 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 02:08:10.726 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 02:08:10.745 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 02:08:10.745 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 02:08:10.745 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 02:08:10.747 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:08:10.747 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 02:08:10.747 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 02:08:10.747 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.28.22:6700) Recv POWERON CMD
2026-01-29 02:08:10.747 [INFO] ctrl_if_trx.py:109 (MS@172.18.28.22:6700) Starting transceiver...
2026-01-29 02:08:10.780 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:08:10.781 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-01-29 02:08:10.785 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 02:08:10.785 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 02:08:10.785 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:08:10.786 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:08:10.820 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 02:08:10.820 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:08:10.821 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:08:10.823 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:08:10.843 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:08:10.846 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:08:10.848 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 02:08:10.848 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 02:08:10.865 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 02:08:10.865 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 02:08:10.865 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 02:08:10.866 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:08:10.866 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 02:08:10.866 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 02:08:10.866 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.28.22:6700) Recv POWERON CMD
2026-01-29 02:08:10.866 [INFO] ctrl_if_trx.py:109 (MS@172.18.28.22:6700) Starting transceiver...
2026-01-29 02:08:10.918 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:08:10.923 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 02:08:10.923 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 02:08:10.923 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:08:10.924 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:08:11.005 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:08:11.007 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:08:11.009 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 02:08:11.009 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 02:08:11.027 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 02:08:11.028 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 02:08:11.028 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 02:08:11.029 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:08:11.029 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 02:08:11.029 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 02:08:11.029 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.28.22:6700) Recv POWERON CMD
2026-01-29 02:08:11.029 [INFO] ctrl_if_trx.py:109 (MS@172.18.28.22:6700) Starting transceiver...
2026-01-29 02:08:11.062 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:08:11.067 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 02:08:11.067 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 02:08:11.068 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:08:11.068 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:08:11.240 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:08:11.243 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:08:11.245 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 02:08:11.245 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 02:08:11.254 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 02:08:11.254 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 02:08:11.254 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 02:08:11.255 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:08:11.255 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 02:08:11.255 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 02:08:11.255 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.28.22:6700) Recv POWERON CMD
2026-01-29 02:08:11.255 [INFO] ctrl_if_trx.py:109 (MS@172.18.28.22:6700) Starting transceiver...
2026-01-29 02:08:11.258 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-01-29 02:08:11.306 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:08:11.312 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 02:08:11.312 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 02:08:11.313 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:08:11.313 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:08:11.411 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:08:11.414 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:08:11.415 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 02:08:11.416 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 02:08:11.425 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 02:08:11.425 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 02:08:11.425 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 02:08:11.426 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:08:11.426 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 02:08:11.426 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 02:08:11.426 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.28.22:6700) Recv POWERON CMD
2026-01-29 02:08:11.426 [INFO] ctrl_if_trx.py:109 (MS@172.18.28.22:6700) Starting transceiver...
2026-01-29 02:08:11.440 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:08:11.443 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 02:08:11.443 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 02:08:11.443 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:08:11.443 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:08:11.647 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:08:11.650 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:08:11.652 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 02:08:11.652 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 02:08:11.661 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 02:08:11.661 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:08:11.661 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:08:11.661 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:08:11.663 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 02:08:11.663 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:08:11.663 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:08:11.663 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:08:11.663 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.28.20:5700) Recv POWEROFF cmd
2026-01-29 02:08:11.663 [INFO] ctrl_if_trx.py:117 (BTS@172.18.28.20:5700) Stopping transceiver...
2026-01-29 02:08:11.663 [INFO] transceiver.py:246 Stopping clock generator
2026-01-29 02:08:11.664 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=395 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:08:11.664 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=395 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:08:11.664 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=395 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:08:11.664 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=395 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:08:11.664 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=395 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:08:11.664 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=395 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:08:16.664 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.28.20:5700) Recv POWEROFF cmd
2026-01-29 02:08:16.664 [INFO] ctrl_if_trx.py:117 (BTS@172.18.28.20:5700) Stopping transceiver...
2026-01-29 02:08:16.666 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:08:16.667 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:08:16.667 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:08:16.667 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 02:08:16.675 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 02:08:16.676 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.28.20:5700) Recv SETFORMAT cmd
2026-01-29 02:08:16.677 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.28.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:08:16.677 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.28.20:5700) Recv SETFORMAT cmd
2026-01-29 02:08:16.677 [INFO] ctrl_if_trx.py:201 (BTS@172.18.28.20:5700) TRXD header version 1 -> 1
2026-01-29 02:08:16.680 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.28.20:5700/1) Recv RXTUNE cmd
2026-01-29 02:08:16.681 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.28.20:5700/1) Recv TXTUNE cmd
2026-01-29 02:08:16.681 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.28.20:5700/1) Recv SETFORMAT cmd
2026-01-29 02:08:16.681 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.28.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:08:16.682 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:08:16.682 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.28.20:5700/1) Recv NOMTXPOWER cmd
2026-01-29 02:08:16.682 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.28.20:5700/1) Recv SETFORMAT cmd
2026-01-29 02:08:16.683 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.28.20:5700/1) TRXD header version 1 -> 1
2026-01-29 02:08:16.684 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.28.20:5700/2) Recv RXTUNE cmd
2026-01-29 02:08:16.684 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.28.20:5700/2) Recv TXTUNE cmd
2026-01-29 02:08:16.684 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.28.20:5700/2) Recv SETFORMAT cmd
2026-01-29 02:08:16.684 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.28.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:08:16.684 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:08:16.684 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.28.20:5700/2) Recv NOMTXPOWER cmd
2026-01-29 02:08:16.684 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.28.20:5700/2) Recv SETFORMAT cmd
2026-01-29 02:08:16.684 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.28.20:5700/2) TRXD header version 1 -> 1
2026-01-29 02:08:16.686 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.28.20:5700/3) Recv RXTUNE cmd
2026-01-29 02:08:16.686 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.28.20:5700/3) Recv TXTUNE cmd
2026-01-29 02:08:16.686 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.28.20:5700/3) Recv SETFORMAT cmd
2026-01-29 02:08:16.686 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.28.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:08:16.686 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:08:16.687 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.28.20:5700/3) Recv NOMTXPOWER cmd
2026-01-29 02:08:16.687 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.28.20:5700/3) Recv SETFORMAT cmd
2026-01-29 02:08:16.687 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.28.20:5700/3) TRXD header version 1 -> 1
2026-01-29 02:08:16.689 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.28.20:5700) Recv RXTUNE cmd
2026-01-29 02:08:16.689 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETTSC
2026-01-29 02:08:16.689 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETTSC
2026-01-29 02:08:16.689 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETTSC
2026-01-29 02:08:16.689 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.28.20:5700) Recv TXTUNE cmd
2026-01-29 02:08:16.689 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETRXGAIN
2026-01-29 02:08:16.690 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETRXGAIN
2026-01-29 02:08:16.690 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETRXGAIN
2026-01-29 02:08:16.690 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETTSC
2026-01-29 02:08:16.690 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:08:16.690 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:08:16.690 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:08:16.690 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.28.20:5700) Recv NOMTXPOWER cmd
2026-01-29 02:08:16.690 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:08:16.690 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:08:16.690 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:08:16.690 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.28.20:5700) Recv POWERON CMD
2026-01-29 02:08:16.690 [INFO] ctrl_if_trx.py:109 (BTS@172.18.28.20:5700) Starting transceiver...
2026-01-29 02:08:16.690 [INFO] transceiver.py:243 Starting clock generator
2026-01-29 02:08:16.690 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-01-29 02:08:16.690 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:08:16.690 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:08:16.690 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:08:16.690 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETRXGAIN
2026-01-29 02:08:16.690 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:08:16.690 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:08:16.691 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:08:16.691 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:08:16.691 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:08:16.691 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:08:16.691 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:08:16.691 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:08:16.691 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:08:16.691 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:08:16.691 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:08:16.691 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:08:16.691 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:08:16.691 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:08:16.691 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:08:16.691 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:08:16.691 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:08:16.691 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:08:16.691 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:08:16.691 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:08:16.691 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:08:16.691 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:08:16.691 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:08:16.695 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-01-29 02:08:17.178 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-01-29 02:08:17.218 [DEBUG] fake_trx.py:278 (BTS@172.18.28.20:5700) Recv FAKE_TOA cmd
2026-01-29 02:08:17.220 [DEBUG] fake_trx.py:297 (BTS@172.18.28.20:5700) Recv FAKE_RSSI cmd
2026-01-29 02:08:17.223 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:08:17.224 [DEBUG] fake_trx.py:322 (BTS@172.18.28.20:5700) Recv FAKE_CI cmd
2026-01-29 02:08:17.236 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 02:08:17.236 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 02:08:17.236 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 02:08:17.237 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:08:17.237 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 02:08:17.237 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 02:08:17.237 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.28.22:6700) Recv POWERON CMD
2026-01-29 02:08:17.237 [INFO] ctrl_if_trx.py:109 (MS@172.18.28.22:6700) Starting transceiver...
2026-01-29 02:08:17.270 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:08:17.273 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 02:08:17.273 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 02:08:17.273 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:08:17.273 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:08:17.655 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-01-29 02:08:17.693 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 02:08:17.693 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:08:17.694 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:08:17.696 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:08:18.133 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-01-29 02:08:18.154 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:08:18.156 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:08:18.158 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 02:08:18.158 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 02:08:18.177 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 02:08:18.177 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 02:08:18.177 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 02:08:18.178 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:08:18.178 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 02:08:18.178 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 02:08:18.178 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.28.22:6700) Recv POWERON CMD
2026-01-29 02:08:18.178 [INFO] ctrl_if_trx.py:109 (MS@172.18.28.22:6700) Starting transceiver...
2026-01-29 02:08:18.228 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:08:18.233 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 02:08:18.233 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 02:08:18.233 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:08:18.234 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:08:18.610 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-01-29 02:08:18.694 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 02:08:18.694 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:08:18.694 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:08:18.697 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:08:19.088 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-01-29 02:08:19.128 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:08:19.131 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:08:19.132 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 02:08:19.132 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 02:08:19.150 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 02:08:19.150 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 02:08:19.150 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 02:08:19.151 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:08:19.151 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 02:08:19.151 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 02:08:19.151 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.28.22:6700) Recv POWERON CMD
2026-01-29 02:08:19.151 [INFO] ctrl_if_trx.py:109 (MS@172.18.28.22:6700) Starting transceiver...
2026-01-29 02:08:19.183 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:08:19.189 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 02:08:19.189 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 02:08:19.189 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:08:19.189 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:08:19.566 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-01-29 02:08:19.694 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 02:08:19.695 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:08:19.695 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:08:19.698 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:08:20.044 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-01-29 02:08:20.344 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:08:20.347 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:08:20.348 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 02:08:20.348 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 02:08:20.368 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 02:08:20.368 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 02:08:20.368 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 02:08:20.370 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:08:20.370 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 02:08:20.370 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 02:08:20.370 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.28.22:6700) Recv POWERON CMD
2026-01-29 02:08:20.370 [INFO] ctrl_if_trx.py:109 (MS@172.18.28.22:6700) Starting transceiver...
2026-01-29 02:08:20.421 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:08:20.426 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 02:08:20.426 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 02:08:20.426 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:08:20.427 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:08:20.522 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-01-29 02:08:20.696 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:08:20.696 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 02:08:20.696 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:08:20.699 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:08:21.000 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-01-29 02:08:21.316 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:08:21.319 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:08:21.320 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 02:08:21.320 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 02:08:21.340 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 02:08:21.340 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 02:08:21.340 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 02:08:21.341 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:08:21.341 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 02:08:21.341 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 02:08:21.341 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.28.22:6700) Recv POWERON CMD
2026-01-29 02:08:21.341 [INFO] ctrl_if_trx.py:109 (MS@172.18.28.22:6700) Starting transceiver...
2026-01-29 02:08:21.377 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:08:21.382 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 02:08:21.382 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 02:08:21.383 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:08:21.383 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:08:21.478 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-01-29 02:08:21.696 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:08:21.696 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 02:08:21.697 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:08:21.700 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:08:21.955 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-01-29 02:08:21.994 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:08:21.997 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:08:21.999 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 02:08:21.999 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 02:08:22.018 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 02:08:22.018 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 02:08:22.018 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 02:08:22.020 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:08:22.020 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 02:08:22.020 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 02:08:22.020 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.28.22:6700) Recv POWERON CMD
2026-01-29 02:08:22.020 [INFO] ctrl_if_trx.py:109 (MS@172.18.28.22:6700) Starting transceiver...
2026-01-29 02:08:22.050 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:08:22.054 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 02:08:22.055 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 02:08:22.055 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:08:22.055 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:08:22.434 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-01-29 02:08:22.912 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-01-29 02:08:22.950 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:08:22.953 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:08:22.955 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 02:08:22.955 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 02:08:22.974 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 02:08:22.974 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 02:08:22.975 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 02:08:22.976 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:08:22.976 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 02:08:22.976 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 02:08:22.976 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.28.22:6700) Recv POWERON CMD
2026-01-29 02:08:22.976 [INFO] ctrl_if_trx.py:109 (MS@172.18.28.22:6700) Starting transceiver...
2026-01-29 02:08:23.007 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:08:23.012 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 02:08:23.012 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 02:08:23.012 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:08:23.012 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:08:23.389 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-01-29 02:08:23.853 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:08:23.856 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:08:23.857 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 02:08:23.857 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 02:08:23.866 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-01-29 02:08:23.877 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 02:08:23.877 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 02:08:23.877 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 02:08:23.879 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:08:23.879 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 02:08:23.879 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 02:08:23.879 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.28.22:6700) Recv POWERON CMD
2026-01-29 02:08:23.879 [INFO] ctrl_if_trx.py:109 (MS@172.18.28.22:6700) Starting transceiver...
2026-01-29 02:08:23.915 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:08:23.919 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 02:08:23.920 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 02:08:23.920 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:08:23.920 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:08:24.344 [DEBUG] clck_gen.py:113 IND CLOCK 1632
2026-01-29 02:08:24.807 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:08:24.810 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:08:24.811 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 02:08:24.811 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 02:08:24.816 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 02:08:24.816 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:08:24.816 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:08:24.816 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:08:24.817 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 02:08:24.817 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:08:24.817 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:08:24.817 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.28.20:5700) Recv POWEROFF cmd
2026-01-29 02:08:24.817 [INFO] ctrl_if_trx.py:117 (BTS@172.18.28.20:5700) Stopping transceiver...
2026-01-29 02:08:24.817 [INFO] transceiver.py:246 Stopping clock generator
2026-01-29 02:08:24.817 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:08:29.820 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.28.20:5700) Recv POWEROFF cmd
2026-01-29 02:08:29.821 [INFO] ctrl_if_trx.py:117 (BTS@172.18.28.20:5700) Stopping transceiver...
2026-01-29 02:08:29.822 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:08:29.823 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:08:29.824 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:08:29.825 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 02:08:29.837 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 02:08:29.838 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.28.20:5700) Recv SETFORMAT cmd
2026-01-29 02:08:29.838 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.28.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:08:29.838 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.28.20:5700) Recv SETFORMAT cmd
2026-01-29 02:08:29.838 [INFO] ctrl_if_trx.py:201 (BTS@172.18.28.20:5700) TRXD header version 1 -> 1
2026-01-29 02:08:29.840 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.28.20:5700/1) Recv RXTUNE cmd
2026-01-29 02:08:29.841 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.28.20:5700/1) Recv TXTUNE cmd
2026-01-29 02:08:29.841 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.28.20:5700/1) Recv SETFORMAT cmd
2026-01-29 02:08:29.841 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.28.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:08:29.841 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:08:29.841 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.28.20:5700/1) Recv NOMTXPOWER cmd
2026-01-29 02:08:29.841 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.28.20:5700/1) Recv SETFORMAT cmd
2026-01-29 02:08:29.841 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.28.20:5700/1) TRXD header version 1 -> 1
2026-01-29 02:08:29.843 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.28.20:5700/2) Recv RXTUNE cmd
2026-01-29 02:08:29.843 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.28.20:5700/2) Recv TXTUNE cmd
2026-01-29 02:08:29.843 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.28.20:5700/2) Recv SETFORMAT cmd
2026-01-29 02:08:29.843 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.28.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:08:29.843 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:08:29.843 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.28.20:5700/2) Recv NOMTXPOWER cmd
2026-01-29 02:08:29.844 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.28.20:5700/2) Recv SETFORMAT cmd
2026-01-29 02:08:29.844 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.28.20:5700/2) TRXD header version 1 -> 1
2026-01-29 02:08:29.845 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.28.20:5700/3) Recv RXTUNE cmd
2026-01-29 02:08:29.845 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.28.20:5700/3) Recv TXTUNE cmd
2026-01-29 02:08:29.845 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.28.20:5700/3) Recv SETFORMAT cmd
2026-01-29 02:08:29.845 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.28.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:08:29.846 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:08:29.846 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.28.20:5700/3) Recv NOMTXPOWER cmd
2026-01-29 02:08:29.846 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.28.20:5700/3) Recv SETFORMAT cmd
2026-01-29 02:08:29.846 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.28.20:5700/3) TRXD header version 1 -> 1
2026-01-29 02:08:29.848 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.28.20:5700) Recv RXTUNE cmd
2026-01-29 02:08:29.848 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETTSC
2026-01-29 02:08:29.848 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETTSC
2026-01-29 02:08:29.848 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETTSC
2026-01-29 02:08:29.848 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.28.20:5700) Recv TXTUNE cmd
2026-01-29 02:08:29.848 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETRXGAIN
2026-01-29 02:08:29.848 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETRXGAIN
2026-01-29 02:08:29.848 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETRXGAIN
2026-01-29 02:08:29.849 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETTSC
2026-01-29 02:08:29.849 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:08:29.849 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:08:29.849 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:08:29.849 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.28.20:5700) Recv NOMTXPOWER cmd
2026-01-29 02:08:29.849 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:08:29.849 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:08:29.849 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:08:29.849 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.28.20:5700) Recv POWERON CMD
2026-01-29 02:08:29.849 [INFO] ctrl_if_trx.py:109 (BTS@172.18.28.20:5700) Starting transceiver...
2026-01-29 02:08:29.849 [INFO] transceiver.py:243 Starting clock generator
2026-01-29 02:08:29.849 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-01-29 02:08:29.849 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:08:29.849 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:08:29.849 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:08:29.849 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETRXGAIN
2026-01-29 02:08:29.849 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:08:29.849 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:08:29.849 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:08:29.849 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:08:29.849 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:08:29.849 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:08:29.850 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:08:29.850 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:08:29.850 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:08:29.850 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:08:29.850 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:08:29.850 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:08:29.850 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:08:29.850 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:08:29.850 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:08:29.850 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:08:29.850 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:08:29.850 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:08:29.850 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:08:29.850 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:08:29.850 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:08:29.850 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:08:29.850 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:08:29.854 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-01-29 02:08:30.336 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-01-29 02:08:30.381 [DEBUG] fake_trx.py:278 (BTS@172.18.28.20:5700) Recv FAKE_TOA cmd
2026-01-29 02:08:30.384 [DEBUG] fake_trx.py:297 (BTS@172.18.28.20:5700) Recv FAKE_RSSI cmd
2026-01-29 02:08:30.385 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:08:30.386 [DEBUG] fake_trx.py:322 (BTS@172.18.28.20:5700) Recv FAKE_CI cmd
2026-01-29 02:08:30.408 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 02:08:30.408 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 02:08:30.408 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 02:08:30.412 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:08:30.413 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 02:08:30.413 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 02:08:30.413 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.28.22:6700) Recv POWERON CMD
2026-01-29 02:08:30.413 [INFO] ctrl_if_trx.py:109 (MS@172.18.28.22:6700) Starting transceiver...
2026-01-29 02:08:30.433 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:08:30.438 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 02:08:30.438 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 02:08:30.439 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:08:30.439 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:08:30.537 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:08:30.540 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:08:30.542 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 02:08:30.542 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 02:08:30.559 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 02:08:30.559 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 02:08:30.559 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 02:08:30.560 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:08:30.560 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 02:08:30.560 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 02:08:30.560 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.28.22:6700) Recv POWERON CMD
2026-01-29 02:08:30.560 [INFO] ctrl_if_trx.py:109 (MS@172.18.28.22:6700) Starting transceiver...
2026-01-29 02:08:30.570 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:08:30.572 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 02:08:30.572 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 02:08:30.572 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:08:30.572 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:08:30.717 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:08:30.721 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:08:30.723 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 02:08:30.723 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 02:08:30.740 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 02:08:30.740 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 02:08:30.740 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 02:08:30.741 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:08:30.741 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 02:08:30.742 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 02:08:30.742 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.28.22:6700) Recv POWERON CMD
2026-01-29 02:08:30.742 [INFO] ctrl_if_trx.py:109 (MS@172.18.28.22:6700) Starting transceiver...
2026-01-29 02:08:30.755 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:08:30.758 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 02:08:30.759 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 02:08:30.759 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:08:30.759 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:08:30.813 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-01-29 02:08:30.852 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 02:08:30.852 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:08:30.854 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:08:30.857 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:08:31.040 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:08:31.043 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:08:31.045 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 02:08:31.045 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 02:08:31.066 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 02:08:31.066 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 02:08:31.066 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 02:08:31.067 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:08:31.067 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 02:08:31.068 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 02:08:31.068 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.28.22:6700) Recv POWERON CMD
2026-01-29 02:08:31.068 [INFO] ctrl_if_trx.py:109 (MS@172.18.28.22:6700) Starting transceiver...
2026-01-29 02:08:31.097 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:08:31.103 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 02:08:31.103 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 02:08:31.104 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:08:31.104 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:08:31.290 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-01-29 02:08:31.444 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:08:31.447 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:08:31.449 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 02:08:31.449 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 02:08:31.458 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 02:08:31.459 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:08:31.459 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:08:31.459 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:08:31.465 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 02:08:31.465 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:08:31.465 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:08:31.465 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:08:31.465 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.28.20:5700) Recv POWEROFF cmd
2026-01-29 02:08:31.465 [INFO] ctrl_if_trx.py:117 (BTS@172.18.28.20:5700) Stopping transceiver...
2026-01-29 02:08:31.465 [INFO] transceiver.py:246 Stopping clock generator
2026-01-29 02:08:31.466 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=344 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:08:31.466 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=344 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:08:36.462 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.28.20:5700) Recv POWEROFF cmd
2026-01-29 02:08:36.462 [INFO] ctrl_if_trx.py:117 (BTS@172.18.28.20:5700) Stopping transceiver...
2026-01-29 02:08:36.464 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:08:36.465 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:08:36.467 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:08:36.469 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 02:08:36.477 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 02:08:36.478 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.28.20:5700) Recv SETFORMAT cmd
2026-01-29 02:08:36.478 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.28.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:08:36.478 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.28.20:5700) Recv SETFORMAT cmd
2026-01-29 02:08:36.479 [INFO] ctrl_if_trx.py:201 (BTS@172.18.28.20:5700) TRXD header version 1 -> 1
2026-01-29 02:08:36.480 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.28.20:5700/1) Recv RXTUNE cmd
2026-01-29 02:08:36.480 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.28.20:5700/1) Recv TXTUNE cmd
2026-01-29 02:08:36.481 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.28.20:5700/1) Recv SETFORMAT cmd
2026-01-29 02:08:36.481 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.28.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:08:36.481 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:08:36.481 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.28.20:5700/1) Recv NOMTXPOWER cmd
2026-01-29 02:08:36.482 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.28.20:5700/1) Recv SETFORMAT cmd
2026-01-29 02:08:36.482 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.28.20:5700/1) TRXD header version 1 -> 1
2026-01-29 02:08:36.482 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.28.20:5700/2) Recv RXTUNE cmd
2026-01-29 02:08:36.482 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.28.20:5700/2) Recv TXTUNE cmd
2026-01-29 02:08:36.482 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.28.20:5700/2) Recv SETFORMAT cmd
2026-01-29 02:08:36.482 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.28.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:08:36.483 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:08:36.483 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.28.20:5700/2) Recv NOMTXPOWER cmd
2026-01-29 02:08:36.483 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.28.20:5700/2) Recv SETFORMAT cmd
2026-01-29 02:08:36.483 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.28.20:5700/2) TRXD header version 1 -> 1
2026-01-29 02:08:36.484 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.28.20:5700/3) Recv RXTUNE cmd
2026-01-29 02:08:36.484 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.28.20:5700/3) Recv TXTUNE cmd
2026-01-29 02:08:36.484 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.28.20:5700/3) Recv SETFORMAT cmd
2026-01-29 02:08:36.484 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.28.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:08:36.484 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:08:36.484 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.28.20:5700/3) Recv NOMTXPOWER cmd
2026-01-29 02:08:36.484 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.28.20:5700/3) Recv SETFORMAT cmd
2026-01-29 02:08:36.484 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.28.20:5700/3) TRXD header version 1 -> 1
2026-01-29 02:08:36.486 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.28.20:5700) Recv RXTUNE cmd
2026-01-29 02:08:36.486 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETTSC
2026-01-29 02:08:36.486 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETTSC
2026-01-29 02:08:36.487 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETTSC
2026-01-29 02:08:36.487 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.28.20:5700) Recv TXTUNE cmd
2026-01-29 02:08:36.487 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETRXGAIN
2026-01-29 02:08:36.487 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETRXGAIN
2026-01-29 02:08:36.487 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETRXGAIN
2026-01-29 02:08:36.487 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETTSC
2026-01-29 02:08:36.487 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:08:36.487 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:08:36.487 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:08:36.487 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.28.20:5700) Recv NOMTXPOWER cmd
2026-01-29 02:08:36.487 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:08:36.487 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:08:36.487 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:08:36.487 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.28.20:5700) Recv POWERON CMD
2026-01-29 02:08:36.487 [INFO] ctrl_if_trx.py:109 (BTS@172.18.28.20:5700) Starting transceiver...
2026-01-29 02:08:36.487 [INFO] transceiver.py:243 Starting clock generator
2026-01-29 02:08:36.487 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-01-29 02:08:36.487 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:08:36.487 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:08:36.487 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:08:36.487 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETRXGAIN
2026-01-29 02:08:36.487 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:08:36.487 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:08:36.487 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:08:36.487 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:08:36.487 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:08:36.487 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:08:36.487 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:08:36.488 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:08:36.488 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:08:36.488 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:08:36.488 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:08:36.488 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:08:36.488 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:08:36.488 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:08:36.488 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:08:36.488 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:08:36.488 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:08:36.488 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:08:36.488 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:08:36.488 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:08:36.488 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:08:36.488 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:08:36.488 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:08:36.492 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-01-29 02:08:36.975 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-01-29 02:08:37.010 [DEBUG] fake_trx.py:278 (BTS@172.18.28.20:5700) Recv FAKE_TOA cmd
2026-01-29 02:08:37.013 [DEBUG] fake_trx.py:297 (BTS@172.18.28.20:5700) Recv FAKE_RSSI cmd
2026-01-29 02:08:37.015 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:08:37.015 [DEBUG] fake_trx.py:322 (BTS@172.18.28.20:5700) Recv FAKE_CI cmd
2026-01-29 02:08:37.040 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 02:08:37.040 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 02:08:37.040 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 02:08:37.044 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:08:37.044 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 02:08:37.044 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 02:08:37.044 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.28.22:6700) Recv POWERON CMD
2026-01-29 02:08:37.044 [INFO] ctrl_if_trx.py:109 (MS@172.18.28.22:6700) Starting transceiver...
2026-01-29 02:08:37.073 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:08:37.078 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 02:08:37.079 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 02:08:37.079 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:08:37.079 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:08:37.176 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:08:37.178 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:08:37.180 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 02:08:37.180 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 02:08:37.199 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 02:08:37.199 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 02:08:37.200 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 02:08:37.201 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:08:37.201 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 02:08:37.201 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 02:08:37.201 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.28.22:6700) Recv POWERON CMD
2026-01-29 02:08:37.201 [INFO] ctrl_if_trx.py:109 (MS@172.18.28.22:6700) Starting transceiver...
2026-01-29 02:08:37.208 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:08:37.209 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 02:08:37.210 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 02:08:37.210 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:08:37.210 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:08:37.355 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:08:37.358 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:08:37.359 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 02:08:37.360 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 02:08:37.377 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 02:08:37.377 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 02:08:37.377 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 02:08:37.378 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:08:37.378 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 02:08:37.378 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 02:08:37.378 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.28.22:6700) Recv POWERON CMD
2026-01-29 02:08:37.378 [INFO] ctrl_if_trx.py:109 (MS@172.18.28.22:6700) Starting transceiver...
2026-01-29 02:08:37.394 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:08:37.398 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 02:08:37.398 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 02:08:37.398 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:08:37.398 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:08:37.451 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-01-29 02:08:37.489 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 02:08:37.511 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:08:37.511 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:08:37.512 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:08:37.679 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:08:37.682 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:08:37.683 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 02:08:37.683 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 02:08:37.701 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 02:08:37.701 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 02:08:37.701 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 02:08:37.702 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:08:37.702 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 02:08:37.702 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 02:08:37.703 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.28.22:6700) Recv POWERON CMD
2026-01-29 02:08:37.703 [INFO] ctrl_if_trx.py:109 (MS@172.18.28.22:6700) Starting transceiver...
2026-01-29 02:08:37.736 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:08:37.741 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 02:08:37.742 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 02:08:37.742 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:08:37.743 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:08:37.929 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-01-29 02:08:38.082 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:08:38.084 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:08:38.085 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 02:08:38.086 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 02:08:38.090 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 02:08:38.090 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:08:38.090 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:08:38.090 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:08:38.091 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 02:08:38.091 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:08:38.091 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:08:38.091 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.28.20:5700) Recv POWEROFF cmd
2026-01-29 02:08:38.091 [INFO] ctrl_if_trx.py:117 (BTS@172.18.28.20:5700) Stopping transceiver...
2026-01-29 02:08:38.091 [INFO] transceiver.py:246 Stopping clock generator
2026-01-29 02:08:38.091 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:08:38.091 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=343 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:08:38.091 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=343 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:08:38.091 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=343 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:08:38.091 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=343 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:08:38.091 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=343 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:08:38.091 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=343 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:08:38.091 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=343 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:08:38.091 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=343 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:08:43.094 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.28.20:5700) Recv POWEROFF cmd
2026-01-29 02:08:43.094 [INFO] ctrl_if_trx.py:117 (BTS@172.18.28.20:5700) Stopping transceiver...
2026-01-29 02:08:43.095 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:08:43.096 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:08:43.097 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:08:43.097 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 02:08:43.107 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 02:08:43.107 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.28.20:5700) Recv SETFORMAT cmd
2026-01-29 02:08:43.107 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.28.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:08:43.107 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.28.20:5700) Recv SETFORMAT cmd
2026-01-29 02:08:43.107 [INFO] ctrl_if_trx.py:201 (BTS@172.18.28.20:5700) TRXD header version 1 -> 1
2026-01-29 02:08:43.108 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.28.20:5700/1) Recv RXTUNE cmd
2026-01-29 02:08:43.109 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.28.20:5700/1) Recv TXTUNE cmd
2026-01-29 02:08:43.109 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.28.20:5700/1) Recv SETFORMAT cmd
2026-01-29 02:08:43.109 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.28.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:08:43.109 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:08:43.110 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.28.20:5700/1) Recv NOMTXPOWER cmd
2026-01-29 02:08:43.110 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.28.20:5700/1) Recv SETFORMAT cmd
2026-01-29 02:08:43.110 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.28.20:5700/1) TRXD header version 1 -> 1
2026-01-29 02:08:43.111 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.28.20:5700/2) Recv RXTUNE cmd
2026-01-29 02:08:43.111 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.28.20:5700/2) Recv TXTUNE cmd
2026-01-29 02:08:43.111 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.28.20:5700/2) Recv SETFORMAT cmd
2026-01-29 02:08:43.111 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.28.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:08:43.111 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:08:43.111 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.28.20:5700/2) Recv NOMTXPOWER cmd
2026-01-29 02:08:43.112 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.28.20:5700/2) Recv SETFORMAT cmd
2026-01-29 02:08:43.112 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.28.20:5700/2) TRXD header version 1 -> 1
2026-01-29 02:08:43.114 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.28.20:5700/3) Recv RXTUNE cmd
2026-01-29 02:08:43.114 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.28.20:5700/3) Recv TXTUNE cmd
2026-01-29 02:08:43.114 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.28.20:5700/3) Recv SETFORMAT cmd
2026-01-29 02:08:43.114 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.28.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:08:43.114 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:08:43.114 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.28.20:5700/3) Recv NOMTXPOWER cmd
2026-01-29 02:08:43.115 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.28.20:5700/3) Recv SETFORMAT cmd
2026-01-29 02:08:43.115 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.28.20:5700/3) TRXD header version 1 -> 1
2026-01-29 02:08:43.118 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.28.20:5700) Recv RXTUNE cmd
2026-01-29 02:08:43.118 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETTSC
2026-01-29 02:08:43.118 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETTSC
2026-01-29 02:08:43.118 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETTSC
2026-01-29 02:08:43.118 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.28.20:5700) Recv TXTUNE cmd
2026-01-29 02:08:43.118 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETRXGAIN
2026-01-29 02:08:43.118 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETRXGAIN
2026-01-29 02:08:43.118 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETRXGAIN
2026-01-29 02:08:43.119 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETTSC
2026-01-29 02:08:43.119 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:08:43.119 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:08:43.119 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:08:43.119 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.28.20:5700) Recv NOMTXPOWER cmd
2026-01-29 02:08:43.119 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:08:43.119 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:08:43.119 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:08:43.119 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.28.20:5700) Recv POWERON CMD
2026-01-29 02:08:43.119 [INFO] ctrl_if_trx.py:109 (BTS@172.18.28.20:5700) Starting transceiver...
2026-01-29 02:08:43.119 [INFO] transceiver.py:243 Starting clock generator
2026-01-29 02:08:43.119 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-01-29 02:08:43.119 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:08:43.119 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:08:43.119 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:08:43.119 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETRXGAIN
2026-01-29 02:08:43.120 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:08:43.120 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:08:43.120 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:08:43.120 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:08:43.120 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:08:43.120 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:08:43.120 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:08:43.120 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:08:43.120 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:08:43.120 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:08:43.120 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:08:43.120 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:08:43.120 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:08:43.120 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:08:43.120 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:08:43.120 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:08:43.120 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:08:43.120 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:08:43.120 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:08:43.120 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:08:43.120 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:08:43.120 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:08:43.121 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:08:43.124 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-01-29 02:08:43.607 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-01-29 02:08:43.647 [DEBUG] fake_trx.py:278 (BTS@172.18.28.20:5700) Recv FAKE_TOA cmd
2026-01-29 02:08:43.649 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:08:43.650 [DEBUG] fake_trx.py:297 (BTS@172.18.28.20:5700) Recv FAKE_RSSI cmd
2026-01-29 02:08:43.654 [DEBUG] fake_trx.py:322 (BTS@172.18.28.20:5700) Recv FAKE_CI cmd
2026-01-29 02:08:43.675 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 02:08:43.675 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 02:08:43.676 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 02:08:43.680 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:08:43.680 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 02:08:43.681 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 02:08:43.681 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.28.22:6700) Recv POWERON CMD
2026-01-29 02:08:43.681 [INFO] ctrl_if_trx.py:109 (MS@172.18.28.22:6700) Starting transceiver...
2026-01-29 02:08:43.704 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:08:43.710 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 02:08:43.710 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 02:08:43.711 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:08:43.711 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:08:43.807 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:08:43.810 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:08:43.811 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 02:08:43.811 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 02:08:43.828 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 02:08:43.828 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 02:08:43.829 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 02:08:43.830 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:08:43.830 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 02:08:43.830 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 02:08:43.830 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.28.22:6700) Recv POWERON CMD
2026-01-29 02:08:43.830 [INFO] ctrl_if_trx.py:109 (MS@172.18.28.22:6700) Starting transceiver...
2026-01-29 02:08:43.840 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:08:43.842 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 02:08:43.842 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 02:08:43.842 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:08:43.842 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:08:43.987 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:08:43.990 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:08:43.991 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 02:08:43.991 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 02:08:44.009 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 02:08:44.009 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 02:08:44.009 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 02:08:44.010 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:08:44.010 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 02:08:44.010 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 02:08:44.011 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.28.22:6700) Recv POWERON CMD
2026-01-29 02:08:44.011 [INFO] ctrl_if_trx.py:109 (MS@172.18.28.22:6700) Starting transceiver...
2026-01-29 02:08:44.026 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:08:44.029 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 02:08:44.029 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 02:08:44.029 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:08:44.029 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:08:44.083 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-01-29 02:08:44.122 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 02:08:44.122 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:08:44.123 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:08:44.125 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:08:44.310 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:08:44.313 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:08:44.314 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 02:08:44.314 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 02:08:44.332 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 02:08:44.333 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 02:08:44.333 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 02:08:44.334 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:08:44.334 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 02:08:44.334 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 02:08:44.334 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.28.22:6700) Recv POWERON CMD
2026-01-29 02:08:44.334 [INFO] ctrl_if_trx.py:109 (MS@172.18.28.22:6700) Starting transceiver...
2026-01-29 02:08:44.367 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:08:44.373 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 02:08:44.373 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 02:08:44.373 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:08:44.373 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:08:44.557 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-01-29 02:08:44.707 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:08:44.710 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:08:44.712 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 02:08:44.712 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 02:08:44.721 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 02:08:44.721 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:08:44.721 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:08:44.721 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:08:44.723 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 02:08:44.723 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:08:44.723 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:08:44.723 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:08:44.723 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.28.20:5700) Recv POWEROFF cmd
2026-01-29 02:08:44.723 [INFO] ctrl_if_trx.py:117 (BTS@172.18.28.20:5700) Stopping transceiver...
2026-01-29 02:08:44.723 [INFO] transceiver.py:246 Stopping clock generator
2026-01-29 02:08:44.723 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=343 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:08:44.723 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=343 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:08:44.723 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=343 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:08:44.723 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=343 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:08:44.723 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=343 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:08:44.723 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=343 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:08:44.723 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=344 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:08:44.723 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=344 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:08:44.723 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=344 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:08:44.723 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=344 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:08:44.723 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=344 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:08:44.723 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=344 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:08:44.723 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=344 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:08:44.723 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=344 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:08:49.725 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.28.20:5700) Recv POWEROFF cmd
2026-01-29 02:08:49.725 [INFO] ctrl_if_trx.py:117 (BTS@172.18.28.20:5700) Stopping transceiver...
2026-01-29 02:08:49.727 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:08:49.728 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:08:49.729 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:08:49.729 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 02:08:49.734 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 02:08:49.735 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.28.20:5700) Recv SETFORMAT cmd
2026-01-29 02:08:49.735 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.28.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:08:49.736 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.28.20:5700) Recv SETFORMAT cmd
2026-01-29 02:08:49.736 [INFO] ctrl_if_trx.py:201 (BTS@172.18.28.20:5700) TRXD header version 1 -> 1
2026-01-29 02:08:49.738 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.28.20:5700/1) Recv RXTUNE cmd
2026-01-29 02:08:49.739 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.28.20:5700/1) Recv TXTUNE cmd
2026-01-29 02:08:49.739 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.28.20:5700/1) Recv SETFORMAT cmd
2026-01-29 02:08:49.739 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.28.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:08:49.740 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:08:49.740 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.28.20:5700/1) Recv NOMTXPOWER cmd
2026-01-29 02:08:49.740 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.28.20:5700/1) Recv SETFORMAT cmd
2026-01-29 02:08:49.740 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.28.20:5700/1) TRXD header version 1 -> 1
2026-01-29 02:08:49.741 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.28.20:5700/2) Recv RXTUNE cmd
2026-01-29 02:08:49.741 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.28.20:5700/2) Recv TXTUNE cmd
2026-01-29 02:08:49.741 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.28.20:5700/2) Recv SETFORMAT cmd
2026-01-29 02:08:49.741 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.28.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:08:49.741 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:08:49.741 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.28.20:5700/2) Recv NOMTXPOWER cmd
2026-01-29 02:08:49.742 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.28.20:5700/2) Recv SETFORMAT cmd
2026-01-29 02:08:49.742 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.28.20:5700/2) TRXD header version 1 -> 1
2026-01-29 02:08:49.744 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.28.20:5700/3) Recv RXTUNE cmd
2026-01-29 02:08:49.744 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.28.20:5700/3) Recv TXTUNE cmd
2026-01-29 02:08:49.744 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.28.20:5700/3) Recv SETFORMAT cmd
2026-01-29 02:08:49.744 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.28.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:08:49.744 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:08:49.744 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.28.20:5700/3) Recv NOMTXPOWER cmd
2026-01-29 02:08:49.744 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.28.20:5700/3) Recv SETFORMAT cmd
2026-01-29 02:08:49.744 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.28.20:5700/3) TRXD header version 1 -> 1
2026-01-29 02:08:49.746 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.28.20:5700) Recv RXTUNE cmd
2026-01-29 02:08:49.746 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETTSC
2026-01-29 02:08:49.747 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETTSC
2026-01-29 02:08:49.747 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETTSC
2026-01-29 02:08:49.747 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.28.20:5700) Recv TXTUNE cmd
2026-01-29 02:08:49.747 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETRXGAIN
2026-01-29 02:08:49.747 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETRXGAIN
2026-01-29 02:08:49.747 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETRXGAIN
2026-01-29 02:08:49.747 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETTSC
2026-01-29 02:08:49.747 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:08:49.747 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:08:49.747 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:08:49.747 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.28.20:5700) Recv NOMTXPOWER cmd
2026-01-29 02:08:49.747 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:08:49.747 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:08:49.747 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:08:49.747 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.28.20:5700) Recv POWERON CMD
2026-01-29 02:08:49.747 [INFO] ctrl_if_trx.py:109 (BTS@172.18.28.20:5700) Starting transceiver...
2026-01-29 02:08:49.747 [INFO] transceiver.py:243 Starting clock generator
2026-01-29 02:08:49.747 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-01-29 02:08:49.747 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:08:49.748 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:08:49.748 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:08:49.748 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETRXGAIN
2026-01-29 02:08:49.748 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:08:49.748 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:08:49.748 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:08:49.748 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:08:49.748 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:08:49.748 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:08:49.748 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:08:49.748 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:08:49.748 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:08:49.748 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:08:49.748 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:08:49.748 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:08:49.748 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:08:49.748 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:08:49.748 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:08:49.748 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:08:49.748 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:08:49.748 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:08:49.748 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:08:49.748 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:08:49.748 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:08:49.748 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:08:49.748 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:08:49.752 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-01-29 02:08:50.236 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-01-29 02:08:50.274 [DEBUG] fake_trx.py:278 (BTS@172.18.28.20:5700) Recv FAKE_TOA cmd
2026-01-29 02:08:50.275 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:08:50.275 [DEBUG] fake_trx.py:297 (BTS@172.18.28.20:5700) Recv FAKE_RSSI cmd
2026-01-29 02:08:50.275 [DEBUG] fake_trx.py:322 (BTS@172.18.28.20:5700) Recv FAKE_CI cmd
2026-01-29 02:08:50.293 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 02:08:50.293 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 02:08:50.293 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 02:08:50.298 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:08:50.298 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 02:08:50.299 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 02:08:50.299 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.28.22:6700) Recv POWERON CMD
2026-01-29 02:08:50.299 [INFO] ctrl_if_trx.py:109 (MS@172.18.28.22:6700) Starting transceiver...
2026-01-29 02:08:50.333 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:08:50.339 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 02:08:50.340 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 02:08:50.340 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:08:50.340 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:08:50.455 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:08:50.458 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:08:50.459 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 02:08:50.459 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 02:08:50.474 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 02:08:50.474 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 02:08:50.475 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 02:08:50.476 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:08:50.476 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 02:08:50.476 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 02:08:50.476 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.28.22:6700) Recv POWERON CMD
2026-01-29 02:08:50.476 [INFO] ctrl_if_trx.py:109 (MS@172.18.28.22:6700) Starting transceiver...
2026-01-29 02:08:50.523 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:08:50.527 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 02:08:50.527 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 02:08:50.528 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:08:50.528 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:08:50.694 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:08:50.697 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:08:50.699 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 02:08:50.699 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 02:08:50.712 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-01-29 02:08:50.716 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 02:08:50.716 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 02:08:50.716 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 02:08:50.718 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:08:50.718 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 02:08:50.718 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 02:08:50.718 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.28.22:6700) Recv POWERON CMD
2026-01-29 02:08:50.718 [INFO] ctrl_if_trx.py:109 (MS@172.18.28.22:6700) Starting transceiver...
2026-01-29 02:08:50.750 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 02:08:50.751 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:08:50.752 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:08:50.753 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:08:50.763 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:08:50.768 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 02:08:50.768 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 02:08:50.769 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:08:50.769 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:08:50.939 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:08:50.942 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:08:50.943 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 02:08:50.944 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 02:08:50.963 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 02:08:50.963 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 02:08:50.963 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 02:08:50.965 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:08:50.965 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 02:08:50.965 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 02:08:50.965 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.28.22:6700) Recv POWERON CMD
2026-01-29 02:08:50.965 [INFO] ctrl_if_trx.py:109 (MS@172.18.28.22:6700) Starting transceiver...
2026-01-29 02:08:50.996 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:08:51.001 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 02:08:51.002 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 02:08:51.002 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:08:51.002 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:08:51.189 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-01-29 02:08:51.343 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:08:51.346 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:08:51.347 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 02:08:51.347 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 02:08:51.357 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 02:08:51.357 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:08:51.357 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:08:51.357 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:08:51.359 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 02:08:51.359 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:08:51.360 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:08:51.360 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:08:51.360 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.28.20:5700) Recv POWEROFF cmd
2026-01-29 02:08:51.360 [INFO] ctrl_if_trx.py:117 (BTS@172.18.28.20:5700) Stopping transceiver...
2026-01-29 02:08:51.360 [INFO] transceiver.py:246 Stopping clock generator
2026-01-29 02:08:56.359 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.28.20:5700) Recv POWEROFF cmd
2026-01-29 02:08:56.359 [INFO] ctrl_if_trx.py:117 (BTS@172.18.28.20:5700) Stopping transceiver...
2026-01-29 02:08:56.361 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:08:56.365 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:08:56.366 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:08:56.366 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 02:08:56.374 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 02:08:56.375 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.28.20:5700) Recv SETFORMAT cmd
2026-01-29 02:08:56.375 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.28.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:08:56.376 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.28.20:5700) Recv SETFORMAT cmd
2026-01-29 02:08:56.376 [INFO] ctrl_if_trx.py:201 (BTS@172.18.28.20:5700) TRXD header version 1 -> 1
2026-01-29 02:08:56.378 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.28.20:5700/1) Recv RXTUNE cmd
2026-01-29 02:08:56.378 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.28.20:5700/1) Recv TXTUNE cmd
2026-01-29 02:08:56.379 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.28.20:5700/1) Recv SETFORMAT cmd
2026-01-29 02:08:56.379 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.28.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:08:56.379 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:08:56.379 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.28.20:5700/1) Recv NOMTXPOWER cmd
2026-01-29 02:08:56.380 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.28.20:5700/1) Recv SETFORMAT cmd
2026-01-29 02:08:56.380 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.28.20:5700/1) TRXD header version 1 -> 1
2026-01-29 02:08:56.380 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.28.20:5700/2) Recv RXTUNE cmd
2026-01-29 02:08:56.381 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.28.20:5700/2) Recv TXTUNE cmd
2026-01-29 02:08:56.381 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.28.20:5700/2) Recv SETFORMAT cmd
2026-01-29 02:08:56.381 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.28.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:08:56.381 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:08:56.381 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.28.20:5700/2) Recv NOMTXPOWER cmd
2026-01-29 02:08:56.381 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.28.20:5700/2) Recv SETFORMAT cmd
2026-01-29 02:08:56.381 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.28.20:5700/2) TRXD header version 1 -> 1
2026-01-29 02:08:56.383 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.28.20:5700/3) Recv RXTUNE cmd
2026-01-29 02:08:56.383 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.28.20:5700/3) Recv TXTUNE cmd
2026-01-29 02:08:56.383 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.28.20:5700/3) Recv SETFORMAT cmd
2026-01-29 02:08:56.383 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.28.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:08:56.383 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:08:56.383 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.28.20:5700/3) Recv NOMTXPOWER cmd
2026-01-29 02:08:56.383 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.28.20:5700/3) Recv SETFORMAT cmd
2026-01-29 02:08:56.383 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.28.20:5700/3) TRXD header version 1 -> 1
2026-01-29 02:08:56.386 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.28.20:5700) Recv RXTUNE cmd
2026-01-29 02:08:56.386 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETTSC
2026-01-29 02:08:56.386 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETTSC
2026-01-29 02:08:56.386 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETTSC
2026-01-29 02:08:56.386 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.28.20:5700) Recv TXTUNE cmd
2026-01-29 02:08:56.386 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETRXGAIN
2026-01-29 02:08:56.386 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETRXGAIN
2026-01-29 02:08:56.386 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETRXGAIN
2026-01-29 02:08:56.386 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETTSC
2026-01-29 02:08:56.386 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:08:56.386 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:08:56.386 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.28.20:5700) Recv NOMTXPOWER cmd
2026-01-29 02:08:56.386 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:08:56.386 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:08:56.386 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:08:56.386 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.28.20:5700) Recv POWERON CMD
2026-01-29 02:08:56.386 [INFO] ctrl_if_trx.py:109 (BTS@172.18.28.20:5700) Starting transceiver...
2026-01-29 02:08:56.386 [INFO] transceiver.py:243 Starting clock generator
2026-01-29 02:08:56.386 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-01-29 02:08:56.386 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:08:56.386 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:08:56.386 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:08:56.386 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETRXGAIN
2026-01-29 02:08:56.387 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:08:56.387 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:08:56.387 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:08:56.387 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:08:56.387 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:08:56.387 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:08:56.387 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:08:56.387 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:08:56.387 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:08:56.387 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:08:56.387 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:08:56.387 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:08:56.387 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:08:56.387 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:08:56.387 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:08:56.387 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:08:56.387 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:08:56.387 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:08:56.387 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:08:56.387 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:08:56.387 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:08:56.387 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:08:56.387 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:08:56.387 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:08:56.391 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-01-29 02:08:56.874 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-01-29 02:08:56.914 [DEBUG] fake_trx.py:278 (BTS@172.18.28.20:5700) Recv FAKE_TOA cmd
2026-01-29 02:08:56.916 [DEBUG] fake_trx.py:297 (BTS@172.18.28.20:5700) Recv FAKE_RSSI cmd
2026-01-29 02:08:56.917 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:08:56.918 [DEBUG] fake_trx.py:322 (BTS@172.18.28.20:5700) Recv FAKE_CI cmd
2026-01-29 02:08:56.935 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 02:08:56.935 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 02:08:56.936 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 02:08:56.941 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:08:56.942 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 02:08:56.942 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 02:08:56.943 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.28.22:6700) Recv POWERON CMD
2026-01-29 02:08:56.943 [INFO] ctrl_if_trx.py:109 (MS@172.18.28.22:6700) Starting transceiver...
2026-01-29 02:08:56.969 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:08:56.971 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 02:08:56.971 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 02:08:56.971 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:08:56.971 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:08:57.289 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:08:57.292 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:08:57.294 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 02:08:57.294 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 02:08:57.313 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 02:08:57.313 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 02:08:57.313 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 02:08:57.315 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:08:57.315 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 02:08:57.315 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 02:08:57.315 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.28.22:6700) Recv POWERON CMD
2026-01-29 02:08:57.315 [INFO] ctrl_if_trx.py:109 (MS@172.18.28.22:6700) Starting transceiver...
2026-01-29 02:08:57.348 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:08:57.351 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-01-29 02:08:57.354 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 02:08:57.354 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 02:08:57.355 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:08:57.355 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:08:57.389 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 02:08:57.389 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:08:57.391 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:08:57.393 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:08:57.829 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-01-29 02:08:57.842 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:08:57.845 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:08:57.847 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 02:08:57.847 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 02:08:57.866 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 02:08:57.866 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 02:08:57.866 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 02:08:57.868 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:08:57.868 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 02:08:57.868 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 02:08:57.868 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.28.22:6700) Recv POWERON CMD
2026-01-29 02:08:57.868 [INFO] ctrl_if_trx.py:109 (MS@172.18.28.22:6700) Starting transceiver...
2026-01-29 02:08:57.872 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:08:57.873 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 02:08:57.873 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 02:08:57.873 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:08:57.873 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:08:58.306 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-01-29 02:08:58.390 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 02:08:58.390 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:08:58.392 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:08:58.394 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:08:58.784 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-01-29 02:08:58.940 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:08:58.942 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:08:58.944 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 02:08:58.944 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 02:08:58.963 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 02:08:58.963 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 02:08:58.963 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 02:08:58.965 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:08:58.965 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 02:08:58.965 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 02:08:58.965 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.28.22:6700) Recv POWERON CMD
2026-01-29 02:08:58.965 [INFO] ctrl_if_trx.py:109 (MS@172.18.28.22:6700) Starting transceiver...
2026-01-29 02:08:59.022 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:08:59.026 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 02:08:59.027 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 02:08:59.028 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:08:59.028 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:08:59.261 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-01-29 02:08:59.390 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 02:08:59.391 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:08:59.393 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:08:59.395 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:08:59.739 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-01-29 02:09:00.057 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:09:00.060 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:09:00.062 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 02:09:00.062 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 02:09:00.073 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 02:09:00.074 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:09:00.074 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:09:00.074 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:09:00.075 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 02:09:00.075 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:09:00.075 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:09:00.075 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:09:00.075 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.28.20:5700) Recv POWEROFF cmd
2026-01-29 02:09:00.075 [INFO] ctrl_if_trx.py:117 (BTS@172.18.28.20:5700) Stopping transceiver...
2026-01-29 02:09:00.075 [INFO] transceiver.py:246 Stopping clock generator
2026-01-29 02:09:00.075 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=788 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:09:00.075 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=788 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:09:00.075 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=788 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:09:00.075 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=788 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:09:00.075 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=788 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:09:00.075 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=788 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:09:00.075 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=788 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:09:00.075 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=788 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:09:05.077 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.28.20:5700) Recv POWEROFF cmd
2026-01-29 02:09:05.077 [INFO] ctrl_if_trx.py:117 (BTS@172.18.28.20:5700) Stopping transceiver...
2026-01-29 02:09:05.081 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:09:05.081 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:09:05.081 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 02:09:05.081 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:09:05.091 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 02:09:05.093 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.28.20:5700) Recv SETFORMAT cmd
2026-01-29 02:09:05.093 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.28.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:09:05.094 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.28.20:5700) Recv SETFORMAT cmd
2026-01-29 02:09:05.094 [INFO] ctrl_if_trx.py:201 (BTS@172.18.28.20:5700) TRXD header version 1 -> 1
2026-01-29 02:09:05.099 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.28.20:5700/1) Recv RXTUNE cmd
2026-01-29 02:09:05.099 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.28.20:5700/1) Recv TXTUNE cmd
2026-01-29 02:09:05.099 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.28.20:5700/1) Recv SETFORMAT cmd
2026-01-29 02:09:05.100 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.28.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:09:05.100 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:09:05.100 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.28.20:5700/1) Recv NOMTXPOWER cmd
2026-01-29 02:09:05.101 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.28.20:5700/1) Recv SETFORMAT cmd
2026-01-29 02:09:05.101 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.28.20:5700/1) TRXD header version 1 -> 1
2026-01-29 02:09:05.102 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.28.20:5700/2) Recv RXTUNE cmd
2026-01-29 02:09:05.102 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.28.20:5700/2) Recv TXTUNE cmd
2026-01-29 02:09:05.102 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.28.20:5700/2) Recv SETFORMAT cmd
2026-01-29 02:09:05.102 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.28.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:09:05.102 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:09:05.103 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.28.20:5700/2) Recv NOMTXPOWER cmd
2026-01-29 02:09:05.103 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.28.20:5700/2) Recv SETFORMAT cmd
2026-01-29 02:09:05.103 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.28.20:5700/2) TRXD header version 1 -> 1
2026-01-29 02:09:05.104 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.28.20:5700/3) Recv RXTUNE cmd
2026-01-29 02:09:05.105 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.28.20:5700/3) Recv TXTUNE cmd
2026-01-29 02:09:05.105 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.28.20:5700/3) Recv SETFORMAT cmd
2026-01-29 02:09:05.105 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.28.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:09:05.105 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:09:05.105 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.28.20:5700/3) Recv NOMTXPOWER cmd
2026-01-29 02:09:05.105 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.28.20:5700/3) Recv SETFORMAT cmd
2026-01-29 02:09:05.105 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.28.20:5700/3) TRXD header version 1 -> 1
2026-01-29 02:09:05.107 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.28.20:5700) Recv RXTUNE cmd
2026-01-29 02:09:05.107 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETTSC
2026-01-29 02:09:05.107 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETTSC
2026-01-29 02:09:05.107 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETTSC
2026-01-29 02:09:05.108 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.28.20:5700) Recv TXTUNE cmd
2026-01-29 02:09:05.108 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETRXGAIN
2026-01-29 02:09:05.108 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETRXGAIN
2026-01-29 02:09:05.108 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETRXGAIN
2026-01-29 02:09:05.108 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETTSC
2026-01-29 02:09:05.108 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:09:05.108 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:09:05.108 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:09:05.108 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.28.20:5700) Recv NOMTXPOWER cmd
2026-01-29 02:09:05.108 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:09:05.108 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:09:05.108 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:09:05.108 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.28.20:5700) Recv POWERON CMD
2026-01-29 02:09:05.108 [INFO] ctrl_if_trx.py:109 (BTS@172.18.28.20:5700) Starting transceiver...
2026-01-29 02:09:05.108 [INFO] transceiver.py:243 Starting clock generator
2026-01-29 02:09:05.108 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-01-29 02:09:05.108 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:09:05.109 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:09:05.109 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:09:05.109 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETRXGAIN
2026-01-29 02:09:05.109 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:09:05.109 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:09:05.109 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:09:05.109 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:09:05.109 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:09:05.109 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:09:05.109 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:09:05.109 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:09:05.109 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:09:05.109 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:09:05.109 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:09:05.109 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:09:05.109 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:09:05.109 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:09:05.109 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:09:05.109 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:09:05.109 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:09:05.109 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:09:05.109 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:09:05.109 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:09:05.109 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:09:05.109 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:09:05.110 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:09:05.113 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-01-29 02:09:05.597 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-01-29 02:09:05.638 [DEBUG] fake_trx.py:278 (BTS@172.18.28.20:5700) Recv FAKE_TOA cmd
2026-01-29 02:09:05.640 [DEBUG] fake_trx.py:297 (BTS@172.18.28.20:5700) Recv FAKE_RSSI cmd
2026-01-29 02:09:05.643 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:09:05.643 [DEBUG] fake_trx.py:322 (BTS@172.18.28.20:5700) Recv FAKE_CI cmd
2026-01-29 02:09:05.664 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 02:09:05.665 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 02:09:05.665 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 02:09:05.671 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:09:05.671 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 02:09:05.672 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 02:09:05.672 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.28.22:6700) Recv POWERON CMD
2026-01-29 02:09:05.672 [INFO] ctrl_if_trx.py:109 (MS@172.18.28.22:6700) Starting transceiver...
2026-01-29 02:09:05.693 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:09:05.698 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 02:09:05.699 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 02:09:05.699 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:09:05.700 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:09:06.012 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:09:06.015 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:09:06.017 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 02:09:06.017 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 02:09:06.035 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 02:09:06.035 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 02:09:06.036 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 02:09:06.037 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:09:06.038 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 02:09:06.038 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 02:09:06.038 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.28.22:6700) Recv POWERON CMD
2026-01-29 02:09:06.038 [INFO] ctrl_if_trx.py:109 (MS@172.18.28.22:6700) Starting transceiver...
2026-01-29 02:09:06.071 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:09:06.074 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-01-29 02:09:06.075 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 02:09:06.076 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 02:09:06.076 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:09:06.076 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:09:06.111 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 02:09:06.112 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:09:06.112 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:09:06.116 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:09:06.552 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-01-29 02:09:06.565 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:09:06.569 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:09:06.570 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 02:09:06.570 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 02:09:06.590 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 02:09:06.590 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 02:09:06.591 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 02:09:06.593 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:09:06.593 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 02:09:06.593 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 02:09:06.593 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.28.22:6700) Recv POWERON CMD
2026-01-29 02:09:06.593 [INFO] ctrl_if_trx.py:109 (MS@172.18.28.22:6700) Starting transceiver...
2026-01-29 02:09:06.595 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:09:06.596 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 02:09:06.596 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 02:09:06.596 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:09:06.596 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:09:07.029 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-01-29 02:09:07.112 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 02:09:07.113 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:09:07.113 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:09:07.116 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:09:07.507 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-01-29 02:09:07.663 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:09:07.666 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:09:07.668 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 02:09:07.668 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 02:09:07.678 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 02:09:07.678 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 02:09:07.678 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 02:09:07.680 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:09:07.680 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 02:09:07.680 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 02:09:07.680 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.28.22:6700) Recv POWERON CMD
2026-01-29 02:09:07.680 [INFO] ctrl_if_trx.py:109 (MS@172.18.28.22:6700) Starting transceiver...
2026-01-29 02:09:07.689 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:09:07.691 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 02:09:07.692 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 02:09:07.692 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:09:07.692 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:09:07.984 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-01-29 02:09:08.113 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 02:09:08.114 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:09:08.114 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:09:08.117 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:09:08.461 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-01-29 02:09:08.779 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:09:08.782 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:09:08.783 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 02:09:08.783 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 02:09:08.788 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 02:09:08.788 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:09:08.788 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:09:08.789 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:09:08.790 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 02:09:08.790 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:09:08.790 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:09:08.790 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.28.20:5700) Recv POWEROFF cmd
2026-01-29 02:09:08.790 [INFO] ctrl_if_trx.py:117 (BTS@172.18.28.20:5700) Stopping transceiver...
2026-01-29 02:09:08.790 [INFO] transceiver.py:246 Stopping clock generator
2026-01-29 02:09:08.790 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:09:08.790 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=787 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:09:08.790 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=787 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:09:08.790 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=787 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:09:08.790 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=787 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:09:08.790 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=787 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:09:08.790 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=787 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:09:08.790 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=787 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:09:08.790 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=787 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:09:13.793 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.28.20:5700) Recv POWEROFF cmd
2026-01-29 02:09:13.793 [INFO] ctrl_if_trx.py:117 (BTS@172.18.28.20:5700) Stopping transceiver...
2026-01-29 02:09:13.795 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:09:13.797 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:09:13.799 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:09:13.803 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 02:09:13.812 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 02:09:13.812 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.28.20:5700) Recv SETFORMAT cmd
2026-01-29 02:09:13.812 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.28.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:09:13.812 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.28.20:5700) Recv SETFORMAT cmd
2026-01-29 02:09:13.812 [INFO] ctrl_if_trx.py:201 (BTS@172.18.28.20:5700) TRXD header version 1 -> 1
2026-01-29 02:09:13.813 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.28.20:5700/1) Recv RXTUNE cmd
2026-01-29 02:09:13.814 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.28.20:5700/1) Recv TXTUNE cmd
2026-01-29 02:09:13.814 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.28.20:5700/1) Recv SETFORMAT cmd
2026-01-29 02:09:13.814 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.28.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:09:13.814 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:09:13.814 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.28.20:5700/1) Recv NOMTXPOWER cmd
2026-01-29 02:09:13.814 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.28.20:5700/1) Recv SETFORMAT cmd
2026-01-29 02:09:13.814 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.28.20:5700/1) TRXD header version 1 -> 1
2026-01-29 02:09:13.815 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.28.20:5700/2) Recv RXTUNE cmd
2026-01-29 02:09:13.815 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.28.20:5700/2) Recv TXTUNE cmd
2026-01-29 02:09:13.815 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.28.20:5700/2) Recv SETFORMAT cmd
2026-01-29 02:09:13.815 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.28.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:09:13.815 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:09:13.815 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.28.20:5700/2) Recv NOMTXPOWER cmd
2026-01-29 02:09:13.815 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.28.20:5700/2) Recv SETFORMAT cmd
2026-01-29 02:09:13.815 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.28.20:5700/2) TRXD header version 1 -> 1
2026-01-29 02:09:13.816 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.28.20:5700/3) Recv RXTUNE cmd
2026-01-29 02:09:13.816 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.28.20:5700/3) Recv TXTUNE cmd
2026-01-29 02:09:13.816 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.28.20:5700/3) Recv SETFORMAT cmd
2026-01-29 02:09:13.816 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.28.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:09:13.816 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:09:13.816 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.28.20:5700/3) Recv NOMTXPOWER cmd
2026-01-29 02:09:13.816 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.28.20:5700/3) Recv SETFORMAT cmd
2026-01-29 02:09:13.816 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.28.20:5700/3) TRXD header version 1 -> 1
2026-01-29 02:09:13.818 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.28.20:5700) Recv RXTUNE cmd
2026-01-29 02:09:13.818 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETTSC
2026-01-29 02:09:13.818 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETTSC
2026-01-29 02:09:13.818 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETTSC
2026-01-29 02:09:13.818 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.28.20:5700) Recv TXTUNE cmd
2026-01-29 02:09:13.818 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETRXGAIN
2026-01-29 02:09:13.818 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETRXGAIN
2026-01-29 02:09:13.818 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETRXGAIN
2026-01-29 02:09:13.818 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETTSC
2026-01-29 02:09:13.818 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:09:13.818 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:09:13.818 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:09:13.818 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.28.20:5700) Recv NOMTXPOWER cmd
2026-01-29 02:09:13.818 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:09:13.818 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:09:13.818 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:09:13.818 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.28.20:5700) Recv POWERON CMD
2026-01-29 02:09:13.818 [INFO] ctrl_if_trx.py:109 (BTS@172.18.28.20:5700) Starting transceiver...
2026-01-29 02:09:13.818 [INFO] transceiver.py:243 Starting clock generator
2026-01-29 02:09:13.818 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-01-29 02:09:13.818 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:09:13.818 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:09:13.818 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:09:13.819 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETRXGAIN
2026-01-29 02:09:13.819 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:09:13.819 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:09:13.819 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:09:13.819 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:09:13.819 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:09:13.819 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:09:13.819 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:09:13.819 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:09:13.819 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:09:13.819 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:09:13.819 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:09:13.819 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:09:13.819 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:09:13.819 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:09:13.819 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:09:13.819 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:09:13.819 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:09:13.819 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:09:13.819 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:09:13.819 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:09:13.819 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:09:13.819 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:09:13.819 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:09:13.823 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-01-29 02:09:14.307 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-01-29 02:09:14.340 [DEBUG] fake_trx.py:278 (BTS@172.18.28.20:5700) Recv FAKE_TOA cmd
2026-01-29 02:09:14.342 [DEBUG] fake_trx.py:297 (BTS@172.18.28.20:5700) Recv FAKE_RSSI cmd
2026-01-29 02:09:14.344 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:09:14.345 [DEBUG] fake_trx.py:322 (BTS@172.18.28.20:5700) Recv FAKE_CI cmd
2026-01-29 02:09:14.368 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 02:09:14.368 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 02:09:14.369 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 02:09:14.374 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:09:14.374 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 02:09:14.374 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 02:09:14.374 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.28.22:6700) Recv POWERON CMD
2026-01-29 02:09:14.374 [INFO] ctrl_if_trx.py:109 (MS@172.18.28.22:6700) Starting transceiver...
2026-01-29 02:09:14.403 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:09:14.408 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 02:09:14.408 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 02:09:14.409 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:09:14.409 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:09:14.722 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:09:14.724 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:09:14.726 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 02:09:14.726 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 02:09:14.745 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 02:09:14.745 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 02:09:14.745 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 02:09:14.747 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:09:14.747 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 02:09:14.747 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 02:09:14.747 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.28.22:6700) Recv POWERON CMD
2026-01-29 02:09:14.747 [INFO] ctrl_if_trx.py:109 (MS@172.18.28.22:6700) Starting transceiver...
2026-01-29 02:09:14.780 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:09:14.784 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-01-29 02:09:14.785 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 02:09:14.786 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 02:09:14.786 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:09:14.787 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:09:14.821 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:09:14.821 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 02:09:14.822 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:09:14.823 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:09:15.262 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-01-29 02:09:15.276 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:09:15.279 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:09:15.280 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 02:09:15.280 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 02:09:15.300 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 02:09:15.300 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 02:09:15.300 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 02:09:15.302 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:09:15.303 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 02:09:15.303 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 02:09:15.303 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.28.22:6700) Recv POWERON CMD
2026-01-29 02:09:15.303 [INFO] ctrl_if_trx.py:109 (MS@172.18.28.22:6700) Starting transceiver...
2026-01-29 02:09:15.305 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:09:15.306 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 02:09:15.306 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 02:09:15.307 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:09:15.307 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:09:15.740 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-01-29 02:09:15.822 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:09:15.822 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 02:09:15.822 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:09:15.823 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:09:16.218 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-01-29 02:09:16.374 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:09:16.376 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:09:16.378 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 02:09:16.378 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 02:09:16.397 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 02:09:16.397 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 02:09:16.398 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 02:09:16.401 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:09:16.401 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 02:09:16.401 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 02:09:16.401 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.28.22:6700) Recv POWERON CMD
2026-01-29 02:09:16.401 [INFO] ctrl_if_trx.py:109 (MS@172.18.28.22:6700) Starting transceiver...
2026-01-29 02:09:16.457 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:09:16.463 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 02:09:16.463 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 02:09:16.464 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:09:16.464 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:09:16.695 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-01-29 02:09:16.822 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:09:16.823 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 02:09:16.823 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:09:16.824 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:09:17.174 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-01-29 02:09:17.492 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:09:17.495 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:09:17.497 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 02:09:17.497 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 02:09:17.502 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 02:09:17.502 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:09:17.502 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:09:17.502 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:09:17.503 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 02:09:17.503 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:09:17.503 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:09:17.503 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:09:17.503 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.28.20:5700) Recv POWEROFF cmd
2026-01-29 02:09:17.503 [INFO] ctrl_if_trx.py:117 (BTS@172.18.28.20:5700) Stopping transceiver...
2026-01-29 02:09:17.503 [INFO] transceiver.py:246 Stopping clock generator
2026-01-29 02:09:17.503 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=787 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:09:17.503 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=787 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:09:17.503 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=787 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:09:17.503 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=787 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:09:17.503 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=787 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:09:17.503 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=787 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:09:17.503 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=787 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:09:17.503 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=787 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:09:22.506 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.28.20:5700) Recv POWEROFF cmd
2026-01-29 02:09:22.506 [INFO] ctrl_if_trx.py:117 (BTS@172.18.28.20:5700) Stopping transceiver...
2026-01-29 02:09:22.508 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:09:22.509 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:09:22.510 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:09:22.510 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 02:09:22.519 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 02:09:22.520 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.28.20:5700) Recv SETFORMAT cmd
2026-01-29 02:09:22.520 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.28.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:09:22.521 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.28.20:5700) Recv SETFORMAT cmd
2026-01-29 02:09:22.521 [INFO] ctrl_if_trx.py:201 (BTS@172.18.28.20:5700) TRXD header version 1 -> 1
2026-01-29 02:09:22.524 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.28.20:5700/1) Recv RXTUNE cmd
2026-01-29 02:09:22.524 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.28.20:5700/1) Recv TXTUNE cmd
2026-01-29 02:09:22.525 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.28.20:5700/1) Recv SETFORMAT cmd
2026-01-29 02:09:22.525 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.28.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:09:22.525 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:09:22.526 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.28.20:5700/1) Recv NOMTXPOWER cmd
2026-01-29 02:09:22.526 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.28.20:5700/1) Recv SETFORMAT cmd
2026-01-29 02:09:22.526 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.28.20:5700/1) TRXD header version 1 -> 1
2026-01-29 02:09:22.527 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.28.20:5700/2) Recv RXTUNE cmd
2026-01-29 02:09:22.527 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.28.20:5700/2) Recv TXTUNE cmd
2026-01-29 02:09:22.527 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.28.20:5700/2) Recv SETFORMAT cmd
2026-01-29 02:09:22.527 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.28.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:09:22.527 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:09:22.527 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.28.20:5700/2) Recv NOMTXPOWER cmd
2026-01-29 02:09:22.527 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.28.20:5700/2) Recv SETFORMAT cmd
2026-01-29 02:09:22.527 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.28.20:5700/2) TRXD header version 1 -> 1
2026-01-29 02:09:22.529 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.28.20:5700/3) Recv RXTUNE cmd
2026-01-29 02:09:22.529 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.28.20:5700/3) Recv TXTUNE cmd
2026-01-29 02:09:22.529 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.28.20:5700/3) Recv SETFORMAT cmd
2026-01-29 02:09:22.530 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.28.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:09:22.530 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:09:22.530 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.28.20:5700/3) Recv NOMTXPOWER cmd
2026-01-29 02:09:22.530 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.28.20:5700/3) Recv SETFORMAT cmd
2026-01-29 02:09:22.530 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.28.20:5700/3) TRXD header version 1 -> 1
2026-01-29 02:09:22.532 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.28.20:5700) Recv RXTUNE cmd
2026-01-29 02:09:22.532 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETTSC
2026-01-29 02:09:22.532 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETTSC
2026-01-29 02:09:22.532 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETTSC
2026-01-29 02:09:22.532 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.28.20:5700) Recv TXTUNE cmd
2026-01-29 02:09:22.533 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETRXGAIN
2026-01-29 02:09:22.533 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETRXGAIN
2026-01-29 02:09:22.533 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETRXGAIN
2026-01-29 02:09:22.533 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETTSC
2026-01-29 02:09:22.533 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:09:22.533 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:09:22.533 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.28.20:5700) Recv NOMTXPOWER cmd
2026-01-29 02:09:22.533 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:09:22.533 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:09:22.533 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:09:22.533 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.28.20:5700) Recv POWERON CMD
2026-01-29 02:09:22.533 [INFO] ctrl_if_trx.py:109 (BTS@172.18.28.20:5700) Starting transceiver...
2026-01-29 02:09:22.533 [INFO] transceiver.py:243 Starting clock generator
2026-01-29 02:09:22.533 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-01-29 02:09:22.533 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:09:22.533 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:09:22.533 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:09:22.533 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETRXGAIN
2026-01-29 02:09:22.533 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:09:22.533 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:09:22.533 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:09:22.533 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:09:22.534 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:09:22.534 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:09:22.534 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:09:22.534 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:09:22.534 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:09:22.534 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:09:22.534 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:09:22.534 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:09:22.534 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:09:22.534 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:09:22.534 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:09:22.534 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:09:22.534 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:09:22.534 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:09:22.534 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:09:22.534 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:09:22.534 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:09:22.534 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:09:22.534 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:09:22.534 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:09:22.538 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-01-29 02:09:23.022 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-01-29 02:09:23.062 [DEBUG] fake_trx.py:278 (BTS@172.18.28.20:5700) Recv FAKE_TOA cmd
2026-01-29 02:09:23.063 [DEBUG] fake_trx.py:297 (BTS@172.18.28.20:5700) Recv FAKE_RSSI cmd
2026-01-29 02:09:23.064 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:09:23.065 [DEBUG] fake_trx.py:322 (BTS@172.18.28.20:5700) Recv FAKE_CI cmd
2026-01-29 02:09:23.079 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 02:09:23.079 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 02:09:23.079 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 02:09:23.084 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:09:23.084 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 02:09:23.084 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 02:09:23.085 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.28.22:6700) Recv POWERON CMD
2026-01-29 02:09:23.085 [INFO] ctrl_if_trx.py:109 (MS@172.18.28.22:6700) Starting transceiver...
2026-01-29 02:09:23.119 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:09:23.124 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 02:09:23.126 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 02:09:23.126 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:09:23.126 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:09:23.438 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:09:23.440 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:09:23.442 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 02:09:23.442 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 02:09:23.455 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 02:09:23.455 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 02:09:23.455 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 02:09:23.457 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:09:23.457 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 02:09:23.457 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 02:09:23.457 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.28.22:6700) Recv POWERON CMD
2026-01-29 02:09:23.457 [INFO] ctrl_if_trx.py:109 (MS@172.18.28.22:6700) Starting transceiver...
2026-01-29 02:09:23.497 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:09:23.498 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-01-29 02:09:23.501 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 02:09:23.502 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 02:09:23.502 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:09:23.503 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:09:23.536 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 02:09:23.537 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:09:23.540 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:09:23.543 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:09:23.974 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-01-29 02:09:23.984 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:09:23.985 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:09:23.985 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 02:09:23.985 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 02:09:23.991 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 02:09:23.991 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 02:09:23.991 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 02:09:23.993 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:09:23.993 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 02:09:23.993 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 02:09:23.993 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.28.22:6700) Recv POWERON CMD
2026-01-29 02:09:23.993 [INFO] ctrl_if_trx.py:109 (MS@172.18.28.22:6700) Starting transceiver...
2026-01-29 02:09:24.017 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:09:24.018 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 02:09:24.018 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 02:09:24.018 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:09:24.018 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:09:24.449 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-01-29 02:09:24.537 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 02:09:24.538 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:09:24.541 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:09:24.544 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:09:24.927 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-01-29 02:09:25.082 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:09:25.085 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:09:25.087 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 02:09:25.087 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 02:09:25.107 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 02:09:25.107 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 02:09:25.107 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 02:09:25.109 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:09:25.109 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 02:09:25.109 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 02:09:25.109 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.28.22:6700) Recv POWERON CMD
2026-01-29 02:09:25.109 [INFO] ctrl_if_trx.py:109 (MS@172.18.28.22:6700) Starting transceiver...
2026-01-29 02:09:25.164 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:09:25.170 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 02:09:25.170 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 02:09:25.170 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:09:25.171 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:09:25.399 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-01-29 02:09:25.539 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 02:09:25.539 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:09:25.542 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:09:25.546 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:09:25.877 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-01-29 02:09:26.194 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:09:26.197 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:09:26.198 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 02:09:26.198 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 02:09:26.207 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 02:09:26.207 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:09:26.207 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:09:26.207 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:09:26.208 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 02:09:26.208 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:09:26.208 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:09:26.208 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.28.20:5700) Recv POWEROFF cmd
2026-01-29 02:09:26.209 [INFO] ctrl_if_trx.py:117 (BTS@172.18.28.20:5700) Stopping transceiver...
2026-01-29 02:09:26.209 [INFO] transceiver.py:246 Stopping clock generator
2026-01-29 02:09:26.209 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:09:26.209 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=787 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:09:26.209 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=787 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:09:26.209 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=787 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:09:26.209 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=787 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:09:26.209 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=787 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:09:31.214 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.28.20:5700) Recv POWEROFF cmd
2026-01-29 02:09:31.214 [INFO] ctrl_if_trx.py:117 (BTS@172.18.28.20:5700) Stopping transceiver...
2026-01-29 02:09:31.215 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:09:31.215 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:09:31.215 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:09:31.215 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 02:09:31.224 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 02:09:31.226 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.28.20:5700) Recv SETFORMAT cmd
2026-01-29 02:09:31.226 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.28.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:09:31.227 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.28.20:5700) Recv SETFORMAT cmd
2026-01-29 02:09:31.227 [INFO] ctrl_if_trx.py:201 (BTS@172.18.28.20:5700) TRXD header version 1 -> 1
2026-01-29 02:09:31.233 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.28.20:5700/1) Recv RXTUNE cmd
2026-01-29 02:09:31.233 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.28.20:5700/1) Recv TXTUNE cmd
2026-01-29 02:09:31.234 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.28.20:5700/1) Recv SETFORMAT cmd
2026-01-29 02:09:31.234 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.28.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:09:31.234 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:09:31.235 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.28.20:5700/1) Recv NOMTXPOWER cmd
2026-01-29 02:09:31.235 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.28.20:5700/1) Recv SETFORMAT cmd
2026-01-29 02:09:31.235 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.28.20:5700/1) TRXD header version 1 -> 1
2026-01-29 02:09:31.237 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.28.20:5700/2) Recv RXTUNE cmd
2026-01-29 02:09:31.237 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.28.20:5700/2) Recv TXTUNE cmd
2026-01-29 02:09:31.238 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.28.20:5700/2) Recv SETFORMAT cmd
2026-01-29 02:09:31.238 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.28.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:09:31.238 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:09:31.238 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.28.20:5700/2) Recv NOMTXPOWER cmd
2026-01-29 02:09:31.238 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.28.20:5700/2) Recv SETFORMAT cmd
2026-01-29 02:09:31.238 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.28.20:5700/2) TRXD header version 1 -> 1
2026-01-29 02:09:31.240 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.28.20:5700/3) Recv RXTUNE cmd
2026-01-29 02:09:31.240 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.28.20:5700/3) Recv TXTUNE cmd
2026-01-29 02:09:31.241 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.28.20:5700/3) Recv SETFORMAT cmd
2026-01-29 02:09:31.241 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.28.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:09:31.241 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:09:31.241 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.28.20:5700/3) Recv NOMTXPOWER cmd
2026-01-29 02:09:31.241 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.28.20:5700/3) Recv SETFORMAT cmd
2026-01-29 02:09:31.241 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.28.20:5700/3) TRXD header version 1 -> 1
2026-01-29 02:09:31.244 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.28.20:5700) Recv RXTUNE cmd
2026-01-29 02:09:31.244 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETTSC
2026-01-29 02:09:31.244 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETTSC
2026-01-29 02:09:31.244 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETTSC
2026-01-29 02:09:31.244 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.28.20:5700) Recv TXTUNE cmd
2026-01-29 02:09:31.244 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETRXGAIN
2026-01-29 02:09:31.244 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETRXGAIN
2026-01-29 02:09:31.245 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETRXGAIN
2026-01-29 02:09:31.245 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETTSC
2026-01-29 02:09:31.245 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:09:31.245 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:09:31.245 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:09:31.245 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.28.20:5700) Recv NOMTXPOWER cmd
2026-01-29 02:09:31.245 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:09:31.245 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:09:31.245 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:09:31.245 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.28.20:5700) Recv POWERON CMD
2026-01-29 02:09:31.245 [INFO] ctrl_if_trx.py:109 (BTS@172.18.28.20:5700) Starting transceiver...
2026-01-29 02:09:31.245 [INFO] transceiver.py:243 Starting clock generator
2026-01-29 02:09:31.245 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-01-29 02:09:31.245 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:09:31.245 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:09:31.245 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:09:31.245 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETRXGAIN
2026-01-29 02:09:31.245 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:09:31.245 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:09:31.245 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:09:31.246 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:09:31.246 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:09:31.246 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:09:31.246 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:09:31.246 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:09:31.246 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:09:31.246 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:09:31.246 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:09:31.246 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:09:31.246 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:09:31.246 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:09:31.246 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:09:31.246 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:09:31.246 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:09:31.246 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:09:31.246 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:09:31.246 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:09:31.246 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:09:31.246 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:09:31.246 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:09:31.250 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-01-29 02:09:31.732 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-01-29 02:09:31.774 [DEBUG] fake_trx.py:278 (BTS@172.18.28.20:5700) Recv FAKE_TOA cmd
2026-01-29 02:09:31.775 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:09:31.776 [DEBUG] fake_trx.py:297 (BTS@172.18.28.20:5700) Recv FAKE_RSSI cmd
2026-01-29 02:09:31.777 [DEBUG] fake_trx.py:322 (BTS@172.18.28.20:5700) Recv FAKE_CI cmd
2026-01-29 02:09:31.792 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 02:09:31.792 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 02:09:31.793 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 02:09:31.811 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 02:09:31.811 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:09:31.811 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:09:31.811 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:09:31.814 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 02:09:31.815 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:09:31.815 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:09:31.815 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.28.20:5700) Recv POWEROFF cmd
2026-01-29 02:09:31.815 [INFO] ctrl_if_trx.py:117 (BTS@172.18.28.20:5700) Stopping transceiver...
2026-01-29 02:09:31.815 [INFO] transceiver.py:246 Stopping clock generator
2026-01-29 02:09:31.815 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:09:31.815 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=121 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:09:31.815 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=121 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:09:31.815 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=121 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:09:31.815 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=121 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:09:31.815 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=121 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:09:31.815 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=121 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:09:31.815 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=121 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:09:31.815 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=121 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:09:36.815 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.28.20:5700) Recv POWEROFF cmd
2026-01-29 02:09:36.815 [INFO] ctrl_if_trx.py:117 (BTS@172.18.28.20:5700) Stopping transceiver...
2026-01-29 02:09:36.817 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:09:36.819 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:09:36.819 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:09:36.819 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 02:09:36.822 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 02:09:36.822 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.28.20:5700) Recv SETFORMAT cmd
2026-01-29 02:09:36.822 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.28.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:09:36.822 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.28.20:5700) Recv SETFORMAT cmd
2026-01-29 02:09:36.822 [INFO] ctrl_if_trx.py:201 (BTS@172.18.28.20:5700) TRXD header version 1 -> 1
2026-01-29 02:09:36.824 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.28.20:5700/1) Recv RXTUNE cmd
2026-01-29 02:09:36.824 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.28.20:5700/1) Recv TXTUNE cmd
2026-01-29 02:09:36.824 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.28.20:5700/1) Recv SETFORMAT cmd
2026-01-29 02:09:36.824 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.28.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:09:36.824 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:09:36.824 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.28.20:5700/1) Recv NOMTXPOWER cmd
2026-01-29 02:09:36.824 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.28.20:5700/1) Recv SETFORMAT cmd
2026-01-29 02:09:36.824 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.28.20:5700/1) TRXD header version 1 -> 1
2026-01-29 02:09:36.828 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.28.20:5700/2) Recv RXTUNE cmd
2026-01-29 02:09:36.828 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.28.20:5700/2) Recv TXTUNE cmd
2026-01-29 02:09:36.828 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.28.20:5700/2) Recv SETFORMAT cmd
2026-01-29 02:09:36.828 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.28.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:09:36.828 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.28.20:5700/2) Recv NOMTXPOWER cmd
2026-01-29 02:09:36.828 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.28.20:5700/2) Recv SETFORMAT cmd
2026-01-29 02:09:36.828 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.28.20:5700/2) TRXD header version 1 -> 1
2026-01-29 02:09:36.828 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:09:36.831 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.28.20:5700/3) Recv RXTUNE cmd
2026-01-29 02:09:36.831 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.28.20:5700/3) Recv TXTUNE cmd
2026-01-29 02:09:36.831 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.28.20:5700/3) Recv SETFORMAT cmd
2026-01-29 02:09:36.831 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.28.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:09:36.831 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:09:36.831 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.28.20:5700/3) Recv NOMTXPOWER cmd
2026-01-29 02:09:36.831 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.28.20:5700/3) Recv SETFORMAT cmd
2026-01-29 02:09:36.831 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.28.20:5700/3) TRXD header version 1 -> 1
2026-01-29 02:09:36.835 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.28.20:5700) Recv RXTUNE cmd
2026-01-29 02:09:36.835 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETTSC
2026-01-29 02:09:36.835 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETTSC
2026-01-29 02:09:36.835 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETTSC
2026-01-29 02:09:36.835 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.28.20:5700) Recv TXTUNE cmd
2026-01-29 02:09:36.835 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETRXGAIN
2026-01-29 02:09:36.835 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETRXGAIN
2026-01-29 02:09:36.835 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETRXGAIN
2026-01-29 02:09:36.835 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETTSC
2026-01-29 02:09:36.835 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:09:36.835 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:09:36.835 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:09:36.835 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.28.20:5700) Recv NOMTXPOWER cmd
2026-01-29 02:09:36.835 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:09:36.836 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:09:36.836 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:09:36.836 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.28.20:5700) Recv POWERON CMD
2026-01-29 02:09:36.836 [INFO] ctrl_if_trx.py:109 (BTS@172.18.28.20:5700) Starting transceiver...
2026-01-29 02:09:36.836 [INFO] transceiver.py:243 Starting clock generator
2026-01-29 02:09:36.836 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-01-29 02:09:36.836 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:09:36.836 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:09:36.836 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:09:36.836 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETRXGAIN
2026-01-29 02:09:36.836 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:09:36.836 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:09:36.836 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:09:36.836 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:09:36.836 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:09:36.836 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:09:36.836 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:09:36.836 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:09:36.836 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:09:36.836 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:09:36.836 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:09:36.836 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:09:36.836 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:09:36.836 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:09:36.836 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:09:36.836 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:09:36.836 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:09:36.836 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:09:36.836 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:09:36.836 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:09:36.836 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:09:36.837 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:09:36.837 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:09:36.840 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-01-29 02:09:37.322 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-01-29 02:09:37.356 [DEBUG] fake_trx.py:278 (BTS@172.18.28.20:5700) Recv FAKE_TOA cmd
2026-01-29 02:09:37.357 [DEBUG] fake_trx.py:297 (BTS@172.18.28.20:5700) Recv FAKE_RSSI cmd
2026-01-29 02:09:37.358 [DEBUG] fake_trx.py:322 (BTS@172.18.28.20:5700) Recv FAKE_CI cmd
2026-01-29 02:09:37.358 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:09:37.376 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 02:09:37.376 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 02:09:37.377 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 02:09:37.393 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 02:09:37.393 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 02:09:37.393 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 02:09:37.395 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:09:37.398 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 02:09:37.398 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:09:37.398 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:09:37.398 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:09:37.400 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 02:09:37.400 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:09:37.400 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:09:37.400 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:09:37.400 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.28.20:5700) Recv POWEROFF cmd
2026-01-29 02:09:37.400 [INFO] ctrl_if_trx.py:117 (BTS@172.18.28.20:5700) Stopping transceiver...
2026-01-29 02:09:37.400 [INFO] transceiver.py:246 Stopping clock generator
2026-01-29 02:09:42.402 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.28.20:5700) Recv POWEROFF cmd
2026-01-29 02:09:42.402 [INFO] ctrl_if_trx.py:117 (BTS@172.18.28.20:5700) Stopping transceiver...
2026-01-29 02:09:42.404 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:09:42.405 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:09:42.406 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:09:42.406 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 02:09:42.417 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 02:09:42.417 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.28.20:5700) Recv SETFORMAT cmd
2026-01-29 02:09:42.417 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.28.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:09:42.418 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.28.20:5700) Recv SETFORMAT cmd
2026-01-29 02:09:42.418 [INFO] ctrl_if_trx.py:201 (BTS@172.18.28.20:5700) TRXD header version 1 -> 1
2026-01-29 02:09:42.419 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.28.20:5700/1) Recv RXTUNE cmd
2026-01-29 02:09:42.419 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.28.20:5700/1) Recv TXTUNE cmd
2026-01-29 02:09:42.420 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.28.20:5700/1) Recv SETFORMAT cmd
2026-01-29 02:09:42.420 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.28.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:09:42.420 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:09:42.420 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.28.20:5700/1) Recv NOMTXPOWER cmd
2026-01-29 02:09:42.421 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.28.20:5700/1) Recv SETFORMAT cmd
2026-01-29 02:09:42.421 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.28.20:5700/1) TRXD header version 1 -> 1
2026-01-29 02:09:42.421 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.28.20:5700/2) Recv RXTUNE cmd
2026-01-29 02:09:42.421 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.28.20:5700/2) Recv TXTUNE cmd
2026-01-29 02:09:42.422 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.28.20:5700/2) Recv SETFORMAT cmd
2026-01-29 02:09:42.422 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.28.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:09:42.422 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:09:42.422 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.28.20:5700/2) Recv NOMTXPOWER cmd
2026-01-29 02:09:42.422 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.28.20:5700/2) Recv SETFORMAT cmd
2026-01-29 02:09:42.422 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.28.20:5700/2) TRXD header version 1 -> 1
2026-01-29 02:09:42.423 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.28.20:5700/3) Recv RXTUNE cmd
2026-01-29 02:09:42.423 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.28.20:5700/3) Recv TXTUNE cmd
2026-01-29 02:09:42.424 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.28.20:5700/3) Recv SETFORMAT cmd
2026-01-29 02:09:42.424 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.28.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:09:42.424 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:09:42.424 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.28.20:5700/3) Recv NOMTXPOWER cmd
2026-01-29 02:09:42.424 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.28.20:5700/3) Recv SETFORMAT cmd
2026-01-29 02:09:42.424 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.28.20:5700/3) TRXD header version 1 -> 1
2026-01-29 02:09:42.426 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.28.20:5700) Recv RXTUNE cmd
2026-01-29 02:09:42.426 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETTSC
2026-01-29 02:09:42.426 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETTSC
2026-01-29 02:09:42.426 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETTSC
2026-01-29 02:09:42.426 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.28.20:5700) Recv TXTUNE cmd
2026-01-29 02:09:42.426 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETRXGAIN
2026-01-29 02:09:42.426 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETRXGAIN
2026-01-29 02:09:42.426 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETRXGAIN
2026-01-29 02:09:42.426 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETTSC
2026-01-29 02:09:42.426 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:09:42.426 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:09:42.427 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:09:42.427 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.28.20:5700) Recv NOMTXPOWER cmd
2026-01-29 02:09:42.427 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:09:42.427 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:09:42.427 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:09:42.427 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.28.20:5700) Recv POWERON CMD
2026-01-29 02:09:42.427 [INFO] ctrl_if_trx.py:109 (BTS@172.18.28.20:5700) Starting transceiver...
2026-01-29 02:09:42.427 [INFO] transceiver.py:243 Starting clock generator
2026-01-29 02:09:42.427 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-01-29 02:09:42.427 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:09:42.427 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:09:42.427 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:09:42.427 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETRXGAIN
2026-01-29 02:09:42.427 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:09:42.427 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:09:42.427 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:09:42.427 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:09:42.427 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:09:42.427 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:09:42.427 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:09:42.427 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:09:42.427 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:09:42.427 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:09:42.428 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:09:42.428 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:09:42.428 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:09:42.428 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:09:42.428 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:09:42.428 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:09:42.428 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:09:42.428 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:09:42.428 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:09:42.428 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:09:42.428 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:09:42.428 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:09:42.428 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:09:42.432 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-01-29 02:09:42.914 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-01-29 02:09:42.956 [DEBUG] fake_trx.py:278 (BTS@172.18.28.20:5700) Recv FAKE_TOA cmd
2026-01-29 02:09:42.957 [DEBUG] fake_trx.py:297 (BTS@172.18.28.20:5700) Recv FAKE_RSSI cmd
2026-01-29 02:09:42.958 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:09:42.959 [DEBUG] fake_trx.py:322 (BTS@172.18.28.20:5700) Recv FAKE_CI cmd
2026-01-29 02:09:42.973 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 02:09:42.973 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 02:09:42.973 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 02:09:42.989 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 02:09:42.989 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:09:42.989 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:09:42.989 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:09:42.992 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 02:09:42.992 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:09:42.992 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:09:42.992 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:09:42.992 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.28.20:5700) Recv POWEROFF cmd
2026-01-29 02:09:42.992 [INFO] ctrl_if_trx.py:117 (BTS@172.18.28.20:5700) Stopping transceiver...
2026-01-29 02:09:42.993 [INFO] transceiver.py:246 Stopping clock generator
2026-01-29 02:09:42.993 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=120 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:09:42.993 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=120 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:09:42.993 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=120 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:09:42.993 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=120 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:09:42.993 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=120 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:09:42.993 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=120 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:09:42.993 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=120 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:09:42.993 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=120 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:09:47.993 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.28.20:5700) Recv POWEROFF cmd
2026-01-29 02:09:47.993 [INFO] ctrl_if_trx.py:117 (BTS@172.18.28.20:5700) Stopping transceiver...
2026-01-29 02:09:47.994 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:09:47.995 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:09:47.996 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:09:47.996 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 02:09:48.003 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 02:09:48.004 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.28.20:5700) Recv SETFORMAT cmd
2026-01-29 02:09:48.005 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.28.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:09:48.005 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.28.20:5700) Recv SETFORMAT cmd
2026-01-29 02:09:48.005 [INFO] ctrl_if_trx.py:201 (BTS@172.18.28.20:5700) TRXD header version 1 -> 1
2026-01-29 02:09:48.007 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.28.20:5700/1) Recv RXTUNE cmd
2026-01-29 02:09:48.008 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.28.20:5700/1) Recv TXTUNE cmd
2026-01-29 02:09:48.008 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.28.20:5700/1) Recv SETFORMAT cmd
2026-01-29 02:09:48.008 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.28.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:09:48.008 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:09:48.009 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.28.20:5700/1) Recv NOMTXPOWER cmd
2026-01-29 02:09:48.009 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.28.20:5700/1) Recv SETFORMAT cmd
2026-01-29 02:09:48.009 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.28.20:5700/1) TRXD header version 1 -> 1
2026-01-29 02:09:48.010 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.28.20:5700/2) Recv RXTUNE cmd
2026-01-29 02:09:48.010 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.28.20:5700/2) Recv TXTUNE cmd
2026-01-29 02:09:48.010 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.28.20:5700/2) Recv SETFORMAT cmd
2026-01-29 02:09:48.011 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.28.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:09:48.011 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:09:48.011 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.28.20:5700/2) Recv NOMTXPOWER cmd
2026-01-29 02:09:48.011 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.28.20:5700/2) Recv SETFORMAT cmd
2026-01-29 02:09:48.011 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.28.20:5700/2) TRXD header version 1 -> 1
2026-01-29 02:09:48.012 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.28.20:5700/3) Recv RXTUNE cmd
2026-01-29 02:09:48.012 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.28.20:5700/3) Recv TXTUNE cmd
2026-01-29 02:09:48.012 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.28.20:5700/3) Recv SETFORMAT cmd
2026-01-29 02:09:48.013 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.28.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:09:48.013 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:09:48.013 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.28.20:5700/3) Recv NOMTXPOWER cmd
2026-01-29 02:09:48.013 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.28.20:5700/3) Recv SETFORMAT cmd
2026-01-29 02:09:48.013 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.28.20:5700/3) TRXD header version 1 -> 1
2026-01-29 02:09:48.015 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.28.20:5700) Recv RXTUNE cmd
2026-01-29 02:09:48.015 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETTSC
2026-01-29 02:09:48.015 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETTSC
2026-01-29 02:09:48.015 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETTSC
2026-01-29 02:09:48.015 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.28.20:5700) Recv TXTUNE cmd
2026-01-29 02:09:48.015 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETRXGAIN
2026-01-29 02:09:48.015 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETRXGAIN
2026-01-29 02:09:48.015 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETRXGAIN
2026-01-29 02:09:48.016 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETTSC
2026-01-29 02:09:48.016 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:09:48.016 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:09:48.016 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:09:48.016 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.28.20:5700) Recv NOMTXPOWER cmd
2026-01-29 02:09:48.016 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:09:48.016 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:09:48.016 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:09:48.016 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.28.20:5700) Recv POWERON CMD
2026-01-29 02:09:48.016 [INFO] ctrl_if_trx.py:109 (BTS@172.18.28.20:5700) Starting transceiver...
2026-01-29 02:09:48.016 [INFO] transceiver.py:243 Starting clock generator
2026-01-29 02:09:48.016 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-01-29 02:09:48.016 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:09:48.016 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:09:48.016 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:09:48.016 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETRXGAIN
2026-01-29 02:09:48.016 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:09:48.016 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:09:48.016 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:09:48.016 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:09:48.016 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:09:48.016 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:09:48.016 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:09:48.017 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:09:48.017 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:09:48.017 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:09:48.017 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:09:48.017 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:09:48.017 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:09:48.017 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:09:48.017 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:09:48.017 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:09:48.017 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:09:48.017 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:09:48.017 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:09:48.017 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:09:48.017 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:09:48.017 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:09:48.018 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:09:48.018 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:09:48.018 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:09:48.018 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:09:48.018 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 02:09:48.018 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.28.20:5700) Recv POWEROFF cmd
2026-01-29 02:09:48.018 [INFO] ctrl_if_trx.py:117 (BTS@172.18.28.20:5700) Stopping transceiver...
2026-01-29 02:09:48.018 [INFO] transceiver.py:246 Stopping clock generator
2026-01-29 02:09:53.021 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.28.20:5700) Recv POWEROFF cmd
2026-01-29 02:09:53.021 [INFO] ctrl_if_trx.py:117 (BTS@172.18.28.20:5700) Stopping transceiver...
2026-01-29 02:09:53.023 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:09:53.024 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:09:53.024 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:09:53.024 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 02:09:53.034 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 02:09:53.035 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.28.20:5700) Recv SETFORMAT cmd
2026-01-29 02:09:53.036 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.28.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:09:53.036 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.28.20:5700) Recv SETFORMAT cmd
2026-01-29 02:09:53.036 [INFO] ctrl_if_trx.py:201 (BTS@172.18.28.20:5700) TRXD header version 1 -> 1
2026-01-29 02:09:53.041 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.28.20:5700/1) Recv RXTUNE cmd
2026-01-29 02:09:53.041 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.28.20:5700/1) Recv TXTUNE cmd
2026-01-29 02:09:53.042 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.28.20:5700/1) Recv SETFORMAT cmd
2026-01-29 02:09:53.042 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.28.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:09:53.042 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:09:53.042 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.28.20:5700/1) Recv NOMTXPOWER cmd
2026-01-29 02:09:53.043 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.28.20:5700/1) Recv SETFORMAT cmd
2026-01-29 02:09:53.043 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.28.20:5700/1) TRXD header version 1 -> 1
2026-01-29 02:09:53.044 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.28.20:5700/2) Recv RXTUNE cmd
2026-01-29 02:09:53.044 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.28.20:5700/2) Recv TXTUNE cmd
2026-01-29 02:09:53.044 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.28.20:5700/2) Recv SETFORMAT cmd
2026-01-29 02:09:53.044 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.28.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:09:53.044 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:09:53.045 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.28.20:5700/2) Recv NOMTXPOWER cmd
2026-01-29 02:09:53.045 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.28.20:5700/2) Recv SETFORMAT cmd
2026-01-29 02:09:53.045 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.28.20:5700/2) TRXD header version 1 -> 1
2026-01-29 02:09:53.047 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.28.20:5700/3) Recv RXTUNE cmd
2026-01-29 02:09:53.047 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.28.20:5700/3) Recv TXTUNE cmd
2026-01-29 02:09:53.047 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.28.20:5700/3) Recv SETFORMAT cmd
2026-01-29 02:09:53.047 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.28.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:09:53.047 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:09:53.047 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.28.20:5700/3) Recv NOMTXPOWER cmd
2026-01-29 02:09:53.047 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.28.20:5700/3) Recv SETFORMAT cmd
2026-01-29 02:09:53.047 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.28.20:5700/3) TRXD header version 1 -> 1
2026-01-29 02:09:53.049 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.28.20:5700) Recv RXTUNE cmd
2026-01-29 02:09:53.050 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETTSC
2026-01-29 02:09:53.050 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETTSC
2026-01-29 02:09:53.050 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETTSC
2026-01-29 02:09:53.050 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.28.20:5700) Recv TXTUNE cmd
2026-01-29 02:09:53.050 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETRXGAIN
2026-01-29 02:09:53.050 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETRXGAIN
2026-01-29 02:09:53.050 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETRXGAIN
2026-01-29 02:09:53.050 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETTSC
2026-01-29 02:09:53.050 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:09:53.050 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:09:53.050 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:09:53.050 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.28.20:5700) Recv NOMTXPOWER cmd
2026-01-29 02:09:53.050 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:09:53.050 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:09:53.050 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:09:53.050 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.28.20:5700) Recv POWERON CMD
2026-01-29 02:09:53.050 [INFO] ctrl_if_trx.py:109 (BTS@172.18.28.20:5700) Starting transceiver...
2026-01-29 02:09:53.050 [INFO] transceiver.py:243 Starting clock generator
2026-01-29 02:09:53.050 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-01-29 02:09:53.051 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:09:53.051 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:09:53.051 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:09:53.051 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETRXGAIN
2026-01-29 02:09:53.051 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:09:53.051 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:09:53.051 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:09:53.051 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:09:53.051 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:09:53.051 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:09:53.051 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:09:53.051 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:09:53.051 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:09:53.051 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:09:53.051 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:09:53.051 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:09:53.051 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:09:53.051 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:09:53.051 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:09:53.051 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:09:53.051 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:09:53.051 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:09:53.051 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:09:53.051 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:09:53.051 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:09:53.051 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:09:53.051 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:09:53.055 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-01-29 02:09:53.537 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-01-29 02:09:53.572 [DEBUG] fake_trx.py:278 (BTS@172.18.28.20:5700) Recv FAKE_TOA cmd
2026-01-29 02:09:53.574 [DEBUG] fake_trx.py:297 (BTS@172.18.28.20:5700) Recv FAKE_RSSI cmd
2026-01-29 02:09:53.575 [DEBUG] fake_trx.py:322 (BTS@172.18.28.20:5700) Recv FAKE_CI cmd
2026-01-29 02:09:53.576 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:09:53.588 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 02:09:53.588 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 02:09:53.588 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 02:09:53.591 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:09:53.591 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 02:09:53.591 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 02:09:53.591 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.28.22:6700) Recv POWERON CMD
2026-01-29 02:09:53.591 [INFO] ctrl_if_trx.py:109 (MS@172.18.28.22:6700) Starting transceiver...
2026-01-29 02:09:53.634 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:09:53.640 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 02:09:53.640 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 02:09:53.641 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:09:53.641 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:09:54.014 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-01-29 02:09:54.053 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 02:09:54.053 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:09:54.055 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:09:54.057 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:09:54.492 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-01-29 02:09:54.601 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:09:54.605 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:09:54.606 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 02:09:54.606 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 02:09:54.615 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 02:09:54.615 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 02:09:54.615 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 02:09:54.616 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:09:54.616 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 02:09:54.616 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 02:09:54.616 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.28.22:6700) Recv POWERON CMD
2026-01-29 02:09:54.616 [INFO] ctrl_if_trx.py:109 (MS@172.18.28.22:6700) Starting transceiver...
2026-01-29 02:09:54.628 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:09:54.629 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 02:09:54.630 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 02:09:54.630 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:09:54.630 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:09:54.967 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-01-29 02:09:55.054 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 02:09:55.054 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:09:55.056 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:09:55.058 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:09:55.445 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-01-29 02:09:55.573 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:09:55.575 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:09:55.576 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 02:09:55.576 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 02:09:55.589 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 02:09:55.589 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 02:09:55.589 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 02:09:55.590 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:09:55.590 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 02:09:55.590 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 02:09:55.590 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.28.22:6700) Recv POWERON CMD
2026-01-29 02:09:55.590 [INFO] ctrl_if_trx.py:109 (MS@172.18.28.22:6700) Starting transceiver...
2026-01-29 02:09:55.632 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:09:55.638 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 02:09:55.638 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 02:09:55.638 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:09:55.638 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:09:55.922 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-01-29 02:09:56.055 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 02:09:56.055 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:09:56.056 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:09:56.059 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:09:56.400 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-01-29 02:09:56.556 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:09:56.558 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:09:56.559 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 02:09:56.559 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 02:09:56.568 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 02:09:56.568 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 02:09:56.568 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 02:09:56.569 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:09:56.569 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 02:09:56.569 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 02:09:56.569 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.28.22:6700) Recv POWERON CMD
2026-01-29 02:09:56.569 [INFO] ctrl_if_trx.py:109 (MS@172.18.28.22:6700) Starting transceiver...
2026-01-29 02:09:56.583 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:09:56.585 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 02:09:56.586 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 02:09:56.586 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:09:56.586 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:09:56.877 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-01-29 02:09:57.056 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 02:09:57.057 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:09:57.058 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:09:57.060 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:09:57.354 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-01-29 02:09:57.528 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:09:57.532 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:09:57.533 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 02:09:57.533 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 02:09:57.552 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 02:09:57.552 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 02:09:57.552 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 02:09:57.554 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:09:57.554 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 02:09:57.554 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 02:09:57.554 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.28.22:6700) Recv POWERON CMD
2026-01-29 02:09:57.554 [INFO] ctrl_if_trx.py:109 (MS@172.18.28.22:6700) Starting transceiver...
2026-01-29 02:09:57.592 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:09:57.597 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 02:09:57.597 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 02:09:57.598 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:09:57.598 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:09:57.832 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-01-29 02:09:58.057 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 02:09:58.057 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:09:58.059 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:09:58.061 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:09:58.149 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:09:58.151 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:09:58.152 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 02:09:58.152 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 02:09:58.172 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 02:09:58.172 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 02:09:58.172 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 02:09:58.173 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:09:58.173 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 02:09:58.174 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 02:09:58.174 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.28.22:6700) Recv POWERON CMD
2026-01-29 02:09:58.174 [INFO] ctrl_if_trx.py:109 (MS@172.18.28.22:6700) Starting transceiver...
2026-01-29 02:09:58.208 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:09:58.214 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 02:09:58.214 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 02:09:58.214 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:09:58.214 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:09:58.309 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-01-29 02:09:58.755 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:09:58.758 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:09:58.759 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 02:09:58.759 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 02:09:58.771 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 02:09:58.771 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 02:09:58.771 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 02:09:58.773 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:09:58.773 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 02:09:58.773 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 02:09:58.773 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.28.22:6700) Recv POWERON CMD
2026-01-29 02:09:58.773 [INFO] ctrl_if_trx.py:109 (MS@172.18.28.22:6700) Starting transceiver...
2026-01-29 02:09:58.777 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:09:58.778 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 02:09:58.778 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 02:09:58.778 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:09:58.778 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:09:58.786 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-01-29 02:09:59.263 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-01-29 02:09:59.332 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:09:59.335 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:09:59.335 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 02:09:59.336 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 02:09:59.355 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 02:09:59.355 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 02:09:59.355 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 02:09:59.358 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:09:59.358 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 02:09:59.358 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 02:09:59.358 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.28.22:6700) Recv POWERON CMD
2026-01-29 02:09:59.358 [INFO] ctrl_if_trx.py:109 (MS@172.18.28.22:6700) Starting transceiver...
2026-01-29 02:09:59.405 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:09:59.406 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:09:59.411 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 02:09:59.411 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 02:09:59.411 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:09:59.412 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:09:59.741 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-01-29 02:10:00.013 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:10:00.016 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:10:00.017 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 02:10:00.017 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 02:10:00.036 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 02:10:00.036 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 02:10:00.037 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 02:10:00.038 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:10:00.038 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 02:10:00.038 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 02:10:00.038 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.28.22:6700) Recv POWERON CMD
2026-01-29 02:10:00.038 [INFO] ctrl_if_trx.py:109 (MS@172.18.28.22:6700) Starting transceiver...
2026-01-29 02:10:00.071 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:10:00.076 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 02:10:00.077 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 02:10:00.077 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:10:00.078 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:10:00.218 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-01-29 02:10:00.681 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:10:00.684 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:10:00.685 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 02:10:00.685 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 02:10:00.696 [DEBUG] clck_gen.py:113 IND CLOCK 1632
2026-01-29 02:10:00.704 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 02:10:00.704 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 02:10:00.704 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 02:10:00.706 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:10:00.706 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 02:10:00.706 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 02:10:00.706 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.28.22:6700) Recv POWERON CMD
2026-01-29 02:10:00.706 [INFO] ctrl_if_trx.py:109 (MS@172.18.28.22:6700) Starting transceiver...
2026-01-29 02:10:00.745 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:10:00.746 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:10:00.751 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 02:10:00.751 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 02:10:00.752 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:10:00.753 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:10:01.174 [DEBUG] clck_gen.py:113 IND CLOCK 1734
2026-01-29 02:10:01.298 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:10:01.301 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:10:01.302 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 02:10:01.302 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 02:10:01.320 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 02:10:01.320 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 02:10:01.320 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 02:10:01.321 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:10:01.321 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 02:10:01.321 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 02:10:01.321 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.28.22:6700) Recv POWERON CMD
2026-01-29 02:10:01.321 [INFO] ctrl_if_trx.py:109 (MS@172.18.28.22:6700) Starting transceiver...
2026-01-29 02:10:01.361 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:10:01.366 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 02:10:01.366 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 02:10:01.366 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:10:01.367 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:10:01.651 [DEBUG] clck_gen.py:113 IND CLOCK 1836
2026-01-29 02:10:01.959 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:10:01.962 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:10:01.963 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 02:10:01.963 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 02:10:01.980 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 02:10:01.980 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 02:10:01.981 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 02:10:01.982 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:10:01.982 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 02:10:01.982 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 02:10:01.982 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.28.22:6700) Recv POWERON CMD
2026-01-29 02:10:01.982 [INFO] ctrl_if_trx.py:109 (MS@172.18.28.22:6700) Starting transceiver...
2026-01-29 02:10:02.027 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:10:02.032 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 02:10:02.032 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 02:10:02.032 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:10:02.033 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:10:02.128 [DEBUG] clck_gen.py:113 IND CLOCK 1938
2026-01-29 02:10:02.606 [DEBUG] clck_gen.py:113 IND CLOCK 2040
2026-01-29 02:10:02.657 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:10:02.659 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:10:02.660 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 02:10:02.660 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 02:10:02.678 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 02:10:02.678 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 02:10:02.679 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 02:10:02.680 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:10:02.680 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 02:10:02.680 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 02:10:02.680 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.28.22:6700) Recv POWERON CMD
2026-01-29 02:10:02.680 [INFO] ctrl_if_trx.py:109 (MS@172.18.28.22:6700) Starting transceiver...
2026-01-29 02:10:02.698 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:10:02.702 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 02:10:02.703 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 02:10:02.703 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:10:02.703 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:10:03.083 [DEBUG] clck_gen.py:113 IND CLOCK 2142
2026-01-29 02:10:03.561 [DEBUG] clck_gen.py:113 IND CLOCK 2244
2026-01-29 02:10:03.563 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:10:03.565 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:10:03.566 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 02:10:03.566 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 02:10:03.578 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 02:10:03.578 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 02:10:03.578 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 02:10:03.579 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:10:03.579 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 02:10:03.579 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 02:10:03.579 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.28.22:6700) Recv POWERON CMD
2026-01-29 02:10:03.579 [INFO] ctrl_if_trx.py:109 (MS@172.18.28.22:6700) Starting transceiver...
2026-01-29 02:10:03.608 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:10:03.613 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 02:10:03.613 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 02:10:03.614 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:10:03.614 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:10:04.038 [DEBUG] clck_gen.py:113 IND CLOCK 2346
2026-01-29 02:10:04.516 [DEBUG] clck_gen.py:113 IND CLOCK 2448
2026-01-29 02:10:04.543 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:10:04.546 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:10:04.546 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 02:10:04.546 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 02:10:04.566 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 02:10:04.566 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 02:10:04.566 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 02:10:04.567 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:10:04.567 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 02:10:04.567 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 02:10:04.567 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.28.22:6700) Recv POWERON CMD
2026-01-29 02:10:04.567 [INFO] ctrl_if_trx.py:109 (MS@172.18.28.22:6700) Starting transceiver...
2026-01-29 02:10:04.611 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:10:04.616 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 02:10:04.616 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 02:10:04.616 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:10:04.616 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:10:04.993 [DEBUG] clck_gen.py:113 IND CLOCK 2550
2026-01-29 02:10:05.471 [DEBUG] clck_gen.py:113 IND CLOCK 2652
2026-01-29 02:10:05.517 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:10:05.519 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:10:05.520 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 02:10:05.520 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 02:10:05.530 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 02:10:05.530 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 02:10:05.530 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 02:10:05.531 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:10:05.531 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 02:10:05.531 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 02:10:05.531 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.28.22:6700) Recv POWERON CMD
2026-01-29 02:10:05.531 [INFO] ctrl_if_trx.py:109 (MS@172.18.28.22:6700) Starting transceiver...
2026-01-29 02:10:05.565 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:10:05.570 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 02:10:05.570 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 02:10:05.571 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:10:05.571 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:10:05.948 [DEBUG] clck_gen.py:113 IND CLOCK 2754
2026-01-29 02:10:06.426 [DEBUG] clck_gen.py:113 IND CLOCK 2856
2026-01-29 02:10:06.490 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:10:06.493 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:10:06.494 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 02:10:06.495 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 02:10:06.513 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 02:10:06.513 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 02:10:06.513 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 02:10:06.515 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:10:06.515 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 02:10:06.515 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 02:10:06.515 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.28.22:6700) Recv POWERON CMD
2026-01-29 02:10:06.515 [INFO] ctrl_if_trx.py:109 (MS@172.18.28.22:6700) Starting transceiver...
2026-01-29 02:10:06.567 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:10:06.571 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 02:10:06.572 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 02:10:06.572 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:10:06.572 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:10:06.903 [DEBUG] clck_gen.py:113 IND CLOCK 2958
2026-01-29 02:10:07.381 [DEBUG] clck_gen.py:113 IND CLOCK 3060
2026-01-29 02:10:07.464 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:10:07.467 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:10:07.467 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 02:10:07.468 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 02:10:07.488 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 02:10:07.489 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 02:10:07.489 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 02:10:07.490 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:10:07.490 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 02:10:07.490 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 02:10:07.490 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.28.22:6700) Recv POWERON CMD
2026-01-29 02:10:07.490 [INFO] ctrl_if_trx.py:109 (MS@172.18.28.22:6700) Starting transceiver...
2026-01-29 02:10:07.522 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:10:07.527 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 02:10:07.527 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 02:10:07.528 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:10:07.528 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:10:07.859 [DEBUG] clck_gen.py:113 IND CLOCK 3162
2026-01-29 02:10:08.337 [DEBUG] clck_gen.py:113 IND CLOCK 3264
2026-01-29 02:10:08.438 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:10:08.442 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:10:08.442 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 02:10:08.443 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 02:10:08.455 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 02:10:08.455 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 02:10:08.456 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 02:10:08.457 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:10:08.457 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 02:10:08.457 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 02:10:08.457 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.28.22:6700) Recv POWERON CMD
2026-01-29 02:10:08.457 [INFO] ctrl_if_trx.py:109 (MS@172.18.28.22:6700) Starting transceiver...
2026-01-29 02:10:08.475 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:10:08.478 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 02:10:08.478 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 02:10:08.479 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:10:08.479 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:10:08.814 [DEBUG] clck_gen.py:113 IND CLOCK 3366
2026-01-29 02:10:09.292 [DEBUG] clck_gen.py:113 IND CLOCK 3468
2026-01-29 02:10:09.411 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:10:09.414 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:10:09.414 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 02:10:09.415 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 02:10:09.434 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 02:10:09.434 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 02:10:09.434 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 02:10:09.436 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:10:09.436 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 02:10:09.436 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 02:10:09.436 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.28.22:6700) Recv POWERON CMD
2026-01-29 02:10:09.436 [INFO] ctrl_if_trx.py:109 (MS@172.18.28.22:6700) Starting transceiver...
2026-01-29 02:10:09.479 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:10:09.484 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 02:10:09.485 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 02:10:09.485 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:10:09.486 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:10:09.769 [DEBUG] clck_gen.py:113 IND CLOCK 3570
2026-01-29 02:10:10.247 [DEBUG] clck_gen.py:113 IND CLOCK 3672
2026-01-29 02:10:10.385 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:10:10.388 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:10:10.388 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 02:10:10.389 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 02:10:10.394 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 02:10:10.394 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:10:10.394 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:10:10.394 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:10:10.395 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 02:10:10.395 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:10:10.395 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:10:10.395 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:10:10.395 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.28.20:5700) Recv POWEROFF cmd
2026-01-29 02:10:10.395 [INFO] ctrl_if_trx.py:117 (BTS@172.18.28.20:5700) Stopping transceiver...
2026-01-29 02:10:10.395 [INFO] transceiver.py:246 Stopping clock generator
2026-01-29 02:10:10.395 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=3706 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:10:10.395 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=3706 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:10:10.395 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=3706 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:10:10.395 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=3706 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:10:10.395 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=3706 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:10:10.395 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=3706 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:10:15.397 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.28.20:5700) Recv POWEROFF cmd
2026-01-29 02:10:15.398 [INFO] ctrl_if_trx.py:117 (BTS@172.18.28.20:5700) Stopping transceiver...
2026-01-29 02:10:15.399 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:10:15.400 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:10:15.400 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:10:15.401 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 02:10:15.410 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 02:10:15.411 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.28.20:5700) Recv SETFORMAT cmd
2026-01-29 02:10:15.411 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.28.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:10:15.411 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.28.20:5700) Recv SETFORMAT cmd
2026-01-29 02:10:15.411 [INFO] ctrl_if_trx.py:201 (BTS@172.18.28.20:5700) TRXD header version 1 -> 1
2026-01-29 02:10:15.413 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.28.20:5700/1) Recv RXTUNE cmd
2026-01-29 02:10:15.413 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.28.20:5700/1) Recv TXTUNE cmd
2026-01-29 02:10:15.414 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.28.20:5700/1) Recv SETFORMAT cmd
2026-01-29 02:10:15.414 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.28.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:10:15.414 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.28.20:5700/1) Recv NOMTXPOWER cmd
2026-01-29 02:10:15.414 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:10:15.414 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.28.20:5700/1) Recv SETFORMAT cmd
2026-01-29 02:10:15.414 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.28.20:5700/1) TRXD header version 1 -> 1
2026-01-29 02:10:15.416 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.28.20:5700/2) Recv RXTUNE cmd
2026-01-29 02:10:15.416 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.28.20:5700/2) Recv TXTUNE cmd
2026-01-29 02:10:15.416 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.28.20:5700/2) Recv SETFORMAT cmd
2026-01-29 02:10:15.416 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.28.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:10:15.416 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.28.20:5700/2) Recv NOMTXPOWER cmd
2026-01-29 02:10:15.416 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:10:15.416 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.28.20:5700/2) Recv SETFORMAT cmd
2026-01-29 02:10:15.416 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.28.20:5700/2) TRXD header version 1 -> 1
2026-01-29 02:10:15.418 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.28.20:5700/3) Recv RXTUNE cmd
2026-01-29 02:10:15.418 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.28.20:5700/3) Recv TXTUNE cmd
2026-01-29 02:10:15.418 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.28.20:5700/3) Recv SETFORMAT cmd
2026-01-29 02:10:15.418 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.28.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:10:15.418 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.28.20:5700/3) Recv NOMTXPOWER cmd
2026-01-29 02:10:15.418 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:10:15.418 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.28.20:5700/3) Recv SETFORMAT cmd
2026-01-29 02:10:15.418 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.28.20:5700/3) TRXD header version 1 -> 1
2026-01-29 02:10:15.420 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.28.20:5700) Recv RXTUNE cmd
2026-01-29 02:10:15.420 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETTSC
2026-01-29 02:10:15.420 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETTSC
2026-01-29 02:10:15.420 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETTSC
2026-01-29 02:10:15.420 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.28.20:5700) Recv TXTUNE cmd
2026-01-29 02:10:15.421 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETRXGAIN
2026-01-29 02:10:15.421 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETRXGAIN
2026-01-29 02:10:15.421 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETRXGAIN
2026-01-29 02:10:15.421 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETTSC
2026-01-29 02:10:15.421 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:10:15.421 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:10:15.421 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:10:15.421 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.28.20:5700) Recv NOMTXPOWER cmd
2026-01-29 02:10:15.421 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:10:15.421 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:10:15.421 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:10:15.421 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.28.20:5700) Recv POWERON CMD
2026-01-29 02:10:15.421 [INFO] ctrl_if_trx.py:109 (BTS@172.18.28.20:5700) Starting transceiver...
2026-01-29 02:10:15.421 [INFO] transceiver.py:243 Starting clock generator
2026-01-29 02:10:15.421 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-01-29 02:10:15.421 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:10:15.421 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:10:15.421 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:10:15.421 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETRXGAIN
2026-01-29 02:10:15.421 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:10:15.421 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:10:15.421 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:10:15.421 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:10:15.421 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:10:15.421 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:10:15.421 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:10:15.421 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:10:15.421 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:10:15.421 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:10:15.421 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:10:15.421 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:10:15.421 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:10:15.421 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:10:15.421 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:10:15.421 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:10:15.421 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:10:15.421 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:10:15.421 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:10:15.421 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:10:15.421 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:10:15.421 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:10:15.422 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:10:15.425 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-01-29 02:10:15.909 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-01-29 02:10:15.942 [DEBUG] fake_trx.py:278 (BTS@172.18.28.20:5700) Recv FAKE_TOA cmd
2026-01-29 02:10:15.943 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:10:15.944 [DEBUG] fake_trx.py:297 (BTS@172.18.28.20:5700) Recv FAKE_RSSI cmd
2026-01-29 02:10:15.946 [DEBUG] fake_trx.py:322 (BTS@172.18.28.20:5700) Recv FAKE_CI cmd
2026-01-29 02:10:15.964 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 02:10:15.964 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 02:10:15.964 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 02:10:15.969 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:10:15.969 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 02:10:15.970 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 02:10:15.970 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.28.22:6700) Recv POWERON CMD
2026-01-29 02:10:15.970 [INFO] ctrl_if_trx.py:109 (MS@172.18.28.22:6700) Starting transceiver...
2026-01-29 02:10:16.004 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:10:16.006 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 02:10:16.006 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 02:10:16.006 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:10:16.006 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:10:16.255 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:10:16.258 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:10:16.259 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 02:10:16.259 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 02:10:16.280 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 02:10:16.280 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 02:10:16.281 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 02:10:16.282 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:10:16.282 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 02:10:16.282 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 02:10:16.283 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.28.22:6700) Recv POWERON CMD
2026-01-29 02:10:16.283 [INFO] ctrl_if_trx.py:109 (MS@172.18.28.22:6700) Starting transceiver...
2026-01-29 02:10:16.331 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:10:16.336 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 02:10:16.336 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 02:10:16.336 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:10:16.337 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:10:16.384 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-01-29 02:10:16.423 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 02:10:16.423 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:10:16.425 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:10:16.426 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:10:16.509 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:10:16.512 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:10:16.512 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 02:10:16.512 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 02:10:16.531 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 02:10:16.531 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 02:10:16.531 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 02:10:16.533 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:10:16.533 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 02:10:16.533 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 02:10:16.533 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.28.22:6700) Recv POWERON CMD
2026-01-29 02:10:16.533 [INFO] ctrl_if_trx.py:109 (MS@172.18.28.22:6700) Starting transceiver...
2026-01-29 02:10:16.567 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:10:16.572 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 02:10:16.572 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 02:10:16.572 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:10:16.573 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:10:16.772 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:10:16.774 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:10:16.775 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 02:10:16.775 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 02:10:16.795 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 02:10:16.795 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 02:10:16.795 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 02:10:16.797 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:10:16.797 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 02:10:16.797 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 02:10:16.797 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.28.22:6700) Recv POWERON CMD
2026-01-29 02:10:16.797 [INFO] ctrl_if_trx.py:109 (MS@172.18.28.22:6700) Starting transceiver...
2026-01-29 02:10:16.853 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:10:16.858 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 02:10:16.858 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 02:10:16.859 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:10:16.859 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:10:16.861 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-01-29 02:10:17.035 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:10:17.038 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:10:17.039 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 02:10:17.039 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 02:10:17.047 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 02:10:17.047 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:10:17.047 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:10:17.047 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:10:17.048 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 02:10:17.048 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:10:17.048 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:10:17.048 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.28.20:5700) Recv POWEROFF cmd
2026-01-29 02:10:17.048 [INFO] ctrl_if_trx.py:117 (BTS@172.18.28.20:5700) Stopping transceiver...
2026-01-29 02:10:17.048 [INFO] transceiver.py:246 Stopping clock generator
2026-01-29 02:10:17.048 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:10:22.050 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.28.20:5700) Recv POWEROFF cmd
2026-01-29 02:10:22.050 [INFO] ctrl_if_trx.py:117 (BTS@172.18.28.20:5700) Stopping transceiver...
2026-01-29 02:10:22.052 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:10:22.053 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:10:22.054 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:10:22.055 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 02:10:22.063 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 02:10:22.064 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.28.20:5700) Recv SETFORMAT cmd
2026-01-29 02:10:22.064 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.28.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:10:22.065 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.28.20:5700) Recv SETFORMAT cmd
2026-01-29 02:10:22.065 [INFO] ctrl_if_trx.py:201 (BTS@172.18.28.20:5700) TRXD header version 1 -> 1
2026-01-29 02:10:22.067 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.28.20:5700/1) Recv RXTUNE cmd
2026-01-29 02:10:22.068 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.28.20:5700/1) Recv TXTUNE cmd
2026-01-29 02:10:22.068 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.28.20:5700/1) Recv SETFORMAT cmd
2026-01-29 02:10:22.068 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.28.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:10:22.069 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:10:22.069 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.28.20:5700/1) Recv NOMTXPOWER cmd
2026-01-29 02:10:22.069 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.28.20:5700/1) Recv SETFORMAT cmd
2026-01-29 02:10:22.069 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.28.20:5700/1) TRXD header version 1 -> 1
2026-01-29 02:10:22.071 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.28.20:5700/2) Recv RXTUNE cmd
2026-01-29 02:10:22.071 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.28.20:5700/2) Recv TXTUNE cmd
2026-01-29 02:10:22.071 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.28.20:5700/2) Recv SETFORMAT cmd
2026-01-29 02:10:22.071 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.28.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:10:22.071 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:10:22.071 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.28.20:5700/2) Recv NOMTXPOWER cmd
2026-01-29 02:10:22.071 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.28.20:5700/2) Recv SETFORMAT cmd
2026-01-29 02:10:22.071 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.28.20:5700/2) TRXD header version 1 -> 1
2026-01-29 02:10:22.074 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.28.20:5700/3) Recv RXTUNE cmd
2026-01-29 02:10:22.074 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.28.20:5700/3) Recv TXTUNE cmd
2026-01-29 02:10:22.074 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.28.20:5700/3) Recv SETFORMAT cmd
2026-01-29 02:10:22.074 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.28.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:10:22.074 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:10:22.074 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.28.20:5700/3) Recv NOMTXPOWER cmd
2026-01-29 02:10:22.074 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.28.20:5700/3) Recv SETFORMAT cmd
2026-01-29 02:10:22.074 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.28.20:5700/3) TRXD header version 1 -> 1
2026-01-29 02:10:22.076 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.28.20:5700) Recv RXTUNE cmd
2026-01-29 02:10:22.077 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETTSC
2026-01-29 02:10:22.077 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETTSC
2026-01-29 02:10:22.077 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETTSC
2026-01-29 02:10:22.077 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.28.20:5700) Recv TXTUNE cmd
2026-01-29 02:10:22.077 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETRXGAIN
2026-01-29 02:10:22.077 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETRXGAIN
2026-01-29 02:10:22.077 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETRXGAIN
2026-01-29 02:10:22.077 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETTSC
2026-01-29 02:10:22.077 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:10:22.077 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:10:22.077 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:10:22.077 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.28.20:5700) Recv NOMTXPOWER cmd
2026-01-29 02:10:22.077 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:10:22.077 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:10:22.077 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:10:22.077 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.28.20:5700) Recv POWERON CMD
2026-01-29 02:10:22.077 [INFO] ctrl_if_trx.py:109 (BTS@172.18.28.20:5700) Starting transceiver...
2026-01-29 02:10:22.077 [INFO] transceiver.py:243 Starting clock generator
2026-01-29 02:10:22.077 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-01-29 02:10:22.077 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:10:22.077 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:10:22.077 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:10:22.077 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETRXGAIN
2026-01-29 02:10:22.077 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:10:22.077 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:10:22.077 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:10:22.077 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:10:22.077 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:10:22.077 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:10:22.077 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:10:22.077 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:10:22.078 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:10:22.078 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:10:22.078 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:10:22.078 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:10:22.078 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:10:22.078 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:10:22.078 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:10:22.078 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:10:22.078 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:10:22.078 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:10:22.078 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:10:22.078 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:10:22.078 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:10:22.078 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:10:22.078 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:10:22.082 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-01-29 02:10:22.566 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-01-29 02:10:23.047 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-01-29 02:10:23.526 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-01-29 02:10:24.004 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-01-29 02:10:24.482 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-01-29 02:10:24.961 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-01-29 02:10:25.443 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-01-29 02:10:25.924 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-01-29 02:10:26.406 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-01-29 02:10:26.888 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-01-29 02:10:27.368 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-01-29 02:10:27.849 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-01-29 02:10:28.328 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-01-29 02:10:28.807 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-01-29 02:10:29.288 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-01-29 02:10:29.770 [DEBUG] clck_gen.py:113 IND CLOCK 1632
2026-01-29 02:10:30.251 [DEBUG] clck_gen.py:113 IND CLOCK 1734
2026-01-29 02:10:30.729 [DEBUG] clck_gen.py:113 IND CLOCK 1836
2026-01-29 02:10:31.210 [DEBUG] clck_gen.py:113 IND CLOCK 1938
2026-01-29 02:10:31.688 [DEBUG] clck_gen.py:113 IND CLOCK 2040
2026-01-29 02:10:32.166 [DEBUG] clck_gen.py:113 IND CLOCK 2142
2026-01-29 02:10:32.648 [DEBUG] clck_gen.py:113 IND CLOCK 2244
2026-01-29 02:10:33.126 [DEBUG] clck_gen.py:113 IND CLOCK 2346
2026-01-29 02:10:33.605 [DEBUG] clck_gen.py:113 IND CLOCK 2448
2026-01-29 02:10:34.087 [DEBUG] clck_gen.py:113 IND CLOCK 2550
2026-01-29 02:10:34.565 [DEBUG] clck_gen.py:113 IND CLOCK 2652
2026-01-29 02:10:35.044 [DEBUG] clck_gen.py:113 IND CLOCK 2754
2026-01-29 02:10:35.526 [DEBUG] clck_gen.py:113 IND CLOCK 2856
2026-01-29 02:10:36.007 [DEBUG] clck_gen.py:113 IND CLOCK 2958
2026-01-29 02:10:36.488 [DEBUG] clck_gen.py:113 IND CLOCK 3060
2026-01-29 02:10:36.970 [DEBUG] clck_gen.py:113 IND CLOCK 3162
2026-01-29 02:10:37.450 [DEBUG] clck_gen.py:113 IND CLOCK 3264
2026-01-29 02:10:37.928 [DEBUG] clck_gen.py:113 IND CLOCK 3366
2026-01-29 02:10:38.405 [DEBUG] clck_gen.py:113 IND CLOCK 3468
2026-01-29 02:10:38.886 [DEBUG] clck_gen.py:113 IND CLOCK 3570
2026-01-29 02:10:39.367 [DEBUG] clck_gen.py:113 IND CLOCK 3672
2026-01-29 02:10:39.849 [DEBUG] clck_gen.py:113 IND CLOCK 3774
2026-01-29 02:10:40.330 [DEBUG] clck_gen.py:113 IND CLOCK 3876
2026-01-29 02:10:40.810 [DEBUG] clck_gen.py:113 IND CLOCK 3978
2026-01-29 02:10:41.290 [DEBUG] clck_gen.py:113 IND CLOCK 4080
2026-01-29 02:10:41.772 [DEBUG] clck_gen.py:113 IND CLOCK 4182
2026-01-29 02:10:42.252 [DEBUG] clck_gen.py:113 IND CLOCK 4284
2026-01-29 02:10:42.730 [DEBUG] clck_gen.py:113 IND CLOCK 4386
2026-01-29 02:10:43.208 [DEBUG] clck_gen.py:113 IND CLOCK 4488
2026-01-29 02:10:43.686 [DEBUG] clck_gen.py:113 IND CLOCK 4590
2026-01-29 02:10:44.166 [DEBUG] clck_gen.py:113 IND CLOCK 4692
2026-01-29 02:10:44.646 [DEBUG] clck_gen.py:113 IND CLOCK 4794
2026-01-29 02:10:45.125 [DEBUG] clck_gen.py:113 IND CLOCK 4896
2026-01-29 02:10:45.605 [DEBUG] clck_gen.py:113 IND CLOCK 4998
2026-01-29 02:10:46.086 [DEBUG] clck_gen.py:113 IND CLOCK 5100
2026-01-29 02:10:46.107 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:10:46.107 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:10:46.108 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 02:10:46.108 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:10:46.108 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.28.20:5700) Recv POWEROFF cmd
2026-01-29 02:10:46.108 [INFO] ctrl_if_trx.py:117 (BTS@172.18.28.20:5700) Stopping transceiver...
2026-01-29 02:10:46.108 [INFO] transceiver.py:246 Stopping clock generator
2026-01-29 02:10:51.111 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.28.20:5700) Recv POWEROFF cmd
2026-01-29 02:10:51.111 [INFO] ctrl_if_trx.py:117 (BTS@172.18.28.20:5700) Stopping transceiver...
2026-01-29 02:10:51.113 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:10:51.113 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:10:51.114 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:10:51.114 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 02:10:51.117 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 02:10:51.117 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.28.20:5700) Recv SETFORMAT cmd
2026-01-29 02:10:51.117 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.28.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:10:51.117 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.28.20:5700) Recv SETFORMAT cmd
2026-01-29 02:10:51.117 [INFO] ctrl_if_trx.py:201 (BTS@172.18.28.20:5700) TRXD header version 1 -> 1
2026-01-29 02:10:51.118 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.28.20:5700/1) Recv RXTUNE cmd
2026-01-29 02:10:51.118 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.28.20:5700/1) Recv TXTUNE cmd
2026-01-29 02:10:51.118 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.28.20:5700/1) Recv SETFORMAT cmd
2026-01-29 02:10:51.118 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.28.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:10:51.118 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:10:51.118 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.28.20:5700/1) Recv NOMTXPOWER cmd
2026-01-29 02:10:51.118 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.28.20:5700/1) Recv SETFORMAT cmd
2026-01-29 02:10:51.118 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.28.20:5700/1) TRXD header version 1 -> 1
2026-01-29 02:10:51.119 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.28.20:5700/2) Recv RXTUNE cmd
2026-01-29 02:10:51.119 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.28.20:5700/2) Recv TXTUNE cmd
2026-01-29 02:10:51.119 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.28.20:5700/2) Recv SETFORMAT cmd
2026-01-29 02:10:51.119 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.28.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:10:51.119 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:10:51.119 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.28.20:5700/2) Recv NOMTXPOWER cmd
2026-01-29 02:10:51.119 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.28.20:5700/2) Recv SETFORMAT cmd
2026-01-29 02:10:51.119 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.28.20:5700/2) TRXD header version 1 -> 1
2026-01-29 02:10:51.120 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.28.20:5700/3) Recv RXTUNE cmd
2026-01-29 02:10:51.120 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.28.20:5700/3) Recv TXTUNE cmd
2026-01-29 02:10:51.120 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.28.20:5700/3) Recv SETFORMAT cmd
2026-01-29 02:10:51.120 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.28.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:10:51.120 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:10:51.120 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.28.20:5700/3) Recv NOMTXPOWER cmd
2026-01-29 02:10:51.121 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.28.20:5700/3) Recv SETFORMAT cmd
2026-01-29 02:10:51.121 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.28.20:5700/3) TRXD header version 1 -> 1
2026-01-29 02:10:51.122 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.28.20:5700) Recv RXTUNE cmd
2026-01-29 02:10:51.122 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETTSC
2026-01-29 02:10:51.122 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETTSC
2026-01-29 02:10:51.122 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETTSC
2026-01-29 02:10:51.122 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.28.20:5700) Recv TXTUNE cmd
2026-01-29 02:10:51.122 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETRXGAIN
2026-01-29 02:10:51.122 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETRXGAIN
2026-01-29 02:10:51.122 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETRXGAIN
2026-01-29 02:10:51.122 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETTSC
2026-01-29 02:10:51.122 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:10:51.122 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:10:51.122 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.28.20:5700) Recv NOMTXPOWER cmd
2026-01-29 02:10:51.122 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:10:51.122 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:10:51.122 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:10:51.122 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.28.20:5700) Recv POWERON CMD
2026-01-29 02:10:51.122 [INFO] ctrl_if_trx.py:109 (BTS@172.18.28.20:5700) Starting transceiver...
2026-01-29 02:10:51.122 [INFO] transceiver.py:243 Starting clock generator
2026-01-29 02:10:51.122 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-01-29 02:10:51.122 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:10:51.122 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:10:51.123 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:10:51.123 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETRXGAIN
2026-01-29 02:10:51.123 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:10:51.123 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:10:51.123 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:10:51.123 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:10:51.123 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:10:51.123 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:10:51.123 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:10:51.123 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:10:51.123 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:10:51.123 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:10:51.123 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:10:51.123 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:10:51.123 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:10:51.123 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:10:51.123 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:10:51.123 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:10:51.123 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:10:51.123 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:10:51.123 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:10:51.123 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:10:51.123 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:10:51.123 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:10:51.123 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:10:51.123 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:10:51.127 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-01-29 02:10:51.611 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-01-29 02:10:52.092 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-01-29 02:10:52.573 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-01-29 02:10:53.053 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-01-29 02:10:53.533 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-01-29 02:10:54.014 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-01-29 02:10:54.496 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-01-29 02:10:54.977 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-01-29 02:10:55.455 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-01-29 02:10:55.933 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-01-29 02:10:56.411 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-01-29 02:10:56.892 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-01-29 02:10:57.374 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-01-29 02:10:57.853 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-01-29 02:10:58.331 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-01-29 02:10:58.809 [DEBUG] clck_gen.py:113 IND CLOCK 1632
2026-01-29 02:10:59.287 [DEBUG] clck_gen.py:113 IND CLOCK 1734
2026-01-29 02:10:59.765 [DEBUG] clck_gen.py:113 IND CLOCK 1836
2026-01-29 02:11:00.238 [DEBUG] clck_gen.py:113 IND CLOCK 1938
2026-01-29 02:11:00.717 [DEBUG] clck_gen.py:113 IND CLOCK 2040
2026-01-29 02:11:01.198 [DEBUG] clck_gen.py:113 IND CLOCK 2142
2026-01-29 02:11:01.678 [DEBUG] clck_gen.py:113 IND CLOCK 2244
2026-01-29 02:11:02.156 [DEBUG] clck_gen.py:113 IND CLOCK 2346
2026-01-29 02:11:02.635 [DEBUG] clck_gen.py:113 IND CLOCK 2448
2026-01-29 02:11:03.113 [DEBUG] clck_gen.py:113 IND CLOCK 2550
2026-01-29 02:11:03.591 [DEBUG] clck_gen.py:113 IND CLOCK 2652
2026-01-29 02:11:04.070 [DEBUG] clck_gen.py:113 IND CLOCK 2754
2026-01-29 02:11:04.548 [DEBUG] clck_gen.py:113 IND CLOCK 2856
2026-01-29 02:11:05.017 [DEBUG] clck_gen.py:113 IND CLOCK 2958
2026-01-29 02:11:05.487 [DEBUG] clck_gen.py:113 IND CLOCK 3060
2026-01-29 02:11:05.958 [DEBUG] clck_gen.py:113 IND CLOCK 3162
2026-01-29 02:11:06.428 [DEBUG] clck_gen.py:113 IND CLOCK 3264
2026-01-29 02:11:06.904 [DEBUG] clck_gen.py:113 IND CLOCK 3366
2026-01-29 02:11:07.381 [DEBUG] clck_gen.py:113 IND CLOCK 3468
2026-01-29 02:11:07.859 [DEBUG] clck_gen.py:113 IND CLOCK 3570
2026-01-29 02:11:08.337 [DEBUG] clck_gen.py:113 IND CLOCK 3672
2026-01-29 02:11:08.816 [DEBUG] clck_gen.py:113 IND CLOCK 3774
2026-01-29 02:11:09.298 [DEBUG] clck_gen.py:113 IND CLOCK 3876
2026-01-29 02:11:09.779 [DEBUG] clck_gen.py:113 IND CLOCK 3978
2026-01-29 02:11:10.261 [DEBUG] clck_gen.py:113 IND CLOCK 4080
2026-01-29 02:11:10.742 [DEBUG] clck_gen.py:113 IND CLOCK 4182
2026-01-29 02:11:11.223 [DEBUG] clck_gen.py:113 IND CLOCK 4284
2026-01-29 02:11:11.704 [DEBUG] clck_gen.py:113 IND CLOCK 4386
2026-01-29 02:11:12.187 [DEBUG] clck_gen.py:113 IND CLOCK 4488
2026-01-29 02:11:12.666 [DEBUG] clck_gen.py:113 IND CLOCK 4590
2026-01-29 02:11:13.145 [DEBUG] clck_gen.py:113 IND CLOCK 4692
2026-01-29 02:11:13.625 [DEBUG] clck_gen.py:113 IND CLOCK 4794
2026-01-29 02:11:14.103 [DEBUG] clck_gen.py:113 IND CLOCK 4896
2026-01-29 02:11:14.580 [DEBUG] clck_gen.py:113 IND CLOCK 4998
2026-01-29 02:11:15.058 [DEBUG] clck_gen.py:113 IND CLOCK 5100
2026-01-29 02:11:15.537 [DEBUG] clck_gen.py:113 IND CLOCK 5202
2026-01-29 02:11:16.015 [DEBUG] clck_gen.py:113 IND CLOCK 5304
2026-01-29 02:11:16.493 [DEBUG] clck_gen.py:113 IND CLOCK 5406
2026-01-29 02:11:16.971 [DEBUG] clck_gen.py:113 IND CLOCK 5508
2026-01-29 02:11:17.449 [DEBUG] clck_gen.py:113 IND CLOCK 5610
2026-01-29 02:11:17.927 [DEBUG] clck_gen.py:113 IND CLOCK 5712
2026-01-29 02:11:18.405 [DEBUG] clck_gen.py:113 IND CLOCK 5814
2026-01-29 02:11:18.883 [DEBUG] clck_gen.py:113 IND CLOCK 5916
2026-01-29 02:11:19.361 [DEBUG] clck_gen.py:113 IND CLOCK 6018
2026-01-29 02:11:19.840 [DEBUG] clck_gen.py:113 IND CLOCK 6120
2026-01-29 02:11:20.311 [DEBUG] clck_gen.py:113 IND CLOCK 6222
2026-01-29 02:11:20.789 [DEBUG] clck_gen.py:113 IND CLOCK 6324
2026-01-29 02:11:21.268 [DEBUG] clck_gen.py:113 IND CLOCK 6426
2026-01-29 02:11:21.746 [DEBUG] clck_gen.py:113 IND CLOCK 6528
2026-01-29 02:11:22.224 [DEBUG] clck_gen.py:113 IND CLOCK 6630
2026-01-29 02:11:22.705 [DEBUG] clck_gen.py:113 IND CLOCK 6732
2026-01-29 02:11:23.186 [DEBUG] clck_gen.py:113 IND CLOCK 6834
2026-01-29 02:11:23.666 [DEBUG] clck_gen.py:113 IND CLOCK 6936
2026-01-29 02:11:24.147 [DEBUG] clck_gen.py:113 IND CLOCK 7038
2026-01-29 02:11:24.627 [DEBUG] clck_gen.py:113 IND CLOCK 7140
2026-01-29 02:11:25.109 [DEBUG] clck_gen.py:113 IND CLOCK 7242
2026-01-29 02:11:25.590 [DEBUG] clck_gen.py:113 IND CLOCK 7344
2026-01-29 02:11:26.072 [DEBUG] clck_gen.py:113 IND CLOCK 7446
2026-01-29 02:11:26.553 [DEBUG] clck_gen.py:113 IND CLOCK 7548
2026-01-29 02:11:27.032 [DEBUG] clck_gen.py:113 IND CLOCK 7650
2026-01-29 02:11:27.513 [DEBUG] clck_gen.py:113 IND CLOCK 7752
2026-01-29 02:11:27.995 [DEBUG] clck_gen.py:113 IND CLOCK 7854
2026-01-29 02:11:28.177 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 02:11:28.475 [DEBUG] clck_gen.py:113 IND CLOCK 7956
2026-01-29 02:11:28.953 [DEBUG] clck_gen.py:113 IND CLOCK 8058
2026-01-29 02:11:29.179 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 02:11:29.433 [DEBUG] clck_gen.py:113 IND CLOCK 8160
2026-01-29 02:11:29.914 [DEBUG] clck_gen.py:113 IND CLOCK 8262
2026-01-29 02:11:30.180 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 02:11:30.396 [DEBUG] clck_gen.py:113 IND CLOCK 8364
2026-01-29 02:11:30.874 [DEBUG] clck_gen.py:113 IND CLOCK 8466
2026-01-29 02:11:31.182 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 02:11:31.352 [DEBUG] clck_gen.py:113 IND CLOCK 8568
2026-01-29 02:11:31.823 [DEBUG] clck_gen.py:113 IND CLOCK 8670
2026-01-29 02:11:32.183 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 02:11:32.299 [DEBUG] clck_gen.py:113 IND CLOCK 8772
2026-01-29 02:11:32.784 [DEBUG] clck_gen.py:113 IND CLOCK 8874
2026-01-29 02:11:33.183 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 02:11:33.183 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:11:33.183 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:11:33.183 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:11:33.183 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 02:11:33.183 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.28.20:5700) Recv POWEROFF cmd
2026-01-29 02:11:33.183 [INFO] ctrl_if_trx.py:117 (BTS@172.18.28.20:5700) Stopping transceiver...
2026-01-29 02:11:33.183 [INFO] transceiver.py:246 Stopping clock generator
2026-01-29 02:11:38.187 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.28.20:5700) Recv POWEROFF cmd
2026-01-29 02:11:38.187 [INFO] ctrl_if_trx.py:117 (BTS@172.18.28.20:5700) Stopping transceiver...
2026-01-29 02:11:38.188 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:11:38.189 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:11:38.189 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:11:38.190 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 02:11:38.192 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 02:11:38.193 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.28.20:5700) Recv SETFORMAT cmd
2026-01-29 02:11:38.193 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.28.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:11:38.193 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.28.20:5700) Recv SETFORMAT cmd
2026-01-29 02:11:38.193 [INFO] ctrl_if_trx.py:201 (BTS@172.18.28.20:5700) TRXD header version 1 -> 1
2026-01-29 02:11:38.193 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.28.20:5700/1) Recv RXTUNE cmd
2026-01-29 02:11:38.194 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.28.20:5700/1) Recv TXTUNE cmd
2026-01-29 02:11:38.194 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.28.20:5700/1) Recv SETFORMAT cmd
2026-01-29 02:11:38.194 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.28.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:11:38.194 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:11:38.194 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.28.20:5700/1) Recv NOMTXPOWER cmd
2026-01-29 02:11:38.194 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.28.20:5700/1) Recv SETFORMAT cmd
2026-01-29 02:11:38.194 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.28.20:5700/1) TRXD header version 1 -> 1
2026-01-29 02:11:38.195 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.28.20:5700/2) Recv RXTUNE cmd
2026-01-29 02:11:38.195 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.28.20:5700/2) Recv TXTUNE cmd
2026-01-29 02:11:38.195 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.28.20:5700/2) Recv SETFORMAT cmd
2026-01-29 02:11:38.195 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.28.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:11:38.195 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:11:38.195 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.28.20:5700/2) Recv NOMTXPOWER cmd
2026-01-29 02:11:38.195 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.28.20:5700/2) Recv SETFORMAT cmd
2026-01-29 02:11:38.195 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.28.20:5700/2) TRXD header version 1 -> 1
2026-01-29 02:11:38.196 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.28.20:5700/3) Recv RXTUNE cmd
2026-01-29 02:11:38.196 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.28.20:5700/3) Recv TXTUNE cmd
2026-01-29 02:11:38.196 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.28.20:5700/3) Recv SETFORMAT cmd
2026-01-29 02:11:38.196 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.28.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:11:38.196 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:11:38.196 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.28.20:5700/3) Recv NOMTXPOWER cmd
2026-01-29 02:11:38.196 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.28.20:5700/3) Recv SETFORMAT cmd
2026-01-29 02:11:38.196 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.28.20:5700/3) TRXD header version 1 -> 1
2026-01-29 02:11:38.197 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.28.20:5700) Recv RXTUNE cmd
2026-01-29 02:11:38.197 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETTSC
2026-01-29 02:11:38.197 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETTSC
2026-01-29 02:11:38.197 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETTSC
2026-01-29 02:11:38.197 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.28.20:5700) Recv TXTUNE cmd
2026-01-29 02:11:38.197 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETRXGAIN
2026-01-29 02:11:38.197 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETRXGAIN
2026-01-29 02:11:38.197 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETRXGAIN
2026-01-29 02:11:38.197 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETTSC
2026-01-29 02:11:38.197 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:11:38.198 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:11:38.198 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:11:38.198 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.28.20:5700) Recv NOMTXPOWER cmd
2026-01-29 02:11:38.198 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:11:38.198 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:11:38.198 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:11:38.198 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.28.20:5700) Recv POWERON CMD
2026-01-29 02:11:38.198 [INFO] ctrl_if_trx.py:109 (BTS@172.18.28.20:5700) Starting transceiver...
2026-01-29 02:11:38.198 [INFO] transceiver.py:243 Starting clock generator
2026-01-29 02:11:38.198 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-01-29 02:11:38.198 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:11:38.198 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:11:38.198 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:11:38.198 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETRXGAIN
2026-01-29 02:11:38.198 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:11:38.198 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:11:38.198 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:11:38.198 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:11:38.198 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:11:38.198 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:11:38.198 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:11:38.198 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:11:38.198 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:11:38.198 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:11:38.198 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:11:38.198 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:11:38.198 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:11:38.198 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:11:38.198 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:11:38.198 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:11:38.198 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:11:38.198 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:11:38.198 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:11:38.198 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:11:38.198 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:11:38.198 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:11:38.199 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:11:38.202 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-01-29 02:11:38.684 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-01-29 02:11:38.726 [DEBUG] fake_trx.py:278 (BTS@172.18.28.20:5700) Recv FAKE_TOA cmd
2026-01-29 02:11:38.728 [DEBUG] fake_trx.py:297 (BTS@172.18.28.20:5700) Recv FAKE_RSSI cmd
2026-01-29 02:11:38.730 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:11:38.730 [DEBUG] fake_trx.py:322 (BTS@172.18.28.20:5700) Recv FAKE_CI cmd
2026-01-29 02:11:38.752 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 02:11:38.752 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 02:11:38.752 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 02:11:38.758 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:11:38.758 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 02:11:38.759 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 02:11:38.759 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.28.22:6700) Recv POWERON CMD
2026-01-29 02:11:38.759 [INFO] ctrl_if_trx.py:109 (MS@172.18.28.22:6700) Starting transceiver...
2026-01-29 02:11:38.778 [DEBUG] fake_trx.py:297 (BTS@172.18.28.20:5700) Recv FAKE_RSSI cmd
2026-01-29 02:11:38.788 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:11:38.791 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 02:11:38.791 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 02:11:38.792 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:11:38.792 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:11:39.162 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-01-29 02:11:39.200 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 02:11:39.201 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:11:39.201 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:11:39.203 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:11:39.640 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-01-29 02:11:39.656 [DEBUG] fake_trx.py:269 (MS@172.18.28.22:6700) Recv SETTA cmd
2026-01-29 02:11:40.118 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-01-29 02:11:40.201 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:11:40.202 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 02:11:40.202 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:11:40.204 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:11:40.596 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-01-29 02:11:41.073 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-01-29 02:11:41.202 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:11:41.202 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:11:41.203 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 02:11:41.206 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:11:41.551 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-01-29 02:11:42.030 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-01-29 02:11:42.203 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:11:42.204 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 02:11:42.204 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:11:42.206 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:11:42.507 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-01-29 02:11:42.995 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-01-29 02:11:43.078 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:11:43.081 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:11:43.081 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 02:11:43.082 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 02:11:43.093 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 02:11:43.093 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 02:11:43.093 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 02:11:43.095 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:11:43.095 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 02:11:43.095 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 02:11:43.095 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.28.22:6700) Recv POWERON CMD
2026-01-29 02:11:43.095 [INFO] ctrl_if_trx.py:109 (MS@172.18.28.22:6700) Starting transceiver...
2026-01-29 02:11:43.134 [DEBUG] fake_trx.py:297 (BTS@172.18.28.20:5700) Recv FAKE_RSSI cmd
2026-01-29 02:11:43.146 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:11:43.149 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 02:11:43.149 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 02:11:43.149 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:11:43.149 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:11:43.204 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:11:43.204 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 02:11:43.205 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:11:43.207 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:11:43.470 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-01-29 02:11:43.949 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-01-29 02:11:44.288 [DEBUG] fake_trx.py:269 (MS@172.18.28.22:6700) Recv SETTA cmd
2026-01-29 02:11:44.426 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-01-29 02:11:44.904 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-01-29 02:11:45.381 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-01-29 02:11:45.859 [DEBUG] clck_gen.py:113 IND CLOCK 1632
2026-01-29 02:11:46.338 [DEBUG] clck_gen.py:113 IND CLOCK 1734
2026-01-29 02:11:46.815 [DEBUG] clck_gen.py:113 IND CLOCK 1836
2026-01-29 02:11:47.213 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:11:47.215 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:11:47.216 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 02:11:47.216 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 02:11:47.232 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 02:11:47.232 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 02:11:47.232 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 02:11:47.233 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:11:47.233 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 02:11:47.234 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 02:11:47.234 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.28.22:6700) Recv POWERON CMD
2026-01-29 02:11:47.234 [INFO] ctrl_if_trx.py:109 (MS@172.18.28.22:6700) Starting transceiver...
2026-01-29 02:11:47.286 [DEBUG] fake_trx.py:297 (BTS@172.18.28.20:5700) Recv FAKE_RSSI cmd
2026-01-29 02:11:47.290 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:11:47.291 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 02:11:47.291 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 02:11:47.292 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:11:47.292 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:11:47.292 [DEBUG] clck_gen.py:113 IND CLOCK 1938
2026-01-29 02:11:47.728 [DEBUG] fake_trx.py:269 (MS@172.18.28.22:6700) Recv SETTA cmd
2026-01-29 02:11:47.769 [DEBUG] clck_gen.py:113 IND CLOCK 2040
2026-01-29 02:11:48.247 [DEBUG] clck_gen.py:113 IND CLOCK 2142
2026-01-29 02:11:48.725 [DEBUG] clck_gen.py:113 IND CLOCK 2244
2026-01-29 02:11:49.202 [DEBUG] clck_gen.py:113 IND CLOCK 2346
2026-01-29 02:11:49.679 [DEBUG] clck_gen.py:113 IND CLOCK 2448
2026-01-29 02:11:50.157 [DEBUG] clck_gen.py:113 IND CLOCK 2550
2026-01-29 02:11:50.635 [DEBUG] clck_gen.py:113 IND CLOCK 2652
2026-01-29 02:11:51.073 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:11:51.075 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:11:51.076 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 02:11:51.076 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 02:11:51.094 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 02:11:51.094 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 02:11:51.094 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 02:11:51.096 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:11:51.096 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 02:11:51.096 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 02:11:51.096 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.28.22:6700) Recv POWERON CMD
2026-01-29 02:11:51.096 [INFO] ctrl_if_trx.py:109 (MS@172.18.28.22:6700) Starting transceiver...
2026-01-29 02:11:51.102 [DEBUG] fake_trx.py:297 (BTS@172.18.28.20:5700) Recv FAKE_RSSI cmd
2026-01-29 02:11:51.105 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:11:51.106 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 02:11:51.106 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 02:11:51.106 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:11:51.107 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:11:51.112 [DEBUG] clck_gen.py:113 IND CLOCK 2754
2026-01-29 02:11:51.589 [DEBUG] clck_gen.py:113 IND CLOCK 2856
2026-01-29 02:11:51.979 [DEBUG] fake_trx.py:269 (MS@172.18.28.22:6700) Recv SETTA cmd
2026-01-29 02:11:52.066 [DEBUG] clck_gen.py:113 IND CLOCK 2958
2026-01-29 02:11:52.457 [DEBUG] fake_trx.py:269 (MS@172.18.28.22:6700) Recv SETTA cmd
2026-01-29 02:11:52.544 [DEBUG] clck_gen.py:113 IND CLOCK 3060
2026-01-29 02:11:53.021 [DEBUG] clck_gen.py:113 IND CLOCK 3162
2026-01-29 02:11:53.412 [DEBUG] fake_trx.py:269 (MS@172.18.28.22:6700) Recv SETTA cmd
2026-01-29 02:11:53.498 [DEBUG] clck_gen.py:113 IND CLOCK 3264
2026-01-29 02:11:53.976 [DEBUG] clck_gen.py:113 IND CLOCK 3366
2026-01-29 02:11:54.454 [DEBUG] clck_gen.py:113 IND CLOCK 3468
2026-01-29 02:11:54.847 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:11:54.849 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:11:54.849 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 02:11:54.849 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 02:11:54.852 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 02:11:54.852 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:11:54.852 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:11:54.852 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:11:54.853 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 02:11:54.853 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:11:54.853 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:11:54.853 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:11:54.853 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.28.20:5700) Recv POWEROFF cmd
2026-01-29 02:11:54.853 [INFO] ctrl_if_trx.py:117 (BTS@172.18.28.20:5700) Stopping transceiver...
2026-01-29 02:11:54.853 [INFO] transceiver.py:246 Stopping clock generator
2026-01-29 02:11:54.853 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=3556 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:11:54.853 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=3556 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:11:54.853 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=3556 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:11:54.853 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=3556 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:11:54.853 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=3556 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:11:54.853 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=3556 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:11:54.853 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=3556 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:11:54.853 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=3556 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:11:59.855 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.28.20:5700) Recv POWEROFF cmd
2026-01-29 02:11:59.856 [INFO] ctrl_if_trx.py:117 (BTS@172.18.28.20:5700) Stopping transceiver...
2026-01-29 02:11:59.857 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:11:59.858 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:11:59.858 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:11:59.859 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 02:11:59.861 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 02:11:59.861 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.28.20:5700) Recv SETFORMAT cmd
2026-01-29 02:11:59.861 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.28.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:11:59.862 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.28.20:5700) Recv SETFORMAT cmd
2026-01-29 02:11:59.862 [INFO] ctrl_if_trx.py:201 (BTS@172.18.28.20:5700) TRXD header version 1 -> 1
2026-01-29 02:11:59.862 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.28.20:5700/1) Recv RXTUNE cmd
2026-01-29 02:11:59.862 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.28.20:5700/1) Recv TXTUNE cmd
2026-01-29 02:11:59.863 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.28.20:5700/1) Recv SETFORMAT cmd
2026-01-29 02:11:59.863 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.28.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:11:59.863 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:11:59.863 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.28.20:5700/1) Recv NOMTXPOWER cmd
2026-01-29 02:11:59.863 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.28.20:5700/1) Recv SETFORMAT cmd
2026-01-29 02:11:59.863 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.28.20:5700/1) TRXD header version 1 -> 1
2026-01-29 02:11:59.863 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.28.20:5700/2) Recv RXTUNE cmd
2026-01-29 02:11:59.863 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.28.20:5700/2) Recv TXTUNE cmd
2026-01-29 02:11:59.863 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.28.20:5700/2) Recv SETFORMAT cmd
2026-01-29 02:11:59.863 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.28.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:11:59.863 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:11:59.864 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.28.20:5700/2) Recv NOMTXPOWER cmd
2026-01-29 02:11:59.864 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.28.20:5700/2) Recv SETFORMAT cmd
2026-01-29 02:11:59.864 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.28.20:5700/2) TRXD header version 1 -> 1
2026-01-29 02:11:59.864 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.28.20:5700/3) Recv RXTUNE cmd
2026-01-29 02:11:59.864 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.28.20:5700/3) Recv TXTUNE cmd
2026-01-29 02:11:59.864 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.28.20:5700/3) Recv SETFORMAT cmd
2026-01-29 02:11:59.864 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.28.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:11:59.865 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:11:59.865 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.28.20:5700/3) Recv NOMTXPOWER cmd
2026-01-29 02:11:59.865 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.28.20:5700/3) Recv SETFORMAT cmd
2026-01-29 02:11:59.865 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.28.20:5700/3) TRXD header version 1 -> 1
2026-01-29 02:11:59.866 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.28.20:5700) Recv RXTUNE cmd
2026-01-29 02:11:59.866 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETTSC
2026-01-29 02:11:59.866 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETTSC
2026-01-29 02:11:59.866 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETTSC
2026-01-29 02:11:59.866 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.28.20:5700) Recv TXTUNE cmd
2026-01-29 02:11:59.866 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETRXGAIN
2026-01-29 02:11:59.866 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETRXGAIN
2026-01-29 02:11:59.866 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETRXGAIN
2026-01-29 02:11:59.866 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETTSC
2026-01-29 02:11:59.866 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:11:59.866 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:11:59.866 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:11:59.866 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.28.20:5700) Recv NOMTXPOWER cmd
2026-01-29 02:11:59.866 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:11:59.866 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:11:59.866 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:11:59.866 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.28.20:5700) Recv POWERON CMD
2026-01-29 02:11:59.866 [INFO] ctrl_if_trx.py:109 (BTS@172.18.28.20:5700) Starting transceiver...
2026-01-29 02:11:59.866 [INFO] transceiver.py:243 Starting clock generator
2026-01-29 02:11:59.866 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-01-29 02:11:59.867 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:11:59.867 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:11:59.867 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:11:59.867 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETRXGAIN
2026-01-29 02:11:59.867 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:11:59.867 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:11:59.867 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:11:59.867 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:11:59.867 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:11:59.867 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:11:59.867 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:11:59.867 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:11:59.867 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:11:59.867 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:11:59.867 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:11:59.867 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:11:59.867 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:11:59.867 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:11:59.867 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:11:59.867 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:11:59.867 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:11:59.867 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:11:59.867 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:11:59.867 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:11:59.867 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:11:59.867 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:11:59.867 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:11:59.871 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-01-29 02:12:00.355 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-01-29 02:12:00.388 [DEBUG] fake_trx.py:278 (BTS@172.18.28.20:5700) Recv FAKE_TOA cmd
2026-01-29 02:12:00.390 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:12:00.391 [DEBUG] fake_trx.py:297 (BTS@172.18.28.20:5700) Recv FAKE_RSSI cmd
2026-01-29 02:12:00.393 [DEBUG] fake_trx.py:322 (BTS@172.18.28.20:5700) Recv FAKE_CI cmd
2026-01-29 02:12:00.421 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 02:12:00.421 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 02:12:00.421 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 02:12:00.427 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:12:00.427 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 02:12:00.427 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 02:12:00.428 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.28.22:6700) Recv POWERON CMD
2026-01-29 02:12:00.428 [INFO] ctrl_if_trx.py:109 (MS@172.18.28.22:6700) Starting transceiver...
2026-01-29 02:12:00.448 [DEBUG] fake_trx.py:297 (BTS@172.18.28.20:5700) Recv FAKE_RSSI cmd
2026-01-29 02:12:00.459 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:12:00.461 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 02:12:00.461 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 02:12:00.461 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:12:00.462 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:12:00.829 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-01-29 02:12:00.869 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 02:12:00.869 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:12:00.870 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:12:00.872 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:12:01.307 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-01-29 02:12:01.323 [DEBUG] fake_trx.py:297 (BTS@172.18.28.20:5700) Recv FAKE_RSSI cmd
2026-01-29 02:12:01.326 [DEBUG] fake_trx.py:269 (MS@172.18.28.22:6700) Recv SETTA cmd
2026-01-29 02:12:01.784 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-01-29 02:12:01.809 [DEBUG] fake_trx.py:297 (BTS@172.18.28.20:5700) Recv FAKE_RSSI cmd
2026-01-29 02:12:01.870 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:12:01.870 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:12:01.871 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 02:12:01.873 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:12:02.263 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-01-29 02:12:02.297 [DEBUG] fake_trx.py:297 (BTS@172.18.28.20:5700) Recv FAKE_RSSI cmd
2026-01-29 02:12:02.740 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-01-29 02:12:02.784 [DEBUG] fake_trx.py:297 (BTS@172.18.28.20:5700) Recv FAKE_RSSI cmd
2026-01-29 02:12:02.871 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:12:02.871 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 02:12:02.871 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:12:02.874 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:12:03.218 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-01-29 02:12:03.271 [DEBUG] fake_trx.py:297 (BTS@172.18.28.20:5700) Recv FAKE_RSSI cmd
2026-01-29 02:12:03.696 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-01-29 02:12:03.758 [DEBUG] fake_trx.py:297 (BTS@172.18.28.20:5700) Recv FAKE_RSSI cmd
2026-01-29 02:12:03.872 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:12:03.872 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 02:12:03.872 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:12:03.876 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:12:04.174 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-01-29 02:12:04.245 [DEBUG] fake_trx.py:297 (BTS@172.18.28.20:5700) Recv FAKE_RSSI cmd
2026-01-29 02:12:04.652 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-01-29 02:12:04.732 [DEBUG] fake_trx.py:297 (BTS@172.18.28.20:5700) Recv FAKE_RSSI cmd
2026-01-29 02:12:04.873 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:12:04.873 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 02:12:04.874 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:12:04.877 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:12:05.125 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-01-29 02:12:05.212 [DEBUG] fake_trx.py:297 (BTS@172.18.28.20:5700) Recv FAKE_RSSI cmd
2026-01-29 02:12:05.600 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-01-29 02:12:05.699 [DEBUG] fake_trx.py:297 (BTS@172.18.28.20:5700) Recv FAKE_RSSI cmd
2026-01-29 02:12:06.078 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-01-29 02:12:06.186 [DEBUG] fake_trx.py:297 (BTS@172.18.28.20:5700) Recv FAKE_RSSI cmd
2026-01-29 02:12:06.556 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-01-29 02:12:06.673 [DEBUG] fake_trx.py:297 (BTS@172.18.28.20:5700) Recv FAKE_RSSI cmd
2026-01-29 02:12:07.034 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-01-29 02:12:07.160 [DEBUG] fake_trx.py:297 (BTS@172.18.28.20:5700) Recv FAKE_RSSI cmd
2026-01-29 02:12:07.511 [DEBUG] clck_gen.py:113 IND CLOCK 1632
2026-01-29 02:12:07.669 [DEBUG] fake_trx.py:297 (BTS@172.18.28.20:5700) Recv FAKE_RSSI cmd
2026-01-29 02:12:07.989 [DEBUG] clck_gen.py:113 IND CLOCK 1734
2026-01-29 02:12:08.134 [DEBUG] fake_trx.py:297 (BTS@172.18.28.20:5700) Recv FAKE_RSSI cmd
2026-01-29 02:12:08.467 [DEBUG] clck_gen.py:113 IND CLOCK 1836
2026-01-29 02:12:08.621 [DEBUG] fake_trx.py:297 (BTS@172.18.28.20:5700) Recv FAKE_RSSI cmd
2026-01-29 02:12:08.626 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:12:08.629 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:12:08.629 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 02:12:08.629 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 02:12:08.629 [WARNING] transceiver.py:257 (MS@172.18.28.22:6700) RX TRXD message (fn=1873 tn=1 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:12:08.649 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 02:12:08.649 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 02:12:08.649 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 02:12:08.650 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:12:08.650 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 02:12:08.650 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 02:12:08.650 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.28.22:6700) Recv POWERON CMD
2026-01-29 02:12:08.650 [INFO] ctrl_if_trx.py:109 (MS@172.18.28.22:6700) Starting transceiver...
2026-01-29 02:12:08.702 [DEBUG] fake_trx.py:297 (BTS@172.18.28.20:5700) Recv FAKE_RSSI cmd
2026-01-29 02:12:08.715 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:12:08.720 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 02:12:08.720 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 02:12:08.720 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:12:08.720 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:12:08.944 [DEBUG] clck_gen.py:113 IND CLOCK 1938
2026-01-29 02:12:09.349 [DEBUG] fake_trx.py:297 (BTS@172.18.28.20:5700) Recv FAKE_RSSI cmd
2026-01-29 02:12:09.422 [DEBUG] clck_gen.py:113 IND CLOCK 2040
2026-01-29 02:12:09.835 [DEBUG] fake_trx.py:297 (BTS@172.18.28.20:5700) Recv FAKE_RSSI cmd
2026-01-29 02:12:09.838 [DEBUG] fake_trx.py:269 (MS@172.18.28.22:6700) Recv SETTA cmd
2026-01-29 02:12:09.900 [DEBUG] clck_gen.py:113 IND CLOCK 2142
2026-01-29 02:12:10.323 [DEBUG] fake_trx.py:297 (BTS@172.18.28.20:5700) Recv FAKE_RSSI cmd
2026-01-29 02:12:10.378 [DEBUG] clck_gen.py:113 IND CLOCK 2244
2026-01-29 02:12:10.810 [DEBUG] fake_trx.py:297 (BTS@172.18.28.20:5700) Recv FAKE_RSSI cmd
2026-01-29 02:12:10.856 [DEBUG] clck_gen.py:113 IND CLOCK 2346
2026-01-29 02:12:11.297 [DEBUG] fake_trx.py:297 (BTS@172.18.28.20:5700) Recv FAKE_RSSI cmd
2026-01-29 02:12:11.334 [DEBUG] clck_gen.py:113 IND CLOCK 2448
2026-01-29 02:12:11.784 [DEBUG] fake_trx.py:297 (BTS@172.18.28.20:5700) Recv FAKE_RSSI cmd
2026-01-29 02:12:11.812 [DEBUG] clck_gen.py:113 IND CLOCK 2550
2026-01-29 02:12:12.272 [DEBUG] fake_trx.py:297 (BTS@172.18.28.20:5700) Recv FAKE_RSSI cmd
2026-01-29 02:12:12.290 [DEBUG] clck_gen.py:113 IND CLOCK 2652
2026-01-29 02:12:12.759 [DEBUG] fake_trx.py:297 (BTS@172.18.28.20:5700) Recv FAKE_RSSI cmd
2026-01-29 02:12:12.769 [DEBUG] clck_gen.py:113 IND CLOCK 2754
2026-01-29 02:12:13.247 [DEBUG] fake_trx.py:297 (BTS@172.18.28.20:5700) Recv FAKE_RSSI cmd
2026-01-29 02:12:13.247 [DEBUG] clck_gen.py:113 IND CLOCK 2856
2026-01-29 02:12:13.725 [DEBUG] clck_gen.py:113 IND CLOCK 2958
2026-01-29 02:12:13.741 [DEBUG] fake_trx.py:297 (BTS@172.18.28.20:5700) Recv FAKE_RSSI cmd
2026-01-29 02:12:14.203 [DEBUG] clck_gen.py:113 IND CLOCK 3060
2026-01-29 02:12:14.229 [DEBUG] fake_trx.py:297 (BTS@172.18.28.20:5700) Recv FAKE_RSSI cmd
2026-01-29 02:12:14.680 [DEBUG] clck_gen.py:113 IND CLOCK 3162
2026-01-29 02:12:14.715 [DEBUG] fake_trx.py:297 (BTS@172.18.28.20:5700) Recv FAKE_RSSI cmd
2026-01-29 02:12:15.158 [DEBUG] clck_gen.py:113 IND CLOCK 3264
2026-01-29 02:12:15.202 [DEBUG] fake_trx.py:297 (BTS@172.18.28.20:5700) Recv FAKE_RSSI cmd
2026-01-29 02:12:15.636 [DEBUG] clck_gen.py:113 IND CLOCK 3366
2026-01-29 02:12:15.689 [DEBUG] fake_trx.py:297 (BTS@172.18.28.20:5700) Recv FAKE_RSSI cmd
2026-01-29 02:12:16.113 [DEBUG] clck_gen.py:113 IND CLOCK 3468
2026-01-29 02:12:16.176 [DEBUG] fake_trx.py:297 (BTS@172.18.28.20:5700) Recv FAKE_RSSI cmd
2026-01-29 02:12:16.590 [DEBUG] clck_gen.py:113 IND CLOCK 3570
2026-01-29 02:12:16.662 [DEBUG] fake_trx.py:297 (BTS@172.18.28.20:5700) Recv FAKE_RSSI cmd
2026-01-29 02:12:16.666 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:12:16.669 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:12:16.670 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 02:12:16.670 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 02:12:16.682 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 02:12:16.682 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 02:12:16.682 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 02:12:16.684 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:12:16.684 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 02:12:16.684 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 02:12:16.684 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.28.22:6700) Recv POWERON CMD
2026-01-29 02:12:16.684 [INFO] ctrl_if_trx.py:109 (MS@172.18.28.22:6700) Starting transceiver...
2026-01-29 02:12:16.729 [DEBUG] fake_trx.py:297 (BTS@172.18.28.20:5700) Recv FAKE_RSSI cmd
2026-01-29 02:12:16.741 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:12:16.744 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 02:12:16.745 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 02:12:16.745 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:12:16.745 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:12:17.026 [DEBUG] fake_trx.py:297 (BTS@172.18.28.20:5700) Recv FAKE_RSSI cmd
2026-01-29 02:12:17.068 [DEBUG] clck_gen.py:113 IND CLOCK 3672
2026-01-29 02:12:17.504 [DEBUG] fake_trx.py:297 (BTS@172.18.28.20:5700) Recv FAKE_RSSI cmd
2026-01-29 02:12:17.506 [DEBUG] fake_trx.py:269 (MS@172.18.28.22:6700) Recv SETTA cmd
2026-01-29 02:12:17.545 [DEBUG] clck_gen.py:113 IND CLOCK 3774
2026-01-29 02:12:17.981 [DEBUG] fake_trx.py:297 (BTS@172.18.28.20:5700) Recv FAKE_RSSI cmd
2026-01-29 02:12:18.023 [DEBUG] clck_gen.py:113 IND CLOCK 3876
2026-01-29 02:12:18.459 [DEBUG] fake_trx.py:297 (BTS@172.18.28.20:5700) Recv FAKE_RSSI cmd
2026-01-29 02:12:18.500 [DEBUG] clck_gen.py:113 IND CLOCK 3978
2026-01-29 02:12:18.936 [DEBUG] fake_trx.py:297 (BTS@172.18.28.20:5700) Recv FAKE_RSSI cmd
2026-01-29 02:12:18.978 [DEBUG] clck_gen.py:113 IND CLOCK 4080
2026-01-29 02:12:19.414 [DEBUG] fake_trx.py:297 (BTS@172.18.28.20:5700) Recv FAKE_RSSI cmd
2026-01-29 02:12:19.456 [DEBUG] clck_gen.py:113 IND CLOCK 4182
2026-01-29 02:12:19.892 [DEBUG] fake_trx.py:297 (BTS@172.18.28.20:5700) Recv FAKE_RSSI cmd
2026-01-29 02:12:19.934 [DEBUG] clck_gen.py:113 IND CLOCK 4284
2026-01-29 02:12:20.370 [DEBUG] fake_trx.py:297 (BTS@172.18.28.20:5700) Recv FAKE_RSSI cmd
2026-01-29 02:12:20.412 [DEBUG] clck_gen.py:113 IND CLOCK 4386
2026-01-29 02:12:20.847 [DEBUG] fake_trx.py:297 (BTS@172.18.28.20:5700) Recv FAKE_RSSI cmd
2026-01-29 02:12:20.889 [DEBUG] clck_gen.py:113 IND CLOCK 4488
2026-01-29 02:12:21.325 [DEBUG] fake_trx.py:297 (BTS@172.18.28.20:5700) Recv FAKE_RSSI cmd
2026-01-29 02:12:21.367 [DEBUG] clck_gen.py:113 IND CLOCK 4590
2026-01-29 02:12:21.803 [DEBUG] fake_trx.py:297 (BTS@172.18.28.20:5700) Recv FAKE_RSSI cmd
2026-01-29 02:12:21.845 [DEBUG] clck_gen.py:113 IND CLOCK 4692
2026-01-29 02:12:22.281 [DEBUG] fake_trx.py:297 (BTS@172.18.28.20:5700) Recv FAKE_RSSI cmd
2026-01-29 02:12:22.323 [DEBUG] clck_gen.py:113 IND CLOCK 4794
2026-01-29 02:12:22.759 [DEBUG] fake_trx.py:297 (BTS@172.18.28.20:5700) Recv FAKE_RSSI cmd
2026-01-29 02:12:22.801 [DEBUG] clck_gen.py:113 IND CLOCK 4896
2026-01-29 02:12:23.236 [DEBUG] fake_trx.py:297 (BTS@172.18.28.20:5700) Recv FAKE_RSSI cmd
2026-01-29 02:12:23.278 [DEBUG] clck_gen.py:113 IND CLOCK 4998
2026-01-29 02:12:23.714 [DEBUG] fake_trx.py:297 (BTS@172.18.28.20:5700) Recv FAKE_RSSI cmd
2026-01-29 02:12:23.756 [DEBUG] clck_gen.py:113 IND CLOCK 5100
2026-01-29 02:12:24.191 [DEBUG] fake_trx.py:297 (BTS@172.18.28.20:5700) Recv FAKE_RSSI cmd
2026-01-29 02:12:24.196 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:12:24.198 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:12:24.198 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 02:12:24.198 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 02:12:24.205 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 02:12:24.205 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 02:12:24.205 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 02:12:24.207 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:12:24.207 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 02:12:24.207 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 02:12:24.207 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.28.22:6700) Recv POWERON CMD
2026-01-29 02:12:24.207 [INFO] ctrl_if_trx.py:109 (MS@172.18.28.22:6700) Starting transceiver...
2026-01-29 02:12:24.225 [DEBUG] fake_trx.py:297 (BTS@172.18.28.20:5700) Recv FAKE_RSSI cmd
2026-01-29 02:12:24.233 [DEBUG] clck_gen.py:113 IND CLOCK 5202
2026-01-29 02:12:24.235 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:12:24.237 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 02:12:24.237 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 02:12:24.237 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:12:24.238 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:12:24.624 [DEBUG] fake_trx.py:297 (BTS@172.18.28.20:5700) Recv FAKE_RSSI cmd
2026-01-29 02:12:24.711 [DEBUG] clck_gen.py:113 IND CLOCK 5304
2026-01-29 02:12:25.101 [DEBUG] fake_trx.py:297 (BTS@172.18.28.20:5700) Recv FAKE_RSSI cmd
2026-01-29 02:12:25.104 [DEBUG] fake_trx.py:269 (MS@172.18.28.22:6700) Recv SETTA cmd
2026-01-29 02:12:25.188 [DEBUG] clck_gen.py:113 IND CLOCK 5406
2026-01-29 02:12:25.578 [DEBUG] fake_trx.py:297 (BTS@172.18.28.20:5700) Recv FAKE_RSSI cmd
2026-01-29 02:12:25.581 [DEBUG] fake_trx.py:269 (MS@172.18.28.22:6700) Recv SETTA cmd
2026-01-29 02:12:25.665 [DEBUG] clck_gen.py:113 IND CLOCK 5508
2026-01-29 02:12:26.056 [DEBUG] fake_trx.py:297 (BTS@172.18.28.20:5700) Recv FAKE_RSSI cmd
2026-01-29 02:12:26.143 [DEBUG] clck_gen.py:113 IND CLOCK 5610
2026-01-29 02:12:26.533 [DEBUG] fake_trx.py:297 (BTS@172.18.28.20:5700) Recv FAKE_RSSI cmd
2026-01-29 02:12:26.536 [DEBUG] fake_trx.py:269 (MS@172.18.28.22:6700) Recv SETTA cmd
2026-01-29 02:12:26.621 [DEBUG] clck_gen.py:113 IND CLOCK 5712
2026-01-29 02:12:27.011 [DEBUG] fake_trx.py:297 (BTS@172.18.28.20:5700) Recv FAKE_RSSI cmd
2026-01-29 02:12:27.098 [DEBUG] clck_gen.py:113 IND CLOCK 5814
2026-01-29 02:12:27.488 [DEBUG] fake_trx.py:297 (BTS@172.18.28.20:5700) Recv FAKE_RSSI cmd
2026-01-29 02:12:27.576 [DEBUG] clck_gen.py:113 IND CLOCK 5916
2026-01-29 02:12:27.966 [DEBUG] fake_trx.py:297 (BTS@172.18.28.20:5700) Recv FAKE_RSSI cmd
2026-01-29 02:12:28.054 [DEBUG] clck_gen.py:113 IND CLOCK 6018
2026-01-29 02:12:28.444 [DEBUG] fake_trx.py:297 (BTS@172.18.28.20:5700) Recv FAKE_RSSI cmd
2026-01-29 02:12:28.532 [DEBUG] clck_gen.py:113 IND CLOCK 6120
2026-01-29 02:12:28.923 [DEBUG] fake_trx.py:297 (BTS@172.18.28.20:5700) Recv FAKE_RSSI cmd
2026-01-29 02:12:29.010 [DEBUG] clck_gen.py:113 IND CLOCK 6222
2026-01-29 02:12:29.400 [DEBUG] fake_trx.py:297 (BTS@172.18.28.20:5700) Recv FAKE_RSSI cmd
2026-01-29 02:12:29.488 [DEBUG] clck_gen.py:113 IND CLOCK 6324
2026-01-29 02:12:29.878 [DEBUG] fake_trx.py:297 (BTS@172.18.28.20:5700) Recv FAKE_RSSI cmd
2026-01-29 02:12:29.965 [DEBUG] clck_gen.py:113 IND CLOCK 6426
2026-01-29 02:12:30.356 [DEBUG] fake_trx.py:297 (BTS@172.18.28.20:5700) Recv FAKE_RSSI cmd
2026-01-29 02:12:30.443 [DEBUG] clck_gen.py:113 IND CLOCK 6528
2026-01-29 02:12:30.833 [DEBUG] fake_trx.py:297 (BTS@172.18.28.20:5700) Recv FAKE_RSSI cmd
2026-01-29 02:12:30.921 [DEBUG] clck_gen.py:113 IND CLOCK 6630
2026-01-29 02:12:31.311 [DEBUG] fake_trx.py:297 (BTS@172.18.28.20:5700) Recv FAKE_RSSI cmd
2026-01-29 02:12:31.399 [DEBUG] clck_gen.py:113 IND CLOCK 6732
2026-01-29 02:12:31.789 [DEBUG] fake_trx.py:297 (BTS@172.18.28.20:5700) Recv FAKE_RSSI cmd
2026-01-29 02:12:31.794 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:12:31.797 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:12:31.797 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 02:12:31.797 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 02:12:31.808 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 02:12:31.809 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:12:31.809 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:12:31.809 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:12:31.809 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 02:12:31.810 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:12:31.810 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:12:31.810 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.28.20:5700) Recv POWEROFF cmd
2026-01-29 02:12:31.810 [INFO] ctrl_if_trx.py:117 (BTS@172.18.28.20:5700) Stopping transceiver...
2026-01-29 02:12:31.810 [INFO] transceiver.py:246 Stopping clock generator
2026-01-29 02:12:31.810 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:12:36.811 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.28.20:5700) Recv POWEROFF cmd
2026-01-29 02:12:36.812 [INFO] ctrl_if_trx.py:117 (BTS@172.18.28.20:5700) Stopping transceiver...
2026-01-29 02:12:36.813 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:12:36.814 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:12:36.814 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:12:36.815 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 02:12:36.821 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 02:12:36.822 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.28.20:5700) Recv SETFORMAT cmd
2026-01-29 02:12:36.822 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.28.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:12:36.823 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.28.20:5700) Recv SETFORMAT cmd
2026-01-29 02:12:36.823 [INFO] ctrl_if_trx.py:201 (BTS@172.18.28.20:5700) TRXD header version 1 -> 1
2026-01-29 02:12:36.826 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.28.20:5700/1) Recv RXTUNE cmd
2026-01-29 02:12:36.827 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.28.20:5700/1) Recv TXTUNE cmd
2026-01-29 02:12:36.827 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.28.20:5700/1) Recv SETFORMAT cmd
2026-01-29 02:12:36.827 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.28.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:12:36.828 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:12:36.828 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.28.20:5700/1) Recv NOMTXPOWER cmd
2026-01-29 02:12:36.828 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.28.20:5700/1) Recv SETFORMAT cmd
2026-01-29 02:12:36.829 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.28.20:5700/1) TRXD header version 1 -> 1
2026-01-29 02:12:36.830 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.28.20:5700/2) Recv RXTUNE cmd
2026-01-29 02:12:36.830 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.28.20:5700/2) Recv TXTUNE cmd
2026-01-29 02:12:36.830 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.28.20:5700/2) Recv SETFORMAT cmd
2026-01-29 02:12:36.830 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.28.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:12:36.830 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:12:36.831 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.28.20:5700/2) Recv NOMTXPOWER cmd
2026-01-29 02:12:36.831 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.28.20:5700/2) Recv SETFORMAT cmd
2026-01-29 02:12:36.831 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.28.20:5700/2) TRXD header version 1 -> 1
2026-01-29 02:12:36.832 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.28.20:5700/3) Recv RXTUNE cmd
2026-01-29 02:12:36.832 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.28.20:5700/3) Recv TXTUNE cmd
2026-01-29 02:12:36.832 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.28.20:5700/3) Recv SETFORMAT cmd
2026-01-29 02:12:36.832 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.28.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:12:36.832 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:12:36.832 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.28.20:5700/3) Recv NOMTXPOWER cmd
2026-01-29 02:12:36.833 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.28.20:5700/3) Recv SETFORMAT cmd
2026-01-29 02:12:36.833 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.28.20:5700/3) TRXD header version 1 -> 1
2026-01-29 02:12:36.835 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.28.20:5700) Recv RXTUNE cmd
2026-01-29 02:12:36.835 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETTSC
2026-01-29 02:12:36.835 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETTSC
2026-01-29 02:12:36.835 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETTSC
2026-01-29 02:12:36.835 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.28.20:5700) Recv TXTUNE cmd
2026-01-29 02:12:36.835 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETRXGAIN
2026-01-29 02:12:36.836 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETRXGAIN
2026-01-29 02:12:36.836 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETRXGAIN
2026-01-29 02:12:36.836 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETTSC
2026-01-29 02:12:36.836 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:12:36.836 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:12:36.836 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:12:36.836 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.28.20:5700) Recv NOMTXPOWER cmd
2026-01-29 02:12:36.836 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:12:36.836 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:12:36.836 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:12:36.836 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.28.20:5700) Recv POWERON CMD
2026-01-29 02:12:36.836 [INFO] ctrl_if_trx.py:109 (BTS@172.18.28.20:5700) Starting transceiver...
2026-01-29 02:12:36.836 [INFO] transceiver.py:243 Starting clock generator
2026-01-29 02:12:36.836 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-01-29 02:12:36.836 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:12:36.836 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:12:36.836 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:12:36.836 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETRXGAIN
2026-01-29 02:12:36.837 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:12:36.837 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:12:36.837 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:12:36.837 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:12:36.837 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:12:36.837 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:12:36.837 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:12:36.837 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:12:36.837 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:12:36.837 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:12:36.837 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:12:36.837 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:12:36.837 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:12:36.837 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:12:36.837 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:12:36.838 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:12:36.838 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:12:36.838 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:12:36.838 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:12:36.838 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:12:36.838 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:12:36.838 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:12:36.838 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:12:36.841 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-01-29 02:12:37.323 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-01-29 02:12:37.368 [DEBUG] fake_trx.py:278 (BTS@172.18.28.20:5700) Recv FAKE_TOA cmd
2026-01-29 02:12:37.370 [DEBUG] fake_trx.py:297 (BTS@172.18.28.20:5700) Recv FAKE_RSSI cmd
2026-01-29 02:12:37.372 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:12:37.372 [DEBUG] fake_trx.py:322 (BTS@172.18.28.20:5700) Recv FAKE_CI cmd
2026-01-29 02:12:37.394 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 02:12:37.395 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 02:12:37.395 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 02:12:37.399 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:12:37.400 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 02:12:37.400 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 02:12:37.401 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.28.22:6700) Recv POWERON CMD
2026-01-29 02:12:37.401 [INFO] ctrl_if_trx.py:109 (MS@172.18.28.22:6700) Starting transceiver...
2026-01-29 02:12:37.420 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:12:37.426 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 02:12:37.427 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 02:12:37.427 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:12:37.428 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:12:37.801 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-01-29 02:12:37.840 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 02:12:37.840 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:12:37.842 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:12:37.844 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:12:38.280 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-01-29 02:12:38.757 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-01-29 02:12:38.841 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:12:38.841 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 02:12:38.842 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:12:38.845 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:12:39.235 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-01-29 02:12:39.529 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:12:39.532 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:12:39.536 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 02:12:39.536 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 02:12:39.549 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 02:12:39.549 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 02:12:39.549 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 02:12:39.550 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:12:39.550 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 02:12:39.550 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 02:12:39.551 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.28.22:6700) Recv POWERON CMD
2026-01-29 02:12:39.551 [INFO] ctrl_if_trx.py:109 (MS@172.18.28.22:6700) Starting transceiver...
2026-01-29 02:12:39.560 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:12:39.562 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 02:12:39.562 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 02:12:39.562 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:12:39.562 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:12:39.713 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-01-29 02:12:39.841 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:12:39.842 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 02:12:39.843 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:12:39.846 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:12:40.191 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-01-29 02:12:40.669 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-01-29 02:12:40.842 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 02:12:40.843 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:12:40.844 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:12:40.848 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:12:41.146 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-01-29 02:12:41.624 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-01-29 02:12:41.665 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:12:41.667 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:12:41.671 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 02:12:41.671 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 02:12:41.688 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 02:12:41.688 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 02:12:41.689 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 02:12:41.689 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:12:41.690 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 02:12:41.690 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 02:12:41.690 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.28.22:6700) Recv POWERON CMD
2026-01-29 02:12:41.690 [INFO] ctrl_if_trx.py:109 (MS@172.18.28.22:6700) Starting transceiver...
2026-01-29 02:12:41.722 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:12:41.727 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 02:12:41.727 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 02:12:41.728 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:12:41.728 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:12:41.843 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:12:41.843 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 02:12:41.845 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:12:41.849 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:12:42.102 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-01-29 02:12:42.580 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-01-29 02:12:43.058 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-01-29 02:12:43.535 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-01-29 02:12:43.811 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:12:43.813 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:12:43.817 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 02:12:43.817 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 02:12:43.824 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 02:12:43.824 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:12:43.824 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:12:43.824 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:12:43.828 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 02:12:43.828 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:12:43.828 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:12:43.828 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:12:43.828 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.28.20:5700) Recv POWEROFF cmd
2026-01-29 02:12:43.828 [INFO] ctrl_if_trx.py:117 (BTS@172.18.28.20:5700) Stopping transceiver...
2026-01-29 02:12:43.829 [INFO] transceiver.py:246 Stopping clock generator
2026-01-29 02:12:43.829 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=1493 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:12:43.829 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=1493 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:12:43.829 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=1493 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:12:43.829 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=1493 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:12:43.829 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=1493 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:12:43.829 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=1493 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:12:48.828 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.28.20:5700) Recv POWEROFF cmd
2026-01-29 02:12:48.828 [INFO] ctrl_if_trx.py:117 (BTS@172.18.28.20:5700) Stopping transceiver...
2026-01-29 02:12:48.830 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:12:48.830 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:12:48.831 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:12:48.831 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 02:12:48.838 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 02:12:48.839 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.28.20:5700) Recv SETFORMAT cmd
2026-01-29 02:12:48.839 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.28.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:12:48.839 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.28.20:5700) Recv SETFORMAT cmd
2026-01-29 02:12:48.840 [INFO] ctrl_if_trx.py:201 (BTS@172.18.28.20:5700) TRXD header version 1 -> 1
2026-01-29 02:12:48.841 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.28.20:5700/1) Recv RXTUNE cmd
2026-01-29 02:12:48.842 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.28.20:5700/1) Recv TXTUNE cmd
2026-01-29 02:12:48.842 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.28.20:5700/1) Recv SETFORMAT cmd
2026-01-29 02:12:48.842 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.28.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:12:48.842 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:12:48.842 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.28.20:5700/1) Recv NOMTXPOWER cmd
2026-01-29 02:12:48.843 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.28.20:5700/1) Recv SETFORMAT cmd
2026-01-29 02:12:48.843 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.28.20:5700/1) TRXD header version 1 -> 1
2026-01-29 02:12:48.844 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.28.20:5700/2) Recv RXTUNE cmd
2026-01-29 02:12:48.844 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.28.20:5700/2) Recv TXTUNE cmd
2026-01-29 02:12:48.844 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.28.20:5700/2) Recv SETFORMAT cmd
2026-01-29 02:12:48.844 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.28.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:12:48.844 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:12:48.844 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.28.20:5700/2) Recv NOMTXPOWER cmd
2026-01-29 02:12:48.844 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.28.20:5700/2) Recv SETFORMAT cmd
2026-01-29 02:12:48.844 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.28.20:5700/2) TRXD header version 1 -> 1
2026-01-29 02:12:48.846 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.28.20:5700/3) Recv RXTUNE cmd
2026-01-29 02:12:48.846 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.28.20:5700/3) Recv TXTUNE cmd
2026-01-29 02:12:48.846 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.28.20:5700/3) Recv SETFORMAT cmd
2026-01-29 02:12:48.846 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.28.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:12:48.846 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:12:48.846 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.28.20:5700/3) Recv NOMTXPOWER cmd
2026-01-29 02:12:48.846 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.28.20:5700/3) Recv SETFORMAT cmd
2026-01-29 02:12:48.846 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.28.20:5700/3) TRXD header version 1 -> 1
2026-01-29 02:12:48.849 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.28.20:5700) Recv RXTUNE cmd
2026-01-29 02:12:48.849 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETTSC
2026-01-29 02:12:48.849 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETTSC
2026-01-29 02:12:48.849 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETTSC
2026-01-29 02:12:48.849 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.28.20:5700) Recv TXTUNE cmd
2026-01-29 02:12:48.849 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETRXGAIN
2026-01-29 02:12:48.849 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETRXGAIN
2026-01-29 02:12:48.849 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETRXGAIN
2026-01-29 02:12:48.849 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETTSC
2026-01-29 02:12:48.849 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:12:48.849 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:12:48.849 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.28.20:5700) Recv NOMTXPOWER cmd
2026-01-29 02:12:48.849 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:12:48.849 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:12:48.849 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:12:48.849 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.28.20:5700) Recv POWERON CMD
2026-01-29 02:12:48.849 [INFO] ctrl_if_trx.py:109 (BTS@172.18.28.20:5700) Starting transceiver...
2026-01-29 02:12:48.849 [INFO] transceiver.py:243 Starting clock generator
2026-01-29 02:12:48.849 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-01-29 02:12:48.849 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:12:48.849 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:12:48.849 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:12:48.849 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETRXGAIN
2026-01-29 02:12:48.849 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:12:48.850 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:12:48.850 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:12:48.850 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:12:48.850 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:12:48.850 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:12:48.850 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:12:48.850 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:12:48.850 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:12:48.850 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:12:48.850 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:12:48.850 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:12:48.850 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:12:48.850 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:12:48.850 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:12:48.850 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:12:48.850 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:12:48.850 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:12:48.850 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:12:48.850 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:12:48.850 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:12:48.850 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:12:48.850 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:12:48.850 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:12:48.854 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-01-29 02:12:49.338 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-01-29 02:12:49.374 [DEBUG] fake_trx.py:278 (BTS@172.18.28.20:5700) Recv FAKE_TOA cmd
2026-01-29 02:12:49.375 [DEBUG] fake_trx.py:297 (BTS@172.18.28.20:5700) Recv FAKE_RSSI cmd
2026-01-29 02:12:49.376 [DEBUG] fake_trx.py:322 (BTS@172.18.28.20:5700) Recv FAKE_CI cmd
2026-01-29 02:12:49.376 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:12:49.390 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 02:12:49.390 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 02:12:49.390 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 02:12:49.394 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:12:49.395 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 02:12:49.395 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 02:12:49.395 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.28.22:6700) Recv POWERON CMD
2026-01-29 02:12:49.395 [INFO] ctrl_if_trx.py:109 (MS@172.18.28.22:6700) Starting transceiver...
2026-01-29 02:12:49.434 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:12:49.440 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 02:12:49.440 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 02:12:49.441 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:12:49.441 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:12:49.815 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-01-29 02:12:49.852 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 02:12:49.853 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:12:49.853 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:12:49.856 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:12:50.293 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-01-29 02:12:50.771 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-01-29 02:12:50.854 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 02:12:50.854 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:12:50.854 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:12:50.858 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:12:51.249 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-01-29 02:12:51.539 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:12:51.542 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:12:51.547 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 02:12:51.547 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 02:12:51.563 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 02:12:51.563 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 02:12:51.563 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 02:12:51.565 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:12:51.565 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 02:12:51.565 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 02:12:51.565 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.28.22:6700) Recv POWERON CMD
2026-01-29 02:12:51.565 [INFO] ctrl_if_trx.py:109 (MS@172.18.28.22:6700) Starting transceiver...
2026-01-29 02:12:51.574 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:12:51.575 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 02:12:51.575 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 02:12:51.576 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:12:51.576 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:12:51.726 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-01-29 02:12:51.855 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:12:51.855 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:12:51.855 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 02:12:51.859 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:12:52.204 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-01-29 02:12:52.682 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-01-29 02:12:52.856 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 02:12:52.856 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:12:52.857 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:12:52.860 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:12:53.160 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-01-29 02:12:53.637 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-01-29 02:12:53.674 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:12:53.676 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:12:53.682 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 02:12:53.682 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 02:12:53.689 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 02:12:53.689 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:12:53.689 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:12:53.689 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:12:53.690 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 02:12:53.690 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:12:53.690 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:12:53.690 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:12:53.690 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.28.20:5700) Recv POWEROFF cmd
2026-01-29 02:12:53.690 [INFO] ctrl_if_trx.py:117 (BTS@172.18.28.20:5700) Stopping transceiver...
2026-01-29 02:12:53.691 [INFO] transceiver.py:246 Stopping clock generator
2026-01-29 02:12:53.691 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=1033 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:12:53.691 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=1033 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:12:53.691 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=1033 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:12:53.691 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=1033 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:12:53.691 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=1033 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:12:53.691 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=1033 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:12:53.691 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=1033 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:12:53.691 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=1033 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:12:58.693 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.28.20:5700) Recv POWEROFF cmd
2026-01-29 02:12:58.693 [INFO] ctrl_if_trx.py:117 (BTS@172.18.28.20:5700) Stopping transceiver...
2026-01-29 02:12:58.696 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:12:58.696 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:12:58.696 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 02:12:58.696 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:12:58.703 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 02:12:58.704 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.28.20:5700) Recv SETFORMAT cmd
2026-01-29 02:12:58.704 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.28.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:12:58.705 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.28.20:5700) Recv SETFORMAT cmd
2026-01-29 02:12:58.705 [INFO] ctrl_if_trx.py:201 (BTS@172.18.28.20:5700) TRXD header version 1 -> 1
2026-01-29 02:12:58.707 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.28.20:5700/1) Recv RXTUNE cmd
2026-01-29 02:12:58.707 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.28.20:5700/1) Recv TXTUNE cmd
2026-01-29 02:12:58.708 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.28.20:5700/1) Recv SETFORMAT cmd
2026-01-29 02:12:58.708 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.28.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:12:58.708 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:12:58.708 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.28.20:5700/1) Recv NOMTXPOWER cmd
2026-01-29 02:12:58.709 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.28.20:5700/1) Recv SETFORMAT cmd
2026-01-29 02:12:58.709 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.28.20:5700/1) TRXD header version 1 -> 1
2026-01-29 02:12:58.709 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.28.20:5700/2) Recv RXTUNE cmd
2026-01-29 02:12:58.710 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.28.20:5700/2) Recv TXTUNE cmd
2026-01-29 02:12:58.710 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.28.20:5700/2) Recv SETFORMAT cmd
2026-01-29 02:12:58.710 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.28.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:12:58.710 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:12:58.710 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.28.20:5700/2) Recv NOMTXPOWER cmd
2026-01-29 02:12:58.710 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.28.20:5700/2) Recv SETFORMAT cmd
2026-01-29 02:12:58.710 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.28.20:5700/2) TRXD header version 1 -> 1
2026-01-29 02:12:58.712 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.28.20:5700/3) Recv RXTUNE cmd
2026-01-29 02:12:58.712 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.28.20:5700/3) Recv TXTUNE cmd
2026-01-29 02:12:58.712 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.28.20:5700/3) Recv SETFORMAT cmd
2026-01-29 02:12:58.712 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.28.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:12:58.712 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:12:58.712 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.28.20:5700/3) Recv NOMTXPOWER cmd
2026-01-29 02:12:58.712 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.28.20:5700/3) Recv SETFORMAT cmd
2026-01-29 02:12:58.712 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.28.20:5700/3) TRXD header version 1 -> 1
2026-01-29 02:12:58.715 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.28.20:5700) Recv RXTUNE cmd
2026-01-29 02:12:58.715 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETTSC
2026-01-29 02:12:58.715 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETTSC
2026-01-29 02:12:58.715 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETTSC
2026-01-29 02:12:58.715 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.28.20:5700) Recv TXTUNE cmd
2026-01-29 02:12:58.715 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETRXGAIN
2026-01-29 02:12:58.715 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETRXGAIN
2026-01-29 02:12:58.715 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETRXGAIN
2026-01-29 02:12:58.715 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETTSC
2026-01-29 02:12:58.715 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:12:58.715 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:12:58.715 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:12:58.715 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.28.20:5700) Recv NOMTXPOWER cmd
2026-01-29 02:12:58.715 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:12:58.715 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:12:58.715 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:12:58.715 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.28.20:5700) Recv POWERON CMD
2026-01-29 02:12:58.715 [INFO] ctrl_if_trx.py:109 (BTS@172.18.28.20:5700) Starting transceiver...
2026-01-29 02:12:58.715 [INFO] transceiver.py:243 Starting clock generator
2026-01-29 02:12:58.715 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-01-29 02:12:58.715 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:12:58.716 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:12:58.716 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:12:58.716 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETRXGAIN
2026-01-29 02:12:58.716 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:12:58.716 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:12:58.716 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:12:58.716 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:12:58.716 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:12:58.716 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:12:58.716 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:12:58.716 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:12:58.716 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:12:58.716 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:12:58.716 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:12:58.716 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:12:58.716 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:12:58.716 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:12:58.716 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:12:58.716 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:12:58.716 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:12:58.716 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:12:58.716 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:12:58.716 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:12:58.717 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:12:58.717 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:12:58.717 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:12:58.720 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-01-29 02:12:59.204 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-01-29 02:12:59.242 [DEBUG] fake_trx.py:278 (BTS@172.18.28.20:5700) Recv FAKE_TOA cmd
2026-01-29 02:12:59.244 [DEBUG] fake_trx.py:297 (BTS@172.18.28.20:5700) Recv FAKE_RSSI cmd
2026-01-29 02:12:59.245 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:12:59.246 [DEBUG] fake_trx.py:322 (BTS@172.18.28.20:5700) Recv FAKE_CI cmd
2026-01-29 02:12:59.260 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 02:12:59.260 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 02:12:59.260 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 02:12:59.264 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:12:59.264 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 02:12:59.265 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 02:12:59.265 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.28.22:6700) Recv POWERON CMD
2026-01-29 02:12:59.265 [INFO] ctrl_if_trx.py:109 (MS@172.18.28.22:6700) Starting transceiver...
2026-01-29 02:12:59.300 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:12:59.306 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 02:12:59.306 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 02:12:59.307 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:12:59.307 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:12:59.682 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-01-29 02:12:59.719 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:12:59.719 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 02:12:59.720 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:12:59.724 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:13:00.160 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-01-29 02:13:00.637 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-01-29 02:13:00.720 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 02:13:00.720 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:13:00.721 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:13:00.725 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:13:01.115 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-01-29 02:13:01.386 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:13:01.388 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:13:01.394 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 02:13:01.395 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 02:13:01.412 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 02:13:01.412 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 02:13:01.412 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 02:13:01.413 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:13:01.413 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 02:13:01.413 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 02:13:01.413 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.28.22:6700) Recv POWERON CMD
2026-01-29 02:13:01.413 [INFO] ctrl_if_trx.py:109 (MS@172.18.28.22:6700) Starting transceiver...
2026-01-29 02:13:01.445 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:13:01.450 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 02:13:01.451 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 02:13:01.451 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:13:01.451 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:13:01.592 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-01-29 02:13:01.721 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 02:13:01.722 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:13:01.722 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:13:01.726 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:13:02.070 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-01-29 02:13:02.548 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-01-29 02:13:02.722 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 02:13:02.722 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:13:02.723 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:13:02.727 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:13:03.026 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-01-29 02:13:03.505 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-01-29 02:13:03.524 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:13:03.526 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:13:03.530 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 02:13:03.531 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 02:13:03.546 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 02:13:03.546 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 02:13:03.546 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 02:13:03.547 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:13:03.547 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 02:13:03.547 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 02:13:03.547 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.28.22:6700) Recv POWERON CMD
2026-01-29 02:13:03.547 [INFO] ctrl_if_trx.py:109 (MS@172.18.28.22:6700) Starting transceiver...
2026-01-29 02:13:03.602 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:13:03.607 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 02:13:03.608 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 02:13:03.608 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:13:03.608 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:13:03.723 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 02:13:03.723 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:13:03.723 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:13:03.728 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:13:03.983 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-01-29 02:13:04.461 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-01-29 02:13:04.939 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-01-29 02:13:05.416 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-01-29 02:13:05.713 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:13:05.715 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:13:05.720 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 02:13:05.720 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 02:13:05.731 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 02:13:05.731 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:13:05.732 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:13:05.732 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:13:05.737 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 02:13:05.737 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:13:05.737 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:13:05.737 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:13:05.738 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.28.20:5700) Recv POWEROFF cmd
2026-01-29 02:13:05.738 [INFO] ctrl_if_trx.py:117 (BTS@172.18.28.20:5700) Stopping transceiver...
2026-01-29 02:13:05.738 [INFO] transceiver.py:246 Stopping clock generator
2026-01-29 02:13:05.738 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=1499 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:13:05.738 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=1499 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:13:05.738 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=1499 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:13:05.739 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=1499 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:13:05.739 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=1499 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:13:05.739 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=1499 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:13:05.739 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=1499 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:13:05.739 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=1499 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:13:10.732 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.28.20:5700) Recv POWEROFF cmd
2026-01-29 02:13:10.733 [INFO] ctrl_if_trx.py:117 (BTS@172.18.28.20:5700) Stopping transceiver...
2026-01-29 02:13:10.734 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:13:10.736 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:13:10.736 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:13:10.737 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 02:13:10.743 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 02:13:10.744 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.28.20:5700) Recv SETFORMAT cmd
2026-01-29 02:13:10.744 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.28.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:13:10.744 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.28.20:5700) Recv SETFORMAT cmd
2026-01-29 02:13:10.744 [INFO] ctrl_if_trx.py:201 (BTS@172.18.28.20:5700) TRXD header version 1 -> 1
2026-01-29 02:13:10.746 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.28.20:5700/1) Recv RXTUNE cmd
2026-01-29 02:13:10.747 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.28.20:5700/1) Recv TXTUNE cmd
2026-01-29 02:13:10.747 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.28.20:5700/1) Recv SETFORMAT cmd
2026-01-29 02:13:10.747 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.28.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:13:10.747 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:13:10.748 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.28.20:5700/1) Recv NOMTXPOWER cmd
2026-01-29 02:13:10.748 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.28.20:5700/1) Recv SETFORMAT cmd
2026-01-29 02:13:10.748 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.28.20:5700/1) TRXD header version 1 -> 1
2026-01-29 02:13:10.749 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.28.20:5700/2) Recv RXTUNE cmd
2026-01-29 02:13:10.749 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.28.20:5700/2) Recv TXTUNE cmd
2026-01-29 02:13:10.749 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.28.20:5700/2) Recv SETFORMAT cmd
2026-01-29 02:13:10.749 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.28.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:13:10.749 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:13:10.749 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.28.20:5700/2) Recv NOMTXPOWER cmd
2026-01-29 02:13:10.749 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.28.20:5700/2) Recv SETFORMAT cmd
2026-01-29 02:13:10.749 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.28.20:5700/2) TRXD header version 1 -> 1
2026-01-29 02:13:10.751 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.28.20:5700/3) Recv RXTUNE cmd
2026-01-29 02:13:10.751 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.28.20:5700/3) Recv TXTUNE cmd
2026-01-29 02:13:10.751 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.28.20:5700/3) Recv SETFORMAT cmd
2026-01-29 02:13:10.751 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.28.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:13:10.751 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:13:10.751 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.28.20:5700/3) Recv NOMTXPOWER cmd
2026-01-29 02:13:10.751 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.28.20:5700/3) Recv SETFORMAT cmd
2026-01-29 02:13:10.751 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.28.20:5700/3) TRXD header version 1 -> 1
2026-01-29 02:13:10.754 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.28.20:5700) Recv RXTUNE cmd
2026-01-29 02:13:10.754 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETTSC
2026-01-29 02:13:10.754 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETTSC
2026-01-29 02:13:10.754 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETTSC
2026-01-29 02:13:10.754 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.28.20:5700) Recv TXTUNE cmd
2026-01-29 02:13:10.754 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETRXGAIN
2026-01-29 02:13:10.754 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETRXGAIN
2026-01-29 02:13:10.754 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETRXGAIN
2026-01-29 02:13:10.754 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETTSC
2026-01-29 02:13:10.754 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:13:10.754 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:13:10.754 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:13:10.754 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.28.20:5700) Recv NOMTXPOWER cmd
2026-01-29 02:13:10.754 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:13:10.754 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:13:10.754 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:13:10.754 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.28.20:5700) Recv POWERON CMD
2026-01-29 02:13:10.754 [INFO] ctrl_if_trx.py:109 (BTS@172.18.28.20:5700) Starting transceiver...
2026-01-29 02:13:10.754 [INFO] transceiver.py:243 Starting clock generator
2026-01-29 02:13:10.754 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-01-29 02:13:10.755 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:13:10.755 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:13:10.755 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:13:10.755 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETRXGAIN
2026-01-29 02:13:10.755 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:13:10.755 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:13:10.755 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:13:10.755 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:13:10.755 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:13:10.755 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:13:10.755 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:13:10.755 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:13:10.755 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:13:10.755 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:13:10.755 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:13:10.755 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:13:10.755 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:13:10.755 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:13:10.755 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:13:10.755 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:13:10.755 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:13:10.755 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:13:10.755 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:13:10.755 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:13:10.756 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:13:10.756 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:13:10.756 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:13:10.759 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-01-29 02:13:11.244 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-01-29 02:13:11.283 [DEBUG] fake_trx.py:278 (BTS@172.18.28.20:5700) Recv FAKE_TOA cmd
2026-01-29 02:13:11.284 [DEBUG] fake_trx.py:297 (BTS@172.18.28.20:5700) Recv FAKE_RSSI cmd
2026-01-29 02:13:11.285 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:13:11.285 [DEBUG] fake_trx.py:322 (BTS@172.18.28.20:5700) Recv FAKE_CI cmd
2026-01-29 02:13:11.297 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 02:13:11.297 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 02:13:11.297 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 02:13:11.300 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:13:11.300 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 02:13:11.300 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 02:13:11.300 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.28.22:6700) Recv POWERON CMD
2026-01-29 02:13:11.300 [INFO] ctrl_if_trx.py:109 (MS@172.18.28.22:6700) Starting transceiver...
2026-01-29 02:13:11.340 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:13:11.346 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 02:13:11.346 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 02:13:11.347 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:13:11.347 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:13:11.721 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-01-29 02:13:11.758 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:13:11.759 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 02:13:11.760 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:13:11.763 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:13:12.199 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-01-29 02:13:12.677 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-01-29 02:13:12.759 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:13:12.760 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 02:13:12.761 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:13:12.764 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:13:13.155 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-01-29 02:13:13.466 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:13:13.469 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:13:13.476 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 02:13:13.476 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 02:13:13.494 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 02:13:13.494 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 02:13:13.494 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 02:13:13.495 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:13:13.495 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 02:13:13.495 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 02:13:13.495 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.28.22:6700) Recv POWERON CMD
2026-01-29 02:13:13.495 [INFO] ctrl_if_trx.py:109 (MS@172.18.28.22:6700) Starting transceiver...
2026-01-29 02:13:13.532 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:13:13.535 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 02:13:13.536 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 02:13:13.536 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:13:13.537 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:13:13.633 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-01-29 02:13:13.760 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 02:13:13.760 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:13:13.762 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:13:13.766 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:13:14.111 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-01-29 02:13:14.588 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-01-29 02:13:14.761 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:13:14.761 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 02:13:14.763 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:13:14.767 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:13:15.066 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-01-29 02:13:15.544 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-01-29 02:13:15.642 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:13:15.644 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:13:15.649 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 02:13:15.649 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 02:13:15.656 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 02:13:15.656 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:13:15.656 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:13:15.656 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:13:15.657 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 02:13:15.657 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:13:15.657 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:13:15.657 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.28.20:5700) Recv POWEROFF cmd
2026-01-29 02:13:15.657 [INFO] ctrl_if_trx.py:117 (BTS@172.18.28.20:5700) Stopping transceiver...
2026-01-29 02:13:15.657 [INFO] transceiver.py:246 Stopping clock generator
2026-01-29 02:13:15.657 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:13:15.657 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=1046 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:13:15.657 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=1046 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:13:15.657 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=1046 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:13:15.657 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=1046 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:13:15.658 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=1046 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:13:15.658 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=1046 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:13:15.658 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=1046 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:13:15.658 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=1046 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:13:20.662 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.28.20:5700) Recv POWEROFF cmd
2026-01-29 02:13:20.662 [INFO] ctrl_if_trx.py:117 (BTS@172.18.28.20:5700) Stopping transceiver...
2026-01-29 02:13:20.663 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:13:20.663 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:13:20.663 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:13:20.663 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 02:13:20.665 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 02:13:20.665 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.28.20:5700) Recv SETFORMAT cmd
2026-01-29 02:13:20.665 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.28.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:13:20.665 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.28.20:5700) Recv SETFORMAT cmd
2026-01-29 02:13:20.665 [INFO] ctrl_if_trx.py:201 (BTS@172.18.28.20:5700) TRXD header version 1 -> 1
2026-01-29 02:13:20.666 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.28.20:5700/1) Recv RXTUNE cmd
2026-01-29 02:13:20.666 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.28.20:5700/1) Recv TXTUNE cmd
2026-01-29 02:13:20.666 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.28.20:5700/1) Recv SETFORMAT cmd
2026-01-29 02:13:20.666 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.28.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:13:20.666 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:13:20.666 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.28.20:5700/1) Recv NOMTXPOWER cmd
2026-01-29 02:13:20.667 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.28.20:5700/1) Recv SETFORMAT cmd
2026-01-29 02:13:20.667 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.28.20:5700/1) TRXD header version 1 -> 1
2026-01-29 02:13:20.667 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.28.20:5700/2) Recv RXTUNE cmd
2026-01-29 02:13:20.667 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.28.20:5700/2) Recv TXTUNE cmd
2026-01-29 02:13:20.667 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.28.20:5700/2) Recv SETFORMAT cmd
2026-01-29 02:13:20.667 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.28.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:13:20.667 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:13:20.667 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.28.20:5700/2) Recv NOMTXPOWER cmd
2026-01-29 02:13:20.667 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.28.20:5700/2) Recv SETFORMAT cmd
2026-01-29 02:13:20.667 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.28.20:5700/2) TRXD header version 1 -> 1
2026-01-29 02:13:20.668 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.28.20:5700/3) Recv RXTUNE cmd
2026-01-29 02:13:20.668 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.28.20:5700/3) Recv TXTUNE cmd
2026-01-29 02:13:20.668 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.28.20:5700/3) Recv SETFORMAT cmd
2026-01-29 02:13:20.668 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.28.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:13:20.668 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:13:20.668 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.28.20:5700/3) Recv NOMTXPOWER cmd
2026-01-29 02:13:20.668 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.28.20:5700/3) Recv SETFORMAT cmd
2026-01-29 02:13:20.668 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.28.20:5700/3) TRXD header version 1 -> 1
2026-01-29 02:13:20.670 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.28.20:5700) Recv RXTUNE cmd
2026-01-29 02:13:20.670 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETTSC
2026-01-29 02:13:20.670 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETTSC
2026-01-29 02:13:20.670 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETTSC
2026-01-29 02:13:20.670 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.28.20:5700) Recv TXTUNE cmd
2026-01-29 02:13:20.670 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETRXGAIN
2026-01-29 02:13:20.670 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETRXGAIN
2026-01-29 02:13:20.670 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETRXGAIN
2026-01-29 02:13:20.670 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETTSC
2026-01-29 02:13:20.670 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:13:20.670 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:13:20.670 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.28.20:5700) Recv NOMTXPOWER cmd
2026-01-29 02:13:20.670 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:13:20.670 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:13:20.670 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:13:20.670 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.28.20:5700) Recv POWERON CMD
2026-01-29 02:13:20.670 [INFO] ctrl_if_trx.py:109 (BTS@172.18.28.20:5700) Starting transceiver...
2026-01-29 02:13:20.670 [INFO] transceiver.py:243 Starting clock generator
2026-01-29 02:13:20.670 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-01-29 02:13:20.670 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:13:20.670 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:13:20.670 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:13:20.670 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETRXGAIN
2026-01-29 02:13:20.670 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:13:20.670 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:13:20.670 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:13:20.670 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:13:20.670 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:13:20.670 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:13:20.670 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:13:20.670 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:13:20.670 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:13:20.670 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:13:20.670 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:13:20.670 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:13:20.670 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:13:20.671 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:13:20.671 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:13:20.671 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:13:20.671 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:13:20.671 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:13:20.671 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:13:20.671 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:13:20.671 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:13:20.671 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:13:20.671 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:13:20.671 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:13:20.675 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-01-29 02:13:21.157 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-01-29 02:13:21.193 [DEBUG] fake_trx.py:278 (BTS@172.18.28.20:5700) Recv FAKE_TOA cmd
2026-01-29 02:13:21.194 [DEBUG] fake_trx.py:297 (BTS@172.18.28.20:5700) Recv FAKE_RSSI cmd
2026-01-29 02:13:21.195 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:13:21.196 [DEBUG] fake_trx.py:322 (BTS@172.18.28.20:5700) Recv FAKE_CI cmd
2026-01-29 02:13:21.208 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 02:13:21.208 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 02:13:21.208 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 02:13:21.212 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:13:21.212 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 02:13:21.212 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 02:13:21.212 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.28.22:6700) Recv POWERON CMD
2026-01-29 02:13:21.212 [INFO] ctrl_if_trx.py:109 (MS@172.18.28.22:6700) Starting transceiver...
2026-01-29 02:13:21.256 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:13:21.262 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 02:13:21.263 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 02:13:21.264 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:13:21.264 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:13:21.635 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-01-29 02:13:21.672 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 02:13:21.673 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:13:21.673 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:13:21.675 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:13:22.113 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-01-29 02:13:22.591 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-01-29 02:13:22.673 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 02:13:22.674 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:13:22.674 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:13:22.677 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:13:23.069 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-01-29 02:13:23.445 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:13:23.447 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:13:23.450 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 02:13:23.450 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 02:13:23.460 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 02:13:23.460 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:13:23.460 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:13:23.460 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:13:23.466 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 02:13:23.466 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:13:23.466 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:13:23.466 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.28.20:5700) Recv POWEROFF cmd
2026-01-29 02:13:23.466 [INFO] ctrl_if_trx.py:117 (BTS@172.18.28.20:5700) Stopping transceiver...
2026-01-29 02:13:23.467 [INFO] transceiver.py:246 Stopping clock generator
2026-01-29 02:13:23.467 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:13:23.467 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=596 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:13:23.467 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=596 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:13:28.464 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.28.20:5700) Recv POWEROFF cmd
2026-01-29 02:13:28.464 [INFO] ctrl_if_trx.py:117 (BTS@172.18.28.20:5700) Stopping transceiver...
2026-01-29 02:13:28.466 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:13:28.470 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:13:28.470 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:13:28.471 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 02:13:28.478 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 02:13:28.479 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.28.20:5700) Recv SETFORMAT cmd
2026-01-29 02:13:28.479 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.28.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:13:28.479 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.28.20:5700) Recv SETFORMAT cmd
2026-01-29 02:13:28.479 [INFO] ctrl_if_trx.py:201 (BTS@172.18.28.20:5700) TRXD header version 1 -> 1
2026-01-29 02:13:28.482 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.28.20:5700/1) Recv RXTUNE cmd
2026-01-29 02:13:28.482 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.28.20:5700/1) Recv TXTUNE cmd
2026-01-29 02:13:28.483 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.28.20:5700/1) Recv SETFORMAT cmd
2026-01-29 02:13:28.483 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.28.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:13:28.483 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:13:28.483 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.28.20:5700/1) Recv NOMTXPOWER cmd
2026-01-29 02:13:28.484 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.28.20:5700/1) Recv SETFORMAT cmd
2026-01-29 02:13:28.484 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.28.20:5700/1) TRXD header version 1 -> 1
2026-01-29 02:13:28.484 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.28.20:5700/2) Recv RXTUNE cmd
2026-01-29 02:13:28.485 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.28.20:5700/2) Recv TXTUNE cmd
2026-01-29 02:13:28.485 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.28.20:5700/2) Recv SETFORMAT cmd
2026-01-29 02:13:28.485 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.28.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:13:28.485 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:13:28.485 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.28.20:5700/2) Recv NOMTXPOWER cmd
2026-01-29 02:13:28.485 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.28.20:5700/2) Recv SETFORMAT cmd
2026-01-29 02:13:28.485 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.28.20:5700/2) TRXD header version 1 -> 1
2026-01-29 02:13:28.487 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.28.20:5700/3) Recv RXTUNE cmd
2026-01-29 02:13:28.487 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.28.20:5700/3) Recv TXTUNE cmd
2026-01-29 02:13:28.487 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.28.20:5700/3) Recv SETFORMAT cmd
2026-01-29 02:13:28.487 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.28.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:13:28.488 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:13:28.488 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.28.20:5700/3) Recv NOMTXPOWER cmd
2026-01-29 02:13:28.488 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.28.20:5700/3) Recv SETFORMAT cmd
2026-01-29 02:13:28.488 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.28.20:5700/3) TRXD header version 1 -> 1
2026-01-29 02:13:28.490 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.28.20:5700) Recv RXTUNE cmd
2026-01-29 02:13:28.490 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETTSC
2026-01-29 02:13:28.490 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETTSC
2026-01-29 02:13:28.490 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETTSC
2026-01-29 02:13:28.490 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.28.20:5700) Recv TXTUNE cmd
2026-01-29 02:13:28.490 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETRXGAIN
2026-01-29 02:13:28.490 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETRXGAIN
2026-01-29 02:13:28.490 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETRXGAIN
2026-01-29 02:13:28.491 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETTSC
2026-01-29 02:13:28.491 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:13:28.491 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:13:28.491 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:13:28.491 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.28.20:5700) Recv NOMTXPOWER cmd
2026-01-29 02:13:28.491 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:13:28.491 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:13:28.491 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:13:28.491 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.28.20:5700) Recv POWERON CMD
2026-01-29 02:13:28.491 [INFO] ctrl_if_trx.py:109 (BTS@172.18.28.20:5700) Starting transceiver...
2026-01-29 02:13:28.491 [INFO] transceiver.py:243 Starting clock generator
2026-01-29 02:13:28.491 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-01-29 02:13:28.491 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:13:28.491 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:13:28.491 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:13:28.491 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETRXGAIN
2026-01-29 02:13:28.491 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:13:28.491 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:13:28.491 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:13:28.491 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:13:28.491 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:13:28.491 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:13:28.491 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:13:28.491 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:13:28.491 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:13:28.491 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:13:28.491 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:13:28.491 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:13:28.492 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:13:28.492 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:13:28.492 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:13:28.492 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:13:28.492 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:13:28.492 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:13:28.492 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:13:28.492 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:13:28.492 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:13:28.492 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:13:28.492 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:13:28.496 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-01-29 02:13:28.979 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-01-29 02:13:29.020 [DEBUG] fake_trx.py:278 (BTS@172.18.28.20:5700) Recv FAKE_TOA cmd
2026-01-29 02:13:29.022 [DEBUG] fake_trx.py:297 (BTS@172.18.28.20:5700) Recv FAKE_RSSI cmd
2026-01-29 02:13:29.024 [DEBUG] fake_trx.py:322 (BTS@172.18.28.20:5700) Recv FAKE_CI cmd
2026-01-29 02:13:29.024 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:13:29.047 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 02:13:29.047 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 02:13:29.047 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 02:13:29.051 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:13:29.052 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 02:13:29.052 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 02:13:29.052 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.28.22:6700) Recv POWERON CMD
2026-01-29 02:13:29.053 [INFO] ctrl_if_trx.py:109 (MS@172.18.28.22:6700) Starting transceiver...
2026-01-29 02:13:29.079 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:13:29.085 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 02:13:29.086 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 02:13:29.086 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:13:29.087 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:13:29.456 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-01-29 02:13:29.494 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 02:13:29.494 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:13:29.495 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:13:29.497 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:13:29.935 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-01-29 02:13:30.412 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-01-29 02:13:30.495 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 02:13:30.495 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:13:30.495 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:13:30.497 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:13:30.890 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-01-29 02:13:31.280 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:13:31.282 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:13:31.286 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 02:13:31.286 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 02:13:31.297 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 02:13:31.297 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:13:31.297 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:13:31.297 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:13:31.298 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 02:13:31.298 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:13:31.298 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:13:31.298 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.28.20:5700) Recv POWEROFF cmd
2026-01-29 02:13:31.298 [INFO] ctrl_if_trx.py:117 (BTS@172.18.28.20:5700) Stopping transceiver...
2026-01-29 02:13:31.298 [INFO] transceiver.py:246 Stopping clock generator
2026-01-29 02:13:31.299 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:13:31.299 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=599 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:13:31.299 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=599 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:13:31.299 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=599 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:13:31.299 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=599 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:13:31.299 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=599 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:13:36.301 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.28.20:5700) Recv POWEROFF cmd
2026-01-29 02:13:36.301 [INFO] ctrl_if_trx.py:117 (BTS@172.18.28.20:5700) Stopping transceiver...
2026-01-29 02:13:36.303 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:13:36.304 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:13:36.305 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:13:36.306 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 02:13:36.312 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 02:13:36.314 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.28.20:5700) Recv SETFORMAT cmd
2026-01-29 02:13:36.314 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.28.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:13:36.314 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.28.20:5700) Recv SETFORMAT cmd
2026-01-29 02:13:36.314 [INFO] ctrl_if_trx.py:201 (BTS@172.18.28.20:5700) TRXD header version 1 -> 1
2026-01-29 02:13:36.318 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.28.20:5700/1) Recv RXTUNE cmd
2026-01-29 02:13:36.319 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.28.20:5700/1) Recv TXTUNE cmd
2026-01-29 02:13:36.319 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.28.20:5700/1) Recv SETFORMAT cmd
2026-01-29 02:13:36.319 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.28.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:13:36.320 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:13:36.320 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.28.20:5700/1) Recv NOMTXPOWER cmd
2026-01-29 02:13:36.320 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.28.20:5700/1) Recv SETFORMAT cmd
2026-01-29 02:13:36.320 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.28.20:5700/1) TRXD header version 1 -> 1
2026-01-29 02:13:36.321 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.28.20:5700/2) Recv RXTUNE cmd
2026-01-29 02:13:36.321 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.28.20:5700/2) Recv TXTUNE cmd
2026-01-29 02:13:36.322 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.28.20:5700/2) Recv SETFORMAT cmd
2026-01-29 02:13:36.322 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.28.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:13:36.322 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:13:36.322 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.28.20:5700/2) Recv NOMTXPOWER cmd
2026-01-29 02:13:36.322 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.28.20:5700/2) Recv SETFORMAT cmd
2026-01-29 02:13:36.322 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.28.20:5700/2) TRXD header version 1 -> 1
2026-01-29 02:13:36.325 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.28.20:5700/3) Recv RXTUNE cmd
2026-01-29 02:13:36.325 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.28.20:5700/3) Recv TXTUNE cmd
2026-01-29 02:13:36.325 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.28.20:5700/3) Recv SETFORMAT cmd
2026-01-29 02:13:36.325 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.28.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:13:36.325 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:13:36.325 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.28.20:5700/3) Recv NOMTXPOWER cmd
2026-01-29 02:13:36.325 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.28.20:5700/3) Recv SETFORMAT cmd
2026-01-29 02:13:36.325 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.28.20:5700/3) TRXD header version 1 -> 1
2026-01-29 02:13:36.328 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.28.20:5700) Recv RXTUNE cmd
2026-01-29 02:13:36.328 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETTSC
2026-01-29 02:13:36.328 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETTSC
2026-01-29 02:13:36.328 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETTSC
2026-01-29 02:13:36.328 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.28.20:5700) Recv TXTUNE cmd
2026-01-29 02:13:36.328 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETRXGAIN
2026-01-29 02:13:36.328 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETRXGAIN
2026-01-29 02:13:36.328 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETRXGAIN
2026-01-29 02:13:36.328 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETTSC
2026-01-29 02:13:36.328 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:13:36.328 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:13:36.328 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.28.20:5700) Recv NOMTXPOWER cmd
2026-01-29 02:13:36.328 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:13:36.328 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:13:36.328 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:13:36.329 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.28.20:5700) Recv POWERON CMD
2026-01-29 02:13:36.329 [INFO] ctrl_if_trx.py:109 (BTS@172.18.28.20:5700) Starting transceiver...
2026-01-29 02:13:36.329 [INFO] transceiver.py:243 Starting clock generator
2026-01-29 02:13:36.329 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-01-29 02:13:36.329 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:13:36.329 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:13:36.329 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:13:36.329 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETRXGAIN
2026-01-29 02:13:36.329 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:13:36.329 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:13:36.329 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:13:36.329 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:13:36.329 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:13:36.329 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:13:36.329 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:13:36.329 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:13:36.329 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:13:36.329 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:13:36.329 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:13:36.330 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:13:36.330 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:13:36.330 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:13:36.330 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:13:36.330 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:13:36.330 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:13:36.330 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:13:36.330 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:13:36.330 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:13:36.330 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:13:36.330 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:13:36.330 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:13:36.330 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:13:36.333 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-01-29 02:13:36.817 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-01-29 02:13:36.857 [DEBUG] fake_trx.py:278 (BTS@172.18.28.20:5700) Recv FAKE_TOA cmd
2026-01-29 02:13:36.859 [DEBUG] fake_trx.py:297 (BTS@172.18.28.20:5700) Recv FAKE_RSSI cmd
2026-01-29 02:13:36.862 [DEBUG] fake_trx.py:322 (BTS@172.18.28.20:5700) Recv FAKE_CI cmd
2026-01-29 02:13:36.862 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:13:36.883 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 02:13:36.883 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 02:13:36.884 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 02:13:36.926 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:13:36.927 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 02:13:36.928 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 02:13:36.928 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.28.22:6700) Recv POWERON CMD
2026-01-29 02:13:36.928 [INFO] ctrl_if_trx.py:109 (MS@172.18.28.22:6700) Starting transceiver...
2026-01-29 02:13:36.957 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:13:36.962 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 02:13:36.962 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 02:13:36.962 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:13:36.963 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:13:37.295 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-01-29 02:13:37.332 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:13:37.332 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 02:13:37.333 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:13:37.335 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:13:37.340 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:13:37.342 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:13:37.349 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 02:13:37.349 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 02:13:37.365 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 02:13:37.365 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 02:13:37.366 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 02:13:37.375 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:13:37.376 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 02:13:37.376 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 02:13:37.376 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.28.22:6700) Recv POWERON CMD
2026-01-29 02:13:37.376 [INFO] ctrl_if_trx.py:109 (MS@172.18.28.22:6700) Starting transceiver...
2026-01-29 02:13:37.385 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:13:37.387 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 02:13:37.387 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 02:13:37.388 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:13:37.388 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:13:37.760 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:13:37.762 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:13:37.767 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 02:13:37.767 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 02:13:37.773 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-01-29 02:13:37.777 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 02:13:37.778 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:13:37.778 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:13:37.778 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:13:37.780 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 02:13:37.780 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:13:37.780 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:13:37.780 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.28.20:5700) Recv POWEROFF cmd
2026-01-29 02:13:37.780 [INFO] ctrl_if_trx.py:117 (BTS@172.18.28.20:5700) Stopping transceiver...
2026-01-29 02:13:37.780 [INFO] transceiver.py:246 Stopping clock generator
2026-01-29 02:13:37.781 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:13:42.781 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.28.20:5700) Recv POWEROFF cmd
2026-01-29 02:13:42.781 [INFO] ctrl_if_trx.py:117 (BTS@172.18.28.20:5700) Stopping transceiver...
2026-01-29 02:13:42.783 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:13:42.784 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:13:42.784 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:13:42.785 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 02:13:42.791 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 02:13:42.792 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.28.20:5700) Recv SETFORMAT cmd
2026-01-29 02:13:42.792 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.28.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:13:42.793 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.28.20:5700) Recv SETFORMAT cmd
2026-01-29 02:13:42.793 [INFO] ctrl_if_trx.py:201 (BTS@172.18.28.20:5700) TRXD header version 1 -> 1
2026-01-29 02:13:42.795 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.28.20:5700/1) Recv RXTUNE cmd
2026-01-29 02:13:42.795 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.28.20:5700/1) Recv TXTUNE cmd
2026-01-29 02:13:42.796 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.28.20:5700/1) Recv SETFORMAT cmd
2026-01-29 02:13:42.796 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.28.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:13:42.796 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:13:42.796 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.28.20:5700/1) Recv NOMTXPOWER cmd
2026-01-29 02:13:42.797 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.28.20:5700/1) Recv SETFORMAT cmd
2026-01-29 02:13:42.797 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.28.20:5700/1) TRXD header version 1 -> 1
2026-01-29 02:13:42.797 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.28.20:5700/2) Recv RXTUNE cmd
2026-01-29 02:13:42.798 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.28.20:5700/2) Recv TXTUNE cmd
2026-01-29 02:13:42.798 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.28.20:5700/2) Recv SETFORMAT cmd
2026-01-29 02:13:42.798 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.28.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:13:42.798 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:13:42.798 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.28.20:5700/2) Recv NOMTXPOWER cmd
2026-01-29 02:13:42.798 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.28.20:5700/2) Recv SETFORMAT cmd
2026-01-29 02:13:42.798 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.28.20:5700/2) TRXD header version 1 -> 1
2026-01-29 02:13:42.800 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.28.20:5700/3) Recv RXTUNE cmd
2026-01-29 02:13:42.800 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.28.20:5700/3) Recv TXTUNE cmd
2026-01-29 02:13:42.800 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.28.20:5700/3) Recv SETFORMAT cmd
2026-01-29 02:13:42.800 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.28.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:13:42.800 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:13:42.800 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.28.20:5700/3) Recv NOMTXPOWER cmd
2026-01-29 02:13:42.800 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.28.20:5700/3) Recv SETFORMAT cmd
2026-01-29 02:13:42.800 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.28.20:5700/3) TRXD header version 1 -> 1
2026-01-29 02:13:42.803 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.28.20:5700) Recv RXTUNE cmd
2026-01-29 02:13:42.803 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETTSC
2026-01-29 02:13:42.803 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETTSC
2026-01-29 02:13:42.803 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETTSC
2026-01-29 02:13:42.803 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.28.20:5700) Recv TXTUNE cmd
2026-01-29 02:13:42.803 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETRXGAIN
2026-01-29 02:13:42.803 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETRXGAIN
2026-01-29 02:13:42.804 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETRXGAIN
2026-01-29 02:13:42.804 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETTSC
2026-01-29 02:13:42.804 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:13:42.804 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:13:42.804 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:13:42.804 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.28.20:5700) Recv NOMTXPOWER cmd
2026-01-29 02:13:42.804 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:13:42.804 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:13:42.804 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:13:42.804 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.28.20:5700) Recv POWERON CMD
2026-01-29 02:13:42.804 [INFO] ctrl_if_trx.py:109 (BTS@172.18.28.20:5700) Starting transceiver...
2026-01-29 02:13:42.804 [INFO] transceiver.py:243 Starting clock generator
2026-01-29 02:13:42.804 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-01-29 02:13:42.804 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:13:42.804 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:13:42.804 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:13:42.804 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETRXGAIN
2026-01-29 02:13:42.805 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:13:42.805 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:13:42.805 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:13:42.805 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:13:42.805 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:13:42.805 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:13:42.805 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:13:42.805 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:13:42.805 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:13:42.805 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:13:42.805 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:13:42.805 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:13:42.805 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:13:42.805 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:13:42.805 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:13:42.805 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:13:42.805 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:13:42.805 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:13:42.805 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:13:42.805 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:13:42.805 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:13:42.805 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:13:42.806 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:13:42.809 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-01-29 02:13:43.293 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-01-29 02:13:43.330 [DEBUG] fake_trx.py:278 (BTS@172.18.28.20:5700) Recv FAKE_TOA cmd
2026-01-29 02:13:43.332 [DEBUG] fake_trx.py:297 (BTS@172.18.28.20:5700) Recv FAKE_RSSI cmd
2026-01-29 02:13:43.333 [DEBUG] fake_trx.py:322 (BTS@172.18.28.20:5700) Recv FAKE_CI cmd
2026-01-29 02:13:43.335 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:13:43.353 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 02:13:43.353 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 02:13:43.353 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 02:13:43.378 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:13:43.378 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 02:13:43.379 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 02:13:43.379 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.28.22:6700) Recv POWERON CMD
2026-01-29 02:13:43.379 [INFO] ctrl_if_trx.py:109 (MS@172.18.28.22:6700) Starting transceiver...
2026-01-29 02:13:43.385 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:13:43.389 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 02:13:43.389 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 02:13:43.389 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:13:43.389 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:13:43.770 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-01-29 02:13:43.796 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:13:43.798 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:13:43.804 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 02:13:43.804 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 02:13:43.807 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 02:13:43.808 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:13:43.809 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:13:43.812 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:13:43.819 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 02:13:43.819 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 02:13:43.820 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 02:13:43.830 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:13:43.830 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 02:13:43.830 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 02:13:43.830 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.28.22:6700) Recv POWERON CMD
2026-01-29 02:13:43.830 [INFO] ctrl_if_trx.py:109 (MS@172.18.28.22:6700) Starting transceiver...
2026-01-29 02:13:43.863 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:13:43.868 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 02:13:43.869 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 02:13:43.869 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:13:43.869 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:13:44.236 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:13:44.238 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:13:44.243 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 02:13:44.243 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 02:13:44.247 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-01-29 02:13:44.253 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 02:13:44.253 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:13:44.253 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:13:44.253 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:13:44.259 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 02:13:44.260 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:13:44.260 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:13:44.260 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.28.20:5700) Recv POWEROFF cmd
2026-01-29 02:13:44.260 [INFO] ctrl_if_trx.py:117 (BTS@172.18.28.20:5700) Stopping transceiver...
2026-01-29 02:13:44.260 [INFO] transceiver.py:246 Stopping clock generator
2026-01-29 02:13:44.260 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:13:44.261 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=310 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:13:44.261 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=310 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:13:44.261 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=310 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:13:44.261 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=310 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:13:44.261 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=310 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:13:44.261 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=310 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:13:44.261 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=310 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:13:44.261 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=310 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:13:49.257 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.28.20:5700) Recv POWEROFF cmd
2026-01-29 02:13:49.257 [INFO] ctrl_if_trx.py:117 (BTS@172.18.28.20:5700) Stopping transceiver...
2026-01-29 02:13:49.258 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:13:49.259 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:13:49.260 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:13:49.260 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 02:13:49.263 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 02:13:49.263 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.28.20:5700) Recv SETFORMAT cmd
2026-01-29 02:13:49.263 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.28.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:13:49.263 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.28.20:5700) Recv SETFORMAT cmd
2026-01-29 02:13:49.263 [INFO] ctrl_if_trx.py:201 (BTS@172.18.28.20:5700) TRXD header version 1 -> 1
2026-01-29 02:13:49.264 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.28.20:5700/1) Recv RXTUNE cmd
2026-01-29 02:13:49.264 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.28.20:5700/1) Recv TXTUNE cmd
2026-01-29 02:13:49.264 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.28.20:5700/1) Recv SETFORMAT cmd
2026-01-29 02:13:49.264 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.28.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:13:49.264 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:13:49.264 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.28.20:5700/1) Recv NOMTXPOWER cmd
2026-01-29 02:13:49.264 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.28.20:5700/1) Recv SETFORMAT cmd
2026-01-29 02:13:49.264 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.28.20:5700/1) TRXD header version 1 -> 1
2026-01-29 02:13:49.265 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.28.20:5700/2) Recv RXTUNE cmd
2026-01-29 02:13:49.265 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.28.20:5700/2) Recv TXTUNE cmd
2026-01-29 02:13:49.265 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.28.20:5700/2) Recv SETFORMAT cmd
2026-01-29 02:13:49.265 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.28.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:13:49.265 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:13:49.265 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.28.20:5700/2) Recv NOMTXPOWER cmd
2026-01-29 02:13:49.265 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.28.20:5700/2) Recv SETFORMAT cmd
2026-01-29 02:13:49.265 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.28.20:5700/2) TRXD header version 1 -> 1
2026-01-29 02:13:49.266 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.28.20:5700/3) Recv RXTUNE cmd
2026-01-29 02:13:49.266 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.28.20:5700/3) Recv TXTUNE cmd
2026-01-29 02:13:49.266 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.28.20:5700/3) Recv SETFORMAT cmd
2026-01-29 02:13:49.266 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.28.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:13:49.266 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:13:49.266 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.28.20:5700/3) Recv NOMTXPOWER cmd
2026-01-29 02:13:49.266 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.28.20:5700/3) Recv SETFORMAT cmd
2026-01-29 02:13:49.266 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.28.20:5700/3) TRXD header version 1 -> 1
2026-01-29 02:13:49.267 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.28.20:5700) Recv RXTUNE cmd
2026-01-29 02:13:49.267 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETTSC
2026-01-29 02:13:49.267 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETTSC
2026-01-29 02:13:49.267 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETTSC
2026-01-29 02:13:49.267 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.28.20:5700) Recv TXTUNE cmd
2026-01-29 02:13:49.268 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETRXGAIN
2026-01-29 02:13:49.268 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETRXGAIN
2026-01-29 02:13:49.268 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETRXGAIN
2026-01-29 02:13:49.268 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETTSC
2026-01-29 02:13:49.268 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:13:49.268 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:13:49.268 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.28.20:5700) Recv NOMTXPOWER cmd
2026-01-29 02:13:49.268 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:13:49.268 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:13:49.268 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:13:49.268 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.28.20:5700) Recv POWERON CMD
2026-01-29 02:13:49.268 [INFO] ctrl_if_trx.py:109 (BTS@172.18.28.20:5700) Starting transceiver...
2026-01-29 02:13:49.268 [INFO] transceiver.py:243 Starting clock generator
2026-01-29 02:13:49.268 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-01-29 02:13:49.268 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:13:49.268 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:13:49.268 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:13:49.268 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETRXGAIN
2026-01-29 02:13:49.268 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:13:49.268 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:13:49.268 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:13:49.268 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:13:49.268 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:13:49.268 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:13:49.268 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:13:49.268 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:13:49.268 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:13:49.268 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:13:49.268 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:13:49.268 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:13:49.268 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:13:49.268 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:13:49.268 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:13:49.268 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:13:49.268 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:13:49.268 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:13:49.268 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:13:49.268 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:13:49.269 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:13:49.269 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:13:49.269 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:13:49.269 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:13:49.273 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-01-29 02:13:49.754 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-01-29 02:13:49.783 [DEBUG] fake_trx.py:278 (BTS@172.18.28.20:5700) Recv FAKE_TOA cmd
2026-01-29 02:13:49.784 [DEBUG] fake_trx.py:297 (BTS@172.18.28.20:5700) Recv FAKE_RSSI cmd
2026-01-29 02:13:49.784 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:13:49.784 [DEBUG] fake_trx.py:322 (BTS@172.18.28.20:5700) Recv FAKE_CI cmd
2026-01-29 02:13:49.794 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 02:13:49.794 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 02:13:49.794 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 02:13:49.825 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:13:49.825 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 02:13:49.825 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 02:13:49.825 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.28.22:6700) Recv POWERON CMD
2026-01-29 02:13:49.825 [INFO] ctrl_if_trx.py:109 (MS@172.18.28.22:6700) Starting transceiver...
2026-01-29 02:13:49.848 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:13:49.853 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 02:13:49.853 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 02:13:49.854 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:13:49.854 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:13:50.229 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:13:50.231 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:13:50.232 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-01-29 02:13:50.238 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 02:13:50.238 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 02:13:50.254 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 02:13:50.254 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 02:13:50.254 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 02:13:50.265 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:13:50.266 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 02:13:50.266 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 02:13:50.266 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.28.22:6700) Recv POWERON CMD
2026-01-29 02:13:50.266 [INFO] ctrl_if_trx.py:109 (MS@172.18.28.22:6700) Starting transceiver...
2026-01-29 02:13:50.270 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 02:13:50.270 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:13:50.271 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:13:50.273 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:13:50.275 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:13:50.277 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 02:13:50.277 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 02:13:50.277 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:13:50.277 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:13:50.678 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:13:50.680 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:13:50.684 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 02:13:50.684 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 02:13:50.694 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 02:13:50.695 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:13:50.695 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:13:50.695 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:13:50.697 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 02:13:50.697 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:13:50.697 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:13:50.697 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.28.20:5700) Recv POWEROFF cmd
2026-01-29 02:13:50.697 [INFO] ctrl_if_trx.py:117 (BTS@172.18.28.20:5700) Stopping transceiver...
2026-01-29 02:13:50.697 [INFO] transceiver.py:246 Stopping clock generator
2026-01-29 02:13:50.698 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:13:50.698 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=306 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:13:50.698 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=306 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:13:50.698 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=306 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:13:50.698 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=306 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:13:50.698 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=306 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:13:50.698 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=306 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:13:50.698 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=306 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:13:50.698 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=306 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:13:55.699 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.28.20:5700) Recv POWEROFF cmd
2026-01-29 02:13:55.699 [INFO] ctrl_if_trx.py:117 (BTS@172.18.28.20:5700) Stopping transceiver...
2026-01-29 02:13:55.701 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:13:55.701 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:13:55.702 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:13:55.702 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 02:13:55.705 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 02:13:55.706 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.28.20:5700) Recv SETFORMAT cmd
2026-01-29 02:13:55.706 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.28.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:13:55.706 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.28.20:5700) Recv SETFORMAT cmd
2026-01-29 02:13:55.706 [INFO] ctrl_if_trx.py:201 (BTS@172.18.28.20:5700) TRXD header version 1 -> 1
2026-01-29 02:13:55.708 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.28.20:5700/1) Recv RXTUNE cmd
2026-01-29 02:13:55.708 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.28.20:5700/1) Recv TXTUNE cmd
2026-01-29 02:13:55.708 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.28.20:5700/1) Recv SETFORMAT cmd
2026-01-29 02:13:55.708 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.28.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:13:55.709 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:13:55.709 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.28.20:5700/1) Recv NOMTXPOWER cmd
2026-01-29 02:13:55.709 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.28.20:5700/1) Recv SETFORMAT cmd
2026-01-29 02:13:55.709 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.28.20:5700/1) TRXD header version 1 -> 1
2026-01-29 02:13:55.710 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.28.20:5700/2) Recv RXTUNE cmd
2026-01-29 02:13:55.710 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.28.20:5700/2) Recv TXTUNE cmd
2026-01-29 02:13:55.710 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.28.20:5700/2) Recv SETFORMAT cmd
2026-01-29 02:13:55.710 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.28.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:13:55.710 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:13:55.710 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.28.20:5700/2) Recv NOMTXPOWER cmd
2026-01-29 02:13:55.710 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.28.20:5700/2) Recv SETFORMAT cmd
2026-01-29 02:13:55.710 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.28.20:5700/2) TRXD header version 1 -> 1
2026-01-29 02:13:55.712 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.28.20:5700/3) Recv RXTUNE cmd
2026-01-29 02:13:55.712 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.28.20:5700/3) Recv TXTUNE cmd
2026-01-29 02:13:55.712 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.28.20:5700/3) Recv SETFORMAT cmd
2026-01-29 02:13:55.712 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.28.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:13:55.712 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:13:55.712 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.28.20:5700/3) Recv NOMTXPOWER cmd
2026-01-29 02:13:55.712 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.28.20:5700/3) Recv SETFORMAT cmd
2026-01-29 02:13:55.712 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.28.20:5700/3) TRXD header version 1 -> 1
2026-01-29 02:13:55.714 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.28.20:5700) Recv RXTUNE cmd
2026-01-29 02:13:55.714 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETTSC
2026-01-29 02:13:55.714 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETTSC
2026-01-29 02:13:55.714 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETTSC
2026-01-29 02:13:55.714 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.28.20:5700) Recv TXTUNE cmd
2026-01-29 02:13:55.714 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETRXGAIN
2026-01-29 02:13:55.714 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETRXGAIN
2026-01-29 02:13:55.714 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETRXGAIN
2026-01-29 02:13:55.714 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETTSC
2026-01-29 02:13:55.714 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:13:55.714 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:13:55.714 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:13:55.714 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.28.20:5700) Recv NOMTXPOWER cmd
2026-01-29 02:13:55.714 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:13:55.714 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:13:55.714 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:13:55.714 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.28.20:5700) Recv POWERON CMD
2026-01-29 02:13:55.714 [INFO] ctrl_if_trx.py:109 (BTS@172.18.28.20:5700) Starting transceiver...
2026-01-29 02:13:55.714 [INFO] transceiver.py:243 Starting clock generator
2026-01-29 02:13:55.714 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-01-29 02:13:55.714 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:13:55.715 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:13:55.715 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:13:55.715 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETRXGAIN
2026-01-29 02:13:55.715 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:13:55.715 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:13:55.715 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:13:55.715 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:13:55.715 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:13:55.715 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:13:55.715 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:13:55.715 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:13:55.715 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:13:55.715 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:13:55.715 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:13:55.715 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:13:55.715 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:13:55.715 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:13:55.715 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:13:55.715 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:13:55.715 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:13:55.715 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:13:55.715 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:13:55.715 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:13:55.715 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:13:55.715 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:13:55.715 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:13:55.719 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-01-29 02:13:56.203 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-01-29 02:13:56.233 [DEBUG] fake_trx.py:278 (BTS@172.18.28.20:5700) Recv FAKE_TOA cmd
2026-01-29 02:13:56.234 [DEBUG] fake_trx.py:297 (BTS@172.18.28.20:5700) Recv FAKE_RSSI cmd
2026-01-29 02:13:56.235 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:13:56.235 [DEBUG] fake_trx.py:322 (BTS@172.18.28.20:5700) Recv FAKE_CI cmd
2026-01-29 02:13:56.245 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 02:13:56.245 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 02:13:56.246 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 02:13:56.271 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:13:56.272 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 02:13:56.272 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 02:13:56.273 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.28.22:6700) Recv POWERON CMD
2026-01-29 02:13:56.273 [INFO] ctrl_if_trx.py:109 (MS@172.18.28.22:6700) Starting transceiver...
2026-01-29 02:13:56.298 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:13:56.303 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 02:13:56.303 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 02:13:56.303 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:13:56.303 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:13:56.680 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-01-29 02:13:56.718 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:13:56.718 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:13:56.718 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 02:13:56.719 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:13:57.158 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-01-29 02:13:57.636 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-01-29 02:13:57.719 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:13:57.719 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:13:57.719 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 02:13:57.720 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:13:58.114 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-01-29 02:13:58.592 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-01-29 02:13:58.720 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 02:13:58.720 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:13:58.720 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:13:58.720 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:13:59.070 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-01-29 02:13:59.548 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-01-29 02:13:59.720 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 02:13:59.721 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:13:59.721 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:13:59.721 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:14:00.026 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-01-29 02:14:00.307 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 02:14:00.308 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 02:14:00.311 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 02:14:00.311 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:14:00.311 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:14:00.311 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:14:00.312 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 02:14:00.312 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:14:00.312 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:14:00.312 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:14:00.312 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.28.20:5700) Recv POWEROFF cmd
2026-01-29 02:14:00.312 [INFO] ctrl_if_trx.py:117 (BTS@172.18.28.20:5700) Stopping transceiver...
2026-01-29 02:14:00.312 [INFO] transceiver.py:246 Stopping clock generator
2026-01-29 02:14:00.312 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=982 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:14:00.312 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=982 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:14:00.312 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=982 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:14:00.312 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=982 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:14:00.312 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=982 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:14:00.312 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=982 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:14:00.312 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=982 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:14:00.312 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=982 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:14:05.318 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.28.20:5700) Recv POWEROFF cmd
2026-01-29 02:14:05.318 [INFO] ctrl_if_trx.py:117 (BTS@172.18.28.20:5700) Stopping transceiver...
2026-01-29 02:14:05.318 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:14:05.318 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:14:05.318 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:14:05.318 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 02:14:05.327 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 02:14:05.329 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.28.20:5700) Recv SETFORMAT cmd
2026-01-29 02:14:05.329 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.28.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:14:05.330 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.28.20:5700) Recv SETFORMAT cmd
2026-01-29 02:14:05.330 [INFO] ctrl_if_trx.py:201 (BTS@172.18.28.20:5700) TRXD header version 1 -> 1
2026-01-29 02:14:05.336 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.28.20:5700/1) Recv RXTUNE cmd
2026-01-29 02:14:05.336 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.28.20:5700/1) Recv TXTUNE cmd
2026-01-29 02:14:05.336 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.28.20:5700/1) Recv SETFORMAT cmd
2026-01-29 02:14:05.337 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.28.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:14:05.337 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:14:05.337 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.28.20:5700/1) Recv NOMTXPOWER cmd
2026-01-29 02:14:05.338 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.28.20:5700/1) Recv SETFORMAT cmd
2026-01-29 02:14:05.338 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.28.20:5700/1) TRXD header version 1 -> 1
2026-01-29 02:14:05.340 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.28.20:5700/2) Recv RXTUNE cmd
2026-01-29 02:14:05.340 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.28.20:5700/2) Recv TXTUNE cmd
2026-01-29 02:14:05.340 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.28.20:5700/2) Recv SETFORMAT cmd
2026-01-29 02:14:05.341 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.28.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:14:05.341 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:14:05.341 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.28.20:5700/2) Recv NOMTXPOWER cmd
2026-01-29 02:14:05.341 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.28.20:5700/2) Recv SETFORMAT cmd
2026-01-29 02:14:05.341 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.28.20:5700/2) TRXD header version 1 -> 1
2026-01-29 02:14:05.343 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.28.20:5700/3) Recv RXTUNE cmd
2026-01-29 02:14:05.343 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.28.20:5700/3) Recv TXTUNE cmd
2026-01-29 02:14:05.343 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.28.20:5700/3) Recv SETFORMAT cmd
2026-01-29 02:14:05.343 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.28.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:14:05.343 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:14:05.343 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.28.20:5700/3) Recv NOMTXPOWER cmd
2026-01-29 02:14:05.343 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.28.20:5700/3) Recv SETFORMAT cmd
2026-01-29 02:14:05.343 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.28.20:5700/3) TRXD header version 1 -> 1
2026-01-29 02:14:05.346 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.28.20:5700) Recv RXTUNE cmd
2026-01-29 02:14:05.346 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETTSC
2026-01-29 02:14:05.346 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETTSC
2026-01-29 02:14:05.346 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.28.20:5700) Recv TXTUNE cmd
2026-01-29 02:14:05.346 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETTSC
2026-01-29 02:14:05.346 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETRXGAIN
2026-01-29 02:14:05.346 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETRXGAIN
2026-01-29 02:14:05.346 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETTSC
2026-01-29 02:14:05.346 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETRXGAIN
2026-01-29 02:14:05.346 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:14:05.346 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:14:05.346 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.28.20:5700) Recv NOMTXPOWER cmd
2026-01-29 02:14:05.346 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:14:05.346 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:14:05.346 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:14:05.346 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.28.20:5700) Recv POWERON CMD
2026-01-29 02:14:05.346 [INFO] ctrl_if_trx.py:109 (BTS@172.18.28.20:5700) Starting transceiver...
2026-01-29 02:14:05.347 [INFO] transceiver.py:243 Starting clock generator
2026-01-29 02:14:05.347 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-01-29 02:14:05.347 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:14:05.347 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:14:05.347 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:14:05.347 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETRXGAIN
2026-01-29 02:14:05.347 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:14:05.347 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:14:05.347 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:14:05.347 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:14:05.347 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:14:05.347 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:14:05.347 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:14:05.347 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:14:05.347 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:14:05.347 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:14:05.347 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:14:05.347 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:14:05.347 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:14:05.347 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:14:05.348 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:14:05.348 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:14:05.348 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:14:05.348 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:14:05.348 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:14:05.348 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:14:05.348 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:14:05.348 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:14:05.348 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:14:05.348 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:14:05.352 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-01-29 02:14:05.835 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-01-29 02:14:05.869 [DEBUG] fake_trx.py:278 (BTS@172.18.28.20:5700) Recv FAKE_TOA cmd
2026-01-29 02:14:05.870 [DEBUG] fake_trx.py:297 (BTS@172.18.28.20:5700) Recv FAKE_RSSI cmd
2026-01-29 02:14:05.871 [DEBUG] fake_trx.py:322 (BTS@172.18.28.20:5700) Recv FAKE_CI cmd
2026-01-29 02:14:05.872 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:14:05.885 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 02:14:05.885 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 02:14:05.886 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 02:14:05.914 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:14:05.915 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 02:14:05.915 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 02:14:05.915 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.28.22:6700) Recv POWERON CMD
2026-01-29 02:14:05.915 [INFO] ctrl_if_trx.py:109 (MS@172.18.28.22:6700) Starting transceiver...
2026-01-29 02:14:05.929 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:14:05.933 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 02:14:05.933 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 02:14:05.934 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:14:05.934 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:14:06.152 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:14:06.154 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:14:06.161 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 02:14:06.161 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 02:14:06.179 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 02:14:06.179 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 02:14:06.179 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 02:14:06.189 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:14:06.189 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 02:14:06.189 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 02:14:06.189 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.28.22:6700) Recv POWERON CMD
2026-01-29 02:14:06.189 [INFO] ctrl_if_trx.py:109 (MS@172.18.28.22:6700) Starting transceiver...
2026-01-29 02:14:06.208 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:14:06.211 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 02:14:06.211 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 02:14:06.212 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:14:06.212 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:14:06.309 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-01-29 02:14:06.350 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:14:06.351 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 02:14:06.351 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:14:06.354 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:14:06.410 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:14:06.411 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:14:06.416 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 02:14:06.416 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 02:14:06.427 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 02:14:06.427 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:14:06.427 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:14:06.427 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:14:06.428 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 02:14:06.428 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:14:06.428 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:14:06.428 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.28.20:5700) Recv POWEROFF cmd
2026-01-29 02:14:06.428 [INFO] ctrl_if_trx.py:117 (BTS@172.18.28.20:5700) Stopping transceiver...
2026-01-29 02:14:06.428 [INFO] transceiver.py:246 Stopping clock generator
2026-01-29 02:14:06.428 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:14:11.428 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.28.20:5700) Recv POWEROFF cmd
2026-01-29 02:14:11.429 [INFO] ctrl_if_trx.py:117 (BTS@172.18.28.20:5700) Stopping transceiver...
2026-01-29 02:14:11.430 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:14:11.432 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:14:11.432 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:14:11.433 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 02:14:11.442 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 02:14:11.443 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.28.20:5700) Recv SETFORMAT cmd
2026-01-29 02:14:11.444 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.28.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:14:11.444 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.28.20:5700) Recv SETFORMAT cmd
2026-01-29 02:14:11.444 [INFO] ctrl_if_trx.py:201 (BTS@172.18.28.20:5700) TRXD header version 1 -> 1
2026-01-29 02:14:11.448 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.28.20:5700/1) Recv RXTUNE cmd
2026-01-29 02:14:11.449 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.28.20:5700/1) Recv TXTUNE cmd
2026-01-29 02:14:11.449 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.28.20:5700/1) Recv SETFORMAT cmd
2026-01-29 02:14:11.449 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.28.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:14:11.449 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:14:11.450 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.28.20:5700/1) Recv NOMTXPOWER cmd
2026-01-29 02:14:11.450 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.28.20:5700/1) Recv SETFORMAT cmd
2026-01-29 02:14:11.450 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.28.20:5700/1) TRXD header version 1 -> 1
2026-01-29 02:14:11.451 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.28.20:5700/2) Recv RXTUNE cmd
2026-01-29 02:14:11.451 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.28.20:5700/2) Recv TXTUNE cmd
2026-01-29 02:14:11.451 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.28.20:5700/2) Recv SETFORMAT cmd
2026-01-29 02:14:11.452 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.28.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:14:11.452 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:14:11.452 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.28.20:5700/2) Recv NOMTXPOWER cmd
2026-01-29 02:14:11.452 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.28.20:5700/2) Recv SETFORMAT cmd
2026-01-29 02:14:11.452 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.28.20:5700/2) TRXD header version 1 -> 1
2026-01-29 02:14:11.454 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.28.20:5700/3) Recv RXTUNE cmd
2026-01-29 02:14:11.454 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.28.20:5700/3) Recv TXTUNE cmd
2026-01-29 02:14:11.455 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.28.20:5700/3) Recv SETFORMAT cmd
2026-01-29 02:14:11.455 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.28.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:14:11.455 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:14:11.455 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.28.20:5700/3) Recv NOMTXPOWER cmd
2026-01-29 02:14:11.455 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.28.20:5700/3) Recv SETFORMAT cmd
2026-01-29 02:14:11.455 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.28.20:5700/3) TRXD header version 1 -> 1
2026-01-29 02:14:11.457 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.28.20:5700) Recv RXTUNE cmd
2026-01-29 02:14:11.457 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETTSC
2026-01-29 02:14:11.457 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETTSC
2026-01-29 02:14:11.457 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETTSC
2026-01-29 02:14:11.458 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.28.20:5700) Recv TXTUNE cmd
2026-01-29 02:14:11.458 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETRXGAIN
2026-01-29 02:14:11.458 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETRXGAIN
2026-01-29 02:14:11.458 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETRXGAIN
2026-01-29 02:14:11.458 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETTSC
2026-01-29 02:14:11.458 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:14:11.458 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:14:11.458 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:14:11.458 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.28.20:5700) Recv NOMTXPOWER cmd
2026-01-29 02:14:11.458 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:14:11.458 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:14:11.458 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:14:11.458 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.28.20:5700) Recv POWERON CMD
2026-01-29 02:14:11.458 [INFO] ctrl_if_trx.py:109 (BTS@172.18.28.20:5700) Starting transceiver...
2026-01-29 02:14:11.458 [INFO] transceiver.py:243 Starting clock generator
2026-01-29 02:14:11.459 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-01-29 02:14:11.459 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:14:11.459 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:14:11.459 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:14:11.459 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETRXGAIN
2026-01-29 02:14:11.459 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:14:11.459 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:14:11.459 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:14:11.459 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:14:11.459 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:14:11.459 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:14:11.459 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:14:11.459 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:14:11.459 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:14:11.459 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:14:11.459 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:14:11.459 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:14:11.459 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:14:11.459 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:14:11.459 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:14:11.459 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:14:11.460 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:14:11.460 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:14:11.460 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:14:11.460 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:14:11.460 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:14:11.460 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:14:11.460 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:14:11.463 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-01-29 02:14:11.947 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-01-29 02:14:11.990 [DEBUG] fake_trx.py:278 (BTS@172.18.28.20:5700) Recv FAKE_TOA cmd
2026-01-29 02:14:11.992 [DEBUG] fake_trx.py:297 (BTS@172.18.28.20:5700) Recv FAKE_RSSI cmd
2026-01-29 02:14:11.995 [DEBUG] fake_trx.py:322 (BTS@172.18.28.20:5700) Recv FAKE_CI cmd
2026-01-29 02:14:11.995 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:14:12.019 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 02:14:12.019 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 02:14:12.019 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 02:14:12.069 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:14:12.069 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 02:14:12.069 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 02:14:12.070 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.28.22:6700) Recv POWERON CMD
2026-01-29 02:14:12.070 [INFO] ctrl_if_trx.py:109 (MS@172.18.28.22:6700) Starting transceiver...
2026-01-29 02:14:12.087 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:14:12.092 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 02:14:12.093 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 02:14:12.093 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:14:12.094 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:14:12.425 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-01-29 02:14:12.462 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:14:12.462 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 02:14:12.463 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:14:12.466 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:14:12.903 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-01-29 02:14:13.381 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-01-29 02:14:13.463 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:14:13.463 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 02:14:13.463 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:14:13.468 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:14:13.859 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-01-29 02:14:14.336 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-01-29 02:14:14.464 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 02:14:14.464 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:14:14.464 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:14:14.468 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:14:14.814 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-01-29 02:14:15.292 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-01-29 02:14:15.464 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 02:14:15.465 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:14:15.465 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:14:15.469 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:14:15.770 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-01-29 02:14:16.098 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 02:14:16.098 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 02:14:16.101 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 02:14:16.101 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:14:16.101 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:14:16.101 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:14:16.102 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 02:14:16.102 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:14:16.102 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:14:16.102 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.28.20:5700) Recv POWEROFF cmd
2026-01-29 02:14:16.102 [INFO] ctrl_if_trx.py:117 (BTS@172.18.28.20:5700) Stopping transceiver...
2026-01-29 02:14:16.102 [INFO] transceiver.py:246 Stopping clock generator
2026-01-29 02:14:16.102 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:14:16.102 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=991 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:14:16.102 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=991 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:14:16.102 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=991 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:14:16.102 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=991 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:14:21.105 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.28.20:5700) Recv POWEROFF cmd
2026-01-29 02:14:21.105 [INFO] ctrl_if_trx.py:117 (BTS@172.18.28.20:5700) Stopping transceiver...
2026-01-29 02:14:21.106 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:14:21.108 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:14:21.109 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:14:21.109 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 02:14:21.117 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 02:14:21.118 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.28.20:5700) Recv SETFORMAT cmd
2026-01-29 02:14:21.118 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.28.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:14:21.119 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.28.20:5700) Recv SETFORMAT cmd
2026-01-29 02:14:21.119 [INFO] ctrl_if_trx.py:201 (BTS@172.18.28.20:5700) TRXD header version 1 -> 1
2026-01-29 02:14:21.121 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.28.20:5700/1) Recv RXTUNE cmd
2026-01-29 02:14:21.121 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.28.20:5700/1) Recv TXTUNE cmd
2026-01-29 02:14:21.121 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.28.20:5700/1) Recv SETFORMAT cmd
2026-01-29 02:14:21.122 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.28.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:14:21.122 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:14:21.122 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.28.20:5700/1) Recv NOMTXPOWER cmd
2026-01-29 02:14:21.123 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.28.20:5700/1) Recv SETFORMAT cmd
2026-01-29 02:14:21.123 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.28.20:5700/1) TRXD header version 1 -> 1
2026-01-29 02:14:21.124 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.28.20:5700/2) Recv RXTUNE cmd
2026-01-29 02:14:21.124 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.28.20:5700/2) Recv TXTUNE cmd
2026-01-29 02:14:21.124 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.28.20:5700/2) Recv SETFORMAT cmd
2026-01-29 02:14:21.124 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.28.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:14:21.124 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:14:21.124 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.28.20:5700/2) Recv NOMTXPOWER cmd
2026-01-29 02:14:21.124 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.28.20:5700/2) Recv SETFORMAT cmd
2026-01-29 02:14:21.124 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.28.20:5700/2) TRXD header version 1 -> 1
2026-01-29 02:14:21.126 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.28.20:5700/3) Recv RXTUNE cmd
2026-01-29 02:14:21.127 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.28.20:5700/3) Recv TXTUNE cmd
2026-01-29 02:14:21.127 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.28.20:5700/3) Recv SETFORMAT cmd
2026-01-29 02:14:21.127 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.28.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:14:21.127 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:14:21.127 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.28.20:5700/3) Recv NOMTXPOWER cmd
2026-01-29 02:14:21.127 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.28.20:5700/3) Recv SETFORMAT cmd
2026-01-29 02:14:21.127 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.28.20:5700/3) TRXD header version 1 -> 1
2026-01-29 02:14:21.130 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.28.20:5700) Recv RXTUNE cmd
2026-01-29 02:14:21.130 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETTSC
2026-01-29 02:14:21.130 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETTSC
2026-01-29 02:14:21.130 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETTSC
2026-01-29 02:14:21.130 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.28.20:5700) Recv TXTUNE cmd
2026-01-29 02:14:21.130 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETRXGAIN
2026-01-29 02:14:21.130 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETRXGAIN
2026-01-29 02:14:21.130 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETRXGAIN
2026-01-29 02:14:21.130 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETTSC
2026-01-29 02:14:21.130 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:14:21.130 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:14:21.130 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.28.20:5700) Recv NOMTXPOWER cmd
2026-01-29 02:14:21.130 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:14:21.130 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:14:21.130 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:14:21.130 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.28.20:5700) Recv POWERON CMD
2026-01-29 02:14:21.130 [INFO] ctrl_if_trx.py:109 (BTS@172.18.28.20:5700) Starting transceiver...
2026-01-29 02:14:21.130 [INFO] transceiver.py:243 Starting clock generator
2026-01-29 02:14:21.131 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-01-29 02:14:21.131 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:14:21.131 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:14:21.131 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:14:21.131 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETRXGAIN
2026-01-29 02:14:21.131 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:14:21.131 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:14:21.131 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:14:21.131 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:14:21.131 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:14:21.131 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:14:21.131 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:14:21.131 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:14:21.131 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:14:21.131 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:14:21.131 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:14:21.131 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:14:21.131 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:14:21.131 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:14:21.131 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:14:21.132 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:14:21.132 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:14:21.132 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:14:21.132 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:14:21.132 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:14:21.132 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:14:21.132 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:14:21.132 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:14:21.132 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:14:21.135 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-01-29 02:14:21.618 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-01-29 02:14:21.654 [DEBUG] fake_trx.py:278 (BTS@172.18.28.20:5700) Recv FAKE_TOA cmd
2026-01-29 02:14:21.655 [DEBUG] fake_trx.py:297 (BTS@172.18.28.20:5700) Recv FAKE_RSSI cmd
2026-01-29 02:14:21.656 [DEBUG] fake_trx.py:322 (BTS@172.18.28.20:5700) Recv FAKE_CI cmd
2026-01-29 02:14:21.657 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:14:21.671 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 02:14:21.671 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 02:14:21.671 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 02:14:21.704 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:14:21.704 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 02:14:21.704 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 02:14:21.704 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.28.22:6700) Recv POWERON CMD
2026-01-29 02:14:21.704 [INFO] ctrl_if_trx.py:109 (MS@172.18.28.22:6700) Starting transceiver...
2026-01-29 02:14:21.711 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:14:21.716 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 02:14:21.717 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 02:14:21.717 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:14:21.717 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:14:22.096 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-01-29 02:14:22.134 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 02:14:22.134 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:14:22.135 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:14:22.138 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:14:22.422 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:14:22.424 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:14:22.430 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 02:14:22.431 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 02:14:22.441 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 02:14:22.442 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:14:22.442 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:14:22.442 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:14:22.444 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 02:14:22.444 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:14:22.444 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:14:22.444 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:14:22.444 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.28.20:5700) Recv POWEROFF cmd
2026-01-29 02:14:22.444 [INFO] ctrl_if_trx.py:117 (BTS@172.18.28.20:5700) Stopping transceiver...
2026-01-29 02:14:22.444 [INFO] transceiver.py:246 Stopping clock generator
2026-01-29 02:14:22.444 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=280 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:14:22.444 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=280 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:14:22.444 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=280 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:14:22.444 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=280 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:14:22.444 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=280 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:14:22.444 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=280 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:14:22.444 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=281 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:14:22.444 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=281 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:14:22.444 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=281 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:14:22.444 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=281 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:14:22.444 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=281 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:14:22.444 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=281 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:14:22.445 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=281 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:14:22.445 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=281 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:14:27.445 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.28.20:5700) Recv POWEROFF cmd
2026-01-29 02:14:27.445 [INFO] ctrl_if_trx.py:117 (BTS@172.18.28.20:5700) Stopping transceiver...
2026-01-29 02:14:27.447 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:14:27.448 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:14:27.449 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:14:27.449 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 02:14:27.459 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 02:14:27.461 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.28.20:5700) Recv SETFORMAT cmd
2026-01-29 02:14:27.461 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.28.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:14:27.462 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.28.20:5700) Recv SETFORMAT cmd
2026-01-29 02:14:27.462 [INFO] ctrl_if_trx.py:201 (BTS@172.18.28.20:5700) TRXD header version 1 -> 1
2026-01-29 02:14:27.465 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.28.20:5700/1) Recv RXTUNE cmd
2026-01-29 02:14:27.466 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.28.20:5700/1) Recv TXTUNE cmd
2026-01-29 02:14:27.466 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.28.20:5700/1) Recv SETFORMAT cmd
2026-01-29 02:14:27.466 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.28.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:14:27.467 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:14:27.467 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.28.20:5700/1) Recv NOMTXPOWER cmd
2026-01-29 02:14:27.468 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.28.20:5700/1) Recv SETFORMAT cmd
2026-01-29 02:14:27.468 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.28.20:5700/1) TRXD header version 1 -> 1
2026-01-29 02:14:27.469 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.28.20:5700/2) Recv RXTUNE cmd
2026-01-29 02:14:27.470 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.28.20:5700/2) Recv TXTUNE cmd
2026-01-29 02:14:27.470 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.28.20:5700/2) Recv SETFORMAT cmd
2026-01-29 02:14:27.470 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.28.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:14:27.470 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:14:27.470 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.28.20:5700/2) Recv NOMTXPOWER cmd
2026-01-29 02:14:27.470 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.28.20:5700/2) Recv SETFORMAT cmd
2026-01-29 02:14:27.470 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.28.20:5700/2) TRXD header version 1 -> 1
2026-01-29 02:14:27.472 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.28.20:5700/3) Recv RXTUNE cmd
2026-01-29 02:14:27.472 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.28.20:5700/3) Recv TXTUNE cmd
2026-01-29 02:14:27.473 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.28.20:5700/3) Recv SETFORMAT cmd
2026-01-29 02:14:27.473 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.28.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:14:27.473 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:14:27.473 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.28.20:5700/3) Recv NOMTXPOWER cmd
2026-01-29 02:14:27.473 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.28.20:5700/3) Recv SETFORMAT cmd
2026-01-29 02:14:27.473 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.28.20:5700/3) TRXD header version 1 -> 1
2026-01-29 02:14:27.476 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.28.20:5700) Recv RXTUNE cmd
2026-01-29 02:14:27.476 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETTSC
2026-01-29 02:14:27.476 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETTSC
2026-01-29 02:14:27.476 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETTSC
2026-01-29 02:14:27.476 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.28.20:5700) Recv TXTUNE cmd
2026-01-29 02:14:27.476 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETRXGAIN
2026-01-29 02:14:27.476 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETRXGAIN
2026-01-29 02:14:27.476 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETRXGAIN
2026-01-29 02:14:27.476 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETTSC
2026-01-29 02:14:27.476 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:14:27.476 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:14:27.476 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.28.20:5700) Recv NOMTXPOWER cmd
2026-01-29 02:14:27.476 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:14:27.476 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:14:27.476 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:14:27.476 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.28.20:5700) Recv POWERON CMD
2026-01-29 02:14:27.476 [INFO] ctrl_if_trx.py:109 (BTS@172.18.28.20:5700) Starting transceiver...
2026-01-29 02:14:27.476 [INFO] transceiver.py:243 Starting clock generator
2026-01-29 02:14:27.477 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-01-29 02:14:27.477 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:14:27.477 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:14:27.477 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:14:27.477 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETRXGAIN
2026-01-29 02:14:27.477 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:14:27.477 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:14:27.477 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:14:27.477 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:14:27.477 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:14:27.477 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:14:27.477 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:14:27.477 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:14:27.477 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:14:27.477 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:14:27.477 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:14:27.477 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:14:27.478 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:14:27.478 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:14:27.478 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:14:27.478 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:14:27.478 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:14:27.478 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:14:27.478 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:14:27.478 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:14:27.478 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:14:27.478 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:14:27.478 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:14:27.478 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:14:27.481 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-01-29 02:14:27.963 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-01-29 02:14:28.006 [DEBUG] fake_trx.py:278 (BTS@172.18.28.20:5700) Recv FAKE_TOA cmd
2026-01-29 02:14:28.006 [DEBUG] fake_trx.py:297 (BTS@172.18.28.20:5700) Recv FAKE_RSSI cmd
2026-01-29 02:14:28.006 [DEBUG] fake_trx.py:322 (BTS@172.18.28.20:5700) Recv FAKE_CI cmd
2026-01-29 02:14:28.007 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:14:28.018 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 02:14:28.018 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 02:14:28.019 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 02:14:28.050 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:14:28.050 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 02:14:28.050 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 02:14:28.050 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.28.22:6700) Recv POWERON CMD
2026-01-29 02:14:28.050 [INFO] ctrl_if_trx.py:109 (MS@172.18.28.22:6700) Starting transceiver...
2026-01-29 02:14:28.056 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:14:28.061 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 02:14:28.061 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 02:14:28.061 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:14:28.061 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:14:28.439 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-01-29 02:14:28.480 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 02:14:28.481 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:14:28.482 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:14:28.487 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:14:28.766 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:14:28.768 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:14:28.774 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 02:14:28.774 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 02:14:28.785 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 02:14:28.786 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:14:28.786 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:14:28.786 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:14:28.792 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 02:14:28.792 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:14:28.792 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:14:28.792 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:14:28.792 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.28.20:5700) Recv POWEROFF cmd
2026-01-29 02:14:28.792 [INFO] ctrl_if_trx.py:117 (BTS@172.18.28.20:5700) Stopping transceiver...
2026-01-29 02:14:28.792 [INFO] transceiver.py:246 Stopping clock generator
2026-01-29 02:14:28.793 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=281 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:14:28.793 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=281 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:14:28.793 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=281 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:14:28.793 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=282 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:14:28.793 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=282 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:14:28.793 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=282 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:14:28.793 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=282 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:14:28.793 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=282 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:14:28.794 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=282 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:14:28.794 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=282 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:14:28.794 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=282 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:14:33.787 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.28.20:5700) Recv POWEROFF cmd
2026-01-29 02:14:33.787 [INFO] ctrl_if_trx.py:117 (BTS@172.18.28.20:5700) Stopping transceiver...
2026-01-29 02:14:33.789 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:14:33.791 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:14:33.791 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:14:33.791 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 02:14:33.794 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 02:14:33.794 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.28.20:5700) Recv SETFORMAT cmd
2026-01-29 02:14:33.794 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.28.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:14:33.794 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.28.20:5700) Recv SETFORMAT cmd
2026-01-29 02:14:33.794 [INFO] ctrl_if_trx.py:201 (BTS@172.18.28.20:5700) TRXD header version 1 -> 1
2026-01-29 02:14:33.796 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.28.20:5700/1) Recv RXTUNE cmd
2026-01-29 02:14:33.796 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.28.20:5700/1) Recv TXTUNE cmd
2026-01-29 02:14:33.796 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.28.20:5700/1) Recv SETFORMAT cmd
2026-01-29 02:14:33.796 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.28.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:14:33.796 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:14:33.796 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.28.20:5700/1) Recv NOMTXPOWER cmd
2026-01-29 02:14:33.796 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.28.20:5700/1) Recv SETFORMAT cmd
2026-01-29 02:14:33.796 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.28.20:5700/1) TRXD header version 1 -> 1
2026-01-29 02:14:33.798 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.28.20:5700/2) Recv RXTUNE cmd
2026-01-29 02:14:33.798 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.28.20:5700/2) Recv TXTUNE cmd
2026-01-29 02:14:33.798 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.28.20:5700/2) Recv SETFORMAT cmd
2026-01-29 02:14:33.798 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.28.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:14:33.798 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:14:33.799 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.28.20:5700/2) Recv NOMTXPOWER cmd
2026-01-29 02:14:33.799 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.28.20:5700/2) Recv SETFORMAT cmd
2026-01-29 02:14:33.799 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.28.20:5700/2) TRXD header version 1 -> 1
2026-01-29 02:14:33.800 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.28.20:5700/3) Recv RXTUNE cmd
2026-01-29 02:14:33.800 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.28.20:5700/3) Recv TXTUNE cmd
2026-01-29 02:14:33.800 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.28.20:5700/3) Recv SETFORMAT cmd
2026-01-29 02:14:33.800 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.28.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:14:33.800 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:14:33.800 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.28.20:5700/3) Recv NOMTXPOWER cmd
2026-01-29 02:14:33.800 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.28.20:5700/3) Recv SETFORMAT cmd
2026-01-29 02:14:33.800 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.28.20:5700/3) TRXD header version 1 -> 1
2026-01-29 02:14:33.802 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.28.20:5700) Recv RXTUNE cmd
2026-01-29 02:14:33.802 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETTSC
2026-01-29 02:14:33.802 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETTSC
2026-01-29 02:14:33.802 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETTSC
2026-01-29 02:14:33.802 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.28.20:5700) Recv TXTUNE cmd
2026-01-29 02:14:33.803 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETRXGAIN
2026-01-29 02:14:33.803 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETRXGAIN
2026-01-29 02:14:33.803 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETRXGAIN
2026-01-29 02:14:33.803 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETTSC
2026-01-29 02:14:33.803 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:14:33.803 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:14:33.803 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:14:33.803 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.28.20:5700) Recv NOMTXPOWER cmd
2026-01-29 02:14:33.803 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:14:33.803 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:14:33.803 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:14:33.803 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.28.20:5700) Recv POWERON CMD
2026-01-29 02:14:33.803 [INFO] ctrl_if_trx.py:109 (BTS@172.18.28.20:5700) Starting transceiver...
2026-01-29 02:14:33.803 [INFO] transceiver.py:243 Starting clock generator
2026-01-29 02:14:33.803 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-01-29 02:14:33.803 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:14:33.803 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:14:33.803 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:14:33.803 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETRXGAIN
2026-01-29 02:14:33.803 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:14:33.803 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:14:33.803 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:14:33.803 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:14:33.803 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:14:33.803 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:14:33.803 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:14:33.803 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:14:33.803 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:14:33.803 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:14:33.804 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:14:33.804 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:14:33.804 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:14:33.804 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:14:33.804 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:14:33.804 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:14:33.804 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:14:33.804 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:14:33.804 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:14:33.804 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:14:33.804 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:14:33.804 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:14:33.804 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:14:33.808 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-01-29 02:14:34.292 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-01-29 02:14:34.323 [DEBUG] fake_trx.py:278 (BTS@172.18.28.20:5700) Recv FAKE_TOA cmd
2026-01-29 02:14:34.326 [DEBUG] fake_trx.py:297 (BTS@172.18.28.20:5700) Recv FAKE_RSSI cmd
2026-01-29 02:14:34.326 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:14:34.327 [DEBUG] fake_trx.py:322 (BTS@172.18.28.20:5700) Recv FAKE_CI cmd
2026-01-29 02:14:34.338 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 02:14:34.338 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 02:14:34.339 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 02:14:34.377 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:14:34.377 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 02:14:34.377 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 02:14:34.377 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.28.22:6700) Recv POWERON CMD
2026-01-29 02:14:34.378 [INFO] ctrl_if_trx.py:109 (MS@172.18.28.22:6700) Starting transceiver...
2026-01-29 02:14:34.386 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:14:34.390 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 02:14:34.391 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 02:14:34.391 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:14:34.391 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:14:34.766 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-01-29 02:14:34.805 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 02:14:34.806 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:14:34.806 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:14:34.808 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:14:35.127 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:14:35.128 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:14:35.135 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 02:14:35.135 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 02:14:35.147 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 02:14:35.147 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:14:35.148 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:14:35.148 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:14:35.153 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 02:14:35.153 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:14:35.153 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:14:35.154 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:14:35.154 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.28.20:5700) Recv POWEROFF cmd
2026-01-29 02:14:35.154 [INFO] ctrl_if_trx.py:117 (BTS@172.18.28.20:5700) Stopping transceiver...
2026-01-29 02:14:35.154 [INFO] transceiver.py:246 Stopping clock generator
2026-01-29 02:14:35.154 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=290 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:14:35.154 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=290 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:14:35.155 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=290 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:14:35.155 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=290 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:14:35.155 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=290 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:14:35.155 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=290 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:14:40.149 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.28.20:5700) Recv POWEROFF cmd
2026-01-29 02:14:40.149 [INFO] ctrl_if_trx.py:117 (BTS@172.18.28.20:5700) Stopping transceiver...
2026-01-29 02:14:40.150 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:14:40.152 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:14:40.152 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:14:40.153 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 02:14:40.165 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 02:14:40.167 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.28.20:5700) Recv SETFORMAT cmd
2026-01-29 02:14:40.167 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.28.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:14:40.167 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.28.20:5700) Recv SETFORMAT cmd
2026-01-29 02:14:40.167 [INFO] ctrl_if_trx.py:201 (BTS@172.18.28.20:5700) TRXD header version 1 -> 1
2026-01-29 02:14:40.169 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.28.20:5700/1) Recv RXTUNE cmd
2026-01-29 02:14:40.169 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.28.20:5700/1) Recv TXTUNE cmd
2026-01-29 02:14:40.170 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.28.20:5700/1) Recv SETFORMAT cmd
2026-01-29 02:14:40.170 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.28.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:14:40.170 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:14:40.171 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.28.20:5700/1) Recv NOMTXPOWER cmd
2026-01-29 02:14:40.171 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.28.20:5700/1) Recv SETFORMAT cmd
2026-01-29 02:14:40.171 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.28.20:5700/1) TRXD header version 1 -> 1
2026-01-29 02:14:40.172 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.28.20:5700/2) Recv RXTUNE cmd
2026-01-29 02:14:40.172 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.28.20:5700/2) Recv TXTUNE cmd
2026-01-29 02:14:40.172 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.28.20:5700/2) Recv SETFORMAT cmd
2026-01-29 02:14:40.172 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.28.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:14:40.173 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:14:40.173 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.28.20:5700/2) Recv NOMTXPOWER cmd
2026-01-29 02:14:40.173 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.28.20:5700/2) Recv SETFORMAT cmd
2026-01-29 02:14:40.173 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.28.20:5700/2) TRXD header version 1 -> 1
2026-01-29 02:14:40.175 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.28.20:5700/3) Recv RXTUNE cmd
2026-01-29 02:14:40.175 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.28.20:5700/3) Recv TXTUNE cmd
2026-01-29 02:14:40.175 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.28.20:5700/3) Recv SETFORMAT cmd
2026-01-29 02:14:40.175 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.28.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:14:40.175 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:14:40.175 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.28.20:5700/3) Recv NOMTXPOWER cmd
2026-01-29 02:14:40.175 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.28.20:5700/3) Recv SETFORMAT cmd
2026-01-29 02:14:40.175 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.28.20:5700/3) TRXD header version 1 -> 1
2026-01-29 02:14:40.178 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.28.20:5700) Recv RXTUNE cmd
2026-01-29 02:14:40.178 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETTSC
2026-01-29 02:14:40.178 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETTSC
2026-01-29 02:14:40.178 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETTSC
2026-01-29 02:14:40.178 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.28.20:5700) Recv TXTUNE cmd
2026-01-29 02:14:40.178 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETRXGAIN
2026-01-29 02:14:40.178 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETRXGAIN
2026-01-29 02:14:40.178 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETRXGAIN
2026-01-29 02:14:40.178 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETTSC
2026-01-29 02:14:40.178 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:14:40.178 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:14:40.178 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.28.20:5700) Recv NOMTXPOWER cmd
2026-01-29 02:14:40.179 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:14:40.179 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:14:40.179 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:14:40.179 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.28.20:5700) Recv POWERON CMD
2026-01-29 02:14:40.179 [INFO] ctrl_if_trx.py:109 (BTS@172.18.28.20:5700) Starting transceiver...
2026-01-29 02:14:40.179 [INFO] transceiver.py:243 Starting clock generator
2026-01-29 02:14:40.179 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-01-29 02:14:40.179 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:14:40.179 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:14:40.179 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:14:40.179 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETRXGAIN
2026-01-29 02:14:40.179 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:14:40.179 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:14:40.179 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:14:40.179 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:14:40.179 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:14:40.179 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:14:40.179 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:14:40.179 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:14:40.180 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:14:40.180 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:14:40.180 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:14:40.180 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:14:40.180 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:14:40.180 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:14:40.180 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:14:40.180 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:14:40.180 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:14:40.180 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:14:40.180 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:14:40.180 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:14:40.180 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:14:40.180 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:14:40.180 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:14:40.180 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:14:40.184 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-01-29 02:14:40.667 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-01-29 02:14:40.710 [DEBUG] fake_trx.py:278 (BTS@172.18.28.20:5700) Recv FAKE_TOA cmd
2026-01-29 02:14:40.712 [DEBUG] fake_trx.py:297 (BTS@172.18.28.20:5700) Recv FAKE_RSSI cmd
2026-01-29 02:14:40.715 [DEBUG] fake_trx.py:322 (BTS@172.18.28.20:5700) Recv FAKE_CI cmd
2026-01-29 02:14:40.715 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:14:40.744 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 02:14:40.744 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 02:14:40.744 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 02:14:40.791 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:14:40.792 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 02:14:40.792 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 02:14:40.792 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.28.22:6700) Recv POWERON CMD
2026-01-29 02:14:40.792 [INFO] ctrl_if_trx.py:109 (MS@172.18.28.22:6700) Starting transceiver...
2026-01-29 02:14:40.808 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:14:40.813 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 02:14:40.813 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 02:14:40.813 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:14:40.814 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:14:41.143 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-01-29 02:14:41.183 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:14:41.183 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 02:14:41.184 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:14:41.188 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:14:41.621 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-01-29 02:14:41.672 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:14:41.674 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:14:41.680 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 02:14:41.680 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 02:14:41.693 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 02:14:41.694 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:14:41.694 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:14:41.694 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:14:41.695 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 02:14:41.695 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:14:41.695 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:14:41.695 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.28.20:5700) Recv POWEROFF cmd
2026-01-29 02:14:41.695 [INFO] ctrl_if_trx.py:117 (BTS@172.18.28.20:5700) Stopping transceiver...
2026-01-29 02:14:41.695 [INFO] transceiver.py:246 Stopping clock generator
2026-01-29 02:14:41.695 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:14:41.695 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=324 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:14:46.695 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.28.20:5700) Recv POWEROFF cmd
2026-01-29 02:14:46.696 [INFO] ctrl_if_trx.py:117 (BTS@172.18.28.20:5700) Stopping transceiver...
2026-01-29 02:14:46.697 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:14:46.698 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:14:46.698 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:14:46.699 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 02:14:46.707 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 02:14:46.708 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.28.20:5700) Recv SETFORMAT cmd
2026-01-29 02:14:46.709 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.28.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:14:46.709 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.28.20:5700) Recv SETFORMAT cmd
2026-01-29 02:14:46.709 [INFO] ctrl_if_trx.py:201 (BTS@172.18.28.20:5700) TRXD header version 1 -> 1
2026-01-29 02:14:46.711 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.28.20:5700/1) Recv RXTUNE cmd
2026-01-29 02:14:46.711 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.28.20:5700/1) Recv TXTUNE cmd
2026-01-29 02:14:46.711 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.28.20:5700/1) Recv SETFORMAT cmd
2026-01-29 02:14:46.711 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.28.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:14:46.712 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:14:46.712 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.28.20:5700/1) Recv NOMTXPOWER cmd
2026-01-29 02:14:46.712 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.28.20:5700/1) Recv SETFORMAT cmd
2026-01-29 02:14:46.712 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.28.20:5700/1) TRXD header version 1 -> 1
2026-01-29 02:14:46.713 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.28.20:5700/2) Recv RXTUNE cmd
2026-01-29 02:14:46.713 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.28.20:5700/2) Recv TXTUNE cmd
2026-01-29 02:14:46.713 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.28.20:5700/2) Recv SETFORMAT cmd
2026-01-29 02:14:46.714 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.28.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:14:46.714 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:14:46.714 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.28.20:5700/2) Recv NOMTXPOWER cmd
2026-01-29 02:14:46.714 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.28.20:5700/2) Recv SETFORMAT cmd
2026-01-29 02:14:46.714 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.28.20:5700/2) TRXD header version 1 -> 1
2026-01-29 02:14:46.716 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.28.20:5700/3) Recv RXTUNE cmd
2026-01-29 02:14:46.716 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.28.20:5700/3) Recv TXTUNE cmd
2026-01-29 02:14:46.716 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.28.20:5700/3) Recv SETFORMAT cmd
2026-01-29 02:14:46.716 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.28.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:14:46.716 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:14:46.716 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.28.20:5700/3) Recv NOMTXPOWER cmd
2026-01-29 02:14:46.716 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.28.20:5700/3) Recv SETFORMAT cmd
2026-01-29 02:14:46.716 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.28.20:5700/3) TRXD header version 1 -> 1
2026-01-29 02:14:46.718 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.28.20:5700) Recv RXTUNE cmd
2026-01-29 02:14:46.719 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETTSC
2026-01-29 02:14:46.719 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETTSC
2026-01-29 02:14:46.719 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETTSC
2026-01-29 02:14:46.719 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.28.20:5700) Recv TXTUNE cmd
2026-01-29 02:14:46.719 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETRXGAIN
2026-01-29 02:14:46.719 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETRXGAIN
2026-01-29 02:14:46.719 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETRXGAIN
2026-01-29 02:14:46.719 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETTSC
2026-01-29 02:14:46.719 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:14:46.719 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:14:46.719 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:14:46.719 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.28.20:5700) Recv NOMTXPOWER cmd
2026-01-29 02:14:46.719 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:14:46.719 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:14:46.719 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:14:46.719 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.28.20:5700) Recv POWERON CMD
2026-01-29 02:14:46.719 [INFO] ctrl_if_trx.py:109 (BTS@172.18.28.20:5700) Starting transceiver...
2026-01-29 02:14:46.719 [INFO] transceiver.py:243 Starting clock generator
2026-01-29 02:14:46.719 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-01-29 02:14:46.720 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:14:46.720 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:14:46.720 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:14:46.720 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETRXGAIN
2026-01-29 02:14:46.720 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:14:46.720 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:14:46.720 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:14:46.720 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:14:46.720 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:14:46.720 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:14:46.720 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:14:46.720 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:14:46.720 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:14:46.720 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:14:46.720 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:14:46.720 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:14:46.720 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:14:46.720 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:14:46.720 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:14:46.720 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:14:46.720 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:14:46.720 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:14:46.720 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:14:46.720 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:14:46.720 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:14:46.720 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:14:46.720 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:14:46.724 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-01-29 02:14:47.206 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-01-29 02:14:47.244 [DEBUG] fake_trx.py:278 (BTS@172.18.28.20:5700) Recv FAKE_TOA cmd
2026-01-29 02:14:47.246 [DEBUG] fake_trx.py:297 (BTS@172.18.28.20:5700) Recv FAKE_RSSI cmd
2026-01-29 02:14:47.247 [DEBUG] fake_trx.py:322 (BTS@172.18.28.20:5700) Recv FAKE_CI cmd
2026-01-29 02:14:47.247 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:14:47.261 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 02:14:47.262 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 02:14:47.262 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 02:14:47.290 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:14:47.290 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 02:14:47.290 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 02:14:47.291 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.28.22:6700) Recv POWERON CMD
2026-01-29 02:14:47.291 [INFO] ctrl_if_trx.py:109 (MS@172.18.28.22:6700) Starting transceiver...
2026-01-29 02:14:47.301 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:14:47.305 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 02:14:47.306 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 02:14:47.306 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:14:47.306 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:14:47.683 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-01-29 02:14:47.722 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 02:14:47.722 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:14:47.723 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:14:47.725 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:14:48.010 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:14:48.011 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:14:48.017 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 02:14:48.017 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 02:14:48.028 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 02:14:48.028 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:14:48.028 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:14:48.028 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:14:48.035 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 02:14:48.035 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:14:48.035 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:14:48.035 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:14:48.036 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.28.20:5700) Recv POWEROFF cmd
2026-01-29 02:14:48.036 [INFO] ctrl_if_trx.py:117 (BTS@172.18.28.20:5700) Stopping transceiver...
2026-01-29 02:14:48.036 [INFO] transceiver.py:246 Stopping clock generator
2026-01-29 02:14:48.036 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=280 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:14:48.036 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=280 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:14:48.036 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=281 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:14:48.036 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=281 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:14:48.037 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=281 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:14:48.037 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=281 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:14:48.037 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=281 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:14:48.037 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=281 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:14:48.037 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=281 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:14:48.037 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=281 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:14:48.037 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=282 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:14:48.037 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=282 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:14:48.037 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=282 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:14:48.037 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=282 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:14:48.037 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=282 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:14:48.037 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=282 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:14:48.038 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=282 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:14:48.038 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=282 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:14:53.033 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.28.20:5700) Recv POWEROFF cmd
2026-01-29 02:14:53.033 [INFO] ctrl_if_trx.py:117 (BTS@172.18.28.20:5700) Stopping transceiver...
2026-01-29 02:14:53.035 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:14:53.035 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:14:53.036 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:14:53.036 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 02:14:53.039 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 02:14:53.040 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.28.20:5700) Recv SETFORMAT cmd
2026-01-29 02:14:53.040 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.28.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:14:53.040 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.28.20:5700) Recv SETFORMAT cmd
2026-01-29 02:14:53.040 [INFO] ctrl_if_trx.py:201 (BTS@172.18.28.20:5700) TRXD header version 1 -> 1
2026-01-29 02:14:53.042 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.28.20:5700/1) Recv RXTUNE cmd
2026-01-29 02:14:53.043 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.28.20:5700/1) Recv TXTUNE cmd
2026-01-29 02:14:53.043 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.28.20:5700/1) Recv SETFORMAT cmd
2026-01-29 02:14:53.043 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.28.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:14:53.043 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:14:53.043 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.28.20:5700/1) Recv NOMTXPOWER cmd
2026-01-29 02:14:53.043 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.28.20:5700/1) Recv SETFORMAT cmd
2026-01-29 02:14:53.043 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.28.20:5700/1) TRXD header version 1 -> 1
2026-01-29 02:14:53.045 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.28.20:5700/2) Recv RXTUNE cmd
2026-01-29 02:14:53.045 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.28.20:5700/2) Recv TXTUNE cmd
2026-01-29 02:14:53.045 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.28.20:5700/2) Recv SETFORMAT cmd
2026-01-29 02:14:53.045 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.28.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:14:53.045 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:14:53.045 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.28.20:5700/2) Recv NOMTXPOWER cmd
2026-01-29 02:14:53.045 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.28.20:5700/2) Recv SETFORMAT cmd
2026-01-29 02:14:53.045 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.28.20:5700/2) TRXD header version 1 -> 1
2026-01-29 02:14:53.046 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.28.20:5700/3) Recv RXTUNE cmd
2026-01-29 02:14:53.046 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.28.20:5700/3) Recv TXTUNE cmd
2026-01-29 02:14:53.046 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.28.20:5700/3) Recv SETFORMAT cmd
2026-01-29 02:14:53.046 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.28.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:14:53.047 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:14:53.047 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.28.20:5700/3) Recv NOMTXPOWER cmd
2026-01-29 02:14:53.047 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.28.20:5700/3) Recv SETFORMAT cmd
2026-01-29 02:14:53.047 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.28.20:5700/3) TRXD header version 1 -> 1
2026-01-29 02:14:53.048 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.28.20:5700) Recv RXTUNE cmd
2026-01-29 02:14:53.048 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETTSC
2026-01-29 02:14:53.048 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETTSC
2026-01-29 02:14:53.049 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETTSC
2026-01-29 02:14:53.049 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.28.20:5700) Recv TXTUNE cmd
2026-01-29 02:14:53.049 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETRXGAIN
2026-01-29 02:14:53.049 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETRXGAIN
2026-01-29 02:14:53.049 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETRXGAIN
2026-01-29 02:14:53.049 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETTSC
2026-01-29 02:14:53.049 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:14:53.049 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:14:53.049 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:14:53.049 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.28.20:5700) Recv NOMTXPOWER cmd
2026-01-29 02:14:53.049 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:14:53.049 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:14:53.049 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:14:53.049 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.28.20:5700) Recv POWERON CMD
2026-01-29 02:14:53.049 [INFO] ctrl_if_trx.py:109 (BTS@172.18.28.20:5700) Starting transceiver...
2026-01-29 02:14:53.049 [INFO] transceiver.py:243 Starting clock generator
2026-01-29 02:14:53.049 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-01-29 02:14:53.049 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:14:53.049 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:14:53.049 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:14:53.049 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETRXGAIN
2026-01-29 02:14:53.049 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:14:53.049 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:14:53.049 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:14:53.049 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:14:53.049 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:14:53.049 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:14:53.049 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:14:53.049 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:14:53.050 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:14:53.050 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:14:53.050 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:14:53.050 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:14:53.050 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:14:53.050 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:14:53.050 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:14:53.050 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:14:53.050 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:14:53.050 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:14:53.050 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:14:53.050 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:14:53.050 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:14:53.050 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:14:53.050 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:14:53.054 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-01-29 02:14:53.536 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-01-29 02:14:53.572 [DEBUG] fake_trx.py:278 (BTS@172.18.28.20:5700) Recv FAKE_TOA cmd
2026-01-29 02:14:53.574 [DEBUG] fake_trx.py:297 (BTS@172.18.28.20:5700) Recv FAKE_RSSI cmd
2026-01-29 02:14:53.574 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:14:53.574 [DEBUG] fake_trx.py:322 (BTS@172.18.28.20:5700) Recv FAKE_CI cmd
2026-01-29 02:14:53.594 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 02:14:53.594 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 02:14:53.594 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 02:14:53.643 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:14:53.643 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 02:14:53.644 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 02:14:53.644 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.28.22:6700) Recv POWERON CMD
2026-01-29 02:14:53.644 [INFO] ctrl_if_trx.py:109 (MS@172.18.28.22:6700) Starting transceiver...
2026-01-29 02:14:53.675 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:14:53.680 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 02:14:53.680 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 02:14:53.681 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:14:53.681 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:14:54.012 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-01-29 02:14:54.051 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:14:54.051 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 02:14:54.053 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:14:54.054 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:14:54.490 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-01-29 02:14:54.540 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:14:54.542 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:14:54.548 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 02:14:54.548 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 02:14:54.559 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 02:14:54.559 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:14:54.559 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:14:54.559 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:14:54.565 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 02:14:54.565 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:14:54.565 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:14:54.565 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:14:54.566 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.28.20:5700) Recv POWEROFF cmd
2026-01-29 02:14:54.566 [INFO] ctrl_if_trx.py:117 (BTS@172.18.28.20:5700) Stopping transceiver...
2026-01-29 02:14:54.566 [INFO] transceiver.py:246 Stopping clock generator
2026-01-29 02:14:54.566 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=323 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:14:54.566 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=323 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:14:54.566 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=323 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:14:54.567 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=323 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:14:54.567 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=323 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:14:54.567 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=323 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:14:54.567 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=324 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:14:54.567 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=324 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:14:54.567 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=324 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:14:54.567 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=324 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:14:54.567 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=324 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:14:54.567 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=324 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:14:54.567 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=324 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:14:54.567 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=324 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:14:59.560 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.28.20:5700) Recv POWEROFF cmd
2026-01-29 02:14:59.560 [INFO] ctrl_if_trx.py:117 (BTS@172.18.28.20:5700) Stopping transceiver...
2026-01-29 02:14:59.562 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:14:59.563 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:14:59.564 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:14:59.564 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 02:14:59.570 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 02:14:59.571 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.28.20:5700) Recv SETFORMAT cmd
2026-01-29 02:14:59.572 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.28.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:14:59.572 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.28.20:5700) Recv SETFORMAT cmd
2026-01-29 02:14:59.572 [INFO] ctrl_if_trx.py:201 (BTS@172.18.28.20:5700) TRXD header version 1 -> 1
2026-01-29 02:14:59.574 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.28.20:5700/1) Recv RXTUNE cmd
2026-01-29 02:14:59.575 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.28.20:5700/1) Recv TXTUNE cmd
2026-01-29 02:14:59.575 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.28.20:5700/1) Recv SETFORMAT cmd
2026-01-29 02:14:59.575 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.28.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:14:59.576 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:14:59.576 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.28.20:5700/1) Recv NOMTXPOWER cmd
2026-01-29 02:14:59.577 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.28.20:5700/1) Recv SETFORMAT cmd
2026-01-29 02:14:59.577 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.28.20:5700/1) TRXD header version 1 -> 1
2026-01-29 02:14:59.578 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.28.20:5700/2) Recv RXTUNE cmd
2026-01-29 02:14:59.578 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.28.20:5700/2) Recv TXTUNE cmd
2026-01-29 02:14:59.578 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.28.20:5700/2) Recv SETFORMAT cmd
2026-01-29 02:14:59.578 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.28.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:14:59.578 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:14:59.578 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.28.20:5700/2) Recv NOMTXPOWER cmd
2026-01-29 02:14:59.578 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.28.20:5700/2) Recv SETFORMAT cmd
2026-01-29 02:14:59.578 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.28.20:5700/2) TRXD header version 1 -> 1
2026-01-29 02:14:59.580 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.28.20:5700/3) Recv RXTUNE cmd
2026-01-29 02:14:59.580 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.28.20:5700/3) Recv TXTUNE cmd
2026-01-29 02:14:59.580 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.28.20:5700/3) Recv SETFORMAT cmd
2026-01-29 02:14:59.580 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.28.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:14:59.580 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:14:59.581 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.28.20:5700/3) Recv NOMTXPOWER cmd
2026-01-29 02:14:59.581 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.28.20:5700/3) Recv SETFORMAT cmd
2026-01-29 02:14:59.581 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.28.20:5700/3) TRXD header version 1 -> 1
2026-01-29 02:14:59.583 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.28.20:5700) Recv RXTUNE cmd
2026-01-29 02:14:59.583 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETTSC
2026-01-29 02:14:59.583 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETTSC
2026-01-29 02:14:59.583 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETTSC
2026-01-29 02:14:59.583 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.28.20:5700) Recv TXTUNE cmd
2026-01-29 02:14:59.584 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETRXGAIN
2026-01-29 02:14:59.584 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETRXGAIN
2026-01-29 02:14:59.584 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETRXGAIN
2026-01-29 02:14:59.584 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETTSC
2026-01-29 02:14:59.584 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:14:59.584 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:14:59.584 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:14:59.584 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.28.20:5700) Recv NOMTXPOWER cmd
2026-01-29 02:14:59.584 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:14:59.584 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:14:59.584 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:14:59.584 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.28.20:5700) Recv POWERON CMD
2026-01-29 02:14:59.584 [INFO] ctrl_if_trx.py:109 (BTS@172.18.28.20:5700) Starting transceiver...
2026-01-29 02:14:59.584 [INFO] transceiver.py:243 Starting clock generator
2026-01-29 02:14:59.584 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-01-29 02:14:59.584 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:14:59.584 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:14:59.584 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:14:59.584 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETRXGAIN
2026-01-29 02:14:59.584 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:14:59.585 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:14:59.585 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:14:59.585 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:14:59.585 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:14:59.585 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:14:59.585 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:14:59.585 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:14:59.585 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:14:59.585 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:14:59.585 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:14:59.585 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:14:59.585 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:14:59.585 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:14:59.585 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:14:59.585 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:14:59.585 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:14:59.585 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:14:59.585 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:14:59.585 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:14:59.585 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:14:59.585 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:14:59.585 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:14:59.589 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-01-29 02:15:00.072 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-01-29 02:15:00.110 [DEBUG] fake_trx.py:278 (BTS@172.18.28.20:5700) Recv FAKE_TOA cmd
2026-01-29 02:15:00.110 [DEBUG] fake_trx.py:297 (BTS@172.18.28.20:5700) Recv FAKE_RSSI cmd
2026-01-29 02:15:00.110 [DEBUG] fake_trx.py:322 (BTS@172.18.28.20:5700) Recv FAKE_CI cmd
2026-01-29 02:15:00.111 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:15:00.123 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 02:15:00.123 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 02:15:00.123 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 02:15:00.126 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:15:00.126 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 02:15:00.126 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 02:15:00.126 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.28.22:6700) Recv POWERON CMD
2026-01-29 02:15:00.126 [INFO] ctrl_if_trx.py:109 (MS@172.18.28.22:6700) Starting transceiver...
2026-01-29 02:15:00.545 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-01-29 02:15:00.588 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:15:00.589 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 02:15:00.589 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:15:00.593 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:15:01.023 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-01-29 02:15:01.180 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:15:01.295 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:15:01.298 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 02:15:01.298 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 02:15:01.316 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 02:15:01.316 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 02:15:01.316 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 02:15:01.317 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:15:01.317 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 02:15:01.317 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 02:15:01.317 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.28.22:6700) Recv POWERON CMD
2026-01-29 02:15:01.317 [INFO] ctrl_if_trx.py:109 (MS@172.18.28.22:6700) Starting transceiver...
2026-01-29 02:15:01.501 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-01-29 02:15:01.589 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:15:01.590 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 02:15:01.590 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:15:01.594 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:15:01.979 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-01-29 02:15:02.365 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD NOHANDOVER
2026-01-29 02:15:02.457 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-01-29 02:15:02.494 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD NOHANDOVER
2026-01-29 02:15:02.497 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 02:15:02.497 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 02:15:02.507 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 02:15:02.507 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:15:02.507 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:15:02.508 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:15:02.513 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 02:15:02.514 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:15:02.514 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:15:02.514 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:15:02.514 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.28.20:5700) Recv POWEROFF cmd
2026-01-29 02:15:02.514 [INFO] ctrl_if_trx.py:117 (BTS@172.18.28.20:5700) Stopping transceiver...
2026-01-29 02:15:02.514 [INFO] transceiver.py:246 Stopping clock generator
2026-01-29 02:15:02.515 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=624 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:15:02.515 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=624 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:15:07.511 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.28.20:5700) Recv POWEROFF cmd
2026-01-29 02:15:07.511 [INFO] ctrl_if_trx.py:117 (BTS@172.18.28.20:5700) Stopping transceiver...
2026-01-29 02:15:07.513 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:15:07.514 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:15:07.514 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:15:07.514 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 02:15:07.523 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 02:15:07.524 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.28.20:5700) Recv SETFORMAT cmd
2026-01-29 02:15:07.524 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.28.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:15:07.525 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.28.20:5700) Recv SETFORMAT cmd
2026-01-29 02:15:07.525 [INFO] ctrl_if_trx.py:201 (BTS@172.18.28.20:5700) TRXD header version 1 -> 1
2026-01-29 02:15:07.529 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.28.20:5700/1) Recv RXTUNE cmd
2026-01-29 02:15:07.529 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.28.20:5700/1) Recv TXTUNE cmd
2026-01-29 02:15:07.530 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.28.20:5700/1) Recv SETFORMAT cmd
2026-01-29 02:15:07.530 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.28.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:15:07.530 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:15:07.531 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.28.20:5700/1) Recv NOMTXPOWER cmd
2026-01-29 02:15:07.531 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.28.20:5700/1) Recv SETFORMAT cmd
2026-01-29 02:15:07.531 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.28.20:5700/1) TRXD header version 1 -> 1
2026-01-29 02:15:07.533 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.28.20:5700/2) Recv RXTUNE cmd
2026-01-29 02:15:07.534 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.28.20:5700/2) Recv TXTUNE cmd
2026-01-29 02:15:07.534 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.28.20:5700/2) Recv SETFORMAT cmd
2026-01-29 02:15:07.534 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.28.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:15:07.534 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:15:07.534 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.28.20:5700/2) Recv NOMTXPOWER cmd
2026-01-29 02:15:07.535 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.28.20:5700/2) Recv SETFORMAT cmd
2026-01-29 02:15:07.535 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.28.20:5700/2) TRXD header version 1 -> 1
2026-01-29 02:15:07.536 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.28.20:5700/3) Recv RXTUNE cmd
2026-01-29 02:15:07.536 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.28.20:5700/3) Recv TXTUNE cmd
2026-01-29 02:15:07.537 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.28.20:5700/3) Recv SETFORMAT cmd
2026-01-29 02:15:07.537 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.28.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:15:07.537 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:15:07.537 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.28.20:5700/3) Recv NOMTXPOWER cmd
2026-01-29 02:15:07.537 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.28.20:5700/3) Recv SETFORMAT cmd
2026-01-29 02:15:07.537 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.28.20:5700/3) TRXD header version 1 -> 1
2026-01-29 02:15:07.540 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.28.20:5700) Recv RXTUNE cmd
2026-01-29 02:15:07.540 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETTSC
2026-01-29 02:15:07.540 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETTSC
2026-01-29 02:15:07.540 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETTSC
2026-01-29 02:15:07.540 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.28.20:5700) Recv TXTUNE cmd
2026-01-29 02:15:07.540 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETRXGAIN
2026-01-29 02:15:07.540 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETRXGAIN
2026-01-29 02:15:07.540 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETRXGAIN
2026-01-29 02:15:07.540 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETTSC
2026-01-29 02:15:07.540 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:15:07.540 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:15:07.540 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:15:07.540 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.28.20:5700) Recv NOMTXPOWER cmd
2026-01-29 02:15:07.540 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:15:07.540 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:15:07.540 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:15:07.540 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.28.20:5700) Recv POWERON CMD
2026-01-29 02:15:07.540 [INFO] ctrl_if_trx.py:109 (BTS@172.18.28.20:5700) Starting transceiver...
2026-01-29 02:15:07.540 [INFO] transceiver.py:243 Starting clock generator
2026-01-29 02:15:07.540 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-01-29 02:15:07.540 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:15:07.540 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:15:07.540 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:15:07.541 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETRXGAIN
2026-01-29 02:15:07.541 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:15:07.541 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:15:07.541 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:15:07.541 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:15:07.541 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:15:07.541 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:15:07.541 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:15:07.541 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:15:07.541 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:15:07.541 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:15:07.541 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:15:07.541 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:15:07.541 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:15:07.541 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:15:07.541 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:15:07.541 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:15:07.541 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:15:07.541 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:15:07.541 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:15:07.541 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:15:07.541 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:15:07.541 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:15:07.541 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:15:07.545 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-01-29 02:15:08.028 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-01-29 02:15:08.062 [DEBUG] fake_trx.py:278 (BTS@172.18.28.20:5700) Recv FAKE_TOA cmd
2026-01-29 02:15:08.063 [DEBUG] fake_trx.py:297 (BTS@172.18.28.20:5700) Recv FAKE_RSSI cmd
2026-01-29 02:15:08.064 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:15:08.065 [DEBUG] fake_trx.py:322 (BTS@172.18.28.20:5700) Recv FAKE_CI cmd
2026-01-29 02:15:08.084 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 02:15:08.084 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 02:15:08.084 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 02:15:08.507 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-01-29 02:15:08.544 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:15:08.544 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 02:15:08.544 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:15:08.546 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:15:08.988 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-01-29 02:15:09.469 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-01-29 02:15:09.545 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:15:09.545 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 02:15:09.546 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:15:09.547 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:15:09.950 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-01-29 02:15:10.431 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-01-29 02:15:10.546 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:15:10.546 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 02:15:10.546 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:15:10.548 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:15:10.909 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-01-29 02:15:11.389 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-01-29 02:15:11.547 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 02:15:11.547 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:15:11.547 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:15:11.550 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:15:11.870 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-01-29 02:15:12.342 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-01-29 02:15:12.548 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:15:12.548 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 02:15:12.548 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:15:12.551 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:15:12.811 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-01-29 02:15:13.280 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-01-29 02:15:13.748 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-01-29 02:15:14.094 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:15:14.095 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 02:15:14.095 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 02:15:14.096 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.28.22:6700) Recv POWERON CMD
2026-01-29 02:15:14.096 [INFO] ctrl_if_trx.py:109 (MS@172.18.28.22:6700) Starting transceiver...
2026-01-29 02:15:14.217 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-01-29 02:15:14.235 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD NOHANDOVER
2026-01-29 02:15:14.239 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 02:15:14.239 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 02:15:14.240 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:15:14.240 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:15:14.687 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-01-29 02:15:15.157 [DEBUG] clck_gen.py:113 IND CLOCK 1632
2026-01-29 02:15:15.628 [DEBUG] clck_gen.py:113 IND CLOCK 1734
2026-01-29 02:15:16.102 [DEBUG] clck_gen.py:113 IND CLOCK 1836
2026-01-29 02:15:16.581 [DEBUG] clck_gen.py:113 IND CLOCK 1938
2026-01-29 02:15:17.062 [DEBUG] clck_gen.py:113 IND CLOCK 2040
2026-01-29 02:15:17.540 [DEBUG] clck_gen.py:113 IND CLOCK 2142
2026-01-29 02:15:18.019 [DEBUG] clck_gen.py:113 IND CLOCK 2244
2026-01-29 02:15:18.497 [DEBUG] clck_gen.py:113 IND CLOCK 2346
2026-01-29 02:15:18.976 [DEBUG] clck_gen.py:113 IND CLOCK 2448
2026-01-29 02:15:19.451 [DEBUG] clck_gen.py:113 IND CLOCK 2550
2026-01-29 02:15:19.920 [DEBUG] clck_gen.py:113 IND CLOCK 2652
2026-01-29 02:15:20.389 [DEBUG] clck_gen.py:113 IND CLOCK 2754
2026-01-29 02:15:20.861 [DEBUG] clck_gen.py:113 IND CLOCK 2856
2026-01-29 02:15:21.339 [DEBUG] clck_gen.py:113 IND CLOCK 2958
2026-01-29 02:15:21.817 [DEBUG] clck_gen.py:113 IND CLOCK 3060
2026-01-29 02:15:22.296 [DEBUG] clck_gen.py:113 IND CLOCK 3162
2026-01-29 02:15:22.774 [DEBUG] clck_gen.py:113 IND CLOCK 3264
2026-01-29 02:15:23.253 [DEBUG] clck_gen.py:113 IND CLOCK 3366
2026-01-29 02:15:23.726 [DEBUG] clck_gen.py:113 IND CLOCK 3468
2026-01-29 02:15:24.196 [DEBUG] clck_gen.py:113 IND CLOCK 3570
2026-01-29 02:15:24.667 [DEBUG] clck_gen.py:113 IND CLOCK 3672
2026-01-29 02:15:25.146 [DEBUG] clck_gen.py:113 IND CLOCK 3774
2026-01-29 02:15:25.624 [DEBUG] clck_gen.py:113 IND CLOCK 3876
2026-01-29 02:15:26.102 [DEBUG] clck_gen.py:113 IND CLOCK 3978
2026-01-29 02:15:26.392 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD NOHANDOVER
2026-01-29 02:15:26.395 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:15:26.396 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 02:15:26.396 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 02:15:26.399 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 02:15:26.399 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:15:26.399 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:15:26.399 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:15:26.400 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 02:15:26.400 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:15:26.400 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:15:26.400 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.28.20:5700) Recv POWEROFF cmd
2026-01-29 02:15:26.400 [INFO] ctrl_if_trx.py:117 (BTS@172.18.28.20:5700) Stopping transceiver...
2026-01-29 02:15:26.400 [INFO] transceiver.py:246 Stopping clock generator
2026-01-29 02:15:26.400 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:15:31.402 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.28.20:5700) Recv POWEROFF cmd
2026-01-29 02:15:31.403 [INFO] ctrl_if_trx.py:117 (BTS@172.18.28.20:5700) Stopping transceiver...
2026-01-29 02:15:31.404 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:15:31.405 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:15:31.406 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:15:31.407 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 02:15:31.415 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 02:15:31.416 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.28.20:5700) Recv SETFORMAT cmd
2026-01-29 02:15:31.416 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.28.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:15:31.417 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.28.20:5700) Recv SETFORMAT cmd
2026-01-29 02:15:31.417 [INFO] ctrl_if_trx.py:201 (BTS@172.18.28.20:5700) TRXD header version 1 -> 1
2026-01-29 02:15:31.420 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.28.20:5700/1) Recv RXTUNE cmd
2026-01-29 02:15:31.420 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.28.20:5700/1) Recv TXTUNE cmd
2026-01-29 02:15:31.421 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.28.20:5700/1) Recv SETFORMAT cmd
2026-01-29 02:15:31.421 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.28.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:15:31.421 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:15:31.421 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.28.20:5700/1) Recv NOMTXPOWER cmd
2026-01-29 02:15:31.421 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.28.20:5700/1) Recv SETFORMAT cmd
2026-01-29 02:15:31.421 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.28.20:5700/1) TRXD header version 1 -> 1
2026-01-29 02:15:31.423 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.28.20:5700/2) Recv RXTUNE cmd
2026-01-29 02:15:31.423 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.28.20:5700/2) Recv TXTUNE cmd
2026-01-29 02:15:31.424 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.28.20:5700/2) Recv SETFORMAT cmd
2026-01-29 02:15:31.424 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.28.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:15:31.424 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:15:31.424 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.28.20:5700/2) Recv NOMTXPOWER cmd
2026-01-29 02:15:31.424 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.28.20:5700/2) Recv SETFORMAT cmd
2026-01-29 02:15:31.424 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.28.20:5700/2) TRXD header version 1 -> 1
2026-01-29 02:15:31.425 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.28.20:5700/3) Recv RXTUNE cmd
2026-01-29 02:15:31.426 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.28.20:5700/3) Recv TXTUNE cmd
2026-01-29 02:15:31.426 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.28.20:5700/3) Recv SETFORMAT cmd
2026-01-29 02:15:31.426 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.28.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:15:31.426 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:15:31.426 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.28.20:5700/3) Recv NOMTXPOWER cmd
2026-01-29 02:15:31.426 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.28.20:5700/3) Recv SETFORMAT cmd
2026-01-29 02:15:31.426 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.28.20:5700/3) TRXD header version 1 -> 1
2026-01-29 02:15:31.429 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.28.20:5700) Recv RXTUNE cmd
2026-01-29 02:15:31.429 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETTSC
2026-01-29 02:15:31.429 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETTSC
2026-01-29 02:15:31.429 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETTSC
2026-01-29 02:15:31.429 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.28.20:5700) Recv TXTUNE cmd
2026-01-29 02:15:31.429 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETRXGAIN
2026-01-29 02:15:31.429 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETRXGAIN
2026-01-29 02:15:31.429 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETRXGAIN
2026-01-29 02:15:31.429 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETTSC
2026-01-29 02:15:31.429 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:15:31.429 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:15:31.429 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:15:31.429 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.28.20:5700) Recv NOMTXPOWER cmd
2026-01-29 02:15:31.429 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:15:31.429 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:15:31.429 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:15:31.429 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.28.20:5700) Recv POWERON CMD
2026-01-29 02:15:31.429 [INFO] ctrl_if_trx.py:109 (BTS@172.18.28.20:5700) Starting transceiver...
2026-01-29 02:15:31.429 [INFO] transceiver.py:243 Starting clock generator
2026-01-29 02:15:31.429 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-01-29 02:15:31.429 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:15:31.430 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:15:31.430 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:15:31.430 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETRXGAIN
2026-01-29 02:15:31.430 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:15:31.430 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:15:31.430 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:15:31.430 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:15:31.430 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:15:31.430 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:15:31.430 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:15:31.430 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:15:31.430 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:15:31.430 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:15:31.430 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:15:31.430 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:15:31.430 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:15:31.430 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:15:31.430 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:15:31.430 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:15:31.430 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:15:31.430 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:15:31.430 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:15:31.430 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:15:31.430 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:15:31.430 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:15:31.431 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:15:31.434 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-01-29 02:15:31.918 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-01-29 02:15:31.950 [DEBUG] fake_trx.py:278 (BTS@172.18.28.20:5700) Recv FAKE_TOA cmd
2026-01-29 02:15:31.951 [DEBUG] fake_trx.py:297 (BTS@172.18.28.20:5700) Recv FAKE_RSSI cmd
2026-01-29 02:15:31.952 [DEBUG] fake_trx.py:322 (BTS@172.18.28.20:5700) Recv FAKE_CI cmd
2026-01-29 02:15:31.953 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:15:31.964 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 02:15:31.964 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 02:15:31.964 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 02:15:32.399 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-01-29 02:15:32.432 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 02:15:32.432 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:15:32.432 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:15:32.434 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:15:32.880 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-01-29 02:15:33.361 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-01-29 02:15:33.433 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 02:15:33.433 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:15:33.433 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:15:33.436 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:15:33.842 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-01-29 02:15:34.324 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-01-29 02:15:34.434 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:15:34.434 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:15:34.434 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 02:15:34.437 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:15:34.802 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-01-29 02:15:35.282 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-01-29 02:15:35.435 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:15:35.435 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 02:15:35.435 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:15:35.439 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:15:35.763 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-01-29 02:15:36.244 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-01-29 02:15:36.436 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 02:15:36.436 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:15:36.436 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:15:36.440 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:15:36.725 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-01-29 02:15:37.207 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-01-29 02:15:37.688 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-01-29 02:15:37.974 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:15:37.974 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 02:15:37.975 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 02:15:37.975 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.28.22:6700) Recv POWERON CMD
2026-01-29 02:15:37.975 [INFO] ctrl_if_trx.py:109 (MS@172.18.28.22:6700) Starting transceiver...
2026-01-29 02:15:38.167 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-01-29 02:15:38.192 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD NOHANDOVER
2026-01-29 02:15:38.197 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 02:15:38.198 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 02:15:38.198 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:15:38.198 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:15:38.645 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-01-29 02:15:39.123 [DEBUG] clck_gen.py:113 IND CLOCK 1632
2026-01-29 02:15:39.601 [DEBUG] clck_gen.py:113 IND CLOCK 1734
2026-01-29 02:15:40.080 [DEBUG] clck_gen.py:113 IND CLOCK 1836
2026-01-29 02:15:40.558 [DEBUG] clck_gen.py:113 IND CLOCK 1938
2026-01-29 02:15:41.036 [DEBUG] clck_gen.py:113 IND CLOCK 2040
2026-01-29 02:15:41.515 [DEBUG] clck_gen.py:113 IND CLOCK 2142
2026-01-29 02:15:41.993 [DEBUG] clck_gen.py:113 IND CLOCK 2244
2026-01-29 02:15:42.472 [DEBUG] clck_gen.py:113 IND CLOCK 2346
2026-01-29 02:15:42.950 [DEBUG] clck_gen.py:113 IND CLOCK 2448
2026-01-29 02:15:43.430 [DEBUG] clck_gen.py:113 IND CLOCK 2550
2026-01-29 02:15:43.591 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD NOHANDOVER
2026-01-29 02:15:43.595 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:15:43.596 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 02:15:43.597 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 02:15:43.606 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 02:15:43.607 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:15:43.607 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:15:43.607 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:15:43.613 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 02:15:43.613 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:15:43.613 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:15:43.613 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:15:43.613 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.28.20:5700) Recv POWEROFF cmd
2026-01-29 02:15:43.613 [INFO] ctrl_if_trx.py:117 (BTS@172.18.28.20:5700) Stopping transceiver...
2026-01-29 02:15:43.613 [INFO] transceiver.py:246 Stopping clock generator
2026-01-29 02:15:43.614 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=2590 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:15:43.614 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=2590 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:15:48.610 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.28.20:5700) Recv POWEROFF cmd
2026-01-29 02:15:48.610 [INFO] ctrl_if_trx.py:117 (BTS@172.18.28.20:5700) Stopping transceiver...
2026-01-29 02:15:48.612 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:15:48.613 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:15:48.614 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:15:48.615 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 02:15:48.622 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 02:15:48.624 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.28.20:5700) Recv SETFORMAT cmd
2026-01-29 02:15:48.624 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.28.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:15:48.624 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.28.20:5700) Recv SETFORMAT cmd
2026-01-29 02:15:48.624 [INFO] ctrl_if_trx.py:201 (BTS@172.18.28.20:5700) TRXD header version 1 -> 1
2026-01-29 02:15:48.629 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.28.20:5700/1) Recv RXTUNE cmd
2026-01-29 02:15:48.629 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.28.20:5700/1) Recv TXTUNE cmd
2026-01-29 02:15:48.629 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.28.20:5700/1) Recv SETFORMAT cmd
2026-01-29 02:15:48.629 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.28.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:15:48.629 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:15:48.629 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.28.20:5700/1) Recv NOMTXPOWER cmd
2026-01-29 02:15:48.629 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.28.20:5700/1) Recv SETFORMAT cmd
2026-01-29 02:15:48.630 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.28.20:5700/1) TRXD header version 1 -> 1
2026-01-29 02:15:48.632 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.28.20:5700/2) Recv RXTUNE cmd
2026-01-29 02:15:48.632 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.28.20:5700/2) Recv TXTUNE cmd
2026-01-29 02:15:48.632 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.28.20:5700/2) Recv SETFORMAT cmd
2026-01-29 02:15:48.632 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.28.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:15:48.633 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:15:48.633 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.28.20:5700/2) Recv NOMTXPOWER cmd
2026-01-29 02:15:48.633 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.28.20:5700/2) Recv SETFORMAT cmd
2026-01-29 02:15:48.633 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.28.20:5700/2) TRXD header version 1 -> 1
2026-01-29 02:15:48.635 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.28.20:5700/3) Recv RXTUNE cmd
2026-01-29 02:15:48.635 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.28.20:5700/3) Recv TXTUNE cmd
2026-01-29 02:15:48.635 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.28.20:5700/3) Recv SETFORMAT cmd
2026-01-29 02:15:48.635 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.28.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:15:48.635 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:15:48.635 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.28.20:5700/3) Recv NOMTXPOWER cmd
2026-01-29 02:15:48.635 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.28.20:5700/3) Recv SETFORMAT cmd
2026-01-29 02:15:48.635 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.28.20:5700/3) TRXD header version 1 -> 1
2026-01-29 02:15:48.638 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.28.20:5700) Recv RXTUNE cmd
2026-01-29 02:15:48.638 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETTSC
2026-01-29 02:15:48.638 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETTSC
2026-01-29 02:15:48.638 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETTSC
2026-01-29 02:15:48.639 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.28.20:5700) Recv TXTUNE cmd
2026-01-29 02:15:48.639 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETRXGAIN
2026-01-29 02:15:48.639 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETRXGAIN
2026-01-29 02:15:48.639 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETRXGAIN
2026-01-29 02:15:48.639 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETTSC
2026-01-29 02:15:48.639 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:15:48.639 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:15:48.639 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:15:48.639 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.28.20:5700) Recv NOMTXPOWER cmd
2026-01-29 02:15:48.639 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:15:48.639 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:15:48.639 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:15:48.639 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.28.20:5700) Recv POWERON CMD
2026-01-29 02:15:48.639 [INFO] ctrl_if_trx.py:109 (BTS@172.18.28.20:5700) Starting transceiver...
2026-01-29 02:15:48.639 [INFO] transceiver.py:243 Starting clock generator
2026-01-29 02:15:48.639 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-01-29 02:15:48.639 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:15:48.639 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:15:48.639 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:15:48.639 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETRXGAIN
2026-01-29 02:15:48.640 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:15:48.640 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:15:48.640 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:15:48.640 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:15:48.640 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:15:48.640 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:15:48.640 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:15:48.640 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:15:48.640 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:15:48.640 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:15:48.640 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:15:48.640 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:15:48.640 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:15:48.640 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:15:48.640 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:15:48.640 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:15:48.640 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:15:48.640 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:15:48.640 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:15:48.640 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:15:48.640 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:15:48.640 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:15:48.641 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:15:48.644 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-01-29 02:15:49.128 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-01-29 02:15:49.165 [DEBUG] fake_trx.py:278 (BTS@172.18.28.20:5700) Recv FAKE_TOA cmd
2026-01-29 02:15:49.167 [DEBUG] fake_trx.py:297 (BTS@172.18.28.20:5700) Recv FAKE_RSSI cmd
2026-01-29 02:15:49.168 [DEBUG] fake_trx.py:322 (BTS@172.18.28.20:5700) Recv FAKE_CI cmd
2026-01-29 02:15:49.169 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:15:49.181 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 02:15:49.181 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 02:15:49.181 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 02:15:49.606 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-01-29 02:15:49.643 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 02:15:49.644 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:15:49.644 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:15:49.645 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:15:50.085 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-01-29 02:15:50.563 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-01-29 02:15:50.644 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:15:50.645 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 02:15:50.645 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:15:50.646 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:15:51.040 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-01-29 02:15:51.518 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-01-29 02:15:51.646 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 02:15:51.646 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:15:51.646 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:15:51.648 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:15:51.999 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-01-29 02:15:52.480 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-01-29 02:15:52.647 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:15:52.647 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:15:52.647 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 02:15:52.649 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:15:52.961 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-01-29 02:15:53.442 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-01-29 02:15:53.648 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:15:53.648 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:15:53.648 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 02:15:53.650 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:15:53.923 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-01-29 02:15:54.404 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-01-29 02:15:54.880 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-01-29 02:15:55.188 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:15:55.188 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 02:15:55.189 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 02:15:55.189 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.28.22:6700) Recv POWERON CMD
2026-01-29 02:15:55.189 [INFO] ctrl_if_trx.py:109 (MS@172.18.28.22:6700) Starting transceiver...
2026-01-29 02:15:55.349 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-01-29 02:15:55.367 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD NOHANDOVER
2026-01-29 02:15:55.371 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 02:15:55.371 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 02:15:55.371 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:15:55.371 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:15:55.818 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-01-29 02:15:56.294 [DEBUG] clck_gen.py:113 IND CLOCK 1632
2026-01-29 02:15:56.773 [DEBUG] clck_gen.py:113 IND CLOCK 1734
2026-01-29 02:15:57.252 [DEBUG] clck_gen.py:113 IND CLOCK 1836
2026-01-29 02:15:57.731 [DEBUG] clck_gen.py:113 IND CLOCK 1938
2026-01-29 02:15:58.209 [DEBUG] clck_gen.py:113 IND CLOCK 2040
2026-01-29 02:15:58.687 [DEBUG] clck_gen.py:113 IND CLOCK 2142
2026-01-29 02:15:59.166 [DEBUG] clck_gen.py:113 IND CLOCK 2244
2026-01-29 02:15:59.300 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD NOHANDOVER
2026-01-29 02:15:59.303 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:15:59.304 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 02:15:59.305 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 02:15:59.315 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 02:15:59.316 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:15:59.316 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:15:59.316 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:15:59.321 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 02:15:59.322 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:15:59.322 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:15:59.322 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.28.20:5700) Recv POWEROFF cmd
2026-01-29 02:15:59.322 [INFO] ctrl_if_trx.py:117 (BTS@172.18.28.20:5700) Stopping transceiver...
2026-01-29 02:15:59.322 [INFO] transceiver.py:246 Stopping clock generator
2026-01-29 02:15:59.322 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:15:59.322 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=2279 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:15:59.322 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=2279 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:15:59.322 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=2279 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:15:59.322 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=2279 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:15:59.322 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=2279 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:15:59.322 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=2279 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:15:59.322 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=2279 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:16:04.318 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.28.20:5700) Recv POWEROFF cmd
2026-01-29 02:16:04.318 [INFO] ctrl_if_trx.py:117 (BTS@172.18.28.20:5700) Stopping transceiver...
2026-01-29 02:16:04.320 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:16:04.321 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:16:04.322 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:16:04.322 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 02:16:04.333 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 02:16:04.334 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.28.20:5700) Recv SETFORMAT cmd
2026-01-29 02:16:04.334 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.28.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:16:04.334 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.28.20:5700) Recv SETFORMAT cmd
2026-01-29 02:16:04.334 [INFO] ctrl_if_trx.py:201 (BTS@172.18.28.20:5700) TRXD header version 1 -> 1
2026-01-29 02:16:04.337 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.28.20:5700/1) Recv RXTUNE cmd
2026-01-29 02:16:04.337 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.28.20:5700/1) Recv TXTUNE cmd
2026-01-29 02:16:04.337 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.28.20:5700/1) Recv SETFORMAT cmd
2026-01-29 02:16:04.337 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.28.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:16:04.337 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:16:04.337 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.28.20:5700/1) Recv NOMTXPOWER cmd
2026-01-29 02:16:04.337 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.28.20:5700/1) Recv SETFORMAT cmd
2026-01-29 02:16:04.337 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.28.20:5700/1) TRXD header version 1 -> 1
2026-01-29 02:16:04.339 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.28.20:5700/2) Recv RXTUNE cmd
2026-01-29 02:16:04.339 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.28.20:5700/2) Recv TXTUNE cmd
2026-01-29 02:16:04.340 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.28.20:5700/2) Recv SETFORMAT cmd
2026-01-29 02:16:04.340 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.28.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:16:04.340 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:16:04.340 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.28.20:5700/2) Recv NOMTXPOWER cmd
2026-01-29 02:16:04.340 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.28.20:5700/2) Recv SETFORMAT cmd
2026-01-29 02:16:04.340 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.28.20:5700/2) TRXD header version 1 -> 1
2026-01-29 02:16:04.342 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.28.20:5700/3) Recv RXTUNE cmd
2026-01-29 02:16:04.342 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.28.20:5700/3) Recv TXTUNE cmd
2026-01-29 02:16:04.342 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.28.20:5700/3) Recv SETFORMAT cmd
2026-01-29 02:16:04.342 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.28.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:16:04.342 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:16:04.343 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.28.20:5700/3) Recv NOMTXPOWER cmd
2026-01-29 02:16:04.343 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.28.20:5700/3) Recv SETFORMAT cmd
2026-01-29 02:16:04.343 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.28.20:5700/3) TRXD header version 1 -> 1
2026-01-29 02:16:04.345 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.28.20:5700) Recv RXTUNE cmd
2026-01-29 02:16:04.345 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETTSC
2026-01-29 02:16:04.345 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETTSC
2026-01-29 02:16:04.345 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETTSC
2026-01-29 02:16:04.345 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.28.20:5700) Recv TXTUNE cmd
2026-01-29 02:16:04.345 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETRXGAIN
2026-01-29 02:16:04.346 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETRXGAIN
2026-01-29 02:16:04.346 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETRXGAIN
2026-01-29 02:16:04.346 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETTSC
2026-01-29 02:16:04.346 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:16:04.346 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:16:04.346 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:16:04.346 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.28.20:5700) Recv NOMTXPOWER cmd
2026-01-29 02:16:04.346 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:16:04.346 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:16:04.346 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:16:04.346 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.28.20:5700) Recv POWERON CMD
2026-01-29 02:16:04.346 [INFO] ctrl_if_trx.py:109 (BTS@172.18.28.20:5700) Starting transceiver...
2026-01-29 02:16:04.346 [INFO] transceiver.py:243 Starting clock generator
2026-01-29 02:16:04.346 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-01-29 02:16:04.346 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:16:04.346 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:16:04.346 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:16:04.346 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETRXGAIN
2026-01-29 02:16:04.346 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:16:04.346 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:16:04.347 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:16:04.347 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:16:04.347 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:16:04.347 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:16:04.347 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:16:04.347 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:16:04.347 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:16:04.347 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:16:04.347 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:16:04.347 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:16:04.347 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:16:04.347 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:16:04.347 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:16:04.347 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:16:04.347 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:16:04.347 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:16:04.347 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:16:04.347 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:16:04.348 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:16:04.348 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:16:04.348 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:16:04.351 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-01-29 02:16:04.835 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-01-29 02:16:04.861 [DEBUG] fake_trx.py:278 (BTS@172.18.28.20:5700) Recv FAKE_TOA cmd
2026-01-29 02:16:04.862 [DEBUG] fake_trx.py:297 (BTS@172.18.28.20:5700) Recv FAKE_RSSI cmd
2026-01-29 02:16:04.863 [DEBUG] fake_trx.py:322 (BTS@172.18.28.20:5700) Recv FAKE_CI cmd
2026-01-29 02:16:04.863 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:16:04.871 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 02:16:04.872 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 02:16:04.872 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 02:16:05.313 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-01-29 02:16:05.350 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:16:05.350 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 02:16:05.350 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:16:05.352 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:16:05.793 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-01-29 02:16:06.271 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-01-29 02:16:06.351 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:16:06.352 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 02:16:06.352 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:16:06.353 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:16:06.752 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-01-29 02:16:07.233 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-01-29 02:16:07.353 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 02:16:07.353 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:16:07.353 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:16:07.355 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:16:07.711 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-01-29 02:16:08.192 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-01-29 02:16:08.354 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:16:08.354 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 02:16:08.354 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:16:08.356 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:16:08.664 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-01-29 02:16:09.137 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-01-29 02:16:09.354 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:16:09.355 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 02:16:09.355 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:16:09.358 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:16:09.615 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-01-29 02:16:10.096 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-01-29 02:16:10.576 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-01-29 02:16:10.880 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:16:10.881 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 02:16:10.882 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 02:16:10.882 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.28.22:6700) Recv POWERON CMD
2026-01-29 02:16:10.882 [INFO] ctrl_if_trx.py:109 (MS@172.18.28.22:6700) Starting transceiver...
2026-01-29 02:16:11.056 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-01-29 02:16:11.077 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD NOHANDOVER
2026-01-29 02:16:11.081 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 02:16:11.081 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 02:16:11.082 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:16:11.082 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:16:11.534 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-01-29 02:16:12.013 [DEBUG] clck_gen.py:113 IND CLOCK 1632
2026-01-29 02:16:12.491 [DEBUG] clck_gen.py:113 IND CLOCK 1734
2026-01-29 02:16:12.970 [DEBUG] clck_gen.py:113 IND CLOCK 1836
2026-01-29 02:16:13.448 [DEBUG] clck_gen.py:113 IND CLOCK 1938
2026-01-29 02:16:13.920 [DEBUG] clck_gen.py:113 IND CLOCK 2040
2026-01-29 02:16:14.391 [DEBUG] clck_gen.py:113 IND CLOCK 2142
2026-01-29 02:16:14.862 [DEBUG] clck_gen.py:113 IND CLOCK 2244
2026-01-29 02:16:15.332 [DEBUG] clck_gen.py:113 IND CLOCK 2346
2026-01-29 02:16:15.474 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD NOHANDOVER
2026-01-29 02:16:15.477 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:16:15.479 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 02:16:15.479 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 02:16:15.490 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 02:16:15.490 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:16:15.490 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:16:15.490 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:16:15.496 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 02:16:15.496 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:16:15.496 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:16:15.497 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:16:15.497 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.28.20:5700) Recv POWEROFF cmd
2026-01-29 02:16:15.497 [INFO] ctrl_if_trx.py:117 (BTS@172.18.28.20:5700) Stopping transceiver...
2026-01-29 02:16:15.497 [INFO] transceiver.py:246 Stopping clock generator
2026-01-29 02:16:15.497 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=2382 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:16:15.497 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=2382 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:16:20.493 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.28.20:5700) Recv POWEROFF cmd
2026-01-29 02:16:20.493 [INFO] ctrl_if_trx.py:117 (BTS@172.18.28.20:5700) Stopping transceiver...
2026-01-29 02:16:20.495 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:16:20.496 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:16:20.496 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:16:20.497 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 02:16:20.503 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 02:16:20.504 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.28.20:5700) Recv SETFORMAT cmd
2026-01-29 02:16:20.504 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.28.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:16:20.505 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.28.20:5700) Recv SETFORMAT cmd
2026-01-29 02:16:20.505 [INFO] ctrl_if_trx.py:201 (BTS@172.18.28.20:5700) TRXD header version 1 -> 1
2026-01-29 02:16:20.507 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.28.20:5700/1) Recv RXTUNE cmd
2026-01-29 02:16:20.508 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.28.20:5700/1) Recv TXTUNE cmd
2026-01-29 02:16:20.508 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.28.20:5700/1) Recv SETFORMAT cmd
2026-01-29 02:16:20.508 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.28.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:16:20.508 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:16:20.509 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.28.20:5700/1) Recv NOMTXPOWER cmd
2026-01-29 02:16:20.509 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.28.20:5700/1) Recv SETFORMAT cmd
2026-01-29 02:16:20.509 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.28.20:5700/1) TRXD header version 1 -> 1
2026-01-29 02:16:20.510 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.28.20:5700/2) Recv RXTUNE cmd
2026-01-29 02:16:20.510 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.28.20:5700/2) Recv TXTUNE cmd
2026-01-29 02:16:20.510 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.28.20:5700/2) Recv SETFORMAT cmd
2026-01-29 02:16:20.510 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.28.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:16:20.510 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:16:20.511 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.28.20:5700/2) Recv NOMTXPOWER cmd
2026-01-29 02:16:20.511 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.28.20:5700/2) Recv SETFORMAT cmd
2026-01-29 02:16:20.511 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.28.20:5700/2) TRXD header version 1 -> 1
2026-01-29 02:16:20.512 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.28.20:5700/3) Recv RXTUNE cmd
2026-01-29 02:16:20.512 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.28.20:5700/3) Recv TXTUNE cmd
2026-01-29 02:16:20.512 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.28.20:5700/3) Recv SETFORMAT cmd
2026-01-29 02:16:20.512 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.28.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:16:20.512 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:16:20.513 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.28.20:5700/3) Recv NOMTXPOWER cmd
2026-01-29 02:16:20.513 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.28.20:5700/3) Recv SETFORMAT cmd
2026-01-29 02:16:20.513 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.28.20:5700/3) TRXD header version 1 -> 1
2026-01-29 02:16:20.515 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.28.20:5700) Recv RXTUNE cmd
2026-01-29 02:16:20.515 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETTSC
2026-01-29 02:16:20.515 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETTSC
2026-01-29 02:16:20.515 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETTSC
2026-01-29 02:16:20.515 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.28.20:5700) Recv TXTUNE cmd
2026-01-29 02:16:20.515 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETRXGAIN
2026-01-29 02:16:20.515 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETRXGAIN
2026-01-29 02:16:20.515 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETRXGAIN
2026-01-29 02:16:20.515 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETTSC
2026-01-29 02:16:20.515 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:16:20.515 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:16:20.515 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.28.20:5700) Recv NOMTXPOWER cmd
2026-01-29 02:16:20.515 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:16:20.516 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:16:20.516 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:16:20.516 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.28.20:5700) Recv POWERON CMD
2026-01-29 02:16:20.516 [INFO] ctrl_if_trx.py:109 (BTS@172.18.28.20:5700) Starting transceiver...
2026-01-29 02:16:20.516 [INFO] transceiver.py:243 Starting clock generator
2026-01-29 02:16:20.516 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-01-29 02:16:20.516 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:16:20.516 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:16:20.516 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:16:20.516 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETRXGAIN
2026-01-29 02:16:20.516 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:16:20.516 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:16:20.516 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:16:20.516 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:16:20.516 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:16:20.516 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:16:20.516 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:16:20.516 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:16:20.516 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:16:20.516 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:16:20.516 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:16:20.516 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:16:20.516 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:16:20.516 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:16:20.517 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:16:20.517 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:16:20.517 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:16:20.517 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:16:20.517 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:16:20.517 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:16:20.517 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:16:20.517 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:16:20.517 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:16:20.517 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:16:20.521 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-01-29 02:16:21.004 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-01-29 02:16:21.038 [DEBUG] fake_trx.py:278 (BTS@172.18.28.20:5700) Recv FAKE_TOA cmd
2026-01-29 02:16:21.039 [DEBUG] fake_trx.py:297 (BTS@172.18.28.20:5700) Recv FAKE_RSSI cmd
2026-01-29 02:16:21.040 [DEBUG] fake_trx.py:322 (BTS@172.18.28.20:5700) Recv FAKE_CI cmd
2026-01-29 02:16:21.041 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:16:21.059 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 02:16:21.059 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 02:16:21.059 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 02:16:21.485 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-01-29 02:16:21.518 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 02:16:21.519 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:16:21.519 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:16:21.523 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:16:21.966 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-01-29 02:16:22.448 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-01-29 02:16:22.520 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:16:22.521 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 02:16:22.521 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:16:22.524 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:16:22.930 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-01-29 02:16:23.410 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-01-29 02:16:23.521 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 02:16:23.521 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:16:23.522 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:16:23.525 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:16:23.878 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-01-29 02:16:24.348 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-01-29 02:16:24.523 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:16:24.523 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 02:16:24.523 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:16:24.526 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:16:24.830 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-01-29 02:16:25.311 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-01-29 02:16:25.523 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 02:16:25.524 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:16:25.524 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:16:25.527 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:16:25.793 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-01-29 02:16:26.274 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-01-29 02:16:26.755 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-01-29 02:16:27.070 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:16:27.070 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 02:16:27.071 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 02:16:27.071 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.28.22:6700) Recv POWERON CMD
2026-01-29 02:16:27.072 [INFO] ctrl_if_trx.py:109 (MS@172.18.28.22:6700) Starting transceiver...
2026-01-29 02:16:27.235 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-01-29 02:16:27.257 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD NOHANDOVER
2026-01-29 02:16:27.261 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 02:16:27.261 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 02:16:27.261 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:16:27.262 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:16:27.714 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-01-29 02:16:28.191 [DEBUG] clck_gen.py:113 IND CLOCK 1632
2026-01-29 02:16:28.669 [DEBUG] clck_gen.py:113 IND CLOCK 1734
2026-01-29 02:16:29.147 [DEBUG] clck_gen.py:113 IND CLOCK 1836
2026-01-29 02:16:29.627 [DEBUG] clck_gen.py:113 IND CLOCK 1938
2026-01-29 02:16:30.107 [DEBUG] clck_gen.py:113 IND CLOCK 2040
2026-01-29 02:16:30.587 [DEBUG] clck_gen.py:113 IND CLOCK 2142
2026-01-29 02:16:31.065 [DEBUG] clck_gen.py:113 IND CLOCK 2244
2026-01-29 02:16:31.198 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD NOHANDOVER
2026-01-29 02:16:31.201 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:16:31.203 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 02:16:31.203 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 02:16:31.214 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 02:16:31.214 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:16:31.214 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:16:31.214 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:16:31.216 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 02:16:31.216 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:16:31.216 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:16:31.216 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:16:31.217 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.28.20:5700) Recv POWEROFF cmd
2026-01-29 02:16:31.217 [INFO] ctrl_if_trx.py:117 (BTS@172.18.28.20:5700) Stopping transceiver...
2026-01-29 02:16:31.217 [INFO] transceiver.py:246 Stopping clock generator
2026-01-29 02:16:31.217 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=2277 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:16:31.217 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=2277 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:16:31.217 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=2277 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:16:31.218 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=2277 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:16:31.218 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=2277 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:16:31.218 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=2278 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:16:31.218 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=2278 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:16:31.218 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=2278 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:16:31.218 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=2278 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:16:31.218 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=2278 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:16:31.218 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=2278 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:16:31.218 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=2278 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:16:31.218 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=2278 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:16:36.218 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.28.20:5700) Recv POWEROFF cmd
2026-01-29 02:16:36.218 [INFO] ctrl_if_trx.py:117 (BTS@172.18.28.20:5700) Stopping transceiver...
2026-01-29 02:16:36.222 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:16:36.222 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:16:36.222 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 02:16:36.222 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:16:36.231 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 02:16:36.233 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.28.20:5700) Recv SETFORMAT cmd
2026-01-29 02:16:36.233 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.28.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:16:36.233 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.28.20:5700) Recv SETFORMAT cmd
2026-01-29 02:16:36.233 [INFO] ctrl_if_trx.py:201 (BTS@172.18.28.20:5700) TRXD header version 1 -> 1
2026-01-29 02:16:36.238 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.28.20:5700/1) Recv RXTUNE cmd
2026-01-29 02:16:36.238 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.28.20:5700/1) Recv TXTUNE cmd
2026-01-29 02:16:36.238 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.28.20:5700/1) Recv SETFORMAT cmd
2026-01-29 02:16:36.238 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.28.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:16:36.238 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:16:36.238 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.28.20:5700/1) Recv NOMTXPOWER cmd
2026-01-29 02:16:36.239 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.28.20:5700/1) Recv SETFORMAT cmd
2026-01-29 02:16:36.239 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.28.20:5700/1) TRXD header version 1 -> 1
2026-01-29 02:16:36.241 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.28.20:5700/2) Recv RXTUNE cmd
2026-01-29 02:16:36.241 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.28.20:5700/2) Recv TXTUNE cmd
2026-01-29 02:16:36.241 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.28.20:5700/2) Recv SETFORMAT cmd
2026-01-29 02:16:36.241 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.28.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:16:36.242 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:16:36.242 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.28.20:5700/2) Recv NOMTXPOWER cmd
2026-01-29 02:16:36.242 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.28.20:5700/2) Recv SETFORMAT cmd
2026-01-29 02:16:36.242 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.28.20:5700/2) TRXD header version 1 -> 1
2026-01-29 02:16:36.244 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.28.20:5700/3) Recv RXTUNE cmd
2026-01-29 02:16:36.244 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.28.20:5700/3) Recv TXTUNE cmd
2026-01-29 02:16:36.244 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.28.20:5700/3) Recv SETFORMAT cmd
2026-01-29 02:16:36.244 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.28.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:16:36.244 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:16:36.244 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.28.20:5700/3) Recv NOMTXPOWER cmd
2026-01-29 02:16:36.245 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.28.20:5700/3) Recv SETFORMAT cmd
2026-01-29 02:16:36.245 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.28.20:5700/3) TRXD header version 1 -> 1
2026-01-29 02:16:36.248 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.28.20:5700) Recv RXTUNE cmd
2026-01-29 02:16:36.248 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETTSC
2026-01-29 02:16:36.248 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETTSC
2026-01-29 02:16:36.248 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETTSC
2026-01-29 02:16:36.248 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.28.20:5700) Recv TXTUNE cmd
2026-01-29 02:16:36.248 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETRXGAIN
2026-01-29 02:16:36.248 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETRXGAIN
2026-01-29 02:16:36.248 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETRXGAIN
2026-01-29 02:16:36.248 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETTSC
2026-01-29 02:16:36.248 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:16:36.248 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:16:36.248 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:16:36.248 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.28.20:5700) Recv NOMTXPOWER cmd
2026-01-29 02:16:36.248 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:16:36.248 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:16:36.248 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:16:36.248 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.28.20:5700) Recv POWERON CMD
2026-01-29 02:16:36.248 [INFO] ctrl_if_trx.py:109 (BTS@172.18.28.20:5700) Starting transceiver...
2026-01-29 02:16:36.248 [INFO] transceiver.py:243 Starting clock generator
2026-01-29 02:16:36.248 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-01-29 02:16:36.249 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:16:36.249 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:16:36.249 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:16:36.249 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETRXGAIN
2026-01-29 02:16:36.249 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:16:36.249 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:16:36.249 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:16:36.249 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:16:36.249 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:16:36.249 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:16:36.249 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:16:36.249 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:16:36.249 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:16:36.249 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:16:36.249 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:16:36.249 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:16:36.249 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:16:36.249 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:16:36.249 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:16:36.249 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:16:36.249 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:16:36.249 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:16:36.249 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:16:36.250 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:16:36.250 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:16:36.250 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:16:36.250 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:16:36.253 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-01-29 02:16:36.737 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-01-29 02:16:36.776 [DEBUG] fake_trx.py:278 (BTS@172.18.28.20:5700) Recv FAKE_TOA cmd
2026-01-29 02:16:36.777 [DEBUG] fake_trx.py:297 (BTS@172.18.28.20:5700) Recv FAKE_RSSI cmd
2026-01-29 02:16:36.777 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:16:36.778 [DEBUG] fake_trx.py:322 (BTS@172.18.28.20:5700) Recv FAKE_CI cmd
2026-01-29 02:16:37.206 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-01-29 02:16:37.251 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 02:16:37.252 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:16:37.253 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:16:37.257 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:16:37.675 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-01-29 02:16:38.150 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-01-29 02:16:38.252 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:16:38.253 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 02:16:38.255 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:16:38.259 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:16:38.630 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-01-29 02:16:39.112 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-01-29 02:16:39.253 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:16:39.254 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 02:16:39.255 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:16:39.260 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:16:39.590 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-01-29 02:16:40.068 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-01-29 02:16:40.254 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 02:16:40.255 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:16:40.256 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:16:40.261 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:16:40.547 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-01-29 02:16:41.028 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-01-29 02:16:41.255 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:16:41.256 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 02:16:41.257 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:16:41.262 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:16:41.508 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-01-29 02:16:41.986 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-01-29 02:16:42.464 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-01-29 02:16:42.942 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-01-29 02:16:43.420 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-01-29 02:16:43.901 [DEBUG] clck_gen.py:113 IND CLOCK 1632
2026-01-29 02:16:44.378 [DEBUG] clck_gen.py:113 IND CLOCK 1734
2026-01-29 02:16:44.859 [DEBUG] clck_gen.py:113 IND CLOCK 1836
2026-01-29 02:16:45.339 [DEBUG] clck_gen.py:113 IND CLOCK 1938
2026-01-29 02:16:45.821 [DEBUG] clck_gen.py:113 IND CLOCK 2040
2026-01-29 02:16:46.303 [DEBUG] clck_gen.py:113 IND CLOCK 2142
2026-01-29 02:16:46.784 [DEBUG] clck_gen.py:113 IND CLOCK 2244
2026-01-29 02:16:46.792 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 02:16:46.792 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:16:46.792 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:16:46.792 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:16:46.794 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 02:16:46.794 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:16:46.794 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:16:46.794 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.28.20:5700) Recv POWEROFF cmd
2026-01-29 02:16:46.794 [INFO] ctrl_if_trx.py:117 (BTS@172.18.28.20:5700) Stopping transceiver...
2026-01-29 02:16:46.794 [INFO] transceiver.py:246 Stopping clock generator
2026-01-29 02:16:46.794 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:16:51.794 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.28.20:5700) Recv POWEROFF cmd
2026-01-29 02:16:51.794 [INFO] ctrl_if_trx.py:117 (BTS@172.18.28.20:5700) Stopping transceiver...
2026-01-29 02:16:51.796 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:16:51.797 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:16:51.797 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:16:51.797 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 02:16:51.801 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 02:16:51.802 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.28.20:5700) Recv SETFORMAT cmd
2026-01-29 02:16:51.802 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.28.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:16:51.802 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.28.20:5700) Recv SETFORMAT cmd
2026-01-29 02:16:51.802 [INFO] ctrl_if_trx.py:201 (BTS@172.18.28.20:5700) TRXD header version 1 -> 1
2026-01-29 02:16:51.803 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.28.20:5700/1) Recv RXTUNE cmd
2026-01-29 02:16:51.803 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.28.20:5700/1) Recv TXTUNE cmd
2026-01-29 02:16:51.803 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.28.20:5700/1) Recv SETFORMAT cmd
2026-01-29 02:16:51.803 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.28.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:16:51.804 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:16:51.804 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.28.20:5700/1) Recv NOMTXPOWER cmd
2026-01-29 02:16:51.804 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.28.20:5700/1) Recv SETFORMAT cmd
2026-01-29 02:16:51.804 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.28.20:5700/1) TRXD header version 1 -> 1
2026-01-29 02:16:51.805 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.28.20:5700/2) Recv RXTUNE cmd
2026-01-29 02:16:51.806 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.28.20:5700/2) Recv TXTUNE cmd
2026-01-29 02:16:51.806 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.28.20:5700/2) Recv SETFORMAT cmd
2026-01-29 02:16:51.806 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.28.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:16:51.806 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:16:51.806 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.28.20:5700/2) Recv NOMTXPOWER cmd
2026-01-29 02:16:51.806 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.28.20:5700/2) Recv SETFORMAT cmd
2026-01-29 02:16:51.806 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.28.20:5700/2) TRXD header version 1 -> 1
2026-01-29 02:16:51.808 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.28.20:5700/3) Recv RXTUNE cmd
2026-01-29 02:16:51.809 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.28.20:5700/3) Recv TXTUNE cmd
2026-01-29 02:16:51.809 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.28.20:5700/3) Recv SETFORMAT cmd
2026-01-29 02:16:51.809 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.28.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:16:51.809 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:16:51.809 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.28.20:5700/3) Recv NOMTXPOWER cmd
2026-01-29 02:16:51.809 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.28.20:5700/3) Recv SETFORMAT cmd
2026-01-29 02:16:51.809 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.28.20:5700/3) TRXD header version 1 -> 1
2026-01-29 02:16:51.813 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.28.20:5700) Recv RXTUNE cmd
2026-01-29 02:16:51.813 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETTSC
2026-01-29 02:16:51.813 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETTSC
2026-01-29 02:16:51.813 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETTSC
2026-01-29 02:16:51.813 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.28.20:5700) Recv TXTUNE cmd
2026-01-29 02:16:51.813 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETRXGAIN
2026-01-29 02:16:51.813 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETRXGAIN
2026-01-29 02:16:51.813 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETRXGAIN
2026-01-29 02:16:51.813 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETTSC
2026-01-29 02:16:51.814 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:16:51.814 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:16:51.814 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.28.20:5700) Recv NOMTXPOWER cmd
2026-01-29 02:16:51.814 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:16:51.814 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:16:51.814 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:16:51.814 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.28.20:5700) Recv POWERON CMD
2026-01-29 02:16:51.814 [INFO] ctrl_if_trx.py:109 (BTS@172.18.28.20:5700) Starting transceiver...
2026-01-29 02:16:51.814 [INFO] transceiver.py:243 Starting clock generator
2026-01-29 02:16:51.814 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-01-29 02:16:51.814 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:16:51.814 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:16:51.814 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:16:51.814 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETRXGAIN
2026-01-29 02:16:51.814 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:16:51.814 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:16:51.815 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:16:51.815 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:16:51.815 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:16:51.815 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:16:51.815 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:16:51.815 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:16:51.815 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:16:51.815 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:16:51.816 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:16:51.816 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:16:51.816 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:16:51.816 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:16:51.816 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:16:51.816 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:16:51.816 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:16:51.816 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:16:51.816 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:16:51.816 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:16:51.816 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:16:51.816 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:16:51.816 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:16:51.816 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:16:51.816 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:16:51.816 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:16:51.816 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 02:16:51.816 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:16:51.816 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.28.20:5700) Recv POWEROFF cmd
2026-01-29 02:16:51.816 [INFO] ctrl_if_trx.py:117 (BTS@172.18.28.20:5700) Stopping transceiver...
2026-01-29 02:16:51.816 [INFO] transceiver.py:246 Stopping clock generator
2026-01-29 02:16:56.822 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.28.20:5700) Recv POWEROFF cmd
2026-01-29 02:16:56.822 [INFO] ctrl_if_trx.py:117 (BTS@172.18.28.20:5700) Stopping transceiver...
2026-01-29 02:16:56.822 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:16:56.822 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 02:16:56.822 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:16:56.822 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:16:56.831 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 02:16:56.833 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.28.20:5700) Recv SETFORMAT cmd
2026-01-29 02:16:56.833 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.28.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:16:56.834 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.28.20:5700) Recv SETFORMAT cmd
2026-01-29 02:16:56.834 [INFO] ctrl_if_trx.py:201 (BTS@172.18.28.20:5700) TRXD header version 1 -> 1
2026-01-29 02:16:56.838 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.28.20:5700/1) Recv RXTUNE cmd
2026-01-29 02:16:56.838 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.28.20:5700/1) Recv TXTUNE cmd
2026-01-29 02:16:56.839 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.28.20:5700/1) Recv SETFORMAT cmd
2026-01-29 02:16:56.839 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.28.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:16:56.839 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:16:56.840 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.28.20:5700/1) Recv NOMTXPOWER cmd
2026-01-29 02:16:56.840 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.28.20:5700/1) Recv SETFORMAT cmd
2026-01-29 02:16:56.840 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.28.20:5700/1) TRXD header version 1 -> 1
2026-01-29 02:16:56.841 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.28.20:5700/2) Recv RXTUNE cmd
2026-01-29 02:16:56.842 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.28.20:5700/2) Recv TXTUNE cmd
2026-01-29 02:16:56.842 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.28.20:5700/2) Recv SETFORMAT cmd
2026-01-29 02:16:56.842 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.28.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:16:56.842 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:16:56.842 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.28.20:5700/2) Recv NOMTXPOWER cmd
2026-01-29 02:16:56.842 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.28.20:5700/2) Recv SETFORMAT cmd
2026-01-29 02:16:56.842 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.28.20:5700/2) TRXD header version 1 -> 1
2026-01-29 02:16:56.845 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.28.20:5700/3) Recv RXTUNE cmd
2026-01-29 02:16:56.845 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.28.20:5700/3) Recv TXTUNE cmd
2026-01-29 02:16:56.845 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.28.20:5700/3) Recv SETFORMAT cmd
2026-01-29 02:16:56.845 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.28.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:16:56.845 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:16:56.846 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.28.20:5700/3) Recv NOMTXPOWER cmd
2026-01-29 02:16:56.846 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.28.20:5700/3) Recv SETFORMAT cmd
2026-01-29 02:16:56.846 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.28.20:5700/3) TRXD header version 1 -> 1
2026-01-29 02:16:56.849 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.28.20:5700) Recv RXTUNE cmd
2026-01-29 02:16:56.849 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETTSC
2026-01-29 02:16:56.849 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETTSC
2026-01-29 02:16:56.849 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETTSC
2026-01-29 02:16:56.849 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.28.20:5700) Recv TXTUNE cmd
2026-01-29 02:16:56.849 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETRXGAIN
2026-01-29 02:16:56.849 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETRXGAIN
2026-01-29 02:16:56.849 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETRXGAIN
2026-01-29 02:16:56.849 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETTSC
2026-01-29 02:16:56.849 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:16:56.849 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:16:56.849 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.28.20:5700) Recv NOMTXPOWER cmd
2026-01-29 02:16:56.849 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:16:56.849 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:16:56.849 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:16:56.849 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.28.20:5700) Recv POWERON CMD
2026-01-29 02:16:56.849 [INFO] ctrl_if_trx.py:109 (BTS@172.18.28.20:5700) Starting transceiver...
2026-01-29 02:16:56.849 [INFO] transceiver.py:243 Starting clock generator
2026-01-29 02:16:56.850 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-01-29 02:16:56.850 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:16:56.850 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:16:56.850 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:16:56.850 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETRXGAIN
2026-01-29 02:16:56.850 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:16:56.850 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:16:56.850 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:16:56.850 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:16:56.850 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:16:56.850 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:16:56.850 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:16:56.850 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:16:56.850 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:16:56.850 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:16:56.850 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:16:56.850 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:16:56.851 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:16:56.851 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:16:56.851 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:16:56.851 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:16:56.851 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:16:56.851 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:16:56.851 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:16:56.851 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:16:56.851 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:16:56.851 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:16:56.851 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:16:56.851 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:16:56.854 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-01-29 02:16:57.338 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-01-29 02:16:57.377 [DEBUG] fake_trx.py:278 (BTS@172.18.28.20:5700) Recv FAKE_TOA cmd
2026-01-29 02:16:57.379 [DEBUG] fake_trx.py:297 (BTS@172.18.28.20:5700) Recv FAKE_RSSI cmd
2026-01-29 02:16:57.380 [DEBUG] fake_trx.py:322 (BTS@172.18.28.20:5700) Recv FAKE_CI cmd
2026-01-29 02:16:57.381 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:16:57.383 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 02:16:57.383 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 02:16:57.383 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 02:16:57.383 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:16:57.384 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 02:16:57.384 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 02:16:57.384 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.28.22:6700) Recv POWERON CMD
2026-01-29 02:16:57.384 [INFO] ctrl_if_trx.py:109 (MS@172.18.28.22:6700) Starting transceiver...
2026-01-29 02:16:57.815 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-01-29 02:16:57.853 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 02:16:57.855 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:16:57.856 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:16:57.861 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:16:58.293 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-01-29 02:16:58.770 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-01-29 02:16:58.854 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 02:16:58.856 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:16:58.857 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:16:58.863 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:16:59.248 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-01-29 02:16:59.726 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-01-29 02:16:59.856 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 02:16:59.857 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:16:59.858 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:16:59.863 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:17:00.204 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-01-29 02:17:00.682 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-01-29 02:17:00.857 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 02:17:00.857 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:17:00.860 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:17:00.864 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:17:01.159 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-01-29 02:17:01.637 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-01-29 02:17:01.858 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:17:01.858 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 02:17:01.860 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:17:01.865 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:17:02.115 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-01-29 02:17:02.593 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-01-29 02:17:03.070 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-01-29 02:17:03.548 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-01-29 02:17:04.026 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-01-29 02:17:04.503 [DEBUG] clck_gen.py:113 IND CLOCK 1632
2026-01-29 02:17:04.980 [DEBUG] clck_gen.py:113 IND CLOCK 1734
2026-01-29 02:17:05.434 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 02:17:05.435 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 02:17:05.436 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 02:17:05.436 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:17:05.436 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:17:05.436 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:17:05.437 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 02:17:05.437 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:17:05.437 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:17:05.437 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:17:05.437 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.28.20:5700) Recv POWEROFF cmd
2026-01-29 02:17:05.437 [INFO] ctrl_if_trx.py:117 (BTS@172.18.28.20:5700) Stopping transceiver...
2026-01-29 02:17:05.437 [INFO] transceiver.py:246 Stopping clock generator
2026-01-29 02:17:10.439 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.28.20:5700) Recv POWEROFF cmd
2026-01-29 02:17:10.439 [INFO] ctrl_if_trx.py:117 (BTS@172.18.28.20:5700) Stopping transceiver...
2026-01-29 02:17:10.441 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:17:10.442 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:17:10.444 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:17:10.444 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 02:17:10.455 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 02:17:10.456 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.28.20:5700) Recv SETFORMAT cmd
2026-01-29 02:17:10.457 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.28.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:17:10.457 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.28.20:5700) Recv SETFORMAT cmd
2026-01-29 02:17:10.457 [INFO] ctrl_if_trx.py:201 (BTS@172.18.28.20:5700) TRXD header version 1 -> 1
2026-01-29 02:17:10.460 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.28.20:5700/1) Recv RXTUNE cmd
2026-01-29 02:17:10.460 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.28.20:5700/1) Recv TXTUNE cmd
2026-01-29 02:17:10.460 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.28.20:5700/1) Recv SETFORMAT cmd
2026-01-29 02:17:10.461 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.28.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:17:10.461 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:17:10.461 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.28.20:5700/1) Recv NOMTXPOWER cmd
2026-01-29 02:17:10.462 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.28.20:5700/1) Recv SETFORMAT cmd
2026-01-29 02:17:10.462 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.28.20:5700/1) TRXD header version 1 -> 1
2026-01-29 02:17:10.463 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.28.20:5700/2) Recv RXTUNE cmd
2026-01-29 02:17:10.463 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.28.20:5700/2) Recv TXTUNE cmd
2026-01-29 02:17:10.463 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.28.20:5700/2) Recv SETFORMAT cmd
2026-01-29 02:17:10.463 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.28.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:17:10.464 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:17:10.464 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.28.20:5700/2) Recv NOMTXPOWER cmd
2026-01-29 02:17:10.464 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.28.20:5700/2) Recv SETFORMAT cmd
2026-01-29 02:17:10.464 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.28.20:5700/2) TRXD header version 1 -> 1
2026-01-29 02:17:10.465 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.28.20:5700/3) Recv RXTUNE cmd
2026-01-29 02:17:10.465 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.28.20:5700/3) Recv TXTUNE cmd
2026-01-29 02:17:10.465 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.28.20:5700/3) Recv SETFORMAT cmd
2026-01-29 02:17:10.465 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.28.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:17:10.465 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:17:10.465 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.28.20:5700/3) Recv NOMTXPOWER cmd
2026-01-29 02:17:10.465 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.28.20:5700/3) Recv SETFORMAT cmd
2026-01-29 02:17:10.466 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.28.20:5700/3) TRXD header version 1 -> 1
2026-01-29 02:17:10.468 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.28.20:5700) Recv RXTUNE cmd
2026-01-29 02:17:10.468 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETTSC
2026-01-29 02:17:10.468 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETTSC
2026-01-29 02:17:10.468 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETTSC
2026-01-29 02:17:10.468 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.28.20:5700) Recv TXTUNE cmd
2026-01-29 02:17:10.468 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETRXGAIN
2026-01-29 02:17:10.468 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETRXGAIN
2026-01-29 02:17:10.468 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETRXGAIN
2026-01-29 02:17:10.468 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETTSC
2026-01-29 02:17:10.468 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:17:10.468 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:17:10.468 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:17:10.468 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.28.20:5700) Recv NOMTXPOWER cmd
2026-01-29 02:17:10.468 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:17:10.468 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:17:10.469 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:17:10.469 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.28.20:5700) Recv POWERON CMD
2026-01-29 02:17:10.469 [INFO] ctrl_if_trx.py:109 (BTS@172.18.28.20:5700) Starting transceiver...
2026-01-29 02:17:10.469 [INFO] transceiver.py:243 Starting clock generator
2026-01-29 02:17:10.469 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-01-29 02:17:10.469 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:17:10.469 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:17:10.469 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:17:10.469 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETRXGAIN
2026-01-29 02:17:10.469 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:17:10.469 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:17:10.469 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:17:10.469 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:17:10.470 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:17:10.470 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:17:10.470 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:17:10.470 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:17:10.470 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:17:10.470 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:17:10.470 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:17:10.470 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:17:10.470 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:17:10.470 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:17:10.470 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:17:10.470 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:17:10.470 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:17:10.470 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:17:10.470 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:17:10.470 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:17:10.470 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:17:10.470 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:17:10.470 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:17:10.470 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:17:10.470 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:17:10.470 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 02:17:10.470 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:17:10.470 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.28.20:5700) Recv POWEROFF cmd
2026-01-29 02:17:10.470 [INFO] ctrl_if_trx.py:117 (BTS@172.18.28.20:5700) Stopping transceiver...
2026-01-29 02:17:10.470 [INFO] transceiver.py:246 Stopping clock generator
2026-01-29 02:17:15.473 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.28.20:5700) Recv POWEROFF cmd
2026-01-29 02:17:15.474 [INFO] ctrl_if_trx.py:117 (BTS@172.18.28.20:5700) Stopping transceiver...
2026-01-29 02:17:15.475 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:17:15.476 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:17:15.476 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:17:15.477 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 02:17:15.484 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 02:17:15.485 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.28.20:5700) Recv SETFORMAT cmd
2026-01-29 02:17:15.485 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.28.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:17:15.485 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.28.20:5700) Recv SETFORMAT cmd
2026-01-29 02:17:15.485 [INFO] ctrl_if_trx.py:201 (BTS@172.18.28.20:5700) TRXD header version 1 -> 1
2026-01-29 02:17:15.487 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.28.20:5700/1) Recv RXTUNE cmd
2026-01-29 02:17:15.488 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.28.20:5700/1) Recv TXTUNE cmd
2026-01-29 02:17:15.488 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.28.20:5700/1) Recv SETFORMAT cmd
2026-01-29 02:17:15.488 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.28.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:17:15.489 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:17:15.489 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.28.20:5700/1) Recv NOMTXPOWER cmd
2026-01-29 02:17:15.489 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.28.20:5700/1) Recv SETFORMAT cmd
2026-01-29 02:17:15.489 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.28.20:5700/1) TRXD header version 1 -> 1
2026-01-29 02:17:15.490 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.28.20:5700/2) Recv RXTUNE cmd
2026-01-29 02:17:15.490 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.28.20:5700/2) Recv TXTUNE cmd
2026-01-29 02:17:15.490 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.28.20:5700/2) Recv SETFORMAT cmd
2026-01-29 02:17:15.491 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.28.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:17:15.491 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:17:15.491 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.28.20:5700/2) Recv NOMTXPOWER cmd
2026-01-29 02:17:15.491 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.28.20:5700/2) Recv SETFORMAT cmd
2026-01-29 02:17:15.491 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.28.20:5700/2) TRXD header version 1 -> 1
2026-01-29 02:17:15.493 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.28.20:5700/3) Recv RXTUNE cmd
2026-01-29 02:17:15.493 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.28.20:5700/3) Recv TXTUNE cmd
2026-01-29 02:17:15.493 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.28.20:5700/3) Recv SETFORMAT cmd
2026-01-29 02:17:15.493 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.28.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:17:15.493 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:17:15.493 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.28.20:5700/3) Recv NOMTXPOWER cmd
2026-01-29 02:17:15.493 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.28.20:5700/3) Recv SETFORMAT cmd
2026-01-29 02:17:15.493 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.28.20:5700/3) TRXD header version 1 -> 1
2026-01-29 02:17:15.496 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.28.20:5700) Recv RXTUNE cmd
2026-01-29 02:17:15.496 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETTSC
2026-01-29 02:17:15.496 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETTSC
2026-01-29 02:17:15.496 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETTSC
2026-01-29 02:17:15.496 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.28.20:5700) Recv TXTUNE cmd
2026-01-29 02:17:15.496 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETRXGAIN
2026-01-29 02:17:15.496 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETRXGAIN
2026-01-29 02:17:15.496 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETRXGAIN
2026-01-29 02:17:15.496 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETTSC
2026-01-29 02:17:15.496 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:17:15.497 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:17:15.497 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:17:15.497 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.28.20:5700) Recv NOMTXPOWER cmd
2026-01-29 02:17:15.497 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:17:15.497 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:17:15.497 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:17:15.497 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.28.20:5700) Recv POWERON CMD
2026-01-29 02:17:15.497 [INFO] ctrl_if_trx.py:109 (BTS@172.18.28.20:5700) Starting transceiver...
2026-01-29 02:17:15.497 [INFO] transceiver.py:243 Starting clock generator
2026-01-29 02:17:15.497 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-01-29 02:17:15.497 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:17:15.497 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:17:15.497 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:17:15.497 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETRXGAIN
2026-01-29 02:17:15.497 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:17:15.497 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:17:15.497 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:17:15.497 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:17:15.498 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:17:15.498 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:17:15.498 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:17:15.498 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:17:15.498 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:17:15.498 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:17:15.498 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:17:15.498 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:17:15.498 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:17:15.498 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:17:15.498 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:17:15.498 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:17:15.498 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:17:15.498 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:17:15.498 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:17:15.498 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:17:15.498 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:17:15.498 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:17:15.498 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:17:15.502 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-01-29 02:17:15.985 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-01-29 02:17:16.033 [DEBUG] fake_trx.py:278 (BTS@172.18.28.20:5700) Recv FAKE_TOA cmd
2026-01-29 02:17:16.035 [DEBUG] fake_trx.py:297 (BTS@172.18.28.20:5700) Recv FAKE_RSSI cmd
2026-01-29 02:17:16.036 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:17:16.037 [DEBUG] fake_trx.py:322 (BTS@172.18.28.20:5700) Recv FAKE_CI cmd
2026-01-29 02:17:16.039 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 02:17:16.039 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 02:17:16.039 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 02:17:16.040 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:17:16.040 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 02:17:16.040 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 02:17:16.040 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.28.22:6700) Recv POWERON CMD
2026-01-29 02:17:16.040 [INFO] ctrl_if_trx.py:109 (MS@172.18.28.22:6700) Starting transceiver...
2026-01-29 02:17:16.462 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-01-29 02:17:16.502 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:17:16.502 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 02:17:16.502 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:17:16.504 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:17:16.940 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-01-29 02:17:17.418 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-01-29 02:17:17.503 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:17:17.504 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 02:17:17.504 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:17:17.505 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:17:17.895 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-01-29 02:17:18.369 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-01-29 02:17:18.504 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 02:17:18.505 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:17:18.505 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:17:18.506 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:17:18.847 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-01-29 02:17:19.324 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-01-29 02:17:19.505 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 02:17:19.505 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:17:19.506 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:17:19.506 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:17:19.802 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-01-29 02:17:20.280 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-01-29 02:17:20.506 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:17:20.506 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 02:17:20.507 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:17:20.507 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:17:20.758 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-01-29 02:17:21.235 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-01-29 02:17:21.713 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-01-29 02:17:22.190 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-01-29 02:17:22.667 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-01-29 02:17:23.145 [DEBUG] clck_gen.py:113 IND CLOCK 1632
2026-01-29 02:17:23.622 [DEBUG] clck_gen.py:113 IND CLOCK 1734
2026-01-29 02:17:24.080 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 02:17:24.080 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 02:17:24.085 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 02:17:24.086 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:17:24.086 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:17:24.086 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:17:24.087 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 02:17:24.087 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:17:24.087 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:17:24.087 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:17:24.087 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.28.20:5700) Recv POWEROFF cmd
2026-01-29 02:17:24.087 [INFO] ctrl_if_trx.py:117 (BTS@172.18.28.20:5700) Stopping transceiver...
2026-01-29 02:17:24.087 [INFO] transceiver.py:246 Stopping clock generator
2026-01-29 02:17:29.087 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.28.20:5700) Recv POWEROFF cmd
2026-01-29 02:17:29.088 [INFO] ctrl_if_trx.py:117 (BTS@172.18.28.20:5700) Stopping transceiver...
2026-01-29 02:17:29.089 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:17:29.090 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:17:29.090 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:17:29.091 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 02:17:29.098 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 02:17:29.098 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.28.20:5700) Recv SETFORMAT cmd
2026-01-29 02:17:29.099 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.28.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:17:29.099 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.28.20:5700) Recv SETFORMAT cmd
2026-01-29 02:17:29.099 [INFO] ctrl_if_trx.py:201 (BTS@172.18.28.20:5700) TRXD header version 1 -> 1
2026-01-29 02:17:29.101 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.28.20:5700/1) Recv RXTUNE cmd
2026-01-29 02:17:29.101 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.28.20:5700/1) Recv TXTUNE cmd
2026-01-29 02:17:29.102 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.28.20:5700/1) Recv SETFORMAT cmd
2026-01-29 02:17:29.102 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.28.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:17:29.102 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:17:29.102 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.28.20:5700/1) Recv NOMTXPOWER cmd
2026-01-29 02:17:29.103 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.28.20:5700/1) Recv SETFORMAT cmd
2026-01-29 02:17:29.103 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.28.20:5700/1) TRXD header version 1 -> 1
2026-01-29 02:17:29.103 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.28.20:5700/2) Recv RXTUNE cmd
2026-01-29 02:17:29.103 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.28.20:5700/2) Recv TXTUNE cmd
2026-01-29 02:17:29.104 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.28.20:5700/2) Recv SETFORMAT cmd
2026-01-29 02:17:29.104 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.28.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:17:29.104 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:17:29.104 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.28.20:5700/2) Recv NOMTXPOWER cmd
2026-01-29 02:17:29.104 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.28.20:5700/2) Recv SETFORMAT cmd
2026-01-29 02:17:29.104 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.28.20:5700/2) TRXD header version 1 -> 1
2026-01-29 02:17:29.106 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.28.20:5700/3) Recv RXTUNE cmd
2026-01-29 02:17:29.106 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.28.20:5700/3) Recv TXTUNE cmd
2026-01-29 02:17:29.106 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.28.20:5700/3) Recv SETFORMAT cmd
2026-01-29 02:17:29.106 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.28.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:17:29.106 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:17:29.106 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.28.20:5700/3) Recv NOMTXPOWER cmd
2026-01-29 02:17:29.106 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.28.20:5700/3) Recv SETFORMAT cmd
2026-01-29 02:17:29.106 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.28.20:5700/3) TRXD header version 1 -> 1
2026-01-29 02:17:29.108 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.28.20:5700) Recv RXTUNE cmd
2026-01-29 02:17:29.108 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETTSC
2026-01-29 02:17:29.108 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETTSC
2026-01-29 02:17:29.108 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETTSC
2026-01-29 02:17:29.108 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.28.20:5700) Recv TXTUNE cmd
2026-01-29 02:17:29.108 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETRXGAIN
2026-01-29 02:17:29.109 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETRXGAIN
2026-01-29 02:17:29.109 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETRXGAIN
2026-01-29 02:17:29.109 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETTSC
2026-01-29 02:17:29.109 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:17:29.109 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:17:29.109 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:17:29.109 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.28.20:5700) Recv NOMTXPOWER cmd
2026-01-29 02:17:29.109 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:17:29.109 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:17:29.109 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:17:29.109 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.28.20:5700) Recv POWERON CMD
2026-01-29 02:17:29.109 [INFO] ctrl_if_trx.py:109 (BTS@172.18.28.20:5700) Starting transceiver...
2026-01-29 02:17:29.109 [INFO] transceiver.py:243 Starting clock generator
2026-01-29 02:17:29.109 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-01-29 02:17:29.109 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:17:29.109 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:17:29.109 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:17:29.109 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETRXGAIN
2026-01-29 02:17:29.109 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:17:29.109 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:17:29.109 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:17:29.109 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:17:29.110 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:17:29.110 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:17:29.110 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:17:29.110 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:17:29.110 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:17:29.110 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:17:29.110 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:17:29.110 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:17:29.110 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:17:29.110 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:17:29.110 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:17:29.111 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:17:29.111 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:17:29.111 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:17:29.111 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:17:29.111 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:17:29.111 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:17:29.111 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:17:29.111 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:17:29.111 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:17:29.111 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 02:17:29.111 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:17:29.111 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.28.20:5700) Recv POWEROFF cmd
2026-01-29 02:17:29.111 [INFO] ctrl_if_trx.py:117 (BTS@172.18.28.20:5700) Stopping transceiver...
2026-01-29 02:17:29.111 [INFO] transceiver.py:246 Stopping clock generator
2026-01-29 02:17:29.111 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:17:34.114 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.28.20:5700) Recv POWEROFF cmd
2026-01-29 02:17:34.114 [INFO] ctrl_if_trx.py:117 (BTS@172.18.28.20:5700) Stopping transceiver...
2026-01-29 02:17:34.116 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:17:34.117 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:17:34.119 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:17:34.121 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 02:17:34.128 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 02:17:34.129 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.28.20:5700) Recv SETFORMAT cmd
2026-01-29 02:17:34.129 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.28.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:17:34.129 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.28.20:5700) Recv SETFORMAT cmd
2026-01-29 02:17:34.129 [INFO] ctrl_if_trx.py:201 (BTS@172.18.28.20:5700) TRXD header version 1 -> 1
2026-01-29 02:17:34.131 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.28.20:5700/1) Recv RXTUNE cmd
2026-01-29 02:17:34.131 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.28.20:5700/1) Recv TXTUNE cmd
2026-01-29 02:17:34.131 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.28.20:5700/1) Recv SETFORMAT cmd
2026-01-29 02:17:34.131 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.28.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:17:34.132 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:17:34.132 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.28.20:5700/1) Recv NOMTXPOWER cmd
2026-01-29 02:17:34.132 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.28.20:5700/1) Recv SETFORMAT cmd
2026-01-29 02:17:34.132 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.28.20:5700/1) TRXD header version 1 -> 1
2026-01-29 02:17:34.133 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.28.20:5700/2) Recv RXTUNE cmd
2026-01-29 02:17:34.133 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.28.20:5700/2) Recv TXTUNE cmd
2026-01-29 02:17:34.133 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.28.20:5700/2) Recv SETFORMAT cmd
2026-01-29 02:17:34.133 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.28.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:17:34.133 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:17:34.133 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.28.20:5700/2) Recv NOMTXPOWER cmd
2026-01-29 02:17:34.133 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.28.20:5700/2) Recv SETFORMAT cmd
2026-01-29 02:17:34.133 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.28.20:5700/2) TRXD header version 1 -> 1
2026-01-29 02:17:34.135 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.28.20:5700/3) Recv RXTUNE cmd
2026-01-29 02:17:34.135 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.28.20:5700/3) Recv TXTUNE cmd
2026-01-29 02:17:34.135 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.28.20:5700/3) Recv SETFORMAT cmd
2026-01-29 02:17:34.135 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.28.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:17:34.135 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:17:34.135 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.28.20:5700/3) Recv NOMTXPOWER cmd
2026-01-29 02:17:34.135 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.28.20:5700/3) Recv SETFORMAT cmd
2026-01-29 02:17:34.135 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.28.20:5700/3) TRXD header version 1 -> 1
2026-01-29 02:17:34.137 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.28.20:5700) Recv RXTUNE cmd
2026-01-29 02:17:34.137 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETTSC
2026-01-29 02:17:34.137 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETTSC
2026-01-29 02:17:34.137 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETTSC
2026-01-29 02:17:34.137 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.28.20:5700) Recv TXTUNE cmd
2026-01-29 02:17:34.137 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETRXGAIN
2026-01-29 02:17:34.137 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETRXGAIN
2026-01-29 02:17:34.137 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETRXGAIN
2026-01-29 02:17:34.137 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETTSC
2026-01-29 02:17:34.137 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:17:34.137 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:17:34.137 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.28.20:5700) Recv NOMTXPOWER cmd
2026-01-29 02:17:34.137 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:17:34.137 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:17:34.137 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:17:34.137 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.28.20:5700) Recv POWERON CMD
2026-01-29 02:17:34.137 [INFO] ctrl_if_trx.py:109 (BTS@172.18.28.20:5700) Starting transceiver...
2026-01-29 02:17:34.137 [INFO] transceiver.py:243 Starting clock generator
2026-01-29 02:17:34.138 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-01-29 02:17:34.138 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:17:34.138 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:17:34.138 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:17:34.138 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETRXGAIN
2026-01-29 02:17:34.138 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:17:34.138 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:17:34.138 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:17:34.138 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:17:34.138 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:17:34.138 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:17:34.138 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:17:34.138 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:17:34.138 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:17:34.138 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:17:34.138 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:17:34.138 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:17:34.138 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:17:34.138 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:17:34.138 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:17:34.138 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:17:34.138 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:17:34.139 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:17:34.139 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:17:34.139 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:17:34.139 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:17:34.139 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:17:34.139 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:17:34.139 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:17:34.142 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-01-29 02:17:34.625 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-01-29 02:17:34.660 [DEBUG] fake_trx.py:278 (BTS@172.18.28.20:5700) Recv FAKE_TOA cmd
2026-01-29 02:17:34.661 [DEBUG] fake_trx.py:297 (BTS@172.18.28.20:5700) Recv FAKE_RSSI cmd
2026-01-29 02:17:34.662 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:17:34.663 [DEBUG] fake_trx.py:322 (BTS@172.18.28.20:5700) Recv FAKE_CI cmd
2026-01-29 02:17:34.665 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 02:17:34.665 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 02:17:34.665 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 02:17:34.666 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:17:34.666 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 02:17:34.667 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 02:17:34.667 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.28.22:6700) Recv POWERON CMD
2026-01-29 02:17:34.667 [INFO] ctrl_if_trx.py:109 (MS@172.18.28.22:6700) Starting transceiver...
2026-01-29 02:17:35.103 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-01-29 02:17:35.140 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 02:17:35.141 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:17:35.141 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:17:35.144 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:17:35.581 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-01-29 02:17:36.058 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-01-29 02:17:36.141 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:17:36.142 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 02:17:36.142 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:17:36.146 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:17:36.536 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-01-29 02:17:37.013 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-01-29 02:17:37.143 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:17:37.143 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 02:17:37.143 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:17:37.147 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:17:37.491 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-01-29 02:17:37.969 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-01-29 02:17:38.144 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 02:17:38.144 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:17:38.145 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:17:38.148 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:17:38.446 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-01-29 02:17:38.924 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-01-29 02:17:39.145 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 02:17:39.145 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:17:39.145 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:17:39.149 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:17:39.402 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-01-29 02:17:39.879 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-01-29 02:17:40.356 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-01-29 02:17:40.834 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-01-29 02:17:41.312 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-01-29 02:17:41.789 [DEBUG] clck_gen.py:113 IND CLOCK 1632
2026-01-29 02:17:42.267 [DEBUG] clck_gen.py:113 IND CLOCK 1734
2026-01-29 02:17:42.681 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 02:17:42.681 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 02:17:42.687 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 02:17:42.688 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:17:42.688 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:17:42.688 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:17:42.691 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 02:17:42.691 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:17:42.691 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:17:42.691 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:17:42.691 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.28.20:5700) Recv POWEROFF cmd
2026-01-29 02:17:42.691 [INFO] ctrl_if_trx.py:117 (BTS@172.18.28.20:5700) Stopping transceiver...
2026-01-29 02:17:42.691 [INFO] transceiver.py:246 Stopping clock generator
2026-01-29 02:17:42.691 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=1826 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:17:42.692 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=1826 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:17:42.692 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=1826 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:17:42.692 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=1826 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:17:42.692 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=1826 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:17:42.692 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=1826 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:17:42.692 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=1827 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:17:42.692 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=1827 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:17:42.692 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=1827 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:17:42.692 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=1827 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:17:42.692 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=1827 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:17:42.692 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=1827 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:17:42.692 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=1827 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:17:42.692 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=1827 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:17:47.691 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.28.20:5700) Recv POWEROFF cmd
2026-01-29 02:17:47.691 [INFO] ctrl_if_trx.py:117 (BTS@172.18.28.20:5700) Stopping transceiver...
2026-01-29 02:17:47.693 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:17:47.694 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:17:47.694 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:17:47.694 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 02:17:47.697 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 02:17:47.697 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.28.20:5700) Recv SETFORMAT cmd
2026-01-29 02:17:47.697 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.28.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:17:47.697 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.28.20:5700) Recv SETFORMAT cmd
2026-01-29 02:17:47.697 [INFO] ctrl_if_trx.py:201 (BTS@172.18.28.20:5700) TRXD header version 1 -> 1
2026-01-29 02:17:47.698 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.28.20:5700/1) Recv RXTUNE cmd
2026-01-29 02:17:47.698 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.28.20:5700/1) Recv TXTUNE cmd
2026-01-29 02:17:47.698 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.28.20:5700/1) Recv SETFORMAT cmd
2026-01-29 02:17:47.698 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.28.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:17:47.698 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:17:47.698 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.28.20:5700/1) Recv NOMTXPOWER cmd
2026-01-29 02:17:47.698 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.28.20:5700/1) Recv SETFORMAT cmd
2026-01-29 02:17:47.698 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.28.20:5700/1) TRXD header version 1 -> 1
2026-01-29 02:17:47.699 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.28.20:5700/2) Recv RXTUNE cmd
2026-01-29 02:17:47.699 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.28.20:5700/2) Recv TXTUNE cmd
2026-01-29 02:17:47.699 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.28.20:5700/2) Recv SETFORMAT cmd
2026-01-29 02:17:47.699 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.28.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:17:47.699 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:17:47.699 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.28.20:5700/2) Recv NOMTXPOWER cmd
2026-01-29 02:17:47.699 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.28.20:5700/2) Recv SETFORMAT cmd
2026-01-29 02:17:47.699 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.28.20:5700/2) TRXD header version 1 -> 1
2026-01-29 02:17:47.700 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.28.20:5700/3) Recv RXTUNE cmd
2026-01-29 02:17:47.700 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.28.20:5700/3) Recv TXTUNE cmd
2026-01-29 02:17:47.700 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.28.20:5700/3) Recv SETFORMAT cmd
2026-01-29 02:17:47.700 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.28.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:17:47.700 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:17:47.700 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.28.20:5700/3) Recv NOMTXPOWER cmd
2026-01-29 02:17:47.700 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.28.20:5700/3) Recv SETFORMAT cmd
2026-01-29 02:17:47.700 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.28.20:5700/3) TRXD header version 1 -> 1
2026-01-29 02:17:47.702 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.28.20:5700) Recv RXTUNE cmd
2026-01-29 02:17:47.702 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETTSC
2026-01-29 02:17:47.702 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETTSC
2026-01-29 02:17:47.702 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETTSC
2026-01-29 02:17:47.702 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.28.20:5700) Recv TXTUNE cmd
2026-01-29 02:17:47.702 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETRXGAIN
2026-01-29 02:17:47.702 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETRXGAIN
2026-01-29 02:17:47.702 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETRXGAIN
2026-01-29 02:17:47.702 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETTSC
2026-01-29 02:17:47.702 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:17:47.702 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:17:47.702 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:17:47.702 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:17:47.702 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.28.20:5700) Recv NOMTXPOWER cmd
2026-01-29 02:17:47.702 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:17:47.702 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:17:47.702 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:17:47.702 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.28.20:5700) Recv POWERON CMD
2026-01-29 02:17:47.702 [INFO] ctrl_if_trx.py:109 (BTS@172.18.28.20:5700) Starting transceiver...
2026-01-29 02:17:47.702 [INFO] transceiver.py:243 Starting clock generator
2026-01-29 02:17:47.702 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-01-29 02:17:47.702 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:17:47.702 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:17:47.702 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:17:47.702 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETRXGAIN
2026-01-29 02:17:47.702 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:17:47.702 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:17:47.702 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:17:47.702 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:17:47.702 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:17:47.702 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:17:47.702 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:17:47.702 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:17:47.702 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:17:47.702 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:17:47.703 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:17:47.703 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:17:47.703 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:17:47.703 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:17:47.703 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:17:47.703 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:17:47.703 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:17:47.703 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:17:47.703 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:17:47.703 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:17:47.703 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:17:47.703 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:17:47.703 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:17:47.704 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:17:47.704 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:17:47.704 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 02:17:47.704 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.28.20:5700) Recv POWEROFF cmd
2026-01-29 02:17:47.704 [INFO] ctrl_if_trx.py:117 (BTS@172.18.28.20:5700) Stopping transceiver...
2026-01-29 02:17:47.704 [INFO] transceiver.py:246 Stopping clock generator
2026-01-29 02:17:52.707 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.28.20:5700) Recv POWEROFF cmd
2026-01-29 02:17:52.713 [INFO] ctrl_if_trx.py:117 (BTS@172.18.28.20:5700) Stopping transceiver...
2026-01-29 02:17:52.713 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:17:52.713 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:17:52.713 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:17:52.713 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 02:17:52.713 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 02:17:52.713 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.28.20:5700) Recv SETFORMAT cmd
2026-01-29 02:17:52.713 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.28.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:17:52.713 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.28.20:5700) Recv SETFORMAT cmd
2026-01-29 02:17:52.713 [INFO] ctrl_if_trx.py:201 (BTS@172.18.28.20:5700) TRXD header version 1 -> 1
2026-01-29 02:17:52.714 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.28.20:5700/1) Recv RXTUNE cmd
2026-01-29 02:17:52.714 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.28.20:5700/1) Recv TXTUNE cmd
2026-01-29 02:17:52.714 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.28.20:5700/1) Recv SETFORMAT cmd
2026-01-29 02:17:52.714 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.28.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:17:52.715 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:17:52.715 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.28.20:5700/1) Recv NOMTXPOWER cmd
2026-01-29 02:17:52.715 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.28.20:5700/1) Recv SETFORMAT cmd
2026-01-29 02:17:52.715 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.28.20:5700/1) TRXD header version 1 -> 1
2026-01-29 02:17:52.715 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.28.20:5700/2) Recv RXTUNE cmd
2026-01-29 02:17:52.715 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.28.20:5700/2) Recv TXTUNE cmd
2026-01-29 02:17:52.715 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.28.20:5700/2) Recv SETFORMAT cmd
2026-01-29 02:17:52.715 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.28.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:17:52.715 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:17:52.715 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.28.20:5700/2) Recv NOMTXPOWER cmd
2026-01-29 02:17:52.715 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.28.20:5700/2) Recv SETFORMAT cmd
2026-01-29 02:17:52.715 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.28.20:5700/2) TRXD header version 1 -> 1
2026-01-29 02:17:52.716 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.28.20:5700/3) Recv RXTUNE cmd
2026-01-29 02:17:52.716 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.28.20:5700/3) Recv TXTUNE cmd
2026-01-29 02:17:52.716 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.28.20:5700/3) Recv SETFORMAT cmd
2026-01-29 02:17:52.716 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.28.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:17:52.716 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:17:52.716 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.28.20:5700/3) Recv NOMTXPOWER cmd
2026-01-29 02:17:52.716 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.28.20:5700/3) Recv SETFORMAT cmd
2026-01-29 02:17:52.716 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.28.20:5700/3) TRXD header version 1 -> 1
2026-01-29 02:17:52.718 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.28.20:5700) Recv RXTUNE cmd
2026-01-29 02:17:52.718 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETTSC
2026-01-29 02:17:52.718 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETTSC
2026-01-29 02:17:52.718 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETTSC
2026-01-29 02:17:52.718 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.28.20:5700) Recv TXTUNE cmd
2026-01-29 02:17:52.718 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETRXGAIN
2026-01-29 02:17:52.718 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETRXGAIN
2026-01-29 02:17:52.718 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETRXGAIN
2026-01-29 02:17:52.718 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETTSC
2026-01-29 02:17:52.718 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:17:52.718 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:17:52.718 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:17:52.718 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.28.20:5700) Recv NOMTXPOWER cmd
2026-01-29 02:17:52.718 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:17:52.718 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:17:52.718 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:17:52.718 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.28.20:5700) Recv POWERON CMD
2026-01-29 02:17:52.718 [INFO] ctrl_if_trx.py:109 (BTS@172.18.28.20:5700) Starting transceiver...
2026-01-29 02:17:52.718 [INFO] transceiver.py:243 Starting clock generator
2026-01-29 02:17:52.718 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-01-29 02:17:52.718 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:17:52.718 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:17:52.718 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:17:52.718 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETRXGAIN
2026-01-29 02:17:52.718 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:17:52.718 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:17:52.719 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:17:52.719 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:17:52.719 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:17:52.719 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:17:52.719 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:17:52.719 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:17:52.719 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:17:52.719 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:17:52.719 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:17:52.719 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:17:52.719 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:17:52.719 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:17:52.719 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:17:52.719 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:17:52.719 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:17:52.719 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:17:52.719 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:17:52.719 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:17:52.719 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:17:52.719 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:17:52.719 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:17:52.723 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-01-29 02:17:53.205 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-01-29 02:17:53.236 [DEBUG] fake_trx.py:278 (BTS@172.18.28.20:5700) Recv FAKE_TOA cmd
2026-01-29 02:17:53.237 [DEBUG] fake_trx.py:297 (BTS@172.18.28.20:5700) Recv FAKE_RSSI cmd
2026-01-29 02:17:53.238 [DEBUG] fake_trx.py:322 (BTS@172.18.28.20:5700) Recv FAKE_CI cmd
2026-01-29 02:17:53.238 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:17:53.239 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 02:17:53.239 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 02:17:53.240 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 02:17:53.240 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:17:53.240 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 02:17:53.240 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 02:17:53.240 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.28.22:6700) Recv POWERON CMD
2026-01-29 02:17:53.240 [INFO] ctrl_if_trx.py:109 (MS@172.18.28.22:6700) Starting transceiver...
2026-01-29 02:17:53.682 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-01-29 02:17:53.721 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 02:17:53.721 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:17:53.722 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:17:53.723 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:17:54.159 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-01-29 02:17:54.637 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-01-29 02:17:54.721 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 02:17:54.722 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:17:54.722 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:17:54.725 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:17:55.115 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-01-29 02:17:55.593 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-01-29 02:17:55.723 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 02:17:55.723 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:17:55.723 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:17:55.725 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:17:56.071 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-01-29 02:17:56.548 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-01-29 02:17:56.724 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:17:56.724 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:17:56.725 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 02:17:56.727 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:17:57.026 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-01-29 02:17:57.504 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-01-29 02:17:57.725 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 02:17:57.742 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:17:57.742 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:17:57.742 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:17:57.982 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-01-29 02:17:58.459 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-01-29 02:17:58.937 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-01-29 02:17:59.415 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-01-29 02:17:59.893 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-01-29 02:18:00.371 [DEBUG] clck_gen.py:113 IND CLOCK 1632
2026-01-29 02:18:00.848 [DEBUG] clck_gen.py:113 IND CLOCK 1734
2026-01-29 02:18:01.252 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 02:18:01.252 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 02:18:01.255 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 02:18:01.255 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:18:01.255 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:18:01.255 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:18:01.256 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 02:18:01.256 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:18:01.256 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:18:01.256 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:18:01.256 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.28.20:5700) Recv POWEROFF cmd
2026-01-29 02:18:01.256 [INFO] ctrl_if_trx.py:117 (BTS@172.18.28.20:5700) Stopping transceiver...
2026-01-29 02:18:01.256 [INFO] transceiver.py:246 Stopping clock generator
2026-01-29 02:18:01.256 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=1824 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:18:01.256 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=1824 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:18:01.256 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=1824 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:18:01.256 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=1824 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:18:01.256 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=1824 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:18:01.256 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=1824 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:18:01.256 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=1824 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:18:01.256 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=1824 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:18:06.261 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.28.20:5700) Recv POWEROFF cmd
2026-01-29 02:18:06.261 [INFO] ctrl_if_trx.py:117 (BTS@172.18.28.20:5700) Stopping transceiver...
2026-01-29 02:18:06.261 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:18:06.261 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:18:06.261 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:18:06.261 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 02:18:06.271 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 02:18:06.273 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.28.20:5700) Recv SETFORMAT cmd
2026-01-29 02:18:06.274 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.28.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:18:06.274 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.28.20:5700) Recv SETFORMAT cmd
2026-01-29 02:18:06.274 [INFO] ctrl_if_trx.py:201 (BTS@172.18.28.20:5700) TRXD header version 1 -> 1
2026-01-29 02:18:06.279 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.28.20:5700/1) Recv RXTUNE cmd
2026-01-29 02:18:06.279 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.28.20:5700/1) Recv TXTUNE cmd
2026-01-29 02:18:06.280 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.28.20:5700/1) Recv SETFORMAT cmd
2026-01-29 02:18:06.280 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.28.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:18:06.280 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:18:06.280 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.28.20:5700/1) Recv NOMTXPOWER cmd
2026-01-29 02:18:06.281 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.28.20:5700/1) Recv SETFORMAT cmd
2026-01-29 02:18:06.281 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.28.20:5700/1) TRXD header version 1 -> 1
2026-01-29 02:18:06.282 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.28.20:5700/2) Recv RXTUNE cmd
2026-01-29 02:18:06.282 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.28.20:5700/2) Recv TXTUNE cmd
2026-01-29 02:18:06.283 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.28.20:5700/2) Recv SETFORMAT cmd
2026-01-29 02:18:06.283 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.28.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:18:06.283 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:18:06.283 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.28.20:5700/2) Recv NOMTXPOWER cmd
2026-01-29 02:18:06.283 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.28.20:5700/2) Recv SETFORMAT cmd
2026-01-29 02:18:06.283 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.28.20:5700/2) TRXD header version 1 -> 1
2026-01-29 02:18:06.285 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.28.20:5700/3) Recv RXTUNE cmd
2026-01-29 02:18:06.285 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.28.20:5700/3) Recv TXTUNE cmd
2026-01-29 02:18:06.285 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.28.20:5700/3) Recv SETFORMAT cmd
2026-01-29 02:18:06.285 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.28.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:18:06.285 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:18:06.285 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.28.20:5700/3) Recv NOMTXPOWER cmd
2026-01-29 02:18:06.285 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.28.20:5700/3) Recv SETFORMAT cmd
2026-01-29 02:18:06.285 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.28.20:5700/3) TRXD header version 1 -> 1
2026-01-29 02:18:06.288 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.28.20:5700) Recv RXTUNE cmd
2026-01-29 02:18:06.289 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETTSC
2026-01-29 02:18:06.289 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETTSC
2026-01-29 02:18:06.289 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETTSC
2026-01-29 02:18:06.289 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.28.20:5700) Recv TXTUNE cmd
2026-01-29 02:18:06.289 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETRXGAIN
2026-01-29 02:18:06.289 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETRXGAIN
2026-01-29 02:18:06.289 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETRXGAIN
2026-01-29 02:18:06.289 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETTSC
2026-01-29 02:18:06.289 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:18:06.289 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:18:06.289 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:18:06.289 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.28.20:5700) Recv NOMTXPOWER cmd
2026-01-29 02:18:06.289 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:18:06.289 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:18:06.289 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:18:06.289 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.28.20:5700) Recv POWERON CMD
2026-01-29 02:18:06.289 [INFO] ctrl_if_trx.py:109 (BTS@172.18.28.20:5700) Starting transceiver...
2026-01-29 02:18:06.289 [INFO] transceiver.py:243 Starting clock generator
2026-01-29 02:18:06.289 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-01-29 02:18:06.290 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:18:06.290 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:18:06.290 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:18:06.290 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETRXGAIN
2026-01-29 02:18:06.290 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:18:06.290 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:18:06.290 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:18:06.290 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:18:06.291 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:18:06.291 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:18:06.291 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:18:06.291 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:18:06.291 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:18:06.291 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:18:06.291 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:18:06.291 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:18:06.291 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:18:06.291 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:18:06.291 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:18:06.291 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:18:06.291 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:18:06.291 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:18:06.291 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:18:06.291 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:18:06.291 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:18:06.291 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:18:06.291 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:18:06.291 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:18:06.291 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:18:06.291 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 02:18:06.291 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:18:06.292 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.28.20:5700) Recv POWEROFF cmd
2026-01-29 02:18:06.292 [INFO] ctrl_if_trx.py:117 (BTS@172.18.28.20:5700) Stopping transceiver...
2026-01-29 02:18:06.292 [INFO] transceiver.py:246 Stopping clock generator
2026-01-29 02:18:11.294 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.28.20:5700) Recv POWEROFF cmd
2026-01-29 02:18:11.294 [INFO] ctrl_if_trx.py:117 (BTS@172.18.28.20:5700) Stopping transceiver...
2026-01-29 02:18:11.296 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:18:11.297 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:18:11.297 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:18:11.297 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 02:18:11.309 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 02:18:11.309 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.28.20:5700) Recv SETFORMAT cmd
2026-01-29 02:18:11.309 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.28.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:18:11.310 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.28.20:5700) Recv SETFORMAT cmd
2026-01-29 02:18:11.310 [INFO] ctrl_if_trx.py:201 (BTS@172.18.28.20:5700) TRXD header version 1 -> 1
2026-01-29 02:18:11.311 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.28.20:5700/1) Recv RXTUNE cmd
2026-01-29 02:18:11.311 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.28.20:5700/1) Recv TXTUNE cmd
2026-01-29 02:18:11.311 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.28.20:5700/1) Recv SETFORMAT cmd
2026-01-29 02:18:11.312 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.28.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:18:11.312 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:18:11.312 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.28.20:5700/1) Recv NOMTXPOWER cmd
2026-01-29 02:18:11.312 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.28.20:5700/1) Recv SETFORMAT cmd
2026-01-29 02:18:11.312 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.28.20:5700/1) TRXD header version 1 -> 1
2026-01-29 02:18:11.313 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.28.20:5700/2) Recv RXTUNE cmd
2026-01-29 02:18:11.313 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.28.20:5700/2) Recv TXTUNE cmd
2026-01-29 02:18:11.313 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.28.20:5700/2) Recv SETFORMAT cmd
2026-01-29 02:18:11.313 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.28.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:18:11.313 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:18:11.313 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.28.20:5700/2) Recv NOMTXPOWER cmd
2026-01-29 02:18:11.313 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.28.20:5700/2) Recv SETFORMAT cmd
2026-01-29 02:18:11.313 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.28.20:5700/2) TRXD header version 1 -> 1
2026-01-29 02:18:11.314 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.28.20:5700/3) Recv RXTUNE cmd
2026-01-29 02:18:11.314 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.28.20:5700/3) Recv TXTUNE cmd
2026-01-29 02:18:11.315 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.28.20:5700/3) Recv SETFORMAT cmd
2026-01-29 02:18:11.315 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.28.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:18:11.315 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:18:11.315 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.28.20:5700/3) Recv NOMTXPOWER cmd
2026-01-29 02:18:11.315 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.28.20:5700/3) Recv SETFORMAT cmd
2026-01-29 02:18:11.315 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.28.20:5700/3) TRXD header version 1 -> 1
2026-01-29 02:18:11.316 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.28.20:5700) Recv RXTUNE cmd
2026-01-29 02:18:11.316 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETTSC
2026-01-29 02:18:11.316 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETTSC
2026-01-29 02:18:11.316 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETTSC
2026-01-29 02:18:11.316 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.28.20:5700) Recv TXTUNE cmd
2026-01-29 02:18:11.316 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETRXGAIN
2026-01-29 02:18:11.316 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETRXGAIN
2026-01-29 02:18:11.316 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETRXGAIN
2026-01-29 02:18:11.316 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETTSC
2026-01-29 02:18:11.317 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:18:11.317 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:18:11.317 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.28.20:5700) Recv NOMTXPOWER cmd
2026-01-29 02:18:11.317 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:18:11.317 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:18:11.317 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:18:11.317 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.28.20:5700) Recv POWERON CMD
2026-01-29 02:18:11.317 [INFO] ctrl_if_trx.py:109 (BTS@172.18.28.20:5700) Starting transceiver...
2026-01-29 02:18:11.317 [INFO] transceiver.py:243 Starting clock generator
2026-01-29 02:18:11.317 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-01-29 02:18:11.317 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:18:11.317 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:18:11.317 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:18:11.317 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETRXGAIN
2026-01-29 02:18:11.317 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:18:11.317 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:18:11.317 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:18:11.317 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:18:11.317 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:18:11.317 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:18:11.317 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:18:11.317 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:18:11.317 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:18:11.317 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:18:11.317 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:18:11.317 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:18:11.317 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:18:11.317 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:18:11.317 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:18:11.317 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:18:11.317 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:18:11.317 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:18:11.317 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:18:11.317 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:18:11.317 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:18:11.317 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:18:11.317 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:18:11.317 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:18:11.321 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-01-29 02:18:11.805 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-01-29 02:18:11.833 [DEBUG] fake_trx.py:278 (BTS@172.18.28.20:5700) Recv FAKE_TOA cmd
2026-01-29 02:18:11.834 [DEBUG] fake_trx.py:297 (BTS@172.18.28.20:5700) Recv FAKE_RSSI cmd
2026-01-29 02:18:11.835 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:18:11.835 [DEBUG] fake_trx.py:322 (BTS@172.18.28.20:5700) Recv FAKE_CI cmd
2026-01-29 02:18:11.837 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 02:18:11.837 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 02:18:11.837 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 02:18:11.837 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:18:11.837 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 02:18:11.837 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 02:18:11.837 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.28.22:6700) Recv POWERON CMD
2026-01-29 02:18:11.837 [INFO] ctrl_if_trx.py:109 (MS@172.18.28.22:6700) Starting transceiver...
2026-01-29 02:18:12.281 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-01-29 02:18:12.319 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 02:18:12.319 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:18:12.320 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:18:12.322 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:18:12.759 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-01-29 02:18:13.237 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-01-29 02:18:13.320 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 02:18:13.320 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:18:13.340 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:18:13.341 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:18:13.714 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-01-29 02:18:14.192 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-01-29 02:18:14.321 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 02:18:14.341 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:18:14.341 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:18:14.341 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:18:14.669 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-01-29 02:18:15.146 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-01-29 02:18:15.321 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 02:18:15.341 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:18:15.342 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:18:15.342 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:18:15.624 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-01-29 02:18:16.101 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-01-29 02:18:16.323 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 02:18:16.342 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:18:16.342 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:18:16.343 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:18:16.579 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-01-29 02:18:17.056 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-01-29 02:18:17.533 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-01-29 02:18:18.011 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-01-29 02:18:18.489 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-01-29 02:18:18.966 [DEBUG] clck_gen.py:113 IND CLOCK 1632
2026-01-29 02:18:19.444 [DEBUG] clck_gen.py:113 IND CLOCK 1734
2026-01-29 02:18:19.921 [DEBUG] clck_gen.py:113 IND CLOCK 1836
2026-01-29 02:18:20.398 [DEBUG] clck_gen.py:113 IND CLOCK 1938
2026-01-29 02:18:20.875 [DEBUG] clck_gen.py:113 IND CLOCK 2040
2026-01-29 02:18:21.352 [DEBUG] clck_gen.py:113 IND CLOCK 2142
2026-01-29 02:18:21.830 [DEBUG] clck_gen.py:113 IND CLOCK 2244
2026-01-29 02:18:22.308 [DEBUG] clck_gen.py:113 IND CLOCK 2346
2026-01-29 02:18:22.785 [DEBUG] clck_gen.py:113 IND CLOCK 2448
2026-01-29 02:18:23.263 [DEBUG] clck_gen.py:113 IND CLOCK 2550
2026-01-29 02:18:23.739 [DEBUG] clck_gen.py:113 IND CLOCK 2652
2026-01-29 02:18:24.216 [DEBUG] clck_gen.py:113 IND CLOCK 2754
2026-01-29 02:18:24.694 [DEBUG] clck_gen.py:113 IND CLOCK 2856
2026-01-29 02:18:25.169 [DEBUG] clck_gen.py:113 IND CLOCK 2958
2026-01-29 02:18:25.646 [DEBUG] clck_gen.py:113 IND CLOCK 3060
2026-01-29 02:18:25.853 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 02:18:25.853 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 02:18:25.859 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 02:18:25.859 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:18:25.859 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:18:25.859 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:18:25.860 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 02:18:25.860 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:18:25.860 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:18:25.860 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:18:25.860 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.28.20:5700) Recv POWEROFF cmd
2026-01-29 02:18:25.860 [INFO] ctrl_if_trx.py:117 (BTS@172.18.28.20:5700) Stopping transceiver...
2026-01-29 02:18:25.860 [INFO] transceiver.py:246 Stopping clock generator
2026-01-29 02:18:25.860 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=3107 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:18:25.860 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=3107 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:18:30.862 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.28.20:5700) Recv POWEROFF cmd
2026-01-29 02:18:30.862 [INFO] ctrl_if_trx.py:117 (BTS@172.18.28.20:5700) Stopping transceiver...
2026-01-29 02:18:30.864 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:18:30.865 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:18:30.866 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:18:30.867 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 02:18:30.871 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 02:18:30.872 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.28.20:5700) Recv SETFORMAT cmd
2026-01-29 02:18:30.872 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.28.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:18:30.873 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.28.20:5700) Recv SETFORMAT cmd
2026-01-29 02:18:30.873 [INFO] ctrl_if_trx.py:201 (BTS@172.18.28.20:5700) TRXD header version 1 -> 1
2026-01-29 02:18:30.876 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.28.20:5700/1) Recv RXTUNE cmd
2026-01-29 02:18:30.876 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.28.20:5700/1) Recv TXTUNE cmd
2026-01-29 02:18:30.877 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.28.20:5700/1) Recv SETFORMAT cmd
2026-01-29 02:18:30.877 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.28.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:18:30.877 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:18:30.877 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.28.20:5700/1) Recv NOMTXPOWER cmd
2026-01-29 02:18:30.877 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.28.20:5700/1) Recv SETFORMAT cmd
2026-01-29 02:18:30.878 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.28.20:5700/1) TRXD header version 1 -> 1
2026-01-29 02:18:30.879 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.28.20:5700/2) Recv RXTUNE cmd
2026-01-29 02:18:30.879 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.28.20:5700/2) Recv TXTUNE cmd
2026-01-29 02:18:30.879 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.28.20:5700/2) Recv SETFORMAT cmd
2026-01-29 02:18:30.879 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.28.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:18:30.880 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:18:30.880 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.28.20:5700/2) Recv NOMTXPOWER cmd
2026-01-29 02:18:30.880 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.28.20:5700/2) Recv SETFORMAT cmd
2026-01-29 02:18:30.880 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.28.20:5700/2) TRXD header version 1 -> 1
2026-01-29 02:18:30.881 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.28.20:5700/3) Recv RXTUNE cmd
2026-01-29 02:18:30.881 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.28.20:5700/3) Recv TXTUNE cmd
2026-01-29 02:18:30.881 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.28.20:5700/3) Recv SETFORMAT cmd
2026-01-29 02:18:30.882 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.28.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:18:30.882 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:18:30.882 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.28.20:5700/3) Recv NOMTXPOWER cmd
2026-01-29 02:18:30.882 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.28.20:5700/3) Recv SETFORMAT cmd
2026-01-29 02:18:30.882 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.28.20:5700/3) TRXD header version 1 -> 1
2026-01-29 02:18:30.884 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.28.20:5700) Recv RXTUNE cmd
2026-01-29 02:18:30.884 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETTSC
2026-01-29 02:18:30.884 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETTSC
2026-01-29 02:18:30.884 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETTSC
2026-01-29 02:18:30.884 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.28.20:5700) Recv TXTUNE cmd
2026-01-29 02:18:30.884 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETRXGAIN
2026-01-29 02:18:30.885 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETRXGAIN
2026-01-29 02:18:30.885 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETRXGAIN
2026-01-29 02:18:30.885 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETTSC
2026-01-29 02:18:30.885 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:18:30.885 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:18:30.885 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:18:30.885 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.28.20:5700) Recv NOMTXPOWER cmd
2026-01-29 02:18:30.885 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:18:30.885 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:18:30.885 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:18:30.885 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.28.20:5700) Recv POWERON CMD
2026-01-29 02:18:30.885 [INFO] ctrl_if_trx.py:109 (BTS@172.18.28.20:5700) Starting transceiver...
2026-01-29 02:18:30.885 [INFO] transceiver.py:243 Starting clock generator
2026-01-29 02:18:30.885 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-01-29 02:18:30.885 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:18:30.885 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:18:30.885 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:18:30.885 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETRXGAIN
2026-01-29 02:18:30.885 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:18:30.885 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:18:30.885 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:18:30.885 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:18:30.885 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:18:30.885 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:18:30.886 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:18:30.886 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:18:30.886 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:18:30.886 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:18:30.886 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:18:30.886 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:18:30.886 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:18:30.886 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:18:30.886 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:18:30.886 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:18:30.886 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:18:30.886 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:18:30.886 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:18:30.886 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:18:30.886 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:18:30.887 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:18:30.887 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:18:30.887 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:18:30.887 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:18:30.887 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:18:30.887 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 02:18:30.887 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.28.20:5700) Recv POWEROFF cmd
2026-01-29 02:18:30.887 [INFO] ctrl_if_trx.py:117 (BTS@172.18.28.20:5700) Stopping transceiver...
2026-01-29 02:18:30.887 [INFO] transceiver.py:246 Stopping clock generator
2026-01-29 02:18:35.890 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.28.20:5700) Recv POWEROFF cmd
2026-01-29 02:18:35.890 [INFO] ctrl_if_trx.py:117 (BTS@172.18.28.20:5700) Stopping transceiver...
2026-01-29 02:18:35.892 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:18:35.893 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:18:35.895 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:18:35.895 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 02:18:35.904 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 02:18:35.905 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.28.20:5700) Recv SETFORMAT cmd
2026-01-29 02:18:35.905 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.28.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:18:35.906 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.28.20:5700) Recv SETFORMAT cmd
2026-01-29 02:18:35.906 [INFO] ctrl_if_trx.py:201 (BTS@172.18.28.20:5700) TRXD header version 1 -> 1
2026-01-29 02:18:35.908 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.28.20:5700/1) Recv RXTUNE cmd
2026-01-29 02:18:35.909 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.28.20:5700/1) Recv TXTUNE cmd
2026-01-29 02:18:35.909 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.28.20:5700/1) Recv SETFORMAT cmd
2026-01-29 02:18:35.909 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.28.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:18:35.910 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:18:35.910 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.28.20:5700/1) Recv NOMTXPOWER cmd
2026-01-29 02:18:35.910 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.28.20:5700/1) Recv SETFORMAT cmd
2026-01-29 02:18:35.910 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.28.20:5700/1) TRXD header version 1 -> 1
2026-01-29 02:18:35.911 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.28.20:5700/2) Recv RXTUNE cmd
2026-01-29 02:18:35.911 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.28.20:5700/2) Recv TXTUNE cmd
2026-01-29 02:18:35.911 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.28.20:5700/2) Recv SETFORMAT cmd
2026-01-29 02:18:35.911 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.28.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:18:35.911 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:18:35.912 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.28.20:5700/2) Recv NOMTXPOWER cmd
2026-01-29 02:18:35.912 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.28.20:5700/2) Recv SETFORMAT cmd
2026-01-29 02:18:35.912 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.28.20:5700/2) TRXD header version 1 -> 1
2026-01-29 02:18:35.913 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.28.20:5700/3) Recv RXTUNE cmd
2026-01-29 02:18:35.914 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.28.20:5700/3) Recv TXTUNE cmd
2026-01-29 02:18:35.914 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.28.20:5700/3) Recv SETFORMAT cmd
2026-01-29 02:18:35.914 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.28.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:18:35.914 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:18:35.914 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.28.20:5700/3) Recv NOMTXPOWER cmd
2026-01-29 02:18:35.914 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.28.20:5700/3) Recv SETFORMAT cmd
2026-01-29 02:18:35.914 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.28.20:5700/3) TRXD header version 1 -> 1
2026-01-29 02:18:35.916 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.28.20:5700) Recv RXTUNE cmd
2026-01-29 02:18:35.916 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETTSC
2026-01-29 02:18:35.917 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETTSC
2026-01-29 02:18:35.917 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETTSC
2026-01-29 02:18:35.917 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.28.20:5700) Recv TXTUNE cmd
2026-01-29 02:18:35.917 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETRXGAIN
2026-01-29 02:18:35.917 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETRXGAIN
2026-01-29 02:18:35.917 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETRXGAIN
2026-01-29 02:18:35.917 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETTSC
2026-01-29 02:18:35.917 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:18:35.917 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:18:35.917 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.28.20:5700) Recv NOMTXPOWER cmd
2026-01-29 02:18:35.917 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:18:35.917 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:18:35.917 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:18:35.917 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.28.20:5700) Recv POWERON CMD
2026-01-29 02:18:35.917 [INFO] ctrl_if_trx.py:109 (BTS@172.18.28.20:5700) Starting transceiver...
2026-01-29 02:18:35.917 [INFO] transceiver.py:243 Starting clock generator
2026-01-29 02:18:35.917 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-01-29 02:18:35.917 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:18:35.917 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:18:35.917 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:18:35.917 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETRXGAIN
2026-01-29 02:18:35.917 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:18:35.917 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:18:35.917 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:18:35.917 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:18:35.918 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:18:35.918 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:18:35.918 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:18:35.918 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:18:35.918 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:18:35.918 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:18:35.918 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:18:35.918 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:18:35.918 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:18:35.918 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:18:35.918 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:18:35.918 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:18:35.918 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:18:35.918 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:18:35.918 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:18:35.919 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:18:35.919 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:18:35.919 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:18:35.919 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:18:35.919 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:18:35.922 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-01-29 02:18:36.405 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-01-29 02:18:36.440 [DEBUG] fake_trx.py:278 (BTS@172.18.28.20:5700) Recv FAKE_TOA cmd
2026-01-29 02:18:36.441 [DEBUG] fake_trx.py:297 (BTS@172.18.28.20:5700) Recv FAKE_RSSI cmd
2026-01-29 02:18:36.443 [DEBUG] fake_trx.py:322 (BTS@172.18.28.20:5700) Recv FAKE_CI cmd
2026-01-29 02:18:36.443 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:18:36.445 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 02:18:36.445 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 02:18:36.445 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 02:18:36.445 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:18:36.446 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 02:18:36.446 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 02:18:36.446 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.28.22:6700) Recv POWERON CMD
2026-01-29 02:18:36.446 [INFO] ctrl_if_trx.py:109 (MS@172.18.28.22:6700) Starting transceiver...
2026-01-29 02:18:36.882 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-01-29 02:18:36.921 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:18:36.921 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 02:18:36.922 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:18:36.924 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:18:37.359 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-01-29 02:18:37.837 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-01-29 02:18:37.923 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 02:18:37.923 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:18:37.923 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:18:37.925 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:18:38.315 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-01-29 02:18:38.792 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-01-29 02:18:38.924 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:18:38.924 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:18:38.924 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 02:18:38.926 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:18:39.270 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-01-29 02:18:39.748 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-01-29 02:18:39.925 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:18:39.925 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 02:18:39.925 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:18:39.927 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:18:40.226 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-01-29 02:18:40.703 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-01-29 02:18:40.925 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:18:40.926 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 02:18:40.926 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:18:40.928 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:18:41.181 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-01-29 02:18:41.658 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-01-29 02:18:42.136 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-01-29 02:18:42.613 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-01-29 02:18:43.091 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-01-29 02:18:43.568 [DEBUG] clck_gen.py:113 IND CLOCK 1632
2026-01-29 02:18:44.046 [DEBUG] clck_gen.py:113 IND CLOCK 1734
2026-01-29 02:18:44.453 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 02:18:44.453 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 02:18:44.459 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 02:18:44.459 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:18:44.459 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:18:44.459 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:18:44.460 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 02:18:44.460 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:18:44.460 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:18:44.460 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:18:44.460 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.28.20:5700) Recv POWEROFF cmd
2026-01-29 02:18:44.460 [INFO] ctrl_if_trx.py:117 (BTS@172.18.28.20:5700) Stopping transceiver...
2026-01-29 02:18:44.460 [INFO] transceiver.py:246 Stopping clock generator
2026-01-29 02:18:49.462 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.28.20:5700) Recv POWEROFF cmd
2026-01-29 02:18:49.463 [INFO] ctrl_if_trx.py:117 (BTS@172.18.28.20:5700) Stopping transceiver...
2026-01-29 02:18:49.464 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:18:49.465 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:18:49.465 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:18:49.466 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 02:18:49.473 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 02:18:49.473 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.28.20:5700) Recv SETFORMAT cmd
2026-01-29 02:18:49.473 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.28.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:18:49.474 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.28.20:5700) Recv SETFORMAT cmd
2026-01-29 02:18:49.474 [INFO] ctrl_if_trx.py:201 (BTS@172.18.28.20:5700) TRXD header version 1 -> 1
2026-01-29 02:18:49.476 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.28.20:5700/1) Recv RXTUNE cmd
2026-01-29 02:18:49.476 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.28.20:5700/1) Recv TXTUNE cmd
2026-01-29 02:18:49.476 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.28.20:5700/1) Recv SETFORMAT cmd
2026-01-29 02:18:49.476 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.28.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:18:49.476 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:18:49.476 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.28.20:5700/1) Recv NOMTXPOWER cmd
2026-01-29 02:18:49.476 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.28.20:5700/1) Recv SETFORMAT cmd
2026-01-29 02:18:49.476 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.28.20:5700/1) TRXD header version 1 -> 1
2026-01-29 02:18:49.478 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.28.20:5700/2) Recv RXTUNE cmd
2026-01-29 02:18:49.478 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.28.20:5700/2) Recv TXTUNE cmd
2026-01-29 02:18:49.478 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.28.20:5700/2) Recv SETFORMAT cmd
2026-01-29 02:18:49.479 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.28.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:18:49.479 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:18:49.479 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.28.20:5700/2) Recv NOMTXPOWER cmd
2026-01-29 02:18:49.479 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.28.20:5700/2) Recv SETFORMAT cmd
2026-01-29 02:18:49.479 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.28.20:5700/2) TRXD header version 1 -> 1
2026-01-29 02:18:49.480 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.28.20:5700/3) Recv RXTUNE cmd
2026-01-29 02:18:49.480 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.28.20:5700/3) Recv TXTUNE cmd
2026-01-29 02:18:49.480 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.28.20:5700/3) Recv SETFORMAT cmd
2026-01-29 02:18:49.481 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.28.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:18:49.481 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:18:49.481 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.28.20:5700/3) Recv NOMTXPOWER cmd
2026-01-29 02:18:49.481 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.28.20:5700/3) Recv SETFORMAT cmd
2026-01-29 02:18:49.481 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.28.20:5700/3) TRXD header version 1 -> 1
2026-01-29 02:18:49.483 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.28.20:5700) Recv RXTUNE cmd
2026-01-29 02:18:49.483 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETTSC
2026-01-29 02:18:49.483 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETTSC
2026-01-29 02:18:49.483 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETTSC
2026-01-29 02:18:49.483 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.28.20:5700) Recv TXTUNE cmd
2026-01-29 02:18:49.483 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETRXGAIN
2026-01-29 02:18:49.483 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETRXGAIN
2026-01-29 02:18:49.483 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETRXGAIN
2026-01-29 02:18:49.483 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETTSC
2026-01-29 02:18:49.484 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:18:49.484 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:18:49.484 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:18:49.484 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.28.20:5700) Recv NOMTXPOWER cmd
2026-01-29 02:18:49.484 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:18:49.484 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:18:49.484 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:18:49.484 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.28.20:5700) Recv POWERON CMD
2026-01-29 02:18:49.484 [INFO] ctrl_if_trx.py:109 (BTS@172.18.28.20:5700) Starting transceiver...
2026-01-29 02:18:49.484 [INFO] transceiver.py:243 Starting clock generator
2026-01-29 02:18:49.484 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-01-29 02:18:49.484 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:18:49.484 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:18:49.484 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:18:49.484 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETRXGAIN
2026-01-29 02:18:49.485 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:18:49.485 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:18:49.485 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:18:49.485 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:18:49.485 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:18:49.485 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:18:49.485 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:18:49.485 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:18:49.485 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:18:49.485 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:18:49.485 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:18:49.485 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:18:49.485 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:18:49.485 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:18:49.485 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:18:49.485 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:18:49.485 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:18:49.485 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:18:49.485 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:18:49.485 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:18:49.485 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:18:49.486 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:18:49.486 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:18:49.486 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:18:49.486 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 02:18:49.486 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:18:49.486 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.28.20:5700) Recv POWEROFF cmd
2026-01-29 02:18:49.486 [INFO] ctrl_if_trx.py:117 (BTS@172.18.28.20:5700) Stopping transceiver...
2026-01-29 02:18:49.486 [INFO] transceiver.py:246 Stopping clock generator
2026-01-29 02:18:49.486 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:18:54.488 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.28.20:5700) Recv POWEROFF cmd
2026-01-29 02:18:54.489 [INFO] ctrl_if_trx.py:117 (BTS@172.18.28.20:5700) Stopping transceiver...
2026-01-29 02:18:54.490 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:18:54.491 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:18:54.491 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:18:54.492 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 02:18:54.499 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 02:18:54.500 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.28.20:5700) Recv SETFORMAT cmd
2026-01-29 02:18:54.500 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.28.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:18:54.500 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.28.20:5700) Recv SETFORMAT cmd
2026-01-29 02:18:54.500 [INFO] ctrl_if_trx.py:201 (BTS@172.18.28.20:5700) TRXD header version 1 -> 1
2026-01-29 02:18:54.502 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.28.20:5700/1) Recv RXTUNE cmd
2026-01-29 02:18:54.503 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.28.20:5700/1) Recv TXTUNE cmd
2026-01-29 02:18:54.503 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.28.20:5700/1) Recv SETFORMAT cmd
2026-01-29 02:18:54.503 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.28.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:18:54.504 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:18:54.504 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.28.20:5700/1) Recv NOMTXPOWER cmd
2026-01-29 02:18:54.504 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.28.20:5700/1) Recv SETFORMAT cmd
2026-01-29 02:18:54.504 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.28.20:5700/1) TRXD header version 1 -> 1
2026-01-29 02:18:54.505 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.28.20:5700/2) Recv RXTUNE cmd
2026-01-29 02:18:54.505 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.28.20:5700/2) Recv TXTUNE cmd
2026-01-29 02:18:54.505 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.28.20:5700/2) Recv SETFORMAT cmd
2026-01-29 02:18:54.505 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.28.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:18:54.506 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:18:54.506 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.28.20:5700/2) Recv NOMTXPOWER cmd
2026-01-29 02:18:54.506 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.28.20:5700/2) Recv SETFORMAT cmd
2026-01-29 02:18:54.506 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.28.20:5700/2) TRXD header version 1 -> 1
2026-01-29 02:18:54.507 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.28.20:5700/3) Recv RXTUNE cmd
2026-01-29 02:18:54.507 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.28.20:5700/3) Recv TXTUNE cmd
2026-01-29 02:18:54.507 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.28.20:5700/3) Recv SETFORMAT cmd
2026-01-29 02:18:54.507 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.28.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:18:54.507 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:18:54.507 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.28.20:5700/3) Recv NOMTXPOWER cmd
2026-01-29 02:18:54.507 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.28.20:5700/3) Recv SETFORMAT cmd
2026-01-29 02:18:54.507 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.28.20:5700/3) TRXD header version 1 -> 1
2026-01-29 02:18:54.510 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.28.20:5700) Recv RXTUNE cmd
2026-01-29 02:18:54.510 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETTSC
2026-01-29 02:18:54.510 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETTSC
2026-01-29 02:18:54.510 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETTSC
2026-01-29 02:18:54.510 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.28.20:5700) Recv TXTUNE cmd
2026-01-29 02:18:54.510 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETRXGAIN
2026-01-29 02:18:54.510 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETRXGAIN
2026-01-29 02:18:54.510 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETRXGAIN
2026-01-29 02:18:54.510 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETTSC
2026-01-29 02:18:54.510 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:18:54.510 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:18:54.510 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:18:54.510 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.28.20:5700) Recv NOMTXPOWER cmd
2026-01-29 02:18:54.510 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:18:54.510 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:18:54.510 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:18:54.510 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.28.20:5700) Recv POWERON CMD
2026-01-29 02:18:54.510 [INFO] ctrl_if_trx.py:109 (BTS@172.18.28.20:5700) Starting transceiver...
2026-01-29 02:18:54.510 [INFO] transceiver.py:243 Starting clock generator
2026-01-29 02:18:54.510 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-01-29 02:18:54.511 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:18:54.511 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:18:54.511 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:18:54.511 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETRXGAIN
2026-01-29 02:18:54.511 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:18:54.511 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:18:54.511 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:18:54.511 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:18:54.511 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:18:54.511 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:18:54.511 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:18:54.511 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:18:54.511 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:18:54.511 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:18:54.511 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:18:54.511 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:18:54.511 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:18:54.511 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:18:54.511 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:18:54.511 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:18:54.511 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:18:54.511 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:18:54.511 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:18:54.511 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:18:54.511 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:18:54.512 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:18:54.512 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:18:54.515 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-01-29 02:18:54.997 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-01-29 02:18:55.040 [DEBUG] fake_trx.py:278 (BTS@172.18.28.20:5700) Recv FAKE_TOA cmd
2026-01-29 02:18:55.042 [DEBUG] fake_trx.py:297 (BTS@172.18.28.20:5700) Recv FAKE_RSSI cmd
2026-01-29 02:18:55.043 [DEBUG] fake_trx.py:322 (BTS@172.18.28.20:5700) Recv FAKE_CI cmd
2026-01-29 02:18:55.043 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:18:55.045 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 02:18:55.046 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 02:18:55.046 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 02:18:55.046 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:18:55.046 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 02:18:55.046 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 02:18:55.046 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.28.22:6700) Recv POWERON CMD
2026-01-29 02:18:55.046 [INFO] ctrl_if_trx.py:109 (MS@172.18.28.22:6700) Starting transceiver...
2026-01-29 02:18:55.474 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-01-29 02:18:55.514 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:18:55.514 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 02:18:55.516 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:18:55.519 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:18:55.952 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-01-29 02:18:56.430 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-01-29 02:18:56.515 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:18:56.515 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 02:18:56.517 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:18:56.519 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:18:56.908 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-01-29 02:18:57.386 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-01-29 02:18:57.515 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:18:57.516 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 02:18:57.518 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:18:57.520 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:18:57.863 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-01-29 02:18:58.341 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-01-29 02:18:58.517 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 02:18:58.517 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:18:58.519 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:18:58.521 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:18:58.819 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-01-29 02:18:59.297 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-01-29 02:18:59.518 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 02:18:59.518 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:18:59.521 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:18:59.522 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:18:59.774 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-01-29 02:19:00.252 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-01-29 02:19:00.730 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-01-29 02:19:01.207 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-01-29 02:19:01.685 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-01-29 02:19:02.162 [DEBUG] clck_gen.py:113 IND CLOCK 1632
2026-01-29 02:19:02.640 [DEBUG] clck_gen.py:113 IND CLOCK 1734
2026-01-29 02:19:03.118 [DEBUG] clck_gen.py:113 IND CLOCK 1836
2026-01-29 02:19:03.596 [DEBUG] clck_gen.py:113 IND CLOCK 1938
2026-01-29 02:19:04.073 [DEBUG] clck_gen.py:113 IND CLOCK 2040
2026-01-29 02:19:04.550 [DEBUG] clck_gen.py:113 IND CLOCK 2142
2026-01-29 02:19:05.028 [DEBUG] clck_gen.py:113 IND CLOCK 2244
2026-01-29 02:19:05.094 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 02:19:05.094 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 02:19:05.099 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 02:19:05.099 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:19:05.099 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:19:05.099 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:19:05.102 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 02:19:05.102 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:19:05.102 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:19:05.102 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.28.20:5700) Recv POWEROFF cmd
2026-01-29 02:19:05.102 [INFO] ctrl_if_trx.py:117 (BTS@172.18.28.20:5700) Stopping transceiver...
2026-01-29 02:19:05.102 [INFO] transceiver.py:246 Stopping clock generator
2026-01-29 02:19:05.102 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:19:05.102 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=2261 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:19:05.102 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=2261 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:19:05.102 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=2261 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:19:05.102 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=2261 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:19:05.102 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=2261 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:19:05.102 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=2261 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:19:05.102 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=2261 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:19:05.102 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=2261 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:19:05.102 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=2262 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:19:05.102 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=2262 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:19:10.102 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.28.20:5700) Recv POWEROFF cmd
2026-01-29 02:19:10.102 [INFO] ctrl_if_trx.py:117 (BTS@172.18.28.20:5700) Stopping transceiver...
2026-01-29 02:19:10.104 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:19:10.105 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:19:10.106 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:19:10.106 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 02:19:10.109 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 02:19:10.109 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.28.20:5700) Recv SETFORMAT cmd
2026-01-29 02:19:10.109 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.28.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:19:10.109 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.28.20:5700) Recv SETFORMAT cmd
2026-01-29 02:19:10.109 [INFO] ctrl_if_trx.py:201 (BTS@172.18.28.20:5700) TRXD header version 1 -> 1
2026-01-29 02:19:10.110 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.28.20:5700/1) Recv RXTUNE cmd
2026-01-29 02:19:10.110 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.28.20:5700/1) Recv TXTUNE cmd
2026-01-29 02:19:10.110 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.28.20:5700/1) Recv SETFORMAT cmd
2026-01-29 02:19:10.110 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.28.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:19:10.111 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:19:10.111 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.28.20:5700/1) Recv NOMTXPOWER cmd
2026-01-29 02:19:10.111 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.28.20:5700/1) Recv SETFORMAT cmd
2026-01-29 02:19:10.111 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.28.20:5700/1) TRXD header version 1 -> 1
2026-01-29 02:19:10.112 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.28.20:5700/2) Recv RXTUNE cmd
2026-01-29 02:19:10.112 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.28.20:5700/2) Recv TXTUNE cmd
2026-01-29 02:19:10.113 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.28.20:5700/2) Recv SETFORMAT cmd
2026-01-29 02:19:10.113 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.28.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:19:10.113 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:19:10.113 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.28.20:5700/2) Recv NOMTXPOWER cmd
2026-01-29 02:19:10.113 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.28.20:5700/2) Recv SETFORMAT cmd
2026-01-29 02:19:10.113 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.28.20:5700/2) TRXD header version 1 -> 1
2026-01-29 02:19:10.114 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.28.20:5700/3) Recv RXTUNE cmd
2026-01-29 02:19:10.114 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.28.20:5700/3) Recv TXTUNE cmd
2026-01-29 02:19:10.114 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.28.20:5700/3) Recv SETFORMAT cmd
2026-01-29 02:19:10.114 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.28.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:19:10.114 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:19:10.114 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.28.20:5700/3) Recv NOMTXPOWER cmd
2026-01-29 02:19:10.115 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.28.20:5700/3) Recv SETFORMAT cmd
2026-01-29 02:19:10.115 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.28.20:5700/3) TRXD header version 1 -> 1
2026-01-29 02:19:10.116 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.28.20:5700) Recv RXTUNE cmd
2026-01-29 02:19:10.116 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETTSC
2026-01-29 02:19:10.116 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETTSC
2026-01-29 02:19:10.116 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETTSC
2026-01-29 02:19:10.117 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.28.20:5700) Recv TXTUNE cmd
2026-01-29 02:19:10.117 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETRXGAIN
2026-01-29 02:19:10.117 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETRXGAIN
2026-01-29 02:19:10.117 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETRXGAIN
2026-01-29 02:19:10.117 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETTSC
2026-01-29 02:19:10.117 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:19:10.117 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:19:10.117 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:19:10.117 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.28.20:5700) Recv NOMTXPOWER cmd
2026-01-29 02:19:10.117 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:19:10.117 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:19:10.117 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:19:10.117 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.28.20:5700) Recv POWERON CMD
2026-01-29 02:19:10.117 [INFO] ctrl_if_trx.py:109 (BTS@172.18.28.20:5700) Starting transceiver...
2026-01-29 02:19:10.117 [INFO] transceiver.py:243 Starting clock generator
2026-01-29 02:19:10.117 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-01-29 02:19:10.117 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:19:10.117 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:19:10.117 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:19:10.117 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETRXGAIN
2026-01-29 02:19:10.117 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:19:10.117 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:19:10.117 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:19:10.117 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:19:10.117 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:19:10.117 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:19:10.117 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:19:10.117 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:19:10.117 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:19:10.118 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:19:10.118 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:19:10.118 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:19:10.118 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:19:10.118 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:19:10.118 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:19:10.118 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:19:10.118 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:19:10.118 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:19:10.118 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:19:10.118 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:19:10.118 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:19:10.118 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:19:10.118 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:19:10.119 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:19:10.119 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:19:10.119 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:19:10.119 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 02:19:10.119 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.28.20:5700) Recv POWEROFF cmd
2026-01-29 02:19:10.119 [INFO] ctrl_if_trx.py:117 (BTS@172.18.28.20:5700) Stopping transceiver...
2026-01-29 02:19:10.119 [INFO] transceiver.py:246 Stopping clock generator
2026-01-29 02:19:15.123 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.28.20:5700) Recv POWEROFF cmd
2026-01-29 02:19:15.123 [INFO] ctrl_if_trx.py:117 (BTS@172.18.28.20:5700) Stopping transceiver...
2026-01-29 02:19:15.125 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:19:15.126 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:19:15.127 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:19:15.127 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 02:19:15.130 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 02:19:15.131 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.28.20:5700) Recv SETFORMAT cmd
2026-01-29 02:19:15.131 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.28.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:19:15.131 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.28.20:5700) Recv SETFORMAT cmd
2026-01-29 02:19:15.131 [INFO] ctrl_if_trx.py:201 (BTS@172.18.28.20:5700) TRXD header version 1 -> 1
2026-01-29 02:19:15.133 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.28.20:5700/1) Recv RXTUNE cmd
2026-01-29 02:19:15.133 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.28.20:5700/1) Recv TXTUNE cmd
2026-01-29 02:19:15.133 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.28.20:5700/1) Recv SETFORMAT cmd
2026-01-29 02:19:15.133 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.28.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:19:15.133 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:19:15.134 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.28.20:5700/1) Recv NOMTXPOWER cmd
2026-01-29 02:19:15.134 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.28.20:5700/1) Recv SETFORMAT cmd
2026-01-29 02:19:15.134 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.28.20:5700/1) TRXD header version 1 -> 1
2026-01-29 02:19:15.135 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.28.20:5700/2) Recv RXTUNE cmd
2026-01-29 02:19:15.135 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.28.20:5700/2) Recv TXTUNE cmd
2026-01-29 02:19:15.135 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.28.20:5700/2) Recv SETFORMAT cmd
2026-01-29 02:19:15.135 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.28.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:19:15.135 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:19:15.135 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.28.20:5700/2) Recv NOMTXPOWER cmd
2026-01-29 02:19:15.135 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.28.20:5700/2) Recv SETFORMAT cmd
2026-01-29 02:19:15.135 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.28.20:5700/2) TRXD header version 1 -> 1
2026-01-29 02:19:15.136 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.28.20:5700/3) Recv RXTUNE cmd
2026-01-29 02:19:15.136 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.28.20:5700/3) Recv TXTUNE cmd
2026-01-29 02:19:15.136 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.28.20:5700/3) Recv SETFORMAT cmd
2026-01-29 02:19:15.136 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.28.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:19:15.136 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:19:15.136 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.28.20:5700/3) Recv NOMTXPOWER cmd
2026-01-29 02:19:15.136 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.28.20:5700/3) Recv SETFORMAT cmd
2026-01-29 02:19:15.136 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.28.20:5700/3) TRXD header version 1 -> 1
2026-01-29 02:19:15.138 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.28.20:5700) Recv RXTUNE cmd
2026-01-29 02:19:15.138 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETTSC
2026-01-29 02:19:15.138 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETTSC
2026-01-29 02:19:15.138 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETTSC
2026-01-29 02:19:15.138 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.28.20:5700) Recv TXTUNE cmd
2026-01-29 02:19:15.138 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETRXGAIN
2026-01-29 02:19:15.138 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETRXGAIN
2026-01-29 02:19:15.138 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETRXGAIN
2026-01-29 02:19:15.139 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETTSC
2026-01-29 02:19:15.139 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:19:15.139 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:19:15.139 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:19:15.139 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.28.20:5700) Recv NOMTXPOWER cmd
2026-01-29 02:19:15.139 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:19:15.139 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:19:15.139 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:19:15.139 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.28.20:5700) Recv POWERON CMD
2026-01-29 02:19:15.139 [INFO] ctrl_if_trx.py:109 (BTS@172.18.28.20:5700) Starting transceiver...
2026-01-29 02:19:15.139 [INFO] transceiver.py:243 Starting clock generator
2026-01-29 02:19:15.139 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-01-29 02:19:15.139 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:19:15.139 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:19:15.139 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:19:15.139 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETRXGAIN
2026-01-29 02:19:15.139 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:19:15.139 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:19:15.139 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:19:15.139 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:19:15.139 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:19:15.139 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:19:15.139 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:19:15.139 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:19:15.139 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:19:15.139 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:19:15.139 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:19:15.139 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:19:15.139 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:19:15.139 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:19:15.139 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:19:15.139 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:19:15.139 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:19:15.139 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:19:15.139 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:19:15.139 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:19:15.140 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:19:15.140 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:19:15.140 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:19:15.143 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-01-29 02:19:15.628 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-01-29 02:19:15.654 [DEBUG] fake_trx.py:278 (BTS@172.18.28.20:5700) Recv FAKE_TOA cmd
2026-01-29 02:19:15.655 [DEBUG] fake_trx.py:297 (BTS@172.18.28.20:5700) Recv FAKE_RSSI cmd
2026-01-29 02:19:15.655 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:19:15.656 [DEBUG] fake_trx.py:322 (BTS@172.18.28.20:5700) Recv FAKE_CI cmd
2026-01-29 02:19:15.656 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 02:19:15.656 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 02:19:15.656 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 02:19:15.657 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:19:15.657 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 02:19:15.657 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 02:19:15.657 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.28.22:6700) Recv POWERON CMD
2026-01-29 02:19:15.657 [INFO] ctrl_if_trx.py:109 (MS@172.18.28.22:6700) Starting transceiver...
2026-01-29 02:19:16.105 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-01-29 02:19:16.142 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:19:16.142 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 02:19:16.143 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:19:16.143 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:19:16.583 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-01-29 02:19:17.061 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-01-29 02:19:17.143 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:19:17.143 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:19:17.144 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 02:19:17.144 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:19:17.538 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-01-29 02:19:18.015 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-01-29 02:19:18.144 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:19:18.144 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 02:19:18.144 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:19:18.145 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:19:18.493 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-01-29 02:19:18.970 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-01-29 02:19:19.145 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 02:19:19.145 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:19:19.145 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:19:19.145 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:19:19.448 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-01-29 02:19:19.926 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-01-29 02:19:20.146 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:19:20.147 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:19:20.147 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 02:19:20.147 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:19:20.403 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-01-29 02:19:20.880 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-01-29 02:19:21.358 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-01-29 02:19:21.836 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-01-29 02:19:22.313 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-01-29 02:19:22.791 [DEBUG] clck_gen.py:113 IND CLOCK 1632
2026-01-29 02:19:23.268 [DEBUG] clck_gen.py:113 IND CLOCK 1734
2026-01-29 02:19:23.745 [DEBUG] clck_gen.py:113 IND CLOCK 1836
2026-01-29 02:19:24.223 [DEBUG] clck_gen.py:113 IND CLOCK 1938
2026-01-29 02:19:24.701 [DEBUG] clck_gen.py:113 IND CLOCK 2040
2026-01-29 02:19:25.179 [DEBUG] clck_gen.py:113 IND CLOCK 2142
2026-01-29 02:19:25.658 [DEBUG] clck_gen.py:113 IND CLOCK 2244
2026-01-29 02:19:26.135 [DEBUG] clck_gen.py:113 IND CLOCK 2346
2026-01-29 02:19:26.613 [DEBUG] clck_gen.py:113 IND CLOCK 2448
2026-01-29 02:19:26.675 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 02:19:26.675 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 02:19:26.681 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 02:19:26.681 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:19:26.681 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:19:26.682 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:19:26.687 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 02:19:26.687 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:19:26.688 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:19:26.688 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:19:26.688 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.28.20:5700) Recv POWEROFF cmd
2026-01-29 02:19:26.688 [INFO] ctrl_if_trx.py:117 (BTS@172.18.28.20:5700) Stopping transceiver...
2026-01-29 02:19:26.688 [INFO] transceiver.py:246 Stopping clock generator
2026-01-29 02:19:26.688 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=2464 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:19:26.689 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=2464 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:19:31.685 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.28.20:5700) Recv POWEROFF cmd
2026-01-29 02:19:31.685 [INFO] ctrl_if_trx.py:117 (BTS@172.18.28.20:5700) Stopping transceiver...
2026-01-29 02:19:31.687 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:19:31.688 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:19:31.689 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:19:31.689 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 02:19:31.697 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 02:19:31.698 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.28.20:5700) Recv SETFORMAT cmd
2026-01-29 02:19:31.698 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.28.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:19:31.698 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.28.20:5700) Recv SETFORMAT cmd
2026-01-29 02:19:31.698 [INFO] ctrl_if_trx.py:201 (BTS@172.18.28.20:5700) TRXD header version 1 -> 1
2026-01-29 02:19:31.702 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.28.20:5700/1) Recv RXTUNE cmd
2026-01-29 02:19:31.703 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.28.20:5700/1) Recv TXTUNE cmd
2026-01-29 02:19:31.703 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.28.20:5700/1) Recv SETFORMAT cmd
2026-01-29 02:19:31.703 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.28.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:19:31.704 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:19:31.704 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.28.20:5700/1) Recv NOMTXPOWER cmd
2026-01-29 02:19:31.705 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.28.20:5700/1) Recv SETFORMAT cmd
2026-01-29 02:19:31.705 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.28.20:5700/1) TRXD header version 1 -> 1
2026-01-29 02:19:31.706 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.28.20:5700/2) Recv RXTUNE cmd
2026-01-29 02:19:31.707 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.28.20:5700/2) Recv TXTUNE cmd
2026-01-29 02:19:31.707 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.28.20:5700/2) Recv SETFORMAT cmd
2026-01-29 02:19:31.707 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.28.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:19:31.707 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:19:31.707 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.28.20:5700/2) Recv NOMTXPOWER cmd
2026-01-29 02:19:31.708 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.28.20:5700/2) Recv SETFORMAT cmd
2026-01-29 02:19:31.708 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.28.20:5700/2) TRXD header version 1 -> 1
2026-01-29 02:19:31.709 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.28.20:5700/3) Recv RXTUNE cmd
2026-01-29 02:19:31.710 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.28.20:5700/3) Recv TXTUNE cmd
2026-01-29 02:19:31.710 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.28.20:5700/3) Recv SETFORMAT cmd
2026-01-29 02:19:31.710 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.28.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:19:31.710 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:19:31.710 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.28.20:5700/3) Recv NOMTXPOWER cmd
2026-01-29 02:19:31.710 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.28.20:5700/3) Recv SETFORMAT cmd
2026-01-29 02:19:31.710 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.28.20:5700/3) TRXD header version 1 -> 1
2026-01-29 02:19:31.712 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.28.20:5700) Recv RXTUNE cmd
2026-01-29 02:19:31.712 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETTSC
2026-01-29 02:19:31.712 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETTSC
2026-01-29 02:19:31.712 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETTSC
2026-01-29 02:19:31.712 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.28.20:5700) Recv TXTUNE cmd
2026-01-29 02:19:31.712 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETRXGAIN
2026-01-29 02:19:31.712 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETRXGAIN
2026-01-29 02:19:31.713 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETRXGAIN
2026-01-29 02:19:31.713 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETTSC
2026-01-29 02:19:31.713 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:19:31.713 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:19:31.713 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:19:31.713 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.28.20:5700) Recv NOMTXPOWER cmd
2026-01-29 02:19:31.713 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:19:31.713 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:19:31.713 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:19:31.713 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.28.20:5700) Recv POWERON CMD
2026-01-29 02:19:31.713 [INFO] ctrl_if_trx.py:109 (BTS@172.18.28.20:5700) Starting transceiver...
2026-01-29 02:19:31.713 [INFO] transceiver.py:243 Starting clock generator
2026-01-29 02:19:31.713 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-01-29 02:19:31.713 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:19:31.713 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:19:31.713 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:19:31.713 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETRXGAIN
2026-01-29 02:19:31.713 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:19:31.713 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:19:31.713 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:19:31.713 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:19:31.713 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:19:31.713 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:19:31.713 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:19:31.713 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:19:31.713 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:19:31.713 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:19:31.714 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:19:31.714 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:19:31.714 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:19:31.714 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:19:31.714 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:19:31.714 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:19:31.714 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:19:31.714 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:19:31.714 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:19:31.715 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:19:31.715 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:19:31.715 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:19:31.715 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:19:31.715 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:19:31.715 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:19:31.715 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:19:31.715 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 02:19:31.715 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.28.20:5700) Recv POWEROFF cmd
2026-01-29 02:19:31.715 [INFO] ctrl_if_trx.py:117 (BTS@172.18.28.20:5700) Stopping transceiver...
2026-01-29 02:19:31.715 [INFO] transceiver.py:246 Stopping clock generator
2026-01-29 02:19:36.718 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.28.20:5700) Recv POWEROFF cmd
2026-01-29 02:19:36.718 [INFO] ctrl_if_trx.py:117 (BTS@172.18.28.20:5700) Stopping transceiver...
2026-01-29 02:19:36.720 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:19:36.721 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:19:36.722 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:19:36.722 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 02:19:36.725 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 02:19:36.726 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.28.20:5700) Recv SETFORMAT cmd
2026-01-29 02:19:36.726 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.28.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:19:36.727 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.28.20:5700) Recv SETFORMAT cmd
2026-01-29 02:19:36.727 [INFO] ctrl_if_trx.py:201 (BTS@172.18.28.20:5700) TRXD header version 1 -> 1
2026-01-29 02:19:36.729 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.28.20:5700/1) Recv RXTUNE cmd
2026-01-29 02:19:36.729 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.28.20:5700/1) Recv TXTUNE cmd
2026-01-29 02:19:36.729 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.28.20:5700/1) Recv SETFORMAT cmd
2026-01-29 02:19:36.729 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.28.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:19:36.730 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:19:36.730 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.28.20:5700/1) Recv NOMTXPOWER cmd
2026-01-29 02:19:36.730 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.28.20:5700/1) Recv SETFORMAT cmd
2026-01-29 02:19:36.730 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.28.20:5700/1) TRXD header version 1 -> 1
2026-01-29 02:19:36.731 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.28.20:5700/2) Recv RXTUNE cmd
2026-01-29 02:19:36.731 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.28.20:5700/2) Recv TXTUNE cmd
2026-01-29 02:19:36.732 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.28.20:5700/2) Recv SETFORMAT cmd
2026-01-29 02:19:36.732 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.28.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:19:36.732 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:19:36.732 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.28.20:5700/2) Recv NOMTXPOWER cmd
2026-01-29 02:19:36.732 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.28.20:5700/2) Recv SETFORMAT cmd
2026-01-29 02:19:36.732 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.28.20:5700/2) TRXD header version 1 -> 1
2026-01-29 02:19:36.733 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.28.20:5700/3) Recv RXTUNE cmd
2026-01-29 02:19:36.733 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.28.20:5700/3) Recv TXTUNE cmd
2026-01-29 02:19:36.733 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.28.20:5700/3) Recv SETFORMAT cmd
2026-01-29 02:19:36.733 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.28.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:19:36.733 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:19:36.733 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.28.20:5700/3) Recv NOMTXPOWER cmd
2026-01-29 02:19:36.733 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.28.20:5700/3) Recv SETFORMAT cmd
2026-01-29 02:19:36.733 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.28.20:5700/3) TRXD header version 1 -> 1
2026-01-29 02:19:36.735 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.28.20:5700) Recv RXTUNE cmd
2026-01-29 02:19:36.736 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETTSC
2026-01-29 02:19:36.736 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETTSC
2026-01-29 02:19:36.736 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETTSC
2026-01-29 02:19:36.736 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.28.20:5700) Recv TXTUNE cmd
2026-01-29 02:19:36.736 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETRXGAIN
2026-01-29 02:19:36.736 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETRXGAIN
2026-01-29 02:19:36.736 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETRXGAIN
2026-01-29 02:19:36.736 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETTSC
2026-01-29 02:19:36.736 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:19:36.736 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:19:36.736 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:19:36.736 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.28.20:5700) Recv NOMTXPOWER cmd
2026-01-29 02:19:36.736 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:19:36.736 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:19:36.736 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:19:36.736 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.28.20:5700) Recv POWERON CMD
2026-01-29 02:19:36.736 [INFO] ctrl_if_trx.py:109 (BTS@172.18.28.20:5700) Starting transceiver...
2026-01-29 02:19:36.736 [INFO] transceiver.py:243 Starting clock generator
2026-01-29 02:19:36.736 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-01-29 02:19:36.736 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:19:36.736 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:19:36.736 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:19:36.736 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETRXGAIN
2026-01-29 02:19:36.736 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:19:36.736 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:19:36.736 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:19:36.736 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:19:36.736 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:19:36.736 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:19:36.736 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:19:36.737 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:19:36.737 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:19:36.737 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:19:36.737 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:19:36.737 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:19:36.737 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:19:36.737 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:19:36.737 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:19:36.737 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:19:36.737 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:19:36.737 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:19:36.737 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:19:36.737 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:19:36.737 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:19:36.737 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:19:36.737 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:19:36.741 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-01-29 02:19:37.223 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-01-29 02:19:37.258 [DEBUG] fake_trx.py:278 (BTS@172.18.28.20:5700) Recv FAKE_TOA cmd
2026-01-29 02:19:37.258 [DEBUG] fake_trx.py:297 (BTS@172.18.28.20:5700) Recv FAKE_RSSI cmd
2026-01-29 02:19:37.259 [DEBUG] fake_trx.py:322 (BTS@172.18.28.20:5700) Recv FAKE_CI cmd
2026-01-29 02:19:37.260 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:19:37.262 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 02:19:37.263 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 02:19:37.263 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 02:19:37.263 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:19:37.264 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 02:19:37.264 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 02:19:37.264 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.28.22:6700) Recv POWERON CMD
2026-01-29 02:19:37.264 [INFO] ctrl_if_trx.py:109 (MS@172.18.28.22:6700) Starting transceiver...
2026-01-29 02:19:37.700 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-01-29 02:19:37.738 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 02:19:37.739 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:19:37.739 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:19:37.741 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:19:38.178 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-01-29 02:19:38.655 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-01-29 02:19:38.739 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 02:19:38.739 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:19:38.740 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:19:38.742 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:19:39.133 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-01-29 02:19:39.611 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-01-29 02:19:39.740 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:19:39.741 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:19:39.741 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 02:19:39.742 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:19:40.089 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-01-29 02:19:40.566 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-01-29 02:19:40.742 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 02:19:40.742 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:19:40.742 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:19:40.743 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:19:41.044 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-01-29 02:19:41.522 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-01-29 02:19:41.743 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:19:41.743 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:19:41.744 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 02:19:41.744 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:19:42.000 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-01-29 02:19:42.477 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-01-29 02:19:42.954 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-01-29 02:19:43.432 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-01-29 02:19:43.910 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-01-29 02:19:44.388 [DEBUG] clck_gen.py:113 IND CLOCK 1632
2026-01-29 02:19:44.866 [DEBUG] clck_gen.py:113 IND CLOCK 1734
2026-01-29 02:19:45.344 [DEBUG] clck_gen.py:113 IND CLOCK 1836
2026-01-29 02:19:45.846 [DEBUG] clck_gen.py:113 IND CLOCK 1938
2026-01-29 02:19:46.324 [DEBUG] clck_gen.py:113 IND CLOCK 2040
2026-01-29 02:19:46.802 [DEBUG] clck_gen.py:113 IND CLOCK 2142
2026-01-29 02:19:47.279 [DEBUG] clck_gen.py:113 IND CLOCK 2244
2026-01-29 02:19:47.757 [DEBUG] clck_gen.py:113 IND CLOCK 2346
2026-01-29 02:19:48.234 [DEBUG] clck_gen.py:113 IND CLOCK 2448
2026-01-29 02:19:48.712 [DEBUG] clck_gen.py:113 IND CLOCK 2550
2026-01-29 02:19:49.189 [DEBUG] clck_gen.py:113 IND CLOCK 2652
2026-01-29 02:19:49.668 [DEBUG] clck_gen.py:113 IND CLOCK 2754
2026-01-29 02:19:50.145 [DEBUG] clck_gen.py:113 IND CLOCK 2856
2026-01-29 02:19:50.623 [DEBUG] clck_gen.py:113 IND CLOCK 2958
2026-01-29 02:19:51.101 [DEBUG] clck_gen.py:113 IND CLOCK 3060
2026-01-29 02:19:51.578 [DEBUG] clck_gen.py:113 IND CLOCK 3162
2026-01-29 02:19:52.055 [DEBUG] clck_gen.py:113 IND CLOCK 3264
2026-01-29 02:19:52.533 [DEBUG] clck_gen.py:113 IND CLOCK 3366
2026-01-29 02:19:53.011 [DEBUG] clck_gen.py:113 IND CLOCK 3468
2026-01-29 02:19:53.488 [DEBUG] clck_gen.py:113 IND CLOCK 3570
2026-01-29 02:19:53.966 [DEBUG] clck_gen.py:113 IND CLOCK 3672
2026-01-29 02:19:54.443 [DEBUG] clck_gen.py:113 IND CLOCK 3774
2026-01-29 02:19:54.921 [DEBUG] clck_gen.py:113 IND CLOCK 3876
2026-01-29 02:19:55.399 [DEBUG] clck_gen.py:113 IND CLOCK 3978
2026-01-29 02:19:55.885 [DEBUG] clck_gen.py:113 IND CLOCK 4080
2026-01-29 02:19:56.363 [DEBUG] clck_gen.py:113 IND CLOCK 4182
2026-01-29 02:19:56.840 [DEBUG] clck_gen.py:113 IND CLOCK 4284
2026-01-29 02:19:57.277 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 02:19:57.277 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 02:19:57.281 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 02:19:57.281 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:19:57.281 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:19:57.281 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:19:57.281 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 02:19:57.281 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:19:57.281 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:19:57.281 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:19:57.281 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.28.20:5700) Recv POWEROFF cmd
2026-01-29 02:19:57.281 [INFO] ctrl_if_trx.py:117 (BTS@172.18.28.20:5700) Stopping transceiver...
2026-01-29 02:19:57.281 [INFO] transceiver.py:246 Stopping clock generator
2026-01-29 02:19:57.281 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=4381 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:19:57.282 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=4381 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:19:57.282 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=4381 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:19:57.282 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=4381 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:19:57.282 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=4381 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:19:57.282 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=4381 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:19:57.282 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=4381 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:20:02.285 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.28.20:5700) Recv POWEROFF cmd
2026-01-29 02:20:02.285 [INFO] ctrl_if_trx.py:117 (BTS@172.18.28.20:5700) Stopping transceiver...
2026-01-29 02:20:02.287 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:20:02.290 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:20:02.292 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:20:02.296 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 02:20:02.304 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 02:20:02.304 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.28.20:5700) Recv SETFORMAT cmd
2026-01-29 02:20:02.304 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.28.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:20:02.304 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.28.20:5700) Recv SETFORMAT cmd
2026-01-29 02:20:02.304 [INFO] ctrl_if_trx.py:201 (BTS@172.18.28.20:5700) TRXD header version 1 -> 1
2026-01-29 02:20:02.306 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.28.20:5700/1) Recv RXTUNE cmd
2026-01-29 02:20:02.306 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.28.20:5700/1) Recv TXTUNE cmd
2026-01-29 02:20:02.306 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.28.20:5700/1) Recv SETFORMAT cmd
2026-01-29 02:20:02.306 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.28.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:20:02.306 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:20:02.306 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.28.20:5700/1) Recv NOMTXPOWER cmd
2026-01-29 02:20:02.306 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.28.20:5700/1) Recv SETFORMAT cmd
2026-01-29 02:20:02.306 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.28.20:5700/1) TRXD header version 1 -> 1
2026-01-29 02:20:02.307 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.28.20:5700/2) Recv RXTUNE cmd
2026-01-29 02:20:02.307 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.28.20:5700/2) Recv TXTUNE cmd
2026-01-29 02:20:02.307 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.28.20:5700/2) Recv SETFORMAT cmd
2026-01-29 02:20:02.307 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.28.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:20:02.307 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:20:02.307 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.28.20:5700/2) Recv NOMTXPOWER cmd
2026-01-29 02:20:02.307 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.28.20:5700/2) Recv SETFORMAT cmd
2026-01-29 02:20:02.307 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.28.20:5700/2) TRXD header version 1 -> 1
2026-01-29 02:20:02.308 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.28.20:5700/3) Recv RXTUNE cmd
2026-01-29 02:20:02.308 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.28.20:5700/3) Recv TXTUNE cmd
2026-01-29 02:20:02.308 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.28.20:5700/3) Recv SETFORMAT cmd
2026-01-29 02:20:02.308 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.28.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:20:02.308 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:20:02.308 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.28.20:5700/3) Recv NOMTXPOWER cmd
2026-01-29 02:20:02.308 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.28.20:5700/3) Recv SETFORMAT cmd
2026-01-29 02:20:02.308 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.28.20:5700/3) TRXD header version 1 -> 1
2026-01-29 02:20:02.310 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.28.20:5700) Recv RXTUNE cmd
2026-01-29 02:20:02.310 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETTSC
2026-01-29 02:20:02.310 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETTSC
2026-01-29 02:20:02.310 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETTSC
2026-01-29 02:20:02.310 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.28.20:5700) Recv TXTUNE cmd
2026-01-29 02:20:02.310 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETRXGAIN
2026-01-29 02:20:02.310 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETRXGAIN
2026-01-29 02:20:02.310 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETRXGAIN
2026-01-29 02:20:02.310 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETTSC
2026-01-29 02:20:02.310 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:20:02.310 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:20:02.310 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.28.20:5700) Recv NOMTXPOWER cmd
2026-01-29 02:20:02.310 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:20:02.310 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:20:02.310 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:20:02.310 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.28.20:5700) Recv POWERON CMD
2026-01-29 02:20:02.310 [INFO] ctrl_if_trx.py:109 (BTS@172.18.28.20:5700) Starting transceiver...
2026-01-29 02:20:02.310 [INFO] transceiver.py:243 Starting clock generator
2026-01-29 02:20:02.310 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-01-29 02:20:02.310 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:20:02.310 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:20:02.310 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:20:02.310 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETRXGAIN
2026-01-29 02:20:02.310 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:20:02.311 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:20:02.311 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:20:02.311 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:20:02.311 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:20:02.311 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:20:02.311 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:20:02.311 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:20:02.311 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:20:02.311 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:20:02.311 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:20:02.311 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:20:02.311 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:20:02.312 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:20:02.312 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:20:02.312 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:20:02.312 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:20:02.312 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:20:02.312 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:20:02.312 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:20:02.312 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:20:02.312 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:20:02.312 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:20:02.312 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:20:02.312 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:20:02.312 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:20:02.312 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:20:02.312 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 02:20:02.312 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.28.20:5700) Recv POWEROFF cmd
2026-01-29 02:20:02.312 [INFO] ctrl_if_trx.py:117 (BTS@172.18.28.20:5700) Stopping transceiver...
2026-01-29 02:20:02.312 [INFO] transceiver.py:246 Stopping clock generator
2026-01-29 02:20:07.315 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.28.20:5700) Recv POWEROFF cmd
2026-01-29 02:20:07.315 [INFO] ctrl_if_trx.py:117 (BTS@172.18.28.20:5700) Stopping transceiver...
2026-01-29 02:20:07.316 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:20:07.318 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:20:07.318 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:20:07.318 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 02:20:07.321 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 02:20:07.321 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.28.20:5700) Recv SETFORMAT cmd
2026-01-29 02:20:07.321 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.28.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:20:07.321 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.28.20:5700) Recv SETFORMAT cmd
2026-01-29 02:20:07.321 [INFO] ctrl_if_trx.py:201 (BTS@172.18.28.20:5700) TRXD header version 1 -> 1
2026-01-29 02:20:07.322 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.28.20:5700/1) Recv RXTUNE cmd
2026-01-29 02:20:07.322 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.28.20:5700/1) Recv TXTUNE cmd
2026-01-29 02:20:07.322 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.28.20:5700/1) Recv SETFORMAT cmd
2026-01-29 02:20:07.322 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.28.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:20:07.322 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:20:07.322 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.28.20:5700/1) Recv NOMTXPOWER cmd
2026-01-29 02:20:07.322 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.28.20:5700/1) Recv SETFORMAT cmd
2026-01-29 02:20:07.322 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.28.20:5700/1) TRXD header version 1 -> 1
2026-01-29 02:20:07.323 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.28.20:5700/2) Recv RXTUNE cmd
2026-01-29 02:20:07.323 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.28.20:5700/2) Recv TXTUNE cmd
2026-01-29 02:20:07.323 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.28.20:5700/2) Recv SETFORMAT cmd
2026-01-29 02:20:07.323 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.28.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:20:07.323 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:20:07.323 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.28.20:5700/2) Recv NOMTXPOWER cmd
2026-01-29 02:20:07.323 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.28.20:5700/2) Recv SETFORMAT cmd
2026-01-29 02:20:07.323 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.28.20:5700/2) TRXD header version 1 -> 1
2026-01-29 02:20:07.324 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.28.20:5700/3) Recv RXTUNE cmd
2026-01-29 02:20:07.324 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.28.20:5700/3) Recv TXTUNE cmd
2026-01-29 02:20:07.324 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.28.20:5700/3) Recv SETFORMAT cmd
2026-01-29 02:20:07.324 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.28.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:20:07.324 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:20:07.324 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.28.20:5700/3) Recv NOMTXPOWER cmd
2026-01-29 02:20:07.324 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.28.20:5700/3) Recv SETFORMAT cmd
2026-01-29 02:20:07.324 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.28.20:5700/3) TRXD header version 1 -> 1
2026-01-29 02:20:07.325 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.28.20:5700) Recv RXTUNE cmd
2026-01-29 02:20:07.325 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETTSC
2026-01-29 02:20:07.325 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETTSC
2026-01-29 02:20:07.326 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETTSC
2026-01-29 02:20:07.326 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.28.20:5700) Recv TXTUNE cmd
2026-01-29 02:20:07.326 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETRXGAIN
2026-01-29 02:20:07.326 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETRXGAIN
2026-01-29 02:20:07.326 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETRXGAIN
2026-01-29 02:20:07.326 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETTSC
2026-01-29 02:20:07.326 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:20:07.326 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:20:07.326 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.28.20:5700) Recv NOMTXPOWER cmd
2026-01-29 02:20:07.326 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:20:07.326 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:20:07.326 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:20:07.326 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.28.20:5700) Recv POWERON CMD
2026-01-29 02:20:07.326 [INFO] ctrl_if_trx.py:109 (BTS@172.18.28.20:5700) Starting transceiver...
2026-01-29 02:20:07.326 [INFO] transceiver.py:243 Starting clock generator
2026-01-29 02:20:07.326 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-01-29 02:20:07.326 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:20:07.326 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:20:07.326 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:20:07.326 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETRXGAIN
2026-01-29 02:20:07.326 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:20:07.326 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:20:07.326 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:20:07.326 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:20:07.326 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:20:07.326 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:20:07.326 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:20:07.326 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:20:07.326 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:20:07.326 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:20:07.326 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:20:07.326 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:20:07.326 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:20:07.326 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:20:07.326 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:20:07.326 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:20:07.326 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:20:07.326 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:20:07.326 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:20:07.327 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:20:07.327 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:20:07.327 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:20:07.327 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:20:07.327 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:20:07.331 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-01-29 02:20:07.814 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-01-29 02:20:07.847 [DEBUG] fake_trx.py:278 (BTS@172.18.28.20:5700) Recv FAKE_TOA cmd
2026-01-29 02:20:07.848 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:20:07.849 [DEBUG] fake_trx.py:297 (BTS@172.18.28.20:5700) Recv FAKE_RSSI cmd
2026-01-29 02:20:07.849 [DEBUG] fake_trx.py:322 (BTS@172.18.28.20:5700) Recv FAKE_CI cmd
2026-01-29 02:20:08.283 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-01-29 02:20:08.328 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:20:08.329 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 02:20:08.329 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:20:08.330 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:20:08.752 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-01-29 02:20:09.223 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-01-29 02:20:09.329 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:20:09.330 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:20:09.330 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 02:20:09.332 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:20:09.701 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-01-29 02:20:10.179 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-01-29 02:20:10.330 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:20:10.331 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:20:10.331 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 02:20:10.333 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:20:10.657 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-01-29 02:20:11.138 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-01-29 02:20:11.331 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:20:11.332 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 02:20:11.332 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:20:11.335 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:20:11.619 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-01-29 02:20:12.098 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-01-29 02:20:12.333 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:20:12.333 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 02:20:12.333 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:20:12.336 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:20:12.576 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-01-29 02:20:13.057 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-01-29 02:20:13.536 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-01-29 02:20:14.015 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-01-29 02:20:14.493 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-01-29 02:20:14.971 [DEBUG] clck_gen.py:113 IND CLOCK 1632
2026-01-29 02:20:15.442 [DEBUG] clck_gen.py:113 IND CLOCK 1734
2026-01-29 02:20:15.916 [DEBUG] clck_gen.py:113 IND CLOCK 1836
2026-01-29 02:20:16.384 [DEBUG] clck_gen.py:113 IND CLOCK 1938
2026-01-29 02:20:16.859 [DEBUG] clck_gen.py:113 IND CLOCK 2040
2026-01-29 02:20:17.340 [DEBUG] clck_gen.py:113 IND CLOCK 2142
2026-01-29 02:20:17.819 [DEBUG] clck_gen.py:113 IND CLOCK 2244
2026-01-29 02:20:17.862 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 02:20:17.862 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:20:17.862 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:20:17.862 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:20:17.863 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 02:20:17.863 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:20:17.863 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:20:17.863 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.28.20:5700) Recv POWEROFF cmd
2026-01-29 02:20:17.863 [INFO] ctrl_if_trx.py:117 (BTS@172.18.28.20:5700) Stopping transceiver...
2026-01-29 02:20:17.863 [INFO] transceiver.py:246 Stopping clock generator
2026-01-29 02:20:17.863 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:20:22.866 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.28.20:5700) Recv POWEROFF cmd
2026-01-29 02:20:22.866 [INFO] ctrl_if_trx.py:117 (BTS@172.18.28.20:5700) Stopping transceiver...
2026-01-29 02:20:22.866 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:20:22.866 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:20:22.866 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:20:22.866 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 02:20:22.868 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 02:20:22.869 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.28.20:5700) Recv SETFORMAT cmd
2026-01-29 02:20:22.869 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.28.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:20:22.869 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.28.20:5700) Recv SETFORMAT cmd
2026-01-29 02:20:22.869 [INFO] ctrl_if_trx.py:201 (BTS@172.18.28.20:5700) TRXD header version 1 -> 1
2026-01-29 02:20:22.869 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.28.20:5700/1) Recv RXTUNE cmd
2026-01-29 02:20:22.870 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.28.20:5700/1) Recv TXTUNE cmd
2026-01-29 02:20:22.870 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.28.20:5700/1) Recv SETFORMAT cmd
2026-01-29 02:20:22.870 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.28.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:20:22.870 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:20:22.870 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.28.20:5700/1) Recv NOMTXPOWER cmd
2026-01-29 02:20:22.870 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.28.20:5700/1) Recv SETFORMAT cmd
2026-01-29 02:20:22.870 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.28.20:5700/1) TRXD header version 1 -> 1
2026-01-29 02:20:22.871 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.28.20:5700/2) Recv RXTUNE cmd
2026-01-29 02:20:22.871 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.28.20:5700/2) Recv TXTUNE cmd
2026-01-29 02:20:22.871 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.28.20:5700/2) Recv SETFORMAT cmd
2026-01-29 02:20:22.871 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.28.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:20:22.871 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:20:22.871 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.28.20:5700/2) Recv NOMTXPOWER cmd
2026-01-29 02:20:22.871 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.28.20:5700/2) Recv SETFORMAT cmd
2026-01-29 02:20:22.871 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.28.20:5700/2) TRXD header version 1 -> 1
2026-01-29 02:20:22.872 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.28.20:5700/3) Recv RXTUNE cmd
2026-01-29 02:20:22.872 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.28.20:5700/3) Recv TXTUNE cmd
2026-01-29 02:20:22.872 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.28.20:5700/3) Recv SETFORMAT cmd
2026-01-29 02:20:22.872 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.28.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:20:22.872 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:20:22.872 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.28.20:5700/3) Recv NOMTXPOWER cmd
2026-01-29 02:20:22.872 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.28.20:5700/3) Recv SETFORMAT cmd
2026-01-29 02:20:22.872 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.28.20:5700/3) TRXD header version 1 -> 1
2026-01-29 02:20:22.873 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.28.20:5700) Recv RXTUNE cmd
2026-01-29 02:20:22.873 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETTSC
2026-01-29 02:20:22.873 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETTSC
2026-01-29 02:20:22.873 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETTSC
2026-01-29 02:20:22.873 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.28.20:5700) Recv TXTUNE cmd
2026-01-29 02:20:22.873 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETRXGAIN
2026-01-29 02:20:22.873 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETRXGAIN
2026-01-29 02:20:22.873 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETRXGAIN
2026-01-29 02:20:22.873 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETTSC
2026-01-29 02:20:22.873 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:20:22.873 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:20:22.874 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.28.20:5700) Recv NOMTXPOWER cmd
2026-01-29 02:20:22.874 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:20:22.874 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:20:22.874 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:20:22.874 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.28.20:5700) Recv POWERON CMD
2026-01-29 02:20:22.874 [INFO] ctrl_if_trx.py:109 (BTS@172.18.28.20:5700) Starting transceiver...
2026-01-29 02:20:22.874 [INFO] transceiver.py:243 Starting clock generator
2026-01-29 02:20:22.874 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-01-29 02:20:22.874 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:20:22.874 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:20:22.874 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:20:22.874 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETRXGAIN
2026-01-29 02:20:22.874 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:20:22.874 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:20:22.874 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:20:22.874 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:20:22.874 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:20:22.874 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:20:22.874 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:20:22.874 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:20:22.874 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:20:22.874 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:20:22.874 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:20:22.874 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:20:22.874 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:20:22.874 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:20:22.875 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:20:22.875 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:20:22.875 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:20:22.875 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:20:22.875 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:20:22.875 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:20:22.875 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:20:22.875 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:20:22.875 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:20:22.875 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:20:22.875 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:20:22.875 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:20:22.875 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:20:22.875 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 02:20:22.875 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.28.20:5700) Recv POWEROFF cmd
2026-01-29 02:20:22.875 [INFO] ctrl_if_trx.py:117 (BTS@172.18.28.20:5700) Stopping transceiver...
2026-01-29 02:20:22.875 [INFO] transceiver.py:246 Stopping clock generator
2026-01-29 02:20:27.882 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.28.20:5700) Recv POWEROFF cmd
2026-01-29 02:20:27.882 [INFO] ctrl_if_trx.py:117 (BTS@172.18.28.20:5700) Stopping transceiver...
2026-01-29 02:20:27.882 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:20:27.882 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:20:27.882 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:20:27.882 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 02:20:27.884 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 02:20:27.884 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.28.20:5700) Recv SETFORMAT cmd
2026-01-29 02:20:27.885 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.28.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:20:27.885 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.28.20:5700) Recv SETFORMAT cmd
2026-01-29 02:20:27.885 [INFO] ctrl_if_trx.py:201 (BTS@172.18.28.20:5700) TRXD header version 1 -> 1
2026-01-29 02:20:27.885 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.28.20:5700/1) Recv RXTUNE cmd
2026-01-29 02:20:27.885 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.28.20:5700/1) Recv TXTUNE cmd
2026-01-29 02:20:27.886 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.28.20:5700/1) Recv SETFORMAT cmd
2026-01-29 02:20:27.886 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.28.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:20:27.886 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:20:27.886 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.28.20:5700/1) Recv NOMTXPOWER cmd
2026-01-29 02:20:27.886 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.28.20:5700/1) Recv SETFORMAT cmd
2026-01-29 02:20:27.886 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.28.20:5700/1) TRXD header version 1 -> 1
2026-01-29 02:20:27.886 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.28.20:5700/2) Recv RXTUNE cmd
2026-01-29 02:20:27.886 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.28.20:5700/2) Recv TXTUNE cmd
2026-01-29 02:20:27.886 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.28.20:5700/2) Recv SETFORMAT cmd
2026-01-29 02:20:27.886 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.28.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:20:27.886 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:20:27.887 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.28.20:5700/2) Recv NOMTXPOWER cmd
2026-01-29 02:20:27.887 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.28.20:5700/2) Recv SETFORMAT cmd
2026-01-29 02:20:27.887 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.28.20:5700/2) TRXD header version 1 -> 1
2026-01-29 02:20:27.887 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.28.20:5700/3) Recv RXTUNE cmd
2026-01-29 02:20:27.887 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.28.20:5700/3) Recv TXTUNE cmd
2026-01-29 02:20:27.887 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.28.20:5700/3) Recv SETFORMAT cmd
2026-01-29 02:20:27.887 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.28.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:20:27.888 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:20:27.888 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.28.20:5700/3) Recv NOMTXPOWER cmd
2026-01-29 02:20:27.888 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.28.20:5700/3) Recv SETFORMAT cmd
2026-01-29 02:20:27.888 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.28.20:5700/3) TRXD header version 1 -> 1
2026-01-29 02:20:27.889 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.28.20:5700) Recv RXTUNE cmd
2026-01-29 02:20:27.889 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETTSC
2026-01-29 02:20:27.889 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETTSC
2026-01-29 02:20:27.889 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETTSC
2026-01-29 02:20:27.889 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.28.20:5700) Recv TXTUNE cmd
2026-01-29 02:20:27.889 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETRXGAIN
2026-01-29 02:20:27.889 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETRXGAIN
2026-01-29 02:20:27.889 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETRXGAIN
2026-01-29 02:20:27.889 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETTSC
2026-01-29 02:20:27.889 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:20:27.889 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:20:27.889 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.28.20:5700) Recv NOMTXPOWER cmd
2026-01-29 02:20:27.889 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:20:27.889 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:20:27.889 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:20:27.889 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.28.20:5700) Recv POWERON CMD
2026-01-29 02:20:27.889 [INFO] ctrl_if_trx.py:109 (BTS@172.18.28.20:5700) Starting transceiver...
2026-01-29 02:20:27.889 [INFO] transceiver.py:243 Starting clock generator
2026-01-29 02:20:27.889 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-01-29 02:20:27.890 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:20:27.890 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:20:27.890 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:20:27.890 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETRXGAIN
2026-01-29 02:20:27.890 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:20:27.890 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:20:27.890 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:20:27.890 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:20:27.890 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:20:27.890 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:20:27.890 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:20:27.890 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:20:27.890 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:20:27.890 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:20:27.890 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:20:27.890 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:20:27.890 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:20:27.890 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:20:27.890 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:20:27.890 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:20:27.890 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:20:27.890 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:20:27.890 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:20:27.890 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:20:27.890 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:20:27.890 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:20:27.890 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:20:27.890 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:20:27.894 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-01-29 02:20:28.378 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-01-29 02:20:28.412 [DEBUG] fake_trx.py:278 (BTS@172.18.28.20:5700) Recv FAKE_TOA cmd
2026-01-29 02:20:28.414 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:20:28.415 [DEBUG] fake_trx.py:297 (BTS@172.18.28.20:5700) Recv FAKE_RSSI cmd
2026-01-29 02:20:28.417 [DEBUG] fake_trx.py:322 (BTS@172.18.28.20:5700) Recv FAKE_CI cmd
2026-01-29 02:20:28.856 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-01-29 02:20:28.892 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:20:28.892 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 02:20:28.893 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:20:28.895 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:20:29.335 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-01-29 02:20:29.817 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-01-29 02:20:29.893 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:20:29.893 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 02:20:29.894 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:20:29.896 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:20:30.295 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-01-29 02:20:30.773 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-01-29 02:20:30.895 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:20:30.895 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 02:20:30.895 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:20:30.897 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:20:31.252 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-01-29 02:20:31.733 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-01-29 02:20:31.895 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:20:31.896 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 02:20:31.896 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:20:31.898 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:20:32.214 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-01-29 02:20:32.695 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-01-29 02:20:32.897 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 02:20:32.897 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:20:32.898 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:20:32.899 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:20:33.176 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-01-29 02:20:33.658 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-01-29 02:20:34.136 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-01-29 02:20:34.615 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-01-29 02:20:35.095 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-01-29 02:20:35.577 [DEBUG] clck_gen.py:113 IND CLOCK 1632
2026-01-29 02:20:36.059 [DEBUG] clck_gen.py:113 IND CLOCK 1734
2026-01-29 02:20:36.540 [DEBUG] clck_gen.py:113 IND CLOCK 1836
2026-01-29 02:20:37.021 [DEBUG] clck_gen.py:113 IND CLOCK 1938
2026-01-29 02:20:37.502 [DEBUG] clck_gen.py:113 IND CLOCK 2040
2026-01-29 02:20:37.983 [DEBUG] clck_gen.py:113 IND CLOCK 2142
2026-01-29 02:20:38.461 [DEBUG] clck_gen.py:113 IND CLOCK 2244
2026-01-29 02:20:38.929 [DEBUG] clck_gen.py:113 IND CLOCK 2346
2026-01-29 02:20:39.401 [DEBUG] clck_gen.py:113 IND CLOCK 2448
2026-01-29 02:20:39.876 [DEBUG] clck_gen.py:113 IND CLOCK 2550
2026-01-29 02:20:40.344 [DEBUG] clck_gen.py:113 IND CLOCK 2652
2026-01-29 02:20:40.429 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 02:20:40.429 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:20:40.430 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:20:40.430 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:20:40.431 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 02:20:40.431 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:20:40.431 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:20:40.431 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:20:40.431 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.28.20:5700) Recv POWEROFF cmd
2026-01-29 02:20:40.431 [INFO] ctrl_if_trx.py:117 (BTS@172.18.28.20:5700) Stopping transceiver...
2026-01-29 02:20:40.431 [INFO] transceiver.py:246 Stopping clock generator
2026-01-29 02:20:40.431 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=2673 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:20:40.431 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=2673 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:20:40.431 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=2673 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:20:40.431 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=2673 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:20:40.431 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=2673 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:20:40.431 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=2673 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:20:45.433 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.28.20:5700) Recv POWEROFF cmd
2026-01-29 02:20:45.433 [INFO] ctrl_if_trx.py:117 (BTS@172.18.28.20:5700) Stopping transceiver...
2026-01-29 02:20:45.435 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:20:45.436 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:20:45.436 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:20:45.437 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 02:20:45.439 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 02:20:45.439 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.28.20:5700) Recv SETFORMAT cmd
2026-01-29 02:20:45.439 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.28.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:20:45.440 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.28.20:5700) Recv SETFORMAT cmd
2026-01-29 02:20:45.440 [INFO] ctrl_if_trx.py:201 (BTS@172.18.28.20:5700) TRXD header version 1 -> 1
2026-01-29 02:20:45.440 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.28.20:5700/1) Recv RXTUNE cmd
2026-01-29 02:20:45.440 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.28.20:5700/1) Recv TXTUNE cmd
2026-01-29 02:20:45.440 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.28.20:5700/1) Recv SETFORMAT cmd
2026-01-29 02:20:45.441 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.28.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:20:45.441 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:20:45.441 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.28.20:5700/1) Recv NOMTXPOWER cmd
2026-01-29 02:20:45.441 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.28.20:5700/1) Recv SETFORMAT cmd
2026-01-29 02:20:45.441 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.28.20:5700/1) TRXD header version 1 -> 1
2026-01-29 02:20:45.441 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.28.20:5700/2) Recv RXTUNE cmd
2026-01-29 02:20:45.441 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.28.20:5700/2) Recv TXTUNE cmd
2026-01-29 02:20:45.441 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.28.20:5700/2) Recv SETFORMAT cmd
2026-01-29 02:20:45.441 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.28.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:20:45.441 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:20:45.441 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.28.20:5700/2) Recv NOMTXPOWER cmd
2026-01-29 02:20:45.441 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.28.20:5700/2) Recv SETFORMAT cmd
2026-01-29 02:20:45.441 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.28.20:5700/2) TRXD header version 1 -> 1
2026-01-29 02:20:45.442 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.28.20:5700/3) Recv RXTUNE cmd
2026-01-29 02:20:45.442 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.28.20:5700/3) Recv TXTUNE cmd
2026-01-29 02:20:45.442 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.28.20:5700/3) Recv SETFORMAT cmd
2026-01-29 02:20:45.442 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.28.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:20:45.442 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:20:45.443 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.28.20:5700/3) Recv NOMTXPOWER cmd
2026-01-29 02:20:45.443 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.28.20:5700/3) Recv SETFORMAT cmd
2026-01-29 02:20:45.443 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.28.20:5700/3) TRXD header version 1 -> 1
2026-01-29 02:20:45.444 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.28.20:5700) Recv RXTUNE cmd
2026-01-29 02:20:45.444 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETTSC
2026-01-29 02:20:45.444 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETTSC
2026-01-29 02:20:45.444 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETTSC
2026-01-29 02:20:45.444 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.28.20:5700) Recv TXTUNE cmd
2026-01-29 02:20:45.444 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETRXGAIN
2026-01-29 02:20:45.444 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETRXGAIN
2026-01-29 02:20:45.444 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETRXGAIN
2026-01-29 02:20:45.444 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETTSC
2026-01-29 02:20:45.444 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:20:45.444 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:20:45.444 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.28.20:5700) Recv NOMTXPOWER cmd
2026-01-29 02:20:45.444 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:20:45.444 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:20:45.444 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:20:45.444 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.28.20:5700) Recv POWERON CMD
2026-01-29 02:20:45.444 [INFO] ctrl_if_trx.py:109 (BTS@172.18.28.20:5700) Starting transceiver...
2026-01-29 02:20:45.444 [INFO] transceiver.py:243 Starting clock generator
2026-01-29 02:20:45.444 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-01-29 02:20:45.444 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:20:45.444 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:20:45.444 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:20:45.445 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETRXGAIN
2026-01-29 02:20:45.445 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:20:45.445 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:20:45.445 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:20:45.445 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:20:45.445 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:20:45.445 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:20:45.445 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:20:45.445 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:20:45.445 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:20:45.445 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:20:45.445 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:20:45.445 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:20:45.445 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:20:45.445 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:20:45.446 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:20:45.446 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:20:45.446 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:20:45.446 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:20:45.446 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:20:45.446 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:20:45.446 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:20:45.446 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:20:45.446 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:20:45.446 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:20:45.446 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:20:45.446 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:20:45.446 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:20:45.446 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 02:20:45.446 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.28.20:5700) Recv POWEROFF cmd
2026-01-29 02:20:45.446 [INFO] ctrl_if_trx.py:117 (BTS@172.18.28.20:5700) Stopping transceiver...
2026-01-29 02:20:45.446 [INFO] transceiver.py:246 Stopping clock generator
2026-01-29 02:20:50.449 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.28.20:5700) Recv POWEROFF cmd
2026-01-29 02:20:50.472 [INFO] ctrl_if_trx.py:117 (BTS@172.18.28.20:5700) Stopping transceiver...
2026-01-29 02:20:50.473 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:20:50.473 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:20:50.473 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:20:50.473 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 02:20:50.475 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 02:20:50.476 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.28.20:5700) Recv SETFORMAT cmd
2026-01-29 02:20:50.476 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.28.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:20:50.477 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.28.20:5700) Recv SETFORMAT cmd
2026-01-29 02:20:50.477 [INFO] ctrl_if_trx.py:201 (BTS@172.18.28.20:5700) TRXD header version 1 -> 1
2026-01-29 02:20:50.479 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.28.20:5700/1) Recv RXTUNE cmd
2026-01-29 02:20:50.479 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.28.20:5700/1) Recv TXTUNE cmd
2026-01-29 02:20:50.479 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.28.20:5700/1) Recv SETFORMAT cmd
2026-01-29 02:20:50.479 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.28.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:20:50.479 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:20:50.480 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.28.20:5700/1) Recv NOMTXPOWER cmd
2026-01-29 02:20:50.480 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.28.20:5700/1) Recv SETFORMAT cmd
2026-01-29 02:20:50.480 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.28.20:5700/1) TRXD header version 1 -> 1
2026-01-29 02:20:50.481 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.28.20:5700/2) Recv RXTUNE cmd
2026-01-29 02:20:50.482 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.28.20:5700/2) Recv TXTUNE cmd
2026-01-29 02:20:50.482 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.28.20:5700/2) Recv SETFORMAT cmd
2026-01-29 02:20:50.482 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.28.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:20:50.482 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:20:50.483 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.28.20:5700/2) Recv NOMTXPOWER cmd
2026-01-29 02:20:50.483 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.28.20:5700/2) Recv SETFORMAT cmd
2026-01-29 02:20:50.483 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.28.20:5700/2) TRXD header version 1 -> 1
2026-01-29 02:20:50.484 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.28.20:5700/3) Recv RXTUNE cmd
2026-01-29 02:20:50.484 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.28.20:5700/3) Recv TXTUNE cmd
2026-01-29 02:20:50.484 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.28.20:5700/3) Recv SETFORMAT cmd
2026-01-29 02:20:50.484 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.28.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:20:50.485 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:20:50.485 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.28.20:5700/3) Recv NOMTXPOWER cmd
2026-01-29 02:20:50.485 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.28.20:5700/3) Recv SETFORMAT cmd
2026-01-29 02:20:50.485 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.28.20:5700/3) TRXD header version 1 -> 1
2026-01-29 02:20:50.488 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.28.20:5700) Recv RXTUNE cmd
2026-01-29 02:20:50.488 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETTSC
2026-01-29 02:20:50.488 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETTSC
2026-01-29 02:20:50.488 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETTSC
2026-01-29 02:20:50.488 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.28.20:5700) Recv TXTUNE cmd
2026-01-29 02:20:50.488 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETRXGAIN
2026-01-29 02:20:50.488 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETRXGAIN
2026-01-29 02:20:50.488 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETRXGAIN
2026-01-29 02:20:50.488 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETTSC
2026-01-29 02:20:50.488 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:20:50.488 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:20:50.488 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.28.20:5700) Recv NOMTXPOWER cmd
2026-01-29 02:20:50.488 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:20:50.488 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:20:50.488 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:20:50.488 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.28.20:5700) Recv POWERON CMD
2026-01-29 02:20:50.488 [INFO] ctrl_if_trx.py:109 (BTS@172.18.28.20:5700) Starting transceiver...
2026-01-29 02:20:50.488 [INFO] transceiver.py:243 Starting clock generator
2026-01-29 02:20:50.488 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-01-29 02:20:50.488 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:20:50.488 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:20:50.488 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:20:50.488 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETRXGAIN
2026-01-29 02:20:50.488 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:20:50.488 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:20:50.488 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:20:50.489 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:20:50.489 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:20:50.489 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:20:50.489 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:20:50.489 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:20:50.489 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:20:50.489 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:20:50.489 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:20:50.489 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:20:50.489 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:20:50.489 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:20:50.489 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:20:50.489 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:20:50.489 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:20:50.489 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:20:50.489 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:20:50.489 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:20:50.489 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:20:50.489 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:20:50.489 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:20:50.489 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:20:50.493 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-01-29 02:20:50.976 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-01-29 02:20:51.016 [DEBUG] fake_trx.py:278 (BTS@172.18.28.20:5700) Recv FAKE_TOA cmd
2026-01-29 02:20:51.019 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:20:51.020 [DEBUG] fake_trx.py:297 (BTS@172.18.28.20:5700) Recv FAKE_RSSI cmd
2026-01-29 02:20:51.022 [DEBUG] fake_trx.py:322 (BTS@172.18.28.20:5700) Recv FAKE_CI cmd
2026-01-29 02:20:51.024 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 02:20:51.024 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 02:20:51.025 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 02:20:51.025 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:20:51.025 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 02:20:51.025 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 02:20:51.026 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.28.22:6700) Recv POWERON CMD
2026-01-29 02:20:51.026 [INFO] ctrl_if_trx.py:109 (MS@172.18.28.22:6700) Starting transceiver...
2026-01-29 02:20:51.066 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 02:20:51.066 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 02:20:51.066 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:20:51.066 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:20:51.453 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-01-29 02:20:51.490 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 02:20:51.491 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:20:51.492 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:20:51.494 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:20:51.931 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-01-29 02:20:52.408 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-01-29 02:20:52.491 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 02:20:52.492 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:20:52.492 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:20:52.494 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:20:52.886 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-01-29 02:20:53.363 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-01-29 02:20:53.492 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 02:20:53.493 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:20:53.493 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:20:53.495 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:20:53.840 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-01-29 02:20:54.317 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-01-29 02:20:54.493 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 02:20:54.493 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:20:54.494 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:20:54.497 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:20:54.795 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-01-29 02:20:55.273 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-01-29 02:20:55.493 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 02:20:55.494 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:20:55.494 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:20:55.498 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:20:55.751 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-01-29 02:20:56.228 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-01-29 02:20:56.706 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-01-29 02:20:57.184 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-01-29 02:20:57.661 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-01-29 02:20:58.139 [DEBUG] clck_gen.py:113 IND CLOCK 1632
2026-01-29 02:20:58.616 [DEBUG] clck_gen.py:113 IND CLOCK 1734
2026-01-29 02:20:59.070 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 02:20:59.071 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 02:20:59.074 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 02:20:59.074 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:20:59.074 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:20:59.074 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:20:59.075 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 02:20:59.075 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:20:59.075 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:20:59.075 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:20:59.075 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.28.20:5700) Recv POWEROFF cmd
2026-01-29 02:20:59.075 [INFO] ctrl_if_trx.py:117 (BTS@172.18.28.20:5700) Stopping transceiver...
2026-01-29 02:20:59.075 [INFO] transceiver.py:246 Stopping clock generator
2026-01-29 02:20:59.075 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=1835 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:20:59.075 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=1835 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:20:59.075 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=1835 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:20:59.075 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=1835 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:20:59.075 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=1835 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:21:04.077 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.28.20:5700) Recv POWEROFF cmd
2026-01-29 02:21:04.078 [INFO] ctrl_if_trx.py:117 (BTS@172.18.28.20:5700) Stopping transceiver...
2026-01-29 02:21:04.079 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:21:04.081 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:21:04.083 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:21:04.085 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 02:21:04.099 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 02:21:04.100 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.28.20:5700) Recv SETFORMAT cmd
2026-01-29 02:21:04.100 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.28.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:21:04.100 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.28.20:5700) Recv SETFORMAT cmd
2026-01-29 02:21:04.100 [INFO] ctrl_if_trx.py:201 (BTS@172.18.28.20:5700) TRXD header version 1 -> 1
2026-01-29 02:21:04.103 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.28.20:5700/1) Recv RXTUNE cmd
2026-01-29 02:21:04.103 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.28.20:5700/1) Recv TXTUNE cmd
2026-01-29 02:21:04.104 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.28.20:5700/1) Recv SETFORMAT cmd
2026-01-29 02:21:04.104 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.28.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:21:04.104 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:21:04.104 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.28.20:5700/1) Recv NOMTXPOWER cmd
2026-01-29 02:21:04.105 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.28.20:5700/1) Recv SETFORMAT cmd
2026-01-29 02:21:04.105 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.28.20:5700/1) TRXD header version 1 -> 1
2026-01-29 02:21:04.106 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.28.20:5700/2) Recv RXTUNE cmd
2026-01-29 02:21:04.106 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.28.20:5700/2) Recv TXTUNE cmd
2026-01-29 02:21:04.106 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.28.20:5700/2) Recv SETFORMAT cmd
2026-01-29 02:21:04.106 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.28.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:21:04.106 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:21:04.106 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.28.20:5700/2) Recv NOMTXPOWER cmd
2026-01-29 02:21:04.106 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.28.20:5700/2) Recv SETFORMAT cmd
2026-01-29 02:21:04.106 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.28.20:5700/2) TRXD header version 1 -> 1
2026-01-29 02:21:04.108 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.28.20:5700/3) Recv RXTUNE cmd
2026-01-29 02:21:04.108 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.28.20:5700/3) Recv TXTUNE cmd
2026-01-29 02:21:04.108 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.28.20:5700/3) Recv SETFORMAT cmd
2026-01-29 02:21:04.109 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.28.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:21:04.109 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:21:04.109 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.28.20:5700/3) Recv NOMTXPOWER cmd
2026-01-29 02:21:04.109 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.28.20:5700/3) Recv SETFORMAT cmd
2026-01-29 02:21:04.109 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.28.20:5700/3) TRXD header version 1 -> 1
2026-01-29 02:21:04.111 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.28.20:5700) Recv RXTUNE cmd
2026-01-29 02:21:04.111 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETTSC
2026-01-29 02:21:04.111 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETTSC
2026-01-29 02:21:04.111 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETTSC
2026-01-29 02:21:04.111 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.28.20:5700) Recv TXTUNE cmd
2026-01-29 02:21:04.111 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETRXGAIN
2026-01-29 02:21:04.111 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETRXGAIN
2026-01-29 02:21:04.111 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETRXGAIN
2026-01-29 02:21:04.111 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETTSC
2026-01-29 02:21:04.111 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:21:04.111 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:21:04.111 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:21:04.111 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.28.20:5700) Recv NOMTXPOWER cmd
2026-01-29 02:21:04.111 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:21:04.111 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:21:04.111 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:21:04.111 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.28.20:5700) Recv POWERON CMD
2026-01-29 02:21:04.111 [INFO] ctrl_if_trx.py:109 (BTS@172.18.28.20:5700) Starting transceiver...
2026-01-29 02:21:04.111 [INFO] transceiver.py:243 Starting clock generator
2026-01-29 02:21:04.112 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-01-29 02:21:04.112 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:21:04.112 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:21:04.112 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:21:04.112 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETRXGAIN
2026-01-29 02:21:04.112 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:21:04.112 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:21:04.112 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:21:04.112 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:21:04.112 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:21:04.112 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:21:04.112 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:21:04.112 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:21:04.112 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:21:04.112 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:21:04.112 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:21:04.112 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:21:04.112 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:21:04.112 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:21:04.112 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:21:04.112 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:21:04.113 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:21:04.113 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:21:04.113 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:21:04.113 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:21:04.113 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:21:04.113 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:21:04.113 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:21:04.113 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:21:04.113 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:21:04.113 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:21:04.113 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 02:21:04.113 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.28.20:5700) Recv POWEROFF cmd
2026-01-29 02:21:04.113 [INFO] ctrl_if_trx.py:117 (BTS@172.18.28.20:5700) Stopping transceiver...
2026-01-29 02:21:04.113 [INFO] transceiver.py:246 Stopping clock generator
2026-01-29 02:21:09.116 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.28.20:5700) Recv POWEROFF cmd
2026-01-29 02:21:09.116 [INFO] ctrl_if_trx.py:117 (BTS@172.18.28.20:5700) Stopping transceiver...
2026-01-29 02:21:09.118 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:21:09.119 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:21:09.119 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:21:09.120 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 02:21:09.122 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 02:21:09.122 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.28.20:5700) Recv SETFORMAT cmd
2026-01-29 02:21:09.122 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.28.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:21:09.122 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.28.20:5700) Recv SETFORMAT cmd
2026-01-29 02:21:09.122 [INFO] ctrl_if_trx.py:201 (BTS@172.18.28.20:5700) TRXD header version 1 -> 1
2026-01-29 02:21:09.123 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.28.20:5700/1) Recv RXTUNE cmd
2026-01-29 02:21:09.123 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.28.20:5700/1) Recv TXTUNE cmd
2026-01-29 02:21:09.123 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.28.20:5700/1) Recv SETFORMAT cmd
2026-01-29 02:21:09.123 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.28.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:21:09.124 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:21:09.124 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.28.20:5700/1) Recv NOMTXPOWER cmd
2026-01-29 02:21:09.124 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.28.20:5700/1) Recv SETFORMAT cmd
2026-01-29 02:21:09.124 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.28.20:5700/1) TRXD header version 1 -> 1
2026-01-29 02:21:09.124 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.28.20:5700/2) Recv RXTUNE cmd
2026-01-29 02:21:09.124 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.28.20:5700/2) Recv TXTUNE cmd
2026-01-29 02:21:09.124 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.28.20:5700/2) Recv SETFORMAT cmd
2026-01-29 02:21:09.124 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.28.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:21:09.124 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:21:09.124 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.28.20:5700/2) Recv NOMTXPOWER cmd
2026-01-29 02:21:09.124 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.28.20:5700/2) Recv SETFORMAT cmd
2026-01-29 02:21:09.124 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.28.20:5700/2) TRXD header version 1 -> 1
2026-01-29 02:21:09.125 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.28.20:5700/3) Recv RXTUNE cmd
2026-01-29 02:21:09.125 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.28.20:5700/3) Recv TXTUNE cmd
2026-01-29 02:21:09.125 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.28.20:5700/3) Recv SETFORMAT cmd
2026-01-29 02:21:09.125 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.28.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:21:09.125 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:21:09.125 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.28.20:5700/3) Recv NOMTXPOWER cmd
2026-01-29 02:21:09.125 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.28.20:5700/3) Recv SETFORMAT cmd
2026-01-29 02:21:09.125 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.28.20:5700/3) TRXD header version 1 -> 1
2026-01-29 02:21:09.127 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.28.20:5700) Recv RXTUNE cmd
2026-01-29 02:21:09.127 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETTSC
2026-01-29 02:21:09.127 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETTSC
2026-01-29 02:21:09.127 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETTSC
2026-01-29 02:21:09.127 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.28.20:5700) Recv TXTUNE cmd
2026-01-29 02:21:09.127 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETRXGAIN
2026-01-29 02:21:09.127 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETRXGAIN
2026-01-29 02:21:09.127 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETRXGAIN
2026-01-29 02:21:09.127 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETTSC
2026-01-29 02:21:09.127 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:21:09.127 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:21:09.127 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:21:09.127 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.28.20:5700) Recv NOMTXPOWER cmd
2026-01-29 02:21:09.127 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:21:09.127 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:21:09.127 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:21:09.127 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.28.20:5700) Recv POWERON CMD
2026-01-29 02:21:09.127 [INFO] ctrl_if_trx.py:109 (BTS@172.18.28.20:5700) Starting transceiver...
2026-01-29 02:21:09.127 [INFO] transceiver.py:243 Starting clock generator
2026-01-29 02:21:09.127 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-01-29 02:21:09.127 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:21:09.127 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:21:09.127 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:21:09.127 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETRXGAIN
2026-01-29 02:21:09.127 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:21:09.127 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:21:09.128 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:21:09.128 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:21:09.128 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:21:09.128 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:21:09.128 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:21:09.128 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:21:09.128 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:21:09.128 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:21:09.128 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:21:09.128 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:21:09.128 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:21:09.128 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:21:09.128 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:21:09.128 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:21:09.128 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:21:09.128 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:21:09.128 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:21:09.128 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:21:09.128 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:21:09.128 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:21:09.128 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:21:09.132 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-01-29 02:21:09.616 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-01-29 02:21:09.648 [DEBUG] fake_trx.py:278 (BTS@172.18.28.20:5700) Recv FAKE_TOA cmd
2026-01-29 02:21:09.649 [DEBUG] fake_trx.py:297 (BTS@172.18.28.20:5700) Recv FAKE_RSSI cmd
2026-01-29 02:21:09.649 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:21:09.650 [DEBUG] fake_trx.py:322 (BTS@172.18.28.20:5700) Recv FAKE_CI cmd
2026-01-29 02:21:09.651 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 02:21:09.651 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 02:21:09.652 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 02:21:09.652 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:21:09.652 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 02:21:09.652 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 02:21:09.652 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.28.22:6700) Recv POWERON CMD
2026-01-29 02:21:09.652 [INFO] ctrl_if_trx.py:109 (MS@172.18.28.22:6700) Starting transceiver...
2026-01-29 02:21:09.659 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 02:21:09.659 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 02:21:09.659 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:21:09.660 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:21:10.093 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-01-29 02:21:10.129 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 02:21:10.130 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:21:10.131 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:21:10.133 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:21:10.571 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-01-29 02:21:11.048 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-01-29 02:21:11.130 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 02:21:11.131 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:21:11.132 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:21:11.134 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:21:11.526 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-01-29 02:21:12.004 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-01-29 02:21:12.131 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 02:21:12.132 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:21:12.133 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:21:12.136 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:21:12.481 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-01-29 02:21:12.959 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-01-29 02:21:13.132 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 02:21:13.133 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:21:13.134 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:21:13.137 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:21:13.436 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-01-29 02:21:13.913 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-01-29 02:21:14.133 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 02:21:14.133 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:21:14.135 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:21:14.138 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:21:14.390 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-01-29 02:21:14.868 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-01-29 02:21:15.345 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-01-29 02:21:15.823 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-01-29 02:21:16.300 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-01-29 02:21:16.778 [DEBUG] clck_gen.py:113 IND CLOCK 1632
2026-01-29 02:21:17.256 [DEBUG] clck_gen.py:113 IND CLOCK 1734
2026-01-29 02:21:17.665 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 02:21:17.666 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 02:21:17.673 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 02:21:17.673 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:21:17.673 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:21:17.673 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:21:17.674 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 02:21:17.674 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:21:17.674 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:21:17.674 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:21:17.674 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.28.20:5700) Recv POWEROFF cmd
2026-01-29 02:21:17.674 [INFO] ctrl_if_trx.py:117 (BTS@172.18.28.20:5700) Stopping transceiver...
2026-01-29 02:21:17.674 [INFO] transceiver.py:246 Stopping clock generator
2026-01-29 02:21:22.678 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.28.20:5700) Recv POWEROFF cmd
2026-01-29 02:21:22.678 [INFO] ctrl_if_trx.py:117 (BTS@172.18.28.20:5700) Stopping transceiver...
2026-01-29 02:21:22.678 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:21:22.678 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:21:22.678 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:21:22.678 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 02:21:22.688 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 02:21:22.690 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.28.20:5700) Recv SETFORMAT cmd
2026-01-29 02:21:22.690 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.28.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:21:22.691 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.28.20:5700) Recv SETFORMAT cmd
2026-01-29 02:21:22.691 [INFO] ctrl_if_trx.py:201 (BTS@172.18.28.20:5700) TRXD header version 1 -> 1
2026-01-29 02:21:22.695 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.28.20:5700/1) Recv RXTUNE cmd
2026-01-29 02:21:22.696 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.28.20:5700/1) Recv TXTUNE cmd
2026-01-29 02:21:22.696 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.28.20:5700/1) Recv SETFORMAT cmd
2026-01-29 02:21:22.696 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.28.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:21:22.697 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:21:22.697 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.28.20:5700/1) Recv NOMTXPOWER cmd
2026-01-29 02:21:22.697 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.28.20:5700/1) Recv SETFORMAT cmd
2026-01-29 02:21:22.697 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.28.20:5700/1) TRXD header version 1 -> 1
2026-01-29 02:21:22.699 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.28.20:5700/2) Recv RXTUNE cmd
2026-01-29 02:21:22.699 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.28.20:5700/2) Recv TXTUNE cmd
2026-01-29 02:21:22.699 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.28.20:5700/2) Recv SETFORMAT cmd
2026-01-29 02:21:22.700 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.28.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:21:22.700 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:21:22.700 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.28.20:5700/2) Recv NOMTXPOWER cmd
2026-01-29 02:21:22.700 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.28.20:5700/2) Recv SETFORMAT cmd
2026-01-29 02:21:22.700 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.28.20:5700/2) TRXD header version 1 -> 1
2026-01-29 02:21:22.702 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.28.20:5700/3) Recv RXTUNE cmd
2026-01-29 02:21:22.702 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.28.20:5700/3) Recv TXTUNE cmd
2026-01-29 02:21:22.702 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.28.20:5700/3) Recv SETFORMAT cmd
2026-01-29 02:21:22.702 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.28.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:21:22.702 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:21:22.702 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.28.20:5700/3) Recv NOMTXPOWER cmd
2026-01-29 02:21:22.702 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.28.20:5700/3) Recv SETFORMAT cmd
2026-01-29 02:21:22.702 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.28.20:5700/3) TRXD header version 1 -> 1
2026-01-29 02:21:22.705 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.28.20:5700) Recv RXTUNE cmd
2026-01-29 02:21:22.705 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETTSC
2026-01-29 02:21:22.705 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETTSC
2026-01-29 02:21:22.705 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETTSC
2026-01-29 02:21:22.705 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.28.20:5700) Recv TXTUNE cmd
2026-01-29 02:21:22.706 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETRXGAIN
2026-01-29 02:21:22.706 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETRXGAIN
2026-01-29 02:21:22.706 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETRXGAIN
2026-01-29 02:21:22.706 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETTSC
2026-01-29 02:21:22.706 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:21:22.706 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:21:22.706 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:21:22.706 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.28.20:5700) Recv NOMTXPOWER cmd
2026-01-29 02:21:22.706 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:21:22.706 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:21:22.706 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:21:22.706 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.28.20:5700) Recv POWERON CMD
2026-01-29 02:21:22.706 [INFO] ctrl_if_trx.py:109 (BTS@172.18.28.20:5700) Starting transceiver...
2026-01-29 02:21:22.706 [INFO] transceiver.py:243 Starting clock generator
2026-01-29 02:21:22.706 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-01-29 02:21:22.706 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:21:22.706 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:21:22.706 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:21:22.707 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETRXGAIN
2026-01-29 02:21:22.707 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:21:22.707 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:21:22.707 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:21:22.707 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:21:22.708 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:21:22.708 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:21:22.708 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:21:22.708 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:21:22.708 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:21:22.708 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:21:22.708 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:21:22.708 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:21:22.708 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:21:22.708 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:21:22.708 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:21:22.708 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:21:22.708 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:21:22.708 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:21:22.708 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:21:22.708 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:21:22.708 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:21:22.708 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:21:22.708 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:21:22.708 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:21:22.708 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 02:21:22.708 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:21:22.708 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.28.20:5700) Recv POWEROFF cmd
2026-01-29 02:21:22.708 [INFO] ctrl_if_trx.py:117 (BTS@172.18.28.20:5700) Stopping transceiver...
2026-01-29 02:21:22.708 [INFO] transceiver.py:246 Stopping clock generator
2026-01-29 02:21:22.709 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:21:27.712 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.28.20:5700) Recv POWEROFF cmd
2026-01-29 02:21:27.712 [INFO] ctrl_if_trx.py:117 (BTS@172.18.28.20:5700) Stopping transceiver...
2026-01-29 02:21:27.714 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:21:27.715 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:21:27.716 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:21:27.717 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 02:21:27.723 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 02:21:27.724 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.28.20:5700) Recv SETFORMAT cmd
2026-01-29 02:21:27.724 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.28.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:21:27.725 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.28.20:5700) Recv SETFORMAT cmd
2026-01-29 02:21:27.725 [INFO] ctrl_if_trx.py:201 (BTS@172.18.28.20:5700) TRXD header version 1 -> 1
2026-01-29 02:21:27.727 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.28.20:5700/1) Recv RXTUNE cmd
2026-01-29 02:21:27.728 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.28.20:5700/1) Recv TXTUNE cmd
2026-01-29 02:21:27.728 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.28.20:5700/1) Recv SETFORMAT cmd
2026-01-29 02:21:27.729 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.28.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:21:27.729 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:21:27.729 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.28.20:5700/1) Recv NOMTXPOWER cmd
2026-01-29 02:21:27.730 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.28.20:5700/1) Recv SETFORMAT cmd
2026-01-29 02:21:27.730 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.28.20:5700/1) TRXD header version 1 -> 1
2026-01-29 02:21:27.732 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.28.20:5700/2) Recv RXTUNE cmd
2026-01-29 02:21:27.732 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.28.20:5700/2) Recv TXTUNE cmd
2026-01-29 02:21:27.732 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.28.20:5700/2) Recv SETFORMAT cmd
2026-01-29 02:21:27.733 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.28.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:21:27.733 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:21:27.733 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.28.20:5700/2) Recv NOMTXPOWER cmd
2026-01-29 02:21:27.733 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.28.20:5700/2) Recv SETFORMAT cmd
2026-01-29 02:21:27.733 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.28.20:5700/2) TRXD header version 1 -> 1
2026-01-29 02:21:27.735 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.28.20:5700/3) Recv RXTUNE cmd
2026-01-29 02:21:27.735 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.28.20:5700/3) Recv TXTUNE cmd
2026-01-29 02:21:27.735 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.28.20:5700/3) Recv SETFORMAT cmd
2026-01-29 02:21:27.735 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.28.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:21:27.736 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:21:27.736 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.28.20:5700/3) Recv NOMTXPOWER cmd
2026-01-29 02:21:27.736 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.28.20:5700/3) Recv SETFORMAT cmd
2026-01-29 02:21:27.736 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.28.20:5700/3) TRXD header version 1 -> 1
2026-01-29 02:21:27.739 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.28.20:5700) Recv RXTUNE cmd
2026-01-29 02:21:27.739 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETTSC
2026-01-29 02:21:27.739 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETTSC
2026-01-29 02:21:27.740 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETTSC
2026-01-29 02:21:27.740 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.28.20:5700) Recv TXTUNE cmd
2026-01-29 02:21:27.740 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETRXGAIN
2026-01-29 02:21:27.740 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETRXGAIN
2026-01-29 02:21:27.740 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETRXGAIN
2026-01-29 02:21:27.740 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETTSC
2026-01-29 02:21:27.740 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:21:27.740 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:21:27.740 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:21:27.740 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.28.20:5700) Recv NOMTXPOWER cmd
2026-01-29 02:21:27.740 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:21:27.740 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:21:27.740 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:21:27.740 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.28.20:5700) Recv POWERON CMD
2026-01-29 02:21:27.740 [INFO] ctrl_if_trx.py:109 (BTS@172.18.28.20:5700) Starting transceiver...
2026-01-29 02:21:27.740 [INFO] transceiver.py:243 Starting clock generator
2026-01-29 02:21:27.740 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-01-29 02:21:27.741 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:21:27.741 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:21:27.741 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:21:27.741 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETRXGAIN
2026-01-29 02:21:27.741 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:21:27.741 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:21:27.741 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:21:27.741 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:21:27.741 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:21:27.741 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:21:27.741 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:21:27.741 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:21:27.741 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:21:27.741 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:21:27.741 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:21:27.741 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:21:27.741 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:21:27.742 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:21:27.742 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:21:27.742 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:21:27.742 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:21:27.742 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:21:27.742 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:21:27.742 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:21:27.742 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:21:27.742 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:21:27.742 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:21:27.745 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-01-29 02:21:28.229 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-01-29 02:21:28.268 [DEBUG] fake_trx.py:278 (BTS@172.18.28.20:5700) Recv FAKE_TOA cmd
2026-01-29 02:21:28.270 [DEBUG] fake_trx.py:297 (BTS@172.18.28.20:5700) Recv FAKE_RSSI cmd
2026-01-29 02:21:28.271 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:21:28.272 [DEBUG] fake_trx.py:322 (BTS@172.18.28.20:5700) Recv FAKE_CI cmd
2026-01-29 02:21:28.274 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 02:21:28.274 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 02:21:28.274 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 02:21:28.274 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:21:28.275 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 02:21:28.275 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 02:21:28.275 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.28.22:6700) Recv POWERON CMD
2026-01-29 02:21:28.275 [INFO] ctrl_if_trx.py:109 (MS@172.18.28.22:6700) Starting transceiver...
2026-01-29 02:21:28.319 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 02:21:28.319 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 02:21:28.319 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:21:28.319 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:21:28.706 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-01-29 02:21:28.744 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 02:21:28.744 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:21:28.745 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:21:28.748 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:21:29.184 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-01-29 02:21:29.661 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-01-29 02:21:29.744 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 02:21:29.745 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:21:29.745 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:21:29.749 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:21:30.138 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-01-29 02:21:30.616 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-01-29 02:21:30.745 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 02:21:30.746 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:21:30.746 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:21:30.750 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:21:31.093 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-01-29 02:21:31.597 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-01-29 02:21:31.746 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 02:21:31.746 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:21:31.746 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:21:31.750 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:21:32.074 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-01-29 02:21:32.552 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-01-29 02:21:32.747 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 02:21:32.747 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:21:32.747 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:21:32.751 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:21:33.030 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-01-29 02:21:33.508 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-01-29 02:21:33.985 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-01-29 02:21:34.463 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-01-29 02:21:34.940 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-01-29 02:21:35.418 [DEBUG] clck_gen.py:113 IND CLOCK 1632
2026-01-29 02:21:35.895 [DEBUG] clck_gen.py:113 IND CLOCK 1734
2026-01-29 02:21:36.323 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 02:21:36.323 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 02:21:36.326 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 02:21:36.326 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:21:36.326 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:21:36.326 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:21:36.327 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 02:21:36.327 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:21:36.327 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:21:36.327 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.28.20:5700) Recv POWEROFF cmd
2026-01-29 02:21:36.327 [INFO] ctrl_if_trx.py:117 (BTS@172.18.28.20:5700) Stopping transceiver...
2026-01-29 02:21:36.327 [INFO] transceiver.py:246 Stopping clock generator
2026-01-29 02:21:36.327 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:21:36.327 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=1829 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:21:36.327 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=1829 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:21:36.327 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=1829 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:21:36.327 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=1829 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:21:36.327 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=1829 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:21:36.327 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=1829 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:21:36.327 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=1829 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:21:36.327 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=1829 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:21:41.334 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.28.20:5700) Recv POWEROFF cmd
2026-01-29 02:21:41.336 [INFO] ctrl_if_trx.py:117 (BTS@172.18.28.20:5700) Stopping transceiver...
2026-01-29 02:21:41.336 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:21:41.336 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 02:21:41.336 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:21:41.336 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:21:41.337 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 02:21:41.337 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.28.20:5700) Recv SETFORMAT cmd
2026-01-29 02:21:41.337 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.28.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:21:41.337 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.28.20:5700) Recv SETFORMAT cmd
2026-01-29 02:21:41.337 [INFO] ctrl_if_trx.py:201 (BTS@172.18.28.20:5700) TRXD header version 1 -> 1
2026-01-29 02:21:41.338 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.28.20:5700/1) Recv RXTUNE cmd
2026-01-29 02:21:41.338 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.28.20:5700/1) Recv TXTUNE cmd
2026-01-29 02:21:41.338 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.28.20:5700/1) Recv SETFORMAT cmd
2026-01-29 02:21:41.338 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.28.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:21:41.338 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:21:41.338 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.28.20:5700/1) Recv NOMTXPOWER cmd
2026-01-29 02:21:41.338 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.28.20:5700/1) Recv SETFORMAT cmd
2026-01-29 02:21:41.338 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.28.20:5700/1) TRXD header version 1 -> 1
2026-01-29 02:21:41.339 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.28.20:5700/2) Recv RXTUNE cmd
2026-01-29 02:21:41.339 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.28.20:5700/2) Recv TXTUNE cmd
2026-01-29 02:21:41.339 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.28.20:5700/2) Recv SETFORMAT cmd
2026-01-29 02:21:41.339 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.28.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:21:41.339 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:21:41.339 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.28.20:5700/2) Recv NOMTXPOWER cmd
2026-01-29 02:21:41.339 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.28.20:5700/2) Recv SETFORMAT cmd
2026-01-29 02:21:41.339 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.28.20:5700/2) TRXD header version 1 -> 1
2026-01-29 02:21:41.340 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.28.20:5700/3) Recv RXTUNE cmd
2026-01-29 02:21:41.340 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.28.20:5700/3) Recv TXTUNE cmd
2026-01-29 02:21:41.340 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.28.20:5700/3) Recv SETFORMAT cmd
2026-01-29 02:21:41.340 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.28.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:21:41.340 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:21:41.340 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.28.20:5700/3) Recv NOMTXPOWER cmd
2026-01-29 02:21:41.340 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.28.20:5700/3) Recv SETFORMAT cmd
2026-01-29 02:21:41.340 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.28.20:5700/3) TRXD header version 1 -> 1
2026-01-29 02:21:41.341 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.28.20:5700) Recv RXTUNE cmd
2026-01-29 02:21:41.341 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETTSC
2026-01-29 02:21:41.341 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETTSC
2026-01-29 02:21:41.341 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETTSC
2026-01-29 02:21:41.341 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.28.20:5700) Recv TXTUNE cmd
2026-01-29 02:21:41.341 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETRXGAIN
2026-01-29 02:21:41.341 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETRXGAIN
2026-01-29 02:21:41.342 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETRXGAIN
2026-01-29 02:21:41.342 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETTSC
2026-01-29 02:21:41.342 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:21:41.342 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:21:41.342 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:21:41.342 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.28.20:5700) Recv NOMTXPOWER cmd
2026-01-29 02:21:41.342 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:21:41.342 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:21:41.342 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:21:41.342 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.28.20:5700) Recv POWERON CMD
2026-01-29 02:21:41.342 [INFO] ctrl_if_trx.py:109 (BTS@172.18.28.20:5700) Starting transceiver...
2026-01-29 02:21:41.342 [INFO] transceiver.py:243 Starting clock generator
2026-01-29 02:21:41.342 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-01-29 02:21:41.342 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:21:41.342 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:21:41.342 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:21:41.342 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETRXGAIN
2026-01-29 02:21:41.342 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:21:41.342 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:21:41.342 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:21:41.342 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:21:41.342 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:21:41.342 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:21:41.342 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:21:41.342 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:21:41.342 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:21:41.342 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:21:41.342 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:21:41.342 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:21:41.342 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:21:41.342 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:21:41.343 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:21:41.343 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:21:41.343 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:21:41.343 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:21:41.343 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:21:41.343 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:21:41.343 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:21:41.343 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:21:41.343 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:21:41.343 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:21:41.343 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:21:41.343 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:21:41.343 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 02:21:41.343 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.28.20:5700) Recv POWEROFF cmd
2026-01-29 02:21:41.343 [INFO] ctrl_if_trx.py:117 (BTS@172.18.28.20:5700) Stopping transceiver...
2026-01-29 02:21:41.343 [INFO] transceiver.py:246 Stopping clock generator
2026-01-29 02:21:46.346 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.28.20:5700) Recv POWEROFF cmd
2026-01-29 02:21:46.369 [INFO] ctrl_if_trx.py:117 (BTS@172.18.28.20:5700) Stopping transceiver...
2026-01-29 02:21:46.370 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:21:46.370 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:21:46.370 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:21:46.370 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 02:21:46.372 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 02:21:46.373 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.28.20:5700) Recv SETFORMAT cmd
2026-01-29 02:21:46.373 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.28.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:21:46.374 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.28.20:5700) Recv SETFORMAT cmd
2026-01-29 02:21:46.374 [INFO] ctrl_if_trx.py:201 (BTS@172.18.28.20:5700) TRXD header version 1 -> 1
2026-01-29 02:21:46.377 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.28.20:5700/1) Recv RXTUNE cmd
2026-01-29 02:21:46.377 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.28.20:5700/1) Recv TXTUNE cmd
2026-01-29 02:21:46.378 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.28.20:5700/1) Recv SETFORMAT cmd
2026-01-29 02:21:46.378 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.28.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:21:46.378 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:21:46.378 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.28.20:5700/1) Recv NOMTXPOWER cmd
2026-01-29 02:21:46.379 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.28.20:5700/1) Recv SETFORMAT cmd
2026-01-29 02:21:46.379 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.28.20:5700/1) TRXD header version 1 -> 1
2026-01-29 02:21:46.380 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.28.20:5700/2) Recv RXTUNE cmd
2026-01-29 02:21:46.380 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.28.20:5700/2) Recv TXTUNE cmd
2026-01-29 02:21:46.380 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.28.20:5700/2) Recv SETFORMAT cmd
2026-01-29 02:21:46.380 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.28.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:21:46.381 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:21:46.381 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.28.20:5700/2) Recv NOMTXPOWER cmd
2026-01-29 02:21:46.381 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.28.20:5700/2) Recv SETFORMAT cmd
2026-01-29 02:21:46.381 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.28.20:5700/2) TRXD header version 1 -> 1
2026-01-29 02:21:46.382 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.28.20:5700/3) Recv RXTUNE cmd
2026-01-29 02:21:46.382 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.28.20:5700/3) Recv TXTUNE cmd
2026-01-29 02:21:46.382 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.28.20:5700/3) Recv SETFORMAT cmd
2026-01-29 02:21:46.382 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.28.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:21:46.382 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:21:46.382 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.28.20:5700/3) Recv NOMTXPOWER cmd
2026-01-29 02:21:46.382 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.28.20:5700/3) Recv SETFORMAT cmd
2026-01-29 02:21:46.382 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.28.20:5700/3) TRXD header version 1 -> 1
2026-01-29 02:21:46.385 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.28.20:5700) Recv RXTUNE cmd
2026-01-29 02:21:46.385 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETTSC
2026-01-29 02:21:46.385 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETTSC
2026-01-29 02:21:46.385 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETTSC
2026-01-29 02:21:46.385 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.28.20:5700) Recv TXTUNE cmd
2026-01-29 02:21:46.385 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETRXGAIN
2026-01-29 02:21:46.385 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETRXGAIN
2026-01-29 02:21:46.385 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETRXGAIN
2026-01-29 02:21:46.385 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETTSC
2026-01-29 02:21:46.385 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:21:46.385 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:21:46.385 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:21:46.385 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.28.20:5700) Recv NOMTXPOWER cmd
2026-01-29 02:21:46.385 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:21:46.385 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:21:46.385 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:21:46.385 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.28.20:5700) Recv POWERON CMD
2026-01-29 02:21:46.385 [INFO] ctrl_if_trx.py:109 (BTS@172.18.28.20:5700) Starting transceiver...
2026-01-29 02:21:46.385 [INFO] transceiver.py:243 Starting clock generator
2026-01-29 02:21:46.385 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-01-29 02:21:46.385 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:21:46.385 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:21:46.385 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:21:46.385 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETRXGAIN
2026-01-29 02:21:46.385 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:21:46.385 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:21:46.385 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:21:46.385 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:21:46.385 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:21:46.385 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:21:46.385 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:21:46.385 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:21:46.385 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:21:46.386 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:21:46.386 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:21:46.386 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:21:46.386 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:21:46.386 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:21:46.386 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:21:46.386 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:21:46.386 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:21:46.386 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:21:46.386 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:21:46.386 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:21:46.386 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:21:46.386 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:21:46.386 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:21:46.390 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-01-29 02:21:46.874 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-01-29 02:21:46.908 [DEBUG] fake_trx.py:278 (BTS@172.18.28.20:5700) Recv FAKE_TOA cmd
2026-01-29 02:21:46.911 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:21:46.911 [DEBUG] fake_trx.py:297 (BTS@172.18.28.20:5700) Recv FAKE_RSSI cmd
2026-01-29 02:21:46.913 [DEBUG] fake_trx.py:322 (BTS@172.18.28.20:5700) Recv FAKE_CI cmd
2026-01-29 02:21:46.917 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 02:21:46.917 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 02:21:46.917 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 02:21:46.918 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:21:46.918 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 02:21:46.919 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 02:21:46.919 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.28.22:6700) Recv POWERON CMD
2026-01-29 02:21:46.920 [INFO] ctrl_if_trx.py:109 (MS@172.18.28.22:6700) Starting transceiver...
2026-01-29 02:21:46.964 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 02:21:46.964 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 02:21:46.964 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:21:46.965 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:21:47.351 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-01-29 02:21:47.387 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 02:21:47.388 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:21:47.388 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:21:47.391 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:21:47.829 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-01-29 02:21:48.307 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-01-29 02:21:48.388 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 02:21:48.389 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:21:48.389 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:21:48.393 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:21:48.784 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-01-29 02:21:49.262 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-01-29 02:21:49.389 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 02:21:49.390 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:21:49.390 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:21:49.394 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:21:49.740 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-01-29 02:21:50.218 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-01-29 02:21:50.391 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:21:50.391 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:21:50.391 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 02:21:50.395 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:21:50.695 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-01-29 02:21:51.173 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-01-29 02:21:51.392 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 02:21:51.393 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:21:51.393 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:21:51.395 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:21:51.651 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-01-29 02:21:52.129 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-01-29 02:21:52.606 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-01-29 02:21:53.083 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-01-29 02:21:53.561 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-01-29 02:21:54.039 [DEBUG] clck_gen.py:113 IND CLOCK 1632
2026-01-29 02:21:54.517 [DEBUG] clck_gen.py:113 IND CLOCK 1734
2026-01-29 02:21:54.968 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 02:21:54.968 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 02:21:54.971 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 02:21:54.972 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:21:54.972 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:21:54.972 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:21:54.973 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 02:21:54.973 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:21:54.973 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:21:54.973 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:21:54.973 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.28.20:5700) Recv POWEROFF cmd
2026-01-29 02:21:54.973 [INFO] ctrl_if_trx.py:117 (BTS@172.18.28.20:5700) Stopping transceiver...
2026-01-29 02:21:54.973 [INFO] transceiver.py:246 Stopping clock generator
2026-01-29 02:21:59.975 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.28.20:5700) Recv POWEROFF cmd
2026-01-29 02:21:59.975 [INFO] ctrl_if_trx.py:117 (BTS@172.18.28.20:5700) Stopping transceiver...
2026-01-29 02:21:59.977 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:21:59.978 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:21:59.979 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:21:59.980 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 02:21:59.988 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 02:21:59.989 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.28.20:5700) Recv SETFORMAT cmd
2026-01-29 02:21:59.989 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.28.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:21:59.990 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.28.20:5700) Recv SETFORMAT cmd
2026-01-29 02:21:59.990 [INFO] ctrl_if_trx.py:201 (BTS@172.18.28.20:5700) TRXD header version 1 -> 1
2026-01-29 02:21:59.993 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.28.20:5700/1) Recv RXTUNE cmd
2026-01-29 02:21:59.994 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.28.20:5700/1) Recv TXTUNE cmd
2026-01-29 02:21:59.994 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.28.20:5700/1) Recv SETFORMAT cmd
2026-01-29 02:21:59.994 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.28.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:21:59.995 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:21:59.995 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.28.20:5700/1) Recv NOMTXPOWER cmd
2026-01-29 02:21:59.996 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.28.20:5700/1) Recv SETFORMAT cmd
2026-01-29 02:21:59.996 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.28.20:5700/1) TRXD header version 1 -> 1
2026-01-29 02:21:59.997 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.28.20:5700/2) Recv RXTUNE cmd
2026-01-29 02:21:59.997 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.28.20:5700/2) Recv TXTUNE cmd
2026-01-29 02:21:59.997 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.28.20:5700/2) Recv SETFORMAT cmd
2026-01-29 02:21:59.997 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.28.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:21:59.997 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:21:59.998 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.28.20:5700/2) Recv NOMTXPOWER cmd
2026-01-29 02:21:59.998 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.28.20:5700/2) Recv SETFORMAT cmd
2026-01-29 02:21:59.998 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.28.20:5700/2) TRXD header version 1 -> 1
2026-01-29 02:22:00.000 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.28.20:5700/3) Recv RXTUNE cmd
2026-01-29 02:22:00.000 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.28.20:5700/3) Recv TXTUNE cmd
2026-01-29 02:22:00.000 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.28.20:5700/3) Recv SETFORMAT cmd
2026-01-29 02:22:00.000 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.28.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:22:00.000 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:22:00.000 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.28.20:5700/3) Recv NOMTXPOWER cmd
2026-01-29 02:22:00.001 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.28.20:5700/3) Recv SETFORMAT cmd
2026-01-29 02:22:00.001 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.28.20:5700/3) TRXD header version 1 -> 1
2026-01-29 02:22:00.004 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.28.20:5700) Recv RXTUNE cmd
2026-01-29 02:22:00.004 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETTSC
2026-01-29 02:22:00.004 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETTSC
2026-01-29 02:22:00.004 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETTSC
2026-01-29 02:22:00.004 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.28.20:5700) Recv TXTUNE cmd
2026-01-29 02:22:00.004 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETRXGAIN
2026-01-29 02:22:00.004 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETRXGAIN
2026-01-29 02:22:00.004 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETRXGAIN
2026-01-29 02:22:00.004 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETTSC
2026-01-29 02:22:00.004 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:22:00.004 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:22:00.004 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:22:00.004 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.28.20:5700) Recv NOMTXPOWER cmd
2026-01-29 02:22:00.004 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:22:00.004 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:22:00.004 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:22:00.004 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.28.20:5700) Recv POWERON CMD
2026-01-29 02:22:00.004 [INFO] ctrl_if_trx.py:109 (BTS@172.18.28.20:5700) Starting transceiver...
2026-01-29 02:22:00.004 [INFO] transceiver.py:243 Starting clock generator
2026-01-29 02:22:00.004 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-01-29 02:22:00.004 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:22:00.005 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:22:00.005 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:22:00.005 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETRXGAIN
2026-01-29 02:22:00.005 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:22:00.005 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:22:00.005 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:22:00.005 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:22:00.005 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:22:00.005 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:22:00.005 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:22:00.005 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:22:00.005 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:22:00.005 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:22:00.005 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:22:00.005 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:22:00.005 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:22:00.005 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:22:00.005 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:22:00.005 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:22:00.006 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:22:00.006 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:22:00.006 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:22:00.006 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:22:00.006 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:22:00.006 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:22:00.006 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:22:00.006 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:22:00.006 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:22:00.006 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:22:00.007 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 02:22:00.007 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.28.20:5700) Recv POWEROFF cmd
2026-01-29 02:22:00.007 [INFO] ctrl_if_trx.py:117 (BTS@172.18.28.20:5700) Stopping transceiver...
2026-01-29 02:22:00.007 [INFO] transceiver.py:246 Stopping clock generator
2026-01-29 02:22:05.010 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.28.20:5700) Recv POWEROFF cmd
2026-01-29 02:22:05.010 [INFO] ctrl_if_trx.py:117 (BTS@172.18.28.20:5700) Stopping transceiver...
2026-01-29 02:22:05.012 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:22:05.013 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:22:05.013 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:22:05.014 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 02:22:05.016 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 02:22:05.016 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.28.20:5700) Recv SETFORMAT cmd
2026-01-29 02:22:05.016 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.28.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:22:05.016 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.28.20:5700) Recv SETFORMAT cmd
2026-01-29 02:22:05.017 [INFO] ctrl_if_trx.py:201 (BTS@172.18.28.20:5700) TRXD header version 1 -> 1
2026-01-29 02:22:05.017 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.28.20:5700/1) Recv RXTUNE cmd
2026-01-29 02:22:05.017 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.28.20:5700/1) Recv TXTUNE cmd
2026-01-29 02:22:05.017 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.28.20:5700/1) Recv SETFORMAT cmd
2026-01-29 02:22:05.017 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.28.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:22:05.018 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:22:05.018 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.28.20:5700/1) Recv NOMTXPOWER cmd
2026-01-29 02:22:05.018 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.28.20:5700/1) Recv SETFORMAT cmd
2026-01-29 02:22:05.018 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.28.20:5700/1) TRXD header version 1 -> 1
2026-01-29 02:22:05.018 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.28.20:5700/2) Recv RXTUNE cmd
2026-01-29 02:22:05.018 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.28.20:5700/2) Recv TXTUNE cmd
2026-01-29 02:22:05.018 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.28.20:5700/2) Recv SETFORMAT cmd
2026-01-29 02:22:05.018 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.28.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:22:05.018 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:22:05.018 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.28.20:5700/2) Recv NOMTXPOWER cmd
2026-01-29 02:22:05.018 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.28.20:5700/2) Recv SETFORMAT cmd
2026-01-29 02:22:05.018 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.28.20:5700/2) TRXD header version 1 -> 1
2026-01-29 02:22:05.019 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.28.20:5700/3) Recv RXTUNE cmd
2026-01-29 02:22:05.019 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.28.20:5700/3) Recv TXTUNE cmd
2026-01-29 02:22:05.019 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.28.20:5700/3) Recv SETFORMAT cmd
2026-01-29 02:22:05.019 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.28.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:22:05.019 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:22:05.019 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.28.20:5700/3) Recv NOMTXPOWER cmd
2026-01-29 02:22:05.019 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.28.20:5700/3) Recv SETFORMAT cmd
2026-01-29 02:22:05.019 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.28.20:5700/3) TRXD header version 1 -> 1
2026-01-29 02:22:05.021 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.28.20:5700) Recv RXTUNE cmd
2026-01-29 02:22:05.021 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETTSC
2026-01-29 02:22:05.021 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETTSC
2026-01-29 02:22:05.021 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETTSC
2026-01-29 02:22:05.021 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.28.20:5700) Recv TXTUNE cmd
2026-01-29 02:22:05.021 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETRXGAIN
2026-01-29 02:22:05.021 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETRXGAIN
2026-01-29 02:22:05.021 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETRXGAIN
2026-01-29 02:22:05.021 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETTSC
2026-01-29 02:22:05.021 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:22:05.021 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:22:05.021 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.28.20:5700) Recv NOMTXPOWER cmd
2026-01-29 02:22:05.021 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:22:05.021 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:22:05.021 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:22:05.021 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.28.20:5700) Recv POWERON CMD
2026-01-29 02:22:05.021 [INFO] ctrl_if_trx.py:109 (BTS@172.18.28.20:5700) Starting transceiver...
2026-01-29 02:22:05.021 [INFO] transceiver.py:243 Starting clock generator
2026-01-29 02:22:05.021 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-01-29 02:22:05.021 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:22:05.021 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:22:05.021 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:22:05.021 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETRXGAIN
2026-01-29 02:22:05.021 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:22:05.021 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:22:05.022 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:22:05.022 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:22:05.022 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:22:05.022 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:22:05.022 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:22:05.022 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:22:05.022 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:22:05.022 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:22:05.022 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:22:05.022 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:22:05.022 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:22:05.022 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:22:05.022 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:22:05.022 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:22:05.022 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:22:05.022 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:22:05.022 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:22:05.022 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:22:05.022 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:22:05.022 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:22:05.022 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:22:05.022 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:22:05.026 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-01-29 02:22:05.509 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-01-29 02:22:05.547 [DEBUG] fake_trx.py:278 (BTS@172.18.28.20:5700) Recv FAKE_TOA cmd
2026-01-29 02:22:05.549 [DEBUG] fake_trx.py:297 (BTS@172.18.28.20:5700) Recv FAKE_RSSI cmd
2026-01-29 02:22:05.551 [DEBUG] fake_trx.py:322 (BTS@172.18.28.20:5700) Recv FAKE_CI cmd
2026-01-29 02:22:05.552 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:22:05.554 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 02:22:05.554 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 02:22:05.554 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 02:22:05.554 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:22:05.554 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 02:22:05.555 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 02:22:05.555 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.28.22:6700) Recv POWERON CMD
2026-01-29 02:22:05.555 [INFO] ctrl_if_trx.py:109 (MS@172.18.28.22:6700) Starting transceiver...
2026-01-29 02:22:05.599 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 02:22:05.600 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 02:22:05.600 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:22:05.600 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:22:05.987 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-01-29 02:22:06.024 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 02:22:06.024 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:22:06.025 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:22:06.026 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:22:06.465 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-01-29 02:22:06.943 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-01-29 02:22:07.025 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 02:22:07.025 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:22:07.025 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:22:07.027 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:22:07.420 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-01-29 02:22:07.898 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-01-29 02:22:08.026 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:22:08.026 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:22:08.026 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 02:22:08.027 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:22:08.375 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-01-29 02:22:08.852 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-01-29 02:22:09.027 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 02:22:09.027 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:22:09.028 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:22:09.028 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:22:09.329 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-01-29 02:22:09.806 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-01-29 02:22:10.028 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 02:22:10.028 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:22:10.029 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:22:10.029 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:22:10.284 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-01-29 02:22:10.762 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-01-29 02:22:11.240 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-01-29 02:22:11.717 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-01-29 02:22:12.195 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-01-29 02:22:12.673 [DEBUG] clck_gen.py:113 IND CLOCK 1632
2026-01-29 02:22:13.151 [DEBUG] clck_gen.py:113 IND CLOCK 1734
2026-01-29 02:22:13.628 [DEBUG] clck_gen.py:113 IND CLOCK 1836
2026-01-29 02:22:14.106 [DEBUG] clck_gen.py:113 IND CLOCK 1938
2026-01-29 02:22:14.584 [DEBUG] clck_gen.py:113 IND CLOCK 2040
2026-01-29 02:22:15.062 [DEBUG] clck_gen.py:113 IND CLOCK 2142
2026-01-29 02:22:15.539 [DEBUG] clck_gen.py:113 IND CLOCK 2244
2026-01-29 02:22:16.017 [DEBUG] clck_gen.py:113 IND CLOCK 2346
2026-01-29 02:22:16.495 [DEBUG] clck_gen.py:113 IND CLOCK 2448
2026-01-29 02:22:16.972 [DEBUG] clck_gen.py:113 IND CLOCK 2550
2026-01-29 02:22:17.450 [DEBUG] clck_gen.py:113 IND CLOCK 2652
2026-01-29 02:22:17.927 [DEBUG] clck_gen.py:113 IND CLOCK 2754
2026-01-29 02:22:18.405 [DEBUG] clck_gen.py:113 IND CLOCK 2856
2026-01-29 02:22:18.882 [DEBUG] clck_gen.py:113 IND CLOCK 2958
2026-01-29 02:22:19.359 [DEBUG] clck_gen.py:113 IND CLOCK 3060
2026-01-29 02:22:19.605 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 02:22:19.605 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 02:22:19.611 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 02:22:19.612 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:22:19.612 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:22:19.612 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:22:19.613 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 02:22:19.613 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:22:19.613 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:22:19.613 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.28.20:5700) Recv POWEROFF cmd
2026-01-29 02:22:19.613 [INFO] ctrl_if_trx.py:117 (BTS@172.18.28.20:5700) Stopping transceiver...
2026-01-29 02:22:19.613 [INFO] transceiver.py:246 Stopping clock generator
2026-01-29 02:22:19.613 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:22:19.613 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=3116 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:22:19.613 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=3116 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:22:19.613 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=3116 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:22:19.613 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=3116 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:22:19.613 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=3116 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:22:19.613 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=3116 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:22:19.613 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=3116 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:22:19.613 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=3116 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:22:24.615 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.28.20:5700) Recv POWEROFF cmd
2026-01-29 02:22:24.615 [INFO] ctrl_if_trx.py:117 (BTS@172.18.28.20:5700) Stopping transceiver...
2026-01-29 02:22:24.617 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:22:24.618 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:22:24.618 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:22:24.619 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 02:22:24.621 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 02:22:24.622 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.28.20:5700) Recv SETFORMAT cmd
2026-01-29 02:22:24.622 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.28.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:22:24.623 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.28.20:5700) Recv SETFORMAT cmd
2026-01-29 02:22:24.623 [INFO] ctrl_if_trx.py:201 (BTS@172.18.28.20:5700) TRXD header version 1 -> 1
2026-01-29 02:22:24.625 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.28.20:5700/1) Recv RXTUNE cmd
2026-01-29 02:22:24.625 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.28.20:5700/1) Recv TXTUNE cmd
2026-01-29 02:22:24.626 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.28.20:5700/1) Recv SETFORMAT cmd
2026-01-29 02:22:24.626 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.28.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:22:24.626 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:22:24.626 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.28.20:5700/1) Recv NOMTXPOWER cmd
2026-01-29 02:22:24.626 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.28.20:5700/1) Recv SETFORMAT cmd
2026-01-29 02:22:24.626 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.28.20:5700/1) TRXD header version 1 -> 1
2026-01-29 02:22:24.628 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.28.20:5700/2) Recv RXTUNE cmd
2026-01-29 02:22:24.628 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.28.20:5700/2) Recv TXTUNE cmd
2026-01-29 02:22:24.629 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.28.20:5700/2) Recv SETFORMAT cmd
2026-01-29 02:22:24.629 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.28.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:22:24.629 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:22:24.629 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.28.20:5700/2) Recv NOMTXPOWER cmd
2026-01-29 02:22:24.629 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.28.20:5700/2) Recv SETFORMAT cmd
2026-01-29 02:22:24.629 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.28.20:5700/2) TRXD header version 1 -> 1
2026-01-29 02:22:24.631 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.28.20:5700/3) Recv RXTUNE cmd
2026-01-29 02:22:24.631 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.28.20:5700/3) Recv TXTUNE cmd
2026-01-29 02:22:24.631 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.28.20:5700/3) Recv SETFORMAT cmd
2026-01-29 02:22:24.631 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.28.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:22:24.631 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:22:24.631 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.28.20:5700/3) Recv NOMTXPOWER cmd
2026-01-29 02:22:24.631 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.28.20:5700/3) Recv SETFORMAT cmd
2026-01-29 02:22:24.631 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.28.20:5700/3) TRXD header version 1 -> 1
2026-01-29 02:22:24.634 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.28.20:5700) Recv RXTUNE cmd
2026-01-29 02:22:24.635 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETTSC
2026-01-29 02:22:24.635 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETTSC
2026-01-29 02:22:24.635 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETTSC
2026-01-29 02:22:24.635 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.28.20:5700) Recv TXTUNE cmd
2026-01-29 02:22:24.635 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETRXGAIN
2026-01-29 02:22:24.635 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETRXGAIN
2026-01-29 02:22:24.635 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETRXGAIN
2026-01-29 02:22:24.635 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETTSC
2026-01-29 02:22:24.635 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:22:24.635 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:22:24.635 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.28.20:5700) Recv NOMTXPOWER cmd
2026-01-29 02:22:24.635 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:22:24.635 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:22:24.635 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:22:24.635 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.28.20:5700) Recv POWERON CMD
2026-01-29 02:22:24.635 [INFO] ctrl_if_trx.py:109 (BTS@172.18.28.20:5700) Starting transceiver...
2026-01-29 02:22:24.635 [INFO] transceiver.py:243 Starting clock generator
2026-01-29 02:22:24.635 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-01-29 02:22:24.636 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:22:24.636 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:22:24.636 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:22:24.636 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETRXGAIN
2026-01-29 02:22:24.636 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:22:24.636 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:22:24.636 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:22:24.636 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:22:24.636 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:22:24.636 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:22:24.636 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:22:24.636 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:22:24.637 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:22:24.637 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:22:24.637 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:22:24.637 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:22:24.637 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:22:24.637 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:22:24.637 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:22:24.637 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:22:24.637 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:22:24.637 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:22:24.637 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:22:24.637 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:22:24.637 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:22:24.637 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:22:24.637 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:22:24.637 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:22:24.638 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:22:24.638 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:22:24.638 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 02:22:24.638 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:22:24.638 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.28.20:5700) Recv POWEROFF cmd
2026-01-29 02:22:24.638 [INFO] ctrl_if_trx.py:117 (BTS@172.18.28.20:5700) Stopping transceiver...
2026-01-29 02:22:24.638 [INFO] transceiver.py:246 Stopping clock generator
2026-01-29 02:22:29.641 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.28.20:5700) Recv POWEROFF cmd
2026-01-29 02:22:29.641 [INFO] ctrl_if_trx.py:117 (BTS@172.18.28.20:5700) Stopping transceiver...
2026-01-29 02:22:29.645 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:22:29.645 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:22:29.645 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 02:22:29.645 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:22:29.659 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 02:22:29.661 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.28.20:5700) Recv SETFORMAT cmd
2026-01-29 02:22:29.661 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.28.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:22:29.661 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.28.20:5700) Recv SETFORMAT cmd
2026-01-29 02:22:29.662 [INFO] ctrl_if_trx.py:201 (BTS@172.18.28.20:5700) TRXD header version 1 -> 1
2026-01-29 02:22:29.665 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.28.20:5700/1) Recv RXTUNE cmd
2026-01-29 02:22:29.666 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.28.20:5700/1) Recv TXTUNE cmd
2026-01-29 02:22:29.666 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.28.20:5700/1) Recv SETFORMAT cmd
2026-01-29 02:22:29.666 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.28.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:22:29.666 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:22:29.666 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.28.20:5700/1) Recv NOMTXPOWER cmd
2026-01-29 02:22:29.666 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.28.20:5700/1) Recv SETFORMAT cmd
2026-01-29 02:22:29.666 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.28.20:5700/1) TRXD header version 1 -> 1
2026-01-29 02:22:29.669 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.28.20:5700/2) Recv RXTUNE cmd
2026-01-29 02:22:29.669 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.28.20:5700/2) Recv TXTUNE cmd
2026-01-29 02:22:29.669 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.28.20:5700/2) Recv SETFORMAT cmd
2026-01-29 02:22:29.669 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.28.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:22:29.669 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:22:29.669 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.28.20:5700/2) Recv NOMTXPOWER cmd
2026-01-29 02:22:29.669 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.28.20:5700/2) Recv SETFORMAT cmd
2026-01-29 02:22:29.669 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.28.20:5700/2) TRXD header version 1 -> 1
2026-01-29 02:22:29.671 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.28.20:5700/3) Recv RXTUNE cmd
2026-01-29 02:22:29.671 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.28.20:5700/3) Recv TXTUNE cmd
2026-01-29 02:22:29.672 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.28.20:5700/3) Recv SETFORMAT cmd
2026-01-29 02:22:29.672 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.28.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:22:29.672 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:22:29.672 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.28.20:5700/3) Recv NOMTXPOWER cmd
2026-01-29 02:22:29.672 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.28.20:5700/3) Recv SETFORMAT cmd
2026-01-29 02:22:29.672 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.28.20:5700/3) TRXD header version 1 -> 1
2026-01-29 02:22:29.675 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.28.20:5700) Recv RXTUNE cmd
2026-01-29 02:22:29.675 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETTSC
2026-01-29 02:22:29.675 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETTSC
2026-01-29 02:22:29.675 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETTSC
2026-01-29 02:22:29.675 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.28.20:5700) Recv TXTUNE cmd
2026-01-29 02:22:29.675 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETRXGAIN
2026-01-29 02:22:29.675 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETRXGAIN
2026-01-29 02:22:29.675 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETRXGAIN
2026-01-29 02:22:29.675 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETTSC
2026-01-29 02:22:29.675 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:22:29.675 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:22:29.675 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.28.20:5700) Recv NOMTXPOWER cmd
2026-01-29 02:22:29.675 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:22:29.676 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:22:29.676 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:22:29.676 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.28.20:5700) Recv POWERON CMD
2026-01-29 02:22:29.676 [INFO] ctrl_if_trx.py:109 (BTS@172.18.28.20:5700) Starting transceiver...
2026-01-29 02:22:29.676 [INFO] transceiver.py:243 Starting clock generator
2026-01-29 02:22:29.676 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-01-29 02:22:29.676 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:22:29.676 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:22:29.676 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:22:29.676 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETRXGAIN
2026-01-29 02:22:29.676 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:22:29.676 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:22:29.676 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:22:29.676 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:22:29.676 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:22:29.676 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:22:29.677 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:22:29.677 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:22:29.677 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:22:29.677 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:22:29.677 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:22:29.677 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:22:29.677 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:22:29.677 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:22:29.677 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:22:29.677 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:22:29.677 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:22:29.678 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:22:29.678 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:22:29.678 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:22:29.678 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:22:29.678 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:22:29.678 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:22:29.678 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:22:29.681 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-01-29 02:22:30.164 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-01-29 02:22:30.200 [DEBUG] fake_trx.py:278 (BTS@172.18.28.20:5700) Recv FAKE_TOA cmd
2026-01-29 02:22:30.202 [DEBUG] fake_trx.py:297 (BTS@172.18.28.20:5700) Recv FAKE_RSSI cmd
2026-01-29 02:22:30.203 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:22:30.205 [DEBUG] fake_trx.py:322 (BTS@172.18.28.20:5700) Recv FAKE_CI cmd
2026-01-29 02:22:30.207 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 02:22:30.207 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 02:22:30.207 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 02:22:30.207 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:22:30.207 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 02:22:30.207 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 02:22:30.207 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.28.22:6700) Recv POWERON CMD
2026-01-29 02:22:30.208 [INFO] ctrl_if_trx.py:109 (MS@172.18.28.22:6700) Starting transceiver...
2026-01-29 02:22:30.254 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 02:22:30.254 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 02:22:30.255 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:22:30.255 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:22:30.641 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-01-29 02:22:30.679 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 02:22:30.680 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:22:30.682 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:22:30.684 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:22:31.119 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-01-29 02:22:31.597 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-01-29 02:22:31.680 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 02:22:31.681 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:22:31.683 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:22:31.684 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:22:32.075 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-01-29 02:22:32.552 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-01-29 02:22:32.681 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 02:22:32.681 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:22:32.684 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:22:32.686 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:22:33.030 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-01-29 02:22:33.508 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-01-29 02:22:33.682 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 02:22:33.683 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:22:33.685 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:22:33.687 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:22:33.986 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-01-29 02:22:34.464 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-01-29 02:22:34.683 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 02:22:34.683 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:22:34.685 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:22:34.688 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:22:34.941 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-01-29 02:22:35.419 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-01-29 02:22:35.896 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-01-29 02:22:36.374 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-01-29 02:22:36.851 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-01-29 02:22:37.328 [DEBUG] clck_gen.py:113 IND CLOCK 1632
2026-01-29 02:22:37.806 [DEBUG] clck_gen.py:113 IND CLOCK 1734
2026-01-29 02:22:38.258 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 02:22:38.259 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 02:22:38.262 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 02:22:38.262 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:22:38.262 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:22:38.262 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:22:38.263 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 02:22:38.263 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:22:38.263 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:22:38.263 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:22:38.263 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.28.20:5700) Recv POWEROFF cmd
2026-01-29 02:22:38.263 [INFO] ctrl_if_trx.py:117 (BTS@172.18.28.20:5700) Stopping transceiver...
2026-01-29 02:22:38.263 [INFO] transceiver.py:246 Stopping clock generator
2026-01-29 02:22:38.263 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=1835 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:22:38.263 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=1835 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:22:38.263 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=1835 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:22:38.263 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=1835 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:22:38.263 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=1835 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:22:38.263 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=1835 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:22:38.263 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=1835 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:22:38.263 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=1835 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:22:43.265 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.28.20:5700) Recv POWEROFF cmd
2026-01-29 02:22:43.265 [INFO] ctrl_if_trx.py:117 (BTS@172.18.28.20:5700) Stopping transceiver...
2026-01-29 02:22:43.267 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:22:43.268 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:22:43.269 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:22:43.269 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 02:22:43.274 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 02:22:43.276 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.28.20:5700) Recv SETFORMAT cmd
2026-01-29 02:22:43.276 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.28.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:22:43.276 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.28.20:5700) Recv SETFORMAT cmd
2026-01-29 02:22:43.277 [INFO] ctrl_if_trx.py:201 (BTS@172.18.28.20:5700) TRXD header version 1 -> 1
2026-01-29 02:22:43.280 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.28.20:5700/1) Recv RXTUNE cmd
2026-01-29 02:22:43.280 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.28.20:5700/1) Recv TXTUNE cmd
2026-01-29 02:22:43.281 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.28.20:5700/1) Recv SETFORMAT cmd
2026-01-29 02:22:43.281 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.28.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:22:43.281 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:22:43.281 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.28.20:5700/1) Recv NOMTXPOWER cmd
2026-01-29 02:22:43.282 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.28.20:5700/1) Recv SETFORMAT cmd
2026-01-29 02:22:43.282 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.28.20:5700/1) TRXD header version 1 -> 1
2026-01-29 02:22:43.283 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.28.20:5700/2) Recv RXTUNE cmd
2026-01-29 02:22:43.283 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.28.20:5700/2) Recv TXTUNE cmd
2026-01-29 02:22:43.283 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.28.20:5700/2) Recv SETFORMAT cmd
2026-01-29 02:22:43.283 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.28.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:22:43.283 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:22:43.283 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.28.20:5700/2) Recv NOMTXPOWER cmd
2026-01-29 02:22:43.283 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.28.20:5700/2) Recv SETFORMAT cmd
2026-01-29 02:22:43.283 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.28.20:5700/2) TRXD header version 1 -> 1
2026-01-29 02:22:43.285 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.28.20:5700/3) Recv RXTUNE cmd
2026-01-29 02:22:43.285 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.28.20:5700/3) Recv TXTUNE cmd
2026-01-29 02:22:43.285 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.28.20:5700/3) Recv SETFORMAT cmd
2026-01-29 02:22:43.285 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.28.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:22:43.286 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:22:43.286 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.28.20:5700/3) Recv NOMTXPOWER cmd
2026-01-29 02:22:43.286 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.28.20:5700/3) Recv SETFORMAT cmd
2026-01-29 02:22:43.286 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.28.20:5700/3) TRXD header version 1 -> 1
2026-01-29 02:22:43.288 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.28.20:5700) Recv RXTUNE cmd
2026-01-29 02:22:43.288 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETTSC
2026-01-29 02:22:43.288 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETTSC
2026-01-29 02:22:43.288 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETTSC
2026-01-29 02:22:43.288 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.28.20:5700) Recv TXTUNE cmd
2026-01-29 02:22:43.288 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETRXGAIN
2026-01-29 02:22:43.288 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETRXGAIN
2026-01-29 02:22:43.289 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETRXGAIN
2026-01-29 02:22:43.289 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETTSC
2026-01-29 02:22:43.289 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:22:43.289 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:22:43.289 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:22:43.289 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.28.20:5700) Recv NOMTXPOWER cmd
2026-01-29 02:22:43.289 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:22:43.289 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:22:43.289 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:22:43.289 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.28.20:5700) Recv POWERON CMD
2026-01-29 02:22:43.289 [INFO] ctrl_if_trx.py:109 (BTS@172.18.28.20:5700) Starting transceiver...
2026-01-29 02:22:43.289 [INFO] transceiver.py:243 Starting clock generator
2026-01-29 02:22:43.289 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-01-29 02:22:43.289 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:22:43.289 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:22:43.289 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:22:43.289 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETRXGAIN
2026-01-29 02:22:43.289 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:22:43.289 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:22:43.289 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:22:43.289 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:22:43.289 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:22:43.289 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:22:43.289 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:22:43.290 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:22:43.290 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:22:43.290 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:22:43.290 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:22:43.290 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:22:43.290 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:22:43.290 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:22:43.290 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:22:43.290 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:22:43.290 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:22:43.290 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:22:43.290 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:22:43.290 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:22:43.290 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:22:43.291 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:22:43.291 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:22:43.291 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:22:43.291 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:22:43.291 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:22:43.291 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 02:22:43.291 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.28.20:5700) Recv POWEROFF cmd
2026-01-29 02:22:43.291 [INFO] ctrl_if_trx.py:117 (BTS@172.18.28.20:5700) Stopping transceiver...
2026-01-29 02:22:43.291 [INFO] transceiver.py:246 Stopping clock generator
2026-01-29 02:22:48.294 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.28.20:5700) Recv POWEROFF cmd
2026-01-29 02:22:48.294 [INFO] ctrl_if_trx.py:117 (BTS@172.18.28.20:5700) Stopping transceiver...
2026-01-29 02:22:48.296 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:22:48.297 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:22:48.298 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:22:48.299 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 02:22:48.303 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 02:22:48.304 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.28.20:5700) Recv SETFORMAT cmd
2026-01-29 02:22:48.304 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.28.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:22:48.305 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.28.20:5700) Recv SETFORMAT cmd
2026-01-29 02:22:48.305 [INFO] ctrl_if_trx.py:201 (BTS@172.18.28.20:5700) TRXD header version 1 -> 1
2026-01-29 02:22:48.308 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.28.20:5700/1) Recv RXTUNE cmd
2026-01-29 02:22:48.308 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.28.20:5700/1) Recv TXTUNE cmd
2026-01-29 02:22:48.309 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.28.20:5700/1) Recv SETFORMAT cmd
2026-01-29 02:22:48.309 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.28.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:22:48.309 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:22:48.309 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.28.20:5700/1) Recv NOMTXPOWER cmd
2026-01-29 02:22:48.310 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.28.20:5700/1) Recv SETFORMAT cmd
2026-01-29 02:22:48.310 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.28.20:5700/1) TRXD header version 1 -> 1
2026-01-29 02:22:48.311 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.28.20:5700/2) Recv RXTUNE cmd
2026-01-29 02:22:48.311 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.28.20:5700/2) Recv TXTUNE cmd
2026-01-29 02:22:48.311 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.28.20:5700/2) Recv SETFORMAT cmd
2026-01-29 02:22:48.311 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.28.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:22:48.311 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:22:48.311 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.28.20:5700/2) Recv NOMTXPOWER cmd
2026-01-29 02:22:48.311 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.28.20:5700/2) Recv SETFORMAT cmd
2026-01-29 02:22:48.311 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.28.20:5700/2) TRXD header version 1 -> 1
2026-01-29 02:22:48.314 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.28.20:5700/3) Recv RXTUNE cmd
2026-01-29 02:22:48.314 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.28.20:5700/3) Recv TXTUNE cmd
2026-01-29 02:22:48.314 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.28.20:5700/3) Recv SETFORMAT cmd
2026-01-29 02:22:48.314 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.28.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:22:48.314 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:22:48.314 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.28.20:5700/3) Recv NOMTXPOWER cmd
2026-01-29 02:22:48.314 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.28.20:5700/3) Recv SETFORMAT cmd
2026-01-29 02:22:48.314 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.28.20:5700/3) TRXD header version 1 -> 1
2026-01-29 02:22:48.316 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.28.20:5700) Recv RXTUNE cmd
2026-01-29 02:22:48.317 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETTSC
2026-01-29 02:22:48.317 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETTSC
2026-01-29 02:22:48.317 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETTSC
2026-01-29 02:22:48.317 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.28.20:5700) Recv TXTUNE cmd
2026-01-29 02:22:48.317 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETRXGAIN
2026-01-29 02:22:48.317 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETRXGAIN
2026-01-29 02:22:48.317 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETRXGAIN
2026-01-29 02:22:48.317 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETTSC
2026-01-29 02:22:48.317 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:22:48.317 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:22:48.317 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:22:48.317 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.28.20:5700) Recv NOMTXPOWER cmd
2026-01-29 02:22:48.317 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:22:48.317 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:22:48.317 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:22:48.317 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.28.20:5700) Recv POWERON CMD
2026-01-29 02:22:48.317 [INFO] ctrl_if_trx.py:109 (BTS@172.18.28.20:5700) Starting transceiver...
2026-01-29 02:22:48.317 [INFO] transceiver.py:243 Starting clock generator
2026-01-29 02:22:48.317 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-01-29 02:22:48.318 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:22:48.318 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:22:48.318 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:22:48.318 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETRXGAIN
2026-01-29 02:22:48.318 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:22:48.318 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:22:48.318 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:22:48.318 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:22:48.318 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:22:48.318 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:22:48.318 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:22:48.318 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:22:48.318 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:22:48.318 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:22:48.318 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:22:48.318 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:22:48.318 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:22:48.318 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:22:48.318 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:22:48.318 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:22:48.318 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:22:48.318 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:22:48.318 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:22:48.318 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:22:48.318 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:22:48.318 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:22:48.318 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:22:48.322 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-01-29 02:22:48.805 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-01-29 02:22:48.848 [DEBUG] fake_trx.py:278 (BTS@172.18.28.20:5700) Recv FAKE_TOA cmd
2026-01-29 02:22:48.850 [DEBUG] fake_trx.py:297 (BTS@172.18.28.20:5700) Recv FAKE_RSSI cmd
2026-01-29 02:22:48.851 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:22:48.852 [DEBUG] fake_trx.py:322 (BTS@172.18.28.20:5700) Recv FAKE_CI cmd
2026-01-29 02:22:48.855 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 02:22:48.855 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 02:22:48.856 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 02:22:48.856 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:22:48.857 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 02:22:48.857 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 02:22:48.858 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.28.22:6700) Recv POWERON CMD
2026-01-29 02:22:48.858 [INFO] ctrl_if_trx.py:109 (MS@172.18.28.22:6700) Starting transceiver...
2026-01-29 02:22:49.283 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-01-29 02:22:49.320 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 02:22:49.321 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:22:49.321 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:22:49.323 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:22:49.761 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-01-29 02:22:50.238 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-01-29 02:22:50.321 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 02:22:50.322 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:22:50.322 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:22:50.324 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:22:50.716 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-01-29 02:22:51.193 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-01-29 02:22:51.323 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:22:51.323 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:22:51.323 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 02:22:51.326 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:22:51.671 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-01-29 02:22:52.149 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-01-29 02:22:52.324 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 02:22:52.324 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:22:52.325 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:22:52.327 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:22:52.626 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-01-29 02:22:53.104 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-01-29 02:22:53.326 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:22:53.326 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:22:53.326 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 02:22:53.327 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:22:53.581 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-01-29 02:22:54.058 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-01-29 02:22:54.536 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-01-29 02:22:55.013 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-01-29 02:22:55.490 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-01-29 02:22:55.968 [DEBUG] clck_gen.py:113 IND CLOCK 1632
2026-01-29 02:22:56.446 [DEBUG] clck_gen.py:113 IND CLOCK 1734
2026-01-29 02:22:56.923 [DEBUG] clck_gen.py:113 IND CLOCK 1836
2026-01-29 02:22:57.400 [DEBUG] clck_gen.py:113 IND CLOCK 1938
2026-01-29 02:22:57.878 [DEBUG] clck_gen.py:113 IND CLOCK 2040
2026-01-29 02:22:58.355 [DEBUG] clck_gen.py:113 IND CLOCK 2142
2026-01-29 02:22:58.833 [DEBUG] clck_gen.py:113 IND CLOCK 2244
2026-01-29 02:22:58.901 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 02:22:58.901 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 02:22:58.907 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 02:22:58.907 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:22:58.907 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:22:58.907 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:22:58.909 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 02:22:58.909 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:22:58.909 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:22:58.909 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.28.20:5700) Recv POWEROFF cmd
2026-01-29 02:22:58.909 [INFO] ctrl_if_trx.py:117 (BTS@172.18.28.20:5700) Stopping transceiver...
2026-01-29 02:22:58.909 [INFO] transceiver.py:246 Stopping clock generator
2026-01-29 02:22:58.909 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:22:58.909 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=2261 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:22:58.910 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=2261 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:22:58.910 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=2261 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:22:58.910 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=2261 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:22:58.910 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=2261 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:22:58.910 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=2262 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:22:58.910 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=2262 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:22:58.910 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=2262 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:22:58.910 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=2262 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:22:58.910 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=2262 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:22:58.910 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=2262 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:22:58.910 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=2262 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:22:58.911 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=2262 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:23:03.911 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.28.20:5700) Recv POWEROFF cmd
2026-01-29 02:23:03.912 [INFO] ctrl_if_trx.py:117 (BTS@172.18.28.20:5700) Stopping transceiver...
2026-01-29 02:23:03.913 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:23:03.914 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:23:03.915 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:23:03.916 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 02:23:03.918 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 02:23:03.919 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.28.20:5700) Recv SETFORMAT cmd
2026-01-29 02:23:03.919 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.28.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:23:03.920 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.28.20:5700) Recv SETFORMAT cmd
2026-01-29 02:23:03.920 [INFO] ctrl_if_trx.py:201 (BTS@172.18.28.20:5700) TRXD header version 1 -> 1
2026-01-29 02:23:03.922 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.28.20:5700/1) Recv RXTUNE cmd
2026-01-29 02:23:03.923 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.28.20:5700/1) Recv TXTUNE cmd
2026-01-29 02:23:03.923 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.28.20:5700/1) Recv SETFORMAT cmd
2026-01-29 02:23:03.923 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.28.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:23:03.923 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:23:03.924 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.28.20:5700/1) Recv NOMTXPOWER cmd
2026-01-29 02:23:03.924 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.28.20:5700/1) Recv SETFORMAT cmd
2026-01-29 02:23:03.924 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.28.20:5700/1) TRXD header version 1 -> 1
2026-01-29 02:23:03.928 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.28.20:5700/2) Recv RXTUNE cmd
2026-01-29 02:23:03.928 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.28.20:5700/2) Recv TXTUNE cmd
2026-01-29 02:23:03.929 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.28.20:5700/2) Recv SETFORMAT cmd
2026-01-29 02:23:03.929 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.28.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:23:03.929 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:23:03.929 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.28.20:5700/2) Recv NOMTXPOWER cmd
2026-01-29 02:23:03.929 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.28.20:5700/2) Recv SETFORMAT cmd
2026-01-29 02:23:03.929 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.28.20:5700/2) TRXD header version 1 -> 1
2026-01-29 02:23:03.930 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.28.20:5700/3) Recv RXTUNE cmd
2026-01-29 02:23:03.930 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.28.20:5700/3) Recv TXTUNE cmd
2026-01-29 02:23:03.930 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.28.20:5700/3) Recv SETFORMAT cmd
2026-01-29 02:23:03.930 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.28.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:23:03.930 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:23:03.930 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.28.20:5700/3) Recv NOMTXPOWER cmd
2026-01-29 02:23:03.930 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.28.20:5700/3) Recv SETFORMAT cmd
2026-01-29 02:23:03.930 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.28.20:5700/3) TRXD header version 1 -> 1
2026-01-29 02:23:03.932 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.28.20:5700) Recv RXTUNE cmd
2026-01-29 02:23:03.932 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETTSC
2026-01-29 02:23:03.932 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETTSC
2026-01-29 02:23:03.932 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETTSC
2026-01-29 02:23:03.932 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.28.20:5700) Recv TXTUNE cmd
2026-01-29 02:23:03.932 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETRXGAIN
2026-01-29 02:23:03.932 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETRXGAIN
2026-01-29 02:23:03.933 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETRXGAIN
2026-01-29 02:23:03.933 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETTSC
2026-01-29 02:23:03.933 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:23:03.933 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:23:03.933 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:23:03.933 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.28.20:5700) Recv NOMTXPOWER cmd
2026-01-29 02:23:03.933 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:23:03.933 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:23:03.933 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:23:03.933 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.28.20:5700) Recv POWERON CMD
2026-01-29 02:23:03.933 [INFO] ctrl_if_trx.py:109 (BTS@172.18.28.20:5700) Starting transceiver...
2026-01-29 02:23:03.933 [INFO] transceiver.py:243 Starting clock generator
2026-01-29 02:23:03.933 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-01-29 02:23:03.933 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:23:03.933 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:23:03.933 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:23:03.933 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETRXGAIN
2026-01-29 02:23:03.933 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:23:03.933 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:23:03.933 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:23:03.933 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:23:03.934 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:23:03.934 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:23:03.934 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:23:03.934 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:23:03.934 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:23:03.934 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:23:03.934 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:23:03.934 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:23:03.934 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:23:03.935 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:23:03.935 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:23:03.935 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:23:03.935 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:23:03.935 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:23:03.935 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:23:03.935 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:23:03.935 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:23:03.935 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:23:03.935 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:23:03.935 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:23:03.935 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 02:23:03.935 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:23:03.935 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.28.20:5700) Recv POWEROFF cmd
2026-01-29 02:23:03.935 [INFO] ctrl_if_trx.py:117 (BTS@172.18.28.20:5700) Stopping transceiver...
2026-01-29 02:23:03.935 [INFO] transceiver.py:246 Stopping clock generator
2026-01-29 02:23:03.935 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:23:08.938 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.28.20:5700) Recv POWEROFF cmd
2026-01-29 02:23:08.938 [INFO] ctrl_if_trx.py:117 (BTS@172.18.28.20:5700) Stopping transceiver...
2026-01-29 02:23:08.940 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:23:08.941 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:23:08.942 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:23:08.943 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 02:23:08.950 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 02:23:08.950 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.28.20:5700) Recv SETFORMAT cmd
2026-01-29 02:23:08.950 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.28.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:23:08.950 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.28.20:5700) Recv SETFORMAT cmd
2026-01-29 02:23:08.950 [INFO] ctrl_if_trx.py:201 (BTS@172.18.28.20:5700) TRXD header version 1 -> 1
2026-01-29 02:23:08.951 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.28.20:5700/1) Recv RXTUNE cmd
2026-01-29 02:23:08.951 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.28.20:5700/1) Recv TXTUNE cmd
2026-01-29 02:23:08.951 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.28.20:5700/1) Recv SETFORMAT cmd
2026-01-29 02:23:08.951 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.28.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:23:08.952 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:23:08.952 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.28.20:5700/1) Recv NOMTXPOWER cmd
2026-01-29 02:23:08.952 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.28.20:5700/1) Recv SETFORMAT cmd
2026-01-29 02:23:08.952 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.28.20:5700/1) TRXD header version 1 -> 1
2026-01-29 02:23:08.953 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.28.20:5700/2) Recv RXTUNE cmd
2026-01-29 02:23:08.953 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.28.20:5700/2) Recv TXTUNE cmd
2026-01-29 02:23:08.953 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.28.20:5700/2) Recv SETFORMAT cmd
2026-01-29 02:23:08.953 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.28.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:23:08.953 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:23:08.953 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.28.20:5700/2) Recv NOMTXPOWER cmd
2026-01-29 02:23:08.953 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.28.20:5700/2) Recv SETFORMAT cmd
2026-01-29 02:23:08.953 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.28.20:5700/2) TRXD header version 1 -> 1
2026-01-29 02:23:08.955 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.28.20:5700/3) Recv RXTUNE cmd
2026-01-29 02:23:08.955 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.28.20:5700/3) Recv TXTUNE cmd
2026-01-29 02:23:08.955 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.28.20:5700/3) Recv SETFORMAT cmd
2026-01-29 02:23:08.955 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.28.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:23:08.955 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:23:08.955 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.28.20:5700/3) Recv NOMTXPOWER cmd
2026-01-29 02:23:08.955 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.28.20:5700/3) Recv SETFORMAT cmd
2026-01-29 02:23:08.955 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.28.20:5700/3) TRXD header version 1 -> 1
2026-01-29 02:23:08.957 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.28.20:5700) Recv RXTUNE cmd
2026-01-29 02:23:08.957 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETTSC
2026-01-29 02:23:08.957 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETTSC
2026-01-29 02:23:08.957 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETTSC
2026-01-29 02:23:08.957 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.28.20:5700) Recv TXTUNE cmd
2026-01-29 02:23:08.958 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETRXGAIN
2026-01-29 02:23:08.958 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETRXGAIN
2026-01-29 02:23:08.958 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETRXGAIN
2026-01-29 02:23:08.958 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETTSC
2026-01-29 02:23:08.958 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:23:08.958 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:23:08.958 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:23:08.958 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.28.20:5700) Recv NOMTXPOWER cmd
2026-01-29 02:23:08.958 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:23:08.958 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:23:08.958 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.28.20:5700) Recv POWERON CMD
2026-01-29 02:23:08.958 [INFO] ctrl_if_trx.py:109 (BTS@172.18.28.20:5700) Starting transceiver...
2026-01-29 02:23:08.958 [INFO] transceiver.py:243 Starting clock generator
2026-01-29 02:23:08.958 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-01-29 02:23:08.958 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:23:08.958 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:23:08.958 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:23:08.958 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETRXGAIN
2026-01-29 02:23:08.958 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:23:08.958 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:23:08.958 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:23:08.958 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:23:08.958 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:23:08.958 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:23:08.958 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:23:08.958 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:23:08.959 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:23:08.959 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:23:08.959 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:23:08.959 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:23:08.959 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:23:08.959 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:23:08.959 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:23:08.959 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:23:08.959 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:23:08.959 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:23:08.959 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:23:08.959 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:23:08.959 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:23:08.959 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:23:08.959 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:23:08.959 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:23:08.963 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-01-29 02:23:09.447 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-01-29 02:23:09.485 [DEBUG] fake_trx.py:278 (BTS@172.18.28.20:5700) Recv FAKE_TOA cmd
2026-01-29 02:23:09.487 [DEBUG] fake_trx.py:297 (BTS@172.18.28.20:5700) Recv FAKE_RSSI cmd
2026-01-29 02:23:09.488 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:23:09.489 [DEBUG] fake_trx.py:322 (BTS@172.18.28.20:5700) Recv FAKE_CI cmd
2026-01-29 02:23:09.492 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 02:23:09.492 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 02:23:09.493 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 02:23:09.493 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:23:09.493 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 02:23:09.493 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 02:23:09.493 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.28.22:6700) Recv POWERON CMD
2026-01-29 02:23:09.493 [INFO] ctrl_if_trx.py:109 (MS@172.18.28.22:6700) Starting transceiver...
2026-01-29 02:23:09.537 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 02:23:09.537 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 02:23:09.538 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:23:09.539 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:23:09.924 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-01-29 02:23:09.961 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 02:23:09.962 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:23:09.962 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:23:09.965 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:23:10.402 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-01-29 02:23:10.879 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-01-29 02:23:10.962 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 02:23:10.963 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:23:10.963 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:23:10.966 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:23:11.357 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-01-29 02:23:11.835 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-01-29 02:23:11.963 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 02:23:11.964 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:23:11.964 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:23:11.968 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:23:12.312 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-01-29 02:23:12.790 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-01-29 02:23:12.965 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:23:12.965 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:23:12.965 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 02:23:12.969 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:23:13.268 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-01-29 02:23:13.746 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-01-29 02:23:13.966 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 02:23:13.966 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:23:13.967 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:23:13.970 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:23:14.223 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-01-29 02:23:14.701 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-01-29 02:23:15.177 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-01-29 02:23:15.655 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-01-29 02:23:16.132 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-01-29 02:23:16.610 [DEBUG] clck_gen.py:113 IND CLOCK 1632
2026-01-29 02:23:17.088 [DEBUG] clck_gen.py:113 IND CLOCK 1734
2026-01-29 02:23:17.565 [DEBUG] clck_gen.py:113 IND CLOCK 1836
2026-01-29 02:23:18.043 [DEBUG] clck_gen.py:113 IND CLOCK 1938
2026-01-29 02:23:18.521 [DEBUG] clck_gen.py:113 IND CLOCK 2040
2026-01-29 02:23:18.999 [DEBUG] clck_gen.py:113 IND CLOCK 2142
2026-01-29 02:23:19.476 [DEBUG] clck_gen.py:113 IND CLOCK 2244
2026-01-29 02:23:19.954 [DEBUG] clck_gen.py:113 IND CLOCK 2346
2026-01-29 02:23:20.432 [DEBUG] clck_gen.py:113 IND CLOCK 2448
2026-01-29 02:23:20.541 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 02:23:20.542 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 02:23:20.548 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 02:23:20.548 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:23:20.548 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:23:20.548 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:23:20.549 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 02:23:20.549 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:23:20.549 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:23:20.549 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.28.20:5700) Recv POWEROFF cmd
2026-01-29 02:23:20.549 [INFO] ctrl_if_trx.py:117 (BTS@172.18.28.20:5700) Stopping transceiver...
2026-01-29 02:23:20.549 [INFO] transceiver.py:246 Stopping clock generator
2026-01-29 02:23:20.549 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:23:25.551 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.28.20:5700) Recv POWEROFF cmd
2026-01-29 02:23:25.551 [INFO] ctrl_if_trx.py:117 (BTS@172.18.28.20:5700) Stopping transceiver...
2026-01-29 02:23:25.553 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:23:25.553 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:23:25.554 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:23:25.554 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 02:23:25.557 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 02:23:25.558 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.28.20:5700) Recv SETFORMAT cmd
2026-01-29 02:23:25.558 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.28.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:23:25.558 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.28.20:5700) Recv SETFORMAT cmd
2026-01-29 02:23:25.558 [INFO] ctrl_if_trx.py:201 (BTS@172.18.28.20:5700) TRXD header version 1 -> 1
2026-01-29 02:23:25.561 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.28.20:5700/1) Recv RXTUNE cmd
2026-01-29 02:23:25.561 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.28.20:5700/1) Recv TXTUNE cmd
2026-01-29 02:23:25.561 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.28.20:5700/1) Recv SETFORMAT cmd
2026-01-29 02:23:25.561 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.28.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:23:25.561 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:23:25.561 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.28.20:5700/1) Recv NOMTXPOWER cmd
2026-01-29 02:23:25.561 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.28.20:5700/1) Recv SETFORMAT cmd
2026-01-29 02:23:25.561 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.28.20:5700/1) TRXD header version 1 -> 1
2026-01-29 02:23:25.563 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.28.20:5700/2) Recv RXTUNE cmd
2026-01-29 02:23:25.563 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.28.20:5700/2) Recv TXTUNE cmd
2026-01-29 02:23:25.563 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.28.20:5700/2) Recv SETFORMAT cmd
2026-01-29 02:23:25.563 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.28.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:23:25.563 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:23:25.563 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.28.20:5700/2) Recv NOMTXPOWER cmd
2026-01-29 02:23:25.563 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.28.20:5700/2) Recv SETFORMAT cmd
2026-01-29 02:23:25.563 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.28.20:5700/2) TRXD header version 1 -> 1
2026-01-29 02:23:25.565 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.28.20:5700/3) Recv RXTUNE cmd
2026-01-29 02:23:25.565 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.28.20:5700/3) Recv TXTUNE cmd
2026-01-29 02:23:25.565 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.28.20:5700/3) Recv SETFORMAT cmd
2026-01-29 02:23:25.565 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.28.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:23:25.565 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:23:25.565 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.28.20:5700/3) Recv NOMTXPOWER cmd
2026-01-29 02:23:25.565 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.28.20:5700/3) Recv SETFORMAT cmd
2026-01-29 02:23:25.565 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.28.20:5700/3) TRXD header version 1 -> 1
2026-01-29 02:23:25.567 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.28.20:5700) Recv RXTUNE cmd
2026-01-29 02:23:25.567 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETTSC
2026-01-29 02:23:25.567 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETTSC
2026-01-29 02:23:25.567 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETTSC
2026-01-29 02:23:25.567 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.28.20:5700) Recv TXTUNE cmd
2026-01-29 02:23:25.567 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETRXGAIN
2026-01-29 02:23:25.567 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETRXGAIN
2026-01-29 02:23:25.567 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETRXGAIN
2026-01-29 02:23:25.567 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETTSC
2026-01-29 02:23:25.567 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:23:25.567 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:23:25.567 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:23:25.567 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.28.20:5700) Recv NOMTXPOWER cmd
2026-01-29 02:23:25.567 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:23:25.567 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:23:25.567 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:23:25.567 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.28.20:5700) Recv POWERON CMD
2026-01-29 02:23:25.567 [INFO] ctrl_if_trx.py:109 (BTS@172.18.28.20:5700) Starting transceiver...
2026-01-29 02:23:25.567 [INFO] transceiver.py:243 Starting clock generator
2026-01-29 02:23:25.568 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-01-29 02:23:25.568 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:23:25.568 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:23:25.568 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:23:25.568 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETRXGAIN
2026-01-29 02:23:25.568 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:23:25.568 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:23:25.568 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:23:25.568 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:23:25.568 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:23:25.568 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:23:25.568 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:23:25.568 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:23:25.568 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:23:25.568 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:23:25.568 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:23:25.568 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:23:25.568 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:23:25.568 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:23:25.569 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:23:25.569 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:23:25.569 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:23:25.569 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:23:25.569 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:23:25.569 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:23:25.569 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:23:25.569 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:23:25.569 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:23:25.569 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:23:25.569 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:23:25.569 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:23:25.569 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 02:23:25.569 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.28.20:5700) Recv POWEROFF cmd
2026-01-29 02:23:25.569 [INFO] ctrl_if_trx.py:117 (BTS@172.18.28.20:5700) Stopping transceiver...
2026-01-29 02:23:25.569 [INFO] transceiver.py:246 Stopping clock generator
2026-01-29 02:23:30.573 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.28.20:5700) Recv POWEROFF cmd
2026-01-29 02:23:30.573 [INFO] ctrl_if_trx.py:117 (BTS@172.18.28.20:5700) Stopping transceiver...
2026-01-29 02:23:30.575 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:23:30.575 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:23:30.576 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:23:30.576 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 02:23:30.579 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 02:23:30.580 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.28.20:5700) Recv SETFORMAT cmd
2026-01-29 02:23:30.580 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.28.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:23:30.580 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.28.20:5700) Recv SETFORMAT cmd
2026-01-29 02:23:30.580 [INFO] ctrl_if_trx.py:201 (BTS@172.18.28.20:5700) TRXD header version 1 -> 1
2026-01-29 02:23:30.582 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.28.20:5700/1) Recv RXTUNE cmd
2026-01-29 02:23:30.582 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.28.20:5700/1) Recv TXTUNE cmd
2026-01-29 02:23:30.582 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.28.20:5700/1) Recv SETFORMAT cmd
2026-01-29 02:23:30.582 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.28.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:23:30.583 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:23:30.583 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.28.20:5700/1) Recv NOMTXPOWER cmd
2026-01-29 02:23:30.583 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.28.20:5700/1) Recv SETFORMAT cmd
2026-01-29 02:23:30.583 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.28.20:5700/1) TRXD header version 1 -> 1
2026-01-29 02:23:30.584 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.28.20:5700/2) Recv RXTUNE cmd
2026-01-29 02:23:30.584 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.28.20:5700/2) Recv TXTUNE cmd
2026-01-29 02:23:30.584 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.28.20:5700/2) Recv SETFORMAT cmd
2026-01-29 02:23:30.584 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.28.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:23:30.584 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:23:30.584 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.28.20:5700/2) Recv NOMTXPOWER cmd
2026-01-29 02:23:30.584 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.28.20:5700/2) Recv SETFORMAT cmd
2026-01-29 02:23:30.584 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.28.20:5700/2) TRXD header version 1 -> 1
2026-01-29 02:23:30.586 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.28.20:5700/3) Recv RXTUNE cmd
2026-01-29 02:23:30.586 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.28.20:5700/3) Recv TXTUNE cmd
2026-01-29 02:23:30.586 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.28.20:5700/3) Recv SETFORMAT cmd
2026-01-29 02:23:30.586 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.28.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:23:30.586 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:23:30.586 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.28.20:5700/3) Recv NOMTXPOWER cmd
2026-01-29 02:23:30.586 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.28.20:5700/3) Recv SETFORMAT cmd
2026-01-29 02:23:30.586 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.28.20:5700/3) TRXD header version 1 -> 1
2026-01-29 02:23:30.588 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.28.20:5700) Recv RXTUNE cmd
2026-01-29 02:23:30.588 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETTSC
2026-01-29 02:23:30.588 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETTSC
2026-01-29 02:23:30.588 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETTSC
2026-01-29 02:23:30.588 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.28.20:5700) Recv TXTUNE cmd
2026-01-29 02:23:30.588 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETRXGAIN
2026-01-29 02:23:30.588 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETRXGAIN
2026-01-29 02:23:30.588 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETRXGAIN
2026-01-29 02:23:30.588 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETTSC
2026-01-29 02:23:30.588 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:23:30.588 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:23:30.588 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:23:30.588 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.28.20:5700) Recv NOMTXPOWER cmd
2026-01-29 02:23:30.588 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:23:30.588 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:23:30.588 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:23:30.588 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.28.20:5700) Recv POWERON CMD
2026-01-29 02:23:30.588 [INFO] ctrl_if_trx.py:109 (BTS@172.18.28.20:5700) Starting transceiver...
2026-01-29 02:23:30.588 [INFO] transceiver.py:243 Starting clock generator
2026-01-29 02:23:30.588 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-01-29 02:23:30.588 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:23:30.588 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:23:30.588 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:23:30.588 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETRXGAIN
2026-01-29 02:23:30.588 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:23:30.588 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:23:30.588 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:23:30.588 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:23:30.588 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:23:30.588 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:23:30.588 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:23:30.589 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:23:30.589 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:23:30.589 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:23:30.589 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:23:30.589 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:23:30.589 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:23:30.589 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:23:30.589 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:23:30.589 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:23:30.589 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:23:30.589 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:23:30.589 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:23:30.589 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:23:30.589 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:23:30.589 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:23:30.589 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:23:30.593 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-01-29 02:23:31.075 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-01-29 02:23:31.112 [DEBUG] fake_trx.py:278 (BTS@172.18.28.20:5700) Recv FAKE_TOA cmd
2026-01-29 02:23:31.114 [DEBUG] fake_trx.py:297 (BTS@172.18.28.20:5700) Recv FAKE_RSSI cmd
2026-01-29 02:23:31.116 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:23:31.116 [DEBUG] fake_trx.py:322 (BTS@172.18.28.20:5700) Recv FAKE_CI cmd
2026-01-29 02:23:31.556 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-01-29 02:23:31.591 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:23:31.591 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 02:23:31.592 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:23:31.593 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:23:32.035 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-01-29 02:23:32.514 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-01-29 02:23:32.592 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:23:32.592 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 02:23:32.592 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:23:32.594 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:23:32.991 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-01-29 02:23:33.471 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-01-29 02:23:33.593 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:23:33.593 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 02:23:33.594 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:23:33.594 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:23:33.950 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-01-29 02:23:34.427 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-01-29 02:23:34.594 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 02:23:34.594 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:23:34.594 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:23:34.595 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:23:34.905 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-01-29 02:23:35.383 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-01-29 02:23:35.595 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 02:23:35.595 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:23:35.595 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:23:35.595 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:23:35.860 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-01-29 02:23:36.340 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-01-29 02:23:36.816 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-01-29 02:23:37.286 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-01-29 02:23:37.754 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-01-29 02:23:38.233 [DEBUG] clck_gen.py:113 IND CLOCK 1632
2026-01-29 02:23:38.705 [DEBUG] clck_gen.py:113 IND CLOCK 1734
2026-01-29 02:23:39.174 [DEBUG] clck_gen.py:113 IND CLOCK 1836
2026-01-29 02:23:39.643 [DEBUG] clck_gen.py:113 IND CLOCK 1938
2026-01-29 02:23:40.117 [DEBUG] clck_gen.py:113 IND CLOCK 2040
2026-01-29 02:23:40.594 [DEBUG] clck_gen.py:113 IND CLOCK 2142
2026-01-29 02:23:41.075 [DEBUG] clck_gen.py:113 IND CLOCK 2244
2026-01-29 02:23:41.124 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 02:23:41.124 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:23:41.124 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:23:41.124 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:23:41.125 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 02:23:41.125 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:23:41.125 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:23:41.125 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.28.20:5700) Recv POWEROFF cmd
2026-01-29 02:23:41.125 [INFO] ctrl_if_trx.py:117 (BTS@172.18.28.20:5700) Stopping transceiver...
2026-01-29 02:23:41.125 [INFO] transceiver.py:246 Stopping clock generator
2026-01-29 02:23:41.125 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:23:41.125 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=2256 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:23:41.125 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=2256 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:23:41.125 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=2256 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:23:46.128 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.28.20:5700) Recv POWEROFF cmd
2026-01-29 02:23:46.128 [INFO] ctrl_if_trx.py:117 (BTS@172.18.28.20:5700) Stopping transceiver...
2026-01-29 02:23:46.130 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:23:46.131 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:23:46.133 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:23:46.135 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 02:23:46.150 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 02:23:46.152 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.28.20:5700) Recv SETFORMAT cmd
2026-01-29 02:23:46.152 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.28.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:23:46.152 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.28.20:5700) Recv SETFORMAT cmd
2026-01-29 02:23:46.153 [INFO] ctrl_if_trx.py:201 (BTS@172.18.28.20:5700) TRXD header version 1 -> 1
2026-01-29 02:23:46.156 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.28.20:5700/1) Recv RXTUNE cmd
2026-01-29 02:23:46.156 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.28.20:5700/1) Recv TXTUNE cmd
2026-01-29 02:23:46.157 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.28.20:5700/1) Recv SETFORMAT cmd
2026-01-29 02:23:46.157 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.28.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:23:46.157 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:23:46.158 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.28.20:5700/1) Recv NOMTXPOWER cmd
2026-01-29 02:23:46.158 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.28.20:5700/1) Recv SETFORMAT cmd
2026-01-29 02:23:46.158 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.28.20:5700/1) TRXD header version 1 -> 1
2026-01-29 02:23:46.159 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.28.20:5700/2) Recv RXTUNE cmd
2026-01-29 02:23:46.159 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.28.20:5700/2) Recv TXTUNE cmd
2026-01-29 02:23:46.159 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.28.20:5700/2) Recv SETFORMAT cmd
2026-01-29 02:23:46.159 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.28.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:23:46.159 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:23:46.159 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.28.20:5700/2) Recv NOMTXPOWER cmd
2026-01-29 02:23:46.159 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.28.20:5700/2) Recv SETFORMAT cmd
2026-01-29 02:23:46.160 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.28.20:5700/2) TRXD header version 1 -> 1
2026-01-29 02:23:46.161 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.28.20:5700/3) Recv RXTUNE cmd
2026-01-29 02:23:46.161 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.28.20:5700/3) Recv TXTUNE cmd
2026-01-29 02:23:46.161 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.28.20:5700/3) Recv SETFORMAT cmd
2026-01-29 02:23:46.161 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.28.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:23:46.162 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:23:46.162 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.28.20:5700/3) Recv NOMTXPOWER cmd
2026-01-29 02:23:46.162 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.28.20:5700/3) Recv SETFORMAT cmd
2026-01-29 02:23:46.162 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.28.20:5700/3) TRXD header version 1 -> 1
2026-01-29 02:23:46.164 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.28.20:5700) Recv RXTUNE cmd
2026-01-29 02:23:46.164 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETTSC
2026-01-29 02:23:46.164 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETTSC
2026-01-29 02:23:46.164 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETTSC
2026-01-29 02:23:46.164 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.28.20:5700) Recv TXTUNE cmd
2026-01-29 02:23:46.164 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETRXGAIN
2026-01-29 02:23:46.164 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETRXGAIN
2026-01-29 02:23:46.164 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETRXGAIN
2026-01-29 02:23:46.164 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETTSC
2026-01-29 02:23:46.164 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:23:46.164 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:23:46.164 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:23:46.164 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.28.20:5700) Recv NOMTXPOWER cmd
2026-01-29 02:23:46.164 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:23:46.165 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:23:46.165 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:23:46.165 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.28.20:5700) Recv POWERON CMD
2026-01-29 02:23:46.165 [INFO] ctrl_if_trx.py:109 (BTS@172.18.28.20:5700) Starting transceiver...
2026-01-29 02:23:46.165 [INFO] transceiver.py:243 Starting clock generator
2026-01-29 02:23:46.165 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-01-29 02:23:46.165 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:23:46.165 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:23:46.165 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:23:46.165 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETRXGAIN
2026-01-29 02:23:46.165 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:23:46.165 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:23:46.165 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:23:46.165 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:23:46.166 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:23:46.166 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:23:46.166 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:23:46.166 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:23:46.166 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:23:46.166 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:23:46.166 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:23:46.166 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:23:46.166 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:23:46.166 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:23:46.166 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:23:46.166 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:23:46.166 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:23:46.166 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:23:46.166 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:23:46.166 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:23:46.166 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:23:46.166 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:23:46.166 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:23:46.166 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:23:46.166 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 02:23:46.166 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:23:46.166 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.28.20:5700) Recv POWEROFF cmd
2026-01-29 02:23:46.166 [INFO] ctrl_if_trx.py:117 (BTS@172.18.28.20:5700) Stopping transceiver...
2026-01-29 02:23:46.166 [INFO] transceiver.py:246 Stopping clock generator
2026-01-29 02:23:46.166 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:23:51.169 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.28.20:5700) Recv POWEROFF cmd
2026-01-29 02:23:51.169 [INFO] ctrl_if_trx.py:117 (BTS@172.18.28.20:5700) Stopping transceiver...
2026-01-29 02:23:51.175 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:23:51.175 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:23:51.175 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:23:51.176 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 02:23:51.183 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 02:23:51.184 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.28.20:5700) Recv SETFORMAT cmd
2026-01-29 02:23:51.184 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.28.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:23:51.185 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.28.20:5700) Recv SETFORMAT cmd
2026-01-29 02:23:51.185 [INFO] ctrl_if_trx.py:201 (BTS@172.18.28.20:5700) TRXD header version 1 -> 1
2026-01-29 02:23:51.188 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.28.20:5700/1) Recv RXTUNE cmd
2026-01-29 02:23:51.189 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.28.20:5700/1) Recv TXTUNE cmd
2026-01-29 02:23:51.189 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.28.20:5700/1) Recv SETFORMAT cmd
2026-01-29 02:23:51.189 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.28.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:23:51.190 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:23:51.190 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.28.20:5700/1) Recv NOMTXPOWER cmd
2026-01-29 02:23:51.190 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.28.20:5700/1) Recv SETFORMAT cmd
2026-01-29 02:23:51.191 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.28.20:5700/1) TRXD header version 1 -> 1
2026-01-29 02:23:51.192 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.28.20:5700/2) Recv RXTUNE cmd
2026-01-29 02:23:51.192 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.28.20:5700/2) Recv TXTUNE cmd
2026-01-29 02:23:51.192 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.28.20:5700/2) Recv SETFORMAT cmd
2026-01-29 02:23:51.192 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.28.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:23:51.192 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:23:51.193 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.28.20:5700/2) Recv NOMTXPOWER cmd
2026-01-29 02:23:51.193 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.28.20:5700/2) Recv SETFORMAT cmd
2026-01-29 02:23:51.193 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.28.20:5700/2) TRXD header version 1 -> 1
2026-01-29 02:23:51.194 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.28.20:5700/3) Recv RXTUNE cmd
2026-01-29 02:23:51.194 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.28.20:5700/3) Recv TXTUNE cmd
2026-01-29 02:23:51.194 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.28.20:5700/3) Recv SETFORMAT cmd
2026-01-29 02:23:51.194 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.28.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:23:51.194 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:23:51.194 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.28.20:5700/3) Recv NOMTXPOWER cmd
2026-01-29 02:23:51.195 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.28.20:5700/3) Recv SETFORMAT cmd
2026-01-29 02:23:51.195 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.28.20:5700/3) TRXD header version 1 -> 1
2026-01-29 02:23:51.197 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.28.20:5700) Recv RXTUNE cmd
2026-01-29 02:23:51.197 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETTSC
2026-01-29 02:23:51.197 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETTSC
2026-01-29 02:23:51.197 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETTSC
2026-01-29 02:23:51.197 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.28.20:5700) Recv TXTUNE cmd
2026-01-29 02:23:51.197 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETRXGAIN
2026-01-29 02:23:51.197 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETRXGAIN
2026-01-29 02:23:51.198 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETRXGAIN
2026-01-29 02:23:51.198 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETTSC
2026-01-29 02:23:51.198 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:23:51.198 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:23:51.198 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:23:51.198 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.28.20:5700) Recv NOMTXPOWER cmd
2026-01-29 02:23:51.198 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:23:51.198 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:23:51.198 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:23:51.198 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.28.20:5700) Recv POWERON CMD
2026-01-29 02:23:51.198 [INFO] ctrl_if_trx.py:109 (BTS@172.18.28.20:5700) Starting transceiver...
2026-01-29 02:23:51.198 [INFO] transceiver.py:243 Starting clock generator
2026-01-29 02:23:51.198 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-01-29 02:23:51.198 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:23:51.198 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:23:51.198 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:23:51.198 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETRXGAIN
2026-01-29 02:23:51.198 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:23:51.198 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:23:51.198 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:23:51.198 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:23:51.199 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:23:51.199 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:23:51.199 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:23:51.199 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:23:51.199 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:23:51.199 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:23:51.199 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:23:51.199 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:23:51.199 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:23:51.199 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:23:51.199 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:23:51.199 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:23:51.199 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:23:51.199 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:23:51.199 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:23:51.199 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:23:51.199 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:23:51.199 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:23:51.199 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:23:51.203 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-01-29 02:23:51.685 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-01-29 02:23:51.713 [DEBUG] fake_trx.py:278 (BTS@172.18.28.20:5700) Recv FAKE_TOA cmd
2026-01-29 02:23:51.714 [DEBUG] fake_trx.py:297 (BTS@172.18.28.20:5700) Recv FAKE_RSSI cmd
2026-01-29 02:23:51.714 [DEBUG] fake_trx.py:322 (BTS@172.18.28.20:5700) Recv FAKE_CI cmd
2026-01-29 02:23:51.714 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:23:52.154 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-01-29 02:23:52.202 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:23:52.202 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 02:23:52.202 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:23:52.206 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:23:52.623 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-01-29 02:23:53.101 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-01-29 02:23:53.202 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:23:53.203 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 02:23:53.203 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:23:53.207 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:23:53.575 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-01-29 02:23:54.044 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-01-29 02:23:54.204 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:23:54.205 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 02:23:54.205 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:23:54.209 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:23:54.520 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-01-29 02:23:54.998 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-01-29 02:23:55.205 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:23:55.206 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 02:23:55.206 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:23:55.210 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:23:55.476 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-01-29 02:23:55.955 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-01-29 02:23:56.206 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:23:56.207 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 02:23:56.207 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:23:56.211 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:23:56.435 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-01-29 02:23:56.911 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-01-29 02:23:57.392 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-01-29 02:23:57.874 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-01-29 02:23:58.352 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-01-29 02:23:58.830 [DEBUG] clck_gen.py:113 IND CLOCK 1632
2026-01-29 02:23:59.309 [DEBUG] clck_gen.py:113 IND CLOCK 1734
2026-01-29 02:23:59.789 [DEBUG] clck_gen.py:113 IND CLOCK 1836
2026-01-29 02:24:00.268 [DEBUG] clck_gen.py:113 IND CLOCK 1938
2026-01-29 02:24:00.748 [DEBUG] clck_gen.py:113 IND CLOCK 2040
2026-01-29 02:24:01.229 [DEBUG] clck_gen.py:113 IND CLOCK 2142
2026-01-29 02:24:01.710 [DEBUG] clck_gen.py:113 IND CLOCK 2244
2026-01-29 02:24:02.192 [DEBUG] clck_gen.py:113 IND CLOCK 2346
2026-01-29 02:24:02.672 [DEBUG] clck_gen.py:113 IND CLOCK 2448
2026-01-29 02:24:03.153 [DEBUG] clck_gen.py:113 IND CLOCK 2550
2026-01-29 02:24:03.634 [DEBUG] clck_gen.py:113 IND CLOCK 2652
2026-01-29 02:24:03.725 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 02:24:03.725 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:24:03.725 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:24:03.725 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:24:03.728 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 02:24:03.728 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:24:03.728 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:24:03.728 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:24:03.728 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.28.20:5700) Recv POWEROFF cmd
2026-01-29 02:24:03.728 [INFO] ctrl_if_trx.py:117 (BTS@172.18.28.20:5700) Stopping transceiver...
2026-01-29 02:24:03.728 [INFO] transceiver.py:246 Stopping clock generator
2026-01-29 02:24:08.727 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.28.20:5700) Recv POWEROFF cmd
2026-01-29 02:24:08.728 [INFO] ctrl_if_trx.py:117 (BTS@172.18.28.20:5700) Stopping transceiver...
2026-01-29 02:24:08.729 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:24:08.730 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:24:08.731 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:24:08.732 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 02:24:08.740 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 02:24:08.742 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.28.20:5700) Recv SETFORMAT cmd
2026-01-29 02:24:08.742 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.28.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:24:08.743 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.28.20:5700) Recv SETFORMAT cmd
2026-01-29 02:24:08.743 [INFO] ctrl_if_trx.py:201 (BTS@172.18.28.20:5700) TRXD header version 1 -> 1
2026-01-29 02:24:08.748 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.28.20:5700/1) Recv RXTUNE cmd
2026-01-29 02:24:08.749 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.28.20:5700/1) Recv TXTUNE cmd
2026-01-29 02:24:08.749 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.28.20:5700/1) Recv SETFORMAT cmd
2026-01-29 02:24:08.749 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.28.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:24:08.750 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:24:08.750 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.28.20:5700/1) Recv NOMTXPOWER cmd
2026-01-29 02:24:08.751 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.28.20:5700/1) Recv SETFORMAT cmd
2026-01-29 02:24:08.751 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.28.20:5700/1) TRXD header version 1 -> 1
2026-01-29 02:24:08.752 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.28.20:5700/2) Recv RXTUNE cmd
2026-01-29 02:24:08.752 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.28.20:5700/2) Recv TXTUNE cmd
2026-01-29 02:24:08.752 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.28.20:5700/2) Recv SETFORMAT cmd
2026-01-29 02:24:08.752 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.28.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:24:08.753 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:24:08.753 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.28.20:5700/2) Recv NOMTXPOWER cmd
2026-01-29 02:24:08.753 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.28.20:5700/2) Recv SETFORMAT cmd
2026-01-29 02:24:08.753 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.28.20:5700/2) TRXD header version 1 -> 1
2026-01-29 02:24:08.755 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.28.20:5700/3) Recv RXTUNE cmd
2026-01-29 02:24:08.755 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.28.20:5700/3) Recv TXTUNE cmd
2026-01-29 02:24:08.755 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.28.20:5700/3) Recv SETFORMAT cmd
2026-01-29 02:24:08.755 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.28.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:24:08.755 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:24:08.755 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.28.20:5700/3) Recv NOMTXPOWER cmd
2026-01-29 02:24:08.755 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.28.20:5700/3) Recv SETFORMAT cmd
2026-01-29 02:24:08.755 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.28.20:5700/3) TRXD header version 1 -> 1
2026-01-29 02:24:08.758 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.28.20:5700) Recv RXTUNE cmd
2026-01-29 02:24:08.758 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETTSC
2026-01-29 02:24:08.758 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETTSC
2026-01-29 02:24:08.758 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETTSC
2026-01-29 02:24:08.758 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.28.20:5700) Recv TXTUNE cmd
2026-01-29 02:24:08.758 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETRXGAIN
2026-01-29 02:24:08.758 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETRXGAIN
2026-01-29 02:24:08.759 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETRXGAIN
2026-01-29 02:24:08.759 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETTSC
2026-01-29 02:24:08.759 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:24:08.759 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:24:08.759 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:24:08.759 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.28.20:5700) Recv NOMTXPOWER cmd
2026-01-29 02:24:08.759 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:24:08.759 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:24:08.759 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:24:08.759 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.28.20:5700) Recv POWERON CMD
2026-01-29 02:24:08.759 [INFO] ctrl_if_trx.py:109 (BTS@172.18.28.20:5700) Starting transceiver...
2026-01-29 02:24:08.759 [INFO] transceiver.py:243 Starting clock generator
2026-01-29 02:24:08.759 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-01-29 02:24:08.759 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:24:08.759 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:24:08.759 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:24:08.759 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETRXGAIN
2026-01-29 02:24:08.759 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:24:08.759 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:24:08.760 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:24:08.760 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:24:08.760 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:24:08.760 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:24:08.760 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:24:08.760 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:24:08.760 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:24:08.760 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:24:08.760 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:24:08.760 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:24:08.760 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:24:08.760 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:24:08.760 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:24:08.760 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:24:08.760 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:24:08.760 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:24:08.760 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:24:08.760 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:24:08.760 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:24:08.760 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:24:08.760 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:24:08.764 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-01-29 02:24:09.248 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-01-29 02:24:09.287 [DEBUG] fake_trx.py:278 (BTS@172.18.28.20:5700) Recv FAKE_TOA cmd
2026-01-29 02:24:09.291 [DEBUG] fake_trx.py:297 (BTS@172.18.28.20:5700) Recv FAKE_RSSI cmd
2026-01-29 02:24:09.292 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:24:09.294 [DEBUG] fake_trx.py:322 (BTS@172.18.28.20:5700) Recv FAKE_CI cmd
2026-01-29 02:24:09.299 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 02:24:09.299 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 02:24:09.299 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 02:24:09.300 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:24:09.300 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 02:24:09.301 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 02:24:09.301 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.28.22:6700) Recv POWERON CMD
2026-01-29 02:24:09.302 [INFO] ctrl_if_trx.py:109 (MS@172.18.28.22:6700) Starting transceiver...
2026-01-29 02:24:09.725 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-01-29 02:24:09.762 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:24:09.763 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 02:24:09.763 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:24:09.764 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:24:10.203 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-01-29 02:24:10.680 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-01-29 02:24:10.764 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 02:24:10.764 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:24:10.764 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:24:10.764 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:24:11.158 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-01-29 02:24:11.636 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-01-29 02:24:11.765 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:24:11.765 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:24:11.765 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 02:24:11.766 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:24:12.114 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-01-29 02:24:12.591 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-01-29 02:24:12.765 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:24:12.766 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:24:12.766 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 02:24:12.766 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:24:13.069 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-01-29 02:24:13.546 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-01-29 02:24:13.767 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 02:24:13.767 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:24:13.767 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:24:13.768 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:24:14.024 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-01-29 02:24:14.502 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-01-29 02:24:14.980 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-01-29 02:24:15.457 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-01-29 02:24:15.935 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-01-29 02:24:16.413 [DEBUG] clck_gen.py:113 IND CLOCK 1632
2026-01-29 02:24:16.890 [DEBUG] clck_gen.py:113 IND CLOCK 1734
2026-01-29 02:24:17.368 [DEBUG] clck_gen.py:113 IND CLOCK 1836
2026-01-29 02:24:17.845 [DEBUG] clck_gen.py:113 IND CLOCK 1938
2026-01-29 02:24:18.323 [DEBUG] clck_gen.py:113 IND CLOCK 2040
2026-01-29 02:24:18.801 [DEBUG] clck_gen.py:113 IND CLOCK 2142
2026-01-29 02:24:19.278 [DEBUG] clck_gen.py:113 IND CLOCK 2244
2026-01-29 02:24:19.756 [DEBUG] clck_gen.py:113 IND CLOCK 2346
2026-01-29 02:24:20.234 [DEBUG] clck_gen.py:113 IND CLOCK 2448
2026-01-29 02:24:20.343 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 02:24:20.343 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 02:24:20.347 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 02:24:20.347 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:24:20.348 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:24:20.348 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:24:20.350 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 02:24:20.350 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:24:20.350 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:24:20.350 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:24:20.350 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.28.20:5700) Recv POWEROFF cmd
2026-01-29 02:24:20.350 [INFO] ctrl_if_trx.py:117 (BTS@172.18.28.20:5700) Stopping transceiver...
2026-01-29 02:24:20.350 [INFO] transceiver.py:246 Stopping clock generator
2026-01-29 02:24:20.350 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=2474 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:24:20.350 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=2474 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:24:20.350 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=2474 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:24:20.350 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=2474 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:24:20.350 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=2474 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:24:20.350 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=2474 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:24:20.350 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=2474 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:24:20.350 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=2475 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:24:20.350 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=2475 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:24:20.350 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=2475 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:24:20.350 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=2475 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:24:20.350 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=2475 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:24:20.350 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=2475 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:24:20.350 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=2475 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:24:20.350 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=2475 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:24:25.351 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.28.20:5700) Recv POWEROFF cmd
2026-01-29 02:24:25.351 [INFO] ctrl_if_trx.py:117 (BTS@172.18.28.20:5700) Stopping transceiver...
2026-01-29 02:24:25.353 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:24:25.354 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:24:25.355 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:24:25.355 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 02:24:25.363 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 02:24:25.364 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.28.20:5700) Recv SETFORMAT cmd
2026-01-29 02:24:25.364 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.28.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:24:25.364 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.28.20:5700) Recv SETFORMAT cmd
2026-01-29 02:24:25.364 [INFO] ctrl_if_trx.py:201 (BTS@172.18.28.20:5700) TRXD header version 1 -> 1
2026-01-29 02:24:25.366 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.28.20:5700/1) Recv RXTUNE cmd
2026-01-29 02:24:25.367 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.28.20:5700/1) Recv TXTUNE cmd
2026-01-29 02:24:25.367 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.28.20:5700/1) Recv SETFORMAT cmd
2026-01-29 02:24:25.367 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.28.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:24:25.367 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:24:25.367 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.28.20:5700/1) Recv NOMTXPOWER cmd
2026-01-29 02:24:25.367 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.28.20:5700/1) Recv SETFORMAT cmd
2026-01-29 02:24:25.367 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.28.20:5700/1) TRXD header version 1 -> 1
2026-01-29 02:24:25.369 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.28.20:5700/2) Recv RXTUNE cmd
2026-01-29 02:24:25.369 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.28.20:5700/2) Recv TXTUNE cmd
2026-01-29 02:24:25.369 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.28.20:5700/2) Recv SETFORMAT cmd
2026-01-29 02:24:25.369 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.28.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:24:25.369 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:24:25.369 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.28.20:5700/2) Recv NOMTXPOWER cmd
2026-01-29 02:24:25.370 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.28.20:5700/2) Recv SETFORMAT cmd
2026-01-29 02:24:25.370 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.28.20:5700/2) TRXD header version 1 -> 1
2026-01-29 02:24:25.372 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.28.20:5700/3) Recv RXTUNE cmd
2026-01-29 02:24:25.372 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.28.20:5700/3) Recv TXTUNE cmd
2026-01-29 02:24:25.372 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.28.20:5700/3) Recv SETFORMAT cmd
2026-01-29 02:24:25.372 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.28.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:24:25.372 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:24:25.372 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.28.20:5700/3) Recv NOMTXPOWER cmd
2026-01-29 02:24:25.372 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.28.20:5700/3) Recv SETFORMAT cmd
2026-01-29 02:24:25.372 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.28.20:5700/3) TRXD header version 1 -> 1
2026-01-29 02:24:25.375 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.28.20:5700) Recv RXTUNE cmd
2026-01-29 02:24:25.375 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETTSC
2026-01-29 02:24:25.375 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETTSC
2026-01-29 02:24:25.375 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETTSC
2026-01-29 02:24:25.375 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.28.20:5700) Recv TXTUNE cmd
2026-01-29 02:24:25.375 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETRXGAIN
2026-01-29 02:24:25.375 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETRXGAIN
2026-01-29 02:24:25.375 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETRXGAIN
2026-01-29 02:24:25.375 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETTSC
2026-01-29 02:24:25.375 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:24:25.375 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:24:25.375 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:24:25.375 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.28.20:5700) Recv NOMTXPOWER cmd
2026-01-29 02:24:25.375 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:24:25.375 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:24:25.375 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:24:25.375 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.28.20:5700) Recv POWERON CMD
2026-01-29 02:24:25.375 [INFO] ctrl_if_trx.py:109 (BTS@172.18.28.20:5700) Starting transceiver...
2026-01-29 02:24:25.376 [INFO] transceiver.py:243 Starting clock generator
2026-01-29 02:24:25.376 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-01-29 02:24:25.376 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:24:25.376 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:24:25.376 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:24:25.376 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETRXGAIN
2026-01-29 02:24:25.376 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:24:25.376 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:24:25.376 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:24:25.376 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:24:25.376 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:24:25.376 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:24:25.376 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:24:25.376 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:24:25.376 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:24:25.376 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:24:25.376 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:24:25.376 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:24:25.376 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:24:25.376 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:24:25.377 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:24:25.377 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:24:25.377 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:24:25.377 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:24:25.377 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:24:25.377 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:24:25.377 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:24:25.377 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:24:25.377 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:24:25.380 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-01-29 02:24:25.863 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-01-29 02:24:25.905 [DEBUG] fake_trx.py:278 (BTS@172.18.28.20:5700) Recv FAKE_TOA cmd
2026-01-29 02:24:25.907 [DEBUG] fake_trx.py:297 (BTS@172.18.28.20:5700) Recv FAKE_RSSI cmd
2026-01-29 02:24:25.908 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:24:25.909 [DEBUG] fake_trx.py:322 (BTS@172.18.28.20:5700) Recv FAKE_CI cmd
2026-01-29 02:24:25.911 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 02:24:25.911 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 02:24:25.912 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 02:24:25.912 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:24:25.912 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 02:24:25.912 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 02:24:25.912 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.28.22:6700) Recv POWERON CMD
2026-01-29 02:24:25.913 [INFO] ctrl_if_trx.py:109 (MS@172.18.28.22:6700) Starting transceiver...
2026-01-29 02:24:26.341 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-01-29 02:24:26.379 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 02:24:26.379 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:24:26.381 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:24:26.383 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:24:26.818 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-01-29 02:24:27.296 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-01-29 02:24:27.379 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 02:24:27.380 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:24:27.382 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:24:27.384 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:24:27.774 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-01-29 02:24:28.251 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-01-29 02:24:28.381 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 02:24:28.381 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:24:28.383 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:24:28.385 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:24:28.729 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-01-29 02:24:29.207 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-01-29 02:24:29.381 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 02:24:29.382 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:24:29.385 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:24:29.386 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:24:29.685 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-01-29 02:24:30.163 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-01-29 02:24:30.382 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 02:24:30.383 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:24:30.385 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:24:30.387 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:24:30.640 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-01-29 02:24:31.118 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-01-29 02:24:31.596 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-01-29 02:24:32.073 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-01-29 02:24:32.550 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-01-29 02:24:33.028 [DEBUG] clck_gen.py:113 IND CLOCK 1632
2026-01-29 02:24:33.506 [DEBUG] clck_gen.py:113 IND CLOCK 1734
2026-01-29 02:24:33.984 [DEBUG] clck_gen.py:113 IND CLOCK 1836
2026-01-29 02:24:34.461 [DEBUG] clck_gen.py:113 IND CLOCK 1938
2026-01-29 02:24:34.938 [DEBUG] clck_gen.py:113 IND CLOCK 2040
2026-01-29 02:24:35.416 [DEBUG] clck_gen.py:113 IND CLOCK 2142
2026-01-29 02:24:35.893 [DEBUG] clck_gen.py:113 IND CLOCK 2244
2026-01-29 02:24:36.371 [DEBUG] clck_gen.py:113 IND CLOCK 2346
2026-01-29 02:24:36.849 [DEBUG] clck_gen.py:113 IND CLOCK 2448
2026-01-29 02:24:37.327 [DEBUG] clck_gen.py:113 IND CLOCK 2550
2026-01-29 02:24:37.805 [DEBUG] clck_gen.py:113 IND CLOCK 2652
2026-01-29 02:24:38.282 [DEBUG] clck_gen.py:113 IND CLOCK 2754
2026-01-29 02:24:38.759 [DEBUG] clck_gen.py:113 IND CLOCK 2856
2026-01-29 02:24:39.237 [DEBUG] clck_gen.py:113 IND CLOCK 2958
2026-01-29 02:24:39.715 [DEBUG] clck_gen.py:113 IND CLOCK 3060
2026-01-29 02:24:40.193 [DEBUG] clck_gen.py:113 IND CLOCK 3162
2026-01-29 02:24:40.671 [DEBUG] clck_gen.py:113 IND CLOCK 3264
2026-01-29 02:24:40.959 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 02:24:40.959 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 02:24:40.963 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 02:24:40.964 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:24:40.964 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:24:40.964 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:24:40.967 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 02:24:40.967 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:24:40.967 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:24:40.967 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:24:40.967 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.28.20:5700) Recv POWEROFF cmd
2026-01-29 02:24:40.967 [INFO] ctrl_if_trx.py:117 (BTS@172.18.28.20:5700) Stopping transceiver...
2026-01-29 02:24:40.967 [INFO] transceiver.py:246 Stopping clock generator
2026-01-29 02:24:40.967 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=3329 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:24:40.967 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=3329 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:24:40.967 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=3329 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:24:40.967 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=3329 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:24:40.967 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=3329 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:24:40.967 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=3329 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:24:40.967 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=3330 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:24:40.967 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=3330 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:24:40.967 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=3330 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:24:40.967 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=3330 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:24:40.968 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=3330 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:24:40.968 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=3330 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:24:40.968 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=3330 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:24:40.968 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=3330 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:24:45.968 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.28.20:5700) Recv POWEROFF cmd
2026-01-29 02:24:45.968 [INFO] ctrl_if_trx.py:117 (BTS@172.18.28.20:5700) Stopping transceiver...
2026-01-29 02:24:45.969 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:24:45.970 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:24:45.970 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:24:45.971 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 02:24:45.978 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 02:24:45.978 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.28.20:5700) Recv SETFORMAT cmd
2026-01-29 02:24:45.979 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.28.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:24:45.979 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.28.20:5700) Recv SETFORMAT cmd
2026-01-29 02:24:45.979 [INFO] ctrl_if_trx.py:201 (BTS@172.18.28.20:5700) TRXD header version 1 -> 1
2026-01-29 02:24:45.981 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.28.20:5700/1) Recv RXTUNE cmd
2026-01-29 02:24:45.981 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.28.20:5700/1) Recv TXTUNE cmd
2026-01-29 02:24:45.981 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.28.20:5700/1) Recv SETFORMAT cmd
2026-01-29 02:24:45.982 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.28.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:24:45.982 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:24:45.982 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.28.20:5700/1) Recv NOMTXPOWER cmd
2026-01-29 02:24:45.983 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.28.20:5700/1) Recv SETFORMAT cmd
2026-01-29 02:24:45.983 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.28.20:5700/1) TRXD header version 1 -> 1
2026-01-29 02:24:45.983 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.28.20:5700/2) Recv RXTUNE cmd
2026-01-29 02:24:45.984 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.28.20:5700/2) Recv TXTUNE cmd
2026-01-29 02:24:45.984 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.28.20:5700/2) Recv SETFORMAT cmd
2026-01-29 02:24:45.984 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.28.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:24:45.984 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:24:45.984 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.28.20:5700/2) Recv NOMTXPOWER cmd
2026-01-29 02:24:45.984 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.28.20:5700/2) Recv SETFORMAT cmd
2026-01-29 02:24:45.985 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.28.20:5700/2) TRXD header version 1 -> 1
2026-01-29 02:24:45.985 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.28.20:5700/3) Recv RXTUNE cmd
2026-01-29 02:24:45.986 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.28.20:5700/3) Recv TXTUNE cmd
2026-01-29 02:24:45.986 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.28.20:5700/3) Recv SETFORMAT cmd
2026-01-29 02:24:45.986 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.28.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:24:45.986 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:24:45.986 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.28.20:5700/3) Recv NOMTXPOWER cmd
2026-01-29 02:24:45.986 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.28.20:5700/3) Recv SETFORMAT cmd
2026-01-29 02:24:45.986 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.28.20:5700/3) TRXD header version 1 -> 1
2026-01-29 02:24:45.988 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.28.20:5700) Recv RXTUNE cmd
2026-01-29 02:24:45.988 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETTSC
2026-01-29 02:24:45.988 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETTSC
2026-01-29 02:24:45.988 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETTSC
2026-01-29 02:24:45.988 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.28.20:5700) Recv TXTUNE cmd
2026-01-29 02:24:45.988 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETRXGAIN
2026-01-29 02:24:45.988 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETRXGAIN
2026-01-29 02:24:45.989 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETRXGAIN
2026-01-29 02:24:45.989 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETTSC
2026-01-29 02:24:45.989 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:24:45.989 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:24:45.989 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.28.20:5700) Recv NOMTXPOWER cmd
2026-01-29 02:24:45.989 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:24:45.989 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:24:45.989 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:24:45.989 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.28.20:5700) Recv POWERON CMD
2026-01-29 02:24:45.989 [INFO] ctrl_if_trx.py:109 (BTS@172.18.28.20:5700) Starting transceiver...
2026-01-29 02:24:45.989 [INFO] transceiver.py:243 Starting clock generator
2026-01-29 02:24:45.989 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-01-29 02:24:45.989 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:24:45.989 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:24:45.989 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:24:45.989 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETRXGAIN
2026-01-29 02:24:45.989 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:24:45.989 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:24:45.989 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:24:45.989 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:24:45.989 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:24:45.989 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:24:45.989 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:24:45.989 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:24:45.989 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:24:45.990 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:24:45.990 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:24:45.990 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:24:45.990 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:24:45.990 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:24:45.990 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:24:45.990 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:24:45.990 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:24:45.990 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:24:45.990 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:24:45.990 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:24:45.990 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:24:45.990 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:24:45.990 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:24:45.990 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:24:45.994 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-01-29 02:24:46.477 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-01-29 02:24:46.518 [DEBUG] fake_trx.py:278 (BTS@172.18.28.20:5700) Recv FAKE_TOA cmd
2026-01-29 02:24:46.520 [DEBUG] fake_trx.py:297 (BTS@172.18.28.20:5700) Recv FAKE_RSSI cmd
2026-01-29 02:24:46.521 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:24:46.522 [DEBUG] fake_trx.py:322 (BTS@172.18.28.20:5700) Recv FAKE_CI cmd
2026-01-29 02:24:46.530 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 02:24:46.530 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 02:24:46.531 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 02:24:46.531 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:24:46.531 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 02:24:46.531 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 02:24:46.532 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.28.22:6700) Recv POWERON CMD
2026-01-29 02:24:46.532 [INFO] ctrl_if_trx.py:109 (MS@172.18.28.22:6700) Starting transceiver...
2026-01-29 02:24:46.572 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 02:24:46.572 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 02:24:46.576 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 02:24:46.576 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:24:46.576 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:24:46.577 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:24:46.577 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 02:24:46.578 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:24:46.578 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:24:46.578 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.28.20:5700) Recv POWEROFF cmd
2026-01-29 02:24:46.578 [INFO] ctrl_if_trx.py:117 (BTS@172.18.28.20:5700) Stopping transceiver...
2026-01-29 02:24:46.578 [INFO] transceiver.py:246 Stopping clock generator
2026-01-29 02:24:46.578 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:24:51.579 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.28.20:5700) Recv POWEROFF cmd
2026-01-29 02:24:51.579 [INFO] ctrl_if_trx.py:117 (BTS@172.18.28.20:5700) Stopping transceiver...
2026-01-29 02:24:51.581 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:24:51.582 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:24:51.583 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:24:51.583 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 02:24:51.589 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 02:24:51.589 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.28.20:5700) Recv SETFORMAT cmd
2026-01-29 02:24:51.589 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.28.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:24:51.589 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.28.20:5700) Recv SETFORMAT cmd
2026-01-29 02:24:51.589 [INFO] ctrl_if_trx.py:201 (BTS@172.18.28.20:5700) TRXD header version 1 -> 1
2026-01-29 02:24:51.590 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.28.20:5700/1) Recv RXTUNE cmd
2026-01-29 02:24:51.590 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.28.20:5700/1) Recv TXTUNE cmd
2026-01-29 02:24:51.590 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.28.20:5700/1) Recv SETFORMAT cmd
2026-01-29 02:24:51.590 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.28.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:24:51.590 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:24:51.590 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.28.20:5700/1) Recv NOMTXPOWER cmd
2026-01-29 02:24:51.590 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.28.20:5700/1) Recv SETFORMAT cmd
2026-01-29 02:24:51.590 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.28.20:5700/1) TRXD header version 1 -> 1
2026-01-29 02:24:51.591 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.28.20:5700/2) Recv RXTUNE cmd
2026-01-29 02:24:51.591 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.28.20:5700/2) Recv TXTUNE cmd
2026-01-29 02:24:51.591 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.28.20:5700/2) Recv SETFORMAT cmd
2026-01-29 02:24:51.591 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.28.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:24:51.591 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:24:51.591 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.28.20:5700/2) Recv NOMTXPOWER cmd
2026-01-29 02:24:51.591 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.28.20:5700/2) Recv SETFORMAT cmd
2026-01-29 02:24:51.592 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.28.20:5700/2) TRXD header version 1 -> 1
2026-01-29 02:24:51.592 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.28.20:5700/3) Recv RXTUNE cmd
2026-01-29 02:24:51.592 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.28.20:5700/3) Recv TXTUNE cmd
2026-01-29 02:24:51.592 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.28.20:5700/3) Recv SETFORMAT cmd
2026-01-29 02:24:51.593 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.28.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:24:51.593 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:24:51.593 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.28.20:5700/3) Recv NOMTXPOWER cmd
2026-01-29 02:24:51.593 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.28.20:5700/3) Recv SETFORMAT cmd
2026-01-29 02:24:51.593 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.28.20:5700/3) TRXD header version 1 -> 1
2026-01-29 02:24:51.594 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.28.20:5700) Recv RXTUNE cmd
2026-01-29 02:24:51.594 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETTSC
2026-01-29 02:24:51.594 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETTSC
2026-01-29 02:24:51.594 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETTSC
2026-01-29 02:24:51.594 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.28.20:5700) Recv TXTUNE cmd
2026-01-29 02:24:51.594 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETRXGAIN
2026-01-29 02:24:51.594 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETRXGAIN
2026-01-29 02:24:51.594 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETRXGAIN
2026-01-29 02:24:51.594 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETTSC
2026-01-29 02:24:51.594 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:24:51.594 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:24:51.594 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:24:51.594 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.28.20:5700) Recv NOMTXPOWER cmd
2026-01-29 02:24:51.594 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:24:51.594 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:24:51.594 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:24:51.594 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.28.20:5700) Recv POWERON CMD
2026-01-29 02:24:51.594 [INFO] ctrl_if_trx.py:109 (BTS@172.18.28.20:5700) Starting transceiver...
2026-01-29 02:24:51.594 [INFO] transceiver.py:243 Starting clock generator
2026-01-29 02:24:51.595 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-01-29 02:24:51.595 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:24:51.595 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:24:51.595 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:24:51.595 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETRXGAIN
2026-01-29 02:24:51.595 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:24:51.595 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:24:51.595 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:24:51.595 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:24:51.595 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:24:51.595 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:24:51.595 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:24:51.595 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:24:51.595 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:24:51.595 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:24:51.595 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:24:51.595 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:24:51.595 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:24:51.595 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:24:51.595 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:24:51.595 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:24:51.595 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:24:51.595 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:24:51.595 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:24:51.596 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:24:51.596 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:24:51.596 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:24:51.596 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:24:51.599 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-01-29 02:24:52.079 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-01-29 02:24:52.119 [DEBUG] fake_trx.py:278 (BTS@172.18.28.20:5700) Recv FAKE_TOA cmd
2026-01-29 02:24:52.123 [DEBUG] fake_trx.py:297 (BTS@172.18.28.20:5700) Recv FAKE_RSSI cmd
2026-01-29 02:24:52.123 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:24:52.124 [DEBUG] fake_trx.py:322 (BTS@172.18.28.20:5700) Recv FAKE_CI cmd
2026-01-29 02:24:52.149 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 02:24:52.150 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 02:24:52.150 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 02:24:52.174 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 02:24:52.174 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 02:24:52.174 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 02:24:52.175 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:24:52.181 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:24:52.181 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 02:24:52.181 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 02:24:52.181 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.28.22:6700) Recv POWERON CMD
2026-01-29 02:24:52.181 [INFO] ctrl_if_trx.py:109 (MS@172.18.28.22:6700) Starting transceiver...
2026-01-29 02:24:52.217 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 02:24:52.217 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 02:24:52.217 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:24:52.218 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:24:52.337 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:24:52.337 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:24:52.341 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 02:24:52.341 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 02:24:52.360 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 02:24:52.360 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 02:24:52.360 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 02:24:52.366 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 02:24:52.367 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 02:24:52.367 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 02:24:52.367 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:24:52.368 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:24:52.368 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 02:24:52.368 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 02:24:52.368 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.28.22:6700) Recv POWERON CMD
2026-01-29 02:24:52.368 [INFO] ctrl_if_trx.py:109 (MS@172.18.28.22:6700) Starting transceiver...
2026-01-29 02:24:52.406 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 02:24:52.406 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 02:24:52.407 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:24:52.407 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:24:52.553 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-01-29 02:24:52.596 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:24:52.596 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:24:52.597 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 02:24:52.597 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:24:52.599 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:24:52.600 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 02:24:52.600 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 02:24:52.600 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:24:52.617 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 02:24:52.617 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 02:24:52.617 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 02:24:52.623 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 02:24:52.623 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 02:24:52.623 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 02:24:52.624 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:24:52.625 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:24:52.625 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 02:24:52.625 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 02:24:52.625 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.28.22:6700) Recv POWERON CMD
2026-01-29 02:24:52.625 [INFO] ctrl_if_trx.py:109 (MS@172.18.28.22:6700) Starting transceiver...
2026-01-29 02:24:52.639 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 02:24:52.639 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 02:24:52.640 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:24:52.640 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:24:52.942 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:24:52.943 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:24:52.946 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 02:24:52.946 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 02:24:52.957 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 02:24:52.957 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 02:24:52.957 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 02:24:52.963 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 02:24:52.963 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 02:24:52.963 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 02:24:52.963 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:24:52.965 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:24:52.965 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 02:24:52.965 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 02:24:52.965 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.28.22:6700) Recv POWERON CMD
2026-01-29 02:24:52.965 [INFO] ctrl_if_trx.py:109 (MS@172.18.28.22:6700) Starting transceiver...
2026-01-29 02:24:52.966 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 02:24:52.966 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 02:24:52.966 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:24:52.966 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:24:53.022 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-01-29 02:24:53.336 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:24:53.336 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:24:53.338 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 02:24:53.338 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 02:24:53.348 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 02:24:53.348 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:24:53.348 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:24:53.348 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:24:53.351 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 02:24:53.351 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:24:53.351 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:24:53.351 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:24:53.351 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.28.20:5700) Recv POWEROFF cmd
2026-01-29 02:24:53.351 [INFO] ctrl_if_trx.py:117 (BTS@172.18.28.20:5700) Stopping transceiver...
2026-01-29 02:24:53.351 [INFO] transceiver.py:246 Stopping clock generator
2026-01-29 02:24:53.352 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=379 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:24:53.352 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=379 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:24:53.352 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=379 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:24:53.352 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=379 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:24:53.352 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=379 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:24:53.352 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=379 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:24:53.352 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=379 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:24:53.352 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=379 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:24:58.350 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.28.20:5700) Recv POWEROFF cmd
2026-01-29 02:24:58.350 [INFO] ctrl_if_trx.py:117 (BTS@172.18.28.20:5700) Stopping transceiver...
2026-01-29 02:24:58.352 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:24:58.353 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:24:58.353 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:24:58.353 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 02:24:58.360 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 02:24:58.361 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.28.20:5700) Recv SETFORMAT cmd
2026-01-29 02:24:58.362 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.28.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:24:58.362 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.28.20:5700) Recv SETFORMAT cmd
2026-01-29 02:24:58.362 [INFO] ctrl_if_trx.py:201 (BTS@172.18.28.20:5700) TRXD header version 1 -> 1
2026-01-29 02:24:58.365 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.28.20:5700/1) Recv RXTUNE cmd
2026-01-29 02:24:58.365 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.28.20:5700/1) Recv TXTUNE cmd
2026-01-29 02:24:58.365 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.28.20:5700/1) Recv SETFORMAT cmd
2026-01-29 02:24:58.365 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.28.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:24:58.366 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:24:58.366 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.28.20:5700/1) Recv NOMTXPOWER cmd
2026-01-29 02:24:58.366 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.28.20:5700/1) Recv SETFORMAT cmd
2026-01-29 02:24:58.366 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.28.20:5700/1) TRXD header version 1 -> 1
2026-01-29 02:24:58.368 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.28.20:5700/2) Recv RXTUNE cmd
2026-01-29 02:24:58.368 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.28.20:5700/2) Recv TXTUNE cmd
2026-01-29 02:24:58.368 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.28.20:5700/2) Recv SETFORMAT cmd
2026-01-29 02:24:58.368 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.28.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:24:58.368 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:24:58.368 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.28.20:5700/2) Recv NOMTXPOWER cmd
2026-01-29 02:24:58.369 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.28.20:5700/2) Recv SETFORMAT cmd
2026-01-29 02:24:58.369 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.28.20:5700/2) TRXD header version 1 -> 1
2026-01-29 02:24:58.370 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.28.20:5700/3) Recv RXTUNE cmd
2026-01-29 02:24:58.371 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.28.20:5700/3) Recv TXTUNE cmd
2026-01-29 02:24:58.371 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.28.20:5700/3) Recv SETFORMAT cmd
2026-01-29 02:24:58.371 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.28.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:24:58.371 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:24:58.371 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.28.20:5700/3) Recv NOMTXPOWER cmd
2026-01-29 02:24:58.371 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.28.20:5700/3) Recv SETFORMAT cmd
2026-01-29 02:24:58.371 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.28.20:5700/3) TRXD header version 1 -> 1
2026-01-29 02:24:58.374 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.28.20:5700) Recv RXTUNE cmd
2026-01-29 02:24:58.374 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETTSC
2026-01-29 02:24:58.374 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETTSC
2026-01-29 02:24:58.374 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETTSC
2026-01-29 02:24:58.374 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.28.20:5700) Recv TXTUNE cmd
2026-01-29 02:24:58.374 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETRXGAIN
2026-01-29 02:24:58.374 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETRXGAIN
2026-01-29 02:24:58.374 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETRXGAIN
2026-01-29 02:24:58.374 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETTSC
2026-01-29 02:24:58.374 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:24:58.374 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:24:58.374 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:24:58.374 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.28.20:5700) Recv NOMTXPOWER cmd
2026-01-29 02:24:58.374 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:24:58.374 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:24:58.374 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:24:58.374 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.28.20:5700) Recv POWERON CMD
2026-01-29 02:24:58.374 [INFO] ctrl_if_trx.py:109 (BTS@172.18.28.20:5700) Starting transceiver...
2026-01-29 02:24:58.374 [INFO] transceiver.py:243 Starting clock generator
2026-01-29 02:24:58.374 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-01-29 02:24:58.374 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:24:58.375 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:24:58.375 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:24:58.375 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETRXGAIN
2026-01-29 02:24:58.375 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:24:58.375 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:24:58.375 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:24:58.375 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:24:58.375 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:24:58.375 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:24:58.375 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:24:58.375 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:24:58.375 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:24:58.375 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:24:58.375 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:24:58.375 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:24:58.375 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:24:58.375 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:24:58.375 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:24:58.375 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:24:58.375 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:24:58.375 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:24:58.375 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:24:58.375 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:24:58.375 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:24:58.376 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:24:58.376 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:24:58.379 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-01-29 02:24:58.857 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-01-29 02:24:58.902 [DEBUG] fake_trx.py:278 (BTS@172.18.28.20:5700) Recv FAKE_TOA cmd
2026-01-29 02:24:58.904 [DEBUG] fake_trx.py:297 (BTS@172.18.28.20:5700) Recv FAKE_RSSI cmd
2026-01-29 02:24:58.906 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:24:58.906 [DEBUG] fake_trx.py:322 (BTS@172.18.28.20:5700) Recv FAKE_CI cmd
2026-01-29 02:24:58.931 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 02:24:58.931 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 02:24:58.931 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 02:24:58.950 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 02:24:58.950 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 02:24:58.951 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 02:24:58.952 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:24:58.956 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:24:58.956 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 02:24:58.956 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 02:24:58.956 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.28.22:6700) Recv POWERON CMD
2026-01-29 02:24:58.956 [INFO] ctrl_if_trx.py:109 (MS@172.18.28.22:6700) Starting transceiver...
2026-01-29 02:24:58.995 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 02:24:58.996 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 02:24:58.996 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:24:58.996 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:24:59.334 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-01-29 02:24:59.379 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:24:59.379 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 02:24:59.379 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:24:59.383 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:24:59.812 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-01-29 02:25:00.290 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-01-29 02:25:00.379 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:25:00.380 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 02:25:00.380 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:25:00.384 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:25:00.768 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-01-29 02:25:01.246 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-01-29 02:25:01.380 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 02:25:01.380 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:25:01.381 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:25:01.385 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:25:01.720 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-01-29 02:25:02.198 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-01-29 02:25:02.382 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:25:02.382 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:25:02.382 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 02:25:02.385 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:25:02.676 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-01-29 02:25:03.154 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-01-29 02:25:03.383 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 02:25:03.383 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:25:03.383 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:25:03.386 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:25:03.631 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-01-29 02:25:04.000 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:25:04.001 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:25:04.005 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 02:25:04.005 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 02:25:04.023 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 02:25:04.023 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 02:25:04.023 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 02:25:04.030 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 02:25:04.030 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 02:25:04.030 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 02:25:04.030 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:25:04.031 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:25:04.031 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 02:25:04.032 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 02:25:04.032 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.28.22:6700) Recv POWERON CMD
2026-01-29 02:25:04.032 [INFO] ctrl_if_trx.py:109 (MS@172.18.28.22:6700) Starting transceiver...
2026-01-29 02:25:04.049 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 02:25:04.049 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 02:25:04.049 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:25:04.049 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:25:04.108 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-01-29 02:25:04.585 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-01-29 02:25:05.063 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-01-29 02:25:05.542 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-01-29 02:25:06.020 [DEBUG] clck_gen.py:113 IND CLOCK 1632
2026-01-29 02:25:06.498 [DEBUG] clck_gen.py:113 IND CLOCK 1734
2026-01-29 02:25:06.973 [DEBUG] clck_gen.py:113 IND CLOCK 1836
2026-01-29 02:25:07.451 [DEBUG] clck_gen.py:113 IND CLOCK 1938
2026-01-29 02:25:07.929 [DEBUG] clck_gen.py:113 IND CLOCK 2040
2026-01-29 02:25:08.405 [DEBUG] clck_gen.py:113 IND CLOCK 2142
2026-01-29 02:25:08.884 [DEBUG] clck_gen.py:113 IND CLOCK 2244
2026-01-29 02:25:09.052 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:25:09.053 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:25:09.057 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 02:25:09.057 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 02:25:09.076 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 02:25:09.076 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 02:25:09.076 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 02:25:09.082 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 02:25:09.082 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 02:25:09.082 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 02:25:09.082 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:25:09.083 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:25:09.083 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 02:25:09.083 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 02:25:09.083 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.28.22:6700) Recv POWERON CMD
2026-01-29 02:25:09.083 [INFO] ctrl_if_trx.py:109 (MS@172.18.28.22:6700) Starting transceiver...
2026-01-29 02:25:09.118 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 02:25:09.119 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 02:25:09.119 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:25:09.119 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:25:09.360 [DEBUG] clck_gen.py:113 IND CLOCK 2346
2026-01-29 02:25:09.838 [DEBUG] clck_gen.py:113 IND CLOCK 2448
2026-01-29 02:25:10.315 [DEBUG] clck_gen.py:113 IND CLOCK 2550
2026-01-29 02:25:10.792 [DEBUG] clck_gen.py:113 IND CLOCK 2652
2026-01-29 02:25:11.269 [DEBUG] clck_gen.py:113 IND CLOCK 2754
2026-01-29 02:25:11.747 [DEBUG] clck_gen.py:113 IND CLOCK 2856
2026-01-29 02:25:12.226 [DEBUG] clck_gen.py:113 IND CLOCK 2958
2026-01-29 02:25:12.704 [DEBUG] clck_gen.py:113 IND CLOCK 3060
2026-01-29 02:25:13.181 [DEBUG] clck_gen.py:113 IND CLOCK 3162
2026-01-29 02:25:13.659 [DEBUG] clck_gen.py:113 IND CLOCK 3264
2026-01-29 02:25:14.123 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:25:14.124 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:25:14.128 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 02:25:14.128 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 02:25:14.136 [DEBUG] clck_gen.py:113 IND CLOCK 3366
2026-01-29 02:25:14.148 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 02:25:14.148 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 02:25:14.148 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 02:25:14.154 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 02:25:14.154 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 02:25:14.154 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 02:25:14.154 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:25:14.156 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:25:14.156 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 02:25:14.156 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 02:25:14.156 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.28.22:6700) Recv POWERON CMD
2026-01-29 02:25:14.156 [INFO] ctrl_if_trx.py:109 (MS@172.18.28.22:6700) Starting transceiver...
2026-01-29 02:25:14.182 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 02:25:14.182 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 02:25:14.182 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:25:14.182 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:25:14.609 [DEBUG] clck_gen.py:113 IND CLOCK 3468
2026-01-29 02:25:15.087 [DEBUG] clck_gen.py:113 IND CLOCK 3570
2026-01-29 02:25:15.566 [DEBUG] clck_gen.py:113 IND CLOCK 3672
2026-01-29 02:25:16.044 [DEBUG] clck_gen.py:113 IND CLOCK 3774
2026-01-29 02:25:16.522 [DEBUG] clck_gen.py:113 IND CLOCK 3876
2026-01-29 02:25:17.000 [DEBUG] clck_gen.py:113 IND CLOCK 3978
2026-01-29 02:25:17.474 [DEBUG] clck_gen.py:113 IND CLOCK 4080
2026-01-29 02:25:17.951 [DEBUG] clck_gen.py:113 IND CLOCK 4182
2026-01-29 02:25:18.429 [DEBUG] clck_gen.py:113 IND CLOCK 4284
2026-01-29 02:25:18.907 [DEBUG] clck_gen.py:113 IND CLOCK 4386
2026-01-29 02:25:19.188 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:25:19.188 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:25:19.193 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 02:25:19.193 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 02:25:19.207 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 02:25:19.207 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:25:19.207 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:25:19.208 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:25:19.213 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 02:25:19.213 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:25:19.214 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:25:19.214 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:25:19.214 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.28.20:5700) Recv POWEROFF cmd
2026-01-29 02:25:19.214 [INFO] ctrl_if_trx.py:117 (BTS@172.18.28.20:5700) Stopping transceiver...
2026-01-29 02:25:19.214 [INFO] transceiver.py:246 Stopping clock generator
2026-01-29 02:25:19.214 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=4452 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:25:19.215 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=4452 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:25:24.211 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.28.20:5700) Recv POWEROFF cmd
2026-01-29 02:25:24.211 [INFO] ctrl_if_trx.py:117 (BTS@172.18.28.20:5700) Stopping transceiver...
2026-01-29 02:25:24.213 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:25:24.214 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:25:24.215 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:25:24.216 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 02:25:24.224 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 02:25:24.226 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.28.20:5700) Recv SETFORMAT cmd
2026-01-29 02:25:24.226 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.28.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:25:24.227 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.28.20:5700) Recv SETFORMAT cmd
2026-01-29 02:25:24.227 [INFO] ctrl_if_trx.py:201 (BTS@172.18.28.20:5700) TRXD header version 1 -> 1
2026-01-29 02:25:24.231 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.28.20:5700/1) Recv RXTUNE cmd
2026-01-29 02:25:24.231 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.28.20:5700/1) Recv TXTUNE cmd
2026-01-29 02:25:24.232 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.28.20:5700/1) Recv SETFORMAT cmd
2026-01-29 02:25:24.232 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.28.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:25:24.232 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:25:24.233 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.28.20:5700/1) Recv NOMTXPOWER cmd
2026-01-29 02:25:24.233 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.28.20:5700/1) Recv SETFORMAT cmd
2026-01-29 02:25:24.233 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.28.20:5700/1) TRXD header version 1 -> 1
2026-01-29 02:25:24.234 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.28.20:5700/2) Recv RXTUNE cmd
2026-01-29 02:25:24.235 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.28.20:5700/2) Recv TXTUNE cmd
2026-01-29 02:25:24.235 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.28.20:5700/2) Recv SETFORMAT cmd
2026-01-29 02:25:24.235 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.28.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:25:24.235 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:25:24.235 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.28.20:5700/2) Recv NOMTXPOWER cmd
2026-01-29 02:25:24.235 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.28.20:5700/2) Recv SETFORMAT cmd
2026-01-29 02:25:24.235 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.28.20:5700/2) TRXD header version 1 -> 1
2026-01-29 02:25:24.237 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.28.20:5700/3) Recv RXTUNE cmd
2026-01-29 02:25:24.237 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.28.20:5700/3) Recv TXTUNE cmd
2026-01-29 02:25:24.237 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.28.20:5700/3) Recv SETFORMAT cmd
2026-01-29 02:25:24.237 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.28.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:25:24.237 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:25:24.237 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.28.20:5700/3) Recv NOMTXPOWER cmd
2026-01-29 02:25:24.237 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.28.20:5700/3) Recv SETFORMAT cmd
2026-01-29 02:25:24.237 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.28.20:5700/3) TRXD header version 1 -> 1
2026-01-29 02:25:24.240 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.28.20:5700) Recv RXTUNE cmd
2026-01-29 02:25:24.240 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETTSC
2026-01-29 02:25:24.240 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETTSC
2026-01-29 02:25:24.240 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETTSC
2026-01-29 02:25:24.240 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.28.20:5700) Recv TXTUNE cmd
2026-01-29 02:25:24.240 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETRXGAIN
2026-01-29 02:25:24.240 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETRXGAIN
2026-01-29 02:25:24.240 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETRXGAIN
2026-01-29 02:25:24.240 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETTSC
2026-01-29 02:25:24.240 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:25:24.240 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:25:24.240 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:25:24.240 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.28.20:5700) Recv NOMTXPOWER cmd
2026-01-29 02:25:24.241 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:25:24.241 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:25:24.241 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:25:24.241 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.28.20:5700) Recv POWERON CMD
2026-01-29 02:25:24.241 [INFO] ctrl_if_trx.py:109 (BTS@172.18.28.20:5700) Starting transceiver...
2026-01-29 02:25:24.241 [INFO] transceiver.py:243 Starting clock generator
2026-01-29 02:25:24.241 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-01-29 02:25:24.241 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:25:24.241 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:25:24.241 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:25:24.241 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETRXGAIN
2026-01-29 02:25:24.241 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:25:24.241 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:25:24.241 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:25:24.241 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:25:24.241 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:25:24.241 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:25:24.241 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:25:24.241 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:25:24.241 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:25:24.241 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:25:24.241 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:25:24.242 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:25:24.242 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:25:24.242 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:25:24.242 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:25:24.242 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:25:24.242 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:25:24.242 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:25:24.242 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:25:24.242 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:25:24.242 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:25:24.242 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:25:24.242 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:25:24.246 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-01-29 02:25:24.725 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-01-29 02:25:24.766 [DEBUG] fake_trx.py:278 (BTS@172.18.28.20:5700) Recv FAKE_TOA cmd
2026-01-29 02:25:24.767 [DEBUG] fake_trx.py:297 (BTS@172.18.28.20:5700) Recv FAKE_RSSI cmd
2026-01-29 02:25:24.769 [DEBUG] fake_trx.py:322 (BTS@172.18.28.20:5700) Recv FAKE_CI cmd
2026-01-29 02:25:24.770 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:25:24.790 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 02:25:24.790 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 02:25:24.790 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 02:25:24.808 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 02:25:24.808 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 02:25:24.808 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 02:25:24.809 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:25:24.813 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:25:24.813 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 02:25:24.813 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 02:25:24.813 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.28.22:6700) Recv POWERON CMD
2026-01-29 02:25:24.813 [INFO] ctrl_if_trx.py:109 (MS@172.18.28.22:6700) Starting transceiver...
2026-01-29 02:25:24.815 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 02:25:24.815 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 02:25:24.815 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:25:24.815 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:25:25.202 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-01-29 02:25:25.244 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 02:25:25.245 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:25:25.246 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:25:25.250 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:25:25.680 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-01-29 02:25:26.158 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-01-29 02:25:26.245 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 02:25:26.246 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:25:26.247 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:25:26.250 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:25:26.637 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-01-29 02:25:27.114 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-01-29 02:25:27.246 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 02:25:27.247 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:25:27.248 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:25:27.251 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:25:27.593 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-01-29 02:25:28.067 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-01-29 02:25:28.247 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 02:25:28.248 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:25:28.249 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:25:28.252 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:25:28.545 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-01-29 02:25:29.023 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-01-29 02:25:29.248 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 02:25:29.249 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:25:29.250 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:25:29.253 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:25:29.501 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-01-29 02:25:29.818 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:25:29.818 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:25:29.822 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 02:25:29.822 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 02:25:29.842 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 02:25:29.842 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 02:25:29.842 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 02:25:29.848 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 02:25:29.848 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 02:25:29.848 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 02:25:29.849 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:25:29.850 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:25:29.850 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 02:25:29.850 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 02:25:29.850 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.28.22:6700) Recv POWERON CMD
2026-01-29 02:25:29.850 [INFO] ctrl_if_trx.py:109 (MS@172.18.28.22:6700) Starting transceiver...
2026-01-29 02:25:29.874 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 02:25:29.874 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 02:25:29.874 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:25:29.874 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:25:29.978 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-01-29 02:25:30.455 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-01-29 02:25:30.934 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-01-29 02:25:31.412 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-01-29 02:25:31.890 [DEBUG] clck_gen.py:113 IND CLOCK 1632
2026-01-29 02:25:32.367 [DEBUG] clck_gen.py:113 IND CLOCK 1734
2026-01-29 02:25:32.844 [DEBUG] clck_gen.py:113 IND CLOCK 1836
2026-01-29 02:25:33.321 [DEBUG] clck_gen.py:113 IND CLOCK 1938
2026-01-29 02:25:33.800 [DEBUG] clck_gen.py:113 IND CLOCK 2040
2026-01-29 02:25:34.277 [DEBUG] clck_gen.py:113 IND CLOCK 2142
2026-01-29 02:25:34.756 [DEBUG] clck_gen.py:113 IND CLOCK 2244
2026-01-29 02:25:34.879 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:25:34.879 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:25:34.882 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 02:25:34.882 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 02:25:34.900 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 02:25:34.900 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 02:25:34.900 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 02:25:34.905 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 02:25:34.905 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 02:25:34.906 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 02:25:34.906 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:25:34.907 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:25:34.907 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 02:25:34.907 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 02:25:34.907 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.28.22:6700) Recv POWERON CMD
2026-01-29 02:25:34.907 [INFO] ctrl_if_trx.py:109 (MS@172.18.28.22:6700) Starting transceiver...
2026-01-29 02:25:34.938 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 02:25:34.938 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 02:25:34.939 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:25:34.939 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:25:35.233 [DEBUG] clck_gen.py:113 IND CLOCK 2346
2026-01-29 02:25:35.710 [DEBUG] clck_gen.py:113 IND CLOCK 2448
2026-01-29 02:25:36.188 [DEBUG] clck_gen.py:113 IND CLOCK 2550
2026-01-29 02:25:36.666 [DEBUG] clck_gen.py:113 IND CLOCK 2652
2026-01-29 02:25:37.144 [DEBUG] clck_gen.py:113 IND CLOCK 2754
2026-01-29 02:25:37.623 [DEBUG] clck_gen.py:113 IND CLOCK 2856
2026-01-29 02:25:38.100 [DEBUG] clck_gen.py:113 IND CLOCK 2958
2026-01-29 02:25:38.578 [DEBUG] clck_gen.py:113 IND CLOCK 3060
2026-01-29 02:25:39.056 [DEBUG] clck_gen.py:113 IND CLOCK 3162
2026-01-29 02:25:39.533 [DEBUG] clck_gen.py:113 IND CLOCK 3264
2026-01-29 02:25:39.942 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:25:39.942 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:25:39.946 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 02:25:39.946 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 02:25:39.964 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 02:25:39.964 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 02:25:39.964 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 02:25:39.969 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 02:25:39.969 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 02:25:39.969 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 02:25:39.970 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:25:39.971 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:25:39.971 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 02:25:39.971 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 02:25:39.971 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.28.22:6700) Recv POWERON CMD
2026-01-29 02:25:39.971 [INFO] ctrl_if_trx.py:109 (MS@172.18.28.22:6700) Starting transceiver...
2026-01-29 02:25:40.003 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 02:25:40.003 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 02:25:40.003 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:25:40.003 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:25:40.010 [DEBUG] clck_gen.py:113 IND CLOCK 3366
2026-01-29 02:25:40.487 [DEBUG] clck_gen.py:113 IND CLOCK 3468
2026-01-29 02:25:40.965 [DEBUG] clck_gen.py:113 IND CLOCK 3570
2026-01-29 02:25:41.443 [DEBUG] clck_gen.py:113 IND CLOCK 3672
2026-01-29 02:25:41.921 [DEBUG] clck_gen.py:113 IND CLOCK 3774
2026-01-29 02:25:42.399 [DEBUG] clck_gen.py:113 IND CLOCK 3876
2026-01-29 02:25:42.877 [DEBUG] clck_gen.py:113 IND CLOCK 3978
2026-01-29 02:25:43.356 [DEBUG] clck_gen.py:113 IND CLOCK 4080
2026-01-29 02:25:43.833 [DEBUG] clck_gen.py:113 IND CLOCK 4182
2026-01-29 02:25:44.311 [DEBUG] clck_gen.py:113 IND CLOCK 4284
2026-01-29 02:25:44.790 [DEBUG] clck_gen.py:113 IND CLOCK 4386
2026-01-29 02:25:45.007 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:25:45.008 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:25:45.013 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 02:25:45.013 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 02:25:45.027 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 02:25:45.027 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:25:45.027 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:25:45.027 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:25:45.028 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 02:25:45.028 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:25:45.028 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:25:45.028 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.28.20:5700) Recv POWEROFF cmd
2026-01-29 02:25:45.028 [INFO] ctrl_if_trx.py:117 (BTS@172.18.28.20:5700) Stopping transceiver...
2026-01-29 02:25:45.028 [INFO] transceiver.py:246 Stopping clock generator
2026-01-29 02:25:45.028 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:25:50.028 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.28.20:5700) Recv POWEROFF cmd
2026-01-29 02:25:50.028 [INFO] ctrl_if_trx.py:117 (BTS@172.18.28.20:5700) Stopping transceiver...
2026-01-29 02:25:50.030 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:25:50.031 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:25:50.032 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:25:50.032 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 02:25:50.036 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 02:25:50.036 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.28.20:5700) Recv SETFORMAT cmd
2026-01-29 02:25:50.036 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.28.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:25:50.037 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.28.20:5700) Recv SETFORMAT cmd
2026-01-29 02:25:50.037 [INFO] ctrl_if_trx.py:201 (BTS@172.18.28.20:5700) TRXD header version 1 -> 1
2026-01-29 02:25:50.038 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.28.20:5700/1) Recv RXTUNE cmd
2026-01-29 02:25:50.039 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.28.20:5700/1) Recv TXTUNE cmd
2026-01-29 02:25:50.039 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.28.20:5700/1) Recv SETFORMAT cmd
2026-01-29 02:25:50.039 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.28.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:25:50.039 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:25:50.039 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.28.20:5700/1) Recv NOMTXPOWER cmd
2026-01-29 02:25:50.039 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.28.20:5700/1) Recv SETFORMAT cmd
2026-01-29 02:25:50.039 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.28.20:5700/1) TRXD header version 1 -> 1
2026-01-29 02:25:50.040 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.28.20:5700/2) Recv RXTUNE cmd
2026-01-29 02:25:50.040 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.28.20:5700/2) Recv TXTUNE cmd
2026-01-29 02:25:50.040 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.28.20:5700/2) Recv SETFORMAT cmd
2026-01-29 02:25:50.040 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.28.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:25:50.040 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:25:50.041 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.28.20:5700/2) Recv NOMTXPOWER cmd
2026-01-29 02:25:50.041 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.28.20:5700/2) Recv SETFORMAT cmd
2026-01-29 02:25:50.041 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.28.20:5700/2) TRXD header version 1 -> 1
2026-01-29 02:25:50.042 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.28.20:5700/3) Recv RXTUNE cmd
2026-01-29 02:25:50.042 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.28.20:5700/3) Recv TXTUNE cmd
2026-01-29 02:25:50.042 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.28.20:5700/3) Recv SETFORMAT cmd
2026-01-29 02:25:50.042 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.28.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:25:50.042 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:25:50.042 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.28.20:5700/3) Recv NOMTXPOWER cmd
2026-01-29 02:25:50.042 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.28.20:5700/3) Recv SETFORMAT cmd
2026-01-29 02:25:50.042 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.28.20:5700/3) TRXD header version 1 -> 1
2026-01-29 02:25:50.046 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.28.20:5700) Recv RXTUNE cmd
2026-01-29 02:25:50.046 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETTSC
2026-01-29 02:25:50.046 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETTSC
2026-01-29 02:25:50.046 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.28.20:5700) Recv TXTUNE cmd
2026-01-29 02:25:50.046 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETTSC
2026-01-29 02:25:50.047 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETRXGAIN
2026-01-29 02:25:50.047 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETRXGAIN
2026-01-29 02:25:50.047 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETTSC
2026-01-29 02:25:50.047 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETRXGAIN
2026-01-29 02:25:50.047 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.28.20:5700) Recv NOMTXPOWER cmd
2026-01-29 02:25:50.047 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:25:50.047 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:25:50.047 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.28.20:5700) Recv POWERON CMD
2026-01-29 02:25:50.047 [INFO] ctrl_if_trx.py:109 (BTS@172.18.28.20:5700) Starting transceiver...
2026-01-29 02:25:50.047 [INFO] transceiver.py:243 Starting clock generator
2026-01-29 02:25:50.047 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-01-29 02:25:50.047 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:25:50.047 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:25:50.047 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:25:50.047 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETRXGAIN
2026-01-29 02:25:50.047 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:25:50.047 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:25:50.047 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:25:50.047 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:25:50.047 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:25:50.047 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:25:50.047 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:25:50.047 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:25:50.047 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:25:50.047 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:25:50.047 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:25:50.047 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:25:50.047 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:25:50.047 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:25:50.048 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:25:50.048 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:25:50.048 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:25:50.048 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:25:50.048 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:25:50.048 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:25:50.048 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:25:50.048 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:25:50.048 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:25:50.048 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:25:50.048 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:25:50.048 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:25:50.048 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:25:50.052 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-01-29 02:25:50.531 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-01-29 02:25:50.561 [DEBUG] fake_trx.py:278 (BTS@172.18.28.20:5700) Recv FAKE_TOA cmd
2026-01-29 02:25:50.561 [DEBUG] fake_trx.py:297 (BTS@172.18.28.20:5700) Recv FAKE_RSSI cmd
2026-01-29 02:25:50.562 [DEBUG] fake_trx.py:322 (BTS@172.18.28.20:5700) Recv FAKE_CI cmd
2026-01-29 02:25:50.562 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:25:50.572 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 02:25:50.572 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 02:25:50.572 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 02:25:50.587 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 02:25:50.587 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 02:25:50.587 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 02:25:50.588 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:25:50.592 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:25:50.593 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 02:25:50.593 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 02:25:50.593 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.28.22:6700) Recv POWERON CMD
2026-01-29 02:25:50.593 [INFO] ctrl_if_trx.py:109 (MS@172.18.28.22:6700) Starting transceiver...
2026-01-29 02:25:50.622 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 02:25:50.623 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 02:25:50.623 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:25:50.623 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:25:51.005 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-01-29 02:25:51.049 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 02:25:51.050 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:25:51.051 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:25:51.053 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:25:51.483 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-01-29 02:25:51.960 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-01-29 02:25:52.051 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 02:25:52.051 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:25:52.052 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:25:52.054 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:25:52.435 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-01-29 02:25:52.913 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-01-29 02:25:53.052 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 02:25:53.052 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:25:53.053 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:25:53.054 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:25:53.390 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-01-29 02:25:53.868 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-01-29 02:25:54.052 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:25:54.053 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 02:25:54.054 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:25:54.056 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:25:54.345 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-01-29 02:25:54.823 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-01-29 02:25:55.055 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 02:25:55.055 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:25:55.055 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:25:55.056 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:25:55.301 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-01-29 02:25:55.628 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:25:55.629 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:25:55.632 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 02:25:55.632 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 02:25:55.649 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 02:25:55.649 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 02:25:55.649 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 02:25:55.655 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 02:25:55.655 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 02:25:55.655 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 02:25:55.656 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:25:55.657 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:25:55.657 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 02:25:55.657 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 02:25:55.657 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.28.22:6700) Recv POWERON CMD
2026-01-29 02:25:55.657 [INFO] ctrl_if_trx.py:109 (MS@172.18.28.22:6700) Starting transceiver...
2026-01-29 02:25:55.673 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 02:25:55.673 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 02:25:55.674 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:25:55.674 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:25:55.778 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-01-29 02:25:56.256 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-01-29 02:25:56.734 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-01-29 02:25:57.212 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-01-29 02:25:57.690 [DEBUG] clck_gen.py:113 IND CLOCK 1632
2026-01-29 02:25:58.168 [DEBUG] clck_gen.py:113 IND CLOCK 1734
2026-01-29 02:25:58.646 [DEBUG] clck_gen.py:113 IND CLOCK 1836
2026-01-29 02:25:59.125 [DEBUG] clck_gen.py:113 IND CLOCK 1938
2026-01-29 02:25:59.603 [DEBUG] clck_gen.py:113 IND CLOCK 2040
2026-01-29 02:26:00.082 [DEBUG] clck_gen.py:113 IND CLOCK 2142
2026-01-29 02:26:00.559 [DEBUG] clck_gen.py:113 IND CLOCK 2244
2026-01-29 02:26:00.676 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:26:00.676 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:26:00.677 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 02:26:00.677 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 02:26:00.684 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 02:26:00.684 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 02:26:00.684 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 02:26:00.690 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 02:26:00.690 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 02:26:00.690 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 02:26:00.691 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:26:00.692 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:26:00.692 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 02:26:00.692 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 02:26:00.692 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.28.22:6700) Recv POWERON CMD
2026-01-29 02:26:00.692 [INFO] ctrl_if_trx.py:109 (MS@172.18.28.22:6700) Starting transceiver...
2026-01-29 02:26:00.694 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 02:26:00.694 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 02:26:00.694 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:26:00.694 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:26:01.032 [DEBUG] clck_gen.py:113 IND CLOCK 2346
2026-01-29 02:26:01.510 [DEBUG] clck_gen.py:113 IND CLOCK 2448
2026-01-29 02:26:01.987 [DEBUG] clck_gen.py:113 IND CLOCK 2550
2026-01-29 02:26:02.465 [DEBUG] clck_gen.py:113 IND CLOCK 2652
2026-01-29 02:26:02.944 [DEBUG] clck_gen.py:113 IND CLOCK 2754
2026-01-29 02:26:03.422 [DEBUG] clck_gen.py:113 IND CLOCK 2856
2026-01-29 02:26:03.899 [DEBUG] clck_gen.py:113 IND CLOCK 2958
2026-01-29 02:26:04.377 [DEBUG] clck_gen.py:113 IND CLOCK 3060
2026-01-29 02:26:04.855 [DEBUG] clck_gen.py:113 IND CLOCK 3162
2026-01-29 02:26:05.333 [DEBUG] clck_gen.py:113 IND CLOCK 3264
2026-01-29 02:26:05.697 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:26:05.698 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:26:05.702 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 02:26:05.702 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 02:26:05.719 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 02:26:05.719 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 02:26:05.719 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 02:26:05.724 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 02:26:05.725 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 02:26:05.725 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 02:26:05.725 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:26:05.726 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:26:05.726 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 02:26:05.727 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 02:26:05.727 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.28.22:6700) Recv POWERON CMD
2026-01-29 02:26:05.727 [INFO] ctrl_if_trx.py:109 (MS@172.18.28.22:6700) Starting transceiver...
2026-01-29 02:26:05.752 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 02:26:05.752 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 02:26:05.752 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:26:05.752 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:26:05.810 [DEBUG] clck_gen.py:113 IND CLOCK 3366
2026-01-29 02:26:06.288 [DEBUG] clck_gen.py:113 IND CLOCK 3468
2026-01-29 02:26:06.766 [DEBUG] clck_gen.py:113 IND CLOCK 3570
2026-01-29 02:26:07.244 [DEBUG] clck_gen.py:113 IND CLOCK 3672
2026-01-29 02:26:07.721 [DEBUG] clck_gen.py:113 IND CLOCK 3774
2026-01-29 02:26:08.199 [DEBUG] clck_gen.py:113 IND CLOCK 3876
2026-01-29 02:26:08.676 [DEBUG] clck_gen.py:113 IND CLOCK 3978
2026-01-29 02:26:09.154 [DEBUG] clck_gen.py:113 IND CLOCK 4080
2026-01-29 02:26:09.632 [DEBUG] clck_gen.py:113 IND CLOCK 4182
2026-01-29 02:26:10.110 [DEBUG] clck_gen.py:113 IND CLOCK 4284
2026-01-29 02:26:10.587 [DEBUG] clck_gen.py:113 IND CLOCK 4386
2026-01-29 02:26:10.756 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:26:10.757 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:26:10.760 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 02:26:10.761 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 02:26:10.773 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 02:26:10.774 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:26:10.774 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:26:10.774 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:26:10.780 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 02:26:10.780 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:26:10.780 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:26:10.780 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.28.20:5700) Recv POWEROFF cmd
2026-01-29 02:26:10.780 [INFO] ctrl_if_trx.py:117 (BTS@172.18.28.20:5700) Stopping transceiver...
2026-01-29 02:26:10.781 [INFO] transceiver.py:246 Stopping clock generator
2026-01-29 02:26:10.781 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:26:10.781 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=4428 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:26:10.781 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=4428 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:26:10.781 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=4428 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:26:10.781 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=4428 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:26:10.781 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=4428 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:26:10.782 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=4428 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:26:10.782 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=4428 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:26:15.778 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.28.20:5700) Recv POWEROFF cmd
2026-01-29 02:26:15.778 [INFO] ctrl_if_trx.py:117 (BTS@172.18.28.20:5700) Stopping transceiver...
2026-01-29 02:26:15.779 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:26:15.781 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:26:15.783 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:26:15.786 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 02:26:15.793 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 02:26:15.793 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.28.20:5700) Recv SETFORMAT cmd
2026-01-29 02:26:15.793 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.28.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:26:15.793 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.28.20:5700) Recv SETFORMAT cmd
2026-01-29 02:26:15.793 [INFO] ctrl_if_trx.py:201 (BTS@172.18.28.20:5700) TRXD header version 1 -> 1
2026-01-29 02:26:15.794 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.28.20:5700/1) Recv RXTUNE cmd
2026-01-29 02:26:15.794 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.28.20:5700/1) Recv TXTUNE cmd
2026-01-29 02:26:15.794 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.28.20:5700/1) Recv SETFORMAT cmd
2026-01-29 02:26:15.794 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.28.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:26:15.794 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:26:15.794 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.28.20:5700/1) Recv NOMTXPOWER cmd
2026-01-29 02:26:15.794 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.28.20:5700/1) Recv SETFORMAT cmd
2026-01-29 02:26:15.794 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.28.20:5700/1) TRXD header version 1 -> 1
2026-01-29 02:26:15.795 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.28.20:5700/2) Recv RXTUNE cmd
2026-01-29 02:26:15.795 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.28.20:5700/2) Recv TXTUNE cmd
2026-01-29 02:26:15.795 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.28.20:5700/2) Recv SETFORMAT cmd
2026-01-29 02:26:15.795 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.28.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:26:15.795 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:26:15.795 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.28.20:5700/2) Recv NOMTXPOWER cmd
2026-01-29 02:26:15.795 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.28.20:5700/2) Recv SETFORMAT cmd
2026-01-29 02:26:15.795 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.28.20:5700/2) TRXD header version 1 -> 1
2026-01-29 02:26:15.796 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.28.20:5700/3) Recv RXTUNE cmd
2026-01-29 02:26:15.796 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.28.20:5700/3) Recv TXTUNE cmd
2026-01-29 02:26:15.796 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.28.20:5700/3) Recv SETFORMAT cmd
2026-01-29 02:26:15.796 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.28.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:26:15.796 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:26:15.796 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.28.20:5700/3) Recv NOMTXPOWER cmd
2026-01-29 02:26:15.796 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.28.20:5700/3) Recv SETFORMAT cmd
2026-01-29 02:26:15.796 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.28.20:5700/3) TRXD header version 1 -> 1
2026-01-29 02:26:15.797 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.28.20:5700) Recv RXTUNE cmd
2026-01-29 02:26:15.797 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETTSC
2026-01-29 02:26:15.797 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETTSC
2026-01-29 02:26:15.797 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETTSC
2026-01-29 02:26:15.797 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.28.20:5700) Recv TXTUNE cmd
2026-01-29 02:26:15.797 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETRXGAIN
2026-01-29 02:26:15.797 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETRXGAIN
2026-01-29 02:26:15.797 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETRXGAIN
2026-01-29 02:26:15.797 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETTSC
2026-01-29 02:26:15.797 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:26:15.797 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:26:15.797 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:26:15.797 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.28.20:5700) Recv NOMTXPOWER cmd
2026-01-29 02:26:15.797 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:26:15.797 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:26:15.797 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:26:15.797 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.28.20:5700) Recv POWERON CMD
2026-01-29 02:26:15.797 [INFO] ctrl_if_trx.py:109 (BTS@172.18.28.20:5700) Starting transceiver...
2026-01-29 02:26:15.797 [INFO] transceiver.py:243 Starting clock generator
2026-01-29 02:26:15.797 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-01-29 02:26:15.797 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:26:15.797 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:26:15.797 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:26:15.797 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETRXGAIN
2026-01-29 02:26:15.798 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:26:15.798 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:26:15.798 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:26:15.798 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:26:15.798 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:26:15.798 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:26:15.798 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:26:15.798 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:26:15.798 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:26:15.798 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:26:15.798 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:26:15.798 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:26:15.798 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:26:15.798 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:26:15.798 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:26:15.798 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:26:15.798 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:26:15.798 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:26:15.798 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:26:15.798 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:26:15.798 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:26:15.798 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:26:15.798 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:26:15.802 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-01-29 02:26:16.280 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-01-29 02:26:16.324 [DEBUG] fake_trx.py:278 (BTS@172.18.28.20:5700) Recv FAKE_TOA cmd
2026-01-29 02:26:16.325 [DEBUG] fake_trx.py:297 (BTS@172.18.28.20:5700) Recv FAKE_RSSI cmd
2026-01-29 02:26:16.326 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:26:16.327 [DEBUG] fake_trx.py:322 (BTS@172.18.28.20:5700) Recv FAKE_CI cmd
2026-01-29 02:26:16.343 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 02:26:16.343 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 02:26:16.343 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 02:26:16.359 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 02:26:16.359 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 02:26:16.359 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 02:26:16.360 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:26:16.364 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:26:16.364 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 02:26:16.365 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 02:26:16.365 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.28.22:6700) Recv POWERON CMD
2026-01-29 02:26:16.365 [INFO] ctrl_if_trx.py:109 (MS@172.18.28.22:6700) Starting transceiver...
2026-01-29 02:26:16.370 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 02:26:16.370 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 02:26:16.371 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:26:16.371 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:26:16.753 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-01-29 02:26:16.799 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 02:26:16.800 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:26:16.802 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:26:16.802 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:26:17.231 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-01-29 02:26:17.708 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-01-29 02:26:17.801 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 02:26:17.801 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:26:17.802 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:26:17.804 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:26:18.186 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-01-29 02:26:18.665 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-01-29 02:26:18.801 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 02:26:18.802 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:26:18.803 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:26:18.805 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:26:19.142 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-01-29 02:26:19.620 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-01-29 02:26:19.802 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 02:26:19.802 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:26:19.804 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:26:19.805 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:26:20.098 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-01-29 02:26:20.576 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-01-29 02:26:20.803 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 02:26:20.803 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:26:20.805 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:26:20.807 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:26:21.054 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-01-29 02:26:21.372 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:26:21.373 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:26:21.378 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 02:26:21.378 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 02:26:21.392 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 02:26:21.392 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 02:26:21.392 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 02:26:21.398 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 02:26:21.398 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 02:26:21.398 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 02:26:21.399 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:26:21.400 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:26:21.400 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 02:26:21.400 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 02:26:21.400 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.28.22:6700) Recv POWERON CMD
2026-01-29 02:26:21.400 [INFO] ctrl_if_trx.py:109 (MS@172.18.28.22:6700) Starting transceiver...
2026-01-29 02:26:21.429 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 02:26:21.429 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 02:26:21.430 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:26:21.431 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:26:21.531 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-01-29 02:26:22.009 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-01-29 02:26:22.487 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-01-29 02:26:22.964 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-01-29 02:26:23.440 [DEBUG] clck_gen.py:113 IND CLOCK 1632
2026-01-29 02:26:23.918 [DEBUG] clck_gen.py:113 IND CLOCK 1734
2026-01-29 02:26:24.396 [DEBUG] clck_gen.py:113 IND CLOCK 1836
2026-01-29 02:26:24.874 [DEBUG] clck_gen.py:113 IND CLOCK 1938
2026-01-29 02:26:25.353 [DEBUG] clck_gen.py:113 IND CLOCK 2040
2026-01-29 02:26:25.831 [DEBUG] clck_gen.py:113 IND CLOCK 2142
2026-01-29 02:26:26.309 [DEBUG] clck_gen.py:113 IND CLOCK 2244
2026-01-29 02:26:26.433 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:26:26.434 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:26:26.438 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 02:26:26.438 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 02:26:26.456 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 02:26:26.456 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 02:26:26.456 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 02:26:26.462 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 02:26:26.462 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 02:26:26.462 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 02:26:26.462 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:26:26.464 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:26:26.464 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 02:26:26.464 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 02:26:26.464 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.28.22:6700) Recv POWERON CMD
2026-01-29 02:26:26.464 [INFO] ctrl_if_trx.py:109 (MS@172.18.28.22:6700) Starting transceiver...
2026-01-29 02:26:26.493 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 02:26:26.493 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 02:26:26.493 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:26:26.493 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:26:26.784 [DEBUG] clck_gen.py:113 IND CLOCK 2346
2026-01-29 02:26:27.262 [DEBUG] clck_gen.py:113 IND CLOCK 2448
2026-01-29 02:26:27.740 [DEBUG] clck_gen.py:113 IND CLOCK 2550
2026-01-29 02:26:28.217 [DEBUG] clck_gen.py:113 IND CLOCK 2652
2026-01-29 02:26:28.695 [DEBUG] clck_gen.py:113 IND CLOCK 2754
2026-01-29 02:26:29.173 [DEBUG] clck_gen.py:113 IND CLOCK 2856
2026-01-29 02:26:29.650 [DEBUG] clck_gen.py:113 IND CLOCK 2958
2026-01-29 02:26:30.128 [DEBUG] clck_gen.py:113 IND CLOCK 3060
2026-01-29 02:26:30.606 [DEBUG] clck_gen.py:113 IND CLOCK 3162
2026-01-29 02:26:31.084 [DEBUG] clck_gen.py:113 IND CLOCK 3264
2026-01-29 02:26:31.497 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:26:31.497 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:26:31.502 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 02:26:31.502 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 02:26:31.521 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 02:26:31.521 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 02:26:31.522 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 02:26:31.528 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 02:26:31.528 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 02:26:31.528 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:26:31.528 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 02:26:31.530 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:26:31.530 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 02:26:31.530 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 02:26:31.530 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.28.22:6700) Recv POWERON CMD
2026-01-29 02:26:31.530 [INFO] ctrl_if_trx.py:109 (MS@172.18.28.22:6700) Starting transceiver...
2026-01-29 02:26:31.554 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 02:26:31.554 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 02:26:31.554 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:26:31.555 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:26:31.561 [DEBUG] clck_gen.py:113 IND CLOCK 3366
2026-01-29 02:26:32.038 [DEBUG] clck_gen.py:113 IND CLOCK 3468
2026-01-29 02:26:32.516 [DEBUG] clck_gen.py:113 IND CLOCK 3570
2026-01-29 02:26:32.994 [DEBUG] clck_gen.py:113 IND CLOCK 3672
2026-01-29 02:26:33.468 [DEBUG] clck_gen.py:113 IND CLOCK 3774
2026-01-29 02:26:33.942 [DEBUG] clck_gen.py:113 IND CLOCK 3876
2026-01-29 02:26:34.419 [DEBUG] clck_gen.py:113 IND CLOCK 3978
2026-01-29 02:26:34.896 [DEBUG] clck_gen.py:113 IND CLOCK 4080
2026-01-29 02:26:35.375 [DEBUG] clck_gen.py:113 IND CLOCK 4182
2026-01-29 02:26:35.852 [DEBUG] clck_gen.py:113 IND CLOCK 4284
2026-01-29 02:26:36.331 [DEBUG] clck_gen.py:113 IND CLOCK 4386
2026-01-29 02:26:36.559 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:26:36.559 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:26:36.564 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 02:26:36.564 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 02:26:36.573 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 02:26:36.573 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:26:36.573 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:26:36.573 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:26:36.575 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 02:26:36.575 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:26:36.575 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:26:36.575 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:26:36.575 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.28.20:5700) Recv POWEROFF cmd
2026-01-29 02:26:36.575 [INFO] ctrl_if_trx.py:117 (BTS@172.18.28.20:5700) Stopping transceiver...
2026-01-29 02:26:36.575 [INFO] transceiver.py:246 Stopping clock generator
2026-01-29 02:26:41.577 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.28.20:5700) Recv POWEROFF cmd
2026-01-29 02:26:41.577 [INFO] ctrl_if_trx.py:117 (BTS@172.18.28.20:5700) Stopping transceiver...
2026-01-29 02:26:41.578 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:26:41.580 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:26:41.582 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:26:41.585 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 02:26:41.598 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 02:26:41.599 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.28.20:5700) Recv SETFORMAT cmd
2026-01-29 02:26:41.599 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.28.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:26:41.599 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.28.20:5700) Recv SETFORMAT cmd
2026-01-29 02:26:41.599 [INFO] ctrl_if_trx.py:201 (BTS@172.18.28.20:5700) TRXD header version 1 -> 1
2026-01-29 02:26:41.602 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.28.20:5700/1) Recv RXTUNE cmd
2026-01-29 02:26:41.602 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.28.20:5700/1) Recv TXTUNE cmd
2026-01-29 02:26:41.603 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.28.20:5700/1) Recv SETFORMAT cmd
2026-01-29 02:26:41.603 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.28.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:26:41.603 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:26:41.603 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.28.20:5700/1) Recv NOMTXPOWER cmd
2026-01-29 02:26:41.604 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.28.20:5700/1) Recv SETFORMAT cmd
2026-01-29 02:26:41.604 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.28.20:5700/1) TRXD header version 1 -> 1
2026-01-29 02:26:41.605 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.28.20:5700/2) Recv RXTUNE cmd
2026-01-29 02:26:41.605 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.28.20:5700/2) Recv TXTUNE cmd
2026-01-29 02:26:41.605 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.28.20:5700/2) Recv SETFORMAT cmd
2026-01-29 02:26:41.605 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.28.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:26:41.605 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:26:41.605 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.28.20:5700/2) Recv NOMTXPOWER cmd
2026-01-29 02:26:41.605 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.28.20:5700/2) Recv SETFORMAT cmd
2026-01-29 02:26:41.605 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.28.20:5700/2) TRXD header version 1 -> 1
2026-01-29 02:26:41.607 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.28.20:5700/3) Recv RXTUNE cmd
2026-01-29 02:26:41.607 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.28.20:5700/3) Recv TXTUNE cmd
2026-01-29 02:26:41.607 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.28.20:5700/3) Recv SETFORMAT cmd
2026-01-29 02:26:41.607 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.28.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:26:41.607 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:26:41.607 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.28.20:5700/3) Recv NOMTXPOWER cmd
2026-01-29 02:26:41.607 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.28.20:5700/3) Recv SETFORMAT cmd
2026-01-29 02:26:41.607 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.28.20:5700/3) TRXD header version 1 -> 1
2026-01-29 02:26:41.610 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.28.20:5700) Recv RXTUNE cmd
2026-01-29 02:26:41.610 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETTSC
2026-01-29 02:26:41.610 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETTSC
2026-01-29 02:26:41.610 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETTSC
2026-01-29 02:26:41.610 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.28.20:5700) Recv TXTUNE cmd
2026-01-29 02:26:41.610 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETRXGAIN
2026-01-29 02:26:41.610 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETRXGAIN
2026-01-29 02:26:41.610 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETRXGAIN
2026-01-29 02:26:41.610 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETTSC
2026-01-29 02:26:41.610 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:26:41.610 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:26:41.610 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:26:41.610 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.28.20:5700) Recv NOMTXPOWER cmd
2026-01-29 02:26:41.610 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:26:41.610 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:26:41.610 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:26:41.610 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.28.20:5700) Recv POWERON CMD
2026-01-29 02:26:41.610 [INFO] ctrl_if_trx.py:109 (BTS@172.18.28.20:5700) Starting transceiver...
2026-01-29 02:26:41.610 [INFO] transceiver.py:243 Starting clock generator
2026-01-29 02:26:41.611 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-01-29 02:26:41.611 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:26:41.611 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:26:41.611 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:26:41.611 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETRXGAIN
2026-01-29 02:26:41.611 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:26:41.611 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:26:41.611 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:26:41.611 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:26:41.611 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:26:41.611 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:26:41.611 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:26:41.611 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:26:41.611 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:26:41.611 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:26:41.611 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:26:41.611 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:26:41.611 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:26:41.611 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:26:41.611 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:26:41.611 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:26:41.611 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:26:41.611 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:26:41.611 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:26:41.611 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:26:41.611 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:26:41.612 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:26:41.612 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:26:41.615 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-01-29 02:26:42.096 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-01-29 02:26:42.131 [DEBUG] fake_trx.py:278 (BTS@172.18.28.20:5700) Recv FAKE_TOA cmd
2026-01-29 02:26:42.132 [DEBUG] fake_trx.py:297 (BTS@172.18.28.20:5700) Recv FAKE_RSSI cmd
2026-01-29 02:26:42.133 [DEBUG] fake_trx.py:322 (BTS@172.18.28.20:5700) Recv FAKE_CI cmd
2026-01-29 02:26:42.134 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:26:42.144 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 02:26:42.144 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 02:26:42.144 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 02:26:42.155 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 02:26:42.155 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 02:26:42.155 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 02:26:42.156 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:26:42.158 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:26:42.158 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 02:26:42.158 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 02:26:42.158 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.28.22:6700) Recv POWERON CMD
2026-01-29 02:26:42.158 [INFO] ctrl_if_trx.py:109 (MS@172.18.28.22:6700) Starting transceiver...
2026-01-29 02:26:42.187 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 02:26:42.187 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 02:26:42.187 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:26:42.188 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:26:42.413 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:26:42.413 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:26:42.417 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 02:26:42.417 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 02:26:42.436 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 02:26:42.436 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 02:26:42.436 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 02:26:42.442 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 02:26:42.442 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 02:26:42.442 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 02:26:42.442 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:26:42.443 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:26:42.443 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 02:26:42.443 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 02:26:42.443 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.28.22:6700) Recv POWERON CMD
2026-01-29 02:26:42.444 [INFO] ctrl_if_trx.py:109 (MS@172.18.28.22:6700) Starting transceiver...
2026-01-29 02:26:42.469 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 02:26:42.469 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 02:26:42.469 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:26:42.469 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:26:42.565 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-01-29 02:26:42.613 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 02:26:42.613 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:26:42.614 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:26:42.617 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:26:42.848 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:26:42.849 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:26:42.852 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 02:26:42.853 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 02:26:42.871 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 02:26:42.871 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 02:26:42.871 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 02:26:42.877 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 02:26:42.877 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 02:26:42.877 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 02:26:42.877 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:26:42.879 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:26:42.879 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 02:26:42.879 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 02:26:42.879 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.28.22:6700) Recv POWERON CMD
2026-01-29 02:26:42.879 [INFO] ctrl_if_trx.py:109 (MS@172.18.28.22:6700) Starting transceiver...
2026-01-29 02:26:42.886 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 02:26:42.886 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 02:26:42.886 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:26:42.886 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:26:43.041 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-01-29 02:26:43.518 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-01-29 02:26:43.614 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 02:26:43.615 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:26:43.615 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:26:43.618 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:26:43.674 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:26:43.675 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:26:43.679 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 02:26:43.679 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 02:26:43.697 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 02:26:43.698 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 02:26:43.698 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 02:26:43.703 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 02:26:43.703 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 02:26:43.704 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 02:26:43.704 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:26:43.705 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:26:43.705 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 02:26:43.705 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 02:26:43.705 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.28.22:6700) Recv POWERON CMD
2026-01-29 02:26:43.705 [INFO] ctrl_if_trx.py:109 (MS@172.18.28.22:6700) Starting transceiver...
2026-01-29 02:26:43.753 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 02:26:43.753 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 02:26:43.753 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:26:43.753 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:26:43.994 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-01-29 02:26:44.471 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-01-29 02:26:44.554 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:26:44.555 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:26:44.559 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 02:26:44.560 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 02:26:44.567 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 02:26:44.567 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:26:44.567 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:26:44.567 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:26:44.568 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 02:26:44.568 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:26:44.568 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:26:44.568 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.28.20:5700) Recv POWEROFF cmd
2026-01-29 02:26:44.568 [INFO] ctrl_if_trx.py:117 (BTS@172.18.28.20:5700) Stopping transceiver...
2026-01-29 02:26:44.568 [INFO] transceiver.py:246 Stopping clock generator
2026-01-29 02:26:44.568 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:26:49.574 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.28.20:5700) Recv POWEROFF cmd
2026-01-29 02:26:49.574 [INFO] ctrl_if_trx.py:117 (BTS@172.18.28.20:5700) Stopping transceiver...
2026-01-29 02:26:49.574 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:26:49.574 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:26:49.574 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:26:49.574 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 02:26:49.581 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 02:26:49.581 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.28.20:5700) Recv SETFORMAT cmd
2026-01-29 02:26:49.581 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.28.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:26:49.582 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.28.20:5700) Recv SETFORMAT cmd
2026-01-29 02:26:49.582 [INFO] ctrl_if_trx.py:201 (BTS@172.18.28.20:5700) TRXD header version 1 -> 1
2026-01-29 02:26:49.585 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.28.20:5700/1) Recv RXTUNE cmd
2026-01-29 02:26:49.586 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.28.20:5700/1) Recv TXTUNE cmd
2026-01-29 02:26:49.586 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.28.20:5700/1) Recv SETFORMAT cmd
2026-01-29 02:26:49.586 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.28.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:26:49.586 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:26:49.586 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.28.20:5700/1) Recv NOMTXPOWER cmd
2026-01-29 02:26:49.587 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.28.20:5700/1) Recv SETFORMAT cmd
2026-01-29 02:26:49.587 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.28.20:5700/1) TRXD header version 1 -> 1
2026-01-29 02:26:49.589 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.28.20:5700/2) Recv RXTUNE cmd
2026-01-29 02:26:49.590 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.28.20:5700/2) Recv TXTUNE cmd
2026-01-29 02:26:49.590 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.28.20:5700/2) Recv SETFORMAT cmd
2026-01-29 02:26:49.590 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.28.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:26:49.590 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:26:49.590 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.28.20:5700/2) Recv NOMTXPOWER cmd
2026-01-29 02:26:49.591 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.28.20:5700/2) Recv SETFORMAT cmd
2026-01-29 02:26:49.591 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.28.20:5700/2) TRXD header version 1 -> 1
2026-01-29 02:26:49.593 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.28.20:5700/3) Recv RXTUNE cmd
2026-01-29 02:26:49.593 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.28.20:5700/3) Recv TXTUNE cmd
2026-01-29 02:26:49.593 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.28.20:5700/3) Recv SETFORMAT cmd
2026-01-29 02:26:49.593 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.28.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:26:49.593 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:26:49.594 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.28.20:5700/3) Recv NOMTXPOWER cmd
2026-01-29 02:26:49.594 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.28.20:5700/3) Recv SETFORMAT cmd
2026-01-29 02:26:49.594 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.28.20:5700/3) TRXD header version 1 -> 1
2026-01-29 02:26:49.597 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.28.20:5700) Recv RXTUNE cmd
2026-01-29 02:26:49.597 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETTSC
2026-01-29 02:26:49.597 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETTSC
2026-01-29 02:26:49.598 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.28.20:5700) Recv TXTUNE cmd
2026-01-29 02:26:49.598 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETTSC
2026-01-29 02:26:49.598 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETRXGAIN
2026-01-29 02:26:49.598 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETRXGAIN
2026-01-29 02:26:49.598 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETTSC
2026-01-29 02:26:49.598 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETRXGAIN
2026-01-29 02:26:49.598 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:26:49.598 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:26:49.598 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.28.20:5700) Recv NOMTXPOWER cmd
2026-01-29 02:26:49.598 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:26:49.598 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:26:49.598 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:26:49.598 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.28.20:5700) Recv POWERON CMD
2026-01-29 02:26:49.598 [INFO] ctrl_if_trx.py:109 (BTS@172.18.28.20:5700) Starting transceiver...
2026-01-29 02:26:49.598 [INFO] transceiver.py:243 Starting clock generator
2026-01-29 02:26:49.598 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-01-29 02:26:49.599 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:26:49.599 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:26:49.599 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:26:49.599 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETRXGAIN
2026-01-29 02:26:49.599 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:26:49.599 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:26:49.599 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:26:49.599 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:26:49.599 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:26:49.599 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:26:49.599 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:26:49.599 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:26:49.599 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:26:49.599 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:26:49.599 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:26:49.599 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:26:49.600 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:26:49.600 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:26:49.600 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:26:49.600 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:26:49.600 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:26:49.600 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:26:49.600 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:26:49.600 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:26:49.600 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:26:49.600 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:26:49.600 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:26:49.600 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:26:49.603 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-01-29 02:26:50.086 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-01-29 02:26:50.129 [DEBUG] fake_trx.py:278 (BTS@172.18.28.20:5700) Recv FAKE_TOA cmd
2026-01-29 02:26:50.131 [DEBUG] fake_trx.py:297 (BTS@172.18.28.20:5700) Recv FAKE_RSSI cmd
2026-01-29 02:26:50.131 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:26:50.132 [DEBUG] fake_trx.py:322 (BTS@172.18.28.20:5700) Recv FAKE_CI cmd
2026-01-29 02:26:50.149 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 02:26:50.150 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 02:26:50.150 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 02:26:50.165 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 02:26:50.166 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 02:26:50.166 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 02:26:50.167 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:26:50.171 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:26:50.171 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 02:26:50.172 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 02:26:50.172 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.28.22:6700) Recv POWERON CMD
2026-01-29 02:26:50.172 [INFO] ctrl_if_trx.py:109 (MS@172.18.28.22:6700) Starting transceiver...
2026-01-29 02:26:50.176 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 02:26:50.177 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 02:26:50.177 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:26:50.177 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:26:50.562 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-01-29 02:26:50.602 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:26:50.603 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 02:26:50.603 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:26:50.608 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:26:51.040 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-01-29 02:26:51.518 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-01-29 02:26:51.603 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 02:26:51.604 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:26:51.605 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:26:51.609 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:26:51.996 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-01-29 02:26:52.474 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-01-29 02:26:52.604 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 02:26:52.604 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:26:52.606 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:26:52.610 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:26:52.952 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-01-29 02:26:53.430 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-01-29 02:26:53.605 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 02:26:53.605 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:26:53.607 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:26:53.611 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:26:53.908 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-01-29 02:26:54.385 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-01-29 02:26:54.605 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 02:26:54.605 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:26:54.608 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:26:54.612 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:26:54.863 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-01-29 02:26:55.340 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-01-29 02:26:55.818 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-01-29 02:26:56.296 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-01-29 02:26:56.772 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-01-29 02:26:57.250 [DEBUG] clck_gen.py:113 IND CLOCK 1632
2026-01-29 02:26:57.729 [DEBUG] clck_gen.py:113 IND CLOCK 1734
2026-01-29 02:26:58.207 [DEBUG] clck_gen.py:113 IND CLOCK 1836
2026-01-29 02:26:58.685 [DEBUG] clck_gen.py:113 IND CLOCK 1938
2026-01-29 02:26:59.163 [DEBUG] clck_gen.py:113 IND CLOCK 2040
2026-01-29 02:26:59.641 [DEBUG] clck_gen.py:113 IND CLOCK 2142
2026-01-29 02:27:00.119 [DEBUG] clck_gen.py:113 IND CLOCK 2244
2026-01-29 02:27:00.597 [DEBUG] clck_gen.py:113 IND CLOCK 2346
2026-01-29 02:27:01.075 [DEBUG] clck_gen.py:113 IND CLOCK 2448
2026-01-29 02:27:01.553 [DEBUG] clck_gen.py:113 IND CLOCK 2550
2026-01-29 02:27:02.030 [DEBUG] clck_gen.py:113 IND CLOCK 2652
2026-01-29 02:27:02.508 [DEBUG] clck_gen.py:113 IND CLOCK 2754
2026-01-29 02:27:02.986 [DEBUG] clck_gen.py:113 IND CLOCK 2856
2026-01-29 02:27:03.464 [DEBUG] clck_gen.py:113 IND CLOCK 2958
2026-01-29 02:27:03.942 [DEBUG] clck_gen.py:113 IND CLOCK 3060
2026-01-29 02:27:04.420 [DEBUG] clck_gen.py:113 IND CLOCK 3162
2026-01-29 02:27:04.898 [DEBUG] clck_gen.py:113 IND CLOCK 3264
2026-01-29 02:27:05.376 [DEBUG] clck_gen.py:113 IND CLOCK 3366
2026-01-29 02:27:05.854 [DEBUG] clck_gen.py:113 IND CLOCK 3468
2026-01-29 02:27:06.332 [DEBUG] clck_gen.py:113 IND CLOCK 3570
2026-01-29 02:27:06.810 [DEBUG] clck_gen.py:113 IND CLOCK 3672
2026-01-29 02:27:07.288 [DEBUG] clck_gen.py:113 IND CLOCK 3774
2026-01-29 02:27:07.766 [DEBUG] clck_gen.py:113 IND CLOCK 3876
2026-01-29 02:27:08.243 [DEBUG] clck_gen.py:113 IND CLOCK 3978
2026-01-29 02:27:08.720 [DEBUG] clck_gen.py:113 IND CLOCK 4080
2026-01-29 02:27:09.198 [DEBUG] clck_gen.py:113 IND CLOCK 4182
2026-01-29 02:27:09.676 [DEBUG] clck_gen.py:113 IND CLOCK 4284
2026-01-29 02:27:10.154 [DEBUG] clck_gen.py:113 IND CLOCK 4386
2026-01-29 02:27:10.180 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:27:10.180 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:27:10.190 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 02:27:10.190 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 02:27:10.201 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 02:27:10.201 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 02:27:10.201 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 02:27:10.207 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 02:27:10.207 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 02:27:10.207 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 02:27:10.208 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:27:10.209 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:27:10.209 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 02:27:10.209 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 02:27:10.209 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.28.22:6700) Recv POWERON CMD
2026-01-29 02:27:10.209 [INFO] ctrl_if_trx.py:109 (MS@172.18.28.22:6700) Starting transceiver...
2026-01-29 02:27:10.246 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 02:27:10.246 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 02:27:10.246 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:27:10.246 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:27:10.631 [DEBUG] clck_gen.py:113 IND CLOCK 4488
2026-01-29 02:27:11.110 [DEBUG] clck_gen.py:113 IND CLOCK 4590
2026-01-29 02:27:11.588 [DEBUG] clck_gen.py:113 IND CLOCK 4692
2026-01-29 02:27:12.066 [DEBUG] clck_gen.py:113 IND CLOCK 4794
2026-01-29 02:27:12.544 [DEBUG] clck_gen.py:113 IND CLOCK 4896
2026-01-29 02:27:13.022 [DEBUG] clck_gen.py:113 IND CLOCK 4998
2026-01-29 02:27:13.501 [DEBUG] clck_gen.py:113 IND CLOCK 5100
2026-01-29 02:27:13.979 [DEBUG] clck_gen.py:113 IND CLOCK 5202
2026-01-29 02:27:14.457 [DEBUG] clck_gen.py:113 IND CLOCK 5304
2026-01-29 02:27:14.936 [DEBUG] clck_gen.py:113 IND CLOCK 5406
2026-01-29 02:27:15.413 [DEBUG] clck_gen.py:113 IND CLOCK 5508
2026-01-29 02:27:15.892 [DEBUG] clck_gen.py:113 IND CLOCK 5610
2026-01-29 02:27:16.370 [DEBUG] clck_gen.py:113 IND CLOCK 5712
2026-01-29 02:27:16.848 [DEBUG] clck_gen.py:113 IND CLOCK 5814
2026-01-29 02:27:17.327 [DEBUG] clck_gen.py:113 IND CLOCK 5916
2026-01-29 02:27:17.805 [DEBUG] clck_gen.py:113 IND CLOCK 6018
2026-01-29 02:27:18.284 [DEBUG] clck_gen.py:113 IND CLOCK 6120
2026-01-29 02:27:18.762 [DEBUG] clck_gen.py:113 IND CLOCK 6222
2026-01-29 02:27:19.240 [DEBUG] clck_gen.py:113 IND CLOCK 6324
2026-01-29 02:27:19.718 [DEBUG] clck_gen.py:113 IND CLOCK 6426
2026-01-29 02:27:20.197 [DEBUG] clck_gen.py:113 IND CLOCK 6528
2026-01-29 02:27:20.675 [DEBUG] clck_gen.py:113 IND CLOCK 6630
2026-01-29 02:27:21.152 [DEBUG] clck_gen.py:113 IND CLOCK 6732
2026-01-29 02:27:21.630 [DEBUG] clck_gen.py:113 IND CLOCK 6834
2026-01-29 02:27:22.108 [DEBUG] clck_gen.py:113 IND CLOCK 6936
2026-01-29 02:27:22.587 [DEBUG] clck_gen.py:113 IND CLOCK 7038
2026-01-29 02:27:23.065 [DEBUG] clck_gen.py:113 IND CLOCK 7140
2026-01-29 02:27:23.543 [DEBUG] clck_gen.py:113 IND CLOCK 7242
2026-01-29 02:27:24.021 [DEBUG] clck_gen.py:113 IND CLOCK 7344
2026-01-29 02:27:24.499 [DEBUG] clck_gen.py:113 IND CLOCK 7446
2026-01-29 02:27:24.977 [DEBUG] clck_gen.py:113 IND CLOCK 7548
2026-01-29 02:27:25.455 [DEBUG] clck_gen.py:113 IND CLOCK 7650
2026-01-29 02:27:25.933 [DEBUG] clck_gen.py:113 IND CLOCK 7752
2026-01-29 02:27:26.411 [DEBUG] clck_gen.py:113 IND CLOCK 7854
2026-01-29 02:27:26.889 [DEBUG] clck_gen.py:113 IND CLOCK 7956
2026-01-29 02:27:27.367 [DEBUG] clck_gen.py:113 IND CLOCK 8058
2026-01-29 02:27:27.844 [DEBUG] clck_gen.py:113 IND CLOCK 8160
2026-01-29 02:27:28.322 [DEBUG] clck_gen.py:113 IND CLOCK 8262
2026-01-29 02:27:28.801 [DEBUG] clck_gen.py:113 IND CLOCK 8364
2026-01-29 02:27:29.279 [DEBUG] clck_gen.py:113 IND CLOCK 8466
2026-01-29 02:27:29.756 [DEBUG] clck_gen.py:113 IND CLOCK 8568
2026-01-29 02:27:30.234 [DEBUG] clck_gen.py:113 IND CLOCK 8670
2026-01-29 02:27:30.249 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:27:30.250 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:27:30.260 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 02:27:30.260 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 02:27:30.274 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 02:27:30.274 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 02:27:30.274 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 02:27:30.280 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 02:27:30.280 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 02:27:30.280 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 02:27:30.280 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:27:30.281 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:27:30.282 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 02:27:30.282 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 02:27:30.282 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.28.22:6700) Recv POWERON CMD
2026-01-29 02:27:30.282 [INFO] ctrl_if_trx.py:109 (MS@172.18.28.22:6700) Starting transceiver...
2026-01-29 02:27:30.326 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 02:27:30.326 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 02:27:30.326 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:27:30.326 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:27:30.711 [DEBUG] clck_gen.py:113 IND CLOCK 8772
2026-01-29 02:27:31.189 [DEBUG] clck_gen.py:113 IND CLOCK 8874
2026-01-29 02:27:31.666 [DEBUG] clck_gen.py:113 IND CLOCK 8976
2026-01-29 02:27:32.143 [DEBUG] clck_gen.py:113 IND CLOCK 9078
2026-01-29 02:27:32.621 [DEBUG] clck_gen.py:113 IND CLOCK 9180
2026-01-29 02:27:33.100 [DEBUG] clck_gen.py:113 IND CLOCK 9282
2026-01-29 02:27:33.578 [DEBUG] clck_gen.py:113 IND CLOCK 9384
2026-01-29 02:27:34.055 [DEBUG] clck_gen.py:113 IND CLOCK 9486
2026-01-29 02:27:34.533 [DEBUG] clck_gen.py:113 IND CLOCK 9588
2026-01-29 02:27:35.011 [DEBUG] clck_gen.py:113 IND CLOCK 9690
2026-01-29 02:27:35.489 [DEBUG] clck_gen.py:113 IND CLOCK 9792
2026-01-29 02:27:35.967 [DEBUG] clck_gen.py:113 IND CLOCK 9894
2026-01-29 02:27:36.445 [DEBUG] clck_gen.py:113 IND CLOCK 9996
2026-01-29 02:27:36.923 [DEBUG] clck_gen.py:113 IND CLOCK 10098
2026-01-29 02:27:37.401 [DEBUG] clck_gen.py:113 IND CLOCK 10200
2026-01-29 02:27:37.879 [DEBUG] clck_gen.py:113 IND CLOCK 10302
2026-01-29 02:27:38.357 [DEBUG] clck_gen.py:113 IND CLOCK 10404
2026-01-29 02:27:38.834 [DEBUG] clck_gen.py:113 IND CLOCK 10506
2026-01-29 02:27:39.311 [DEBUG] clck_gen.py:113 IND CLOCK 10608
2026-01-29 02:27:39.789 [DEBUG] clck_gen.py:113 IND CLOCK 10710
2026-01-29 02:27:40.268 [DEBUG] clck_gen.py:113 IND CLOCK 10812
2026-01-29 02:27:40.745 [DEBUG] clck_gen.py:113 IND CLOCK 10914
2026-01-29 02:27:41.223 [DEBUG] clck_gen.py:113 IND CLOCK 11016
2026-01-29 02:27:41.701 [DEBUG] clck_gen.py:113 IND CLOCK 11118
2026-01-29 02:27:42.179 [DEBUG] clck_gen.py:113 IND CLOCK 11220
2026-01-29 02:27:42.657 [DEBUG] clck_gen.py:113 IND CLOCK 11322
2026-01-29 02:27:43.135 [DEBUG] clck_gen.py:113 IND CLOCK 11424
2026-01-29 02:27:43.614 [DEBUG] clck_gen.py:113 IND CLOCK 11526
2026-01-29 02:27:44.092 [DEBUG] clck_gen.py:113 IND CLOCK 11628
2026-01-29 02:27:44.569 [DEBUG] clck_gen.py:113 IND CLOCK 11730
2026-01-29 02:27:45.047 [DEBUG] clck_gen.py:113 IND CLOCK 11832
2026-01-29 02:27:45.525 [DEBUG] clck_gen.py:113 IND CLOCK 11934
2026-01-29 02:27:46.003 [DEBUG] clck_gen.py:113 IND CLOCK 12036
2026-01-29 02:27:46.481 [DEBUG] clck_gen.py:113 IND CLOCK 12138
2026-01-29 02:27:46.959 [DEBUG] clck_gen.py:113 IND CLOCK 12240
2026-01-29 02:27:47.435 [DEBUG] clck_gen.py:113 IND CLOCK 12342
2026-01-29 02:27:47.912 [DEBUG] clck_gen.py:113 IND CLOCK 12444
2026-01-29 02:27:48.390 [DEBUG] clck_gen.py:113 IND CLOCK 12546
2026-01-29 02:27:48.868 [DEBUG] clck_gen.py:113 IND CLOCK 12648
2026-01-29 02:27:49.345 [DEBUG] clck_gen.py:113 IND CLOCK 12750
2026-01-29 02:27:49.822 [DEBUG] clck_gen.py:113 IND CLOCK 12852
2026-01-29 02:27:50.300 [DEBUG] clck_gen.py:113 IND CLOCK 12954
2026-01-29 02:27:50.329 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:27:50.332 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:27:50.337 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 02:27:50.337 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 02:27:50.354 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 02:27:50.354 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 02:27:50.354 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 02:27:50.360 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 02:27:50.360 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 02:27:50.360 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:27:50.360 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 02:27:50.362 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:27:50.362 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 02:27:50.362 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 02:27:50.362 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.28.22:6700) Recv POWERON CMD
2026-01-29 02:27:50.362 [INFO] ctrl_if_trx.py:109 (MS@172.18.28.22:6700) Starting transceiver...
2026-01-29 02:27:50.392 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 02:27:50.392 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 02:27:50.393 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:27:50.393 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:27:50.778 [DEBUG] clck_gen.py:113 IND CLOCK 13056
2026-01-29 02:27:51.256 [DEBUG] clck_gen.py:113 IND CLOCK 13158
2026-01-29 02:27:51.734 [DEBUG] clck_gen.py:113 IND CLOCK 13260
2026-01-29 02:27:52.213 [DEBUG] clck_gen.py:113 IND CLOCK 13362
2026-01-29 02:27:52.691 [DEBUG] clck_gen.py:113 IND CLOCK 13464
2026-01-29 02:27:53.169 [DEBUG] clck_gen.py:113 IND CLOCK 13566
2026-01-29 02:27:53.646 [DEBUG] clck_gen.py:113 IND CLOCK 13668
2026-01-29 02:27:54.124 [DEBUG] clck_gen.py:113 IND CLOCK 13770
2026-01-29 02:27:54.603 [DEBUG] clck_gen.py:113 IND CLOCK 13872
2026-01-29 02:27:55.081 [DEBUG] clck_gen.py:113 IND CLOCK 13974
2026-01-29 02:27:55.559 [DEBUG] clck_gen.py:113 IND CLOCK 14076
2026-01-29 02:27:56.037 [DEBUG] clck_gen.py:113 IND CLOCK 14178
2026-01-29 02:27:56.515 [DEBUG] clck_gen.py:113 IND CLOCK 14280
2026-01-29 02:27:56.993 [DEBUG] clck_gen.py:113 IND CLOCK 14382
2026-01-29 02:27:57.471 [DEBUG] clck_gen.py:113 IND CLOCK 14484
2026-01-29 02:27:57.948 [DEBUG] clck_gen.py:113 IND CLOCK 14586
2026-01-29 02:27:58.426 [DEBUG] clck_gen.py:113 IND CLOCK 14688
2026-01-29 02:27:58.905 [DEBUG] clck_gen.py:113 IND CLOCK 14790
2026-01-29 02:27:59.382 [DEBUG] clck_gen.py:113 IND CLOCK 14892
2026-01-29 02:27:59.860 [DEBUG] clck_gen.py:113 IND CLOCK 14994
2026-01-29 02:28:00.338 [DEBUG] clck_gen.py:113 IND CLOCK 15096
2026-01-29 02:28:00.816 [DEBUG] clck_gen.py:113 IND CLOCK 15198
2026-01-29 02:28:01.294 [DEBUG] clck_gen.py:113 IND CLOCK 15300
2026-01-29 02:28:01.772 [DEBUG] clck_gen.py:113 IND CLOCK 15402
2026-01-29 02:28:02.249 [DEBUG] clck_gen.py:113 IND CLOCK 15504
2026-01-29 02:28:02.723 [DEBUG] clck_gen.py:113 IND CLOCK 15606
2026-01-29 02:28:03.196 [DEBUG] clck_gen.py:113 IND CLOCK 15708
2026-01-29 02:28:03.667 [DEBUG] clck_gen.py:113 IND CLOCK 15810
2026-01-29 02:28:04.138 [DEBUG] clck_gen.py:113 IND CLOCK 15912
2026-01-29 02:28:04.607 [DEBUG] clck_gen.py:113 IND CLOCK 16014
2026-01-29 02:28:05.076 [DEBUG] clck_gen.py:113 IND CLOCK 16116
2026-01-29 02:28:05.552 [DEBUG] clck_gen.py:113 IND CLOCK 16218
2026-01-29 02:28:06.030 [DEBUG] clck_gen.py:113 IND CLOCK 16320
2026-01-29 02:28:06.508 [DEBUG] clck_gen.py:113 IND CLOCK 16422
2026-01-29 02:28:06.987 [DEBUG] clck_gen.py:113 IND CLOCK 16524
2026-01-29 02:28:07.465 [DEBUG] clck_gen.py:113 IND CLOCK 16626
2026-01-29 02:28:07.943 [DEBUG] clck_gen.py:113 IND CLOCK 16728
2026-01-29 02:28:08.421 [DEBUG] clck_gen.py:113 IND CLOCK 16830
2026-01-29 02:28:08.897 [DEBUG] clck_gen.py:113 IND CLOCK 16932
2026-01-29 02:28:09.375 [DEBUG] clck_gen.py:113 IND CLOCK 17034
2026-01-29 02:28:09.854 [DEBUG] clck_gen.py:113 IND CLOCK 17136
2026-01-29 02:28:10.332 [DEBUG] clck_gen.py:113 IND CLOCK 17238
2026-01-29 02:28:10.395 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:28:10.395 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:28:10.399 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 02:28:10.399 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 02:28:10.410 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 02:28:10.410 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:28:10.411 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:28:10.411 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:28:10.413 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 02:28:10.413 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:28:10.413 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:28:10.413 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.28.20:5700) Recv POWEROFF cmd
2026-01-29 02:28:10.414 [INFO] ctrl_if_trx.py:117 (BTS@172.18.28.20:5700) Stopping transceiver...
2026-01-29 02:28:10.414 [INFO] transceiver.py:246 Stopping clock generator
2026-01-29 02:28:10.414 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:28:10.414 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=17257 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:28:10.414 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=17257 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:28:10.414 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=17257 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:28:10.414 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=17257 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:28:10.414 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=17257 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:28:10.414 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=17257 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:28:10.414 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=17257 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:28:10.414 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=17257 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:28:15.414 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.28.20:5700) Recv POWEROFF cmd
2026-01-29 02:28:15.414 [INFO] ctrl_if_trx.py:117 (BTS@172.18.28.20:5700) Stopping transceiver...
2026-01-29 02:28:15.416 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:28:15.417 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:28:15.419 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:28:15.419 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 02:28:15.429 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 02:28:15.431 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.28.20:5700) Recv SETFORMAT cmd
2026-01-29 02:28:15.431 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.28.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:28:15.431 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.28.20:5700) Recv SETFORMAT cmd
2026-01-29 02:28:15.432 [INFO] ctrl_if_trx.py:201 (BTS@172.18.28.20:5700) TRXD header version 1 -> 1
2026-01-29 02:28:15.435 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.28.20:5700/1) Recv RXTUNE cmd
2026-01-29 02:28:15.435 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.28.20:5700/1) Recv TXTUNE cmd
2026-01-29 02:28:15.436 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.28.20:5700/1) Recv SETFORMAT cmd
2026-01-29 02:28:15.436 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.28.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:28:15.436 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:28:15.437 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.28.20:5700/1) Recv NOMTXPOWER cmd
2026-01-29 02:28:15.437 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.28.20:5700/1) Recv SETFORMAT cmd
2026-01-29 02:28:15.437 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.28.20:5700/1) TRXD header version 1 -> 1
2026-01-29 02:28:15.439 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.28.20:5700/2) Recv RXTUNE cmd
2026-01-29 02:28:15.439 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.28.20:5700/2) Recv TXTUNE cmd
2026-01-29 02:28:15.439 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.28.20:5700/2) Recv SETFORMAT cmd
2026-01-29 02:28:15.439 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.28.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:28:15.440 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:28:15.440 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.28.20:5700/2) Recv NOMTXPOWER cmd
2026-01-29 02:28:15.441 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.28.20:5700/2) Recv SETFORMAT cmd
2026-01-29 02:28:15.441 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.28.20:5700/2) TRXD header version 1 -> 1
2026-01-29 02:28:15.442 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.28.20:5700/3) Recv RXTUNE cmd
2026-01-29 02:28:15.442 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.28.20:5700/3) Recv TXTUNE cmd
2026-01-29 02:28:15.442 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.28.20:5700/3) Recv SETFORMAT cmd
2026-01-29 02:28:15.442 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.28.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:28:15.442 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:28:15.442 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.28.20:5700/3) Recv NOMTXPOWER cmd
2026-01-29 02:28:15.442 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.28.20:5700/3) Recv SETFORMAT cmd
2026-01-29 02:28:15.442 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.28.20:5700/3) TRXD header version 1 -> 1
2026-01-29 02:28:15.446 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.28.20:5700) Recv RXTUNE cmd
2026-01-29 02:28:15.446 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETTSC
2026-01-29 02:28:15.446 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETTSC
2026-01-29 02:28:15.446 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETTSC
2026-01-29 02:28:15.446 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.28.20:5700) Recv TXTUNE cmd
2026-01-29 02:28:15.446 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETRXGAIN
2026-01-29 02:28:15.446 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETRXGAIN
2026-01-29 02:28:15.446 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETTSC
2026-01-29 02:28:15.446 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETRXGAIN
2026-01-29 02:28:15.446 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:28:15.446 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:28:15.446 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.28.20:5700) Recv NOMTXPOWER cmd
2026-01-29 02:28:15.446 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:28:15.446 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:28:15.446 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:28:15.446 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.28.20:5700) Recv POWERON CMD
2026-01-29 02:28:15.446 [INFO] ctrl_if_trx.py:109 (BTS@172.18.28.20:5700) Starting transceiver...
2026-01-29 02:28:15.446 [INFO] transceiver.py:243 Starting clock generator
2026-01-29 02:28:15.447 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-01-29 02:28:15.447 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:28:15.447 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:28:15.447 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:28:15.447 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETRXGAIN
2026-01-29 02:28:15.447 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:28:15.447 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:28:15.447 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:28:15.447 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:28:15.448 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:28:15.448 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:28:15.448 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:28:15.448 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:28:15.448 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:28:15.448 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:28:15.448 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:28:15.448 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:28:15.448 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:28:15.448 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:28:15.448 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:28:15.448 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:28:15.448 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:28:15.448 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:28:15.449 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:28:15.449 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:28:15.449 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:28:15.449 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:28:15.449 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:28:15.449 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:28:15.449 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:28:15.449 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 02:28:15.449 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:28:15.449 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.28.20:5700) Recv POWEROFF cmd
2026-01-29 02:28:15.449 [INFO] ctrl_if_trx.py:117 (BTS@172.18.28.20:5700) Stopping transceiver...
2026-01-29 02:28:15.449 [INFO] transceiver.py:246 Stopping clock generator
2026-01-29 02:28:15.449 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:28:20.452 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.28.20:5700) Recv POWEROFF cmd
2026-01-29 02:28:20.452 [INFO] ctrl_if_trx.py:117 (BTS@172.18.28.20:5700) Stopping transceiver...
2026-01-29 02:28:20.454 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:28:20.455 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:28:20.455 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:28:20.456 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 02:28:20.462 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 02:28:20.463 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.28.20:5700) Recv SETFORMAT cmd
2026-01-29 02:28:20.463 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.28.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:28:20.464 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.28.20:5700) Recv SETFORMAT cmd
2026-01-29 02:28:20.464 [INFO] ctrl_if_trx.py:201 (BTS@172.18.28.20:5700) TRXD header version 1 -> 1
2026-01-29 02:28:20.466 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.28.20:5700/1) Recv RXTUNE cmd
2026-01-29 02:28:20.466 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.28.20:5700/1) Recv TXTUNE cmd
2026-01-29 02:28:20.466 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.28.20:5700/1) Recv SETFORMAT cmd
2026-01-29 02:28:20.467 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.28.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:28:20.467 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:28:20.467 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.28.20:5700/1) Recv NOMTXPOWER cmd
2026-01-29 02:28:20.467 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.28.20:5700/1) Recv SETFORMAT cmd
2026-01-29 02:28:20.467 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.28.20:5700/1) TRXD header version 1 -> 1
2026-01-29 02:28:20.468 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.28.20:5700/2) Recv RXTUNE cmd
2026-01-29 02:28:20.469 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.28.20:5700/2) Recv TXTUNE cmd
2026-01-29 02:28:20.469 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.28.20:5700/2) Recv SETFORMAT cmd
2026-01-29 02:28:20.469 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.28.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:28:20.469 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:28:20.470 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.28.20:5700/2) Recv NOMTXPOWER cmd
2026-01-29 02:28:20.470 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.28.20:5700/2) Recv SETFORMAT cmd
2026-01-29 02:28:20.470 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.28.20:5700/2) TRXD header version 1 -> 1
2026-01-29 02:28:20.471 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.28.20:5700/3) Recv RXTUNE cmd
2026-01-29 02:28:20.471 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.28.20:5700/3) Recv TXTUNE cmd
2026-01-29 02:28:20.471 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.28.20:5700/3) Recv SETFORMAT cmd
2026-01-29 02:28:20.471 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.28.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:28:20.471 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:28:20.471 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.28.20:5700/3) Recv NOMTXPOWER cmd
2026-01-29 02:28:20.471 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.28.20:5700/3) Recv SETFORMAT cmd
2026-01-29 02:28:20.471 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.28.20:5700/3) TRXD header version 1 -> 1
2026-01-29 02:28:20.473 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.28.20:5700) Recv RXTUNE cmd
2026-01-29 02:28:20.473 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETTSC
2026-01-29 02:28:20.473 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETTSC
2026-01-29 02:28:20.473 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETTSC
2026-01-29 02:28:20.473 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.28.20:5700) Recv TXTUNE cmd
2026-01-29 02:28:20.473 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETRXGAIN
2026-01-29 02:28:20.474 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETRXGAIN
2026-01-29 02:28:20.474 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETRXGAIN
2026-01-29 02:28:20.474 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETTSC
2026-01-29 02:28:20.474 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:28:20.474 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:28:20.474 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:28:20.474 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.28.20:5700) Recv NOMTXPOWER cmd
2026-01-29 02:28:20.474 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:28:20.474 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:28:20.474 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.28.20:5700) Recv POWERON CMD
2026-01-29 02:28:20.474 [INFO] ctrl_if_trx.py:109 (BTS@172.18.28.20:5700) Starting transceiver...
2026-01-29 02:28:20.474 [INFO] transceiver.py:243 Starting clock generator
2026-01-29 02:28:20.474 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-01-29 02:28:20.474 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:28:20.474 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:28:20.474 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:28:20.474 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETRXGAIN
2026-01-29 02:28:20.474 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:28:20.474 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:28:20.474 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:28:20.474 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:28:20.474 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:28:20.475 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:28:20.475 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:28:20.475 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:28:20.475 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:28:20.475 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:28:20.475 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:28:20.475 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:28:20.475 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:28:20.475 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:28:20.475 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:28:20.475 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:28:20.475 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:28:20.475 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:28:20.475 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:28:20.475 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:28:20.475 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:28:20.475 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:28:20.475 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:28:20.475 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:28:20.479 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-01-29 02:28:20.960 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-01-29 02:28:21.007 [DEBUG] fake_trx.py:278 (BTS@172.18.28.20:5700) Recv FAKE_TOA cmd
2026-01-29 02:28:21.009 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:28:21.009 [DEBUG] fake_trx.py:297 (BTS@172.18.28.20:5700) Recv FAKE_RSSI cmd
2026-01-29 02:28:21.011 [DEBUG] fake_trx.py:322 (BTS@172.18.28.20:5700) Recv FAKE_CI cmd
2026-01-29 02:28:21.034 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 02:28:21.034 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 02:28:21.035 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 02:28:21.060 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 02:28:21.061 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 02:28:21.061 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 02:28:21.062 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:28:21.068 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:28:21.068 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 02:28:21.068 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 02:28:21.069 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.28.22:6700) Recv POWERON CMD
2026-01-29 02:28:21.069 [INFO] ctrl_if_trx.py:109 (MS@172.18.28.22:6700) Starting transceiver...
2026-01-29 02:28:21.098 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 02:28:21.098 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 02:28:21.098 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:28:21.099 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:28:21.296 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:28:21.297 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:28:21.301 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 02:28:21.301 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 02:28:21.312 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:28:21.313 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 02:28:21.313 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 02:28:21.313 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 02:28:21.316 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:28:21.316 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 02:28:21.316 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 02:28:21.317 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.28.22:6700) Recv POWERON CMD
2026-01-29 02:28:21.317 [INFO] ctrl_if_trx.py:109 (MS@172.18.28.22:6700) Starting transceiver...
2026-01-29 02:28:21.331 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 02:28:21.331 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 02:28:21.331 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:28:21.331 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:28:21.437 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-01-29 02:28:21.477 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 02:28:21.477 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:28:21.478 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:28:21.480 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:28:21.542 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:28:21.542 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:28:21.546 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 02:28:21.546 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 02:28:21.560 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:28:21.561 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 02:28:21.561 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 02:28:21.561 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 02:28:21.563 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:28:21.563 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 02:28:21.563 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 02:28:21.563 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.28.22:6700) Recv POWERON CMD
2026-01-29 02:28:21.563 [INFO] ctrl_if_trx.py:109 (MS@172.18.28.22:6700) Starting transceiver...
2026-01-29 02:28:21.571 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 02:28:21.572 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 02:28:21.572 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:28:21.572 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:28:21.782 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:28:21.782 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:28:21.786 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 02:28:21.786 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 02:28:21.803 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 02:28:21.803 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 02:28:21.803 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 02:28:21.809 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 02:28:21.809 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 02:28:21.809 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 02:28:21.810 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:28:21.811 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:28:21.811 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 02:28:21.811 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 02:28:21.811 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.28.22:6700) Recv POWERON CMD
2026-01-29 02:28:21.811 [INFO] ctrl_if_trx.py:109 (MS@172.18.28.22:6700) Starting transceiver...
2026-01-29 02:28:21.856 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 02:28:21.856 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 02:28:21.856 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:28:21.857 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:28:21.909 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-01-29 02:28:22.160 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:28:22.161 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:28:22.165 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 02:28:22.165 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 02:28:22.179 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:28:22.179 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 02:28:22.179 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 02:28:22.180 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 02:28:22.181 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:28:22.181 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 02:28:22.181 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 02:28:22.181 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.28.22:6700) Recv POWERON CMD
2026-01-29 02:28:22.181 [INFO] ctrl_if_trx.py:109 (MS@172.18.28.22:6700) Starting transceiver...
2026-01-29 02:28:22.185 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 02:28:22.185 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 02:28:22.185 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:28:22.185 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:28:22.383 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-01-29 02:28:22.478 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 02:28:22.478 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:28:22.480 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:28:22.481 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:28:22.484 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:28:22.484 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:28:22.488 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 02:28:22.488 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 02:28:22.502 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:28:22.503 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 02:28:22.503 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 02:28:22.503 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 02:28:22.505 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:28:22.505 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 02:28:22.505 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 02:28:22.505 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.28.22:6700) Recv POWERON CMD
2026-01-29 02:28:22.505 [INFO] ctrl_if_trx.py:109 (MS@172.18.28.22:6700) Starting transceiver...
2026-01-29 02:28:22.513 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 02:28:22.513 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 02:28:22.513 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:28:22.513 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:28:22.802 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:28:22.803 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:28:22.806 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 02:28:22.807 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 02:28:22.817 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 02:28:22.818 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 02:28:22.818 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 02:28:22.823 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 02:28:22.823 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 02:28:22.823 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 02:28:22.824 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:28:22.825 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:28:22.825 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 02:28:22.825 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 02:28:22.825 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.28.22:6700) Recv POWERON CMD
2026-01-29 02:28:22.825 [INFO] ctrl_if_trx.py:109 (MS@172.18.28.22:6700) Starting transceiver...
2026-01-29 02:28:22.847 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 02:28:22.847 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 02:28:22.847 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:28:22.847 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:28:22.859 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-01-29 02:28:23.336 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-01-29 02:28:23.479 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 02:28:23.479 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:28:23.481 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:28:23.481 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:28:23.814 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-01-29 02:28:24.291 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-01-29 02:28:24.480 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:28:24.480 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 02:28:24.481 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:28:24.482 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:28:24.769 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-01-29 02:28:25.247 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-01-29 02:28:25.403 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:28:25.404 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:28:25.408 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 02:28:25.408 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 02:28:25.424 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:28:25.424 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 02:28:25.424 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 02:28:25.424 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 02:28:25.426 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:28:25.426 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 02:28:25.426 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 02:28:25.426 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.28.22:6700) Recv POWERON CMD
2026-01-29 02:28:25.426 [INFO] ctrl_if_trx.py:109 (MS@172.18.28.22:6700) Starting transceiver...
2026-01-29 02:28:25.428 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 02:28:25.428 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 02:28:25.428 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:28:25.428 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:28:25.480 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:28:25.480 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 02:28:25.482 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:28:25.482 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:28:25.723 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-01-29 02:28:26.202 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-01-29 02:28:26.679 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-01-29 02:28:27.156 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-01-29 02:28:27.633 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-01-29 02:28:28.024 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:28:28.025 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:28:28.029 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 02:28:28.029 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 02:28:28.045 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:28:28.046 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 02:28:28.046 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 02:28:28.047 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 02:28:28.048 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:28:28.048 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 02:28:28.048 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 02:28:28.048 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.28.22:6700) Recv POWERON CMD
2026-01-29 02:28:28.048 [INFO] ctrl_if_trx.py:109 (MS@172.18.28.22:6700) Starting transceiver...
2026-01-29 02:28:28.050 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 02:28:28.050 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 02:28:28.050 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:28:28.050 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:28:28.111 [DEBUG] clck_gen.py:113 IND CLOCK 1632
2026-01-29 02:28:28.588 [DEBUG] clck_gen.py:113 IND CLOCK 1734
2026-01-29 02:28:29.065 [DEBUG] clck_gen.py:113 IND CLOCK 1836
2026-01-29 02:28:29.542 [DEBUG] clck_gen.py:113 IND CLOCK 1938
2026-01-29 02:28:30.020 [DEBUG] clck_gen.py:113 IND CLOCK 2040
2026-01-29 02:28:30.498 [DEBUG] clck_gen.py:113 IND CLOCK 2142
2026-01-29 02:28:30.654 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:28:30.655 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:28:30.659 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 02:28:30.659 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 02:28:30.677 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 02:28:30.677 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 02:28:30.678 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 02:28:30.684 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 02:28:30.684 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 02:28:30.684 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 02:28:30.684 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:28:30.685 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:28:30.685 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 02:28:30.685 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 02:28:30.685 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.28.22:6700) Recv POWERON CMD
2026-01-29 02:28:30.685 [INFO] ctrl_if_trx.py:109 (MS@172.18.28.22:6700) Starting transceiver...
2026-01-29 02:28:30.732 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 02:28:30.733 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 02:28:30.733 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:28:30.733 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:28:30.974 [DEBUG] clck_gen.py:113 IND CLOCK 2244
2026-01-29 02:28:31.451 [DEBUG] clck_gen.py:113 IND CLOCK 2346
2026-01-29 02:28:31.929 [DEBUG] clck_gen.py:113 IND CLOCK 2448
2026-01-29 02:28:32.408 [DEBUG] clck_gen.py:113 IND CLOCK 2550
2026-01-29 02:28:32.885 [DEBUG] clck_gen.py:113 IND CLOCK 2652
2026-01-29 02:28:33.203 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:28:33.204 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:28:33.207 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 02:28:33.208 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 02:28:33.221 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:28:33.222 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 02:28:33.222 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 02:28:33.223 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 02:28:33.224 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:28:33.224 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 02:28:33.224 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 02:28:33.224 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.28.22:6700) Recv POWERON CMD
2026-01-29 02:28:33.224 [INFO] ctrl_if_trx.py:109 (MS@172.18.28.22:6700) Starting transceiver...
2026-01-29 02:28:33.258 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 02:28:33.259 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 02:28:33.259 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:28:33.259 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:28:33.363 [DEBUG] clck_gen.py:113 IND CLOCK 2754
2026-01-29 02:28:33.841 [DEBUG] clck_gen.py:113 IND CLOCK 2856
2026-01-29 02:28:34.318 [DEBUG] clck_gen.py:113 IND CLOCK 2958
2026-01-29 02:28:34.795 [DEBUG] clck_gen.py:113 IND CLOCK 3060
2026-01-29 02:28:35.274 [DEBUG] clck_gen.py:113 IND CLOCK 3162
2026-01-29 02:28:35.751 [DEBUG] clck_gen.py:113 IND CLOCK 3264
2026-01-29 02:28:35.834 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:28:35.834 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:28:35.838 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 02:28:35.838 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 02:28:35.854 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:28:35.856 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 02:28:35.856 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 02:28:35.856 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 02:28:35.858 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:28:35.858 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 02:28:35.858 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 02:28:35.858 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.28.22:6700) Recv POWERON CMD
2026-01-29 02:28:35.858 [INFO] ctrl_if_trx.py:109 (MS@172.18.28.22:6700) Starting transceiver...
2026-01-29 02:28:35.891 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 02:28:35.891 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 02:28:35.892 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:28:35.892 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:28:36.229 [DEBUG] clck_gen.py:113 IND CLOCK 3366
2026-01-29 02:28:36.706 [DEBUG] clck_gen.py:113 IND CLOCK 3468
2026-01-29 02:28:37.184 [DEBUG] clck_gen.py:113 IND CLOCK 3570
2026-01-29 02:28:37.662 [DEBUG] clck_gen.py:113 IND CLOCK 3672
2026-01-29 02:28:38.139 [DEBUG] clck_gen.py:113 IND CLOCK 3774
2026-01-29 02:28:38.457 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:28:38.458 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:28:38.463 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 02:28:38.463 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 02:28:38.475 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 02:28:38.476 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:28:38.476 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:28:38.476 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:28:38.482 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 02:28:38.482 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:28:38.482 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:28:38.482 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:28:38.482 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.28.20:5700) Recv POWEROFF cmd
2026-01-29 02:28:38.482 [INFO] ctrl_if_trx.py:117 (BTS@172.18.28.20:5700) Stopping transceiver...
2026-01-29 02:28:38.483 [INFO] transceiver.py:246 Stopping clock generator
2026-01-29 02:28:38.483 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=3848 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:28:38.483 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=3848 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:28:43.483 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.28.20:5700) Recv POWEROFF cmd
2026-01-29 02:28:43.483 [INFO] ctrl_if_trx.py:117 (BTS@172.18.28.20:5700) Stopping transceiver...
2026-01-29 02:28:43.483 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:28:43.483 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:28:43.483 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:28:43.483 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 02:28:43.491 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 02:28:43.493 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.28.20:5700) Recv SETFORMAT cmd
2026-01-29 02:28:43.493 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.28.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:28:43.494 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.28.20:5700) Recv SETFORMAT cmd
2026-01-29 02:28:43.494 [INFO] ctrl_if_trx.py:201 (BTS@172.18.28.20:5700) TRXD header version 1 -> 1
2026-01-29 02:28:43.498 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.28.20:5700/1) Recv RXTUNE cmd
2026-01-29 02:28:43.499 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.28.20:5700/1) Recv TXTUNE cmd
2026-01-29 02:28:43.499 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.28.20:5700/1) Recv SETFORMAT cmd
2026-01-29 02:28:43.499 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.28.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:28:43.500 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:28:43.500 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.28.20:5700/1) Recv NOMTXPOWER cmd
2026-01-29 02:28:43.501 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.28.20:5700/1) Recv SETFORMAT cmd
2026-01-29 02:28:43.501 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.28.20:5700/1) TRXD header version 1 -> 1
2026-01-29 02:28:43.502 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.28.20:5700/2) Recv RXTUNE cmd
2026-01-29 02:28:43.502 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.28.20:5700/2) Recv TXTUNE cmd
2026-01-29 02:28:43.503 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.28.20:5700/2) Recv SETFORMAT cmd
2026-01-29 02:28:43.503 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.28.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:28:43.503 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:28:43.503 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.28.20:5700/2) Recv NOMTXPOWER cmd
2026-01-29 02:28:43.503 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.28.20:5700/2) Recv SETFORMAT cmd
2026-01-29 02:28:43.503 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.28.20:5700/2) TRXD header version 1 -> 1
2026-01-29 02:28:43.505 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.28.20:5700/3) Recv RXTUNE cmd
2026-01-29 02:28:43.505 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.28.20:5700/3) Recv TXTUNE cmd
2026-01-29 02:28:43.505 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.28.20:5700/3) Recv SETFORMAT cmd
2026-01-29 02:28:43.505 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.28.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:28:43.505 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:28:43.505 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.28.20:5700/3) Recv NOMTXPOWER cmd
2026-01-29 02:28:43.505 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.28.20:5700/3) Recv SETFORMAT cmd
2026-01-29 02:28:43.505 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.28.20:5700/3) TRXD header version 1 -> 1
2026-01-29 02:28:43.508 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.28.20:5700) Recv RXTUNE cmd
2026-01-29 02:28:43.508 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETTSC
2026-01-29 02:28:43.508 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETTSC
2026-01-29 02:28:43.508 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETTSC
2026-01-29 02:28:43.508 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.28.20:5700) Recv TXTUNE cmd
2026-01-29 02:28:43.508 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETRXGAIN
2026-01-29 02:28:43.508 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETRXGAIN
2026-01-29 02:28:43.508 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETRXGAIN
2026-01-29 02:28:43.508 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETTSC
2026-01-29 02:28:43.509 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:28:43.509 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:28:43.509 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:28:43.509 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.28.20:5700) Recv NOMTXPOWER cmd
2026-01-29 02:28:43.509 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:28:43.509 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:28:43.509 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:28:43.509 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.28.20:5700) Recv POWERON CMD
2026-01-29 02:28:43.509 [INFO] ctrl_if_trx.py:109 (BTS@172.18.28.20:5700) Starting transceiver...
2026-01-29 02:28:43.509 [INFO] transceiver.py:243 Starting clock generator
2026-01-29 02:28:43.509 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-01-29 02:28:43.509 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:28:43.509 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:28:43.509 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:28:43.509 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETRXGAIN
2026-01-29 02:28:43.509 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:28:43.509 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:28:43.509 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:28:43.509 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:28:43.510 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:28:43.510 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:28:43.510 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:28:43.510 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:28:43.510 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:28:43.510 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:28:43.510 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:28:43.510 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:28:43.510 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:28:43.510 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:28:43.510 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:28:43.510 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:28:43.510 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:28:43.510 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:28:43.510 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:28:43.510 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:28:43.510 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:28:43.510 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:28:43.510 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:28:43.514 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-01-29 02:28:43.994 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-01-29 02:28:44.037 [DEBUG] fake_trx.py:278 (BTS@172.18.28.20:5700) Recv FAKE_TOA cmd
2026-01-29 02:28:44.038 [DEBUG] fake_trx.py:297 (BTS@172.18.28.20:5700) Recv FAKE_RSSI cmd
2026-01-29 02:28:44.039 [DEBUG] fake_trx.py:322 (BTS@172.18.28.20:5700) Recv FAKE_CI cmd
2026-01-29 02:28:44.040 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:28:44.063 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 02:28:44.063 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 02:28:44.063 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 02:28:44.086 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 02:28:44.086 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 02:28:44.086 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 02:28:44.088 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:28:44.095 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:28:44.095 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 02:28:44.095 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 02:28:44.095 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.28.22:6700) Recv POWERON CMD
2026-01-29 02:28:44.095 [INFO] ctrl_if_trx.py:109 (MS@172.18.28.22:6700) Starting transceiver...
2026-01-29 02:28:44.132 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 02:28:44.132 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 02:28:44.132 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:28:44.133 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:28:44.470 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-01-29 02:28:44.512 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 02:28:44.513 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:28:44.513 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:28:44.516 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:28:44.948 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-01-29 02:28:45.426 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-01-29 02:28:45.513 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 02:28:45.514 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:28:45.515 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:28:45.517 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:28:45.905 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-01-29 02:28:46.382 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-01-29 02:28:46.513 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 02:28:46.515 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:28:46.515 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:28:46.518 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:28:46.861 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-01-29 02:28:47.243 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:28:47.245 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:28:47.249 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 02:28:47.249 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 02:28:47.268 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 02:28:47.268 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 02:28:47.269 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 02:28:47.275 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 02:28:47.275 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 02:28:47.275 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 02:28:47.275 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:28:47.277 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:28:47.277 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 02:28:47.277 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 02:28:47.277 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.28.22:6700) Recv POWERON CMD
2026-01-29 02:28:47.277 [INFO] ctrl_if_trx.py:109 (MS@172.18.28.22:6700) Starting transceiver...
2026-01-29 02:28:47.331 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 02:28:47.331 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 02:28:47.332 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:28:47.332 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:28:47.337 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-01-29 02:28:47.514 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 02:28:47.516 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:28:47.516 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:28:47.519 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:28:47.814 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-01-29 02:28:48.292 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-01-29 02:28:48.515 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 02:28:48.517 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:28:48.517 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:28:48.519 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:28:48.771 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-01-29 02:28:49.249 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-01-29 02:28:49.727 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-01-29 02:28:50.206 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-01-29 02:28:50.535 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:28:50.536 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:28:50.539 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 02:28:50.539 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 02:28:50.558 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 02:28:50.558 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 02:28:50.559 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 02:28:50.565 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 02:28:50.565 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 02:28:50.565 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 02:28:50.565 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:28:50.566 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:28:50.566 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 02:28:50.566 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 02:28:50.566 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.28.22:6700) Recv POWERON CMD
2026-01-29 02:28:50.566 [INFO] ctrl_if_trx.py:109 (MS@172.18.28.22:6700) Starting transceiver...
2026-01-29 02:28:50.576 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 02:28:50.576 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 02:28:50.577 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:28:50.577 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:28:50.682 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-01-29 02:28:51.160 [DEBUG] clck_gen.py:113 IND CLOCK 1632
2026-01-29 02:28:51.638 [DEBUG] clck_gen.py:113 IND CLOCK 1734
2026-01-29 02:28:52.116 [DEBUG] clck_gen.py:113 IND CLOCK 1836
2026-01-29 02:28:52.594 [DEBUG] clck_gen.py:113 IND CLOCK 1938
2026-01-29 02:28:53.072 [DEBUG] clck_gen.py:113 IND CLOCK 2040
2026-01-29 02:28:53.549 [DEBUG] clck_gen.py:113 IND CLOCK 2142
2026-01-29 02:28:53.909 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:28:53.911 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:28:53.914 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 02:28:53.914 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 02:28:53.934 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 02:28:53.934 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 02:28:53.934 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 02:28:53.940 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 02:28:53.940 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 02:28:53.941 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 02:28:53.941 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:28:53.942 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:28:53.942 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 02:28:53.942 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 02:28:53.942 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.28.22:6700) Recv POWERON CMD
2026-01-29 02:28:53.942 [INFO] ctrl_if_trx.py:109 (MS@172.18.28.22:6700) Starting transceiver...
2026-01-29 02:28:53.968 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 02:28:53.968 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 02:28:53.968 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:28:53.968 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:28:54.025 [DEBUG] clck_gen.py:113 IND CLOCK 2244
2026-01-29 02:28:54.504 [DEBUG] clck_gen.py:113 IND CLOCK 2346
2026-01-29 02:28:54.982 [DEBUG] clck_gen.py:113 IND CLOCK 2448
2026-01-29 02:28:55.461 [DEBUG] clck_gen.py:113 IND CLOCK 2550
2026-01-29 02:28:55.939 [DEBUG] clck_gen.py:113 IND CLOCK 2652
2026-01-29 02:28:56.417 [DEBUG] clck_gen.py:113 IND CLOCK 2754
2026-01-29 02:28:56.896 [DEBUG] clck_gen.py:113 IND CLOCK 2856
2026-01-29 02:28:57.179 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:28:57.180 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:28:57.184 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 02:28:57.184 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 02:28:57.198 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 02:28:57.198 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:28:57.198 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:28:57.198 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:28:57.200 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 02:28:57.200 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:28:57.200 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:28:57.200 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.28.20:5700) Recv POWEROFF cmd
2026-01-29 02:28:57.200 [INFO] ctrl_if_trx.py:117 (BTS@172.18.28.20:5700) Stopping transceiver...
2026-01-29 02:28:57.200 [INFO] transceiver.py:246 Stopping clock generator
2026-01-29 02:28:57.200 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:29:02.200 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.28.20:5700) Recv POWEROFF cmd
2026-01-29 02:29:02.200 [INFO] ctrl_if_trx.py:117 (BTS@172.18.28.20:5700) Stopping transceiver...
2026-01-29 02:29:02.202 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:29:02.202 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:29:02.203 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:29:02.203 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 02:29:02.206 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 02:29:02.206 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.28.20:5700) Recv SETFORMAT cmd
2026-01-29 02:29:02.206 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.28.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:29:02.206 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.28.20:5700) Recv SETFORMAT cmd
2026-01-29 02:29:02.206 [INFO] ctrl_if_trx.py:201 (BTS@172.18.28.20:5700) TRXD header version 1 -> 1
2026-01-29 02:29:02.207 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.28.20:5700/1) Recv RXTUNE cmd
2026-01-29 02:29:02.207 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.28.20:5700/1) Recv TXTUNE cmd
2026-01-29 02:29:02.207 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.28.20:5700/1) Recv SETFORMAT cmd
2026-01-29 02:29:02.207 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.28.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:29:02.207 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:29:02.207 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.28.20:5700/1) Recv NOMTXPOWER cmd
2026-01-29 02:29:02.208 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.28.20:5700/1) Recv SETFORMAT cmd
2026-01-29 02:29:02.208 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.28.20:5700/1) TRXD header version 1 -> 1
2026-01-29 02:29:02.208 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.28.20:5700/2) Recv RXTUNE cmd
2026-01-29 02:29:02.208 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.28.20:5700/2) Recv TXTUNE cmd
2026-01-29 02:29:02.208 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.28.20:5700/2) Recv SETFORMAT cmd
2026-01-29 02:29:02.208 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.28.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:29:02.208 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:29:02.208 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.28.20:5700/2) Recv NOMTXPOWER cmd
2026-01-29 02:29:02.208 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.28.20:5700/2) Recv SETFORMAT cmd
2026-01-29 02:29:02.208 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.28.20:5700/2) TRXD header version 1 -> 1
2026-01-29 02:29:02.209 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.28.20:5700/3) Recv RXTUNE cmd
2026-01-29 02:29:02.209 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.28.20:5700/3) Recv TXTUNE cmd
2026-01-29 02:29:02.209 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.28.20:5700/3) Recv SETFORMAT cmd
2026-01-29 02:29:02.209 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.28.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:29:02.209 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:29:02.209 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.28.20:5700/3) Recv NOMTXPOWER cmd
2026-01-29 02:29:02.209 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.28.20:5700/3) Recv SETFORMAT cmd
2026-01-29 02:29:02.209 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.28.20:5700/3) TRXD header version 1 -> 1
2026-01-29 02:29:02.211 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.28.20:5700) Recv RXTUNE cmd
2026-01-29 02:29:02.211 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETTSC
2026-01-29 02:29:02.211 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETTSC
2026-01-29 02:29:02.211 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETTSC
2026-01-29 02:29:02.211 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.28.20:5700) Recv TXTUNE cmd
2026-01-29 02:29:02.211 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETRXGAIN
2026-01-29 02:29:02.211 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETRXGAIN
2026-01-29 02:29:02.211 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETRXGAIN
2026-01-29 02:29:02.211 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETTSC
2026-01-29 02:29:02.211 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:29:02.211 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:29:02.211 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:29:02.211 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.28.20:5700) Recv NOMTXPOWER cmd
2026-01-29 02:29:02.211 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:29:02.211 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:29:02.211 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:29:02.211 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.28.20:5700) Recv POWERON CMD
2026-01-29 02:29:02.211 [INFO] ctrl_if_trx.py:109 (BTS@172.18.28.20:5700) Starting transceiver...
2026-01-29 02:29:02.211 [INFO] transceiver.py:243 Starting clock generator
2026-01-29 02:29:02.211 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-01-29 02:29:02.211 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:29:02.211 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:29:02.211 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:29:02.211 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETRXGAIN
2026-01-29 02:29:02.211 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:29:02.211 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:29:02.211 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:29:02.211 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:29:02.211 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:29:02.211 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:29:02.211 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:29:02.212 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:29:02.212 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:29:02.212 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:29:02.212 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:29:02.212 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:29:02.212 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:29:02.212 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:29:02.212 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:29:02.212 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:29:02.212 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:29:02.212 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:29:02.212 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:29:02.212 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:29:02.212 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:29:02.212 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:29:02.212 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:29:02.216 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-01-29 02:29:02.700 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-01-29 02:29:02.735 [DEBUG] fake_trx.py:278 (BTS@172.18.28.20:5700) Recv FAKE_TOA cmd
2026-01-29 02:29:02.737 [DEBUG] fake_trx.py:297 (BTS@172.18.28.20:5700) Recv FAKE_RSSI cmd
2026-01-29 02:29:02.737 [DEBUG] fake_trx.py:322 (BTS@172.18.28.20:5700) Recv FAKE_CI cmd
2026-01-29 02:29:02.737 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:29:02.757 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 02:29:02.757 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 02:29:02.758 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 02:29:02.782 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 02:29:02.783 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 02:29:02.783 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 02:29:02.785 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:29:02.791 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:29:02.792 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 02:29:02.792 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 02:29:02.792 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.28.22:6700) Recv POWERON CMD
2026-01-29 02:29:02.792 [INFO] ctrl_if_trx.py:109 (MS@172.18.28.22:6700) Starting transceiver...
2026-01-29 02:29:02.838 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 02:29:02.838 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 02:29:02.838 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:29:02.838 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:29:03.155 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:29:03.156 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:29:03.160 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 02:29:03.160 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 02:29:03.176 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-01-29 02:29:03.178 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 02:29:03.178 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 02:29:03.178 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 02:29:03.184 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 02:29:03.184 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 02:29:03.184 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 02:29:03.185 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:29:03.186 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:29:03.186 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 02:29:03.186 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 02:29:03.186 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.28.22:6700) Recv POWERON CMD
2026-01-29 02:29:03.186 [INFO] ctrl_if_trx.py:109 (MS@172.18.28.22:6700) Starting transceiver...
2026-01-29 02:29:03.213 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 02:29:03.214 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:29:03.214 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:29:03.216 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:29:03.221 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 02:29:03.222 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 02:29:03.222 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:29:03.222 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:29:03.650 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-01-29 02:29:03.701 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:29:03.703 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:29:03.707 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 02:29:03.707 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 02:29:03.726 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 02:29:03.726 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 02:29:03.726 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 02:29:03.732 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 02:29:03.732 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 02:29:03.732 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 02:29:03.732 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:29:03.734 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:29:03.734 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 02:29:03.734 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 02:29:03.734 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.28.22:6700) Recv POWERON CMD
2026-01-29 02:29:03.734 [INFO] ctrl_if_trx.py:109 (MS@172.18.28.22:6700) Starting transceiver...
2026-01-29 02:29:03.735 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 02:29:03.735 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 02:29:03.735 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:29:03.735 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:29:04.125 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-01-29 02:29:04.214 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 02:29:04.214 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:29:04.215 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:29:04.217 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:29:04.603 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-01-29 02:29:05.080 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-01-29 02:29:05.215 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 02:29:05.215 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:29:05.215 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:29:05.218 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:29:05.558 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-01-29 02:29:06.036 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-01-29 02:29:06.216 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 02:29:06.216 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:29:06.216 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:29:06.219 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:29:06.513 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-01-29 02:29:06.669 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:29:06.669 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:29:06.673 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 02:29:06.673 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 02:29:06.685 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 02:29:06.685 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 02:29:06.685 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 02:29:06.690 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 02:29:06.690 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 02:29:06.690 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 02:29:06.691 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:29:06.692 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:29:06.692 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 02:29:06.692 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 02:29:06.692 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.28.22:6700) Recv POWERON CMD
2026-01-29 02:29:06.692 [INFO] ctrl_if_trx.py:109 (MS@172.18.28.22:6700) Starting transceiver...
2026-01-29 02:29:06.694 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 02:29:06.694 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 02:29:06.694 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:29:06.694 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:29:06.989 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-01-29 02:29:07.216 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:29:07.217 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 02:29:07.217 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:29:07.220 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:29:07.468 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-01-29 02:29:07.946 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-01-29 02:29:08.423 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-01-29 02:29:08.898 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-01-29 02:29:09.376 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-01-29 02:29:09.693 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:29:09.695 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:29:09.698 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 02:29:09.699 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 02:29:09.711 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 02:29:09.711 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:29:09.711 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:29:09.711 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:29:09.717 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 02:29:09.717 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:29:09.717 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:29:09.717 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:29:09.718 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.28.20:5700) Recv POWEROFF cmd
2026-01-29 02:29:09.718 [INFO] ctrl_if_trx.py:117 (BTS@172.18.28.20:5700) Stopping transceiver...
2026-01-29 02:29:09.718 [INFO] transceiver.py:246 Stopping clock generator
2026-01-29 02:29:09.718 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=1605 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:29:09.718 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=1605 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:29:09.718 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=1605 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:29:09.718 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=1605 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:29:14.712 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.28.20:5700) Recv POWEROFF cmd
2026-01-29 02:29:14.712 [INFO] ctrl_if_trx.py:117 (BTS@172.18.28.20:5700) Stopping transceiver...
2026-01-29 02:29:14.714 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:29:14.715 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:29:14.716 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:29:14.717 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 02:29:14.726 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 02:29:14.727 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.28.20:5700) Recv SETFORMAT cmd
2026-01-29 02:29:14.727 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.28.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:29:14.728 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.28.20:5700) Recv SETFORMAT cmd
2026-01-29 02:29:14.728 [INFO] ctrl_if_trx.py:201 (BTS@172.18.28.20:5700) TRXD header version 1 -> 1
2026-01-29 02:29:14.733 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.28.20:5700/1) Recv RXTUNE cmd
2026-01-29 02:29:14.734 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.28.20:5700/1) Recv TXTUNE cmd
2026-01-29 02:29:14.734 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.28.20:5700/1) Recv SETFORMAT cmd
2026-01-29 02:29:14.735 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.28.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:29:14.735 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:29:14.736 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.28.20:5700/1) Recv NOMTXPOWER cmd
2026-01-29 02:29:14.736 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.28.20:5700/1) Recv SETFORMAT cmd
2026-01-29 02:29:14.736 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.28.20:5700/1) TRXD header version 1 -> 1
2026-01-29 02:29:14.738 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.28.20:5700/2) Recv RXTUNE cmd
2026-01-29 02:29:14.739 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.28.20:5700/2) Recv TXTUNE cmd
2026-01-29 02:29:14.739 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.28.20:5700/2) Recv SETFORMAT cmd
2026-01-29 02:29:14.739 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.28.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:29:14.739 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:29:14.740 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.28.20:5700/2) Recv NOMTXPOWER cmd
2026-01-29 02:29:14.740 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.28.20:5700/2) Recv SETFORMAT cmd
2026-01-29 02:29:14.740 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.28.20:5700/2) TRXD header version 1 -> 1
2026-01-29 02:29:14.742 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.28.20:5700/3) Recv RXTUNE cmd
2026-01-29 02:29:14.743 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.28.20:5700/3) Recv TXTUNE cmd
2026-01-29 02:29:14.743 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.28.20:5700/3) Recv SETFORMAT cmd
2026-01-29 02:29:14.743 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.28.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:29:14.744 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:29:14.744 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.28.20:5700/3) Recv NOMTXPOWER cmd
2026-01-29 02:29:14.744 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.28.20:5700/3) Recv SETFORMAT cmd
2026-01-29 02:29:14.744 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.28.20:5700/3) TRXD header version 1 -> 1
2026-01-29 02:29:14.747 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.28.20:5700) Recv RXTUNE cmd
2026-01-29 02:29:14.747 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETTSC
2026-01-29 02:29:14.747 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETTSC
2026-01-29 02:29:14.747 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETTSC
2026-01-29 02:29:14.747 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.28.20:5700) Recv TXTUNE cmd
2026-01-29 02:29:14.747 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETRXGAIN
2026-01-29 02:29:14.747 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETRXGAIN
2026-01-29 02:29:14.747 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETRXGAIN
2026-01-29 02:29:14.747 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETTSC
2026-01-29 02:29:14.748 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:29:14.748 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:29:14.748 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.28.20:5700) Recv NOMTXPOWER cmd
2026-01-29 02:29:14.748 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:29:14.748 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:29:14.748 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:29:14.748 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.28.20:5700) Recv POWERON CMD
2026-01-29 02:29:14.748 [INFO] ctrl_if_trx.py:109 (BTS@172.18.28.20:5700) Starting transceiver...
2026-01-29 02:29:14.748 [INFO] transceiver.py:243 Starting clock generator
2026-01-29 02:29:14.748 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-01-29 02:29:14.748 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:29:14.748 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:29:14.748 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:29:14.748 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETRXGAIN
2026-01-29 02:29:14.748 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:29:14.748 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:29:14.748 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:29:14.749 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:29:14.749 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:29:14.749 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:29:14.749 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:29:14.749 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:29:14.749 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:29:14.749 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:29:14.749 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:29:14.749 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:29:14.749 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:29:14.749 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:29:14.749 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:29:14.749 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:29:14.749 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:29:14.749 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:29:14.749 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:29:14.749 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:29:14.750 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:29:14.750 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:29:14.750 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:29:14.750 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:29:14.753 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-01-29 02:29:15.236 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-01-29 02:29:15.276 [DEBUG] fake_trx.py:278 (BTS@172.18.28.20:5700) Recv FAKE_TOA cmd
2026-01-29 02:29:15.278 [DEBUG] fake_trx.py:297 (BTS@172.18.28.20:5700) Recv FAKE_RSSI cmd
2026-01-29 02:29:15.280 [DEBUG] fake_trx.py:322 (BTS@172.18.28.20:5700) Recv FAKE_CI cmd
2026-01-29 02:29:15.281 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:29:15.301 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 02:29:15.301 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 02:29:15.302 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 02:29:15.322 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 02:29:15.322 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 02:29:15.322 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 02:29:15.324 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:29:15.331 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:29:15.331 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 02:29:15.332 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 02:29:15.332 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.28.22:6700) Recv POWERON CMD
2026-01-29 02:29:15.333 [INFO] ctrl_if_trx.py:109 (MS@172.18.28.22:6700) Starting transceiver...
2026-01-29 02:29:15.374 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 02:29:15.375 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 02:29:15.375 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:29:15.375 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:29:15.714 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-01-29 02:29:15.751 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 02:29:15.752 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:29:15.752 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:29:15.753 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:29:16.192 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-01-29 02:29:16.670 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-01-29 02:29:16.694 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:29:16.695 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:29:16.699 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 02:29:16.699 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 02:29:16.717 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 02:29:16.717 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 02:29:16.717 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 02:29:16.724 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 02:29:16.724 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 02:29:16.724 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 02:29:16.724 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:29:16.725 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:29:16.725 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 02:29:16.725 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 02:29:16.725 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.28.22:6700) Recv POWERON CMD
2026-01-29 02:29:16.725 [INFO] ctrl_if_trx.py:109 (MS@172.18.28.22:6700) Starting transceiver...
2026-01-29 02:29:16.753 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 02:29:16.753 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:29:16.753 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:29:16.753 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:29:16.762 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 02:29:16.762 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 02:29:16.762 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:29:16.762 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:29:17.148 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-01-29 02:29:17.626 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-01-29 02:29:17.753 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 02:29:17.753 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:29:17.754 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:29:17.754 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:29:18.104 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-01-29 02:29:18.582 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-01-29 02:29:18.754 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:29:18.754 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 02:29:18.755 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:29:18.755 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:29:18.906 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:29:18.907 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:29:18.910 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 02:29:18.910 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 02:29:18.928 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 02:29:18.928 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 02:29:18.929 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 02:29:18.935 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 02:29:18.935 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 02:29:18.935 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 02:29:18.935 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:29:18.936 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:29:18.936 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 02:29:18.936 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 02:29:18.936 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.28.22:6700) Recv POWERON CMD
2026-01-29 02:29:18.936 [INFO] ctrl_if_trx.py:109 (MS@172.18.28.22:6700) Starting transceiver...
2026-01-29 02:29:18.954 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 02:29:18.954 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 02:29:18.954 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:29:18.954 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:29:19.059 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-01-29 02:29:19.539 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-01-29 02:29:19.755 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:29:19.755 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:29:19.756 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 02:29:19.756 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:29:20.016 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-01-29 02:29:20.493 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-01-29 02:29:20.971 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-01-29 02:29:21.449 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-01-29 02:29:21.927 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-01-29 02:29:22.405 [DEBUG] clck_gen.py:113 IND CLOCK 1632
2026-01-29 02:29:22.882 [DEBUG] clck_gen.py:113 IND CLOCK 1734
2026-01-29 02:29:23.360 [DEBUG] clck_gen.py:113 IND CLOCK 1836
2026-01-29 02:29:23.822 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:29:23.823 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:29:23.827 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 02:29:23.827 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 02:29:23.837 [DEBUG] clck_gen.py:113 IND CLOCK 1938
2026-01-29 02:29:23.844 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 02:29:23.844 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 02:29:23.844 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 02:29:23.850 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 02:29:23.850 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 02:29:23.850 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 02:29:23.850 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:29:23.852 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:29:23.852 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 02:29:23.852 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 02:29:23.852 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.28.22:6700) Recv POWERON CMD
2026-01-29 02:29:23.852 [INFO] ctrl_if_trx.py:109 (MS@172.18.28.22:6700) Starting transceiver...
2026-01-29 02:29:23.882 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 02:29:23.883 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 02:29:23.883 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:29:23.883 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:29:24.313 [DEBUG] clck_gen.py:113 IND CLOCK 2040
2026-01-29 02:29:24.791 [DEBUG] clck_gen.py:113 IND CLOCK 2142
2026-01-29 02:29:25.269 [DEBUG] clck_gen.py:113 IND CLOCK 2244
2026-01-29 02:29:25.747 [DEBUG] clck_gen.py:113 IND CLOCK 2346
2026-01-29 02:29:26.224 [DEBUG] clck_gen.py:113 IND CLOCK 2448
2026-01-29 02:29:26.702 [DEBUG] clck_gen.py:113 IND CLOCK 2550
2026-01-29 02:29:27.179 [DEBUG] clck_gen.py:113 IND CLOCK 2652
2026-01-29 02:29:27.657 [DEBUG] clck_gen.py:113 IND CLOCK 2754
2026-01-29 02:29:28.135 [DEBUG] clck_gen.py:113 IND CLOCK 2856
2026-01-29 02:29:28.614 [DEBUG] clck_gen.py:113 IND CLOCK 2958
2026-01-29 02:29:28.767 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:29:28.767 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:29:28.771 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 02:29:28.772 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 02:29:28.781 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 02:29:28.781 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:29:28.781 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:29:28.781 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:29:28.782 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 02:29:28.782 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:29:28.782 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:29:28.782 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:29:28.782 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.28.20:5700) Recv POWEROFF cmd
2026-01-29 02:29:28.782 [INFO] ctrl_if_trx.py:117 (BTS@172.18.28.20:5700) Stopping transceiver...
2026-01-29 02:29:28.782 [INFO] transceiver.py:246 Stopping clock generator
2026-01-29 02:29:28.782 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=2996 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:29:28.782 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=2996 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:29:28.782 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=2996 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:29:28.782 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=2996 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:29:28.782 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=2996 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:29:28.782 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=2996 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:29:28.782 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=2996 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:29:33.786 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.28.20:5700) Recv POWEROFF cmd
2026-01-29 02:29:33.786 [INFO] ctrl_if_trx.py:117 (BTS@172.18.28.20:5700) Stopping transceiver...
2026-01-29 02:29:33.789 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:29:33.789 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:29:33.789 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:29:33.789 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 02:29:33.796 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 02:29:33.797 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.28.20:5700) Recv SETFORMAT cmd
2026-01-29 02:29:33.797 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.28.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:29:33.797 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.28.20:5700) Recv SETFORMAT cmd
2026-01-29 02:29:33.798 [INFO] ctrl_if_trx.py:201 (BTS@172.18.28.20:5700) TRXD header version 1 -> 1
2026-01-29 02:29:33.799 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.28.20:5700/1) Recv RXTUNE cmd
2026-01-29 02:29:33.800 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.28.20:5700/1) Recv TXTUNE cmd
2026-01-29 02:29:33.800 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.28.20:5700/1) Recv SETFORMAT cmd
2026-01-29 02:29:33.800 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.28.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:29:33.800 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:29:33.800 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.28.20:5700/1) Recv NOMTXPOWER cmd
2026-01-29 02:29:33.801 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.28.20:5700/1) Recv SETFORMAT cmd
2026-01-29 02:29:33.801 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.28.20:5700/1) TRXD header version 1 -> 1
2026-01-29 02:29:33.801 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.28.20:5700/2) Recv RXTUNE cmd
2026-01-29 02:29:33.801 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.28.20:5700/2) Recv TXTUNE cmd
2026-01-29 02:29:33.802 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.28.20:5700/2) Recv SETFORMAT cmd
2026-01-29 02:29:33.802 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.28.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:29:33.802 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:29:33.802 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.28.20:5700/2) Recv NOMTXPOWER cmd
2026-01-29 02:29:33.802 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.28.20:5700/2) Recv SETFORMAT cmd
2026-01-29 02:29:33.802 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.28.20:5700/2) TRXD header version 1 -> 1
2026-01-29 02:29:33.803 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.28.20:5700/3) Recv RXTUNE cmd
2026-01-29 02:29:33.803 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.28.20:5700/3) Recv TXTUNE cmd
2026-01-29 02:29:33.803 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.28.20:5700/3) Recv SETFORMAT cmd
2026-01-29 02:29:33.803 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.28.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:29:33.803 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:29:33.803 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.28.20:5700/3) Recv NOMTXPOWER cmd
2026-01-29 02:29:33.803 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.28.20:5700/3) Recv SETFORMAT cmd
2026-01-29 02:29:33.803 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.28.20:5700/3) TRXD header version 1 -> 1
2026-01-29 02:29:33.805 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.28.20:5700) Recv RXTUNE cmd
2026-01-29 02:29:33.805 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETTSC
2026-01-29 02:29:33.805 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETTSC
2026-01-29 02:29:33.805 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETTSC
2026-01-29 02:29:33.805 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.28.20:5700) Recv TXTUNE cmd
2026-01-29 02:29:33.805 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETRXGAIN
2026-01-29 02:29:33.805 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETRXGAIN
2026-01-29 02:29:33.805 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETRXGAIN
2026-01-29 02:29:33.805 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETTSC
2026-01-29 02:29:33.805 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:29:33.805 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:29:33.805 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:29:33.805 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.28.20:5700) Recv NOMTXPOWER cmd
2026-01-29 02:29:33.805 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:29:33.805 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:29:33.805 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:29:33.806 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.28.20:5700) Recv POWERON CMD
2026-01-29 02:29:33.806 [INFO] ctrl_if_trx.py:109 (BTS@172.18.28.20:5700) Starting transceiver...
2026-01-29 02:29:33.806 [INFO] transceiver.py:243 Starting clock generator
2026-01-29 02:29:33.806 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-01-29 02:29:33.806 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:29:33.806 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:29:33.806 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:29:33.806 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETRXGAIN
2026-01-29 02:29:33.806 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:29:33.806 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:29:33.806 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:29:33.806 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:29:33.806 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:29:33.806 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:29:33.806 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:29:33.806 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:29:33.806 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:29:33.806 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:29:33.806 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:29:33.806 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:29:33.806 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:29:33.806 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:29:33.806 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:29:33.806 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:29:33.806 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:29:33.806 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:29:33.806 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:29:33.806 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:29:33.806 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:29:33.806 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:29:33.807 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:29:33.810 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-01-29 02:29:34.293 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-01-29 02:29:34.329 [DEBUG] fake_trx.py:278 (BTS@172.18.28.20:5700) Recv FAKE_TOA cmd
2026-01-29 02:29:34.332 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:29:34.333 [DEBUG] fake_trx.py:297 (BTS@172.18.28.20:5700) Recv FAKE_RSSI cmd
2026-01-29 02:29:34.335 [DEBUG] fake_trx.py:322 (BTS@172.18.28.20:5700) Recv FAKE_CI cmd
2026-01-29 02:29:34.361 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 02:29:34.361 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 02:29:34.361 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 02:29:34.380 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 02:29:34.380 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 02:29:34.381 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 02:29:34.382 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:29:34.388 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:29:34.388 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 02:29:34.388 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 02:29:34.388 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.28.22:6700) Recv POWERON CMD
2026-01-29 02:29:34.388 [INFO] ctrl_if_trx.py:109 (MS@172.18.28.22:6700) Starting transceiver...
2026-01-29 02:29:34.431 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 02:29:34.431 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 02:29:34.431 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:29:34.432 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:29:34.769 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-01-29 02:29:34.807 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 02:29:34.808 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:29:34.809 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:29:34.810 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:29:35.054 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:29:35.055 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:29:35.059 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 02:29:35.059 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 02:29:35.078 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 02:29:35.078 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 02:29:35.078 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 02:29:35.084 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 02:29:35.084 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 02:29:35.084 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 02:29:35.084 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:29:35.086 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:29:35.086 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 02:29:35.086 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 02:29:35.086 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.28.22:6700) Recv POWERON CMD
2026-01-29 02:29:35.086 [INFO] ctrl_if_trx.py:109 (MS@172.18.28.22:6700) Starting transceiver...
2026-01-29 02:29:35.093 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 02:29:35.093 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 02:29:35.093 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:29:35.093 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:29:35.244 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-01-29 02:29:35.722 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-01-29 02:29:35.809 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 02:29:35.809 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:29:35.810 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:29:35.811 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:29:36.026 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:29:36.027 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:29:36.031 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 02:29:36.031 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 02:29:36.050 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 02:29:36.050 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 02:29:36.050 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 02:29:36.056 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 02:29:36.056 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 02:29:36.057 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 02:29:36.057 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:29:36.058 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:29:36.058 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 02:29:36.058 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 02:29:36.058 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.28.22:6700) Recv POWERON CMD
2026-01-29 02:29:36.058 [INFO] ctrl_if_trx.py:109 (MS@172.18.28.22:6700) Starting transceiver...
2026-01-29 02:29:36.095 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 02:29:36.096 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 02:29:36.096 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:29:36.097 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:29:36.199 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-01-29 02:29:36.677 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-01-29 02:29:36.810 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:29:36.810 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 02:29:36.811 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:29:36.811 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:29:37.155 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-01-29 02:29:37.633 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-01-29 02:29:37.811 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 02:29:37.811 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:29:37.812 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:29:37.812 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:29:38.025 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:29:38.025 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:29:38.029 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 02:29:38.029 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 02:29:38.048 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 02:29:38.048 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 02:29:38.048 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 02:29:38.054 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 02:29:38.054 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 02:29:38.054 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 02:29:38.054 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:29:38.056 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:29:38.056 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 02:29:38.056 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 02:29:38.056 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.28.22:6700) Recv POWERON CMD
2026-01-29 02:29:38.056 [INFO] ctrl_if_trx.py:109 (MS@172.18.28.22:6700) Starting transceiver...
2026-01-29 02:29:38.103 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 02:29:38.103 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 02:29:38.104 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:29:38.104 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:29:38.110 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-01-29 02:29:38.586 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-01-29 02:29:38.812 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 02:29:38.812 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:29:38.812 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:29:38.813 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:29:39.065 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-01-29 02:29:39.543 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-01-29 02:29:40.022 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-01-29 02:29:40.104 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:29:40.105 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:29:40.108 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 02:29:40.109 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 02:29:40.120 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 02:29:40.121 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:29:40.121 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:29:40.121 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:29:40.127 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 02:29:40.127 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:29:40.127 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:29:40.127 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:29:40.127 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.28.20:5700) Recv POWEROFF cmd
2026-01-29 02:29:40.128 [INFO] ctrl_if_trx.py:117 (BTS@172.18.28.20:5700) Stopping transceiver...
2026-01-29 02:29:40.128 [INFO] transceiver.py:246 Stopping clock generator
2026-01-29 02:29:40.128 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=1349 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:29:40.128 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=1349 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:29:45.124 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.28.20:5700) Recv POWEROFF cmd
2026-01-29 02:29:45.124 [INFO] ctrl_if_trx.py:117 (BTS@172.18.28.20:5700) Stopping transceiver...
2026-01-29 02:29:45.126 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:29:45.127 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:29:45.128 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:29:45.129 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 02:29:45.133 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 02:29:45.135 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.28.20:5700) Recv SETFORMAT cmd
2026-01-29 02:29:45.135 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.28.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:29:45.135 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.28.20:5700) Recv SETFORMAT cmd
2026-01-29 02:29:45.135 [INFO] ctrl_if_trx.py:201 (BTS@172.18.28.20:5700) TRXD header version 1 -> 1
2026-01-29 02:29:45.138 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.28.20:5700/1) Recv RXTUNE cmd
2026-01-29 02:29:45.139 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.28.20:5700/1) Recv TXTUNE cmd
2026-01-29 02:29:45.139 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.28.20:5700/1) Recv SETFORMAT cmd
2026-01-29 02:29:45.139 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.28.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:29:45.140 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:29:45.140 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.28.20:5700/1) Recv NOMTXPOWER cmd
2026-01-29 02:29:45.141 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.28.20:5700/1) Recv SETFORMAT cmd
2026-01-29 02:29:45.141 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.28.20:5700/1) TRXD header version 1 -> 1
2026-01-29 02:29:45.141 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.28.20:5700/2) Recv RXTUNE cmd
2026-01-29 02:29:45.141 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.28.20:5700/2) Recv TXTUNE cmd
2026-01-29 02:29:45.142 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.28.20:5700/2) Recv SETFORMAT cmd
2026-01-29 02:29:45.142 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.28.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:29:45.142 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:29:45.142 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.28.20:5700/2) Recv NOMTXPOWER cmd
2026-01-29 02:29:45.142 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.28.20:5700/2) Recv SETFORMAT cmd
2026-01-29 02:29:45.142 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.28.20:5700/2) TRXD header version 1 -> 1
2026-01-29 02:29:45.144 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.28.20:5700/3) Recv RXTUNE cmd
2026-01-29 02:29:45.144 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.28.20:5700/3) Recv TXTUNE cmd
2026-01-29 02:29:45.144 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.28.20:5700/3) Recv SETFORMAT cmd
2026-01-29 02:29:45.144 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.28.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:29:45.144 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:29:45.144 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.28.20:5700/3) Recv NOMTXPOWER cmd
2026-01-29 02:29:45.144 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.28.20:5700/3) Recv SETFORMAT cmd
2026-01-29 02:29:45.144 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.28.20:5700/3) TRXD header version 1 -> 1
2026-01-29 02:29:45.147 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.28.20:5700) Recv RXTUNE cmd
2026-01-29 02:29:45.147 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETTSC
2026-01-29 02:29:45.147 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETTSC
2026-01-29 02:29:45.147 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETTSC
2026-01-29 02:29:45.147 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.28.20:5700) Recv TXTUNE cmd
2026-01-29 02:29:45.147 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETRXGAIN
2026-01-29 02:29:45.147 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETRXGAIN
2026-01-29 02:29:45.147 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETRXGAIN
2026-01-29 02:29:45.147 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETTSC
2026-01-29 02:29:45.148 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:29:45.148 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:29:45.148 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:29:45.148 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.28.20:5700) Recv NOMTXPOWER cmd
2026-01-29 02:29:45.148 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:29:45.148 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:29:45.148 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:29:45.148 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.28.20:5700) Recv POWERON CMD
2026-01-29 02:29:45.148 [INFO] ctrl_if_trx.py:109 (BTS@172.18.28.20:5700) Starting transceiver...
2026-01-29 02:29:45.148 [INFO] transceiver.py:243 Starting clock generator
2026-01-29 02:29:45.148 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-01-29 02:29:45.148 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:29:45.148 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:29:45.148 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:29:45.148 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETRXGAIN
2026-01-29 02:29:45.148 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:29:45.148 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:29:45.148 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:29:45.148 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:29:45.148 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:29:45.148 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:29:45.148 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:29:45.148 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:29:45.148 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:29:45.149 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:29:45.149 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:29:45.149 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:29:45.149 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:29:45.149 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:29:45.149 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:29:45.149 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:29:45.149 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:29:45.149 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:29:45.149 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:29:45.149 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:29:45.149 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:29:45.149 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:29:45.149 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:29:45.153 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-01-29 02:29:45.637 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-01-29 02:29:45.677 [DEBUG] fake_trx.py:278 (BTS@172.18.28.20:5700) Recv FAKE_TOA cmd
2026-01-29 02:29:45.678 [DEBUG] fake_trx.py:297 (BTS@172.18.28.20:5700) Recv FAKE_RSSI cmd
2026-01-29 02:29:45.679 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:29:45.680 [DEBUG] fake_trx.py:322 (BTS@172.18.28.20:5700) Recv FAKE_CI cmd
2026-01-29 02:29:45.699 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 02:29:45.700 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 02:29:45.700 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 02:29:45.724 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 02:29:45.725 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 02:29:45.725 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 02:29:45.726 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:29:45.733 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:29:45.733 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 02:29:45.734 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 02:29:45.734 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.28.22:6700) Recv POWERON CMD
2026-01-29 02:29:45.734 [INFO] ctrl_if_trx.py:109 (MS@172.18.28.22:6700) Starting transceiver...
2026-01-29 02:29:45.775 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 02:29:45.775 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 02:29:45.775 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:29:45.776 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:29:46.114 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-01-29 02:29:46.151 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:29:46.152 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 02:29:46.153 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:29:46.157 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:29:46.592 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-01-29 02:29:47.070 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-01-29 02:29:47.153 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 02:29:47.153 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:29:47.153 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:29:47.158 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:29:47.549 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-01-29 02:29:48.027 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-01-29 02:29:48.153 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 02:29:48.153 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:29:48.154 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:29:48.159 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:29:48.229 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:29:48.229 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:29:48.233 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 02:29:48.233 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 02:29:48.247 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 02:29:48.247 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 02:29:48.247 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 02:29:48.253 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 02:29:48.254 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 02:29:48.254 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 02:29:48.254 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:29:48.255 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:29:48.255 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 02:29:48.255 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 02:29:48.255 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.28.22:6700) Recv POWERON CMD
2026-01-29 02:29:48.255 [INFO] ctrl_if_trx.py:109 (MS@172.18.28.22:6700) Starting transceiver...
2026-01-29 02:29:48.259 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 02:29:48.259 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 02:29:48.259 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:29:48.259 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:29:48.500 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-01-29 02:29:48.978 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-01-29 02:29:49.154 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 02:29:49.154 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:29:49.155 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:29:49.160 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:29:49.456 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-01-29 02:29:49.934 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-01-29 02:29:50.155 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:29:50.155 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:29:50.156 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 02:29:50.160 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:29:50.412 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-01-29 02:29:50.890 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-01-29 02:29:50.986 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:29:50.987 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:29:50.991 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 02:29:50.991 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 02:29:51.005 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 02:29:51.005 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 02:29:51.005 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 02:29:51.011 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 02:29:51.011 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 02:29:51.011 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 02:29:51.011 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:29:51.013 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:29:51.013 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 02:29:51.013 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 02:29:51.013 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.28.22:6700) Recv POWERON CMD
2026-01-29 02:29:51.013 [INFO] ctrl_if_trx.py:109 (MS@172.18.28.22:6700) Starting transceiver...
2026-01-29 02:29:51.026 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 02:29:51.026 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 02:29:51.026 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:29:51.026 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:29:51.364 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-01-29 02:29:51.842 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-01-29 02:29:52.319 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-01-29 02:29:52.797 [DEBUG] clck_gen.py:113 IND CLOCK 1632
2026-01-29 02:29:53.274 [DEBUG] clck_gen.py:113 IND CLOCK 1734
2026-01-29 02:29:53.752 [DEBUG] clck_gen.py:113 IND CLOCK 1836
2026-01-29 02:29:54.230 [DEBUG] clck_gen.py:113 IND CLOCK 1938
2026-01-29 02:29:54.386 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:29:54.387 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:29:54.391 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 02:29:54.391 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 02:29:54.401 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 02:29:54.401 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 02:29:54.401 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 02:29:54.407 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 02:29:54.407 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 02:29:54.407 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 02:29:54.407 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:29:54.408 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:29:54.408 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 02:29:54.408 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 02:29:54.408 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.28.22:6700) Recv POWERON CMD
2026-01-29 02:29:54.408 [INFO] ctrl_if_trx.py:109 (MS@172.18.28.22:6700) Starting transceiver...
2026-01-29 02:29:54.411 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 02:29:54.411 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 02:29:54.411 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:29:54.411 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:29:54.706 [DEBUG] clck_gen.py:113 IND CLOCK 2040
2026-01-29 02:29:55.184 [DEBUG] clck_gen.py:113 IND CLOCK 2142
2026-01-29 02:29:55.663 [DEBUG] clck_gen.py:113 IND CLOCK 2244
2026-01-29 02:29:56.142 [DEBUG] clck_gen.py:113 IND CLOCK 2346
2026-01-29 02:29:56.619 [DEBUG] clck_gen.py:113 IND CLOCK 2448
2026-01-29 02:29:57.097 [DEBUG] clck_gen.py:113 IND CLOCK 2550
2026-01-29 02:29:57.575 [DEBUG] clck_gen.py:113 IND CLOCK 2652
2026-01-29 02:29:57.893 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:29:57.894 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:29:57.898 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 02:29:57.898 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 02:29:57.912 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 02:29:57.912 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:29:57.912 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:29:57.912 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:29:57.918 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 02:29:57.918 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:29:57.918 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:29:57.919 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:29:57.919 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.28.20:5700) Recv POWEROFF cmd
2026-01-29 02:29:57.919 [INFO] ctrl_if_trx.py:117 (BTS@172.18.28.20:5700) Stopping transceiver...
2026-01-29 02:29:57.919 [INFO] transceiver.py:246 Stopping clock generator
2026-01-29 02:29:57.919 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=2726 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:29:57.920 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=2726 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:30:02.918 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.28.20:5700) Recv POWEROFF cmd
2026-01-29 02:30:02.918 [INFO] ctrl_if_trx.py:117 (BTS@172.18.28.20:5700) Stopping transceiver...
2026-01-29 02:30:02.918 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:30:02.918 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:30:02.918 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:30:02.918 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 02:30:02.928 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 02:30:02.930 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.28.20:5700) Recv SETFORMAT cmd
2026-01-29 02:30:02.930 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.28.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:30:02.930 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.28.20:5700) Recv SETFORMAT cmd
2026-01-29 02:30:02.930 [INFO] ctrl_if_trx.py:201 (BTS@172.18.28.20:5700) TRXD header version 1 -> 1
2026-01-29 02:30:02.935 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.28.20:5700/1) Recv RXTUNE cmd
2026-01-29 02:30:02.935 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.28.20:5700/1) Recv TXTUNE cmd
2026-01-29 02:30:02.935 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.28.20:5700/1) Recv SETFORMAT cmd
2026-01-29 02:30:02.935 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.28.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:30:02.936 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:30:02.936 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.28.20:5700/1) Recv NOMTXPOWER cmd
2026-01-29 02:30:02.936 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.28.20:5700/1) Recv SETFORMAT cmd
2026-01-29 02:30:02.936 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.28.20:5700/1) TRXD header version 1 -> 1
2026-01-29 02:30:02.939 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.28.20:5700/2) Recv RXTUNE cmd
2026-01-29 02:30:02.939 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.28.20:5700/2) Recv TXTUNE cmd
2026-01-29 02:30:02.939 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.28.20:5700/2) Recv SETFORMAT cmd
2026-01-29 02:30:02.939 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.28.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:30:02.940 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.28.20:5700/2) Recv NOMTXPOWER cmd
2026-01-29 02:30:02.940 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:30:02.940 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.28.20:5700/2) Recv SETFORMAT cmd
2026-01-29 02:30:02.940 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.28.20:5700/2) TRXD header version 1 -> 1
2026-01-29 02:30:02.943 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.28.20:5700/3) Recv RXTUNE cmd
2026-01-29 02:30:02.943 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.28.20:5700/3) Recv TXTUNE cmd
2026-01-29 02:30:02.943 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.28.20:5700/3) Recv SETFORMAT cmd
2026-01-29 02:30:02.943 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.28.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:30:02.944 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:30:02.944 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.28.20:5700/3) Recv NOMTXPOWER cmd
2026-01-29 02:30:02.944 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.28.20:5700/3) Recv SETFORMAT cmd
2026-01-29 02:30:02.944 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.28.20:5700/3) TRXD header version 1 -> 1
2026-01-29 02:30:02.948 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.28.20:5700) Recv RXTUNE cmd
2026-01-29 02:30:02.948 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETTSC
2026-01-29 02:30:02.948 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETTSC
2026-01-29 02:30:02.948 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETTSC
2026-01-29 02:30:02.948 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.28.20:5700) Recv TXTUNE cmd
2026-01-29 02:30:02.948 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETRXGAIN
2026-01-29 02:30:02.948 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETRXGAIN
2026-01-29 02:30:02.948 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETRXGAIN
2026-01-29 02:30:02.948 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETTSC
2026-01-29 02:30:02.948 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:30:02.948 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.28.20:5700) Recv NOMTXPOWER cmd
2026-01-29 02:30:02.948 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:30:02.948 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:30:02.948 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.28.20:5700) Recv POWERON CMD
2026-01-29 02:30:02.948 [INFO] ctrl_if_trx.py:109 (BTS@172.18.28.20:5700) Starting transceiver...
2026-01-29 02:30:02.948 [INFO] transceiver.py:243 Starting clock generator
2026-01-29 02:30:02.948 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-01-29 02:30:02.948 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:30:02.948 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:30:02.948 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:30:02.948 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETRXGAIN
2026-01-29 02:30:02.948 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:30:02.948 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:30:02.948 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:30:02.948 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:30:02.948 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:30:02.948 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:30:02.948 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:30:02.948 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:30:02.949 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:30:02.949 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:30:02.949 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:30:02.949 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:30:02.949 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:30:02.949 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:30:02.949 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:30:02.949 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:30:02.949 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:30:02.949 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:30:02.949 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:30:02.949 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:30:02.949 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:30:02.949 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:30:02.949 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:30:02.949 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:30:02.949 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:30:02.949 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:30:02.953 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-01-29 02:30:03.436 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-01-29 02:30:03.471 [DEBUG] fake_trx.py:278 (BTS@172.18.28.20:5700) Recv FAKE_TOA cmd
2026-01-29 02:30:03.473 [DEBUG] fake_trx.py:297 (BTS@172.18.28.20:5700) Recv FAKE_RSSI cmd
2026-01-29 02:30:03.474 [DEBUG] fake_trx.py:322 (BTS@172.18.28.20:5700) Recv FAKE_CI cmd
2026-01-29 02:30:03.475 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:30:03.490 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 02:30:03.490 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 02:30:03.490 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 02:30:03.508 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 02:30:03.508 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 02:30:03.508 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 02:30:03.509 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:30:03.515 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:30:03.515 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 02:30:03.515 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 02:30:03.515 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.28.22:6700) Recv POWERON CMD
2026-01-29 02:30:03.515 [INFO] ctrl_if_trx.py:109 (MS@172.18.28.22:6700) Starting transceiver...
2026-01-29 02:30:03.528 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 02:30:03.529 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 02:30:03.529 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:30:03.529 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:30:03.731 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:30:03.731 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:30:03.735 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 02:30:03.735 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 02:30:03.754 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 02:30:03.754 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 02:30:03.754 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 02:30:03.760 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 02:30:03.760 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 02:30:03.761 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 02:30:03.761 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:30:03.763 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:30:03.763 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 02:30:03.763 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 02:30:03.763 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.28.22:6700) Recv POWERON CMD
2026-01-29 02:30:03.763 [INFO] ctrl_if_trx.py:109 (MS@172.18.28.22:6700) Starting transceiver...
2026-01-29 02:30:03.810 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 02:30:03.810 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 02:30:03.810 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:30:03.810 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:30:03.909 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-01-29 02:30:03.950 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 02:30:03.951 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:30:03.952 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:30:03.956 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:30:04.151 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:30:04.152 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:30:04.156 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 02:30:04.156 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 02:30:04.171 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 02:30:04.171 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 02:30:04.171 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 02:30:04.177 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 02:30:04.177 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 02:30:04.177 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 02:30:04.177 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:30:04.179 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:30:04.179 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 02:30:04.179 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 02:30:04.179 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.28.22:6700) Recv POWERON CMD
2026-01-29 02:30:04.179 [INFO] ctrl_if_trx.py:109 (MS@172.18.28.22:6700) Starting transceiver...
2026-01-29 02:30:04.186 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 02:30:04.186 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 02:30:04.186 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:30:04.186 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:30:04.386 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-01-29 02:30:04.777 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:30:04.777 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:30:04.781 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 02:30:04.781 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 02:30:04.801 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 02:30:04.801 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 02:30:04.802 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 02:30:04.807 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 02:30:04.807 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 02:30:04.807 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 02:30:04.808 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:30:04.809 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:30:04.809 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 02:30:04.809 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 02:30:04.809 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.28.22:6700) Recv POWERON CMD
2026-01-29 02:30:04.809 [INFO] ctrl_if_trx.py:109 (MS@172.18.28.22:6700) Starting transceiver...
2026-01-29 02:30:04.855 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 02:30:04.856 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 02:30:04.856 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:30:04.856 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:30:04.862 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-01-29 02:30:04.951 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 02:30:04.951 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:30:04.953 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:30:04.957 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:30:05.339 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-01-29 02:30:05.423 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:30:05.423 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:30:05.427 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 02:30:05.427 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 02:30:05.440 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 02:30:05.440 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:30:05.441 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:30:05.441 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:30:05.446 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 02:30:05.446 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:30:05.446 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:30:05.446 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.28.20:5700) Recv POWEROFF cmd
2026-01-29 02:30:05.447 [INFO] ctrl_if_trx.py:117 (BTS@172.18.28.20:5700) Stopping transceiver...
2026-01-29 02:30:05.447 [INFO] transceiver.py:246 Stopping clock generator
2026-01-29 02:30:05.447 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:30:05.447 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=534 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:30:05.447 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=534 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:30:10.442 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.28.20:5700) Recv POWEROFF cmd
2026-01-29 02:30:10.442 [INFO] ctrl_if_trx.py:117 (BTS@172.18.28.20:5700) Stopping transceiver...
2026-01-29 02:30:10.443 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:30:10.444 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:30:10.444 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:30:10.444 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 02:30:10.452 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 02:30:10.453 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.28.20:5700) Recv SETFORMAT cmd
2026-01-29 02:30:10.453 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.28.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:30:10.454 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.28.20:5700) Recv SETFORMAT cmd
2026-01-29 02:30:10.454 [INFO] ctrl_if_trx.py:201 (BTS@172.18.28.20:5700) TRXD header version 1 -> 1
2026-01-29 02:30:10.456 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.28.20:5700/1) Recv RXTUNE cmd
2026-01-29 02:30:10.456 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.28.20:5700/1) Recv TXTUNE cmd
2026-01-29 02:30:10.457 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.28.20:5700/1) Recv SETFORMAT cmd
2026-01-29 02:30:10.457 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.28.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:30:10.457 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:30:10.457 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.28.20:5700/1) Recv NOMTXPOWER cmd
2026-01-29 02:30:10.458 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.28.20:5700/1) Recv SETFORMAT cmd
2026-01-29 02:30:10.458 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.28.20:5700/1) TRXD header version 1 -> 1
2026-01-29 02:30:10.458 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.28.20:5700/2) Recv RXTUNE cmd
2026-01-29 02:30:10.459 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.28.20:5700/2) Recv TXTUNE cmd
2026-01-29 02:30:10.459 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.28.20:5700/2) Recv SETFORMAT cmd
2026-01-29 02:30:10.459 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.28.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:30:10.459 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:30:10.459 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.28.20:5700/2) Recv NOMTXPOWER cmd
2026-01-29 02:30:10.459 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.28.20:5700/2) Recv SETFORMAT cmd
2026-01-29 02:30:10.459 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.28.20:5700/2) TRXD header version 1 -> 1
2026-01-29 02:30:10.461 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.28.20:5700/3) Recv RXTUNE cmd
2026-01-29 02:30:10.461 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.28.20:5700/3) Recv TXTUNE cmd
2026-01-29 02:30:10.461 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.28.20:5700/3) Recv SETFORMAT cmd
2026-01-29 02:30:10.461 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.28.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:30:10.461 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:30:10.461 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.28.20:5700/3) Recv NOMTXPOWER cmd
2026-01-29 02:30:10.461 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.28.20:5700/3) Recv SETFORMAT cmd
2026-01-29 02:30:10.461 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.28.20:5700/3) TRXD header version 1 -> 1
2026-01-29 02:30:10.463 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.28.20:5700) Recv RXTUNE cmd
2026-01-29 02:30:10.463 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETTSC
2026-01-29 02:30:10.463 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETTSC
2026-01-29 02:30:10.463 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETTSC
2026-01-29 02:30:10.464 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.28.20:5700) Recv TXTUNE cmd
2026-01-29 02:30:10.464 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETRXGAIN
2026-01-29 02:30:10.464 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETRXGAIN
2026-01-29 02:30:10.464 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETRXGAIN
2026-01-29 02:30:10.464 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETTSC
2026-01-29 02:30:10.464 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:30:10.464 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:30:10.464 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:30:10.464 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.28.20:5700) Recv NOMTXPOWER cmd
2026-01-29 02:30:10.464 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:30:10.464 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:30:10.464 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:30:10.464 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.28.20:5700) Recv POWERON CMD
2026-01-29 02:30:10.464 [INFO] ctrl_if_trx.py:109 (BTS@172.18.28.20:5700) Starting transceiver...
2026-01-29 02:30:10.464 [INFO] transceiver.py:243 Starting clock generator
2026-01-29 02:30:10.464 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-01-29 02:30:10.464 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:30:10.464 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:30:10.464 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:30:10.464 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETRXGAIN
2026-01-29 02:30:10.465 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:30:10.465 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:30:10.465 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:30:10.465 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:30:10.465 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:30:10.465 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:30:10.465 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:30:10.465 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:30:10.465 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:30:10.465 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:30:10.465 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:30:10.465 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:30:10.465 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:30:10.465 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:30:10.465 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:30:10.465 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:30:10.465 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:30:10.465 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:30:10.465 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:30:10.465 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:30:10.465 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:30:10.465 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:30:10.465 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:30:10.469 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-01-29 02:30:10.953 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-01-29 02:30:10.986 [DEBUG] fake_trx.py:278 (BTS@172.18.28.20:5700) Recv FAKE_TOA cmd
2026-01-29 02:30:10.987 [DEBUG] fake_trx.py:297 (BTS@172.18.28.20:5700) Recv FAKE_RSSI cmd
2026-01-29 02:30:10.988 [DEBUG] fake_trx.py:322 (BTS@172.18.28.20:5700) Recv FAKE_CI cmd
2026-01-29 02:30:10.989 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:30:11.001 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 02:30:11.001 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 02:30:11.001 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 02:30:11.014 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 02:30:11.014 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 02:30:11.015 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 02:30:11.016 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:30:11.020 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:30:11.020 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 02:30:11.020 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 02:30:11.020 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.28.22:6700) Recv POWERON CMD
2026-01-29 02:30:11.020 [INFO] ctrl_if_trx.py:109 (MS@172.18.28.22:6700) Starting transceiver...
2026-01-29 02:30:11.044 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 02:30:11.044 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 02:30:11.044 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:30:11.044 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:30:11.426 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-01-29 02:30:11.467 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 02:30:11.467 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:30:11.469 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:30:11.470 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:30:11.904 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-01-29 02:30:12.381 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-01-29 02:30:12.468 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 02:30:12.468 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:30:12.469 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:30:12.471 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:30:12.859 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-01-29 02:30:13.337 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-01-29 02:30:13.469 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 02:30:13.469 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:30:13.470 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:30:13.472 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:30:13.815 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-01-29 02:30:14.292 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-01-29 02:30:14.469 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 02:30:14.470 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:30:14.472 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:30:14.472 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:30:14.770 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-01-29 02:30:15.248 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-01-29 02:30:15.470 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:30:15.471 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 02:30:15.473 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:30:15.473 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:30:15.726 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-01-29 02:30:16.204 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-01-29 02:30:16.682 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-01-29 02:30:17.160 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-01-29 02:30:17.639 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-01-29 02:30:18.116 [DEBUG] clck_gen.py:113 IND CLOCK 1632
2026-01-29 02:30:18.595 [DEBUG] clck_gen.py:113 IND CLOCK 1734
2026-01-29 02:30:19.073 [DEBUG] clck_gen.py:113 IND CLOCK 1836
2026-01-29 02:30:19.551 [DEBUG] clck_gen.py:113 IND CLOCK 1938
2026-01-29 02:30:20.029 [DEBUG] clck_gen.py:113 IND CLOCK 2040
2026-01-29 02:30:20.506 [DEBUG] clck_gen.py:113 IND CLOCK 2142
2026-01-29 02:30:20.985 [DEBUG] clck_gen.py:113 IND CLOCK 2244
2026-01-29 02:30:21.463 [DEBUG] clck_gen.py:113 IND CLOCK 2346
2026-01-29 02:30:21.940 [DEBUG] clck_gen.py:113 IND CLOCK 2448
2026-01-29 02:30:22.418 [DEBUG] clck_gen.py:113 IND CLOCK 2550
2026-01-29 02:30:22.896 [DEBUG] clck_gen.py:113 IND CLOCK 2652
2026-01-29 02:30:23.374 [DEBUG] clck_gen.py:113 IND CLOCK 2754
2026-01-29 02:30:23.851 [DEBUG] clck_gen.py:113 IND CLOCK 2856
2026-01-29 02:30:24.329 [DEBUG] clck_gen.py:113 IND CLOCK 2958
2026-01-29 02:30:24.807 [DEBUG] clck_gen.py:113 IND CLOCK 3060
2026-01-29 02:30:25.284 [DEBUG] clck_gen.py:113 IND CLOCK 3162
2026-01-29 02:30:25.762 [DEBUG] clck_gen.py:113 IND CLOCK 3264
2026-01-29 02:30:26.240 [DEBUG] clck_gen.py:113 IND CLOCK 3366
2026-01-29 02:30:26.718 [DEBUG] clck_gen.py:113 IND CLOCK 3468
2026-01-29 02:30:27.196 [DEBUG] clck_gen.py:113 IND CLOCK 3570
2026-01-29 02:30:27.673 [DEBUG] clck_gen.py:113 IND CLOCK 3672
2026-01-29 02:30:28.151 [DEBUG] clck_gen.py:113 IND CLOCK 3774
2026-01-29 02:30:28.628 [DEBUG] clck_gen.py:113 IND CLOCK 3876
2026-01-29 02:30:29.105 [DEBUG] clck_gen.py:113 IND CLOCK 3978
2026-01-29 02:30:29.583 [DEBUG] clck_gen.py:113 IND CLOCK 4080
2026-01-29 02:30:30.061 [DEBUG] clck_gen.py:113 IND CLOCK 4182
2026-01-29 02:30:30.539 [DEBUG] clck_gen.py:113 IND CLOCK 4284
2026-01-29 02:30:31.017 [DEBUG] clck_gen.py:113 IND CLOCK 4386
2026-01-29 02:30:31.495 [DEBUG] clck_gen.py:113 IND CLOCK 4488
2026-01-29 02:30:31.973 [DEBUG] clck_gen.py:113 IND CLOCK 4590
2026-01-29 02:30:32.451 [DEBUG] clck_gen.py:113 IND CLOCK 4692
2026-01-29 02:30:32.929 [DEBUG] clck_gen.py:113 IND CLOCK 4794
2026-01-29 02:30:33.407 [DEBUG] clck_gen.py:113 IND CLOCK 4896
2026-01-29 02:30:33.885 [DEBUG] clck_gen.py:113 IND CLOCK 4998
2026-01-29 02:30:34.362 [DEBUG] clck_gen.py:113 IND CLOCK 5100
2026-01-29 02:30:34.840 [DEBUG] clck_gen.py:113 IND CLOCK 5202
2026-01-29 02:30:35.318 [DEBUG] clck_gen.py:113 IND CLOCK 5304
2026-01-29 02:30:35.796 [DEBUG] clck_gen.py:113 IND CLOCK 5406
2026-01-29 02:30:36.274 [DEBUG] clck_gen.py:113 IND CLOCK 5508
2026-01-29 02:30:36.752 [DEBUG] clck_gen.py:113 IND CLOCK 5610
2026-01-29 02:30:37.230 [DEBUG] clck_gen.py:113 IND CLOCK 5712
2026-01-29 02:30:37.708 [DEBUG] clck_gen.py:113 IND CLOCK 5814
2026-01-29 02:30:38.186 [DEBUG] clck_gen.py:113 IND CLOCK 5916
2026-01-29 02:30:38.663 [DEBUG] clck_gen.py:113 IND CLOCK 6018
2026-01-29 02:30:39.141 [DEBUG] clck_gen.py:113 IND CLOCK 6120
2026-01-29 02:30:39.619 [DEBUG] clck_gen.py:113 IND CLOCK 6222
2026-01-29 02:30:40.097 [DEBUG] clck_gen.py:113 IND CLOCK 6324
2026-01-29 02:30:40.575 [DEBUG] clck_gen.py:113 IND CLOCK 6426
2026-01-29 02:30:41.052 [DEBUG] clck_gen.py:113 IND CLOCK 6528
2026-01-29 02:30:41.530 [DEBUG] clck_gen.py:113 IND CLOCK 6630
2026-01-29 02:30:42.007 [DEBUG] clck_gen.py:113 IND CLOCK 6732
2026-01-29 02:30:42.486 [DEBUG] clck_gen.py:113 IND CLOCK 6834
2026-01-29 02:30:42.963 [DEBUG] clck_gen.py:113 IND CLOCK 6936
2026-01-29 02:30:43.440 [DEBUG] clck_gen.py:113 IND CLOCK 7038
2026-01-29 02:30:43.919 [DEBUG] clck_gen.py:113 IND CLOCK 7140
2026-01-29 02:30:44.037 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:30:44.038 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:30:44.050 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 02:30:44.051 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 02:30:44.064 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 02:30:44.064 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 02:30:44.064 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 02:30:44.070 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 02:30:44.070 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 02:30:44.070 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 02:30:44.071 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:30:44.072 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:30:44.072 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 02:30:44.072 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 02:30:44.072 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.28.22:6700) Recv POWERON CMD
2026-01-29 02:30:44.072 [INFO] ctrl_if_trx.py:109 (MS@172.18.28.22:6700) Starting transceiver...
2026-01-29 02:30:44.103 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 02:30:44.103 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 02:30:44.104 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:30:44.104 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:30:44.395 [DEBUG] clck_gen.py:113 IND CLOCK 7242
2026-01-29 02:30:44.874 [DEBUG] clck_gen.py:113 IND CLOCK 7344
2026-01-29 02:30:45.352 [DEBUG] clck_gen.py:113 IND CLOCK 7446
2026-01-29 02:30:45.830 [DEBUG] clck_gen.py:113 IND CLOCK 7548
2026-01-29 02:30:46.308 [DEBUG] clck_gen.py:113 IND CLOCK 7650
2026-01-29 02:30:46.786 [DEBUG] clck_gen.py:113 IND CLOCK 7752
2026-01-29 02:30:47.264 [DEBUG] clck_gen.py:113 IND CLOCK 7854
2026-01-29 02:30:47.742 [DEBUG] clck_gen.py:113 IND CLOCK 7956
2026-01-29 02:30:48.220 [DEBUG] clck_gen.py:113 IND CLOCK 8058
2026-01-29 02:30:48.697 [DEBUG] clck_gen.py:113 IND CLOCK 8160
2026-01-29 02:30:49.176 [DEBUG] clck_gen.py:113 IND CLOCK 8262
2026-01-29 02:30:49.654 [DEBUG] clck_gen.py:113 IND CLOCK 8364
2026-01-29 02:30:50.132 [DEBUG] clck_gen.py:113 IND CLOCK 8466
2026-01-29 02:30:50.609 [DEBUG] clck_gen.py:113 IND CLOCK 8568
2026-01-29 02:30:51.088 [DEBUG] clck_gen.py:113 IND CLOCK 8670
2026-01-29 02:30:51.566 [DEBUG] clck_gen.py:113 IND CLOCK 8772
2026-01-29 02:30:52.044 [DEBUG] clck_gen.py:113 IND CLOCK 8874
2026-01-29 02:30:52.522 [DEBUG] clck_gen.py:113 IND CLOCK 8976
2026-01-29 02:30:52.999 [DEBUG] clck_gen.py:113 IND CLOCK 9078
2026-01-29 02:30:53.477 [DEBUG] clck_gen.py:113 IND CLOCK 9180
2026-01-29 02:30:53.954 [DEBUG] clck_gen.py:113 IND CLOCK 9282
2026-01-29 02:30:54.433 [DEBUG] clck_gen.py:113 IND CLOCK 9384
2026-01-29 02:30:54.911 [DEBUG] clck_gen.py:113 IND CLOCK 9486
2026-01-29 02:30:55.388 [DEBUG] clck_gen.py:113 IND CLOCK 9588
2026-01-29 02:30:55.866 [DEBUG] clck_gen.py:113 IND CLOCK 9690
2026-01-29 02:30:56.344 [DEBUG] clck_gen.py:113 IND CLOCK 9792
2026-01-29 02:30:56.823 [DEBUG] clck_gen.py:113 IND CLOCK 9894
2026-01-29 02:30:57.301 [DEBUG] clck_gen.py:113 IND CLOCK 9996
2026-01-29 02:30:57.779 [DEBUG] clck_gen.py:113 IND CLOCK 10098
2026-01-29 02:30:58.257 [DEBUG] clck_gen.py:113 IND CLOCK 10200
2026-01-29 02:30:58.735 [DEBUG] clck_gen.py:113 IND CLOCK 10302
2026-01-29 02:30:59.214 [DEBUG] clck_gen.py:113 IND CLOCK 10404
2026-01-29 02:30:59.710 [DEBUG] clck_gen.py:113 IND CLOCK 10506
2026-01-29 02:31:00.188 [DEBUG] clck_gen.py:113 IND CLOCK 10608
2026-01-29 02:31:00.666 [DEBUG] clck_gen.py:113 IND CLOCK 10710
2026-01-29 02:31:01.145 [DEBUG] clck_gen.py:113 IND CLOCK 10812
2026-01-29 02:31:01.623 [DEBUG] clck_gen.py:113 IND CLOCK 10914
2026-01-29 02:31:02.101 [DEBUG] clck_gen.py:113 IND CLOCK 11016
2026-01-29 02:31:02.579 [DEBUG] clck_gen.py:113 IND CLOCK 11118
2026-01-29 02:31:03.058 [DEBUG] clck_gen.py:113 IND CLOCK 11220
2026-01-29 02:31:03.537 [DEBUG] clck_gen.py:113 IND CLOCK 11322
2026-01-29 02:31:04.015 [DEBUG] clck_gen.py:113 IND CLOCK 11424
2026-01-29 02:31:04.493 [DEBUG] clck_gen.py:113 IND CLOCK 11526
2026-01-29 02:31:04.972 [DEBUG] clck_gen.py:113 IND CLOCK 11628
2026-01-29 02:31:05.450 [DEBUG] clck_gen.py:113 IND CLOCK 11730
2026-01-29 02:31:05.929 [DEBUG] clck_gen.py:113 IND CLOCK 11832
2026-01-29 02:31:06.407 [DEBUG] clck_gen.py:113 IND CLOCK 11934
2026-01-29 02:31:06.886 [DEBUG] clck_gen.py:113 IND CLOCK 12036
2026-01-29 02:31:07.364 [DEBUG] clck_gen.py:113 IND CLOCK 12138
2026-01-29 02:31:07.842 [DEBUG] clck_gen.py:113 IND CLOCK 12240
2026-01-29 02:31:08.320 [DEBUG] clck_gen.py:113 IND CLOCK 12342
2026-01-29 02:31:08.797 [DEBUG] clck_gen.py:113 IND CLOCK 12444
2026-01-29 02:31:09.275 [DEBUG] clck_gen.py:113 IND CLOCK 12546
2026-01-29 02:31:09.753 [DEBUG] clck_gen.py:113 IND CLOCK 12648
2026-01-29 02:31:10.232 [DEBUG] clck_gen.py:113 IND CLOCK 12750
2026-01-29 02:31:10.710 [DEBUG] clck_gen.py:113 IND CLOCK 12852
2026-01-29 02:31:11.188 [DEBUG] clck_gen.py:113 IND CLOCK 12954
2026-01-29 02:31:11.666 [DEBUG] clck_gen.py:113 IND CLOCK 13056
2026-01-29 02:31:12.145 [DEBUG] clck_gen.py:113 IND CLOCK 13158
2026-01-29 02:31:12.623 [DEBUG] clck_gen.py:113 IND CLOCK 13260
2026-01-29 02:31:13.101 [DEBUG] clck_gen.py:113 IND CLOCK 13362
2026-01-29 02:31:13.578 [DEBUG] clck_gen.py:113 IND CLOCK 13464
2026-01-29 02:31:14.056 [DEBUG] clck_gen.py:113 IND CLOCK 13566
2026-01-29 02:31:14.534 [DEBUG] clck_gen.py:113 IND CLOCK 13668
2026-01-29 02:31:15.013 [DEBUG] clck_gen.py:113 IND CLOCK 13770
2026-01-29 02:31:15.491 [DEBUG] clck_gen.py:113 IND CLOCK 13872
2026-01-29 02:31:15.969 [DEBUG] clck_gen.py:113 IND CLOCK 13974
2026-01-29 02:31:16.447 [DEBUG] clck_gen.py:113 IND CLOCK 14076
2026-01-29 02:31:16.925 [DEBUG] clck_gen.py:113 IND CLOCK 14178
2026-01-29 02:31:17.403 [DEBUG] clck_gen.py:113 IND CLOCK 14280
2026-01-29 02:31:17.723 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:31:17.724 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:31:17.729 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 02:31:17.729 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 02:31:17.746 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 02:31:17.747 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 02:31:17.747 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 02:31:17.753 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 02:31:17.753 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 02:31:17.753 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 02:31:17.753 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:31:17.754 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:31:17.754 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 02:31:17.754 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 02:31:17.754 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.28.22:6700) Recv POWERON CMD
2026-01-29 02:31:17.754 [INFO] ctrl_if_trx.py:109 (MS@172.18.28.22:6700) Starting transceiver...
2026-01-29 02:31:17.776 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 02:31:17.776 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 02:31:17.776 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:31:17.776 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:31:17.880 [DEBUG] clck_gen.py:113 IND CLOCK 14382
2026-01-29 02:31:18.358 [DEBUG] clck_gen.py:113 IND CLOCK 14484
2026-01-29 02:31:18.836 [DEBUG] clck_gen.py:113 IND CLOCK 14586
2026-01-29 02:31:19.314 [DEBUG] clck_gen.py:113 IND CLOCK 14688
2026-01-29 02:31:19.791 [DEBUG] clck_gen.py:113 IND CLOCK 14790
2026-01-29 02:31:20.269 [DEBUG] clck_gen.py:113 IND CLOCK 14892
2026-01-29 02:31:20.748 [DEBUG] clck_gen.py:113 IND CLOCK 14994
2026-01-29 02:31:21.225 [DEBUG] clck_gen.py:113 IND CLOCK 15096
2026-01-29 02:31:21.702 [DEBUG] clck_gen.py:113 IND CLOCK 15198
2026-01-29 02:31:22.180 [DEBUG] clck_gen.py:113 IND CLOCK 15300
2026-01-29 02:31:22.658 [DEBUG] clck_gen.py:113 IND CLOCK 15402
2026-01-29 02:31:23.136 [DEBUG] clck_gen.py:113 IND CLOCK 15504
2026-01-29 02:31:23.613 [DEBUG] clck_gen.py:113 IND CLOCK 15606
2026-01-29 02:31:24.091 [DEBUG] clck_gen.py:113 IND CLOCK 15708
2026-01-29 02:31:24.569 [DEBUG] clck_gen.py:113 IND CLOCK 15810
2026-01-29 02:31:25.046 [DEBUG] clck_gen.py:113 IND CLOCK 15912
2026-01-29 02:31:25.524 [DEBUG] clck_gen.py:113 IND CLOCK 16014
2026-01-29 02:31:26.002 [DEBUG] clck_gen.py:113 IND CLOCK 16116
2026-01-29 02:31:26.480 [DEBUG] clck_gen.py:113 IND CLOCK 16218
2026-01-29 02:31:26.957 [DEBUG] clck_gen.py:113 IND CLOCK 16320
2026-01-29 02:31:27.435 [DEBUG] clck_gen.py:113 IND CLOCK 16422
2026-01-29 02:31:27.913 [DEBUG] clck_gen.py:113 IND CLOCK 16524
2026-01-29 02:31:28.391 [DEBUG] clck_gen.py:113 IND CLOCK 16626
2026-01-29 02:31:28.868 [DEBUG] clck_gen.py:113 IND CLOCK 16728
2026-01-29 02:31:29.346 [DEBUG] clck_gen.py:113 IND CLOCK 16830
2026-01-29 02:31:29.822 [DEBUG] clck_gen.py:113 IND CLOCK 16932
2026-01-29 02:31:30.300 [DEBUG] clck_gen.py:113 IND CLOCK 17034
2026-01-29 02:31:30.777 [DEBUG] clck_gen.py:113 IND CLOCK 17136
2026-01-29 02:31:31.255 [DEBUG] clck_gen.py:113 IND CLOCK 17238
2026-01-29 02:31:31.732 [DEBUG] clck_gen.py:113 IND CLOCK 17340
2026-01-29 02:31:32.210 [DEBUG] clck_gen.py:113 IND CLOCK 17442
2026-01-29 02:31:32.688 [DEBUG] clck_gen.py:113 IND CLOCK 17544
2026-01-29 02:31:33.166 [DEBUG] clck_gen.py:113 IND CLOCK 17646
2026-01-29 02:31:33.643 [DEBUG] clck_gen.py:113 IND CLOCK 17748
2026-01-29 02:31:34.120 [DEBUG] clck_gen.py:113 IND CLOCK 17850
2026-01-29 02:31:34.598 [DEBUG] clck_gen.py:113 IND CLOCK 17952
2026-01-29 02:31:35.076 [DEBUG] clck_gen.py:113 IND CLOCK 18054
2026-01-29 02:31:35.554 [DEBUG] clck_gen.py:113 IND CLOCK 18156
2026-01-29 02:31:36.031 [DEBUG] clck_gen.py:113 IND CLOCK 18258
2026-01-29 02:31:36.509 [DEBUG] clck_gen.py:113 IND CLOCK 18360
2026-01-29 02:31:36.986 [DEBUG] clck_gen.py:113 IND CLOCK 18462
2026-01-29 02:31:37.464 [DEBUG] clck_gen.py:113 IND CLOCK 18564
2026-01-29 02:31:37.941 [DEBUG] clck_gen.py:113 IND CLOCK 18666
2026-01-29 02:31:38.419 [DEBUG] clck_gen.py:113 IND CLOCK 18768
2026-01-29 02:31:38.896 [DEBUG] clck_gen.py:113 IND CLOCK 18870
2026-01-29 02:31:39.374 [DEBUG] clck_gen.py:113 IND CLOCK 18972
2026-01-29 02:31:39.852 [DEBUG] clck_gen.py:113 IND CLOCK 19074
2026-01-29 02:31:40.330 [DEBUG] clck_gen.py:113 IND CLOCK 19176
2026-01-29 02:31:40.807 [DEBUG] clck_gen.py:113 IND CLOCK 19278
2026-01-29 02:31:41.285 [DEBUG] clck_gen.py:113 IND CLOCK 19380
2026-01-29 02:31:41.762 [DEBUG] clck_gen.py:113 IND CLOCK 19482
2026-01-29 02:31:42.240 [DEBUG] clck_gen.py:113 IND CLOCK 19584
2026-01-29 02:31:42.718 [DEBUG] clck_gen.py:113 IND CLOCK 19686
2026-01-29 02:31:43.196 [DEBUG] clck_gen.py:113 IND CLOCK 19788
2026-01-29 02:31:43.674 [DEBUG] clck_gen.py:113 IND CLOCK 19890
2026-01-29 02:31:44.152 [DEBUG] clck_gen.py:113 IND CLOCK 19992
2026-01-29 02:31:44.629 [DEBUG] clck_gen.py:113 IND CLOCK 20094
2026-01-29 02:31:45.107 [DEBUG] clck_gen.py:113 IND CLOCK 20196
2026-01-29 02:31:45.584 [DEBUG] clck_gen.py:113 IND CLOCK 20298
2026-01-29 02:31:46.062 [DEBUG] clck_gen.py:113 IND CLOCK 20400
2026-01-29 02:31:46.540 [DEBUG] clck_gen.py:113 IND CLOCK 20502
2026-01-29 02:31:47.018 [DEBUG] clck_gen.py:113 IND CLOCK 20604
2026-01-29 02:31:47.496 [DEBUG] clck_gen.py:113 IND CLOCK 20706
2026-01-29 02:31:47.973 [DEBUG] clck_gen.py:113 IND CLOCK 20808
2026-01-29 02:31:48.451 [DEBUG] clck_gen.py:113 IND CLOCK 20910
2026-01-29 02:31:48.930 [DEBUG] clck_gen.py:113 IND CLOCK 21012
2026-01-29 02:31:49.407 [DEBUG] clck_gen.py:113 IND CLOCK 21114
2026-01-29 02:31:49.885 [DEBUG] clck_gen.py:113 IND CLOCK 21216
2026-01-29 02:31:50.363 [DEBUG] clck_gen.py:113 IND CLOCK 21318
2026-01-29 02:31:50.841 [DEBUG] clck_gen.py:113 IND CLOCK 21420
2026-01-29 02:31:51.319 [DEBUG] clck_gen.py:113 IND CLOCK 21522
2026-01-29 02:31:51.797 [DEBUG] clck_gen.py:113 IND CLOCK 21624
2026-01-29 02:31:52.275 [DEBUG] clck_gen.py:113 IND CLOCK 21726
2026-01-29 02:31:52.752 [DEBUG] clck_gen.py:113 IND CLOCK 21828
2026-01-29 02:31:53.147 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:31:53.148 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:31:53.161 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 02:31:53.161 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 02:31:53.171 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 02:31:53.171 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 02:31:53.171 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 02:31:53.177 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 02:31:53.177 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 02:31:53.177 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:31:53.177 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 02:31:53.178 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:31:53.178 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 02:31:53.178 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 02:31:53.179 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.28.22:6700) Recv POWERON CMD
2026-01-29 02:31:53.179 [INFO] ctrl_if_trx.py:109 (MS@172.18.28.22:6700) Starting transceiver...
2026-01-29 02:31:53.222 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 02:31:53.223 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 02:31:53.223 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:31:53.223 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:31:53.229 [DEBUG] clck_gen.py:113 IND CLOCK 21930
2026-01-29 02:31:53.705 [DEBUG] clck_gen.py:113 IND CLOCK 22032
2026-01-29 02:31:54.182 [DEBUG] clck_gen.py:113 IND CLOCK 22134
2026-01-29 02:31:54.661 [DEBUG] clck_gen.py:113 IND CLOCK 22236
2026-01-29 02:31:55.139 [DEBUG] clck_gen.py:113 IND CLOCK 22338
2026-01-29 02:31:55.616 [DEBUG] clck_gen.py:113 IND CLOCK 22440
2026-01-29 02:31:56.094 [DEBUG] clck_gen.py:113 IND CLOCK 22542
2026-01-29 02:31:56.571 [DEBUG] clck_gen.py:113 IND CLOCK 22644
2026-01-29 02:31:57.049 [DEBUG] clck_gen.py:113 IND CLOCK 22746
2026-01-29 02:31:57.527 [DEBUG] clck_gen.py:113 IND CLOCK 22848
2026-01-29 02:31:58.004 [DEBUG] clck_gen.py:113 IND CLOCK 22950
2026-01-29 02:31:58.482 [DEBUG] clck_gen.py:113 IND CLOCK 23052
2026-01-29 02:31:58.960 [DEBUG] clck_gen.py:113 IND CLOCK 23154
2026-01-29 02:31:59.437 [DEBUG] clck_gen.py:113 IND CLOCK 23256
2026-01-29 02:31:59.916 [DEBUG] clck_gen.py:113 IND CLOCK 23358
2026-01-29 02:32:00.393 [DEBUG] clck_gen.py:113 IND CLOCK 23460
2026-01-29 02:32:00.872 [DEBUG] clck_gen.py:113 IND CLOCK 23562
2026-01-29 02:32:01.349 [DEBUG] clck_gen.py:113 IND CLOCK 23664
2026-01-29 02:32:01.827 [DEBUG] clck_gen.py:113 IND CLOCK 23766
2026-01-29 02:32:02.305 [DEBUG] clck_gen.py:113 IND CLOCK 23868
2026-01-29 02:32:02.783 [DEBUG] clck_gen.py:113 IND CLOCK 23970
2026-01-29 02:32:03.260 [DEBUG] clck_gen.py:113 IND CLOCK 24072
2026-01-29 02:32:03.738 [DEBUG] clck_gen.py:113 IND CLOCK 24174
2026-01-29 02:32:04.216 [DEBUG] clck_gen.py:113 IND CLOCK 24276
2026-01-29 02:32:04.693 [DEBUG] clck_gen.py:113 IND CLOCK 24378
2026-01-29 02:32:05.170 [DEBUG] clck_gen.py:113 IND CLOCK 24480
2026-01-29 02:32:05.648 [DEBUG] clck_gen.py:113 IND CLOCK 24582
2026-01-29 02:32:06.126 [DEBUG] clck_gen.py:113 IND CLOCK 24684
2026-01-29 02:32:06.604 [DEBUG] clck_gen.py:113 IND CLOCK 24786
2026-01-29 02:32:07.081 [DEBUG] clck_gen.py:113 IND CLOCK 24888
2026-01-29 02:32:07.559 [DEBUG] clck_gen.py:113 IND CLOCK 24990
2026-01-29 02:32:08.037 [DEBUG] clck_gen.py:113 IND CLOCK 25092
2026-01-29 02:32:08.514 [DEBUG] clck_gen.py:113 IND CLOCK 25194
2026-01-29 02:32:08.992 [DEBUG] clck_gen.py:113 IND CLOCK 25296
2026-01-29 02:32:09.470 [DEBUG] clck_gen.py:113 IND CLOCK 25398
2026-01-29 02:32:09.949 [DEBUG] clck_gen.py:113 IND CLOCK 25500
2026-01-29 02:32:10.426 [DEBUG] clck_gen.py:113 IND CLOCK 25602
2026-01-29 02:32:10.904 [DEBUG] clck_gen.py:113 IND CLOCK 25704
2026-01-29 02:32:11.382 [DEBUG] clck_gen.py:113 IND CLOCK 25806
2026-01-29 02:32:11.859 [DEBUG] clck_gen.py:113 IND CLOCK 25908
2026-01-29 02:32:12.337 [DEBUG] clck_gen.py:113 IND CLOCK 26010
2026-01-29 02:32:12.815 [DEBUG] clck_gen.py:113 IND CLOCK 26112
2026-01-29 02:32:13.292 [DEBUG] clck_gen.py:113 IND CLOCK 26214
2026-01-29 02:32:13.770 [DEBUG] clck_gen.py:113 IND CLOCK 26316
2026-01-29 02:32:14.249 [DEBUG] clck_gen.py:113 IND CLOCK 26418
2026-01-29 02:32:14.727 [DEBUG] clck_gen.py:113 IND CLOCK 26520
2026-01-29 02:32:15.205 [DEBUG] clck_gen.py:113 IND CLOCK 26622
2026-01-29 02:32:15.683 [DEBUG] clck_gen.py:113 IND CLOCK 26724
2026-01-29 02:32:16.161 [DEBUG] clck_gen.py:113 IND CLOCK 26826
2026-01-29 02:32:16.638 [DEBUG] clck_gen.py:113 IND CLOCK 26928
2026-01-29 02:32:17.113 [DEBUG] clck_gen.py:113 IND CLOCK 27030
2026-01-29 02:32:17.591 [DEBUG] clck_gen.py:113 IND CLOCK 27132
2026-01-29 02:32:18.068 [DEBUG] clck_gen.py:113 IND CLOCK 27234
2026-01-29 02:32:18.546 [DEBUG] clck_gen.py:113 IND CLOCK 27336
2026-01-29 02:32:19.025 [DEBUG] clck_gen.py:113 IND CLOCK 27438
2026-01-29 02:32:19.502 [DEBUG] clck_gen.py:113 IND CLOCK 27540
2026-01-29 02:32:19.980 [DEBUG] clck_gen.py:113 IND CLOCK 27642
2026-01-29 02:32:20.458 [DEBUG] clck_gen.py:113 IND CLOCK 27744
2026-01-29 02:32:20.936 [DEBUG] clck_gen.py:113 IND CLOCK 27846
2026-01-29 02:32:21.414 [DEBUG] clck_gen.py:113 IND CLOCK 27948
2026-01-29 02:32:21.893 [DEBUG] clck_gen.py:113 IND CLOCK 28050
2026-01-29 02:32:22.372 [DEBUG] clck_gen.py:113 IND CLOCK 28152
2026-01-29 02:32:22.850 [DEBUG] clck_gen.py:113 IND CLOCK 28254
2026-01-29 02:32:23.329 [DEBUG] clck_gen.py:113 IND CLOCK 28356
2026-01-29 02:32:23.806 [DEBUG] clck_gen.py:113 IND CLOCK 28458
2026-01-29 02:32:24.284 [DEBUG] clck_gen.py:113 IND CLOCK 28560
2026-01-29 02:32:24.762 [DEBUG] clck_gen.py:113 IND CLOCK 28662
2026-01-29 02:32:25.240 [DEBUG] clck_gen.py:113 IND CLOCK 28764
2026-01-29 02:32:25.718 [DEBUG] clck_gen.py:113 IND CLOCK 28866
2026-01-29 02:32:26.195 [DEBUG] clck_gen.py:113 IND CLOCK 28968
2026-01-29 02:32:26.673 [DEBUG] clck_gen.py:113 IND CLOCK 29070
2026-01-29 02:32:27.150 [DEBUG] clck_gen.py:113 IND CLOCK 29172
2026-01-29 02:32:27.629 [DEBUG] clck_gen.py:113 IND CLOCK 29274
2026-01-29 02:32:28.107 [DEBUG] clck_gen.py:113 IND CLOCK 29376
2026-01-29 02:32:28.585 [DEBUG] clck_gen.py:113 IND CLOCK 29478
2026-01-29 02:32:28.660 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:32:28.661 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:32:28.675 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 02:32:28.675 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 02:32:28.682 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 02:32:28.682 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:32:28.682 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:32:28.682 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:32:28.684 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 02:32:28.684 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:32:28.684 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:32:28.684 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:32:28.684 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.28.20:5700) Recv POWEROFF cmd
2026-01-29 02:32:28.684 [INFO] ctrl_if_trx.py:117 (BTS@172.18.28.20:5700) Stopping transceiver...
2026-01-29 02:32:28.684 [INFO] transceiver.py:246 Stopping clock generator
2026-01-29 02:32:28.684 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=29501 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:32:28.684 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=29501 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:32:28.684 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=29501 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:32:28.684 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=29501 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:32:28.684 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=29501 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:32:28.684 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=29501 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:32:28.684 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=29501 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:32:28.684 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=29501 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:32:33.686 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.28.20:5700) Recv POWEROFF cmd
2026-01-29 02:32:33.686 [INFO] ctrl_if_trx.py:117 (BTS@172.18.28.20:5700) Stopping transceiver...
2026-01-29 02:32:33.689 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:32:33.689 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:32:33.689 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 02:32:33.689 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:32:33.699 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 02:32:33.701 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.28.20:5700) Recv SETFORMAT cmd
2026-01-29 02:32:33.701 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.28.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:32:33.702 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.28.20:5700) Recv SETFORMAT cmd
2026-01-29 02:32:33.702 [INFO] ctrl_if_trx.py:201 (BTS@172.18.28.20:5700) TRXD header version 1 -> 1
2026-01-29 02:32:33.707 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.28.20:5700/1) Recv RXTUNE cmd
2026-01-29 02:32:33.707 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.28.20:5700/1) Recv TXTUNE cmd
2026-01-29 02:32:33.708 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.28.20:5700/1) Recv SETFORMAT cmd
2026-01-29 02:32:33.708 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.28.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:32:33.708 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:32:33.708 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.28.20:5700/1) Recv NOMTXPOWER cmd
2026-01-29 02:32:33.708 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.28.20:5700/1) Recv SETFORMAT cmd
2026-01-29 02:32:33.708 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.28.20:5700/1) TRXD header version 1 -> 1
2026-01-29 02:32:33.710 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.28.20:5700/2) Recv RXTUNE cmd
2026-01-29 02:32:33.710 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.28.20:5700/2) Recv TXTUNE cmd
2026-01-29 02:32:33.710 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.28.20:5700/2) Recv SETFORMAT cmd
2026-01-29 02:32:33.710 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.28.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:32:33.711 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:32:33.711 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.28.20:5700/2) Recv NOMTXPOWER cmd
2026-01-29 02:32:33.711 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.28.20:5700/2) Recv SETFORMAT cmd
2026-01-29 02:32:33.711 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.28.20:5700/2) TRXD header version 1 -> 1
2026-01-29 02:32:33.713 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.28.20:5700/3) Recv RXTUNE cmd
2026-01-29 02:32:33.713 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.28.20:5700/3) Recv TXTUNE cmd
2026-01-29 02:32:33.713 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.28.20:5700/3) Recv SETFORMAT cmd
2026-01-29 02:32:33.713 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.28.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:32:33.713 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:32:33.713 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.28.20:5700/3) Recv NOMTXPOWER cmd
2026-01-29 02:32:33.714 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.28.20:5700/3) Recv SETFORMAT cmd
2026-01-29 02:32:33.714 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.28.20:5700/3) TRXD header version 1 -> 1
2026-01-29 02:32:33.716 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.28.20:5700) Recv RXTUNE cmd
2026-01-29 02:32:33.716 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETTSC
2026-01-29 02:32:33.716 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETTSC
2026-01-29 02:32:33.716 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETTSC
2026-01-29 02:32:33.716 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.28.20:5700) Recv TXTUNE cmd
2026-01-29 02:32:33.716 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETRXGAIN
2026-01-29 02:32:33.716 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETRXGAIN
2026-01-29 02:32:33.717 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETRXGAIN
2026-01-29 02:32:33.717 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETTSC
2026-01-29 02:32:33.717 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:32:33.717 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:32:33.717 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:32:33.717 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.28.20:5700) Recv NOMTXPOWER cmd
2026-01-29 02:32:33.717 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:32:33.717 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:32:33.717 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:32:33.717 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.28.20:5700) Recv POWERON CMD
2026-01-29 02:32:33.717 [INFO] ctrl_if_trx.py:109 (BTS@172.18.28.20:5700) Starting transceiver...
2026-01-29 02:32:33.717 [INFO] transceiver.py:243 Starting clock generator
2026-01-29 02:32:33.717 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-01-29 02:32:33.717 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:32:33.717 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:32:33.717 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:32:33.717 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETRXGAIN
2026-01-29 02:32:33.717 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:32:33.717 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:32:33.717 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:32:33.717 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:32:33.718 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:32:33.718 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:32:33.718 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:32:33.718 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:32:33.718 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:32:33.718 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:32:33.718 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:32:33.718 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:32:33.718 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:32:33.718 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:32:33.719 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:32:33.719 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:32:33.719 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:32:33.719 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:32:33.719 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:32:33.719 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:32:33.719 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:32:33.719 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:32:33.719 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:32:33.719 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:32:33.719 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:32:33.719 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:32:33.719 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 02:32:33.719 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.28.20:5700) Recv POWEROFF cmd
2026-01-29 02:32:33.719 [INFO] ctrl_if_trx.py:117 (BTS@172.18.28.20:5700) Stopping transceiver...
2026-01-29 02:32:33.719 [INFO] transceiver.py:246 Stopping clock generator
2026-01-29 02:32:38.725 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.28.20:5700) Recv POWEROFF cmd
2026-01-29 02:32:38.725 [INFO] ctrl_if_trx.py:117 (BTS@172.18.28.20:5700) Stopping transceiver...
2026-01-29 02:32:38.725 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:32:38.725 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:32:38.725 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:32:38.725 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 02:32:38.734 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 02:32:38.736 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.28.20:5700) Recv SETFORMAT cmd
2026-01-29 02:32:38.736 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.28.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:32:38.736 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.28.20:5700) Recv SETFORMAT cmd
2026-01-29 02:32:38.736 [INFO] ctrl_if_trx.py:201 (BTS@172.18.28.20:5700) TRXD header version 1 -> 1
2026-01-29 02:32:38.740 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.28.20:5700/1) Recv RXTUNE cmd
2026-01-29 02:32:38.741 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.28.20:5700/1) Recv TXTUNE cmd
2026-01-29 02:32:38.741 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.28.20:5700/1) Recv SETFORMAT cmd
2026-01-29 02:32:38.742 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.28.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:32:38.742 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:32:38.742 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.28.20:5700/1) Recv NOMTXPOWER cmd
2026-01-29 02:32:38.743 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.28.20:5700/1) Recv SETFORMAT cmd
2026-01-29 02:32:38.743 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.28.20:5700/1) TRXD header version 1 -> 1
2026-01-29 02:32:38.744 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.28.20:5700/2) Recv RXTUNE cmd
2026-01-29 02:32:38.745 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.28.20:5700/2) Recv TXTUNE cmd
2026-01-29 02:32:38.745 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.28.20:5700/2) Recv SETFORMAT cmd
2026-01-29 02:32:38.745 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.28.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:32:38.745 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:32:38.745 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.28.20:5700/2) Recv NOMTXPOWER cmd
2026-01-29 02:32:38.745 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.28.20:5700/2) Recv SETFORMAT cmd
2026-01-29 02:32:38.745 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.28.20:5700/2) TRXD header version 1 -> 1
2026-01-29 02:32:38.747 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.28.20:5700/3) Recv RXTUNE cmd
2026-01-29 02:32:38.748 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.28.20:5700/3) Recv TXTUNE cmd
2026-01-29 02:32:38.748 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.28.20:5700/3) Recv SETFORMAT cmd
2026-01-29 02:32:38.748 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.28.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:32:38.748 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:32:38.748 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.28.20:5700/3) Recv NOMTXPOWER cmd
2026-01-29 02:32:38.748 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.28.20:5700/3) Recv SETFORMAT cmd
2026-01-29 02:32:38.748 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.28.20:5700/3) TRXD header version 1 -> 1
2026-01-29 02:32:38.751 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.28.20:5700) Recv RXTUNE cmd
2026-01-29 02:32:38.751 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETTSC
2026-01-29 02:32:38.751 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETTSC
2026-01-29 02:32:38.751 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETTSC
2026-01-29 02:32:38.751 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.28.20:5700) Recv TXTUNE cmd
2026-01-29 02:32:38.751 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETRXGAIN
2026-01-29 02:32:38.751 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETRXGAIN
2026-01-29 02:32:38.751 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETRXGAIN
2026-01-29 02:32:38.751 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETTSC
2026-01-29 02:32:38.751 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:32:38.751 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:32:38.752 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:32:38.752 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.28.20:5700) Recv NOMTXPOWER cmd
2026-01-29 02:32:38.752 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:32:38.752 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:32:38.752 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:32:38.752 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.28.20:5700) Recv POWERON CMD
2026-01-29 02:32:38.752 [INFO] ctrl_if_trx.py:109 (BTS@172.18.28.20:5700) Starting transceiver...
2026-01-29 02:32:38.752 [INFO] transceiver.py:243 Starting clock generator
2026-01-29 02:32:38.752 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-01-29 02:32:38.752 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:32:38.752 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:32:38.752 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:32:38.752 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETRXGAIN
2026-01-29 02:32:38.752 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:32:38.752 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:32:38.752 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:32:38.752 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:32:38.753 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:32:38.753 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:32:38.753 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:32:38.753 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:32:38.753 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:32:38.753 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:32:38.753 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:32:38.753 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:32:38.753 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:32:38.753 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:32:38.753 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:32:38.753 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:32:38.753 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:32:38.753 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:32:38.753 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:32:38.753 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:32:38.753 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:32:38.753 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:32:38.753 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:32:38.757 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-01-29 02:32:39.239 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-01-29 02:32:39.282 [DEBUG] fake_trx.py:278 (BTS@172.18.28.20:5700) Recv FAKE_TOA cmd
2026-01-29 02:32:39.285 [DEBUG] fake_trx.py:297 (BTS@172.18.28.20:5700) Recv FAKE_RSSI cmd
2026-01-29 02:32:39.286 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:32:39.288 [DEBUG] fake_trx.py:322 (BTS@172.18.28.20:5700) Recv FAKE_CI cmd
2026-01-29 02:32:39.308 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 02:32:39.308 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 02:32:39.308 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 02:32:39.334 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 02:32:39.334 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 02:32:39.334 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 02:32:39.336 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:32:39.341 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:32:39.341 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 02:32:39.342 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 02:32:39.342 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.28.22:6700) Recv POWERON CMD
2026-01-29 02:32:39.342 [INFO] ctrl_if_trx.py:109 (MS@172.18.28.22:6700) Starting transceiver...
2026-01-29 02:32:39.391 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 02:32:39.392 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 02:32:39.392 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:32:39.393 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:32:39.716 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-01-29 02:32:39.755 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 02:32:39.756 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:32:39.757 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:32:39.759 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:32:40.194 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-01-29 02:32:40.672 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-01-29 02:32:40.755 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 02:32:40.757 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:32:40.757 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:32:40.760 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:32:40.837 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:32:40.838 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:32:40.842 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 02:32:40.842 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 02:32:40.855 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 02:32:40.855 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 02:32:40.855 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 02:32:40.861 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 02:32:40.861 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 02:32:40.861 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 02:32:40.861 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:32:40.862 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:32:40.862 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 02:32:40.862 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 02:32:40.862 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.28.22:6700) Recv POWERON CMD
2026-01-29 02:32:40.862 [INFO] ctrl_if_trx.py:109 (MS@172.18.28.22:6700) Starting transceiver...
2026-01-29 02:32:40.906 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 02:32:40.907 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 02:32:40.907 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:32:40.907 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:32:41.148 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-01-29 02:32:41.626 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-01-29 02:32:41.756 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 02:32:41.757 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:32:41.758 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:32:41.761 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:32:42.105 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-01-29 02:32:42.583 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-01-29 02:32:42.757 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 02:32:42.758 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:32:42.758 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:32:42.762 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:32:43.061 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-01-29 02:32:43.212 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:32:43.213 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:32:43.217 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 02:32:43.217 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 02:32:43.235 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 02:32:43.235 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 02:32:43.235 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 02:32:43.241 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 02:32:43.241 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 02:32:43.241 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 02:32:43.241 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:32:43.243 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:32:43.243 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 02:32:43.243 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 02:32:43.243 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.28.22:6700) Recv POWERON CMD
2026-01-29 02:32:43.243 [INFO] ctrl_if_trx.py:109 (MS@172.18.28.22:6700) Starting transceiver...
2026-01-29 02:32:43.296 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 02:32:43.296 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 02:32:43.296 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:32:43.296 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:32:43.533 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-01-29 02:32:43.758 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 02:32:43.759 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:32:43.759 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:32:43.763 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:32:44.010 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-01-29 02:32:44.488 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-01-29 02:32:44.966 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-01-29 02:32:45.444 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-01-29 02:32:45.922 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-01-29 02:32:46.400 [DEBUG] clck_gen.py:113 IND CLOCK 1632
2026-01-29 02:32:46.791 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:32:46.792 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:32:46.795 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 02:32:46.795 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 02:32:46.815 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 02:32:46.815 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 02:32:46.815 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 02:32:46.821 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 02:32:46.821 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 02:32:46.821 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 02:32:46.821 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:32:46.823 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:32:46.823 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 02:32:46.823 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 02:32:46.823 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.28.22:6700) Recv POWERON CMD
2026-01-29 02:32:46.823 [INFO] ctrl_if_trx.py:109 (MS@172.18.28.22:6700) Starting transceiver...
2026-01-29 02:32:46.869 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 02:32:46.869 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 02:32:46.870 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:32:46.870 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:32:46.876 [DEBUG] clck_gen.py:113 IND CLOCK 1734
2026-01-29 02:32:47.354 [DEBUG] clck_gen.py:113 IND CLOCK 1836
2026-01-29 02:32:47.831 [DEBUG] clck_gen.py:113 IND CLOCK 1938
2026-01-29 02:32:48.309 [DEBUG] clck_gen.py:113 IND CLOCK 2040
2026-01-29 02:32:48.787 [DEBUG] clck_gen.py:113 IND CLOCK 2142
2026-01-29 02:32:49.265 [DEBUG] clck_gen.py:113 IND CLOCK 2244
2026-01-29 02:32:49.743 [DEBUG] clck_gen.py:113 IND CLOCK 2346
2026-01-29 02:32:50.220 [DEBUG] clck_gen.py:113 IND CLOCK 2448
2026-01-29 02:32:50.303 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:32:50.304 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:32:50.307 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 02:32:50.307 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 02:32:50.315 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 02:32:50.315 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:32:50.315 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:32:50.315 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:32:50.316 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 02:32:50.316 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:32:50.316 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:32:50.316 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:32:50.316 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.28.20:5700) Recv POWEROFF cmd
2026-01-29 02:32:50.316 [INFO] ctrl_if_trx.py:117 (BTS@172.18.28.20:5700) Stopping transceiver...
2026-01-29 02:32:50.316 [INFO] transceiver.py:246 Stopping clock generator
2026-01-29 02:32:55.318 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.28.20:5700) Recv POWEROFF cmd
2026-01-29 02:32:55.318 [INFO] ctrl_if_trx.py:117 (BTS@172.18.28.20:5700) Stopping transceiver...
2026-01-29 02:32:55.320 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:32:55.320 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:32:55.321 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:32:55.321 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 02:32:55.330 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 02:32:55.331 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.28.20:5700) Recv SETFORMAT cmd
2026-01-29 02:32:55.331 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.28.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:32:55.332 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.28.20:5700) Recv SETFORMAT cmd
2026-01-29 02:32:55.332 [INFO] ctrl_if_trx.py:201 (BTS@172.18.28.20:5700) TRXD header version 1 -> 1
2026-01-29 02:32:55.335 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.28.20:5700/1) Recv RXTUNE cmd
2026-01-29 02:32:55.335 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.28.20:5700/1) Recv TXTUNE cmd
2026-01-29 02:32:55.336 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.28.20:5700/1) Recv SETFORMAT cmd
2026-01-29 02:32:55.336 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.28.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:32:55.336 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:32:55.336 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.28.20:5700/1) Recv NOMTXPOWER cmd
2026-01-29 02:32:55.337 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.28.20:5700/1) Recv SETFORMAT cmd
2026-01-29 02:32:55.337 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.28.20:5700/1) TRXD header version 1 -> 1
2026-01-29 02:32:55.338 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.28.20:5700/2) Recv RXTUNE cmd
2026-01-29 02:32:55.338 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.28.20:5700/2) Recv TXTUNE cmd
2026-01-29 02:32:55.338 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.28.20:5700/2) Recv SETFORMAT cmd
2026-01-29 02:32:55.338 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.28.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:32:55.338 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:32:55.338 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.28.20:5700/2) Recv NOMTXPOWER cmd
2026-01-29 02:32:55.338 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.28.20:5700/2) Recv SETFORMAT cmd
2026-01-29 02:32:55.338 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.28.20:5700/2) TRXD header version 1 -> 1
2026-01-29 02:32:55.340 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.28.20:5700/3) Recv RXTUNE cmd
2026-01-29 02:32:55.340 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.28.20:5700/3) Recv TXTUNE cmd
2026-01-29 02:32:55.340 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.28.20:5700/3) Recv SETFORMAT cmd
2026-01-29 02:32:55.341 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.28.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:32:55.341 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:32:55.341 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.28.20:5700/3) Recv NOMTXPOWER cmd
2026-01-29 02:32:55.341 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.28.20:5700/3) Recv SETFORMAT cmd
2026-01-29 02:32:55.341 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.28.20:5700/3) TRXD header version 1 -> 1
2026-01-29 02:32:55.343 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.28.20:5700) Recv RXTUNE cmd
2026-01-29 02:32:55.343 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETTSC
2026-01-29 02:32:55.343 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETTSC
2026-01-29 02:32:55.343 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETTSC
2026-01-29 02:32:55.344 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.28.20:5700) Recv TXTUNE cmd
2026-01-29 02:32:55.344 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETRXGAIN
2026-01-29 02:32:55.344 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETRXGAIN
2026-01-29 02:32:55.344 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETRXGAIN
2026-01-29 02:32:55.344 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETTSC
2026-01-29 02:32:55.344 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:32:55.344 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:32:55.344 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:32:55.344 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.28.20:5700) Recv NOMTXPOWER cmd
2026-01-29 02:32:55.344 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:32:55.344 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:32:55.344 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:32:55.344 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.28.20:5700) Recv POWERON CMD
2026-01-29 02:32:55.344 [INFO] ctrl_if_trx.py:109 (BTS@172.18.28.20:5700) Starting transceiver...
2026-01-29 02:32:55.344 [INFO] transceiver.py:243 Starting clock generator
2026-01-29 02:32:55.344 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-01-29 02:32:55.344 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:32:55.344 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:32:55.344 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:32:55.344 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETRXGAIN
2026-01-29 02:32:55.344 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:32:55.344 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:32:55.345 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:32:55.345 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:32:55.345 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:32:55.345 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:32:55.345 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:32:55.345 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:32:55.345 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:32:55.345 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:32:55.345 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:32:55.345 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:32:55.345 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:32:55.345 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:32:55.345 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:32:55.345 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:32:55.345 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:32:55.345 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:32:55.345 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:32:55.345 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:32:55.345 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:32:55.345 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:32:55.345 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:32:55.349 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-01-29 02:32:55.832 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-01-29 02:32:55.873 [DEBUG] fake_trx.py:278 (BTS@172.18.28.20:5700) Recv FAKE_TOA cmd
2026-01-29 02:32:55.875 [DEBUG] fake_trx.py:297 (BTS@172.18.28.20:5700) Recv FAKE_RSSI cmd
2026-01-29 02:32:55.877 [DEBUG] fake_trx.py:322 (BTS@172.18.28.20:5700) Recv FAKE_CI cmd
2026-01-29 02:32:55.878 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:32:55.900 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 02:32:55.900 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 02:32:55.900 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 02:32:55.926 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 02:32:55.926 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 02:32:55.926 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 02:32:55.928 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:32:55.936 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:32:55.936 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 02:32:55.936 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 02:32:55.936 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.28.22:6700) Recv POWERON CMD
2026-01-29 02:32:55.936 [INFO] ctrl_if_trx.py:109 (MS@172.18.28.22:6700) Starting transceiver...
2026-01-29 02:32:55.970 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 02:32:55.971 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 02:32:55.971 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:32:55.971 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:32:56.309 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-01-29 02:32:56.347 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 02:32:56.348 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:32:56.348 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:32:56.351 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:32:56.787 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-01-29 02:32:57.265 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-01-29 02:32:57.348 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:32:57.349 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 02:32:57.349 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:32:57.352 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:32:57.743 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-01-29 02:32:58.221 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-01-29 02:32:58.349 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:32:58.350 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 02:32:58.350 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:32:58.353 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:32:58.699 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-01-29 02:32:59.177 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-01-29 02:32:59.350 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 02:32:59.351 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:32:59.351 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:32:59.354 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:32:59.654 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-01-29 02:33:00.132 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-01-29 02:33:00.351 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 02:33:00.351 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:33:00.351 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:33:00.354 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:33:00.610 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-01-29 02:33:01.088 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-01-29 02:33:01.566 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-01-29 02:33:02.044 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-01-29 02:33:02.522 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-01-29 02:33:03.000 [DEBUG] clck_gen.py:113 IND CLOCK 1632
2026-01-29 02:33:03.478 [DEBUG] clck_gen.py:113 IND CLOCK 1734
2026-01-29 02:33:03.956 [DEBUG] clck_gen.py:113 IND CLOCK 1836
2026-01-29 02:33:04.434 [DEBUG] clck_gen.py:113 IND CLOCK 1938
2026-01-29 02:33:04.912 [DEBUG] clck_gen.py:113 IND CLOCK 2040
2026-01-29 02:33:05.390 [DEBUG] clck_gen.py:113 IND CLOCK 2142
2026-01-29 02:33:05.867 [DEBUG] clck_gen.py:113 IND CLOCK 2244
2026-01-29 02:33:06.345 [DEBUG] clck_gen.py:113 IND CLOCK 2346
2026-01-29 02:33:06.823 [DEBUG] clck_gen.py:113 IND CLOCK 2448
2026-01-29 02:33:07.301 [DEBUG] clck_gen.py:113 IND CLOCK 2550
2026-01-29 02:33:07.779 [DEBUG] clck_gen.py:113 IND CLOCK 2652
2026-01-29 02:33:08.257 [DEBUG] clck_gen.py:113 IND CLOCK 2754
2026-01-29 02:33:08.734 [DEBUG] clck_gen.py:113 IND CLOCK 2856
2026-01-29 02:33:09.212 [DEBUG] clck_gen.py:113 IND CLOCK 2958
2026-01-29 02:33:09.690 [DEBUG] clck_gen.py:113 IND CLOCK 3060
2026-01-29 02:33:10.168 [DEBUG] clck_gen.py:113 IND CLOCK 3162
2026-01-29 02:33:10.646 [DEBUG] clck_gen.py:113 IND CLOCK 3264
2026-01-29 02:33:11.124 [DEBUG] clck_gen.py:113 IND CLOCK 3366
2026-01-29 02:33:11.419 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:33:11.420 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:33:11.423 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 02:33:11.424 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 02:33:11.434 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 02:33:11.434 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 02:33:11.434 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 02:33:11.440 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 02:33:11.440 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 02:33:11.440 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 02:33:11.440 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:33:11.441 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:33:11.442 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 02:33:11.442 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 02:33:11.442 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.28.22:6700) Recv POWERON CMD
2026-01-29 02:33:11.442 [INFO] ctrl_if_trx.py:109 (MS@172.18.28.22:6700) Starting transceiver...
2026-01-29 02:33:11.448 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 02:33:11.448 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 02:33:11.448 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:33:11.448 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:33:11.600 [DEBUG] clck_gen.py:113 IND CLOCK 3468
2026-01-29 02:33:12.078 [DEBUG] clck_gen.py:113 IND CLOCK 3570
2026-01-29 02:33:12.556 [DEBUG] clck_gen.py:113 IND CLOCK 3672
2026-01-29 02:33:13.034 [DEBUG] clck_gen.py:113 IND CLOCK 3774
2026-01-29 02:33:13.513 [DEBUG] clck_gen.py:113 IND CLOCK 3876
2026-01-29 02:33:13.991 [DEBUG] clck_gen.py:113 IND CLOCK 3978
2026-01-29 02:33:14.469 [DEBUG] clck_gen.py:113 IND CLOCK 4080
2026-01-29 02:33:14.947 [DEBUG] clck_gen.py:113 IND CLOCK 4182
2026-01-29 02:33:15.425 [DEBUG] clck_gen.py:113 IND CLOCK 4284
2026-01-29 02:33:15.903 [DEBUG] clck_gen.py:113 IND CLOCK 4386
2026-01-29 02:33:16.381 [DEBUG] clck_gen.py:113 IND CLOCK 4488
2026-01-29 02:33:16.859 [DEBUG] clck_gen.py:113 IND CLOCK 4590
2026-01-29 02:33:17.337 [DEBUG] clck_gen.py:113 IND CLOCK 4692
2026-01-29 02:33:17.815 [DEBUG] clck_gen.py:113 IND CLOCK 4794
2026-01-29 02:33:18.291 [DEBUG] clck_gen.py:113 IND CLOCK 4896
2026-01-29 02:33:18.765 [DEBUG] clck_gen.py:113 IND CLOCK 4998
2026-01-29 02:33:19.241 [DEBUG] clck_gen.py:113 IND CLOCK 5100
2026-01-29 02:33:19.719 [DEBUG] clck_gen.py:113 IND CLOCK 5202
2026-01-29 02:33:20.198 [DEBUG] clck_gen.py:113 IND CLOCK 5304
2026-01-29 02:33:20.676 [DEBUG] clck_gen.py:113 IND CLOCK 5406
2026-01-29 02:33:21.154 [DEBUG] clck_gen.py:113 IND CLOCK 5508
2026-01-29 02:33:21.633 [DEBUG] clck_gen.py:113 IND CLOCK 5610
2026-01-29 02:33:22.111 [DEBUG] clck_gen.py:113 IND CLOCK 5712
2026-01-29 02:33:22.589 [DEBUG] clck_gen.py:113 IND CLOCK 5814
2026-01-29 02:33:23.068 [DEBUG] clck_gen.py:113 IND CLOCK 5916
2026-01-29 02:33:23.545 [DEBUG] clck_gen.py:113 IND CLOCK 6018
2026-01-29 02:33:24.024 [DEBUG] clck_gen.py:113 IND CLOCK 6120
2026-01-29 02:33:24.502 [DEBUG] clck_gen.py:113 IND CLOCK 6222
2026-01-29 02:33:24.980 [DEBUG] clck_gen.py:113 IND CLOCK 6324
2026-01-29 02:33:25.458 [DEBUG] clck_gen.py:113 IND CLOCK 6426
2026-01-29 02:33:25.936 [DEBUG] clck_gen.py:113 IND CLOCK 6528
2026-01-29 02:33:26.414 [DEBUG] clck_gen.py:113 IND CLOCK 6630
2026-01-29 02:33:26.764 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:33:26.766 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:33:26.769 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 02:33:26.769 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 02:33:26.795 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 02:33:26.795 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 02:33:26.795 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 02:33:26.800 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 02:33:26.800 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 02:33:26.800 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 02:33:26.801 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:33:26.802 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:33:26.802 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 02:33:26.802 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 02:33:26.802 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.28.22:6700) Recv POWERON CMD
2026-01-29 02:33:26.802 [INFO] ctrl_if_trx.py:109 (MS@172.18.28.22:6700) Starting transceiver...
2026-01-29 02:33:26.833 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 02:33:26.834 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 02:33:26.834 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:33:26.834 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:33:26.891 [DEBUG] clck_gen.py:113 IND CLOCK 6732
2026-01-29 02:33:27.369 [DEBUG] clck_gen.py:113 IND CLOCK 6834
2026-01-29 02:33:27.847 [DEBUG] clck_gen.py:113 IND CLOCK 6936
2026-01-29 02:33:28.325 [DEBUG] clck_gen.py:113 IND CLOCK 7038
2026-01-29 02:33:28.803 [DEBUG] clck_gen.py:113 IND CLOCK 7140
2026-01-29 02:33:29.281 [DEBUG] clck_gen.py:113 IND CLOCK 7242
2026-01-29 02:33:29.758 [DEBUG] clck_gen.py:113 IND CLOCK 7344
2026-01-29 02:33:30.236 [DEBUG] clck_gen.py:113 IND CLOCK 7446
2026-01-29 02:33:30.714 [DEBUG] clck_gen.py:113 IND CLOCK 7548
2026-01-29 02:33:31.191 [DEBUG] clck_gen.py:113 IND CLOCK 7650
2026-01-29 02:33:31.669 [DEBUG] clck_gen.py:113 IND CLOCK 7752
2026-01-29 02:33:32.147 [DEBUG] clck_gen.py:113 IND CLOCK 7854
2026-01-29 02:33:32.624 [DEBUG] clck_gen.py:113 IND CLOCK 7956
2026-01-29 02:33:33.102 [DEBUG] clck_gen.py:113 IND CLOCK 8058
2026-01-29 02:33:33.580 [DEBUG] clck_gen.py:113 IND CLOCK 8160
2026-01-29 02:33:34.058 [DEBUG] clck_gen.py:113 IND CLOCK 8262
2026-01-29 02:33:34.536 [DEBUG] clck_gen.py:113 IND CLOCK 8364
2026-01-29 02:33:35.014 [DEBUG] clck_gen.py:113 IND CLOCK 8466
2026-01-29 02:33:35.491 [DEBUG] clck_gen.py:113 IND CLOCK 8568
2026-01-29 02:33:35.968 [DEBUG] clck_gen.py:113 IND CLOCK 8670
2026-01-29 02:33:36.446 [DEBUG] clck_gen.py:113 IND CLOCK 8772
2026-01-29 02:33:36.924 [DEBUG] clck_gen.py:113 IND CLOCK 8874
2026-01-29 02:33:37.402 [DEBUG] clck_gen.py:113 IND CLOCK 8976
2026-01-29 02:33:37.880 [DEBUG] clck_gen.py:113 IND CLOCK 9078
2026-01-29 02:33:38.357 [DEBUG] clck_gen.py:113 IND CLOCK 9180
2026-01-29 02:33:38.834 [DEBUG] clck_gen.py:113 IND CLOCK 9282
2026-01-29 02:33:39.312 [DEBUG] clck_gen.py:113 IND CLOCK 9384
2026-01-29 02:33:39.790 [DEBUG] clck_gen.py:113 IND CLOCK 9486
2026-01-29 02:33:40.268 [DEBUG] clck_gen.py:113 IND CLOCK 9588
2026-01-29 02:33:40.745 [DEBUG] clck_gen.py:113 IND CLOCK 9690
2026-01-29 02:33:41.182 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:33:41.183 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:33:41.186 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 02:33:41.187 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 02:33:41.203 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 02:33:41.203 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 02:33:41.204 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 02:33:41.209 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 02:33:41.209 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 02:33:41.210 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 02:33:41.210 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:33:41.211 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:33:41.211 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 02:33:41.211 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 02:33:41.211 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.28.22:6700) Recv POWERON CMD
2026-01-29 02:33:41.211 [INFO] ctrl_if_trx.py:109 (MS@172.18.28.22:6700) Starting transceiver...
2026-01-29 02:33:41.222 [DEBUG] clck_gen.py:113 IND CLOCK 9792
2026-01-29 02:33:41.269 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 02:33:41.269 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 02:33:41.269 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:33:41.269 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:33:41.698 [DEBUG] clck_gen.py:113 IND CLOCK 9894
2026-01-29 02:33:42.175 [DEBUG] clck_gen.py:113 IND CLOCK 9996
2026-01-29 02:33:42.653 [DEBUG] clck_gen.py:113 IND CLOCK 10098
2026-01-29 02:33:43.130 [DEBUG] clck_gen.py:113 IND CLOCK 10200
2026-01-29 02:33:43.608 [DEBUG] clck_gen.py:113 IND CLOCK 10302
2026-01-29 02:33:44.086 [DEBUG] clck_gen.py:113 IND CLOCK 10404
2026-01-29 02:33:44.563 [DEBUG] clck_gen.py:113 IND CLOCK 10506
2026-01-29 02:33:45.041 [DEBUG] clck_gen.py:113 IND CLOCK 10608
2026-01-29 02:33:45.519 [DEBUG] clck_gen.py:113 IND CLOCK 10710
2026-01-29 02:33:45.996 [DEBUG] clck_gen.py:113 IND CLOCK 10812
2026-01-29 02:33:46.475 [DEBUG] clck_gen.py:113 IND CLOCK 10914
2026-01-29 02:33:46.953 [DEBUG] clck_gen.py:113 IND CLOCK 11016
2026-01-29 02:33:47.432 [DEBUG] clck_gen.py:113 IND CLOCK 11118
2026-01-29 02:33:47.909 [DEBUG] clck_gen.py:113 IND CLOCK 11220
2026-01-29 02:33:48.387 [DEBUG] clck_gen.py:113 IND CLOCK 11322
2026-01-29 02:33:48.865 [DEBUG] clck_gen.py:113 IND CLOCK 11424
2026-01-29 02:33:49.343 [DEBUG] clck_gen.py:113 IND CLOCK 11526
2026-01-29 02:33:49.820 [DEBUG] clck_gen.py:113 IND CLOCK 11628
2026-01-29 02:33:50.299 [DEBUG] clck_gen.py:113 IND CLOCK 11730
2026-01-29 02:33:50.777 [DEBUG] clck_gen.py:113 IND CLOCK 11832
2026-01-29 02:33:51.255 [DEBUG] clck_gen.py:113 IND CLOCK 11934
2026-01-29 02:33:51.733 [DEBUG] clck_gen.py:113 IND CLOCK 12036
2026-01-29 02:33:52.212 [DEBUG] clck_gen.py:113 IND CLOCK 12138
2026-01-29 02:33:52.689 [DEBUG] clck_gen.py:113 IND CLOCK 12240
2026-01-29 02:33:53.168 [DEBUG] clck_gen.py:113 IND CLOCK 12342
2026-01-29 02:33:53.645 [DEBUG] clck_gen.py:113 IND CLOCK 12444
2026-01-29 02:33:54.123 [DEBUG] clck_gen.py:113 IND CLOCK 12546
2026-01-29 02:33:54.600 [DEBUG] clck_gen.py:113 IND CLOCK 12648
2026-01-29 02:33:55.078 [DEBUG] clck_gen.py:113 IND CLOCK 12750
2026-01-29 02:33:55.555 [DEBUG] clck_gen.py:113 IND CLOCK 12852
2026-01-29 02:33:55.948 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:33:55.949 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:33:55.952 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 02:33:55.952 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 02:33:55.964 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 02:33:55.964 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:33:55.965 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:33:55.965 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:33:55.969 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 02:33:55.969 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:33:55.970 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:33:55.970 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:33:55.970 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.28.20:5700) Recv POWEROFF cmd
2026-01-29 02:33:55.970 [INFO] ctrl_if_trx.py:117 (BTS@172.18.28.20:5700) Stopping transceiver...
2026-01-29 02:33:55.970 [INFO] transceiver.py:246 Stopping clock generator
2026-01-29 02:33:55.970 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=12943 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:33:55.970 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=12943 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:33:55.970 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=12943 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:33:55.970 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=12943 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:33:55.970 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=12943 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:33:55.970 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=12943 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:34:00.968 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.28.20:5700) Recv POWEROFF cmd
2026-01-29 02:34:00.968 [INFO] ctrl_if_trx.py:117 (BTS@172.18.28.20:5700) Stopping transceiver...
2026-01-29 02:34:00.970 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:34:00.971 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:34:00.971 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:34:00.971 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 02:34:00.981 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 02:34:00.983 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.28.20:5700) Recv SETFORMAT cmd
2026-01-29 02:34:00.983 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.28.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:34:00.983 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.28.20:5700) Recv SETFORMAT cmd
2026-01-29 02:34:00.983 [INFO] ctrl_if_trx.py:201 (BTS@172.18.28.20:5700) TRXD header version 1 -> 1
2026-01-29 02:34:00.986 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.28.20:5700/1) Recv RXTUNE cmd
2026-01-29 02:34:00.986 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.28.20:5700/1) Recv TXTUNE cmd
2026-01-29 02:34:00.987 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.28.20:5700/1) Recv SETFORMAT cmd
2026-01-29 02:34:00.987 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.28.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:34:00.987 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:34:00.987 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.28.20:5700/1) Recv NOMTXPOWER cmd
2026-01-29 02:34:00.988 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.28.20:5700/1) Recv SETFORMAT cmd
2026-01-29 02:34:00.988 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.28.20:5700/1) TRXD header version 1 -> 1
2026-01-29 02:34:00.989 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.28.20:5700/2) Recv RXTUNE cmd
2026-01-29 02:34:00.990 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.28.20:5700/2) Recv TXTUNE cmd
2026-01-29 02:34:00.990 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.28.20:5700/2) Recv SETFORMAT cmd
2026-01-29 02:34:00.990 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.28.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:34:00.990 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:34:00.990 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.28.20:5700/2) Recv NOMTXPOWER cmd
2026-01-29 02:34:00.990 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.28.20:5700/2) Recv SETFORMAT cmd
2026-01-29 02:34:00.990 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.28.20:5700/2) TRXD header version 1 -> 1
2026-01-29 02:34:00.992 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.28.20:5700/3) Recv RXTUNE cmd
2026-01-29 02:34:00.993 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.28.20:5700/3) Recv TXTUNE cmd
2026-01-29 02:34:00.993 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.28.20:5700/3) Recv SETFORMAT cmd
2026-01-29 02:34:00.993 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.28.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:34:00.993 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:34:00.993 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.28.20:5700/3) Recv NOMTXPOWER cmd
2026-01-29 02:34:00.993 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.28.20:5700/3) Recv SETFORMAT cmd
2026-01-29 02:34:00.993 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.28.20:5700/3) TRXD header version 1 -> 1
2026-01-29 02:34:00.996 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.28.20:5700) Recv RXTUNE cmd
2026-01-29 02:34:00.996 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETTSC
2026-01-29 02:34:00.996 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETTSC
2026-01-29 02:34:00.996 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETTSC
2026-01-29 02:34:00.996 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.28.20:5700) Recv TXTUNE cmd
2026-01-29 02:34:00.996 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETRXGAIN
2026-01-29 02:34:00.996 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETRXGAIN
2026-01-29 02:34:00.996 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETRXGAIN
2026-01-29 02:34:00.996 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETTSC
2026-01-29 02:34:00.996 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:34:00.996 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:34:00.996 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:34:00.996 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.28.20:5700) Recv NOMTXPOWER cmd
2026-01-29 02:34:00.996 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:34:00.996 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:34:00.996 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:34:00.996 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.28.20:5700) Recv POWERON CMD
2026-01-29 02:34:00.996 [INFO] ctrl_if_trx.py:109 (BTS@172.18.28.20:5700) Starting transceiver...
2026-01-29 02:34:00.996 [INFO] transceiver.py:243 Starting clock generator
2026-01-29 02:34:00.996 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-01-29 02:34:00.997 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:34:00.997 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:34:00.997 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:34:00.997 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETRXGAIN
2026-01-29 02:34:00.997 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:34:00.997 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:34:00.997 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:34:00.997 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:34:00.997 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:34:00.997 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:34:00.997 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:34:00.997 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:34:00.997 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:34:00.997 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:34:00.997 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:34:00.997 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:34:00.997 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:34:00.997 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:34:00.997 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:34:00.998 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:34:00.998 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:34:00.998 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:34:00.998 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:34:00.998 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:34:00.998 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:34:00.998 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:34:00.998 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:34:00.998 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:34:00.998 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:34:00.998 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:34:00.998 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 02:34:00.998 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.28.20:5700) Recv POWEROFF cmd
2026-01-29 02:34:00.998 [INFO] ctrl_if_trx.py:117 (BTS@172.18.28.20:5700) Stopping transceiver...
2026-01-29 02:34:00.998 [INFO] transceiver.py:246 Stopping clock generator
2026-01-29 02:34:06.002 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.28.20:5700) Recv POWEROFF cmd
2026-01-29 02:34:06.002 [INFO] ctrl_if_trx.py:117 (BTS@172.18.28.20:5700) Stopping transceiver...
2026-01-29 02:34:06.004 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:34:06.005 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:34:06.005 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:34:06.006 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 02:34:06.008 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 02:34:06.008 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.28.20:5700) Recv SETFORMAT cmd
2026-01-29 02:34:06.008 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.28.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:34:06.009 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.28.20:5700) Recv SETFORMAT cmd
2026-01-29 02:34:06.009 [INFO] ctrl_if_trx.py:201 (BTS@172.18.28.20:5700) TRXD header version 1 -> 1
2026-01-29 02:34:06.009 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.28.20:5700/1) Recv RXTUNE cmd
2026-01-29 02:34:06.009 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.28.20:5700/1) Recv TXTUNE cmd
2026-01-29 02:34:06.010 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.28.20:5700/1) Recv SETFORMAT cmd
2026-01-29 02:34:06.010 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.28.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:34:06.010 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:34:06.010 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.28.20:5700/1) Recv NOMTXPOWER cmd
2026-01-29 02:34:06.010 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.28.20:5700/1) Recv SETFORMAT cmd
2026-01-29 02:34:06.010 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.28.20:5700/1) TRXD header version 1 -> 1
2026-01-29 02:34:06.010 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.28.20:5700/2) Recv RXTUNE cmd
2026-01-29 02:34:06.010 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.28.20:5700/2) Recv TXTUNE cmd
2026-01-29 02:34:06.010 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.28.20:5700/2) Recv SETFORMAT cmd
2026-01-29 02:34:06.010 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.28.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:34:06.010 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:34:06.011 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.28.20:5700/2) Recv NOMTXPOWER cmd
2026-01-29 02:34:06.011 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.28.20:5700/2) Recv SETFORMAT cmd
2026-01-29 02:34:06.011 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.28.20:5700/2) TRXD header version 1 -> 1
2026-01-29 02:34:06.011 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.28.20:5700/3) Recv RXTUNE cmd
2026-01-29 02:34:06.011 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.28.20:5700/3) Recv TXTUNE cmd
2026-01-29 02:34:06.011 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.28.20:5700/3) Recv SETFORMAT cmd
2026-01-29 02:34:06.011 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.28.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:34:06.012 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:34:06.012 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.28.20:5700/3) Recv NOMTXPOWER cmd
2026-01-29 02:34:06.012 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.28.20:5700/3) Recv SETFORMAT cmd
2026-01-29 02:34:06.012 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.28.20:5700/3) TRXD header version 1 -> 1
2026-01-29 02:34:06.013 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.28.20:5700) Recv RXTUNE cmd
2026-01-29 02:34:06.013 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETTSC
2026-01-29 02:34:06.013 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETTSC
2026-01-29 02:34:06.013 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETTSC
2026-01-29 02:34:06.013 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.28.20:5700) Recv TXTUNE cmd
2026-01-29 02:34:06.013 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETRXGAIN
2026-01-29 02:34:06.013 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETRXGAIN
2026-01-29 02:34:06.013 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETRXGAIN
2026-01-29 02:34:06.013 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETTSC
2026-01-29 02:34:06.013 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:34:06.013 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:34:06.013 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:34:06.013 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.28.20:5700) Recv NOMTXPOWER cmd
2026-01-29 02:34:06.013 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:34:06.013 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:34:06.013 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:34:06.013 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.28.20:5700) Recv POWERON CMD
2026-01-29 02:34:06.013 [INFO] ctrl_if_trx.py:109 (BTS@172.18.28.20:5700) Starting transceiver...
2026-01-29 02:34:06.013 [INFO] transceiver.py:243 Starting clock generator
2026-01-29 02:34:06.013 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-01-29 02:34:06.014 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:34:06.014 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:34:06.014 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:34:06.014 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETRXGAIN
2026-01-29 02:34:06.014 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:34:06.014 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:34:06.014 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:34:06.014 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:34:06.014 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:34:06.014 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:34:06.014 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:34:06.014 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:34:06.014 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:34:06.014 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:34:06.014 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:34:06.014 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:34:06.014 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:34:06.014 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:34:06.014 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:34:06.014 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:34:06.014 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:34:06.014 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:34:06.014 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:34:06.014 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:34:06.014 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:34:06.014 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:34:06.014 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:34:06.018 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-01-29 02:34:06.502 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-01-29 02:34:06.539 [DEBUG] fake_trx.py:278 (BTS@172.18.28.20:5700) Recv FAKE_TOA cmd
2026-01-29 02:34:06.542 [DEBUG] fake_trx.py:297 (BTS@172.18.28.20:5700) Recv FAKE_RSSI cmd
2026-01-29 02:34:06.542 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:34:06.544 [DEBUG] fake_trx.py:322 (BTS@172.18.28.20:5700) Recv FAKE_CI cmd
2026-01-29 02:34:06.568 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 02:34:06.568 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 02:34:06.569 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 02:34:06.592 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 02:34:06.592 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 02:34:06.592 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 02:34:06.593 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:34:06.600 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:34:06.601 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 02:34:06.601 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 02:34:06.601 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.28.22:6700) Recv POWERON CMD
2026-01-29 02:34:06.601 [INFO] ctrl_if_trx.py:109 (MS@172.18.28.22:6700) Starting transceiver...
2026-01-29 02:34:06.640 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 02:34:06.640 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 02:34:06.641 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:34:06.641 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:34:06.978 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-01-29 02:34:07.016 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 02:34:07.017 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:34:07.017 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:34:07.019 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:34:07.457 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-01-29 02:34:07.935 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-01-29 02:34:08.017 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 02:34:08.018 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:34:08.018 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:34:08.019 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:34:08.413 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-01-29 02:34:08.890 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-01-29 02:34:09.018 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 02:34:09.018 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:34:09.019 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:34:09.020 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:34:09.369 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-01-29 02:34:09.847 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-01-29 02:34:10.019 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 02:34:10.019 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:34:10.019 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:34:10.021 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:34:10.324 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-01-29 02:34:10.802 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-01-29 02:34:11.019 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 02:34:11.020 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:34:11.020 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:34:11.021 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:34:11.280 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-01-29 02:34:11.758 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-01-29 02:34:12.236 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-01-29 02:34:12.714 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-01-29 02:34:13.192 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-01-29 02:34:13.670 [DEBUG] clck_gen.py:113 IND CLOCK 1632
2026-01-29 02:34:14.148 [DEBUG] clck_gen.py:113 IND CLOCK 1734
2026-01-29 02:34:14.626 [DEBUG] clck_gen.py:113 IND CLOCK 1836
2026-01-29 02:34:15.104 [DEBUG] clck_gen.py:113 IND CLOCK 1938
2026-01-29 02:34:15.581 [DEBUG] clck_gen.py:113 IND CLOCK 2040
2026-01-29 02:34:16.060 [DEBUG] clck_gen.py:113 IND CLOCK 2142
2026-01-29 02:34:16.538 [DEBUG] clck_gen.py:113 IND CLOCK 2244
2026-01-29 02:34:17.015 [DEBUG] clck_gen.py:113 IND CLOCK 2346
2026-01-29 02:34:17.219 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:34:17.220 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:34:17.223 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 02:34:17.223 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 02:34:17.242 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 02:34:17.242 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 02:34:17.242 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 02:34:17.248 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 02:34:17.248 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 02:34:17.248 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 02:34:17.249 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:34:17.250 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:34:17.250 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 02:34:17.250 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 02:34:17.250 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.28.22:6700) Recv POWERON CMD
2026-01-29 02:34:17.250 [INFO] ctrl_if_trx.py:109 (MS@172.18.28.22:6700) Starting transceiver...
2026-01-29 02:34:17.296 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 02:34:17.296 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 02:34:17.296 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:34:17.296 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:34:17.488 [DEBUG] clck_gen.py:113 IND CLOCK 2448
2026-01-29 02:34:17.965 [DEBUG] clck_gen.py:113 IND CLOCK 2550
2026-01-29 02:34:18.444 [DEBUG] clck_gen.py:113 IND CLOCK 2652
2026-01-29 02:34:18.923 [DEBUG] clck_gen.py:113 IND CLOCK 2754
2026-01-29 02:34:19.401 [DEBUG] clck_gen.py:113 IND CLOCK 2856
2026-01-29 02:34:19.879 [DEBUG] clck_gen.py:113 IND CLOCK 2958
2026-01-29 02:34:20.357 [DEBUG] clck_gen.py:113 IND CLOCK 3060
2026-01-29 02:34:20.835 [DEBUG] clck_gen.py:113 IND CLOCK 3162
2026-01-29 02:34:21.314 [DEBUG] clck_gen.py:113 IND CLOCK 3264
2026-01-29 02:34:21.792 [DEBUG] clck_gen.py:113 IND CLOCK 3366
2026-01-29 02:34:22.270 [DEBUG] clck_gen.py:113 IND CLOCK 3468
2026-01-29 02:34:22.748 [DEBUG] clck_gen.py:113 IND CLOCK 3570
2026-01-29 02:34:23.226 [DEBUG] clck_gen.py:113 IND CLOCK 3672
2026-01-29 02:34:23.703 [DEBUG] clck_gen.py:113 IND CLOCK 3774
2026-01-29 02:34:24.181 [DEBUG] clck_gen.py:113 IND CLOCK 3876
2026-01-29 02:34:24.659 [DEBUG] clck_gen.py:113 IND CLOCK 3978
2026-01-29 02:34:25.137 [DEBUG] clck_gen.py:113 IND CLOCK 4080
2026-01-29 02:34:25.615 [DEBUG] clck_gen.py:113 IND CLOCK 4182
2026-01-29 02:34:26.093 [DEBUG] clck_gen.py:113 IND CLOCK 4284
2026-01-29 02:34:26.571 [DEBUG] clck_gen.py:113 IND CLOCK 4386
2026-01-29 02:34:27.049 [DEBUG] clck_gen.py:113 IND CLOCK 4488
2026-01-29 02:34:27.527 [DEBUG] clck_gen.py:113 IND CLOCK 4590
2026-01-29 02:34:27.695 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:34:27.696 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:34:27.700 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 02:34:27.700 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 02:34:27.711 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 02:34:27.711 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 02:34:27.711 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 02:34:27.716 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 02:34:27.716 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 02:34:27.716 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 02:34:27.716 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:34:27.718 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:34:27.718 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 02:34:27.718 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 02:34:27.718 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.28.22:6700) Recv POWERON CMD
2026-01-29 02:34:27.718 [INFO] ctrl_if_trx.py:109 (MS@172.18.28.22:6700) Starting transceiver...
2026-01-29 02:34:27.762 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 02:34:27.762 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 02:34:27.762 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:34:27.762 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:34:28.005 [DEBUG] clck_gen.py:113 IND CLOCK 4692
2026-01-29 02:34:28.483 [DEBUG] clck_gen.py:113 IND CLOCK 4794
2026-01-29 02:34:28.961 [DEBUG] clck_gen.py:113 IND CLOCK 4896
2026-01-29 02:34:29.459 [DEBUG] clck_gen.py:113 IND CLOCK 4998
2026-01-29 02:34:29.937 [DEBUG] clck_gen.py:113 IND CLOCK 5100
2026-01-29 02:34:30.414 [DEBUG] clck_gen.py:113 IND CLOCK 5202
2026-01-29 02:34:30.892 [DEBUG] clck_gen.py:113 IND CLOCK 5304
2026-01-29 02:34:31.370 [DEBUG] clck_gen.py:113 IND CLOCK 5406
2026-01-29 02:34:31.847 [DEBUG] clck_gen.py:113 IND CLOCK 5508
2026-01-29 02:34:32.326 [DEBUG] clck_gen.py:113 IND CLOCK 5610
2026-01-29 02:34:32.803 [DEBUG] clck_gen.py:113 IND CLOCK 5712
2026-01-29 02:34:33.281 [DEBUG] clck_gen.py:113 IND CLOCK 5814
2026-01-29 02:34:33.755 [DEBUG] clck_gen.py:113 IND CLOCK 5916
2026-01-29 02:34:34.233 [DEBUG] clck_gen.py:113 IND CLOCK 6018
2026-01-29 02:34:34.710 [DEBUG] clck_gen.py:113 IND CLOCK 6120
2026-01-29 02:34:34.749 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:34:34.750 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:34:34.754 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 02:34:34.754 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 02:34:34.765 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 02:34:34.765 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 02:34:34.765 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 02:34:34.771 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 02:34:34.771 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 02:34:34.771 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 02:34:34.771 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:34:34.772 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:34:34.772 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 02:34:34.773 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 02:34:34.773 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.28.22:6700) Recv POWERON CMD
2026-01-29 02:34:34.773 [INFO] ctrl_if_trx.py:109 (MS@172.18.28.22:6700) Starting transceiver...
2026-01-29 02:34:34.802 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 02:34:34.803 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 02:34:34.803 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:34:34.803 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:34:35.187 [DEBUG] clck_gen.py:113 IND CLOCK 6222
2026-01-29 02:34:35.664 [DEBUG] clck_gen.py:113 IND CLOCK 6324
2026-01-29 02:34:36.142 [DEBUG] clck_gen.py:113 IND CLOCK 6426
2026-01-29 02:34:36.620 [DEBUG] clck_gen.py:113 IND CLOCK 6528
2026-01-29 02:34:37.098 [DEBUG] clck_gen.py:113 IND CLOCK 6630
2026-01-29 02:34:37.576 [DEBUG] clck_gen.py:113 IND CLOCK 6732
2026-01-29 02:34:38.053 [DEBUG] clck_gen.py:113 IND CLOCK 6834
2026-01-29 02:34:38.531 [DEBUG] clck_gen.py:113 IND CLOCK 6936
2026-01-29 02:34:39.009 [DEBUG] clck_gen.py:113 IND CLOCK 7038
2026-01-29 02:34:39.486 [DEBUG] clck_gen.py:113 IND CLOCK 7140
2026-01-29 02:34:39.964 [DEBUG] clck_gen.py:113 IND CLOCK 7242
2026-01-29 02:34:40.441 [DEBUG] clck_gen.py:113 IND CLOCK 7344
2026-01-29 02:34:40.920 [DEBUG] clck_gen.py:113 IND CLOCK 7446
2026-01-29 02:34:41.397 [DEBUG] clck_gen.py:113 IND CLOCK 7548
2026-01-29 02:34:41.861 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:34:41.861 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:34:41.865 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 02:34:41.865 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 02:34:41.875 [DEBUG] clck_gen.py:113 IND CLOCK 7650
2026-01-29 02:34:41.877 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 02:34:41.877 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:34:41.877 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:34:41.877 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:34:41.879 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 02:34:41.880 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:34:41.880 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:34:41.880 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:34:41.880 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.28.20:5700) Recv POWEROFF cmd
2026-01-29 02:34:41.880 [INFO] ctrl_if_trx.py:117 (BTS@172.18.28.20:5700) Stopping transceiver...
2026-01-29 02:34:41.880 [INFO] transceiver.py:246 Stopping clock generator
2026-01-29 02:34:46.881 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.28.20:5700) Recv POWEROFF cmd
2026-01-29 02:34:46.881 [INFO] ctrl_if_trx.py:117 (BTS@172.18.28.20:5700) Stopping transceiver...
2026-01-29 02:34:46.883 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:34:46.883 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:34:46.884 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:34:46.884 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 02:34:46.894 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 02:34:46.895 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.28.20:5700) Recv SETFORMAT cmd
2026-01-29 02:34:46.895 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.28.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:34:46.895 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.28.20:5700) Recv SETFORMAT cmd
2026-01-29 02:34:46.895 [INFO] ctrl_if_trx.py:201 (BTS@172.18.28.20:5700) TRXD header version 1 -> 1
2026-01-29 02:34:46.898 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.28.20:5700/1) Recv RXTUNE cmd
2026-01-29 02:34:46.898 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.28.20:5700/1) Recv TXTUNE cmd
2026-01-29 02:34:46.898 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.28.20:5700/1) Recv SETFORMAT cmd
2026-01-29 02:34:46.899 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.28.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:34:46.899 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:34:46.899 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.28.20:5700/1) Recv NOMTXPOWER cmd
2026-01-29 02:34:46.899 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.28.20:5700/1) Recv SETFORMAT cmd
2026-01-29 02:34:46.899 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.28.20:5700/1) TRXD header version 1 -> 1
2026-01-29 02:34:46.901 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.28.20:5700/2) Recv RXTUNE cmd
2026-01-29 02:34:46.901 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.28.20:5700/2) Recv TXTUNE cmd
2026-01-29 02:34:46.901 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.28.20:5700/2) Recv SETFORMAT cmd
2026-01-29 02:34:46.901 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.28.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:34:46.901 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:34:46.901 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.28.20:5700/2) Recv NOMTXPOWER cmd
2026-01-29 02:34:46.901 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.28.20:5700/2) Recv SETFORMAT cmd
2026-01-29 02:34:46.901 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.28.20:5700/2) TRXD header version 1 -> 1
2026-01-29 02:34:46.903 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.28.20:5700/3) Recv RXTUNE cmd
2026-01-29 02:34:46.903 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.28.20:5700/3) Recv TXTUNE cmd
2026-01-29 02:34:46.903 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.28.20:5700/3) Recv SETFORMAT cmd
2026-01-29 02:34:46.903 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.28.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:34:46.903 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.28.20:5700/3) Recv NOMTXPOWER cmd
2026-01-29 02:34:46.903 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:34:46.903 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.28.20:5700/3) Recv SETFORMAT cmd
2026-01-29 02:34:46.903 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.28.20:5700/3) TRXD header version 1 -> 1
2026-01-29 02:34:46.905 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.28.20:5700) Recv RXTUNE cmd
2026-01-29 02:34:46.905 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETTSC
2026-01-29 02:34:46.905 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETTSC
2026-01-29 02:34:46.905 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETTSC
2026-01-29 02:34:46.905 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.28.20:5700) Recv TXTUNE cmd
2026-01-29 02:34:46.905 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETRXGAIN
2026-01-29 02:34:46.905 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETRXGAIN
2026-01-29 02:34:46.905 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETRXGAIN
2026-01-29 02:34:46.906 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETTSC
2026-01-29 02:34:46.906 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:34:46.906 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:34:46.906 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:34:46.906 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.28.20:5700) Recv NOMTXPOWER cmd
2026-01-29 02:34:46.906 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:34:46.906 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:34:46.906 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:34:46.906 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.28.20:5700) Recv POWERON CMD
2026-01-29 02:34:46.906 [INFO] ctrl_if_trx.py:109 (BTS@172.18.28.20:5700) Starting transceiver...
2026-01-29 02:34:46.906 [INFO] transceiver.py:243 Starting clock generator
2026-01-29 02:34:46.906 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-01-29 02:34:46.906 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:34:46.906 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:34:46.906 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:34:46.906 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETRXGAIN
2026-01-29 02:34:46.906 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:34:46.906 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:34:46.906 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:34:46.906 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:34:46.906 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:34:46.906 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:34:46.906 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:34:46.906 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:34:46.906 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:34:46.907 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:34:46.907 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:34:46.907 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:34:46.907 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:34:46.907 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:34:46.907 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:34:46.907 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:34:46.907 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:34:46.907 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:34:46.907 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:34:46.907 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:34:46.907 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:34:46.907 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:34:46.907 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:34:46.911 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-01-29 02:34:47.394 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-01-29 02:34:47.436 [DEBUG] fake_trx.py:278 (BTS@172.18.28.20:5700) Recv FAKE_TOA cmd
2026-01-29 02:34:47.438 [DEBUG] fake_trx.py:297 (BTS@172.18.28.20:5700) Recv FAKE_RSSI cmd
2026-01-29 02:34:47.438 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:34:47.439 [DEBUG] fake_trx.py:322 (BTS@172.18.28.20:5700) Recv FAKE_CI cmd
2026-01-29 02:34:47.460 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 02:34:47.460 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 02:34:47.461 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 02:34:47.483 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 02:34:47.483 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 02:34:47.483 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 02:34:47.485 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:34:47.492 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:34:47.493 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 02:34:47.493 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 02:34:47.494 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.28.22:6700) Recv POWERON CMD
2026-01-29 02:34:47.494 [INFO] ctrl_if_trx.py:109 (MS@172.18.28.22:6700) Starting transceiver...
2026-01-29 02:34:47.533 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 02:34:47.533 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 02:34:47.534 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:34:47.534 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:34:47.850 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:34:47.851 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:34:47.855 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 02:34:47.855 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 02:34:47.865 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 02:34:47.865 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 02:34:47.865 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 02:34:47.871 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 02:34:47.871 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 02:34:47.871 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 02:34:47.872 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-01-29 02:34:47.872 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:34:47.873 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:34:47.873 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 02:34:47.873 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 02:34:47.873 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.28.22:6700) Recv POWERON CMD
2026-01-29 02:34:47.873 [INFO] ctrl_if_trx.py:109 (MS@172.18.28.22:6700) Starting transceiver...
2026-01-29 02:34:47.908 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 02:34:47.909 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:34:47.910 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:34:47.912 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:34:47.917 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 02:34:47.917 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 02:34:47.917 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:34:47.918 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:34:48.347 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-01-29 02:34:48.397 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:34:48.398 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:34:48.402 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 02:34:48.402 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 02:34:48.420 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 02:34:48.420 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 02:34:48.421 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 02:34:48.426 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 02:34:48.426 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 02:34:48.426 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 02:34:48.427 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:34:48.428 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:34:48.428 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 02:34:48.428 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 02:34:48.428 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.28.22:6700) Recv POWERON CMD
2026-01-29 02:34:48.428 [INFO] ctrl_if_trx.py:109 (MS@172.18.28.22:6700) Starting transceiver...
2026-01-29 02:34:48.431 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 02:34:48.431 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 02:34:48.431 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:34:48.431 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:34:48.824 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-01-29 02:34:48.910 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:34:48.910 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 02:34:48.910 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:34:48.913 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:34:49.215 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:34:49.216 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:34:49.220 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 02:34:49.220 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 02:34:49.238 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 02:34:49.238 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 02:34:49.238 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 02:34:49.244 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 02:34:49.244 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 02:34:49.244 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 02:34:49.244 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:34:49.245 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:34:49.246 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 02:34:49.246 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 02:34:49.246 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.28.22:6700) Recv POWERON CMD
2026-01-29 02:34:49.246 [INFO] ctrl_if_trx.py:109 (MS@172.18.28.22:6700) Starting transceiver...
2026-01-29 02:34:49.294 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 02:34:49.294 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 02:34:49.295 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:34:49.295 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:34:49.302 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-01-29 02:34:49.780 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-01-29 02:34:49.910 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:34:49.911 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 02:34:49.911 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:34:49.914 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:34:50.099 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:34:50.099 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:34:50.104 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 02:34:50.104 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 02:34:50.111 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 02:34:50.111 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:34:50.111 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:34:50.111 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:34:50.112 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 02:34:50.112 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:34:50.112 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:34:50.113 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.28.20:5700) Recv POWEROFF cmd
2026-01-29 02:34:50.113 [INFO] ctrl_if_trx.py:117 (BTS@172.18.28.20:5700) Stopping transceiver...
2026-01-29 02:34:50.113 [INFO] transceiver.py:246 Stopping clock generator
2026-01-29 02:34:50.113 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:34:50.113 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=686 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:34:50.113 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=686 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:34:50.113 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=686 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:34:50.113 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=686 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:34:50.113 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=686 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:34:50.113 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=686 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:34:50.113 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=686 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:34:55.116 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.28.20:5700) Recv POWEROFF cmd
2026-01-29 02:34:55.116 [INFO] ctrl_if_trx.py:117 (BTS@172.18.28.20:5700) Stopping transceiver...
2026-01-29 02:34:55.117 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:34:55.118 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:34:55.118 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:34:55.119 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 02:34:55.126 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 02:34:55.127 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.28.20:5700) Recv SETFORMAT cmd
2026-01-29 02:34:55.127 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.28.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:34:55.127 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.28.20:5700) Recv SETFORMAT cmd
2026-01-29 02:34:55.127 [INFO] ctrl_if_trx.py:201 (BTS@172.18.28.20:5700) TRXD header version 1 -> 1
2026-01-29 02:34:55.131 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.28.20:5700/1) Recv RXTUNE cmd
2026-01-29 02:34:55.132 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.28.20:5700/1) Recv TXTUNE cmd
2026-01-29 02:34:55.132 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.28.20:5700/1) Recv SETFORMAT cmd
2026-01-29 02:34:55.132 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.28.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:34:55.132 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:34:55.133 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.28.20:5700/1) Recv NOMTXPOWER cmd
2026-01-29 02:34:55.133 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.28.20:5700/1) Recv SETFORMAT cmd
2026-01-29 02:34:55.133 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.28.20:5700/1) TRXD header version 1 -> 1
2026-01-29 02:34:55.134 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.28.20:5700/2) Recv RXTUNE cmd
2026-01-29 02:34:55.134 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.28.20:5700/2) Recv TXTUNE cmd
2026-01-29 02:34:55.134 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.28.20:5700/2) Recv SETFORMAT cmd
2026-01-29 02:34:55.134 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.28.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:34:55.134 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:34:55.134 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.28.20:5700/2) Recv NOMTXPOWER cmd
2026-01-29 02:34:55.135 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.28.20:5700/2) Recv SETFORMAT cmd
2026-01-29 02:34:55.135 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.28.20:5700/2) TRXD header version 1 -> 1
2026-01-29 02:34:55.137 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.28.20:5700/3) Recv RXTUNE cmd
2026-01-29 02:34:55.137 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.28.20:5700/3) Recv TXTUNE cmd
2026-01-29 02:34:55.137 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.28.20:5700/3) Recv SETFORMAT cmd
2026-01-29 02:34:55.137 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.28.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:34:55.137 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:34:55.137 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.28.20:5700/3) Recv NOMTXPOWER cmd
2026-01-29 02:34:55.137 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.28.20:5700/3) Recv SETFORMAT cmd
2026-01-29 02:34:55.137 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.28.20:5700/3) TRXD header version 1 -> 1
2026-01-29 02:34:55.140 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.28.20:5700) Recv RXTUNE cmd
2026-01-29 02:34:55.140 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETTSC
2026-01-29 02:34:55.140 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETTSC
2026-01-29 02:34:55.140 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETTSC
2026-01-29 02:34:55.140 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.28.20:5700) Recv TXTUNE cmd
2026-01-29 02:34:55.140 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETRXGAIN
2026-01-29 02:34:55.140 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETRXGAIN
2026-01-29 02:34:55.140 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETRXGAIN
2026-01-29 02:34:55.140 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETTSC
2026-01-29 02:34:55.140 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:34:55.140 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:34:55.140 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:34:55.140 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.28.20:5700) Recv NOMTXPOWER cmd
2026-01-29 02:34:55.140 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:34:55.140 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:34:55.140 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:34:55.140 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.28.20:5700) Recv POWERON CMD
2026-01-29 02:34:55.140 [INFO] ctrl_if_trx.py:109 (BTS@172.18.28.20:5700) Starting transceiver...
2026-01-29 02:34:55.141 [INFO] transceiver.py:243 Starting clock generator
2026-01-29 02:34:55.141 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-01-29 02:34:55.141 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:34:55.141 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:34:55.141 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:34:55.141 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETRXGAIN
2026-01-29 02:34:55.141 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:34:55.141 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:34:55.141 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:34:55.141 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:34:55.141 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:34:55.141 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:34:55.141 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:34:55.141 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:34:55.141 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:34:55.141 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:34:55.141 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:34:55.141 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:34:55.141 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:34:55.141 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:34:55.141 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:34:55.141 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:34:55.141 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:34:55.142 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:34:55.142 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:34:55.142 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:34:55.142 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:34:55.142 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:34:55.142 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:34:55.145 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-01-29 02:34:55.628 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-01-29 02:34:55.668 [DEBUG] fake_trx.py:278 (BTS@172.18.28.20:5700) Recv FAKE_TOA cmd
2026-01-29 02:34:55.671 [DEBUG] fake_trx.py:297 (BTS@172.18.28.20:5700) Recv FAKE_RSSI cmd
2026-01-29 02:34:55.672 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:34:55.673 [DEBUG] fake_trx.py:322 (BTS@172.18.28.20:5700) Recv FAKE_CI cmd
2026-01-29 02:34:55.691 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 02:34:55.691 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 02:34:55.691 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 02:34:55.708 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 02:34:55.708 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 02:34:55.708 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 02:34:55.709 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:34:55.713 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:34:55.713 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 02:34:55.713 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 02:34:55.713 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.28.22:6700) Recv POWERON CMD
2026-01-29 02:34:55.713 [INFO] ctrl_if_trx.py:109 (MS@172.18.28.22:6700) Starting transceiver...
2026-01-29 02:34:55.718 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 02:34:55.718 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 02:34:55.718 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:34:55.718 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:34:56.104 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-01-29 02:34:56.143 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 02:34:56.144 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:34:56.145 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:34:56.146 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:34:56.582 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-01-29 02:34:57.059 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-01-29 02:34:57.144 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 02:34:57.144 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:34:57.147 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:34:57.147 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:34:57.537 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-01-29 02:34:58.015 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-01-29 02:34:58.144 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 02:34:58.145 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:34:58.147 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:34:58.148 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:34:58.493 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-01-29 02:34:58.944 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:34:58.945 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:34:58.949 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 02:34:58.949 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 02:34:58.964 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 02:34:58.964 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 02:34:58.964 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 02:34:58.970 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-01-29 02:34:58.970 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 02:34:58.970 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 02:34:58.970 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 02:34:58.971 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:34:58.972 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:34:58.972 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 02:34:58.972 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 02:34:58.972 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.28.22:6700) Recv POWERON CMD
2026-01-29 02:34:58.972 [INFO] ctrl_if_trx.py:109 (MS@172.18.28.22:6700) Starting transceiver...
2026-01-29 02:34:59.015 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 02:34:59.015 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 02:34:59.016 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:34:59.016 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:34:59.145 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:34:59.146 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 02:34:59.148 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:34:59.149 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:34:59.446 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-01-29 02:34:59.925 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-01-29 02:35:00.147 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 02:35:00.147 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:35:00.149 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:35:00.150 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:35:00.403 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-01-29 02:35:00.881 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-01-29 02:35:01.352 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-01-29 02:35:01.829 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-01-29 02:35:02.307 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-01-29 02:35:02.353 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:35:02.354 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:35:02.357 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 02:35:02.358 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 02:35:02.377 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 02:35:02.377 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 02:35:02.377 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 02:35:02.383 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 02:35:02.383 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 02:35:02.383 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 02:35:02.384 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:35:02.385 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:35:02.385 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 02:35:02.385 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 02:35:02.385 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.28.22:6700) Recv POWERON CMD
2026-01-29 02:35:02.385 [INFO] ctrl_if_trx.py:109 (MS@172.18.28.22:6700) Starting transceiver...
2026-01-29 02:35:02.396 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 02:35:02.396 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 02:35:02.396 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:35:02.396 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:35:02.783 [DEBUG] clck_gen.py:113 IND CLOCK 1632
2026-01-29 02:35:03.261 [DEBUG] clck_gen.py:113 IND CLOCK 1734
2026-01-29 02:35:03.739 [DEBUG] clck_gen.py:113 IND CLOCK 1836
2026-01-29 02:35:04.217 [DEBUG] clck_gen.py:113 IND CLOCK 1938
2026-01-29 02:35:04.695 [DEBUG] clck_gen.py:113 IND CLOCK 2040
2026-01-29 02:35:05.173 [DEBUG] clck_gen.py:113 IND CLOCK 2142
2026-01-29 02:35:05.651 [DEBUG] clck_gen.py:113 IND CLOCK 2244
2026-01-29 02:35:06.042 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:35:06.043 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:35:06.047 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 02:35:06.047 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 02:35:06.067 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 02:35:06.067 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 02:35:06.067 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 02:35:06.072 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 02:35:06.073 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 02:35:06.073 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 02:35:06.073 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:35:06.074 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:35:06.074 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 02:35:06.074 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 02:35:06.074 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.28.22:6700) Recv POWERON CMD
2026-01-29 02:35:06.074 [INFO] ctrl_if_trx.py:109 (MS@172.18.28.22:6700) Starting transceiver...
2026-01-29 02:35:06.121 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 02:35:06.121 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 02:35:06.121 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:35:06.121 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:35:06.128 [DEBUG] clck_gen.py:113 IND CLOCK 2346
2026-01-29 02:35:06.605 [DEBUG] clck_gen.py:113 IND CLOCK 2448
2026-01-29 02:35:07.082 [DEBUG] clck_gen.py:113 IND CLOCK 2550
2026-01-29 02:35:07.560 [DEBUG] clck_gen.py:113 IND CLOCK 2652
2026-01-29 02:35:08.037 [DEBUG] clck_gen.py:113 IND CLOCK 2754
2026-01-29 02:35:08.515 [DEBUG] clck_gen.py:113 IND CLOCK 2856
2026-01-29 02:35:08.993 [DEBUG] clck_gen.py:113 IND CLOCK 2958
2026-01-29 02:35:09.471 [DEBUG] clck_gen.py:113 IND CLOCK 3060
2026-01-29 02:35:09.789 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:35:09.790 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:35:09.794 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 02:35:09.794 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 02:35:09.807 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 02:35:09.807 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:35:09.807 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:35:09.807 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:35:09.810 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 02:35:09.810 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:35:09.810 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:35:09.810 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:35:09.810 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.28.20:5700) Recv POWEROFF cmd
2026-01-29 02:35:09.810 [INFO] ctrl_if_trx.py:117 (BTS@172.18.28.20:5700) Stopping transceiver...
2026-01-29 02:35:09.810 [INFO] transceiver.py:246 Stopping clock generator
2026-01-29 02:35:09.810 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=3134 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:35:09.810 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=3134 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:35:09.810 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=3134 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:35:09.810 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=3134 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:35:09.810 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=3134 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:35:09.810 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=3134 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:35:09.810 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=3134 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:35:09.810 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=3135 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:35:09.810 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=3135 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:35:09.810 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=3135 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:35:09.810 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=3135 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:35:09.810 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=3135 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:35:09.810 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=3135 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:35:09.810 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=3135 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:35:09.810 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=3135 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:35:14.811 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.28.20:5700) Recv POWEROFF cmd
2026-01-29 02:35:14.811 [INFO] ctrl_if_trx.py:117 (BTS@172.18.28.20:5700) Stopping transceiver...
2026-01-29 02:35:14.812 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:35:14.813 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:35:14.814 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:35:14.814 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 02:35:14.821 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 02:35:14.822 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.28.20:5700) Recv SETFORMAT cmd
2026-01-29 02:35:14.822 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.28.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:35:14.823 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.28.20:5700) Recv SETFORMAT cmd
2026-01-29 02:35:14.823 [INFO] ctrl_if_trx.py:201 (BTS@172.18.28.20:5700) TRXD header version 1 -> 1
2026-01-29 02:35:14.824 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.28.20:5700/1) Recv RXTUNE cmd
2026-01-29 02:35:14.825 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.28.20:5700/1) Recv TXTUNE cmd
2026-01-29 02:35:14.825 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.28.20:5700/1) Recv SETFORMAT cmd
2026-01-29 02:35:14.825 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.28.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:35:14.825 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:35:14.826 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.28.20:5700/1) Recv NOMTXPOWER cmd
2026-01-29 02:35:14.826 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.28.20:5700/1) Recv SETFORMAT cmd
2026-01-29 02:35:14.826 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.28.20:5700/1) TRXD header version 1 -> 1
2026-01-29 02:35:14.827 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.28.20:5700/2) Recv RXTUNE cmd
2026-01-29 02:35:14.827 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.28.20:5700/2) Recv TXTUNE cmd
2026-01-29 02:35:14.827 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.28.20:5700/2) Recv SETFORMAT cmd
2026-01-29 02:35:14.827 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.28.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:35:14.827 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:35:14.827 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.28.20:5700/2) Recv NOMTXPOWER cmd
2026-01-29 02:35:14.827 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.28.20:5700/2) Recv SETFORMAT cmd
2026-01-29 02:35:14.827 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.28.20:5700/2) TRXD header version 1 -> 1
2026-01-29 02:35:14.828 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.28.20:5700/3) Recv RXTUNE cmd
2026-01-29 02:35:14.828 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.28.20:5700/3) Recv TXTUNE cmd
2026-01-29 02:35:14.829 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.28.20:5700/3) Recv SETFORMAT cmd
2026-01-29 02:35:14.829 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.28.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:35:14.829 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:35:14.829 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.28.20:5700/3) Recv NOMTXPOWER cmd
2026-01-29 02:35:14.829 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.28.20:5700/3) Recv SETFORMAT cmd
2026-01-29 02:35:14.829 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.28.20:5700/3) TRXD header version 1 -> 1
2026-01-29 02:35:14.831 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.28.20:5700) Recv RXTUNE cmd
2026-01-29 02:35:14.831 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETTSC
2026-01-29 02:35:14.831 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETTSC
2026-01-29 02:35:14.831 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETTSC
2026-01-29 02:35:14.831 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.28.20:5700) Recv TXTUNE cmd
2026-01-29 02:35:14.831 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETRXGAIN
2026-01-29 02:35:14.831 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETRXGAIN
2026-01-29 02:35:14.831 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETRXGAIN
2026-01-29 02:35:14.831 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETTSC
2026-01-29 02:35:14.831 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:35:14.831 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:35:14.831 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:35:14.831 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.28.20:5700) Recv NOMTXPOWER cmd
2026-01-29 02:35:14.831 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:35:14.831 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:35:14.831 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:35:14.831 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.28.20:5700) Recv POWERON CMD
2026-01-29 02:35:14.831 [INFO] ctrl_if_trx.py:109 (BTS@172.18.28.20:5700) Starting transceiver...
2026-01-29 02:35:14.831 [INFO] transceiver.py:243 Starting clock generator
2026-01-29 02:35:14.831 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-01-29 02:35:14.831 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:35:14.831 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:35:14.831 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:35:14.832 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETRXGAIN
2026-01-29 02:35:14.832 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:35:14.832 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:35:14.832 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:35:14.832 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:35:14.832 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:35:14.832 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:35:14.832 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:35:14.832 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:35:14.832 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:35:14.832 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:35:14.832 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:35:14.832 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:35:14.832 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:35:14.832 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:35:14.832 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:35:14.832 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:35:14.832 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:35:14.832 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:35:14.832 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:35:14.832 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:35:14.832 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:35:14.832 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:35:14.832 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:35:14.836 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-01-29 02:35:15.319 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-01-29 02:35:15.357 [DEBUG] fake_trx.py:278 (BTS@172.18.28.20:5700) Recv FAKE_TOA cmd
2026-01-29 02:35:15.359 [DEBUG] fake_trx.py:297 (BTS@172.18.28.20:5700) Recv FAKE_RSSI cmd
2026-01-29 02:35:15.360 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:35:15.361 [DEBUG] fake_trx.py:322 (BTS@172.18.28.20:5700) Recv FAKE_CI cmd
2026-01-29 02:35:15.380 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 02:35:15.380 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 02:35:15.381 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 02:35:15.405 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 02:35:15.405 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 02:35:15.405 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 02:35:15.407 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:35:15.415 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:35:15.415 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 02:35:15.415 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 02:35:15.416 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.28.22:6700) Recv POWERON CMD
2026-01-29 02:35:15.416 [INFO] ctrl_if_trx.py:109 (MS@172.18.28.22:6700) Starting transceiver...
2026-01-29 02:35:15.457 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 02:35:15.458 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 02:35:15.458 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:35:15.458 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:35:15.797 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-01-29 02:35:15.834 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:35:15.834 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 02:35:15.835 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:35:15.837 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:35:15.841 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:35:15.842 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:35:15.846 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 02:35:15.846 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 02:35:15.864 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 02:35:15.864 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 02:35:15.864 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 02:35:15.870 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 02:35:15.871 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 02:35:15.871 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 02:35:15.871 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:35:15.872 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:35:15.872 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 02:35:15.872 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 02:35:15.873 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.28.22:6700) Recv POWERON CMD
2026-01-29 02:35:15.873 [INFO] ctrl_if_trx.py:109 (MS@172.18.28.22:6700) Starting transceiver...
2026-01-29 02:35:15.887 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 02:35:15.887 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 02:35:15.887 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:35:15.888 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:35:16.273 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-01-29 02:35:16.489 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:35:16.490 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:35:16.495 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 02:35:16.495 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 02:35:16.514 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 02:35:16.514 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 02:35:16.514 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 02:35:16.520 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 02:35:16.520 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 02:35:16.520 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 02:35:16.521 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:35:16.522 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:35:16.523 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 02:35:16.523 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 02:35:16.523 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.28.22:6700) Recv POWERON CMD
2026-01-29 02:35:16.523 [INFO] ctrl_if_trx.py:109 (MS@172.18.28.22:6700) Starting transceiver...
2026-01-29 02:35:16.553 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 02:35:16.553 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 02:35:16.554 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:35:16.554 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:35:16.751 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-01-29 02:35:16.834 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:35:16.835 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 02:35:16.835 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:35:16.838 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:35:17.229 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-01-29 02:35:17.619 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:35:17.620 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:35:17.624 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 02:35:17.624 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 02:35:17.643 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 02:35:17.643 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 02:35:17.643 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 02:35:17.649 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 02:35:17.649 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 02:35:17.649 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:35:17.649 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 02:35:17.651 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:35:17.651 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 02:35:17.651 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 02:35:17.651 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.28.22:6700) Recv POWERON CMD
2026-01-29 02:35:17.651 [INFO] ctrl_if_trx.py:109 (MS@172.18.28.22:6700) Starting transceiver...
2026-01-29 02:35:17.701 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 02:35:17.701 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 02:35:17.701 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:35:17.702 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:35:17.706 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-01-29 02:35:17.836 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:35:17.836 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 02:35:17.836 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:35:17.840 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:35:18.184 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-01-29 02:35:18.661 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-01-29 02:35:18.744 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:35:18.745 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:35:18.749 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 02:35:18.749 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 02:35:18.761 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 02:35:18.762 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:35:18.762 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:35:18.762 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:35:18.767 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 02:35:18.768 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:35:18.768 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:35:18.768 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:35:18.768 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.28.20:5700) Recv POWEROFF cmd
2026-01-29 02:35:18.768 [INFO] ctrl_if_trx.py:117 (BTS@172.18.28.20:5700) Stopping transceiver...
2026-01-29 02:35:18.768 [INFO] transceiver.py:246 Stopping clock generator
2026-01-29 02:35:18.769 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=840 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:35:18.769 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=840 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:35:23.763 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.28.20:5700) Recv POWEROFF cmd
2026-01-29 02:35:23.764 [INFO] ctrl_if_trx.py:117 (BTS@172.18.28.20:5700) Stopping transceiver...
2026-01-29 02:35:23.765 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:35:23.767 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:35:23.767 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:35:23.767 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 02:35:23.774 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 02:35:23.775 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.28.20:5700) Recv SETFORMAT cmd
2026-01-29 02:35:23.775 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.28.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:35:23.775 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.28.20:5700) Recv SETFORMAT cmd
2026-01-29 02:35:23.775 [INFO] ctrl_if_trx.py:201 (BTS@172.18.28.20:5700) TRXD header version 1 -> 1
2026-01-29 02:35:23.777 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.28.20:5700/1) Recv RXTUNE cmd
2026-01-29 02:35:23.777 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.28.20:5700/1) Recv TXTUNE cmd
2026-01-29 02:35:23.778 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.28.20:5700/1) Recv SETFORMAT cmd
2026-01-29 02:35:23.778 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.28.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:35:23.778 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:35:23.779 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.28.20:5700/1) Recv NOMTXPOWER cmd
2026-01-29 02:35:23.779 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.28.20:5700/1) Recv SETFORMAT cmd
2026-01-29 02:35:23.779 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.28.20:5700/1) TRXD header version 1 -> 1
2026-01-29 02:35:23.780 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.28.20:5700/2) Recv RXTUNE cmd
2026-01-29 02:35:23.780 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.28.20:5700/2) Recv TXTUNE cmd
2026-01-29 02:35:23.780 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.28.20:5700/2) Recv SETFORMAT cmd
2026-01-29 02:35:23.780 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.28.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:35:23.780 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:35:23.780 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.28.20:5700/2) Recv NOMTXPOWER cmd
2026-01-29 02:35:23.780 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.28.20:5700/2) Recv SETFORMAT cmd
2026-01-29 02:35:23.780 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.28.20:5700/2) TRXD header version 1 -> 1
2026-01-29 02:35:23.782 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.28.20:5700/3) Recv RXTUNE cmd
2026-01-29 02:35:23.782 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.28.20:5700/3) Recv TXTUNE cmd
2026-01-29 02:35:23.782 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.28.20:5700/3) Recv SETFORMAT cmd
2026-01-29 02:35:23.782 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.28.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:35:23.782 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:35:23.782 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.28.20:5700/3) Recv NOMTXPOWER cmd
2026-01-29 02:35:23.782 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.28.20:5700/3) Recv SETFORMAT cmd
2026-01-29 02:35:23.782 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.28.20:5700/3) TRXD header version 1 -> 1
2026-01-29 02:35:23.785 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.28.20:5700) Recv RXTUNE cmd
2026-01-29 02:35:23.785 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETTSC
2026-01-29 02:35:23.785 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETTSC
2026-01-29 02:35:23.785 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETTSC
2026-01-29 02:35:23.785 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.28.20:5700) Recv TXTUNE cmd
2026-01-29 02:35:23.785 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETRXGAIN
2026-01-29 02:35:23.785 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETRXGAIN
2026-01-29 02:35:23.785 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETRXGAIN
2026-01-29 02:35:23.785 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETTSC
2026-01-29 02:35:23.785 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:35:23.785 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:35:23.785 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:35:23.785 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.28.20:5700) Recv NOMTXPOWER cmd
2026-01-29 02:35:23.785 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:35:23.785 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:35:23.785 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:35:23.785 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.28.20:5700) Recv POWERON CMD
2026-01-29 02:35:23.786 [INFO] ctrl_if_trx.py:109 (BTS@172.18.28.20:5700) Starting transceiver...
2026-01-29 02:35:23.786 [INFO] transceiver.py:243 Starting clock generator
2026-01-29 02:35:23.786 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-01-29 02:35:23.786 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:35:23.786 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:35:23.786 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:35:23.786 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETRXGAIN
2026-01-29 02:35:23.786 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:35:23.786 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:35:23.786 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:35:23.786 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:35:23.786 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:35:23.786 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:35:23.786 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:35:23.786 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:35:23.786 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:35:23.786 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:35:23.786 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:35:23.786 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:35:23.786 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:35:23.787 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:35:23.787 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:35:23.787 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:35:23.787 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:35:23.787 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:35:23.787 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:35:23.787 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:35:23.787 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:35:23.787 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:35:23.787 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:35:23.790 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-01-29 02:35:24.273 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-01-29 02:35:24.301 [DEBUG] fake_trx.py:278 (BTS@172.18.28.20:5700) Recv FAKE_TOA cmd
2026-01-29 02:35:24.302 [DEBUG] fake_trx.py:297 (BTS@172.18.28.20:5700) Recv FAKE_RSSI cmd
2026-01-29 02:35:24.302 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:35:24.303 [DEBUG] fake_trx.py:322 (BTS@172.18.28.20:5700) Recv FAKE_CI cmd
2026-01-29 02:35:24.316 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 02:35:24.316 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 02:35:24.316 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 02:35:24.341 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 02:35:24.341 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 02:35:24.341 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 02:35:24.342 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:35:24.347 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:35:24.347 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 02:35:24.347 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 02:35:24.347 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.28.22:6700) Recv POWERON CMD
2026-01-29 02:35:24.347 [INFO] ctrl_if_trx.py:109 (MS@172.18.28.22:6700) Starting transceiver...
2026-01-29 02:35:24.381 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 02:35:24.382 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 02:35:24.382 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:35:24.382 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:35:24.763 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-01-29 02:35:24.789 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:35:24.789 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 02:35:24.789 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:35:24.793 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:35:25.242 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-01-29 02:35:25.719 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-01-29 02:35:25.789 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:35:25.790 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 02:35:25.790 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:35:25.794 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:35:26.197 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-01-29 02:35:26.676 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-01-29 02:35:26.790 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 02:35:26.791 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:35:26.791 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:35:26.795 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:35:27.153 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-01-29 02:35:27.244 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:35:27.245 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:35:27.248 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 02:35:27.248 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 02:35:27.266 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 02:35:27.266 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 02:35:27.266 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 02:35:27.273 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 02:35:27.273 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 02:35:27.273 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 02:35:27.273 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:35:27.274 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:35:27.274 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 02:35:27.274 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 02:35:27.274 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.28.22:6700) Recv POWERON CMD
2026-01-29 02:35:27.274 [INFO] ctrl_if_trx.py:109 (MS@172.18.28.22:6700) Starting transceiver...
2026-01-29 02:35:27.289 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 02:35:27.289 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 02:35:27.289 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:35:27.290 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:35:27.628 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-01-29 02:35:27.791 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:35:27.791 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 02:35:27.792 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:35:27.796 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:35:28.106 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-01-29 02:35:28.585 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-01-29 02:35:28.792 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:35:28.793 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 02:35:28.793 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:35:28.796 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:35:29.062 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-01-29 02:35:29.541 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-01-29 02:35:30.018 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-01-29 02:35:30.496 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-01-29 02:35:30.974 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-01-29 02:35:31.452 [DEBUG] clck_gen.py:113 IND CLOCK 1632
2026-01-29 02:35:31.908 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:35:31.909 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:35:31.912 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 02:35:31.912 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 02:35:31.923 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 02:35:31.923 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 02:35:31.924 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 02:35:31.930 [DEBUG] clck_gen.py:113 IND CLOCK 1734
2026-01-29 02:35:31.930 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 02:35:31.930 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 02:35:31.930 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 02:35:31.930 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:35:31.932 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:35:31.932 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 02:35:31.932 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 02:35:31.932 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.28.22:6700) Recv POWERON CMD
2026-01-29 02:35:31.932 [INFO] ctrl_if_trx.py:109 (MS@172.18.28.22:6700) Starting transceiver...
2026-01-29 02:35:31.975 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 02:35:31.975 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 02:35:31.975 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:35:31.976 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:35:32.406 [DEBUG] clck_gen.py:113 IND CLOCK 1836
2026-01-29 02:35:32.884 [DEBUG] clck_gen.py:113 IND CLOCK 1938
2026-01-29 02:35:33.361 [DEBUG] clck_gen.py:113 IND CLOCK 2040
2026-01-29 02:35:33.839 [DEBUG] clck_gen.py:113 IND CLOCK 2142
2026-01-29 02:35:34.316 [DEBUG] clck_gen.py:113 IND CLOCK 2244
2026-01-29 02:35:34.794 [DEBUG] clck_gen.py:113 IND CLOCK 2346
2026-01-29 02:35:35.271 [DEBUG] clck_gen.py:113 IND CLOCK 2448
2026-01-29 02:35:35.748 [DEBUG] clck_gen.py:113 IND CLOCK 2550
2026-01-29 02:35:36.226 [DEBUG] clck_gen.py:113 IND CLOCK 2652
2026-01-29 02:35:36.704 [DEBUG] clck_gen.py:113 IND CLOCK 2754
2026-01-29 02:35:37.182 [DEBUG] clck_gen.py:113 IND CLOCK 2856
2026-01-29 02:35:37.660 [DEBUG] clck_gen.py:113 IND CLOCK 2958
2026-01-29 02:35:38.138 [DEBUG] clck_gen.py:113 IND CLOCK 3060
2026-01-29 02:35:38.615 [DEBUG] clck_gen.py:113 IND CLOCK 3162
2026-01-29 02:35:38.771 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:35:38.772 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:35:38.776 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 02:35:38.776 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 02:35:38.795 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 02:35:38.795 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 02:35:38.796 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 02:35:38.802 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 02:35:38.802 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 02:35:38.802 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 02:35:38.803 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:35:38.804 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:35:38.804 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 02:35:38.804 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 02:35:38.804 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.28.22:6700) Recv POWERON CMD
2026-01-29 02:35:38.804 [INFO] ctrl_if_trx.py:109 (MS@172.18.28.22:6700) Starting transceiver...
2026-01-29 02:35:38.850 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 02:35:38.850 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 02:35:38.850 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:35:38.851 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:35:39.091 [DEBUG] clck_gen.py:113 IND CLOCK 3264
2026-01-29 02:35:39.569 [DEBUG] clck_gen.py:113 IND CLOCK 3366
2026-01-29 02:35:40.047 [DEBUG] clck_gen.py:113 IND CLOCK 3468
2026-01-29 02:35:40.524 [DEBUG] clck_gen.py:113 IND CLOCK 3570
2026-01-29 02:35:41.002 [DEBUG] clck_gen.py:113 IND CLOCK 3672
2026-01-29 02:35:41.479 [DEBUG] clck_gen.py:113 IND CLOCK 3774
2026-01-29 02:35:41.957 [DEBUG] clck_gen.py:113 IND CLOCK 3876
2026-01-29 02:35:42.434 [DEBUG] clck_gen.py:113 IND CLOCK 3978
2026-01-29 02:35:42.912 [DEBUG] clck_gen.py:113 IND CLOCK 4080
2026-01-29 02:35:43.389 [DEBUG] clck_gen.py:113 IND CLOCK 4182
2026-01-29 02:35:43.867 [DEBUG] clck_gen.py:113 IND CLOCK 4284
2026-01-29 02:35:44.345 [DEBUG] clck_gen.py:113 IND CLOCK 4386
2026-01-29 02:35:44.823 [DEBUG] clck_gen.py:113 IND CLOCK 4488
2026-01-29 02:35:45.301 [DEBUG] clck_gen.py:113 IND CLOCK 4590
2026-01-29 02:35:45.619 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:35:45.620 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:35:45.624 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 02:35:45.624 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 02:35:45.639 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 02:35:45.639 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:35:45.639 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:35:45.639 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:35:45.645 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 02:35:45.645 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:35:45.645 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:35:45.645 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:35:45.646 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.28.20:5700) Recv POWEROFF cmd
2026-01-29 02:35:45.646 [INFO] ctrl_if_trx.py:117 (BTS@172.18.28.20:5700) Stopping transceiver...
2026-01-29 02:35:45.646 [INFO] transceiver.py:246 Stopping clock generator
2026-01-29 02:35:45.646 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=4666 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:35:45.646 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=4666 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:35:45.646 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=4666 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:35:45.646 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=4666 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:35:45.646 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=4666 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:35:45.647 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=4666 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:35:50.641 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.28.20:5700) Recv POWEROFF cmd
2026-01-29 02:35:50.641 [INFO] ctrl_if_trx.py:117 (BTS@172.18.28.20:5700) Stopping transceiver...
2026-01-29 02:35:50.643 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:35:50.643 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:35:50.644 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:35:50.644 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 02:35:50.647 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 02:35:50.648 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.28.20:5700) Recv SETFORMAT cmd
2026-01-29 02:35:50.648 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.28.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:35:50.648 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.28.20:5700) Recv SETFORMAT cmd
2026-01-29 02:35:50.648 [INFO] ctrl_if_trx.py:201 (BTS@172.18.28.20:5700) TRXD header version 1 -> 1
2026-01-29 02:35:50.650 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.28.20:5700/1) Recv RXTUNE cmd
2026-01-29 02:35:50.650 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.28.20:5700/1) Recv TXTUNE cmd
2026-01-29 02:35:50.650 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.28.20:5700/1) Recv SETFORMAT cmd
2026-01-29 02:35:50.650 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.28.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:35:50.651 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:35:50.651 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.28.20:5700/1) Recv NOMTXPOWER cmd
2026-01-29 02:35:50.651 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.28.20:5700/1) Recv SETFORMAT cmd
2026-01-29 02:35:50.651 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.28.20:5700/1) TRXD header version 1 -> 1
2026-01-29 02:35:50.652 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.28.20:5700/2) Recv RXTUNE cmd
2026-01-29 02:35:50.652 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.28.20:5700/2) Recv TXTUNE cmd
2026-01-29 02:35:50.652 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.28.20:5700/2) Recv SETFORMAT cmd
2026-01-29 02:35:50.652 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.28.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:35:50.652 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:35:50.652 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.28.20:5700/2) Recv NOMTXPOWER cmd
2026-01-29 02:35:50.652 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.28.20:5700/2) Recv SETFORMAT cmd
2026-01-29 02:35:50.652 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.28.20:5700/2) TRXD header version 1 -> 1
2026-01-29 02:35:50.654 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.28.20:5700/3) Recv RXTUNE cmd
2026-01-29 02:35:50.654 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.28.20:5700/3) Recv TXTUNE cmd
2026-01-29 02:35:50.654 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.28.20:5700/3) Recv SETFORMAT cmd
2026-01-29 02:35:50.654 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.28.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:35:50.654 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:35:50.654 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.28.20:5700/3) Recv NOMTXPOWER cmd
2026-01-29 02:35:50.654 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.28.20:5700/3) Recv SETFORMAT cmd
2026-01-29 02:35:50.654 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.28.20:5700/3) TRXD header version 1 -> 1
2026-01-29 02:35:50.656 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.28.20:5700) Recv RXTUNE cmd
2026-01-29 02:35:50.656 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETTSC
2026-01-29 02:35:50.656 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETTSC
2026-01-29 02:35:50.656 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETTSC
2026-01-29 02:35:50.656 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.28.20:5700) Recv TXTUNE cmd
2026-01-29 02:35:50.656 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETRXGAIN
2026-01-29 02:35:50.656 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETRXGAIN
2026-01-29 02:35:50.656 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETRXGAIN
2026-01-29 02:35:50.656 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETTSC
2026-01-29 02:35:50.656 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:35:50.656 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:35:50.656 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:35:50.656 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.28.20:5700) Recv NOMTXPOWER cmd
2026-01-29 02:35:50.656 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:35:50.656 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:35:50.656 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:35:50.656 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.28.20:5700) Recv POWERON CMD
2026-01-29 02:35:50.656 [INFO] ctrl_if_trx.py:109 (BTS@172.18.28.20:5700) Starting transceiver...
2026-01-29 02:35:50.656 [INFO] transceiver.py:243 Starting clock generator
2026-01-29 02:35:50.657 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-01-29 02:35:50.657 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:35:50.657 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:35:50.657 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:35:50.657 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETRXGAIN
2026-01-29 02:35:50.657 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:35:50.657 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:35:50.657 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:35:50.657 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:35:50.657 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:35:50.657 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:35:50.657 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:35:50.657 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:35:50.657 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:35:50.657 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:35:50.657 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:35:50.657 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:35:50.657 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:35:50.657 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:35:50.657 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:35:50.657 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:35:50.657 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:35:50.657 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:35:50.657 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:35:50.657 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:35:50.657 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:35:50.657 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:35:50.657 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:35:50.661 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-01-29 02:35:51.144 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-01-29 02:35:51.184 [DEBUG] fake_trx.py:278 (BTS@172.18.28.20:5700) Recv FAKE_TOA cmd
2026-01-29 02:35:51.186 [DEBUG] fake_trx.py:297 (BTS@172.18.28.20:5700) Recv FAKE_RSSI cmd
2026-01-29 02:35:51.188 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:35:51.189 [DEBUG] fake_trx.py:322 (BTS@172.18.28.20:5700) Recv FAKE_CI cmd
2026-01-29 02:35:51.212 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 02:35:51.212 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 02:35:51.212 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 02:35:51.239 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 02:35:51.239 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 02:35:51.240 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 02:35:51.242 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:35:51.249 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:35:51.250 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 02:35:51.250 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 02:35:51.251 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.28.22:6700) Recv POWERON CMD
2026-01-29 02:35:51.251 [INFO] ctrl_if_trx.py:109 (MS@172.18.28.22:6700) Starting transceiver...
2026-01-29 02:35:51.282 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 02:35:51.282 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 02:35:51.283 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:35:51.283 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:35:51.622 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-01-29 02:35:51.659 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 02:35:51.659 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:35:51.660 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:35:51.661 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:35:52.099 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-01-29 02:35:52.577 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-01-29 02:35:52.660 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 02:35:52.660 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:35:52.660 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:35:52.662 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:35:53.043 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:35:53.044 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:35:53.048 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 02:35:53.048 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 02:35:53.055 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-01-29 02:35:53.068 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 02:35:53.068 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 02:35:53.068 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 02:35:53.075 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 02:35:53.075 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 02:35:53.075 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 02:35:53.075 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:35:53.077 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:35:53.077 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 02:35:53.077 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 02:35:53.077 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.28.22:6700) Recv POWERON CMD
2026-01-29 02:35:53.077 [INFO] ctrl_if_trx.py:109 (MS@172.18.28.22:6700) Starting transceiver...
2026-01-29 02:35:53.100 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 02:35:53.100 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 02:35:53.101 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:35:53.101 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:35:53.531 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-01-29 02:35:53.661 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 02:35:53.661 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:35:53.661 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:35:53.662 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:35:54.009 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-01-29 02:35:54.488 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-01-29 02:35:54.661 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:35:54.662 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 02:35:54.662 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:35:54.663 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:35:54.981 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-01-29 02:35:55.459 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-01-29 02:35:55.662 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 02:35:55.662 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:35:55.663 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:35:55.664 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:35:55.859 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:35:55.860 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:35:55.863 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 02:35:55.863 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 02:35:55.875 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 02:35:55.875 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 02:35:55.875 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 02:35:55.882 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 02:35:55.882 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 02:35:55.882 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 02:35:55.882 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:35:55.884 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:35:55.884 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 02:35:55.884 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 02:35:55.884 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.28.22:6700) Recv POWERON CMD
2026-01-29 02:35:55.884 [INFO] ctrl_if_trx.py:109 (MS@172.18.28.22:6700) Starting transceiver...
2026-01-29 02:35:55.929 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 02:35:55.929 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 02:35:55.930 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:35:55.930 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:35:55.935 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-01-29 02:35:56.411 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-01-29 02:35:56.889 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-01-29 02:35:57.367 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-01-29 02:35:57.845 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-01-29 02:35:58.322 [DEBUG] clck_gen.py:113 IND CLOCK 1632
2026-01-29 02:35:58.800 [DEBUG] clck_gen.py:113 IND CLOCK 1734
2026-01-29 02:35:59.278 [DEBUG] clck_gen.py:113 IND CLOCK 1836
2026-01-29 02:35:59.756 [DEBUG] clck_gen.py:113 IND CLOCK 1938
2026-01-29 02:36:00.234 [DEBUG] clck_gen.py:113 IND CLOCK 2040
2026-01-29 02:36:00.389 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:36:00.390 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:36:00.393 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 02:36:00.394 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 02:36:00.407 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 02:36:00.407 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 02:36:00.407 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 02:36:00.415 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 02:36:00.415 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 02:36:00.415 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 02:36:00.415 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:36:00.416 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:36:00.416 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 02:36:00.416 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 02:36:00.416 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.28.22:6700) Recv POWERON CMD
2026-01-29 02:36:00.416 [INFO] ctrl_if_trx.py:109 (MS@172.18.28.22:6700) Starting transceiver...
2026-01-29 02:36:00.468 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 02:36:00.468 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 02:36:00.468 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:36:00.469 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:36:00.709 [DEBUG] clck_gen.py:113 IND CLOCK 2142
2026-01-29 02:36:01.187 [DEBUG] clck_gen.py:113 IND CLOCK 2244
2026-01-29 02:36:01.665 [DEBUG] clck_gen.py:113 IND CLOCK 2346
2026-01-29 02:36:02.142 [DEBUG] clck_gen.py:113 IND CLOCK 2448
2026-01-29 02:36:02.621 [DEBUG] clck_gen.py:113 IND CLOCK 2550
2026-01-29 02:36:03.099 [DEBUG] clck_gen.py:113 IND CLOCK 2652
2026-01-29 02:36:03.578 [DEBUG] clck_gen.py:113 IND CLOCK 2754
2026-01-29 02:36:04.055 [DEBUG] clck_gen.py:113 IND CLOCK 2856
2026-01-29 02:36:04.534 [DEBUG] clck_gen.py:113 IND CLOCK 2958
2026-01-29 02:36:04.852 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:36:04.853 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:36:04.857 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 02:36:04.857 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 02:36:04.864 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 02:36:04.864 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:36:04.864 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:36:04.864 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:36:04.869 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 02:36:04.869 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:36:04.869 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:36:04.869 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.28.20:5700) Recv POWEROFF cmd
2026-01-29 02:36:04.869 [INFO] ctrl_if_trx.py:117 (BTS@172.18.28.20:5700) Stopping transceiver...
2026-01-29 02:36:04.869 [INFO] transceiver.py:246 Stopping clock generator
2026-01-29 02:36:04.869 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:36:04.869 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=3032 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:36:04.869 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=3032 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:36:04.870 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=3032 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:36:04.870 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=3032 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:36:04.870 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=3032 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:36:04.870 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=3032 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:36:04.870 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=3032 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:36:04.870 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=3032 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:36:09.869 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.28.20:5700) Recv POWEROFF cmd
2026-01-29 02:36:09.869 [INFO] ctrl_if_trx.py:117 (BTS@172.18.28.20:5700) Stopping transceiver...
2026-01-29 02:36:09.870 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:36:09.871 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:36:09.871 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:36:09.872 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 02:36:09.875 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 02:36:09.875 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.28.20:5700) Recv SETFORMAT cmd
2026-01-29 02:36:09.875 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.28.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:36:09.875 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.28.20:5700) Recv SETFORMAT cmd
2026-01-29 02:36:09.875 [INFO] ctrl_if_trx.py:201 (BTS@172.18.28.20:5700) TRXD header version 1 -> 1
2026-01-29 02:36:09.877 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.28.20:5700/1) Recv RXTUNE cmd
2026-01-29 02:36:09.877 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.28.20:5700/1) Recv TXTUNE cmd
2026-01-29 02:36:09.877 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.28.20:5700/1) Recv SETFORMAT cmd
2026-01-29 02:36:09.877 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.28.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:36:09.877 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:36:09.878 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.28.20:5700/1) Recv NOMTXPOWER cmd
2026-01-29 02:36:09.878 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.28.20:5700/1) Recv SETFORMAT cmd
2026-01-29 02:36:09.878 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.28.20:5700/1) TRXD header version 1 -> 1
2026-01-29 02:36:09.879 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.28.20:5700/2) Recv RXTUNE cmd
2026-01-29 02:36:09.879 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.28.20:5700/2) Recv TXTUNE cmd
2026-01-29 02:36:09.879 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.28.20:5700/2) Recv SETFORMAT cmd
2026-01-29 02:36:09.879 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.28.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:36:09.879 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:36:09.879 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.28.20:5700/2) Recv NOMTXPOWER cmd
2026-01-29 02:36:09.879 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.28.20:5700/2) Recv SETFORMAT cmd
2026-01-29 02:36:09.879 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.28.20:5700/2) TRXD header version 1 -> 1
2026-01-29 02:36:09.881 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.28.20:5700/3) Recv RXTUNE cmd
2026-01-29 02:36:09.881 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.28.20:5700/3) Recv TXTUNE cmd
2026-01-29 02:36:09.881 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.28.20:5700/3) Recv SETFORMAT cmd
2026-01-29 02:36:09.881 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.28.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:36:09.881 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:36:09.881 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.28.20:5700/3) Recv NOMTXPOWER cmd
2026-01-29 02:36:09.881 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.28.20:5700/3) Recv SETFORMAT cmd
2026-01-29 02:36:09.881 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.28.20:5700/3) TRXD header version 1 -> 1
2026-01-29 02:36:09.883 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.28.20:5700) Recv RXTUNE cmd
2026-01-29 02:36:09.883 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETTSC
2026-01-29 02:36:09.883 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETTSC
2026-01-29 02:36:09.883 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETTSC
2026-01-29 02:36:09.883 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.28.20:5700) Recv TXTUNE cmd
2026-01-29 02:36:09.883 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETRXGAIN
2026-01-29 02:36:09.883 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETRXGAIN
2026-01-29 02:36:09.883 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETRXGAIN
2026-01-29 02:36:09.883 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETTSC
2026-01-29 02:36:09.883 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:36:09.883 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:36:09.883 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:36:09.883 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.28.20:5700) Recv NOMTXPOWER cmd
2026-01-29 02:36:09.883 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:36:09.883 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:36:09.884 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:36:09.884 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.28.20:5700) Recv POWERON CMD
2026-01-29 02:36:09.884 [INFO] ctrl_if_trx.py:109 (BTS@172.18.28.20:5700) Starting transceiver...
2026-01-29 02:36:09.884 [INFO] transceiver.py:243 Starting clock generator
2026-01-29 02:36:09.884 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-01-29 02:36:09.884 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:36:09.884 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:36:09.884 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:36:09.884 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETRXGAIN
2026-01-29 02:36:09.884 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:36:09.884 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:36:09.884 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:36:09.884 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:36:09.884 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:36:09.884 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:36:09.884 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:36:09.884 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:36:09.884 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:36:09.884 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:36:09.884 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:36:09.884 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:36:09.884 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:36:09.884 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:36:09.884 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:36:09.884 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:36:09.884 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:36:09.884 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:36:09.884 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:36:09.884 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:36:09.884 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:36:09.885 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:36:09.885 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:36:09.888 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-01-29 02:36:10.372 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-01-29 02:36:10.409 [DEBUG] fake_trx.py:278 (BTS@172.18.28.20:5700) Recv FAKE_TOA cmd
2026-01-29 02:36:10.411 [DEBUG] fake_trx.py:297 (BTS@172.18.28.20:5700) Recv FAKE_RSSI cmd
2026-01-29 02:36:10.414 [DEBUG] fake_trx.py:322 (BTS@172.18.28.20:5700) Recv FAKE_CI cmd
2026-01-29 02:36:10.415 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:36:10.446 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:36:10.459 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:36:10.752 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:36:10.765 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:36:10.779 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:36:10.783 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:36:10.850 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-01-29 02:36:10.886 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:36:10.887 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 02:36:10.887 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:36:10.890 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:36:11.083 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:36:11.087 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:36:11.101 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:36:11.106 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:36:11.318 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-01-29 02:36:11.404 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:36:11.409 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:36:11.424 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:36:11.428 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:36:11.728 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:36:11.732 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:36:11.745 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 02:36:11.745 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:36:11.745 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:36:11.745 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:36:11.748 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 02:36:11.748 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:36:11.748 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:36:11.748 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.28.20:5700) Recv POWEROFF cmd
2026-01-29 02:36:11.748 [INFO] ctrl_if_trx.py:117 (BTS@172.18.28.20:5700) Stopping transceiver...
2026-01-29 02:36:11.748 [INFO] transceiver.py:246 Stopping clock generator
2026-01-29 02:36:11.748 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:36:11.748 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=400 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:36:11.748 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=400 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:36:11.748 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=400 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:36:11.749 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=400 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:36:11.749 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=401 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:36:11.749 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=401 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:36:11.749 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=401 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:36:11.749 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=401 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:36:11.749 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=401 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:36:11.749 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=401 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:36:11.749 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=401 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:36:11.749 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=401 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:36:16.749 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.28.20:5700) Recv POWEROFF cmd
2026-01-29 02:36:16.749 [INFO] ctrl_if_trx.py:117 (BTS@172.18.28.20:5700) Stopping transceiver...
2026-01-29 02:36:16.752 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:36:16.752 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:36:16.752 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:36:16.752 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 02:36:16.755 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 02:36:16.755 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.28.20:5700) Recv SETFORMAT cmd
2026-01-29 02:36:16.755 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.28.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:36:16.755 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.28.20:5700) Recv SETFORMAT cmd
2026-01-29 02:36:16.755 [INFO] ctrl_if_trx.py:201 (BTS@172.18.28.20:5700) TRXD header version 1 -> 1
2026-01-29 02:36:16.756 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.28.20:5700/1) Recv RXTUNE cmd
2026-01-29 02:36:16.756 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.28.20:5700/1) Recv TXTUNE cmd
2026-01-29 02:36:16.756 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.28.20:5700/1) Recv SETFORMAT cmd
2026-01-29 02:36:16.756 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.28.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:36:16.756 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:36:16.756 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.28.20:5700/1) Recv NOMTXPOWER cmd
2026-01-29 02:36:16.757 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.28.20:5700/1) Recv SETFORMAT cmd
2026-01-29 02:36:16.757 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.28.20:5700/1) TRXD header version 1 -> 1
2026-01-29 02:36:16.757 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.28.20:5700/2) Recv RXTUNE cmd
2026-01-29 02:36:16.757 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.28.20:5700/2) Recv TXTUNE cmd
2026-01-29 02:36:16.757 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.28.20:5700/2) Recv SETFORMAT cmd
2026-01-29 02:36:16.757 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.28.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:36:16.757 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:36:16.757 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.28.20:5700/2) Recv NOMTXPOWER cmd
2026-01-29 02:36:16.757 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.28.20:5700/2) Recv SETFORMAT cmd
2026-01-29 02:36:16.757 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.28.20:5700/2) TRXD header version 1 -> 1
2026-01-29 02:36:16.758 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.28.20:5700/3) Recv RXTUNE cmd
2026-01-29 02:36:16.758 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.28.20:5700/3) Recv TXTUNE cmd
2026-01-29 02:36:16.758 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.28.20:5700/3) Recv SETFORMAT cmd
2026-01-29 02:36:16.758 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.28.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:36:16.758 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:36:16.758 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.28.20:5700/3) Recv NOMTXPOWER cmd
2026-01-29 02:36:16.758 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.28.20:5700/3) Recv SETFORMAT cmd
2026-01-29 02:36:16.758 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.28.20:5700/3) TRXD header version 1 -> 1
2026-01-29 02:36:16.760 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.28.20:5700) Recv RXTUNE cmd
2026-01-29 02:36:16.760 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETTSC
2026-01-29 02:36:16.760 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETTSC
2026-01-29 02:36:16.760 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETTSC
2026-01-29 02:36:16.760 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.28.20:5700) Recv TXTUNE cmd
2026-01-29 02:36:16.760 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETRXGAIN
2026-01-29 02:36:16.760 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETRXGAIN
2026-01-29 02:36:16.760 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETRXGAIN
2026-01-29 02:36:16.760 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETTSC
2026-01-29 02:36:16.760 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:36:16.760 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:36:16.760 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:36:16.760 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.28.20:5700) Recv NOMTXPOWER cmd
2026-01-29 02:36:16.760 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:36:16.760 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:36:16.760 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:36:16.760 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.28.20:5700) Recv POWERON CMD
2026-01-29 02:36:16.760 [INFO] ctrl_if_trx.py:109 (BTS@172.18.28.20:5700) Starting transceiver...
2026-01-29 02:36:16.760 [INFO] transceiver.py:243 Starting clock generator
2026-01-29 02:36:16.760 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-01-29 02:36:16.760 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:36:16.760 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:36:16.760 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:36:16.760 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETRXGAIN
2026-01-29 02:36:16.760 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:36:16.760 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:36:16.760 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:36:16.760 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:36:16.760 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:36:16.760 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:36:16.760 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:36:16.761 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:36:16.761 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:36:16.761 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:36:16.761 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:36:16.761 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:36:16.761 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:36:16.761 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:36:16.761 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:36:16.761 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:36:16.761 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:36:16.761 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:36:16.761 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:36:16.761 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:36:16.761 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:36:16.761 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:36:16.761 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:36:16.765 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-01-29 02:36:17.249 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-01-29 02:36:17.285 [DEBUG] fake_trx.py:278 (BTS@172.18.28.20:5700) Recv FAKE_TOA cmd
2026-01-29 02:36:17.288 [DEBUG] fake_trx.py:297 (BTS@172.18.28.20:5700) Recv FAKE_RSSI cmd
2026-01-29 02:36:17.288 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:36:17.290 [DEBUG] fake_trx.py:322 (BTS@172.18.28.20:5700) Recv FAKE_CI cmd
2026-01-29 02:36:17.312 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:36:17.318 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:36:17.324 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:36:17.329 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:36:17.616 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:36:17.622 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:36:17.628 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:36:17.633 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:36:17.653 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:36:17.658 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:36:17.662 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:36:17.665 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:36:17.719 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-01-29 02:36:17.762 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 02:36:17.763 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:36:17.763 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:36:17.764 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:36:17.958 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:36:17.962 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:36:17.965 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:36:17.969 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:36:17.986 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:36:17.993 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:36:17.995 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:36:17.998 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:36:18.194 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-01-29 02:36:18.289 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:36:18.295 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:36:18.298 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:36:18.301 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:36:18.320 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:36:18.324 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:36:18.328 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:36:18.331 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:36:18.623 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:36:18.627 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:36:18.631 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:36:18.634 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:36:18.637 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 02:36:18.637 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:36:18.637 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:36:18.637 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:36:18.638 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 02:36:18.638 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:36:18.638 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:36:18.638 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:36:18.638 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.28.20:5700) Recv POWEROFF cmd
2026-01-29 02:36:18.638 [INFO] ctrl_if_trx.py:117 (BTS@172.18.28.20:5700) Stopping transceiver...
2026-01-29 02:36:18.638 [INFO] transceiver.py:246 Stopping clock generator
2026-01-29 02:36:18.638 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=404 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:36:18.638 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=404 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:36:18.638 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=404 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:36:18.638 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=404 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:36:18.638 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=404 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:36:18.638 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=404 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:36:18.638 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=404 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:36:23.641 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.28.20:5700) Recv POWEROFF cmd
2026-01-29 02:36:23.641 [INFO] ctrl_if_trx.py:117 (BTS@172.18.28.20:5700) Stopping transceiver...
2026-01-29 02:36:23.643 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:36:23.643 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:36:23.644 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:36:23.644 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 02:36:23.647 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 02:36:23.648 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.28.20:5700) Recv SETFORMAT cmd
2026-01-29 02:36:23.648 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.28.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:36:23.648 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.28.20:5700) Recv SETFORMAT cmd
2026-01-29 02:36:23.648 [INFO] ctrl_if_trx.py:201 (BTS@172.18.28.20:5700) TRXD header version 1 -> 1
2026-01-29 02:36:23.651 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.28.20:5700/1) Recv RXTUNE cmd
2026-01-29 02:36:23.651 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.28.20:5700/1) Recv TXTUNE cmd
2026-01-29 02:36:23.651 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.28.20:5700/1) Recv SETFORMAT cmd
2026-01-29 02:36:23.651 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.28.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:36:23.651 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:36:23.651 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.28.20:5700/1) Recv NOMTXPOWER cmd
2026-01-29 02:36:23.651 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.28.20:5700/1) Recv SETFORMAT cmd
2026-01-29 02:36:23.651 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.28.20:5700/1) TRXD header version 1 -> 1
2026-01-29 02:36:23.653 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.28.20:5700/2) Recv RXTUNE cmd
2026-01-29 02:36:23.653 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.28.20:5700/2) Recv TXTUNE cmd
2026-01-29 02:36:23.653 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.28.20:5700/2) Recv SETFORMAT cmd
2026-01-29 02:36:23.653 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.28.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:36:23.653 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:36:23.653 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.28.20:5700/2) Recv NOMTXPOWER cmd
2026-01-29 02:36:23.653 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.28.20:5700/2) Recv SETFORMAT cmd
2026-01-29 02:36:23.653 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.28.20:5700/2) TRXD header version 1 -> 1
2026-01-29 02:36:23.655 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.28.20:5700/3) Recv RXTUNE cmd
2026-01-29 02:36:23.655 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.28.20:5700/3) Recv TXTUNE cmd
2026-01-29 02:36:23.655 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.28.20:5700/3) Recv SETFORMAT cmd
2026-01-29 02:36:23.655 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.28.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:36:23.655 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:36:23.655 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.28.20:5700/3) Recv NOMTXPOWER cmd
2026-01-29 02:36:23.655 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.28.20:5700/3) Recv SETFORMAT cmd
2026-01-29 02:36:23.655 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.28.20:5700/3) TRXD header version 1 -> 1
2026-01-29 02:36:23.657 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.28.20:5700) Recv RXTUNE cmd
2026-01-29 02:36:23.657 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETTSC
2026-01-29 02:36:23.657 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETTSC
2026-01-29 02:36:23.657 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETTSC
2026-01-29 02:36:23.657 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.28.20:5700) Recv TXTUNE cmd
2026-01-29 02:36:23.657 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETRXGAIN
2026-01-29 02:36:23.657 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETRXGAIN
2026-01-29 02:36:23.657 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETRXGAIN
2026-01-29 02:36:23.657 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETTSC
2026-01-29 02:36:23.657 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:36:23.657 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:36:23.657 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:36:23.657 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.28.20:5700) Recv NOMTXPOWER cmd
2026-01-29 02:36:23.657 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:36:23.657 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:36:23.657 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:36:23.657 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.28.20:5700) Recv POWERON CMD
2026-01-29 02:36:23.657 [INFO] ctrl_if_trx.py:109 (BTS@172.18.28.20:5700) Starting transceiver...
2026-01-29 02:36:23.657 [INFO] transceiver.py:243 Starting clock generator
2026-01-29 02:36:23.657 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-01-29 02:36:23.657 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:36:23.657 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:36:23.657 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:36:23.658 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETRXGAIN
2026-01-29 02:36:23.658 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:36:23.658 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:36:23.658 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:36:23.658 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:36:23.658 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:36:23.658 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:36:23.658 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:36:23.658 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:36:23.658 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:36:23.658 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:36:23.658 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:36:23.658 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:36:23.658 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:36:23.658 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:36:23.658 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:36:23.658 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:36:23.658 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:36:23.658 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:36:23.658 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:36:23.658 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:36:23.658 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:36:23.658 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:36:23.658 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:36:23.662 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-01-29 02:36:24.146 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-01-29 02:36:24.180 [DEBUG] fake_trx.py:278 (BTS@172.18.28.20:5700) Recv FAKE_TOA cmd
2026-01-29 02:36:24.182 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:36:24.183 [DEBUG] fake_trx.py:297 (BTS@172.18.28.20:5700) Recv FAKE_RSSI cmd
2026-01-29 02:36:24.185 [DEBUG] fake_trx.py:322 (BTS@172.18.28.20:5700) Recv FAKE_CI cmd
2026-01-29 02:36:24.215 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:36:24.229 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:36:24.243 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:36:24.547 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:36:24.548 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:36:24.549 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:36:24.565 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:36:24.570 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:36:24.574 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:36:24.624 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-01-29 02:36:24.660 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:36:24.661 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 02:36:24.661 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:36:24.663 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:36:24.868 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:36:24.873 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:36:24.877 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:36:24.885 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:36:24.889 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:36:24.894 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:36:25.102 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-01-29 02:36:25.189 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:36:25.193 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:36:25.197 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:36:25.209 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:36:25.214 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:36:25.218 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:36:25.513 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:36:25.518 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:36:25.521 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:36:25.526 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 02:36:25.527 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:36:25.527 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:36:25.527 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:36:25.528 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 02:36:25.528 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:36:25.528 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:36:25.528 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.28.20:5700) Recv POWEROFF cmd
2026-01-29 02:36:25.528 [INFO] ctrl_if_trx.py:117 (BTS@172.18.28.20:5700) Stopping transceiver...
2026-01-29 02:36:25.528 [INFO] transceiver.py:246 Stopping clock generator
2026-01-29 02:36:25.528 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:36:25.528 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=400 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:36:25.528 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=400 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:36:25.528 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=400 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:36:25.528 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=400 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:36:25.528 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=400 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:36:25.528 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=400 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:36:25.528 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=400 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:36:25.528 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=400 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:36:30.534 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.28.20:5700) Recv POWEROFF cmd
2026-01-29 02:36:30.534 [INFO] ctrl_if_trx.py:117 (BTS@172.18.28.20:5700) Stopping transceiver...
2026-01-29 02:36:30.534 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:36:30.534 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 02:36:30.534 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:36:30.534 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:36:30.541 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 02:36:30.541 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.28.20:5700) Recv SETFORMAT cmd
2026-01-29 02:36:30.541 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.28.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:36:30.542 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.28.20:5700) Recv SETFORMAT cmd
2026-01-29 02:36:30.542 [INFO] ctrl_if_trx.py:201 (BTS@172.18.28.20:5700) TRXD header version 1 -> 1
2026-01-29 02:36:30.545 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.28.20:5700/1) Recv RXTUNE cmd
2026-01-29 02:36:30.545 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.28.20:5700/1) Recv TXTUNE cmd
2026-01-29 02:36:30.545 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.28.20:5700/1) Recv SETFORMAT cmd
2026-01-29 02:36:30.545 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.28.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:36:30.546 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:36:30.546 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.28.20:5700/1) Recv NOMTXPOWER cmd
2026-01-29 02:36:30.546 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.28.20:5700/1) Recv SETFORMAT cmd
2026-01-29 02:36:30.546 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.28.20:5700/1) TRXD header version 1 -> 1
2026-01-29 02:36:30.548 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.28.20:5700/2) Recv RXTUNE cmd
2026-01-29 02:36:30.549 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.28.20:5700/2) Recv TXTUNE cmd
2026-01-29 02:36:30.549 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.28.20:5700/2) Recv SETFORMAT cmd
2026-01-29 02:36:30.549 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.28.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:36:30.550 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:36:30.550 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.28.20:5700/2) Recv NOMTXPOWER cmd
2026-01-29 02:36:30.551 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.28.20:5700/2) Recv SETFORMAT cmd
2026-01-29 02:36:30.551 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.28.20:5700/2) TRXD header version 1 -> 1
2026-01-29 02:36:30.551 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.28.20:5700/3) Recv RXTUNE cmd
2026-01-29 02:36:30.551 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.28.20:5700/3) Recv TXTUNE cmd
2026-01-29 02:36:30.552 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.28.20:5700/3) Recv SETFORMAT cmd
2026-01-29 02:36:30.552 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.28.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:36:30.552 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:36:30.552 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.28.20:5700/3) Recv NOMTXPOWER cmd
2026-01-29 02:36:30.552 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.28.20:5700/3) Recv SETFORMAT cmd
2026-01-29 02:36:30.552 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.28.20:5700/3) TRXD header version 1 -> 1
2026-01-29 02:36:30.555 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.28.20:5700) Recv RXTUNE cmd
2026-01-29 02:36:30.555 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETTSC
2026-01-29 02:36:30.555 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETTSC
2026-01-29 02:36:30.555 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETTSC
2026-01-29 02:36:30.555 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.28.20:5700) Recv TXTUNE cmd
2026-01-29 02:36:30.555 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETRXGAIN
2026-01-29 02:36:30.555 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETRXGAIN
2026-01-29 02:36:30.555 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETRXGAIN
2026-01-29 02:36:30.555 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETTSC
2026-01-29 02:36:30.555 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:36:30.555 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:36:30.555 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.28.20:5700) Recv NOMTXPOWER cmd
2026-01-29 02:36:30.555 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:36:30.555 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:36:30.555 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:36:30.555 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.28.20:5700) Recv POWERON CMD
2026-01-29 02:36:30.555 [INFO] ctrl_if_trx.py:109 (BTS@172.18.28.20:5700) Starting transceiver...
2026-01-29 02:36:30.555 [INFO] transceiver.py:243 Starting clock generator
2026-01-29 02:36:30.556 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-01-29 02:36:30.556 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:36:30.556 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:36:30.556 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:36:30.556 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETRXGAIN
2026-01-29 02:36:30.556 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:36:30.556 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:36:30.556 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:36:30.556 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:36:30.556 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:36:30.556 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:36:30.556 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:36:30.556 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:36:30.556 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:36:30.556 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:36:30.556 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:36:30.557 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:36:30.557 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:36:30.557 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:36:30.557 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:36:30.557 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:36:30.557 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:36:30.557 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:36:30.557 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:36:30.557 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:36:30.557 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:36:30.557 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:36:30.557 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:36:30.557 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:36:30.560 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-01-29 02:36:31.043 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-01-29 02:36:31.086 [DEBUG] fake_trx.py:278 (BTS@172.18.28.20:5700) Recv FAKE_TOA cmd
2026-01-29 02:36:31.088 [DEBUG] fake_trx.py:297 (BTS@172.18.28.20:5700) Recv FAKE_RSSI cmd
2026-01-29 02:36:31.088 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:36:31.088 [DEBUG] fake_trx.py:322 (BTS@172.18.28.20:5700) Recv FAKE_CI cmd
2026-01-29 02:36:31.116 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:36:31.129 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:36:31.422 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:36:31.433 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:36:31.449 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:36:31.453 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:36:31.520 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-01-29 02:36:31.559 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:36:31.560 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 02:36:31.560 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:36:31.561 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:36:31.753 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:36:31.757 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:36:31.780 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:36:31.785 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:36:31.996 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-01-29 02:36:32.083 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:36:32.088 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:36:32.109 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:36:32.113 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:36:32.413 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:36:32.416 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:36:32.428 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 02:36:32.428 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:36:32.428 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:36:32.429 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:36:32.432 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 02:36:32.432 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:36:32.432 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:36:32.432 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.28.20:5700) Recv POWEROFF cmd
2026-01-29 02:36:32.432 [INFO] ctrl_if_trx.py:117 (BTS@172.18.28.20:5700) Stopping transceiver...
2026-01-29 02:36:32.432 [INFO] transceiver.py:246 Stopping clock generator
2026-01-29 02:36:32.433 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:36:32.433 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=401 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:36:32.433 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=401 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:36:32.433 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=401 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:36:32.433 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=401 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:36:32.433 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=401 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:36:32.434 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=401 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:36:32.434 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=401 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:36:32.434 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=402 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:36:32.434 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=402 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:36:32.434 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=402 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:36:32.434 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=402 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:36:32.434 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=402 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:36:32.434 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=402 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:36:32.434 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=402 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:36:32.434 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=402 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:36:37.432 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.28.20:5700) Recv POWEROFF cmd
2026-01-29 02:36:37.432 [INFO] ctrl_if_trx.py:117 (BTS@172.18.28.20:5700) Stopping transceiver...
2026-01-29 02:36:37.434 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:36:37.436 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:36:37.436 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:36:37.437 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 02:36:37.440 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 02:36:37.440 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.28.20:5700) Recv SETFORMAT cmd
2026-01-29 02:36:37.440 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.28.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:36:37.440 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.28.20:5700) Recv SETFORMAT cmd
2026-01-29 02:36:37.440 [INFO] ctrl_if_trx.py:201 (BTS@172.18.28.20:5700) TRXD header version 1 -> 1
2026-01-29 02:36:37.442 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.28.20:5700/1) Recv RXTUNE cmd
2026-01-29 02:36:37.442 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.28.20:5700/1) Recv TXTUNE cmd
2026-01-29 02:36:37.442 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.28.20:5700/1) Recv SETFORMAT cmd
2026-01-29 02:36:37.442 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.28.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:36:37.442 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:36:37.442 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.28.20:5700/1) Recv NOMTXPOWER cmd
2026-01-29 02:36:37.443 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.28.20:5700/1) Recv SETFORMAT cmd
2026-01-29 02:36:37.443 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.28.20:5700/1) TRXD header version 1 -> 1
2026-01-29 02:36:37.444 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.28.20:5700/2) Recv RXTUNE cmd
2026-01-29 02:36:37.444 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.28.20:5700/2) Recv TXTUNE cmd
2026-01-29 02:36:37.444 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.28.20:5700/2) Recv SETFORMAT cmd
2026-01-29 02:36:37.444 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.28.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:36:37.444 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:36:37.444 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.28.20:5700/2) Recv NOMTXPOWER cmd
2026-01-29 02:36:37.445 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.28.20:5700/2) Recv SETFORMAT cmd
2026-01-29 02:36:37.445 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.28.20:5700/2) TRXD header version 1 -> 1
2026-01-29 02:36:37.446 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.28.20:5700/3) Recv RXTUNE cmd
2026-01-29 02:36:37.446 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.28.20:5700/3) Recv TXTUNE cmd
2026-01-29 02:36:37.446 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.28.20:5700/3) Recv SETFORMAT cmd
2026-01-29 02:36:37.446 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.28.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:36:37.446 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:36:37.446 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.28.20:5700/3) Recv NOMTXPOWER cmd
2026-01-29 02:36:37.446 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.28.20:5700/3) Recv SETFORMAT cmd
2026-01-29 02:36:37.446 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.28.20:5700/3) TRXD header version 1 -> 1
2026-01-29 02:36:37.448 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.28.20:5700) Recv RXTUNE cmd
2026-01-29 02:36:37.448 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETTSC
2026-01-29 02:36:37.448 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETTSC
2026-01-29 02:36:37.448 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETTSC
2026-01-29 02:36:37.448 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.28.20:5700) Recv TXTUNE cmd
2026-01-29 02:36:37.448 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETRXGAIN
2026-01-29 02:36:37.448 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETRXGAIN
2026-01-29 02:36:37.448 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETRXGAIN
2026-01-29 02:36:37.448 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETTSC
2026-01-29 02:36:37.448 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:36:37.448 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:36:37.448 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:36:37.448 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.28.20:5700) Recv NOMTXPOWER cmd
2026-01-29 02:36:37.448 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:36:37.448 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:36:37.448 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:36:37.448 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.28.20:5700) Recv POWERON CMD
2026-01-29 02:36:37.448 [INFO] ctrl_if_trx.py:109 (BTS@172.18.28.20:5700) Starting transceiver...
2026-01-29 02:36:37.448 [INFO] transceiver.py:243 Starting clock generator
2026-01-29 02:36:37.449 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-01-29 02:36:37.449 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:36:37.449 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:36:37.449 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:36:37.449 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETRXGAIN
2026-01-29 02:36:37.449 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:36:37.449 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:36:37.449 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:36:37.449 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:36:37.449 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:36:37.449 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:36:37.449 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:36:37.449 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:36:37.449 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:36:37.449 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:36:37.449 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:36:37.449 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:36:37.449 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:36:37.449 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:36:37.449 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:36:37.449 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:36:37.449 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:36:37.449 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:36:37.449 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:36:37.449 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:36:37.449 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:36:37.449 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:36:37.449 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:36:37.453 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-01-29 02:36:37.937 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-01-29 02:36:37.964 [DEBUG] fake_trx.py:278 (BTS@172.18.28.20:5700) Recv FAKE_TOA cmd
2026-01-29 02:36:37.965 [DEBUG] fake_trx.py:297 (BTS@172.18.28.20:5700) Recv FAKE_RSSI cmd
2026-01-29 02:36:37.965 [DEBUG] fake_trx.py:322 (BTS@172.18.28.20:5700) Recv FAKE_CI cmd
2026-01-29 02:36:37.965 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:36:37.974 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:36:37.974 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:36:37.977 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:36:38.277 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:36:38.280 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:36:38.297 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:36:38.302 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:36:38.406 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-01-29 02:36:38.451 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:36:38.451 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 02:36:38.451 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:36:38.454 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:36:38.599 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:36:38.605 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:36:38.617 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:36:38.623 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:36:38.875 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-01-29 02:36:38.920 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:36:38.926 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:36:38.938 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:36:38.943 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:36:39.241 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:36:39.246 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:36:39.260 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 02:36:39.260 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:36:39.260 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:36:39.260 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:36:39.261 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 02:36:39.261 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:36:39.261 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:36:39.261 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.28.20:5700) Recv POWEROFF cmd
2026-01-29 02:36:39.261 [INFO] ctrl_if_trx.py:117 (BTS@172.18.28.20:5700) Stopping transceiver...
2026-01-29 02:36:39.261 [INFO] transceiver.py:246 Stopping clock generator
2026-01-29 02:36:39.261 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:36:39.261 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=391 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:36:39.261 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=391 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:36:39.261 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=391 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:36:39.261 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=391 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:36:39.262 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=391 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:36:39.262 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=391 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:36:39.262 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=391 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:36:39.262 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=391 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:36:44.264 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.28.20:5700) Recv POWEROFF cmd
2026-01-29 02:36:44.264 [INFO] ctrl_if_trx.py:117 (BTS@172.18.28.20:5700) Stopping transceiver...
2026-01-29 02:36:44.265 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:36:44.267 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:36:44.268 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:36:44.268 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 02:36:44.275 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 02:36:44.275 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.28.20:5700) Recv SETFORMAT cmd
2026-01-29 02:36:44.275 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.28.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:36:44.275 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.28.20:5700) Recv SETFORMAT cmd
2026-01-29 02:36:44.275 [INFO] ctrl_if_trx.py:201 (BTS@172.18.28.20:5700) TRXD header version 1 -> 1
2026-01-29 02:36:44.278 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.28.20:5700/1) Recv RXTUNE cmd
2026-01-29 02:36:44.278 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.28.20:5700/1) Recv TXTUNE cmd
2026-01-29 02:36:44.278 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.28.20:5700/1) Recv SETFORMAT cmd
2026-01-29 02:36:44.278 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.28.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:36:44.279 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:36:44.279 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.28.20:5700/1) Recv NOMTXPOWER cmd
2026-01-29 02:36:44.279 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.28.20:5700/1) Recv SETFORMAT cmd
2026-01-29 02:36:44.279 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.28.20:5700/1) TRXD header version 1 -> 1
2026-01-29 02:36:44.281 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.28.20:5700/2) Recv RXTUNE cmd
2026-01-29 02:36:44.281 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.28.20:5700/2) Recv TXTUNE cmd
2026-01-29 02:36:44.281 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.28.20:5700/2) Recv SETFORMAT cmd
2026-01-29 02:36:44.281 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.28.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:36:44.281 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:36:44.282 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.28.20:5700/2) Recv NOMTXPOWER cmd
2026-01-29 02:36:44.282 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.28.20:5700/2) Recv SETFORMAT cmd
2026-01-29 02:36:44.282 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.28.20:5700/2) TRXD header version 1 -> 1
2026-01-29 02:36:44.284 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.28.20:5700/3) Recv RXTUNE cmd
2026-01-29 02:36:44.284 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.28.20:5700/3) Recv TXTUNE cmd
2026-01-29 02:36:44.284 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.28.20:5700/3) Recv SETFORMAT cmd
2026-01-29 02:36:44.284 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.28.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:36:44.284 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:36:44.284 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.28.20:5700/3) Recv NOMTXPOWER cmd
2026-01-29 02:36:44.284 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.28.20:5700/3) Recv SETFORMAT cmd
2026-01-29 02:36:44.284 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.28.20:5700/3) TRXD header version 1 -> 1
2026-01-29 02:36:44.287 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.28.20:5700) Recv RXTUNE cmd
2026-01-29 02:36:44.287 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETTSC
2026-01-29 02:36:44.287 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETTSC
2026-01-29 02:36:44.287 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETTSC
2026-01-29 02:36:44.287 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.28.20:5700) Recv TXTUNE cmd
2026-01-29 02:36:44.287 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETRXGAIN
2026-01-29 02:36:44.287 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETRXGAIN
2026-01-29 02:36:44.287 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETRXGAIN
2026-01-29 02:36:44.287 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETTSC
2026-01-29 02:36:44.287 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:36:44.287 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:36:44.287 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:36:44.287 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.28.20:5700) Recv NOMTXPOWER cmd
2026-01-29 02:36:44.287 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:36:44.287 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:36:44.287 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:36:44.287 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.28.20:5700) Recv POWERON CMD
2026-01-29 02:36:44.287 [INFO] ctrl_if_trx.py:109 (BTS@172.18.28.20:5700) Starting transceiver...
2026-01-29 02:36:44.288 [INFO] transceiver.py:243 Starting clock generator
2026-01-29 02:36:44.288 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-01-29 02:36:44.288 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:36:44.288 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:36:44.288 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:36:44.288 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETRXGAIN
2026-01-29 02:36:44.288 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:36:44.288 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:36:44.288 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:36:44.288 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:36:44.288 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:36:44.288 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:36:44.288 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:36:44.288 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:36:44.288 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:36:44.288 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:36:44.289 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:36:44.289 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:36:44.289 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:36:44.289 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:36:44.289 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:36:44.289 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:36:44.289 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:36:44.289 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:36:44.289 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:36:44.289 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:36:44.289 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:36:44.289 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:36:44.289 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:36:44.292 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-01-29 02:36:44.775 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-01-29 02:36:44.814 [DEBUG] fake_trx.py:278 (BTS@172.18.28.20:5700) Recv FAKE_TOA cmd
2026-01-29 02:36:44.816 [DEBUG] fake_trx.py:297 (BTS@172.18.28.20:5700) Recv FAKE_RSSI cmd
2026-01-29 02:36:44.816 [DEBUG] fake_trx.py:322 (BTS@172.18.28.20:5700) Recv FAKE_CI cmd
2026-01-29 02:36:44.817 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:36:44.837 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:36:44.838 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:36:44.847 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:36:44.858 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:36:44.867 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:36:45.143 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:36:45.150 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:36:45.161 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:36:45.168 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:36:45.177 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:36:45.180 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:36:45.185 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:36:45.190 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:36:45.244 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-01-29 02:36:45.292 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:36:45.292 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 02:36:45.292 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:36:45.293 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:36:45.480 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:36:45.483 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:36:45.488 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:36:45.493 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:36:45.508 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:36:45.514 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:36:45.518 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:36:45.523 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:36:45.718 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-01-29 02:36:45.812 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:36:45.818 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:36:45.821 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:36:45.826 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:36:45.842 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:36:45.847 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:36:45.851 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:36:45.855 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:36:46.146 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:36:46.150 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:36:46.154 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:36:46.158 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:36:46.162 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 02:36:46.162 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:36:46.162 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:36:46.162 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:36:46.163 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 02:36:46.163 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:36:46.163 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:36:46.163 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.28.20:5700) Recv POWEROFF cmd
2026-01-29 02:36:46.163 [INFO] ctrl_if_trx.py:117 (BTS@172.18.28.20:5700) Stopping transceiver...
2026-01-29 02:36:46.163 [INFO] transceiver.py:246 Stopping clock generator
2026-01-29 02:36:46.164 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:36:46.164 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=404 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:36:46.164 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=404 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:36:46.164 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=404 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:36:46.164 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=404 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:36:51.165 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.28.20:5700) Recv POWEROFF cmd
2026-01-29 02:36:51.166 [INFO] ctrl_if_trx.py:117 (BTS@172.18.28.20:5700) Stopping transceiver...
2026-01-29 02:36:51.167 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:36:51.168 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:36:51.169 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:36:51.169 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 02:36:51.173 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 02:36:51.174 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.28.20:5700) Recv SETFORMAT cmd
2026-01-29 02:36:51.174 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.28.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:36:51.174 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.28.20:5700) Recv SETFORMAT cmd
2026-01-29 02:36:51.174 [INFO] ctrl_if_trx.py:201 (BTS@172.18.28.20:5700) TRXD header version 1 -> 1
2026-01-29 02:36:51.178 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.28.20:5700/1) Recv RXTUNE cmd
2026-01-29 02:36:51.178 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.28.20:5700/1) Recv TXTUNE cmd
2026-01-29 02:36:51.178 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.28.20:5700/1) Recv SETFORMAT cmd
2026-01-29 02:36:51.178 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.28.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:36:51.178 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:36:51.178 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.28.20:5700/1) Recv NOMTXPOWER cmd
2026-01-29 02:36:51.178 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.28.20:5700/1) Recv SETFORMAT cmd
2026-01-29 02:36:51.178 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.28.20:5700/1) TRXD header version 1 -> 1
2026-01-29 02:36:51.181 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.28.20:5700/2) Recv RXTUNE cmd
2026-01-29 02:36:51.181 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.28.20:5700/2) Recv TXTUNE cmd
2026-01-29 02:36:51.181 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.28.20:5700/2) Recv SETFORMAT cmd
2026-01-29 02:36:51.181 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.28.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:36:51.181 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:36:51.181 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.28.20:5700/2) Recv NOMTXPOWER cmd
2026-01-29 02:36:51.181 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.28.20:5700/2) Recv SETFORMAT cmd
2026-01-29 02:36:51.181 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.28.20:5700/2) TRXD header version 1 -> 1
2026-01-29 02:36:51.183 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.28.20:5700/3) Recv RXTUNE cmd
2026-01-29 02:36:51.183 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.28.20:5700/3) Recv TXTUNE cmd
2026-01-29 02:36:51.184 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.28.20:5700/3) Recv SETFORMAT cmd
2026-01-29 02:36:51.184 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.28.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:36:51.184 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:36:51.184 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.28.20:5700/3) Recv NOMTXPOWER cmd
2026-01-29 02:36:51.184 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.28.20:5700/3) Recv SETFORMAT cmd
2026-01-29 02:36:51.184 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.28.20:5700/3) TRXD header version 1 -> 1
2026-01-29 02:36:51.187 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.28.20:5700) Recv RXTUNE cmd
2026-01-29 02:36:51.187 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETTSC
2026-01-29 02:36:51.187 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETTSC
2026-01-29 02:36:51.187 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETTSC
2026-01-29 02:36:51.187 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.28.20:5700) Recv TXTUNE cmd
2026-01-29 02:36:51.187 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETRXGAIN
2026-01-29 02:36:51.187 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETRXGAIN
2026-01-29 02:36:51.187 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETRXGAIN
2026-01-29 02:36:51.187 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETTSC
2026-01-29 02:36:51.187 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:36:51.187 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:36:51.187 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.28.20:5700) Recv NOMTXPOWER cmd
2026-01-29 02:36:51.187 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:36:51.187 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:36:51.187 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:36:51.187 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.28.20:5700) Recv POWERON CMD
2026-01-29 02:36:51.187 [INFO] ctrl_if_trx.py:109 (BTS@172.18.28.20:5700) Starting transceiver...
2026-01-29 02:36:51.187 [INFO] transceiver.py:243 Starting clock generator
2026-01-29 02:36:51.187 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-01-29 02:36:51.188 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:36:51.188 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:36:51.188 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:36:51.188 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETRXGAIN
2026-01-29 02:36:51.188 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:36:51.188 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:36:51.188 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:36:51.188 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:36:51.188 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:36:51.188 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:36:51.188 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:36:51.188 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:36:51.188 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:36:51.188 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:36:51.188 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:36:51.188 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:36:51.188 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:36:51.188 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:36:51.188 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:36:51.188 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:36:51.188 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:36:51.188 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:36:51.188 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:36:51.188 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:36:51.188 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:36:51.189 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:36:51.189 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:36:51.189 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:36:51.192 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-01-29 02:36:51.676 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-01-29 02:36:51.714 [DEBUG] fake_trx.py:278 (BTS@172.18.28.20:5700) Recv FAKE_TOA cmd
2026-01-29 02:36:51.715 [DEBUG] fake_trx.py:297 (BTS@172.18.28.20:5700) Recv FAKE_RSSI cmd
2026-01-29 02:36:51.717 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:36:51.717 [DEBUG] fake_trx.py:322 (BTS@172.18.28.20:5700) Recv FAKE_CI cmd
2026-01-29 02:36:51.734 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:36:51.735 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:36:51.741 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:36:51.750 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:36:52.040 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:36:52.045 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:36:52.052 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:36:52.060 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:36:52.064 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:36:52.068 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:36:52.152 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-01-29 02:36:52.191 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:36:52.191 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 02:36:52.191 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:36:52.194 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:36:52.363 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:36:52.367 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:36:52.371 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:36:52.387 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:36:52.392 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:36:52.395 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:36:52.625 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-01-29 02:36:52.691 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:36:52.695 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:36:52.699 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:36:52.710 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:36:52.715 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:36:52.720 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:36:53.014 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:36:53.019 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:36:53.023 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:36:53.036 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 02:36:53.036 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:36:53.036 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:36:53.036 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:36:53.037 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 02:36:53.037 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:36:53.037 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:36:53.037 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.28.20:5700) Recv POWEROFF cmd
2026-01-29 02:36:53.037 [INFO] ctrl_if_trx.py:117 (BTS@172.18.28.20:5700) Stopping transceiver...
2026-01-29 02:36:53.037 [INFO] transceiver.py:246 Stopping clock generator
2026-01-29 02:36:53.037 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:36:58.039 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.28.20:5700) Recv POWEROFF cmd
2026-01-29 02:36:58.039 [INFO] ctrl_if_trx.py:117 (BTS@172.18.28.20:5700) Stopping transceiver...
2026-01-29 02:36:58.041 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:36:58.042 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:36:58.042 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:36:58.042 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 02:36:58.049 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 02:36:58.050 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.28.20:5700) Recv SETFORMAT cmd
2026-01-29 02:36:58.050 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.28.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:36:58.051 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.28.20:5700) Recv SETFORMAT cmd
2026-01-29 02:36:58.051 [INFO] ctrl_if_trx.py:201 (BTS@172.18.28.20:5700) TRXD header version 1 -> 1
2026-01-29 02:36:58.053 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.28.20:5700/1) Recv RXTUNE cmd
2026-01-29 02:36:58.053 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.28.20:5700/1) Recv TXTUNE cmd
2026-01-29 02:36:58.054 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.28.20:5700/1) Recv SETFORMAT cmd
2026-01-29 02:36:58.054 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.28.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:36:58.054 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:36:58.055 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.28.20:5700/1) Recv NOMTXPOWER cmd
2026-01-29 02:36:58.055 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.28.20:5700/1) Recv SETFORMAT cmd
2026-01-29 02:36:58.055 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.28.20:5700/1) TRXD header version 1 -> 1
2026-01-29 02:36:58.056 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.28.20:5700/2) Recv RXTUNE cmd
2026-01-29 02:36:58.056 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.28.20:5700/2) Recv TXTUNE cmd
2026-01-29 02:36:58.057 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.28.20:5700/2) Recv SETFORMAT cmd
2026-01-29 02:36:58.057 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.28.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:36:58.057 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:36:58.057 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.28.20:5700/2) Recv NOMTXPOWER cmd
2026-01-29 02:36:58.057 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.28.20:5700/2) Recv SETFORMAT cmd
2026-01-29 02:36:58.057 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.28.20:5700/2) TRXD header version 1 -> 1
2026-01-29 02:36:58.058 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.28.20:5700/3) Recv RXTUNE cmd
2026-01-29 02:36:58.058 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.28.20:5700/3) Recv TXTUNE cmd
2026-01-29 02:36:58.058 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.28.20:5700/3) Recv SETFORMAT cmd
2026-01-29 02:36:58.058 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.28.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:36:58.058 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:36:58.059 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.28.20:5700/3) Recv NOMTXPOWER cmd
2026-01-29 02:36:58.059 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.28.20:5700/3) Recv SETFORMAT cmd
2026-01-29 02:36:58.059 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.28.20:5700/3) TRXD header version 1 -> 1
2026-01-29 02:36:58.061 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.28.20:5700) Recv RXTUNE cmd
2026-01-29 02:36:58.061 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETTSC
2026-01-29 02:36:58.061 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETTSC
2026-01-29 02:36:58.061 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETTSC
2026-01-29 02:36:58.061 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.28.20:5700) Recv TXTUNE cmd
2026-01-29 02:36:58.061 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETRXGAIN
2026-01-29 02:36:58.061 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETRXGAIN
2026-01-29 02:36:58.061 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETRXGAIN
2026-01-29 02:36:58.061 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETTSC
2026-01-29 02:36:58.061 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:36:58.062 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:36:58.062 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.28.20:5700) Recv NOMTXPOWER cmd
2026-01-29 02:36:58.062 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:36:58.062 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:36:58.062 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:36:58.062 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.28.20:5700) Recv POWERON CMD
2026-01-29 02:36:58.062 [INFO] ctrl_if_trx.py:109 (BTS@172.18.28.20:5700) Starting transceiver...
2026-01-29 02:36:58.062 [INFO] transceiver.py:243 Starting clock generator
2026-01-29 02:36:58.062 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-01-29 02:36:58.062 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:36:58.062 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:36:58.062 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:36:58.062 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETRXGAIN
2026-01-29 02:36:58.062 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:36:58.062 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:36:58.062 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:36:58.062 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:36:58.062 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:36:58.062 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:36:58.062 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:36:58.062 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:36:58.062 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:36:58.062 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:36:58.062 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:36:58.063 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:36:58.063 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:36:58.063 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:36:58.063 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:36:58.063 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:36:58.063 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:36:58.063 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:36:58.063 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:36:58.063 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:36:58.063 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:36:58.063 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:36:58.063 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:36:58.063 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:36:58.067 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-01-29 02:36:58.551 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-01-29 02:36:58.591 [DEBUG] fake_trx.py:278 (BTS@172.18.28.20:5700) Recv FAKE_TOA cmd
2026-01-29 02:36:58.593 [DEBUG] fake_trx.py:297 (BTS@172.18.28.20:5700) Recv FAKE_RSSI cmd
2026-01-29 02:36:58.595 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:36:58.595 [DEBUG] fake_trx.py:322 (BTS@172.18.28.20:5700) Recv FAKE_CI cmd
2026-01-29 02:36:58.625 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:36:58.631 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:36:58.635 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:36:58.638 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:36:58.641 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:36:58.643 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:36:58.655 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:36:58.656 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:36:58.656 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:36:58.660 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:36:58.661 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:36:58.661 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:36:58.669 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:36:58.669 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:36:58.670 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:36:58.675 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:36:58.676 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:36:58.676 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:36:58.684 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:36:58.685 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:36:58.685 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:36:58.687 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:36:58.688 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:36:58.689 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:36:58.692 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 02:36:58.692 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:36:58.692 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:36:58.692 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:36:58.695 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 02:36:58.695 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:36:58.695 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:36:58.695 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:36:58.695 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.28.20:5700) Recv POWEROFF cmd
2026-01-29 02:36:58.695 [INFO] ctrl_if_trx.py:117 (BTS@172.18.28.20:5700) Stopping transceiver...
2026-01-29 02:36:58.695 [INFO] transceiver.py:246 Stopping clock generator
2026-01-29 02:36:58.695 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=135 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:36:58.695 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=135 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:36:58.695 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=135 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:36:58.695 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=135 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:36:58.695 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=135 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:36:58.695 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=135 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:36:58.695 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=135 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:36:58.695 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=135 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:37:03.696 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.28.20:5700) Recv POWEROFF cmd
2026-01-29 02:37:03.697 [INFO] ctrl_if_trx.py:117 (BTS@172.18.28.20:5700) Stopping transceiver...
2026-01-29 02:37:03.698 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:37:03.700 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:37:03.701 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:37:03.701 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 02:37:03.707 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 02:37:03.708 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.28.20:5700) Recv SETFORMAT cmd
2026-01-29 02:37:03.708 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.28.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:37:03.708 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.28.20:5700) Recv SETFORMAT cmd
2026-01-29 02:37:03.708 [INFO] ctrl_if_trx.py:201 (BTS@172.18.28.20:5700) TRXD header version 1 -> 1
2026-01-29 02:37:03.711 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.28.20:5700/1) Recv RXTUNE cmd
2026-01-29 02:37:03.712 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.28.20:5700/1) Recv TXTUNE cmd
2026-01-29 02:37:03.712 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.28.20:5700/1) Recv SETFORMAT cmd
2026-01-29 02:37:03.712 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.28.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:37:03.712 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:37:03.713 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.28.20:5700/1) Recv NOMTXPOWER cmd
2026-01-29 02:37:03.713 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.28.20:5700/1) Recv SETFORMAT cmd
2026-01-29 02:37:03.713 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.28.20:5700/1) TRXD header version 1 -> 1
2026-01-29 02:37:03.714 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.28.20:5700/2) Recv RXTUNE cmd
2026-01-29 02:37:03.714 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.28.20:5700/2) Recv TXTUNE cmd
2026-01-29 02:37:03.714 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.28.20:5700/2) Recv SETFORMAT cmd
2026-01-29 02:37:03.715 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.28.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:37:03.715 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:37:03.715 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.28.20:5700/2) Recv NOMTXPOWER cmd
2026-01-29 02:37:03.715 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.28.20:5700/2) Recv SETFORMAT cmd
2026-01-29 02:37:03.715 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.28.20:5700/2) TRXD header version 1 -> 1
2026-01-29 02:37:03.717 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.28.20:5700/3) Recv RXTUNE cmd
2026-01-29 02:37:03.717 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.28.20:5700/3) Recv TXTUNE cmd
2026-01-29 02:37:03.717 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.28.20:5700/3) Recv SETFORMAT cmd
2026-01-29 02:37:03.717 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.28.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:37:03.717 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:37:03.717 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.28.20:5700/3) Recv NOMTXPOWER cmd
2026-01-29 02:37:03.718 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.28.20:5700/3) Recv SETFORMAT cmd
2026-01-29 02:37:03.718 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.28.20:5700/3) TRXD header version 1 -> 1
2026-01-29 02:37:03.720 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.28.20:5700) Recv RXTUNE cmd
2026-01-29 02:37:03.720 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETTSC
2026-01-29 02:37:03.720 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETTSC
2026-01-29 02:37:03.720 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETTSC
2026-01-29 02:37:03.720 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.28.20:5700) Recv TXTUNE cmd
2026-01-29 02:37:03.720 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETRXGAIN
2026-01-29 02:37:03.720 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETRXGAIN
2026-01-29 02:37:03.721 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETRXGAIN
2026-01-29 02:37:03.721 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETTSC
2026-01-29 02:37:03.721 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:37:03.721 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:37:03.721 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:37:03.721 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.28.20:5700) Recv NOMTXPOWER cmd
2026-01-29 02:37:03.721 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:37:03.721 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:37:03.721 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:37:03.721 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.28.20:5700) Recv POWERON CMD
2026-01-29 02:37:03.721 [INFO] ctrl_if_trx.py:109 (BTS@172.18.28.20:5700) Starting transceiver...
2026-01-29 02:37:03.721 [INFO] transceiver.py:243 Starting clock generator
2026-01-29 02:37:03.721 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-01-29 02:37:03.721 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:37:03.721 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:37:03.721 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:37:03.721 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETRXGAIN
2026-01-29 02:37:03.721 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:37:03.721 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:37:03.721 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:37:03.721 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:37:03.721 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:37:03.722 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:37:03.722 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:37:03.722 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:37:03.722 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:37:03.722 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:37:03.722 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:37:03.722 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:37:03.722 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:37:03.722 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:37:03.722 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:37:03.722 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:37:03.722 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:37:03.722 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:37:03.722 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:37:03.722 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:37:03.722 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:37:03.722 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:37:03.722 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:37:03.726 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-01-29 02:37:04.210 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-01-29 02:37:04.243 [DEBUG] fake_trx.py:278 (BTS@172.18.28.20:5700) Recv FAKE_TOA cmd
2026-01-29 02:37:04.245 [DEBUG] fake_trx.py:297 (BTS@172.18.28.20:5700) Recv FAKE_RSSI cmd
2026-01-29 02:37:04.246 [DEBUG] fake_trx.py:322 (BTS@172.18.28.20:5700) Recv FAKE_CI cmd
2026-01-29 02:37:04.246 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:37:04.268 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:37:04.273 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:37:04.277 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:37:04.280 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:37:04.285 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:37:04.286 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:37:04.290 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:37:04.292 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:37:04.293 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:37:04.295 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:37:04.296 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:37:04.297 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:37:04.304 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:37:04.305 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:37:04.305 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:37:04.308 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:37:04.309 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:37:04.310 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:37:04.312 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:37:04.313 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:37:04.313 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:37:04.316 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:37:04.317 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:37:04.318 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:37:04.325 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:37:04.326 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:37:04.327 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:37:04.330 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:37:04.331 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:37:04.332 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:37:04.333 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:37:04.335 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:37:04.336 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:37:04.338 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:37:04.339 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:37:04.339 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:37:04.347 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:37:04.348 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:37:04.349 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:37:04.351 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:37:04.352 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:37:04.352 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:37:04.354 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:37:04.356 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:37:04.357 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:37:04.359 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:37:04.360 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:37:04.361 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:37:04.364 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 02:37:04.364 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:37:04.364 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:37:04.364 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:37:04.365 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 02:37:04.365 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:37:04.365 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:37:04.365 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:37:04.365 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.28.20:5700) Recv POWEROFF cmd
2026-01-29 02:37:04.365 [INFO] ctrl_if_trx.py:117 (BTS@172.18.28.20:5700) Stopping transceiver...
2026-01-29 02:37:04.365 [INFO] transceiver.py:246 Stopping clock generator
2026-01-29 02:37:04.365 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=137 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:37:04.365 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=137 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:37:04.365 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=137 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:37:04.365 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=137 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:37:04.365 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=137 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:37:04.365 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=137 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:37:04.365 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=137 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:37:04.365 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=137 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:37:09.371 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.28.20:5700) Recv POWEROFF cmd
2026-01-29 02:37:09.371 [INFO] ctrl_if_trx.py:117 (BTS@172.18.28.20:5700) Stopping transceiver...
2026-01-29 02:37:09.371 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:37:09.371 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:37:09.371 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:37:09.371 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 02:37:09.379 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 02:37:09.381 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.28.20:5700) Recv SETFORMAT cmd
2026-01-29 02:37:09.381 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.28.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:37:09.382 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.28.20:5700) Recv SETFORMAT cmd
2026-01-29 02:37:09.382 [INFO] ctrl_if_trx.py:201 (BTS@172.18.28.20:5700) TRXD header version 1 -> 1
2026-01-29 02:37:09.386 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.28.20:5700/1) Recv RXTUNE cmd
2026-01-29 02:37:09.386 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.28.20:5700/1) Recv TXTUNE cmd
2026-01-29 02:37:09.386 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.28.20:5700/1) Recv SETFORMAT cmd
2026-01-29 02:37:09.386 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.28.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:37:09.387 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:37:09.387 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.28.20:5700/1) Recv NOMTXPOWER cmd
2026-01-29 02:37:09.387 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.28.20:5700/1) Recv SETFORMAT cmd
2026-01-29 02:37:09.387 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.28.20:5700/1) TRXD header version 1 -> 1
2026-01-29 02:37:09.390 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.28.20:5700/2) Recv RXTUNE cmd
2026-01-29 02:37:09.390 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.28.20:5700/2) Recv TXTUNE cmd
2026-01-29 02:37:09.391 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.28.20:5700/2) Recv SETFORMAT cmd
2026-01-29 02:37:09.391 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.28.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:37:09.391 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:37:09.392 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.28.20:5700/2) Recv NOMTXPOWER cmd
2026-01-29 02:37:09.392 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.28.20:5700/2) Recv SETFORMAT cmd
2026-01-29 02:37:09.392 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.28.20:5700/2) TRXD header version 1 -> 1
2026-01-29 02:37:09.393 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.28.20:5700/3) Recv RXTUNE cmd
2026-01-29 02:37:09.393 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.28.20:5700/3) Recv TXTUNE cmd
2026-01-29 02:37:09.394 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.28.20:5700/3) Recv SETFORMAT cmd
2026-01-29 02:37:09.394 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.28.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:37:09.394 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:37:09.394 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.28.20:5700/3) Recv NOMTXPOWER cmd
2026-01-29 02:37:09.394 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.28.20:5700/3) Recv SETFORMAT cmd
2026-01-29 02:37:09.394 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.28.20:5700/3) TRXD header version 1 -> 1
2026-01-29 02:37:09.397 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.28.20:5700) Recv RXTUNE cmd
2026-01-29 02:37:09.397 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETTSC
2026-01-29 02:37:09.397 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETTSC
2026-01-29 02:37:09.397 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETTSC
2026-01-29 02:37:09.397 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.28.20:5700) Recv TXTUNE cmd
2026-01-29 02:37:09.397 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETRXGAIN
2026-01-29 02:37:09.398 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETRXGAIN
2026-01-29 02:37:09.398 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETRXGAIN
2026-01-29 02:37:09.398 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETTSC
2026-01-29 02:37:09.398 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:37:09.398 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:37:09.398 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.28.20:5700) Recv NOMTXPOWER cmd
2026-01-29 02:37:09.398 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:37:09.398 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:37:09.398 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:37:09.398 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.28.20:5700) Recv POWERON CMD
2026-01-29 02:37:09.398 [INFO] ctrl_if_trx.py:109 (BTS@172.18.28.20:5700) Starting transceiver...
2026-01-29 02:37:09.398 [INFO] transceiver.py:243 Starting clock generator
2026-01-29 02:37:09.398 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-01-29 02:37:09.398 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:37:09.398 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:37:09.398 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:37:09.398 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETRXGAIN
2026-01-29 02:37:09.399 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:37:09.399 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:37:09.399 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:37:09.399 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:37:09.399 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:37:09.399 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:37:09.399 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:37:09.399 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:37:09.399 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:37:09.399 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:37:09.399 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:37:09.399 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:37:09.399 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:37:09.399 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:37:09.399 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:37:09.399 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:37:09.399 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:37:09.399 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:37:09.399 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:37:09.399 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:37:09.399 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:37:09.399 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:37:09.399 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:37:09.399 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:37:09.403 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-01-29 02:37:09.886 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-01-29 02:37:09.929 [DEBUG] fake_trx.py:278 (BTS@172.18.28.20:5700) Recv FAKE_TOA cmd
2026-01-29 02:37:09.932 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:37:09.932 [DEBUG] fake_trx.py:297 (BTS@172.18.28.20:5700) Recv FAKE_RSSI cmd
2026-01-29 02:37:09.936 [DEBUG] fake_trx.py:322 (BTS@172.18.28.20:5700) Recv FAKE_CI cmd
2026-01-29 02:37:09.964 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:37:09.971 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:37:09.974 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:37:09.977 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:37:09.980 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:37:09.984 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:37:09.989 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:37:09.990 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:37:09.991 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:37:09.999 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:37:10.001 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:37:10.002 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:37:10.004 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:37:10.006 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:37:10.007 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:37:10.008 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:37:10.009 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:37:10.010 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:37:10.018 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:37:10.019 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:37:10.019 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:37:10.022 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:37:10.023 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:37:10.023 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:37:10.026 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:37:10.027 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:37:10.027 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:37:10.035 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:37:10.036 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:37:10.037 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:37:10.038 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:37:10.039 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:37:10.040 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:37:10.042 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:37:10.043 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:37:10.043 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:37:10.046 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 02:37:10.046 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:37:10.046 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:37:10.046 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:37:10.047 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 02:37:10.047 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:37:10.047 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:37:10.047 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:37:10.047 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.28.20:5700) Recv POWEROFF cmd
2026-01-29 02:37:10.047 [INFO] ctrl_if_trx.py:117 (BTS@172.18.28.20:5700) Stopping transceiver...
2026-01-29 02:37:10.047 [INFO] transceiver.py:246 Stopping clock generator
2026-01-29 02:37:15.050 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.28.20:5700) Recv POWEROFF cmd
2026-01-29 02:37:15.050 [INFO] ctrl_if_trx.py:117 (BTS@172.18.28.20:5700) Stopping transceiver...
2026-01-29 02:37:15.051 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:37:15.052 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:37:15.053 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:37:15.053 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 02:37:15.059 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 02:37:15.061 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.28.20:5700) Recv SETFORMAT cmd
2026-01-29 02:37:15.061 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.28.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:37:15.062 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.28.20:5700) Recv SETFORMAT cmd
2026-01-29 02:37:15.062 [INFO] ctrl_if_trx.py:201 (BTS@172.18.28.20:5700) TRXD header version 1 -> 1
2026-01-29 02:37:15.067 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.28.20:5700/1) Recv RXTUNE cmd
2026-01-29 02:37:15.067 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.28.20:5700/1) Recv TXTUNE cmd
2026-01-29 02:37:15.067 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.28.20:5700/1) Recv SETFORMAT cmd
2026-01-29 02:37:15.067 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.28.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:37:15.067 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:37:15.067 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.28.20:5700/1) Recv NOMTXPOWER cmd
2026-01-29 02:37:15.067 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.28.20:5700/1) Recv SETFORMAT cmd
2026-01-29 02:37:15.067 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.28.20:5700/1) TRXD header version 1 -> 1
2026-01-29 02:37:15.070 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.28.20:5700/2) Recv RXTUNE cmd
2026-01-29 02:37:15.071 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.28.20:5700/2) Recv TXTUNE cmd
2026-01-29 02:37:15.071 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.28.20:5700/2) Recv SETFORMAT cmd
2026-01-29 02:37:15.071 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.28.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:37:15.071 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:37:15.071 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.28.20:5700/2) Recv NOMTXPOWER cmd
2026-01-29 02:37:15.071 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.28.20:5700/2) Recv SETFORMAT cmd
2026-01-29 02:37:15.071 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.28.20:5700/2) TRXD header version 1 -> 1
2026-01-29 02:37:15.074 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.28.20:5700/3) Recv RXTUNE cmd
2026-01-29 02:37:15.074 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.28.20:5700/3) Recv TXTUNE cmd
2026-01-29 02:37:15.074 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.28.20:5700/3) Recv SETFORMAT cmd
2026-01-29 02:37:15.074 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.28.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:37:15.074 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:37:15.074 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.28.20:5700/3) Recv NOMTXPOWER cmd
2026-01-29 02:37:15.074 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.28.20:5700/3) Recv SETFORMAT cmd
2026-01-29 02:37:15.074 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.28.20:5700/3) TRXD header version 1 -> 1
2026-01-29 02:37:15.078 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.28.20:5700) Recv RXTUNE cmd
2026-01-29 02:37:15.078 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETTSC
2026-01-29 02:37:15.078 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETTSC
2026-01-29 02:37:15.078 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETTSC
2026-01-29 02:37:15.078 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.28.20:5700) Recv TXTUNE cmd
2026-01-29 02:37:15.078 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETRXGAIN
2026-01-29 02:37:15.078 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETRXGAIN
2026-01-29 02:37:15.078 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETRXGAIN
2026-01-29 02:37:15.078 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETTSC
2026-01-29 02:37:15.078 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:37:15.079 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:37:15.079 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:37:15.079 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.28.20:5700) Recv NOMTXPOWER cmd
2026-01-29 02:37:15.079 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:37:15.079 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:37:15.079 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:37:15.079 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.28.20:5700) Recv POWERON CMD
2026-01-29 02:37:15.079 [INFO] ctrl_if_trx.py:109 (BTS@172.18.28.20:5700) Starting transceiver...
2026-01-29 02:37:15.079 [INFO] transceiver.py:243 Starting clock generator
2026-01-29 02:37:15.079 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-01-29 02:37:15.079 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:37:15.079 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:37:15.079 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:37:15.079 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETRXGAIN
2026-01-29 02:37:15.080 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:37:15.080 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:37:15.080 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:37:15.080 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:37:15.080 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:37:15.080 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:37:15.080 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:37:15.080 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:37:15.080 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:37:15.080 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:37:15.080 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:37:15.080 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:37:15.080 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:37:15.080 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:37:15.080 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:37:15.080 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:37:15.080 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:37:15.080 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:37:15.080 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:37:15.080 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:37:15.081 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:37:15.081 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:37:15.081 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:37:15.084 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-01-29 02:37:15.568 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-01-29 02:37:15.609 [DEBUG] fake_trx.py:278 (BTS@172.18.28.20:5700) Recv FAKE_TOA cmd
2026-01-29 02:37:15.611 [DEBUG] fake_trx.py:297 (BTS@172.18.28.20:5700) Recv FAKE_RSSI cmd
2026-01-29 02:37:15.612 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:37:15.613 [DEBUG] fake_trx.py:322 (BTS@172.18.28.20:5700) Recv FAKE_CI cmd
2026-01-29 02:37:15.638 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:37:15.641 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:37:15.642 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:37:15.644 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:37:15.646 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:37:15.646 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:37:15.654 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:37:15.655 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:37:15.655 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:37:15.658 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:37:15.659 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:37:15.659 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:37:15.666 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:37:15.667 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:37:15.668 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:37:15.671 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:37:15.672 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:37:15.672 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:37:15.680 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:37:15.681 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:37:15.682 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:37:15.684 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:37:15.685 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:37:15.685 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:37:15.687 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 02:37:15.687 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:37:15.687 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:37:15.687 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:37:15.689 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 02:37:15.689 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:37:15.689 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:37:15.689 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.28.20:5700) Recv POWEROFF cmd
2026-01-29 02:37:15.689 [INFO] ctrl_if_trx.py:117 (BTS@172.18.28.20:5700) Stopping transceiver...
2026-01-29 02:37:15.689 [INFO] transceiver.py:246 Stopping clock generator
2026-01-29 02:37:15.689 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:37:15.689 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=130 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:37:15.689 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=130 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:37:15.689 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=130 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:37:15.689 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=130 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:37:15.689 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=130 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:37:15.689 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=130 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:37:15.689 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=130 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:37:15.689 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=130 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:37:20.695 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.28.20:5700) Recv POWEROFF cmd
2026-01-29 02:37:20.695 [INFO] ctrl_if_trx.py:117 (BTS@172.18.28.20:5700) Stopping transceiver...
2026-01-29 02:37:20.695 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:37:20.695 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:37:20.695 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:37:20.695 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 02:37:20.702 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 02:37:20.703 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.28.20:5700) Recv SETFORMAT cmd
2026-01-29 02:37:20.703 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.28.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:37:20.704 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.28.20:5700) Recv SETFORMAT cmd
2026-01-29 02:37:20.704 [INFO] ctrl_if_trx.py:201 (BTS@172.18.28.20:5700) TRXD header version 1 -> 1
2026-01-29 02:37:20.707 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.28.20:5700/1) Recv RXTUNE cmd
2026-01-29 02:37:20.707 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.28.20:5700/1) Recv TXTUNE cmd
2026-01-29 02:37:20.708 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.28.20:5700/1) Recv SETFORMAT cmd
2026-01-29 02:37:20.708 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.28.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:37:20.708 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:37:20.709 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.28.20:5700/1) Recv NOMTXPOWER cmd
2026-01-29 02:37:20.709 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.28.20:5700/1) Recv SETFORMAT cmd
2026-01-29 02:37:20.709 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.28.20:5700/1) TRXD header version 1 -> 1
2026-01-29 02:37:20.711 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.28.20:5700/2) Recv RXTUNE cmd
2026-01-29 02:37:20.711 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.28.20:5700/2) Recv TXTUNE cmd
2026-01-29 02:37:20.711 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.28.20:5700/2) Recv SETFORMAT cmd
2026-01-29 02:37:20.711 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.28.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:37:20.711 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:37:20.711 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.28.20:5700/2) Recv NOMTXPOWER cmd
2026-01-29 02:37:20.712 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.28.20:5700/2) Recv SETFORMAT cmd
2026-01-29 02:37:20.712 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.28.20:5700/2) TRXD header version 1 -> 1
2026-01-29 02:37:20.713 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.28.20:5700/3) Recv RXTUNE cmd
2026-01-29 02:37:20.713 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.28.20:5700/3) Recv TXTUNE cmd
2026-01-29 02:37:20.713 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.28.20:5700/3) Recv SETFORMAT cmd
2026-01-29 02:37:20.713 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.28.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:37:20.714 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:37:20.714 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.28.20:5700/3) Recv NOMTXPOWER cmd
2026-01-29 02:37:20.714 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.28.20:5700/3) Recv SETFORMAT cmd
2026-01-29 02:37:20.714 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.28.20:5700/3) TRXD header version 1 -> 1
2026-01-29 02:37:20.716 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.28.20:5700) Recv RXTUNE cmd
2026-01-29 02:37:20.716 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETTSC
2026-01-29 02:37:20.716 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETTSC
2026-01-29 02:37:20.716 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETTSC
2026-01-29 02:37:20.716 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.28.20:5700) Recv TXTUNE cmd
2026-01-29 02:37:20.716 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETRXGAIN
2026-01-29 02:37:20.717 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETRXGAIN
2026-01-29 02:37:20.717 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETRXGAIN
2026-01-29 02:37:20.717 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETTSC
2026-01-29 02:37:20.717 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:37:20.717 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:37:20.717 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:37:20.717 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.28.20:5700) Recv NOMTXPOWER cmd
2026-01-29 02:37:20.717 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:37:20.717 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:37:20.717 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:37:20.717 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.28.20:5700) Recv POWERON CMD
2026-01-29 02:37:20.717 [INFO] ctrl_if_trx.py:109 (BTS@172.18.28.20:5700) Starting transceiver...
2026-01-29 02:37:20.717 [INFO] transceiver.py:243 Starting clock generator
2026-01-29 02:37:20.717 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-01-29 02:37:20.717 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:37:20.717 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:37:20.717 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:37:20.717 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETRXGAIN
2026-01-29 02:37:20.718 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:37:20.718 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:37:20.718 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:37:20.718 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:37:20.718 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:37:20.718 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:37:20.718 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:37:20.718 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:37:20.718 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:37:20.718 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:37:20.718 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:37:20.718 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:37:20.718 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:37:20.718 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:37:20.718 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:37:20.718 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:37:20.718 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:37:20.718 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:37:20.718 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:37:20.718 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:37:20.718 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:37:20.719 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:37:20.719 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:37:20.722 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-01-29 02:37:21.199 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-01-29 02:37:21.250 [DEBUG] fake_trx.py:278 (BTS@172.18.28.20:5700) Recv FAKE_TOA cmd
2026-01-29 02:37:21.252 [DEBUG] fake_trx.py:297 (BTS@172.18.28.20:5700) Recv FAKE_RSSI cmd
2026-01-29 02:37:21.253 [DEBUG] fake_trx.py:322 (BTS@172.18.28.20:5700) Recv FAKE_CI cmd
2026-01-29 02:37:21.254 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:37:21.278 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:37:21.279 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:37:21.284 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:37:21.288 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:37:21.294 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:37:21.299 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:37:21.301 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:37:21.310 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:37:21.312 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:37:21.312 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:37:21.315 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:37:21.316 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:37:21.316 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:37:21.324 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:37:21.325 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:37:21.326 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:37:21.328 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:37:21.329 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:37:21.330 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:37:21.337 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:37:21.338 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:37:21.339 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:37:21.341 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:37:21.342 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:37:21.343 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:37:21.346 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 02:37:21.346 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:37:21.346 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:37:21.346 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:37:21.348 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 02:37:21.348 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:37:21.348 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:37:21.348 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.28.20:5700) Recv POWEROFF cmd
2026-01-29 02:37:21.348 [INFO] ctrl_if_trx.py:117 (BTS@172.18.28.20:5700) Stopping transceiver...
2026-01-29 02:37:21.348 [INFO] transceiver.py:246 Stopping clock generator
2026-01-29 02:37:21.348 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:37:21.348 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=136 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:37:21.348 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=136 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:37:21.348 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=136 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:37:21.348 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=136 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:37:21.348 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=136 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:37:21.348 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=136 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:37:21.348 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=136 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:37:21.348 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=136 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:37:26.350 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.28.20:5700) Recv POWEROFF cmd
2026-01-29 02:37:26.350 [INFO] ctrl_if_trx.py:117 (BTS@172.18.28.20:5700) Stopping transceiver...
2026-01-29 02:37:26.352 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:37:26.353 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:37:26.354 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:37:26.354 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 02:37:26.357 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 02:37:26.357 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.28.20:5700) Recv SETFORMAT cmd
2026-01-29 02:37:26.358 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.28.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:37:26.358 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.28.20:5700) Recv SETFORMAT cmd
2026-01-29 02:37:26.358 [INFO] ctrl_if_trx.py:201 (BTS@172.18.28.20:5700) TRXD header version 1 -> 1
2026-01-29 02:37:26.359 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.28.20:5700/1) Recv RXTUNE cmd
2026-01-29 02:37:26.359 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.28.20:5700/1) Recv TXTUNE cmd
2026-01-29 02:37:26.360 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.28.20:5700/1) Recv SETFORMAT cmd
2026-01-29 02:37:26.360 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.28.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:37:26.360 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:37:26.360 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.28.20:5700/1) Recv NOMTXPOWER cmd
2026-01-29 02:37:26.360 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.28.20:5700/1) Recv SETFORMAT cmd
2026-01-29 02:37:26.360 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.28.20:5700/1) TRXD header version 1 -> 1
2026-01-29 02:37:26.361 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.28.20:5700/2) Recv RXTUNE cmd
2026-01-29 02:37:26.361 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.28.20:5700/2) Recv TXTUNE cmd
2026-01-29 02:37:26.361 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.28.20:5700/2) Recv SETFORMAT cmd
2026-01-29 02:37:26.361 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.28.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:37:26.361 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:37:26.361 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.28.20:5700/2) Recv NOMTXPOWER cmd
2026-01-29 02:37:26.361 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.28.20:5700/2) Recv SETFORMAT cmd
2026-01-29 02:37:26.361 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.28.20:5700/2) TRXD header version 1 -> 1
2026-01-29 02:37:26.363 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.28.20:5700/3) Recv RXTUNE cmd
2026-01-29 02:37:26.363 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.28.20:5700/3) Recv TXTUNE cmd
2026-01-29 02:37:26.363 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.28.20:5700/3) Recv SETFORMAT cmd
2026-01-29 02:37:26.363 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.28.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:37:26.363 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:37:26.363 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.28.20:5700/3) Recv NOMTXPOWER cmd
2026-01-29 02:37:26.363 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.28.20:5700/3) Recv SETFORMAT cmd
2026-01-29 02:37:26.363 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.28.20:5700/3) TRXD header version 1 -> 1
2026-01-29 02:37:26.365 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.28.20:5700) Recv RXTUNE cmd
2026-01-29 02:37:26.365 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETTSC
2026-01-29 02:37:26.365 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETTSC
2026-01-29 02:37:26.365 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETTSC
2026-01-29 02:37:26.365 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.28.20:5700) Recv TXTUNE cmd
2026-01-29 02:37:26.365 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETRXGAIN
2026-01-29 02:37:26.365 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETRXGAIN
2026-01-29 02:37:26.365 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETRXGAIN
2026-01-29 02:37:26.365 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETTSC
2026-01-29 02:37:26.365 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:37:26.365 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:37:26.365 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:37:26.365 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.28.20:5700) Recv NOMTXPOWER cmd
2026-01-29 02:37:26.365 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:37:26.365 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:37:26.365 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:37:26.365 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.28.20:5700) Recv POWERON CMD
2026-01-29 02:37:26.365 [INFO] ctrl_if_trx.py:109 (BTS@172.18.28.20:5700) Starting transceiver...
2026-01-29 02:37:26.365 [INFO] transceiver.py:243 Starting clock generator
2026-01-29 02:37:26.365 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-01-29 02:37:26.365 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:37:26.365 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:37:26.365 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:37:26.365 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETRXGAIN
2026-01-29 02:37:26.365 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:37:26.365 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:37:26.365 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:37:26.365 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:37:26.366 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:37:26.366 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:37:26.366 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:37:26.366 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:37:26.366 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:37:26.366 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:37:26.366 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:37:26.366 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:37:26.366 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:37:26.366 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:37:26.366 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:37:26.366 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:37:26.366 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:37:26.366 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:37:26.366 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:37:26.366 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:37:26.366 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:37:26.366 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:37:26.366 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:37:26.370 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-01-29 02:37:26.851 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-01-29 02:37:26.880 [DEBUG] fake_trx.py:278 (BTS@172.18.28.20:5700) Recv FAKE_TOA cmd
2026-01-29 02:37:26.880 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:37:26.880 [DEBUG] fake_trx.py:297 (BTS@172.18.28.20:5700) Recv FAKE_RSSI cmd
2026-01-29 02:37:26.881 [DEBUG] fake_trx.py:322 (BTS@172.18.28.20:5700) Recv FAKE_CI cmd
2026-01-29 02:37:26.889 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:37:26.889 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:37:26.890 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:37:26.891 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:37:26.892 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:37:26.893 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:37:26.894 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:37:26.896 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:37:26.897 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:37:26.898 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:37:26.901 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:37:26.902 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:37:26.903 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:37:26.911 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:37:26.912 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:37:26.913 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:37:26.914 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:37:26.916 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:37:26.916 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:37:26.918 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:37:26.919 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:37:26.920 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:37:26.923 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:37:26.924 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:37:26.924 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:37:26.932 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:37:26.933 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:37:26.934 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:37:26.936 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:37:26.937 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:37:26.938 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:37:26.939 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:37:26.940 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:37:26.941 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:37:26.944 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:37:26.945 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:37:26.946 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:37:26.954 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:37:26.955 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:37:26.956 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:37:26.958 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:37:26.959 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:37:26.960 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:37:26.963 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:37:26.964 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:37:26.965 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:37:26.967 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:37:26.968 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:37:26.969 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:37:26.972 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 02:37:26.972 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:37:26.972 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:37:26.972 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:37:26.973 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 02:37:26.973 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:37:26.973 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:37:26.973 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.28.20:5700) Recv POWEROFF cmd
2026-01-29 02:37:26.973 [INFO] ctrl_if_trx.py:117 (BTS@172.18.28.20:5700) Stopping transceiver...
2026-01-29 02:37:26.973 [INFO] transceiver.py:246 Stopping clock generator
2026-01-29 02:37:26.973 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:37:26.973 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=130 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:37:26.973 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=130 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:37:26.973 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=130 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:37:26.973 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=130 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:37:26.973 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=130 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:37:26.973 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=130 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:37:26.973 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=130 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:37:26.973 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=130 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:37:31.976 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.28.20:5700) Recv POWEROFF cmd
2026-01-29 02:37:31.976 [INFO] ctrl_if_trx.py:117 (BTS@172.18.28.20:5700) Stopping transceiver...
2026-01-29 02:37:31.977 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:37:31.979 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:37:31.981 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:37:31.983 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 02:37:31.991 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 02:37:31.992 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.28.20:5700) Recv SETFORMAT cmd
2026-01-29 02:37:31.992 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.28.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:37:31.992 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.28.20:5700) Recv SETFORMAT cmd
2026-01-29 02:37:31.992 [INFO] ctrl_if_trx.py:201 (BTS@172.18.28.20:5700) TRXD header version 1 -> 1
2026-01-29 02:37:31.994 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.28.20:5700/1) Recv RXTUNE cmd
2026-01-29 02:37:31.994 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.28.20:5700/1) Recv TXTUNE cmd
2026-01-29 02:37:31.994 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.28.20:5700/1) Recv SETFORMAT cmd
2026-01-29 02:37:31.994 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.28.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:37:31.994 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:37:31.994 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.28.20:5700/1) Recv NOMTXPOWER cmd
2026-01-29 02:37:31.994 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.28.20:5700/1) Recv SETFORMAT cmd
2026-01-29 02:37:31.994 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.28.20:5700/1) TRXD header version 1 -> 1
2026-01-29 02:37:31.996 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.28.20:5700/2) Recv RXTUNE cmd
2026-01-29 02:37:31.996 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.28.20:5700/2) Recv TXTUNE cmd
2026-01-29 02:37:31.996 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.28.20:5700/2) Recv SETFORMAT cmd
2026-01-29 02:37:31.996 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.28.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:37:31.996 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:37:31.996 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.28.20:5700/2) Recv NOMTXPOWER cmd
2026-01-29 02:37:31.996 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.28.20:5700/2) Recv SETFORMAT cmd
2026-01-29 02:37:31.996 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.28.20:5700/2) TRXD header version 1 -> 1
2026-01-29 02:37:31.998 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.28.20:5700/3) Recv RXTUNE cmd
2026-01-29 02:37:31.998 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.28.20:5700/3) Recv TXTUNE cmd
2026-01-29 02:37:31.998 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.28.20:5700/3) Recv SETFORMAT cmd
2026-01-29 02:37:31.998 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.28.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:37:31.998 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:37:31.998 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.28.20:5700/3) Recv NOMTXPOWER cmd
2026-01-29 02:37:31.998 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.28.20:5700/3) Recv SETFORMAT cmd
2026-01-29 02:37:31.998 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.28.20:5700/3) TRXD header version 1 -> 1
2026-01-29 02:37:32.000 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.28.20:5700) Recv RXTUNE cmd
2026-01-29 02:37:32.000 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETTSC
2026-01-29 02:37:32.000 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETTSC
2026-01-29 02:37:32.000 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETTSC
2026-01-29 02:37:32.000 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.28.20:5700) Recv TXTUNE cmd
2026-01-29 02:37:32.001 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETRXGAIN
2026-01-29 02:37:32.001 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETRXGAIN
2026-01-29 02:37:32.001 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETRXGAIN
2026-01-29 02:37:32.001 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETTSC
2026-01-29 02:37:32.001 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:37:32.001 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:37:32.001 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:37:32.001 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.28.20:5700) Recv NOMTXPOWER cmd
2026-01-29 02:37:32.001 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:37:32.001 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:37:32.001 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:37:32.001 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.28.20:5700) Recv POWERON CMD
2026-01-29 02:37:32.001 [INFO] ctrl_if_trx.py:109 (BTS@172.18.28.20:5700) Starting transceiver...
2026-01-29 02:37:32.001 [INFO] transceiver.py:243 Starting clock generator
2026-01-29 02:37:32.001 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-01-29 02:37:32.001 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:37:32.001 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:37:32.001 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:37:32.001 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETRXGAIN
2026-01-29 02:37:32.001 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:37:32.001 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:37:32.001 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:37:32.001 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:37:32.001 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:37:32.001 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:37:32.001 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:37:32.002 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:37:32.002 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:37:32.002 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:37:32.002 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:37:32.002 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:37:32.002 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:37:32.002 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:37:32.002 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:37:32.002 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:37:32.002 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:37:32.002 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:37:32.002 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:37:32.002 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:37:32.002 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:37:32.002 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:37:32.002 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:37:32.006 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-01-29 02:37:32.486 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-01-29 02:37:32.514 [DEBUG] fake_trx.py:278 (BTS@172.18.28.20:5700) Recv FAKE_TOA cmd
2026-01-29 02:37:32.515 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:37:32.515 [DEBUG] fake_trx.py:297 (BTS@172.18.28.20:5700) Recv FAKE_RSSI cmd
2026-01-29 02:37:32.516 [DEBUG] fake_trx.py:322 (BTS@172.18.28.20:5700) Recv FAKE_CI cmd
2026-01-29 02:37:32.529 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:37:32.529 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:37:32.532 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:37:32.534 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:37:32.538 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:37:32.540 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:37:32.541 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:37:32.545 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:37:32.546 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:37:32.546 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:37:32.555 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:37:32.556 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:37:32.557 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:37:32.561 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:37:32.562 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:37:32.562 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:37:32.565 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:37:32.566 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:37:32.567 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:37:32.574 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:37:32.575 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:37:32.576 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:37:32.578 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:37:32.578 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:37:32.579 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:37:32.582 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:37:32.583 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:37:32.584 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:37:32.591 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:37:32.592 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:37:32.593 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:37:32.595 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:37:32.596 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:37:32.596 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:37:32.599 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:37:32.600 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:37:32.601 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:37:32.604 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 02:37:32.604 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:37:32.604 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:37:32.604 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:37:32.605 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 02:37:32.605 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:37:32.605 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:37:32.605 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:37:32.605 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.28.20:5700) Recv POWEROFF cmd
2026-01-29 02:37:32.605 [INFO] ctrl_if_trx.py:117 (BTS@172.18.28.20:5700) Stopping transceiver...
2026-01-29 02:37:32.605 [INFO] transceiver.py:246 Stopping clock generator
2026-01-29 02:37:37.608 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.28.20:5700) Recv POWEROFF cmd
2026-01-29 02:37:37.608 [INFO] ctrl_if_trx.py:117 (BTS@172.18.28.20:5700) Stopping transceiver...
2026-01-29 02:37:37.610 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:37:37.612 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:37:37.613 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:37:37.616 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 02:37:37.623 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 02:37:37.624 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.28.20:5700) Recv SETFORMAT cmd
2026-01-29 02:37:37.624 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.28.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:37:37.624 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.28.20:5700) Recv SETFORMAT cmd
2026-01-29 02:37:37.624 [INFO] ctrl_if_trx.py:201 (BTS@172.18.28.20:5700) TRXD header version 1 -> 1
2026-01-29 02:37:37.626 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.28.20:5700/1) Recv RXTUNE cmd
2026-01-29 02:37:37.626 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.28.20:5700/1) Recv TXTUNE cmd
2026-01-29 02:37:37.626 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.28.20:5700/1) Recv SETFORMAT cmd
2026-01-29 02:37:37.626 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.28.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:37:37.626 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:37:37.626 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.28.20:5700/1) Recv NOMTXPOWER cmd
2026-01-29 02:37:37.627 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.28.20:5700/1) Recv SETFORMAT cmd
2026-01-29 02:37:37.627 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.28.20:5700/1) TRXD header version 1 -> 1
2026-01-29 02:37:37.628 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.28.20:5700/2) Recv RXTUNE cmd
2026-01-29 02:37:37.628 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.28.20:5700/2) Recv TXTUNE cmd
2026-01-29 02:37:37.628 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.28.20:5700/2) Recv SETFORMAT cmd
2026-01-29 02:37:37.628 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.28.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:37:37.628 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:37:37.628 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.28.20:5700/2) Recv NOMTXPOWER cmd
2026-01-29 02:37:37.628 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.28.20:5700/2) Recv SETFORMAT cmd
2026-01-29 02:37:37.628 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.28.20:5700/2) TRXD header version 1 -> 1
2026-01-29 02:37:37.630 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.28.20:5700/3) Recv RXTUNE cmd
2026-01-29 02:37:37.630 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.28.20:5700/3) Recv TXTUNE cmd
2026-01-29 02:37:37.630 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.28.20:5700/3) Recv SETFORMAT cmd
2026-01-29 02:37:37.630 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.28.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:37:37.630 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:37:37.630 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.28.20:5700/3) Recv NOMTXPOWER cmd
2026-01-29 02:37:37.630 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.28.20:5700/3) Recv SETFORMAT cmd
2026-01-29 02:37:37.630 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.28.20:5700/3) TRXD header version 1 -> 1
2026-01-29 02:37:37.632 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.28.20:5700) Recv RXTUNE cmd
2026-01-29 02:37:37.632 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETTSC
2026-01-29 02:37:37.632 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETTSC
2026-01-29 02:37:37.632 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETTSC
2026-01-29 02:37:37.632 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.28.20:5700) Recv TXTUNE cmd
2026-01-29 02:37:37.632 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETRXGAIN
2026-01-29 02:37:37.632 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETRXGAIN
2026-01-29 02:37:37.632 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETRXGAIN
2026-01-29 02:37:37.632 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETTSC
2026-01-29 02:37:37.632 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:37:37.632 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.28.20:5700) Recv NOMTXPOWER cmd
2026-01-29 02:37:37.632 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:37:37.632 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:37:37.632 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.28.20:5700) Recv POWERON CMD
2026-01-29 02:37:37.632 [INFO] ctrl_if_trx.py:109 (BTS@172.18.28.20:5700) Starting transceiver...
2026-01-29 02:37:37.632 [INFO] transceiver.py:243 Starting clock generator
2026-01-29 02:37:37.632 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-01-29 02:37:37.632 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:37:37.632 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:37:37.632 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:37:37.632 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETRXGAIN
2026-01-29 02:37:37.633 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:37:37.633 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:37:37.633 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:37:37.633 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:37:37.633 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:37:37.633 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:37:37.633 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:37:37.633 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:37:37.633 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:37:37.633 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:37:37.633 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:37:37.633 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:37:37.633 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:37:37.633 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:37:37.633 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:37:37.633 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:37:37.633 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:37:37.633 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:37:37.633 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:37:37.633 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:37:37.633 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:37:37.633 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:37:37.633 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:37:37.633 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:37:37.633 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:37:37.633 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:37:37.637 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-01-29 02:37:38.118 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-01-29 02:37:38.157 [DEBUG] fake_trx.py:278 (BTS@172.18.28.20:5700) Recv FAKE_TOA cmd
2026-01-29 02:37:38.160 [DEBUG] fake_trx.py:297 (BTS@172.18.28.20:5700) Recv FAKE_RSSI cmd
2026-01-29 02:37:38.162 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:37:38.163 [DEBUG] fake_trx.py:322 (BTS@172.18.28.20:5700) Recv FAKE_CI cmd
2026-01-29 02:37:38.169 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 02:37:38.169 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 02:37:38.169 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 02:37:38.170 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:37:38.170 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 02:37:38.171 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 02:37:38.171 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.28.22:6700) Recv POWERON CMD
2026-01-29 02:37:38.171 [INFO] ctrl_if_trx.py:109 (MS@172.18.28.22:6700) Starting transceiver...
2026-01-29 02:37:38.595 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-01-29 02:37:38.635 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:37:38.635 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 02:37:38.636 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:37:38.638 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:37:39.073 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-01-29 02:37:39.551 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-01-29 02:37:39.636 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:37:39.636 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 02:37:39.636 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:37:39.639 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:37:40.029 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-01-29 02:37:40.507 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-01-29 02:37:40.636 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:37:40.637 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 02:37:40.637 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:37:40.640 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:37:40.985 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-01-29 02:37:41.463 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-01-29 02:37:41.635 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 02:37:41.635 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 02:37:41.637 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 02:37:41.637 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:37:41.637 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:37:41.637 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:37:41.639 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 02:37:41.640 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:37:41.640 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:37:41.640 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:37:41.640 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.28.20:5700) Recv POWEROFF cmd
2026-01-29 02:37:41.640 [INFO] ctrl_if_trx.py:117 (BTS@172.18.28.20:5700) Stopping transceiver...
2026-01-29 02:37:41.640 [INFO] transceiver.py:246 Stopping clock generator
2026-01-29 02:37:41.640 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=856 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:37:41.641 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=856 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:37:41.641 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=856 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:37:41.641 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=856 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:37:41.641 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=856 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:37:41.641 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=856 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:37:46.641 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.28.20:5700) Recv POWEROFF cmd
2026-01-29 02:37:46.641 [INFO] ctrl_if_trx.py:117 (BTS@172.18.28.20:5700) Stopping transceiver...
2026-01-29 02:37:46.643 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:37:46.644 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:37:46.646 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:37:46.649 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 02:37:46.659 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 02:37:46.660 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.28.20:5700) Recv SETFORMAT cmd
2026-01-29 02:37:46.660 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.28.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:37:46.660 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.28.20:5700) Recv SETFORMAT cmd
2026-01-29 02:37:46.660 [INFO] ctrl_if_trx.py:201 (BTS@172.18.28.20:5700) TRXD header version 1 -> 1
2026-01-29 02:37:46.662 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.28.20:5700/1) Recv RXTUNE cmd
2026-01-29 02:37:46.662 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.28.20:5700/1) Recv TXTUNE cmd
2026-01-29 02:37:46.662 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.28.20:5700/1) Recv SETFORMAT cmd
2026-01-29 02:37:46.662 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.28.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:37:46.663 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:37:46.663 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.28.20:5700/1) Recv NOMTXPOWER cmd
2026-01-29 02:37:46.663 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.28.20:5700/1) Recv SETFORMAT cmd
2026-01-29 02:37:46.663 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.28.20:5700/1) TRXD header version 1 -> 1
2026-01-29 02:37:46.666 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.28.20:5700/2) Recv RXTUNE cmd
2026-01-29 02:37:46.666 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.28.20:5700/2) Recv TXTUNE cmd
2026-01-29 02:37:46.666 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.28.20:5700/2) Recv SETFORMAT cmd
2026-01-29 02:37:46.666 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.28.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:37:46.667 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:37:46.667 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.28.20:5700/2) Recv NOMTXPOWER cmd
2026-01-29 02:37:46.667 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.28.20:5700/2) Recv SETFORMAT cmd
2026-01-29 02:37:46.667 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.28.20:5700/2) TRXD header version 1 -> 1
2026-01-29 02:37:46.669 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.28.20:5700/3) Recv RXTUNE cmd
2026-01-29 02:37:46.669 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.28.20:5700/3) Recv TXTUNE cmd
2026-01-29 02:37:46.669 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.28.20:5700/3) Recv SETFORMAT cmd
2026-01-29 02:37:46.669 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.28.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:37:46.670 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:37:46.670 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.28.20:5700/3) Recv NOMTXPOWER cmd
2026-01-29 02:37:46.670 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.28.20:5700/3) Recv SETFORMAT cmd
2026-01-29 02:37:46.670 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.28.20:5700/3) TRXD header version 1 -> 1
2026-01-29 02:37:46.673 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.28.20:5700) Recv RXTUNE cmd
2026-01-29 02:37:46.673 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETTSC
2026-01-29 02:37:46.673 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETTSC
2026-01-29 02:37:46.673 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETTSC
2026-01-29 02:37:46.673 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.28.20:5700) Recv TXTUNE cmd
2026-01-29 02:37:46.673 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETRXGAIN
2026-01-29 02:37:46.674 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETRXGAIN
2026-01-29 02:37:46.674 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETRXGAIN
2026-01-29 02:37:46.674 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETTSC
2026-01-29 02:37:46.674 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:37:46.674 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:37:46.674 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.28.20:5700) Recv NOMTXPOWER cmd
2026-01-29 02:37:46.674 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:37:46.674 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:37:46.674 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:37:46.674 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.28.20:5700) Recv POWERON CMD
2026-01-29 02:37:46.674 [INFO] ctrl_if_trx.py:109 (BTS@172.18.28.20:5700) Starting transceiver...
2026-01-29 02:37:46.674 [INFO] transceiver.py:243 Starting clock generator
2026-01-29 02:37:46.674 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-01-29 02:37:46.674 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:37:46.674 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:37:46.675 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:37:46.675 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETRXGAIN
2026-01-29 02:37:46.675 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:37:46.675 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:37:46.675 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:37:46.675 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:37:46.675 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:37:46.675 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:37:46.675 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:37:46.675 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:37:46.675 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:37:46.675 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:37:46.675 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:37:46.675 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:37:46.675 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:37:46.675 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:37:46.675 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:37:46.675 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:37:46.675 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:37:46.675 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:37:46.675 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:37:46.675 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:37:46.675 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:37:46.675 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:37:46.675 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:37:46.675 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:37:46.679 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-01-29 02:37:47.160 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-01-29 02:37:47.193 [DEBUG] fake_trx.py:278 (BTS@172.18.28.20:5700) Recv FAKE_TOA cmd
2026-01-29 02:37:47.193 [DEBUG] fake_trx.py:297 (BTS@172.18.28.20:5700) Recv FAKE_RSSI cmd
2026-01-29 02:37:47.193 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:37:47.194 [DEBUG] fake_trx.py:322 (BTS@172.18.28.20:5700) Recv FAKE_CI cmd
2026-01-29 02:37:47.205 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 02:37:47.205 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 02:37:47.205 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 02:37:47.208 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:37:47.209 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 02:37:47.209 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 02:37:47.209 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.28.22:6700) Recv POWERON CMD
2026-01-29 02:37:47.209 [INFO] ctrl_if_trx.py:109 (MS@172.18.28.22:6700) Starting transceiver...
2026-01-29 02:37:47.255 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD HANDOVER
2026-01-29 02:37:47.256 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 02:37:47.257 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 02:37:47.257 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:37:47.257 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:37:47.637 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-01-29 02:37:47.679 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 02:37:47.679 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:37:47.680 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:37:47.683 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:37:47.759 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:37:47.760 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 02:37:47.760 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 02:37:47.760 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 02:37:47.760 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:37:47.761 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 02:37:47.761 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 02:37:47.761 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.28.22:6700) Recv POWERON CMD
2026-01-29 02:37:47.761 [INFO] ctrl_if_trx.py:109 (MS@172.18.28.22:6700) Starting transceiver...
2026-01-29 02:37:47.774 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:37:47.777 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 02:37:47.777 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 02:37:47.787 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 02:37:47.787 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:37:47.787 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:37:47.787 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:37:47.789 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 02:37:47.789 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:37:47.789 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:37:47.790 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:37:47.790 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.28.20:5700) Recv POWEROFF cmd
2026-01-29 02:37:47.790 [INFO] ctrl_if_trx.py:117 (BTS@172.18.28.20:5700) Stopping transceiver...
2026-01-29 02:37:47.790 [INFO] transceiver.py:246 Stopping clock generator
2026-01-29 02:37:47.790 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=238 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:37:47.790 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=238 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:37:52.791 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.28.20:5700) Recv POWEROFF cmd
2026-01-29 02:37:52.791 [INFO] ctrl_if_trx.py:117 (BTS@172.18.28.20:5700) Stopping transceiver...
2026-01-29 02:37:52.793 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:37:52.794 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:37:52.794 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:37:52.794 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 02:37:52.805 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 02:37:52.807 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.28.20:5700) Recv SETFORMAT cmd
2026-01-29 02:37:52.807 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.28.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:37:52.807 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.28.20:5700) Recv SETFORMAT cmd
2026-01-29 02:37:52.807 [INFO] ctrl_if_trx.py:201 (BTS@172.18.28.20:5700) TRXD header version 1 -> 1
2026-01-29 02:37:52.811 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.28.20:5700/1) Recv RXTUNE cmd
2026-01-29 02:37:52.812 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.28.20:5700/1) Recv TXTUNE cmd
2026-01-29 02:37:52.813 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.28.20:5700/1) Recv SETFORMAT cmd
2026-01-29 02:37:52.813 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.28.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:37:52.813 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:37:52.814 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.28.20:5700/1) Recv NOMTXPOWER cmd
2026-01-29 02:37:52.814 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.28.20:5700/1) Recv SETFORMAT cmd
2026-01-29 02:37:52.814 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.28.20:5700/1) TRXD header version 1 -> 1
2026-01-29 02:37:52.816 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.28.20:5700/2) Recv RXTUNE cmd
2026-01-29 02:37:52.816 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.28.20:5700/2) Recv TXTUNE cmd
2026-01-29 02:37:52.817 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.28.20:5700/2) Recv SETFORMAT cmd
2026-01-29 02:37:52.817 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.28.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:37:52.818 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:37:52.818 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.28.20:5700/2) Recv NOMTXPOWER cmd
2026-01-29 02:37:52.818 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.28.20:5700/2) Recv SETFORMAT cmd
2026-01-29 02:37:52.818 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.28.20:5700/2) TRXD header version 1 -> 1
2026-01-29 02:37:52.819 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.28.20:5700/3) Recv RXTUNE cmd
2026-01-29 02:37:52.820 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.28.20:5700/3) Recv TXTUNE cmd
2026-01-29 02:37:52.820 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.28.20:5700/3) Recv SETFORMAT cmd
2026-01-29 02:37:52.820 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.28.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:37:52.820 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:37:52.820 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.28.20:5700/3) Recv NOMTXPOWER cmd
2026-01-29 02:37:52.820 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.28.20:5700/3) Recv SETFORMAT cmd
2026-01-29 02:37:52.820 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.28.20:5700/3) TRXD header version 1 -> 1
2026-01-29 02:37:52.824 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.28.20:5700) Recv RXTUNE cmd
2026-01-29 02:37:52.824 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETTSC
2026-01-29 02:37:52.824 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETTSC
2026-01-29 02:37:52.824 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETTSC
2026-01-29 02:37:52.824 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.28.20:5700) Recv TXTUNE cmd
2026-01-29 02:37:52.824 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETRXGAIN
2026-01-29 02:37:52.824 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETRXGAIN
2026-01-29 02:37:52.824 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETRXGAIN
2026-01-29 02:37:52.824 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETTSC
2026-01-29 02:37:52.824 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:37:52.824 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:37:52.824 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.28.20:5700) Recv NOMTXPOWER cmd
2026-01-29 02:37:52.824 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:37:52.824 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:37:52.825 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:37:52.825 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.28.20:5700) Recv POWERON CMD
2026-01-29 02:37:52.825 [INFO] ctrl_if_trx.py:109 (BTS@172.18.28.20:5700) Starting transceiver...
2026-01-29 02:37:52.825 [INFO] transceiver.py:243 Starting clock generator
2026-01-29 02:37:52.825 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-01-29 02:37:52.825 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:37:52.825 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:37:52.825 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:37:52.825 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETRXGAIN
2026-01-29 02:37:52.825 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:37:52.825 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:37:52.825 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:37:52.825 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:37:52.825 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:37:52.825 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:37:52.825 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:37:52.826 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:37:52.826 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:37:52.826 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:37:52.826 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:37:52.826 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:37:52.826 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:37:52.826 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:37:52.826 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:37:52.826 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:37:52.826 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:37:52.827 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:37:52.827 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:37:52.827 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:37:52.827 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:37:52.827 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:37:52.827 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:37:52.827 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:37:52.830 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-01-29 02:37:53.312 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-01-29 02:37:53.347 [DEBUG] fake_trx.py:278 (BTS@172.18.28.20:5700) Recv FAKE_TOA cmd
2026-01-29 02:37:53.349 [DEBUG] fake_trx.py:297 (BTS@172.18.28.20:5700) Recv FAKE_RSSI cmd
2026-01-29 02:37:53.350 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:37:53.351 [DEBUG] fake_trx.py:322 (BTS@172.18.28.20:5700) Recv FAKE_CI cmd
2026-01-29 02:37:53.369 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 02:37:53.369 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 02:37:53.369 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 02:37:53.371 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:37:53.371 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 02:37:53.371 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 02:37:53.371 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.28.22:6700) Recv POWERON CMD
2026-01-29 02:37:53.371 [INFO] ctrl_if_trx.py:109 (MS@172.18.28.22:6700) Starting transceiver...
2026-01-29 02:37:53.405 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD HANDOVER
2026-01-29 02:37:53.409 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 02:37:53.409 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 02:37:53.409 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:37:53.409 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:37:53.469 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:37:53.527 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:37:53.527 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 02:37:53.527 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 02:37:53.527 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 02:37:53.528 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:37:53.528 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 02:37:53.528 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 02:37:53.528 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.28.22:6700) Recv POWERON CMD
2026-01-29 02:37:53.528 [INFO] ctrl_if_trx.py:109 (MS@172.18.28.22:6700) Starting transceiver...
2026-01-29 02:37:53.784 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-01-29 02:37:53.829 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 02:37:53.829 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:37:53.830 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:37:53.834 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:37:54.262 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-01-29 02:37:54.739 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-01-29 02:37:54.830 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 02:37:54.830 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:37:54.831 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:37:54.834 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:37:55.217 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-01-29 02:37:55.695 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-01-29 02:37:55.830 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 02:37:55.831 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:37:55.832 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:37:55.836 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:37:56.172 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-01-29 02:37:56.650 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-01-29 02:37:56.831 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 02:37:56.832 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:37:56.834 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:37:56.836 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:37:57.128 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-01-29 02:37:57.605 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-01-29 02:37:57.832 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 02:37:57.832 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:37:57.835 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:37:57.837 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:37:58.083 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-01-29 02:37:58.560 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-01-29 02:37:59.038 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-01-29 02:37:59.516 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-01-29 02:37:59.993 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-01-29 02:38:00.471 [DEBUG] clck_gen.py:113 IND CLOCK 1632
2026-01-29 02:38:00.949 [DEBUG] clck_gen.py:113 IND CLOCK 1734
2026-01-29 02:38:01.426 [DEBUG] clck_gen.py:113 IND CLOCK 1836
2026-01-29 02:38:01.904 [DEBUG] clck_gen.py:113 IND CLOCK 1938
2026-01-29 02:38:02.382 [DEBUG] clck_gen.py:113 IND CLOCK 2040
2026-01-29 02:38:02.859 [DEBUG] clck_gen.py:113 IND CLOCK 2142
2026-01-29 02:38:03.337 [DEBUG] clck_gen.py:113 IND CLOCK 2244
2026-01-29 02:38:03.815 [DEBUG] clck_gen.py:113 IND CLOCK 2346
2026-01-29 02:38:04.292 [DEBUG] clck_gen.py:113 IND CLOCK 2448
2026-01-29 02:38:04.770 [DEBUG] clck_gen.py:113 IND CLOCK 2550
2026-01-29 02:38:05.248 [DEBUG] clck_gen.py:113 IND CLOCK 2652
2026-01-29 02:38:05.725 [DEBUG] clck_gen.py:113 IND CLOCK 2754
2026-01-29 02:38:06.203 [DEBUG] clck_gen.py:113 IND CLOCK 2856
2026-01-29 02:38:06.680 [DEBUG] clck_gen.py:113 IND CLOCK 2958
2026-01-29 02:38:07.158 [DEBUG] clck_gen.py:113 IND CLOCK 3060
2026-01-29 02:38:07.635 [DEBUG] clck_gen.py:113 IND CLOCK 3162
2026-01-29 02:38:08.113 [DEBUG] clck_gen.py:113 IND CLOCK 3264
2026-01-29 02:38:08.588 [DEBUG] clck_gen.py:113 IND CLOCK 3366
2026-01-29 02:38:08.880 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:38:08.881 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 02:38:08.881 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 02:38:08.881 [WARNING] transceiver.py:257 (MS@172.18.28.22:6700) RX TRXD message (fn=3432 tn=6 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:38:08.881 [WARNING] transceiver.py:257 (MS@172.18.28.22:6700) RX TRXD message (fn=3432 tn=7 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:38:08.881 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 02:38:08.889 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:38:08.889 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 02:38:08.889 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 02:38:08.889 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.28.22:6700) Recv POWERON CMD
2026-01-29 02:38:08.889 [INFO] ctrl_if_trx.py:109 (MS@172.18.28.22:6700) Starting transceiver...
2026-01-29 02:38:08.910 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:38:08.913 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 02:38:08.913 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 02:38:08.922 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 02:38:08.922 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:38:08.923 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:38:08.923 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:38:08.925 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 02:38:08.925 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:38:08.925 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:38:08.925 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:38:08.925 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.28.20:5700) Recv POWEROFF cmd
2026-01-29 02:38:08.925 [INFO] ctrl_if_trx.py:117 (BTS@172.18.28.20:5700) Stopping transceiver...
2026-01-29 02:38:08.925 [INFO] transceiver.py:246 Stopping clock generator
2026-01-29 02:38:08.925 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=3441 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:38:08.925 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=3441 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:38:08.925 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=3441 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:38:08.925 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=3441 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:38:08.925 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=3441 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:38:08.925 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=3441 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:38:08.925 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=3441 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:38:08.925 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=3442 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:38:08.925 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=3442 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:38:13.925 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.28.20:5700) Recv POWEROFF cmd
2026-01-29 02:38:13.926 [INFO] ctrl_if_trx.py:117 (BTS@172.18.28.20:5700) Stopping transceiver...
2026-01-29 02:38:13.927 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:38:13.929 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:38:13.930 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:38:13.933 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 02:38:13.946 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 02:38:13.947 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.28.20:5700) Recv SETFORMAT cmd
2026-01-29 02:38:13.947 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.28.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:38:13.948 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.28.20:5700) Recv SETFORMAT cmd
2026-01-29 02:38:13.948 [INFO] ctrl_if_trx.py:201 (BTS@172.18.28.20:5700) TRXD header version 1 -> 1
2026-01-29 02:38:13.951 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.28.20:5700/1) Recv RXTUNE cmd
2026-01-29 02:38:13.951 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.28.20:5700/1) Recv TXTUNE cmd
2026-01-29 02:38:13.951 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.28.20:5700/1) Recv SETFORMAT cmd
2026-01-29 02:38:13.951 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.28.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:38:13.952 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:38:13.952 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.28.20:5700/1) Recv NOMTXPOWER cmd
2026-01-29 02:38:13.952 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.28.20:5700/1) Recv SETFORMAT cmd
2026-01-29 02:38:13.953 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.28.20:5700/1) TRXD header version 1 -> 1
2026-01-29 02:38:13.953 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.28.20:5700/2) Recv RXTUNE cmd
2026-01-29 02:38:13.953 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.28.20:5700/2) Recv TXTUNE cmd
2026-01-29 02:38:13.953 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.28.20:5700/2) Recv SETFORMAT cmd
2026-01-29 02:38:13.953 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.28.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:38:13.954 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:38:13.954 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.28.20:5700/2) Recv NOMTXPOWER cmd
2026-01-29 02:38:13.954 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.28.20:5700/2) Recv SETFORMAT cmd
2026-01-29 02:38:13.954 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.28.20:5700/2) TRXD header version 1 -> 1
2026-01-29 02:38:13.956 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.28.20:5700/3) Recv RXTUNE cmd
2026-01-29 02:38:13.956 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.28.20:5700/3) Recv TXTUNE cmd
2026-01-29 02:38:13.956 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.28.20:5700/3) Recv SETFORMAT cmd
2026-01-29 02:38:13.956 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.28.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:38:13.956 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:38:13.956 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.28.20:5700/3) Recv NOMTXPOWER cmd
2026-01-29 02:38:13.956 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.28.20:5700/3) Recv SETFORMAT cmd
2026-01-29 02:38:13.956 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.28.20:5700/3) TRXD header version 1 -> 1
2026-01-29 02:38:13.958 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.28.20:5700) Recv RXTUNE cmd
2026-01-29 02:38:13.958 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETTSC
2026-01-29 02:38:13.958 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETTSC
2026-01-29 02:38:13.958 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETTSC
2026-01-29 02:38:13.958 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.28.20:5700) Recv TXTUNE cmd
2026-01-29 02:38:13.959 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETRXGAIN
2026-01-29 02:38:13.959 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETRXGAIN
2026-01-29 02:38:13.959 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETRXGAIN
2026-01-29 02:38:13.959 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETTSC
2026-01-29 02:38:13.959 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:38:13.959 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:38:13.959 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:38:13.959 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.28.20:5700) Recv NOMTXPOWER cmd
2026-01-29 02:38:13.959 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:38:13.959 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:38:13.959 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:38:13.959 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.28.20:5700) Recv POWERON CMD
2026-01-29 02:38:13.959 [INFO] ctrl_if_trx.py:109 (BTS@172.18.28.20:5700) Starting transceiver...
2026-01-29 02:38:13.959 [INFO] transceiver.py:243 Starting clock generator
2026-01-29 02:38:13.959 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-01-29 02:38:13.959 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:38:13.959 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:38:13.959 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:38:13.959 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETRXGAIN
2026-01-29 02:38:13.959 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:38:13.959 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:38:13.959 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:38:13.959 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:38:13.959 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:38:13.960 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:38:13.960 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:38:13.960 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:38:13.960 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:38:13.960 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:38:13.960 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:38:13.960 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:38:13.960 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:38:13.960 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:38:13.960 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:38:13.960 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:38:13.960 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:38:13.960 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:38:13.960 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:38:13.960 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:38:13.960 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:38:13.960 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:38:13.960 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:38:13.964 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-01-29 02:38:14.443 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-01-29 02:38:14.485 [DEBUG] fake_trx.py:278 (BTS@172.18.28.20:5700) Recv FAKE_TOA cmd
2026-01-29 02:38:14.487 [DEBUG] fake_trx.py:297 (BTS@172.18.28.20:5700) Recv FAKE_RSSI cmd
2026-01-29 02:38:14.489 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:38:14.489 [DEBUG] fake_trx.py:322 (BTS@172.18.28.20:5700) Recv FAKE_CI cmd
2026-01-29 02:38:14.514 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 02:38:14.514 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 02:38:14.514 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 02:38:14.519 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:38:14.519 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 02:38:14.519 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 02:38:14.519 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.28.22:6700) Recv POWERON CMD
2026-01-29 02:38:14.519 [INFO] ctrl_if_trx.py:109 (MS@172.18.28.22:6700) Starting transceiver...
2026-01-29 02:38:14.539 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD HANDOVER
2026-01-29 02:38:14.544 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 02:38:14.545 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 02:38:14.545 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:38:14.546 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:38:14.601 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:38:14.761 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD HANDOVER
2026-01-29 02:38:14.837 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:38:14.838 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 02:38:14.838 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 02:38:14.838 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 02:38:14.838 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:38:14.839 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 02:38:14.839 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 02:38:14.839 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.28.22:6700) Recv POWERON CMD
2026-01-29 02:38:14.839 [INFO] ctrl_if_trx.py:109 (MS@172.18.28.22:6700) Starting transceiver...
2026-01-29 02:38:14.861 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:38:14.885 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 02:38:14.885 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 02:38:14.888 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 02:38:14.888 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:38:14.888 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:38:14.888 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:38:14.891 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 02:38:14.891 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:38:14.891 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:38:14.891 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:38:14.891 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.28.20:5700) Recv POWEROFF cmd
2026-01-29 02:38:14.891 [INFO] ctrl_if_trx.py:117 (BTS@172.18.28.20:5700) Stopping transceiver...
2026-01-29 02:38:14.891 [INFO] transceiver.py:246 Stopping clock generator
2026-01-29 02:38:14.892 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=200 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:38:14.892 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=200 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:38:14.892 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=200 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:38:14.892 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=200 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:38:14.892 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=200 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:38:14.892 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=200 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:38:14.892 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=201 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:38:14.892 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=201 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:38:14.892 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=201 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:38:14.892 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=201 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:38:14.892 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=201 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:38:14.892 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=201 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:38:14.892 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=201 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:38:14.892 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=201 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:38:19.909 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.28.20:5700) Recv POWEROFF cmd
2026-01-29 02:38:19.909 [INFO] ctrl_if_trx.py:117 (BTS@172.18.28.20:5700) Stopping transceiver...
2026-01-29 02:38:19.910 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:38:19.912 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:38:19.912 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:38:19.912 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 02:38:19.919 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 02:38:19.920 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.28.20:5700) Recv SETFORMAT cmd
2026-01-29 02:38:19.920 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.28.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:38:19.921 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.28.20:5700) Recv SETFORMAT cmd
2026-01-29 02:38:19.921 [INFO] ctrl_if_trx.py:201 (BTS@172.18.28.20:5700) TRXD header version 1 -> 1
2026-01-29 02:38:19.923 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.28.20:5700/1) Recv RXTUNE cmd
2026-01-29 02:38:19.924 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.28.20:5700/1) Recv TXTUNE cmd
2026-01-29 02:38:19.924 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.28.20:5700/1) Recv SETFORMAT cmd
2026-01-29 02:38:19.924 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.28.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:38:19.924 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:38:19.925 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.28.20:5700/1) Recv NOMTXPOWER cmd
2026-01-29 02:38:19.925 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.28.20:5700/1) Recv SETFORMAT cmd
2026-01-29 02:38:19.925 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.28.20:5700/1) TRXD header version 1 -> 1
2026-01-29 02:38:19.926 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.28.20:5700/2) Recv RXTUNE cmd
2026-01-29 02:38:19.926 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.28.20:5700/2) Recv TXTUNE cmd
2026-01-29 02:38:19.927 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.28.20:5700/2) Recv SETFORMAT cmd
2026-01-29 02:38:19.927 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.28.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:38:19.927 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:38:19.927 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.28.20:5700/2) Recv NOMTXPOWER cmd
2026-01-29 02:38:19.927 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.28.20:5700/2) Recv SETFORMAT cmd
2026-01-29 02:38:19.927 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.28.20:5700/2) TRXD header version 1 -> 1
2026-01-29 02:38:19.929 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.28.20:5700/3) Recv RXTUNE cmd
2026-01-29 02:38:19.929 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.28.20:5700/3) Recv TXTUNE cmd
2026-01-29 02:38:19.929 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.28.20:5700/3) Recv SETFORMAT cmd
2026-01-29 02:38:19.929 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.28.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:38:19.929 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:38:19.929 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.28.20:5700/3) Recv NOMTXPOWER cmd
2026-01-29 02:38:19.929 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.28.20:5700/3) Recv SETFORMAT cmd
2026-01-29 02:38:19.929 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.28.20:5700/3) TRXD header version 1 -> 1
2026-01-29 02:38:19.931 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.28.20:5700) Recv RXTUNE cmd
2026-01-29 02:38:19.931 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETTSC
2026-01-29 02:38:19.931 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETTSC
2026-01-29 02:38:19.931 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETTSC
2026-01-29 02:38:19.931 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.28.20:5700) Recv TXTUNE cmd
2026-01-29 02:38:19.931 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETRXGAIN
2026-01-29 02:38:19.931 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETRXGAIN
2026-01-29 02:38:19.931 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETRXGAIN
2026-01-29 02:38:19.931 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETTSC
2026-01-29 02:38:19.931 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:38:19.931 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:38:19.931 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:38:19.931 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.28.20:5700) Recv NOMTXPOWER cmd
2026-01-29 02:38:19.931 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:38:19.931 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:38:19.932 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:38:19.932 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.28.20:5700) Recv POWERON CMD
2026-01-29 02:38:19.932 [INFO] ctrl_if_trx.py:109 (BTS@172.18.28.20:5700) Starting transceiver...
2026-01-29 02:38:19.932 [INFO] transceiver.py:243 Starting clock generator
2026-01-29 02:38:19.932 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-01-29 02:38:19.932 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:38:19.932 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:38:19.932 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:38:19.932 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETRXGAIN
2026-01-29 02:38:19.932 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:38:19.932 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:38:19.932 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:38:19.932 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:38:19.932 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:38:19.932 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:38:19.932 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:38:19.932 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:38:19.932 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:38:19.932 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:38:19.932 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:38:19.932 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:38:19.932 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:38:19.932 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:38:19.932 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:38:19.932 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:38:19.932 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:38:19.932 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:38:19.932 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:38:19.932 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:38:19.932 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:38:19.933 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:38:19.933 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:38:19.936 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-01-29 02:38:20.417 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-01-29 02:38:20.456 [DEBUG] fake_trx.py:278 (BTS@172.18.28.20:5700) Recv FAKE_TOA cmd
2026-01-29 02:38:20.459 [DEBUG] fake_trx.py:297 (BTS@172.18.28.20:5700) Recv FAKE_RSSI cmd
2026-01-29 02:38:20.460 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:38:20.461 [DEBUG] fake_trx.py:322 (BTS@172.18.28.20:5700) Recv FAKE_CI cmd
2026-01-29 02:38:20.477 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 02:38:20.477 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 02:38:20.477 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 02:38:20.481 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:38:20.481 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 02:38:20.482 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 02:38:20.482 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.28.22:6700) Recv POWERON CMD
2026-01-29 02:38:20.482 [INFO] ctrl_if_trx.py:109 (MS@172.18.28.22:6700) Starting transceiver...
2026-01-29 02:38:20.513 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD HANDOVER
2026-01-29 02:38:20.519 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 02:38:20.519 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 02:38:20.519 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:38:20.520 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:38:20.895 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-01-29 02:38:20.934 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:38:20.935 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 02:38:20.935 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:38:20.937 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:38:21.373 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-01-29 02:38:21.850 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-01-29 02:38:21.936 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 02:38:21.936 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:38:21.936 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:38:21.938 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:38:22.328 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-01-29 02:38:22.526 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:38:22.526 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 02:38:22.526 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 02:38:22.527 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 02:38:22.545 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:38:22.545 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 02:38:22.545 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 02:38:22.545 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.28.22:6700) Recv POWERON CMD
2026-01-29 02:38:22.545 [INFO] ctrl_if_trx.py:109 (MS@172.18.28.22:6700) Starting transceiver...
2026-01-29 02:38:22.562 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:38:22.565 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 02:38:22.565 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 02:38:22.575 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 02:38:22.575 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:38:22.575 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:38:22.575 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:38:22.576 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 02:38:22.576 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:38:22.576 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:38:22.576 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:38:22.577 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.28.20:5700) Recv POWEROFF cmd
2026-01-29 02:38:22.577 [INFO] ctrl_if_trx.py:117 (BTS@172.18.28.20:5700) Stopping transceiver...
2026-01-29 02:38:22.577 [INFO] transceiver.py:246 Stopping clock generator
2026-01-29 02:38:22.577 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=565 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:38:22.577 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=565 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:38:22.577 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=565 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:38:22.577 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=565 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:38:22.577 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=565 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:38:22.577 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=565 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:38:27.578 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.28.20:5700) Recv POWEROFF cmd
2026-01-29 02:38:27.578 [INFO] ctrl_if_trx.py:117 (BTS@172.18.28.20:5700) Stopping transceiver...
2026-01-29 02:38:27.578 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:38:27.579 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:38:27.580 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:38:27.581 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 02:38:27.583 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 02:38:27.583 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.28.20:5700) Recv SETFORMAT cmd
2026-01-29 02:38:27.583 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.28.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:38:27.583 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.28.20:5700) Recv SETFORMAT cmd
2026-01-29 02:38:27.583 [INFO] ctrl_if_trx.py:201 (BTS@172.18.28.20:5700) TRXD header version 1 -> 1
2026-01-29 02:38:27.584 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.28.20:5700/1) Recv RXTUNE cmd
2026-01-29 02:38:27.584 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.28.20:5700/1) Recv TXTUNE cmd
2026-01-29 02:38:27.584 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.28.20:5700/1) Recv SETFORMAT cmd
2026-01-29 02:38:27.584 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.28.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:38:27.584 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:38:27.584 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.28.20:5700/1) Recv NOMTXPOWER cmd
2026-01-29 02:38:27.584 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.28.20:5700/1) Recv SETFORMAT cmd
2026-01-29 02:38:27.584 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.28.20:5700/1) TRXD header version 1 -> 1
2026-01-29 02:38:27.585 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.28.20:5700/2) Recv RXTUNE cmd
2026-01-29 02:38:27.585 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.28.20:5700/2) Recv TXTUNE cmd
2026-01-29 02:38:27.585 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.28.20:5700/2) Recv SETFORMAT cmd
2026-01-29 02:38:27.585 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.28.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:38:27.585 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:38:27.585 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.28.20:5700/2) Recv NOMTXPOWER cmd
2026-01-29 02:38:27.585 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.28.20:5700/2) Recv SETFORMAT cmd
2026-01-29 02:38:27.585 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.28.20:5700/2) TRXD header version 1 -> 1
2026-01-29 02:38:27.586 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.28.20:5700/3) Recv RXTUNE cmd
2026-01-29 02:38:27.586 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.28.20:5700/3) Recv TXTUNE cmd
2026-01-29 02:38:27.586 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.28.20:5700/3) Recv SETFORMAT cmd
2026-01-29 02:38:27.586 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.28.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:38:27.586 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:38:27.586 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.28.20:5700/3) Recv NOMTXPOWER cmd
2026-01-29 02:38:27.586 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.28.20:5700/3) Recv SETFORMAT cmd
2026-01-29 02:38:27.586 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.28.20:5700/3) TRXD header version 1 -> 1
2026-01-29 02:38:27.587 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.28.20:5700) Recv RXTUNE cmd
2026-01-29 02:38:27.587 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETTSC
2026-01-29 02:38:27.587 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETTSC
2026-01-29 02:38:27.587 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETTSC
2026-01-29 02:38:27.587 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.28.20:5700) Recv TXTUNE cmd
2026-01-29 02:38:27.587 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETRXGAIN
2026-01-29 02:38:27.587 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETRXGAIN
2026-01-29 02:38:27.587 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETRXGAIN
2026-01-29 02:38:27.587 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETTSC
2026-01-29 02:38:27.587 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:38:27.587 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:38:27.587 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:38:27.587 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.28.20:5700) Recv NOMTXPOWER cmd
2026-01-29 02:38:27.587 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:38:27.587 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:38:27.587 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:38:27.587 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.28.20:5700) Recv POWERON CMD
2026-01-29 02:38:27.587 [INFO] ctrl_if_trx.py:109 (BTS@172.18.28.20:5700) Starting transceiver...
2026-01-29 02:38:27.587 [INFO] transceiver.py:243 Starting clock generator
2026-01-29 02:38:27.587 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-01-29 02:38:27.587 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:38:27.588 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:38:27.588 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:38:27.588 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETRXGAIN
2026-01-29 02:38:27.588 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:38:27.588 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:38:27.588 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:38:27.588 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:38:27.588 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:38:27.588 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:38:27.588 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:38:27.588 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:38:27.588 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:38:27.588 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:38:27.588 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:38:27.589 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:38:27.589 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:38:27.589 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:38:27.589 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:38:27.589 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:38:27.589 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:38:27.589 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:38:27.589 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:38:27.589 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:38:27.589 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:38:27.589 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:38:27.589 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:38:27.589 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:38:27.589 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:38:27.589 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 02:38:27.589 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:38:27.589 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.28.20:5700) Recv POWEROFF cmd
2026-01-29 02:38:27.589 [INFO] ctrl_if_trx.py:117 (BTS@172.18.28.20:5700) Stopping transceiver...
2026-01-29 02:38:27.589 [INFO] transceiver.py:246 Stopping clock generator
2026-01-29 02:38:32.590 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.28.20:5700) Recv POWEROFF cmd
2026-01-29 02:38:32.590 [INFO] ctrl_if_trx.py:117 (BTS@172.18.28.20:5700) Stopping transceiver...
2026-01-29 02:38:32.590 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:38:32.590 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:38:32.591 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:38:32.591 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 02:38:32.593 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 02:38:32.593 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.28.20:5700) Recv SETFORMAT cmd
2026-01-29 02:38:32.593 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.28.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:38:32.593 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.28.20:5700) Recv SETFORMAT cmd
2026-01-29 02:38:32.593 [INFO] ctrl_if_trx.py:201 (BTS@172.18.28.20:5700) TRXD header version 1 -> 1
2026-01-29 02:38:32.594 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.28.20:5700/1) Recv RXTUNE cmd
2026-01-29 02:38:32.594 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.28.20:5700/1) Recv TXTUNE cmd
2026-01-29 02:38:32.594 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.28.20:5700/1) Recv SETFORMAT cmd
2026-01-29 02:38:32.594 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.28.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:38:32.594 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:38:32.594 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.28.20:5700/1) Recv NOMTXPOWER cmd
2026-01-29 02:38:32.594 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.28.20:5700/1) Recv SETFORMAT cmd
2026-01-29 02:38:32.594 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.28.20:5700/1) TRXD header version 1 -> 1
2026-01-29 02:38:32.595 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.28.20:5700/2) Recv RXTUNE cmd
2026-01-29 02:38:32.595 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.28.20:5700/2) Recv TXTUNE cmd
2026-01-29 02:38:32.595 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.28.20:5700/2) Recv SETFORMAT cmd
2026-01-29 02:38:32.595 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.28.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:38:32.595 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:38:32.595 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.28.20:5700/2) Recv NOMTXPOWER cmd
2026-01-29 02:38:32.595 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.28.20:5700/2) Recv SETFORMAT cmd
2026-01-29 02:38:32.595 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.28.20:5700/2) TRXD header version 1 -> 1
2026-01-29 02:38:32.596 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.28.20:5700/3) Recv RXTUNE cmd
2026-01-29 02:38:32.596 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.28.20:5700/3) Recv TXTUNE cmd
2026-01-29 02:38:32.596 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.28.20:5700/3) Recv SETFORMAT cmd
2026-01-29 02:38:32.596 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.28.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:38:32.596 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:38:32.596 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.28.20:5700/3) Recv NOMTXPOWER cmd
2026-01-29 02:38:32.596 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.28.20:5700/3) Recv SETFORMAT cmd
2026-01-29 02:38:32.596 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.28.20:5700/3) TRXD header version 1 -> 1
2026-01-29 02:38:32.597 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.28.20:5700) Recv RXTUNE cmd
2026-01-29 02:38:32.597 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETTSC
2026-01-29 02:38:32.597 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETTSC
2026-01-29 02:38:32.597 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETTSC
2026-01-29 02:38:32.597 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.28.20:5700) Recv TXTUNE cmd
2026-01-29 02:38:32.597 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETRXGAIN
2026-01-29 02:38:32.597 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETRXGAIN
2026-01-29 02:38:32.597 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETRXGAIN
2026-01-29 02:38:32.597 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETTSC
2026-01-29 02:38:32.597 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:38:32.597 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:38:32.597 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:38:32.597 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.28.20:5700) Recv NOMTXPOWER cmd
2026-01-29 02:38:32.597 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:38:32.597 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:38:32.597 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:38:32.597 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.28.20:5700) Recv POWERON CMD
2026-01-29 02:38:32.597 [INFO] ctrl_if_trx.py:109 (BTS@172.18.28.20:5700) Starting transceiver...
2026-01-29 02:38:32.597 [INFO] transceiver.py:243 Starting clock generator
2026-01-29 02:38:32.597 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-01-29 02:38:32.597 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:38:32.597 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:38:32.597 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:38:32.597 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETRXGAIN
2026-01-29 02:38:32.597 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:38:32.598 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:38:32.598 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:38:32.598 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:38:32.598 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:38:32.598 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:38:32.598 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:38:32.598 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:38:32.598 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:38:32.598 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:38:32.598 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:38:32.598 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:38:32.598 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:38:32.598 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:38:32.598 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:38:32.598 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:38:32.598 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:38:32.598 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:38:32.598 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:38:32.598 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:38:32.599 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:38:32.599 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:38:32.599 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:38:32.599 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:38:32.599 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:38:32.599 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:38:32.599 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 02:38:32.599 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.28.20:5700) Recv POWEROFF cmd
2026-01-29 02:38:32.599 [INFO] ctrl_if_trx.py:117 (BTS@172.18.28.20:5700) Stopping transceiver...
2026-01-29 02:38:32.599 [INFO] transceiver.py:246 Stopping clock generator
2026-01-29 02:38:36.850 [INFO] transceiver.py:125 Init transceiver 'BTS@172.18.28.20:5700'
2026-01-29 02:38:36.850 [DEBUG] data_if.py:31 Init TRXD interface (L:0.0.0.0:5702 <-> R:172.18.28.20:5802)
2026-01-29 02:38:36.850 [DEBUG] ctrl_if.py:29 Init TRXC interface (L:0.0.0.0:5701 <-> R:172.18.28.20:5801)
2026-01-29 02:38:36.850 [INFO] transceiver.py:125 Init transceiver 'MS@172.18.28.22:6700'
2026-01-29 02:38:36.850 [DEBUG] data_if.py:31 Init TRXD interface (L:0.0.0.0:6702 <-> R:172.18.28.22:6802)
2026-01-29 02:38:36.850 [DEBUG] ctrl_if.py:29 Init TRXC interface (L:0.0.0.0:6701 <-> R:172.18.28.22:6801)
2026-01-29 02:38:36.850 [INFO] transceiver.py:125 Init transceiver 'TRX1@172.18.28.20:5700/1'
2026-01-29 02:38:36.850 [DEBUG] data_if.py:31 Init TRXD interface (L:0.0.0.0:5704 <-> R:172.18.28.20:5804)
2026-01-29 02:38:36.850 [DEBUG] ctrl_if.py:29 Init TRXC interface (L:0.0.0.0:5703 <-> R:172.18.28.20:5803)
2026-01-29 02:38:36.850 [INFO] transceiver.py:125 Init transceiver 'TRX2@172.18.28.20:5700/2'
2026-01-29 02:38:36.850 [DEBUG] data_if.py:31 Init TRXD interface (L:0.0.0.0:5706 <-> R:172.18.28.20:5806)
2026-01-29 02:38:36.850 [DEBUG] ctrl_if.py:29 Init TRXC interface (L:0.0.0.0:5705 <-> R:172.18.28.20:5805)
2026-01-29 02:38:36.850 [INFO] transceiver.py:125 Init transceiver 'TRX3@172.18.28.20:5700/3'
2026-01-29 02:38:36.850 [DEBUG] data_if.py:31 Init TRXD interface (L:0.0.0.0:5708 <-> R:172.18.28.20:5808)
2026-01-29 02:38:36.850 [DEBUG] ctrl_if.py:29 Init TRXC interface (L:0.0.0.0:5707 <-> R:172.18.28.20:5807)
2026-01-29 02:38:36.850 [INFO] fake_trx.py:429 Init complete
2026-01-29 02:38:36.850 [INFO] fake_trx.py:460 Setting real time process scheduler to SCHED_RR, priority 30
2026-01-29 02:38:38.434 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:38:38.435 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.28.20:5700) Recv POWEROFF cmd
2026-01-29 02:38:38.435 [INFO] ctrl_if_trx.py:117 (BTS@172.18.28.20:5700) Stopping transceiver...
2026-01-29 02:38:38.435 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:38:38.436 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 02:38:38.436 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:38:49.524 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:38:49.525 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 02:38:49.525 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:38:49.525 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:38:54.534 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.28.20:5700) Recv POWEROFF cmd
2026-01-29 02:38:54.534 [INFO] ctrl_if_trx.py:117 (BTS@172.18.28.20:5700) Stopping transceiver...
2026-01-29 02:38:54.535 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:38:54.535 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:38:54.535 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:38:54.536 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 02:38:54.546 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:38:54.546 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 02:38:54.546 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:38:54.546 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:38:59.574 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.28.20:5700) Recv POWEROFF cmd
2026-01-29 02:38:59.574 [INFO] ctrl_if_trx.py:117 (BTS@172.18.28.20:5700) Stopping transceiver...
2026-01-29 02:38:59.574 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:38:59.577 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:38:59.577 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:38:59.577 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 02:38:59.600 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:38:59.600 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 02:38:59.600 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:38:59.600 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:39:04.628 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.28.20:5700) Recv POWEROFF cmd
2026-01-29 02:39:04.628 [INFO] ctrl_if_trx.py:117 (BTS@172.18.28.20:5700) Stopping transceiver...
2026-01-29 02:39:04.629 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:39:04.629 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:39:04.630 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:39:04.632 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 02:39:04.652 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:39:04.652 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 02:39:04.652 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:39:04.652 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:39:09.660 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.28.20:5700) Recv POWEROFF cmd
2026-01-29 02:39:09.660 [INFO] ctrl_if_trx.py:117 (BTS@172.18.28.20:5700) Stopping transceiver...
2026-01-29 02:39:09.660 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:39:09.660 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:39:09.661 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:39:09.664 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 02:39:09.687 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:39:09.687 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 02:39:09.687 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:39:09.687 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:39:14.700 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.28.20:5700) Recv POWEROFF cmd
2026-01-29 02:39:14.700 [INFO] ctrl_if_trx.py:117 (BTS@172.18.28.20:5700) Stopping transceiver...
2026-01-29 02:39:14.700 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:39:14.700 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:39:14.700 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:39:14.700 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 02:39:14.717 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:39:14.717 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:39:14.717 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 02:39:14.717 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:39:19.726 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.28.20:5700) Recv POWEROFF cmd
2026-01-29 02:39:19.726 [INFO] ctrl_if_trx.py:117 (BTS@172.18.28.20:5700) Stopping transceiver...
2026-01-29 02:39:19.726 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:39:19.726 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:39:19.727 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:39:19.728 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 02:39:19.749 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:39:19.749 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 02:39:19.749 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:39:19.749 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:39:24.757 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.28.20:5700) Recv POWEROFF cmd
2026-01-29 02:39:24.757 [INFO] ctrl_if_trx.py:117 (BTS@172.18.28.20:5700) Stopping transceiver...
2026-01-29 02:39:24.758 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:39:24.758 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:39:24.759 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:39:24.759 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 02:39:24.781 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:39:24.781 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 02:39:24.781 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:39:24.781 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:39:29.785 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.28.20:5700) Recv POWEROFF cmd
2026-01-29 02:39:29.785 [INFO] ctrl_if_trx.py:117 (BTS@172.18.28.20:5700) Stopping transceiver...
2026-01-29 02:39:29.786 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:39:29.789 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:39:29.790 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:39:29.790 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 02:39:29.810 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 02:39:29.811 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:39:29.811 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:39:29.811 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:39:34.819 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.28.20:5700) Recv POWEROFF cmd
2026-01-29 02:39:34.819 [INFO] ctrl_if_trx.py:117 (BTS@172.18.28.20:5700) Stopping transceiver...
2026-01-29 02:39:34.819 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:39:34.819 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:39:34.819 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:39:34.822 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 02:39:34.843 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:39:34.843 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 02:39:34.843 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:39:34.843 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:39:39.851 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.28.20:5700) Recv POWEROFF cmd
2026-01-29 02:39:39.851 [INFO] ctrl_if_trx.py:117 (BTS@172.18.28.20:5700) Stopping transceiver...
2026-01-29 02:39:39.852 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:39:39.852 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:39:39.852 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:39:39.854 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 02:39:39.876 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.28.20:5700) Recv RXTUNE cmd
2026-01-29 02:39:39.876 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETTSC
2026-01-29 02:39:39.876 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETTSC
2026-01-29 02:39:39.876 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETTSC
2026-01-29 02:39:39.876 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.28.20:5700) Recv TXTUNE cmd
2026-01-29 02:39:39.876 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.28.20:5700/1) Recv SETFORMAT cmd
2026-01-29 02:39:39.876 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.28.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:39:39.876 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.28.20:5700/2) Recv SETFORMAT cmd
2026-01-29 02:39:39.876 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.28.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:39:39.876 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.28.20:5700/3) Recv SETFORMAT cmd
2026-01-29 02:39:39.876 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.28.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:39:39.876 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.28.20:5700) Recv SETFORMAT cmd
2026-01-29 02:39:39.876 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.28.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:39:39.876 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.28.20:5700/1) Recv SETFORMAT cmd
2026-01-29 02:39:39.876 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.28.20:5700/1) TRXD header version 0 -> 1
2026-01-29 02:39:39.876 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.28.20:5700/2) Recv SETFORMAT cmd
2026-01-29 02:39:39.876 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.28.20:5700/2) TRXD header version 0 -> 1
2026-01-29 02:39:39.876 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.28.20:5700/3) Recv SETFORMAT cmd
2026-01-29 02:39:39.876 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.28.20:5700/3) TRXD header version 0 -> 1
2026-01-29 02:39:39.876 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETTSC
2026-01-29 02:39:39.876 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.28.20:5700) Recv NOMTXPOWER cmd
2026-01-29 02:39:39.876 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.28.20:5700) Recv SETFORMAT cmd
2026-01-29 02:39:39.877 [INFO] ctrl_if_trx.py:201 (BTS@172.18.28.20:5700) TRXD header version 0 -> 1
2026-01-29 02:39:39.884 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 02:39:39.884 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:39:39.884 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:39:39.884 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:39:44.893 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.28.20:5700) Recv POWEROFF cmd
2026-01-29 02:39:44.893 [INFO] ctrl_if_trx.py:117 (BTS@172.18.28.20:5700) Stopping transceiver...
2026-01-29 02:39:44.893 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:39:44.893 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:39:44.893 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:39:44.894 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 02:39:44.916 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:39:44.916 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 02:39:44.916 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:39:44.916 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:39:49.924 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.28.20:5700) Recv POWEROFF cmd
2026-01-29 02:39:49.924 [INFO] ctrl_if_trx.py:117 (BTS@172.18.28.20:5700) Stopping transceiver...
2026-01-29 02:39:49.925 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:39:49.925 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:39:49.925 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:39:49.928 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 02:39:49.928 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.28.20:5700) Recv SETFORMAT cmd
2026-01-29 02:39:49.928 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.28.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:39:49.929 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.28.20:5700) Recv SETFORMAT cmd
2026-01-29 02:39:49.929 [INFO] ctrl_if_trx.py:201 (BTS@172.18.28.20:5700) TRXD header version 1 -> 1
2026-01-29 02:39:49.951 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:39:49.951 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 02:39:49.951 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:39:49.951 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:39:54.959 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.28.20:5700) Recv POWEROFF cmd
2026-01-29 02:39:54.959 [INFO] ctrl_if_trx.py:117 (BTS@172.18.28.20:5700) Stopping transceiver...
2026-01-29 02:39:54.959 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:39:54.959 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:39:54.960 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:39:54.962 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 02:39:54.984 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 02:39:54.984 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:39:54.984 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:39:54.984 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:39:59.993 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.28.20:5700) Recv POWEROFF cmd
2026-01-29 02:39:59.993 [INFO] ctrl_if_trx.py:117 (BTS@172.18.28.20:5700) Stopping transceiver...
2026-01-29 02:39:59.993 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:39:59.994 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:39:59.994 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:39:59.997 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 02:40:00.011 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:40:00.011 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:40:00.011 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:40:00.011 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 02:40:05.019 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.28.20:5700) Recv POWEROFF cmd
2026-01-29 02:40:05.019 [INFO] ctrl_if_trx.py:117 (BTS@172.18.28.20:5700) Stopping transceiver...
2026-01-29 02:40:05.020 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:40:05.022 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:40:05.023 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:40:05.023 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 02:40:05.041 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 02:40:05.041 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:40:05.041 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:40:05.041 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:40:10.049 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.28.20:5700) Recv POWEROFF cmd
2026-01-29 02:40:10.049 [INFO] ctrl_if_trx.py:117 (BTS@172.18.28.20:5700) Stopping transceiver...
2026-01-29 02:40:10.050 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:40:10.050 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:40:10.050 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:40:10.052 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 02:40:10.074 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:40:10.074 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 02:40:10.074 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:40:10.074 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:40:16.248 [INFO] transceiver.py:125 Init transceiver 'BTS@172.18.28.20:5700'
2026-01-29 02:40:16.248 [DEBUG] data_if.py:31 Init TRXD interface (L:0.0.0.0:5702 <-> R:172.18.28.20:5802)
2026-01-29 02:40:16.248 [DEBUG] ctrl_if.py:29 Init TRXC interface (L:0.0.0.0:5701 <-> R:172.18.28.20:5801)
2026-01-29 02:40:16.248 [INFO] transceiver.py:125 Init transceiver 'MS@172.18.28.22:6700'
2026-01-29 02:40:16.248 [DEBUG] data_if.py:31 Init TRXD interface (L:0.0.0.0:6702 <-> R:172.18.28.22:6802)
2026-01-29 02:40:16.248 [DEBUG] ctrl_if.py:29 Init TRXC interface (L:0.0.0.0:6701 <-> R:172.18.28.22:6801)
2026-01-29 02:40:16.248 [INFO] transceiver.py:125 Init transceiver 'TRX1@172.18.28.20:5700/1'
2026-01-29 02:40:16.248 [DEBUG] data_if.py:31 Init TRXD interface (L:0.0.0.0:5704 <-> R:172.18.28.20:5804)
2026-01-29 02:40:16.248 [DEBUG] ctrl_if.py:29 Init TRXC interface (L:0.0.0.0:5703 <-> R:172.18.28.20:5803)
2026-01-29 02:40:16.248 [INFO] transceiver.py:125 Init transceiver 'TRX2@172.18.28.20:5700/2'
2026-01-29 02:40:16.248 [DEBUG] data_if.py:31 Init TRXD interface (L:0.0.0.0:5706 <-> R:172.18.28.20:5806)
2026-01-29 02:40:16.248 [DEBUG] ctrl_if.py:29 Init TRXC interface (L:0.0.0.0:5705 <-> R:172.18.28.20:5805)
2026-01-29 02:40:16.248 [INFO] transceiver.py:125 Init transceiver 'TRX3@172.18.28.20:5700/3'
2026-01-29 02:40:16.248 [DEBUG] data_if.py:31 Init TRXD interface (L:0.0.0.0:5708 <-> R:172.18.28.20:5808)
2026-01-29 02:40:16.248 [DEBUG] ctrl_if.py:29 Init TRXC interface (L:0.0.0.0:5707 <-> R:172.18.28.20:5807)
2026-01-29 02:40:16.248 [INFO] fake_trx.py:429 Init complete
2026-01-29 02:40:16.249 [INFO] fake_trx.py:460 Setting real time process scheduler to SCHED_RR, priority 30
2026-01-29 02:40:17.864 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.28.20:5700) Recv POWEROFF cmd
2026-01-29 02:40:17.865 [INFO] ctrl_if_trx.py:117 (BTS@172.18.28.20:5700) Stopping transceiver...
2026-01-29 02:40:17.865 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:40:17.865 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:40:17.866 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 02:40:17.866 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:40:20.880 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 02:40:20.881 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.28.20:5700) Recv SETFORMAT cmd
2026-01-29 02:40:20.882 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.28.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:40:20.882 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.28.20:5700) Recv SETFORMAT cmd
2026-01-29 02:40:20.883 [INFO] ctrl_if_trx.py:201 (BTS@172.18.28.20:5700) TRXD header version 0 -> 1
2026-01-29 02:40:20.888 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.28.20:5700/1) Recv RXTUNE cmd
2026-01-29 02:40:20.889 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.28.20:5700/1) Recv TXTUNE cmd
2026-01-29 02:40:20.889 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.28.20:5700/1) Recv SETFORMAT cmd
2026-01-29 02:40:20.889 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.28.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:40:20.890 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:40:20.890 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.28.20:5700/1) Recv NOMTXPOWER cmd
2026-01-29 02:40:20.891 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.28.20:5700/1) Recv SETFORMAT cmd
2026-01-29 02:40:20.891 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.28.20:5700/1) TRXD header version 0 -> 1
2026-01-29 02:40:20.893 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.28.20:5700/2) Recv RXTUNE cmd
2026-01-29 02:40:20.893 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.28.20:5700/2) Recv TXTUNE cmd
2026-01-29 02:40:20.893 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.28.20:5700/2) Recv SETFORMAT cmd
2026-01-29 02:40:20.893 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.28.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:40:20.893 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:40:20.893 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.28.20:5700/2) Recv NOMTXPOWER cmd
2026-01-29 02:40:20.894 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.28.20:5700/2) Recv SETFORMAT cmd
2026-01-29 02:40:20.894 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.28.20:5700/2) TRXD header version 0 -> 1
2026-01-29 02:40:20.896 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.28.20:5700/3) Recv RXTUNE cmd
2026-01-29 02:40:20.896 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.28.20:5700/3) Recv TXTUNE cmd
2026-01-29 02:40:20.897 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.28.20:5700/3) Recv SETFORMAT cmd
2026-01-29 02:40:20.897 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.28.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:40:20.897 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:40:20.897 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.28.20:5700/3) Recv NOMTXPOWER cmd
2026-01-29 02:40:20.897 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.28.20:5700/3) Recv SETFORMAT cmd
2026-01-29 02:40:20.897 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.28.20:5700/3) TRXD header version 0 -> 1
2026-01-29 02:40:20.899 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.28.20:5700) Recv RXTUNE cmd
2026-01-29 02:40:20.899 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETTSC
2026-01-29 02:40:20.899 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETTSC
2026-01-29 02:40:20.899 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETTSC
2026-01-29 02:40:20.899 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.28.20:5700) Recv TXTUNE cmd
2026-01-29 02:40:20.899 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETTSC
2026-01-29 02:40:20.899 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETRXGAIN
2026-01-29 02:40:20.899 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.28.20:5700) Recv NOMTXPOWER cmd
2026-01-29 02:40:20.899 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:40:20.899 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.28.20:5700) Recv POWERON CMD
2026-01-29 02:40:20.899 [INFO] ctrl_if_trx.py:109 (BTS@172.18.28.20:5700) Starting transceiver...
2026-01-29 02:40:20.899 [INFO] transceiver.py:243 Starting clock generator
2026-01-29 02:40:20.900 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-01-29 02:40:20.900 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:40:20.900 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETRXGAIN
2026-01-29 02:40:20.900 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETRXGAIN
2026-01-29 02:40:20.900 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETRXGAIN
2026-01-29 02:40:20.900 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:40:20.900 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:40:20.900 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:40:20.900 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:40:20.900 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:40:20.900 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:40:20.900 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:40:20.900 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:40:20.900 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:40:20.900 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:40:20.900 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:40:20.901 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:40:20.901 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:40:20.901 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:40:20.901 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:40:20.901 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:40:20.901 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:40:20.901 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:40:20.901 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:40:20.901 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:40:20.901 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:40:20.901 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:40:20.901 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:40:20.901 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:40:20.901 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:40:20.901 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:40:20.901 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:40:20.901 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:40:20.901 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:40:20.901 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:40:20.905 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-01-29 02:40:21.388 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-01-29 02:40:21.433 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:40:21.433 [DEBUG] fake_trx.py:278 (BTS@172.18.28.20:5700) Recv FAKE_TOA cmd
2026-01-29 02:40:21.438 [DEBUG] fake_trx.py:297 (BTS@172.18.28.20:5700) Recv FAKE_RSSI cmd
2026-01-29 02:40:21.439 [DEBUG] fake_trx.py:322 (BTS@172.18.28.20:5700) Recv FAKE_CI cmd
2026-01-29 02:40:21.465 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 02:40:21.465 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 02:40:21.466 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 02:40:21.471 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:40:21.471 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 02:40:21.472 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 02:40:21.472 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.28.22:6700) Recv POWERON CMD
2026-01-29 02:40:21.472 [INFO] ctrl_if_trx.py:109 (MS@172.18.28.22:6700) Starting transceiver...
2026-01-29 02:40:21.492 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:40:21.661 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 02:40:21.661 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 02:40:21.661 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:40:21.662 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:40:21.866 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-01-29 02:40:21.903 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 02:40:21.904 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:40:21.904 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:40:21.907 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:40:22.066 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:40:22.068 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:40:22.071 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 02:40:22.071 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 02:40:22.088 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 02:40:22.088 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 02:40:22.088 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 02:40:22.090 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:40:22.090 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 02:40:22.090 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 02:40:22.090 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.28.22:6700) Recv POWERON CMD
2026-01-29 02:40:22.090 [INFO] ctrl_if_trx.py:109 (MS@172.18.28.22:6700) Starting transceiver...
2026-01-29 02:40:22.115 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:40:22.164 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 02:40:22.165 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 02:40:22.165 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:40:22.165 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:40:22.343 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-01-29 02:40:22.562 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:40:22.564 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:40:22.567 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 02:40:22.567 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 02:40:22.582 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 02:40:22.582 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 02:40:22.582 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 02:40:22.583 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:40:22.583 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 02:40:22.583 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 02:40:22.583 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.28.22:6700) Recv POWERON CMD
2026-01-29 02:40:22.583 [INFO] ctrl_if_trx.py:109 (MS@172.18.28.22:6700) Starting transceiver...
2026-01-29 02:40:22.644 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:40:22.820 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-01-29 02:40:22.857 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 02:40:22.857 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 02:40:22.858 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:40:22.858 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:40:22.904 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 02:40:22.904 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:40:22.905 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:40:22.908 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:40:23.256 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:40:23.258 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:40:23.262 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 02:40:23.262 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 02:40:23.282 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 02:40:23.282 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 02:40:23.283 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 02:40:23.284 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:40:23.284 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 02:40:23.284 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 02:40:23.284 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.28.22:6700) Recv POWERON CMD
2026-01-29 02:40:23.284 [INFO] ctrl_if_trx.py:109 (MS@172.18.28.22:6700) Starting transceiver...
2026-01-29 02:40:23.298 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-01-29 02:40:23.316 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:40:23.359 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 02:40:23.359 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 02:40:23.359 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:40:23.359 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:40:23.752 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:40:23.754 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:40:23.758 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 02:40:23.758 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 02:40:23.774 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-01-29 02:40:23.777 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 02:40:23.777 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 02:40:23.777 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 02:40:23.778 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:40:23.778 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 02:40:23.778 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 02:40:23.779 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.28.22:6700) Recv POWERON CMD
2026-01-29 02:40:23.779 [INFO] ctrl_if_trx.py:109 (MS@172.18.28.22:6700) Starting transceiver...
2026-01-29 02:40:23.841 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:40:23.905 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 02:40:23.905 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:40:23.905 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:40:23.909 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:40:24.046 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 02:40:24.046 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 02:40:24.046 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:40:24.047 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:40:24.252 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-01-29 02:40:24.730 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-01-29 02:40:24.792 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:40:24.794 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:40:24.796 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 02:40:24.796 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 02:40:24.815 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 02:40:24.816 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 02:40:24.816 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 02:40:24.817 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:40:24.817 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 02:40:24.817 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 02:40:24.817 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.28.22:6700) Recv POWERON CMD
2026-01-29 02:40:24.817 [INFO] ctrl_if_trx.py:109 (MS@172.18.28.22:6700) Starting transceiver...
2026-01-29 02:40:24.824 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:40:24.906 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:40:24.906 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 02:40:24.906 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:40:24.909 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:40:25.002 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.28.22:6700) Recv SETFH cmd
2026-01-29 02:40:25.002 [INFO] transceiver.py:201 (MS@172.18.28.22:6700) Frequency hopping configured: hsn=2, maio=0, ma_len=2
2026-01-29 02:40:25.003 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:40:25.003 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:40:25.206 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-01-29 02:40:25.684 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-01-29 02:40:25.825 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:40:25.827 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:40:25.830 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 02:40:25.830 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 02:40:25.830 [INFO] transceiver.py:205 (MS@172.18.28.22:6700) Frequency hopping disabled
2026-01-29 02:40:25.843 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 02:40:25.843 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 02:40:25.843 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 02:40:25.845 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:40:25.845 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 02:40:25.845 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 02:40:25.845 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.28.22:6700) Recv POWERON CMD
2026-01-29 02:40:25.845 [INFO] ctrl_if_trx.py:109 (MS@172.18.28.22:6700) Starting transceiver...
2026-01-29 02:40:25.890 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:40:25.957 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.28.22:6700) Recv SETFH cmd
2026-01-29 02:40:25.957 [INFO] transceiver.py:201 (MS@172.18.28.22:6700) Frequency hopping configured: hsn=3, maio=3, ma_len=4
2026-01-29 02:40:25.957 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:40:25.958 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:40:26.162 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-01-29 02:40:26.372 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:40:26.375 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:40:26.378 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 02:40:26.378 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 02:40:26.378 [INFO] transceiver.py:205 (MS@172.18.28.22:6700) Frequency hopping disabled
2026-01-29 02:40:26.396 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 02:40:26.396 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 02:40:26.396 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 02:40:26.397 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:40:26.398 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 02:40:26.398 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 02:40:26.398 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.28.22:6700) Recv POWERON CMD
2026-01-29 02:40:26.398 [INFO] ctrl_if_trx.py:109 (MS@172.18.28.22:6700) Starting transceiver...
2026-01-29 02:40:26.463 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:40:26.464 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:40:26.640 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-01-29 02:40:26.676 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 02:40:26.676 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 02:40:26.677 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:40:26.677 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:40:27.119 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-01-29 02:40:27.407 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:40:27.409 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:40:27.411 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 02:40:27.412 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 02:40:27.430 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 02:40:27.430 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 02:40:27.430 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 02:40:27.432 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:40:27.432 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 02:40:27.432 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 02:40:27.432 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.28.22:6700) Recv POWERON CMD
2026-01-29 02:40:27.432 [INFO] ctrl_if_trx.py:109 (MS@172.18.28.22:6700) Starting transceiver...
2026-01-29 02:40:27.451 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:40:27.596 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-01-29 02:40:27.634 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 02:40:27.635 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 02:40:27.635 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:40:27.635 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:40:28.074 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-01-29 02:40:28.441 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:40:28.443 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:40:28.445 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 02:40:28.445 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 02:40:28.464 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 02:40:28.464 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 02:40:28.464 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 02:40:28.465 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:40:28.465 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 02:40:28.465 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 02:40:28.465 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.28.22:6700) Recv POWERON CMD
2026-01-29 02:40:28.465 [INFO] ctrl_if_trx.py:109 (MS@172.18.28.22:6700) Starting transceiver...
2026-01-29 02:40:28.517 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:40:28.517 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:40:28.552 [DEBUG] clck_gen.py:113 IND CLOCK 1632
2026-01-29 02:40:28.588 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 02:40:28.588 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 02:40:28.588 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:40:28.588 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:40:29.030 [DEBUG] clck_gen.py:113 IND CLOCK 1734
2026-01-29 02:40:29.355 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:40:29.357 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:40:29.359 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 02:40:29.359 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 02:40:29.378 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 02:40:29.378 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 02:40:29.378 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 02:40:29.379 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:40:29.379 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 02:40:29.379 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 02:40:29.379 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.28.22:6700) Recv POWERON CMD
2026-01-29 02:40:29.379 [INFO] ctrl_if_trx.py:109 (MS@172.18.28.22:6700) Starting transceiver...
2026-01-29 02:40:29.411 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:40:29.507 [DEBUG] clck_gen.py:113 IND CLOCK 1836
2026-01-29 02:40:29.543 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.28.22:6700) Recv SETFH cmd
2026-01-29 02:40:29.543 [INFO] transceiver.py:201 (MS@172.18.28.22:6700) Frequency hopping configured: hsn=5, maio=0, ma_len=4
2026-01-29 02:40:29.544 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:40:29.544 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:40:29.985 [DEBUG] clck_gen.py:113 IND CLOCK 1938
2026-01-29 02:40:30.329 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:40:30.332 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:40:30.335 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 02:40:30.335 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 02:40:30.335 [INFO] transceiver.py:205 (MS@172.18.28.22:6700) Frequency hopping disabled
2026-01-29 02:40:30.353 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 02:40:30.354 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 02:40:30.354 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 02:40:30.355 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:40:30.355 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 02:40:30.355 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 02:40:30.356 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.28.22:6700) Recv POWERON CMD
2026-01-29 02:40:30.356 [INFO] ctrl_if_trx.py:109 (MS@172.18.28.22:6700) Starting transceiver...
2026-01-29 02:40:30.427 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:40:30.464 [DEBUG] clck_gen.py:113 IND CLOCK 2040
2026-01-29 02:40:30.500 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.28.22:6700) Recv SETFH cmd
2026-01-29 02:40:30.501 [INFO] transceiver.py:201 (MS@172.18.28.22:6700) Frequency hopping configured: hsn=5, maio=0, ma_len=4
2026-01-29 02:40:30.501 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:40:30.501 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:40:30.877 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:40:30.878 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:40:30.882 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 02:40:30.882 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 02:40:30.882 [INFO] transceiver.py:205 (MS@172.18.28.22:6700) Frequency hopping disabled
2026-01-29 02:40:30.901 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 02:40:30.901 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 02:40:30.901 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 02:40:30.902 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:40:30.903 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 02:40:30.903 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 02:40:30.903 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.28.22:6700) Recv POWERON CMD
2026-01-29 02:40:30.903 [INFO] ctrl_if_trx.py:109 (MS@172.18.28.22:6700) Starting transceiver...
2026-01-29 02:40:30.942 [DEBUG] clck_gen.py:113 IND CLOCK 2142
2026-01-29 02:40:30.959 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:40:31.006 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.28.22:6700) Recv SETFH cmd
2026-01-29 02:40:31.006 [INFO] transceiver.py:201 (MS@172.18.28.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2026-01-29 02:40:31.007 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:40:31.007 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:40:31.097 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:40:31.099 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:40:31.102 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 02:40:31.102 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 02:40:31.102 [INFO] transceiver.py:205 (MS@172.18.28.22:6700) Frequency hopping disabled
2026-01-29 02:40:31.111 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 02:40:31.111 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 02:40:31.111 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 02:40:31.112 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:40:31.112 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 02:40:31.112 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 02:40:31.112 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.28.22:6700) Recv POWERON CMD
2026-01-29 02:40:31.112 [INFO] ctrl_if_trx.py:109 (MS@172.18.28.22:6700) Starting transceiver...
2026-01-29 02:40:31.150 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:40:31.214 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.28.22:6700) Recv SETFH cmd
2026-01-29 02:40:31.215 [INFO] transceiver.py:201 (MS@172.18.28.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2026-01-29 02:40:31.215 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:40:31.215 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:40:31.420 [DEBUG] clck_gen.py:113 IND CLOCK 2244
2026-01-29 02:40:31.594 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:40:31.596 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:40:31.599 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 02:40:31.599 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 02:40:31.600 [INFO] transceiver.py:205 (MS@172.18.28.22:6700) Frequency hopping disabled
2026-01-29 02:40:31.619 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 02:40:31.619 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 02:40:31.619 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 02:40:31.621 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:40:31.621 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 02:40:31.621 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 02:40:31.621 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.28.22:6700) Recv POWERON CMD
2026-01-29 02:40:31.621 [INFO] ctrl_if_trx.py:109 (MS@172.18.28.22:6700) Starting transceiver...
2026-01-29 02:40:31.673 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:40:31.720 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.28.22:6700) Recv SETFH cmd
2026-01-29 02:40:31.720 [INFO] transceiver.py:201 (MS@172.18.28.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2026-01-29 02:40:31.720 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:40:31.720 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:40:31.898 [DEBUG] clck_gen.py:113 IND CLOCK 2346
2026-01-29 02:40:32.090 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:40:32.092 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:40:32.095 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 02:40:32.095 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 02:40:32.095 [INFO] transceiver.py:205 (MS@172.18.28.22:6700) Frequency hopping disabled
2026-01-29 02:40:32.114 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 02:40:32.114 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 02:40:32.114 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 02:40:32.115 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:40:32.115 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 02:40:32.115 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 02:40:32.115 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.28.22:6700) Recv POWERON CMD
2026-01-29 02:40:32.115 [INFO] ctrl_if_trx.py:109 (MS@172.18.28.22:6700) Starting transceiver...
2026-01-29 02:40:32.151 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:40:32.198 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.28.22:6700) Recv SETFH cmd
2026-01-29 02:40:32.198 [INFO] transceiver.py:201 (MS@172.18.28.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2026-01-29 02:40:32.198 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:40:32.198 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:40:32.376 [DEBUG] clck_gen.py:113 IND CLOCK 2448
2026-01-29 02:40:32.586 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:40:32.588 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:40:32.590 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 02:40:32.590 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 02:40:32.590 [INFO] transceiver.py:205 (MS@172.18.28.22:6700) Frequency hopping disabled
2026-01-29 02:40:32.601 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 02:40:32.601 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 02:40:32.601 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 02:40:32.602 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:40:32.602 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 02:40:32.602 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 02:40:32.602 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.28.22:6700) Recv POWERON CMD
2026-01-29 02:40:32.602 [INFO] ctrl_if_trx.py:109 (MS@172.18.28.22:6700) Starting transceiver...
2026-01-29 02:40:32.629 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:40:32.676 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.28.22:6700) Recv SETFH cmd
2026-01-29 02:40:32.676 [INFO] transceiver.py:201 (MS@172.18.28.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2026-01-29 02:40:32.676 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:40:32.676 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:40:32.766 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:40:32.768 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:40:32.772 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 02:40:32.772 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 02:40:32.772 [INFO] transceiver.py:205 (MS@172.18.28.22:6700) Frequency hopping disabled
2026-01-29 02:40:32.791 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 02:40:32.791 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 02:40:32.791 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 02:40:32.792 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:40:32.793 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 02:40:32.793 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 02:40:32.793 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.28.22:6700) Recv POWERON CMD
2026-01-29 02:40:32.793 [INFO] ctrl_if_trx.py:109 (MS@172.18.28.22:6700) Starting transceiver...
2026-01-29 02:40:32.854 [DEBUG] clck_gen.py:113 IND CLOCK 2550
2026-01-29 02:40:32.873 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:40:32.918 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.28.22:6700) Recv SETFH cmd
2026-01-29 02:40:32.918 [INFO] transceiver.py:201 (MS@172.18.28.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2026-01-29 02:40:32.918 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:40:32.919 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:40:33.263 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:40:33.265 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:40:33.268 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 02:40:33.268 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 02:40:33.268 [INFO] transceiver.py:205 (MS@172.18.28.22:6700) Frequency hopping disabled
2026-01-29 02:40:33.277 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 02:40:33.277 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 02:40:33.277 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 02:40:33.278 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:40:33.279 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 02:40:33.279 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 02:40:33.279 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.28.22:6700) Recv POWERON CMD
2026-01-29 02:40:33.279 [INFO] ctrl_if_trx.py:109 (MS@172.18.28.22:6700) Starting transceiver...
2026-01-29 02:40:33.332 [DEBUG] clck_gen.py:113 IND CLOCK 2652
2026-01-29 02:40:33.352 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:40:33.396 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.28.22:6700) Recv SETFH cmd
2026-01-29 02:40:33.397 [INFO] transceiver.py:201 (MS@172.18.28.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2026-01-29 02:40:33.397 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:40:33.397 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:40:33.759 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:40:33.761 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:40:33.764 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 02:40:33.764 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 02:40:33.764 [INFO] transceiver.py:205 (MS@172.18.28.22:6700) Frequency hopping disabled
2026-01-29 02:40:33.783 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 02:40:33.783 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 02:40:33.784 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 02:40:33.785 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:40:33.785 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 02:40:33.785 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 02:40:33.785 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.28.22:6700) Recv POWERON CMD
2026-01-29 02:40:33.785 [INFO] ctrl_if_trx.py:109 (MS@172.18.28.22:6700) Starting transceiver...
2026-01-29 02:40:33.810 [DEBUG] clck_gen.py:113 IND CLOCK 2754
2026-01-29 02:40:33.828 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:40:33.874 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.28.22:6700) Recv SETFH cmd
2026-01-29 02:40:33.874 [INFO] transceiver.py:201 (MS@172.18.28.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2026-01-29 02:40:33.874 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:40:33.875 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:40:34.256 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:40:34.257 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:40:34.260 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 02:40:34.260 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 02:40:34.260 [INFO] transceiver.py:205 (MS@172.18.28.22:6700) Frequency hopping disabled
2026-01-29 02:40:34.267 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 02:40:34.267 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:40:34.267 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:40:34.267 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:40:34.268 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 02:40:34.268 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:40:34.268 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:40:34.268 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:40:34.268 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.28.20:5700) Recv POWEROFF cmd
2026-01-29 02:40:34.268 [INFO] ctrl_if_trx.py:117 (BTS@172.18.28.20:5700) Stopping transceiver...
2026-01-29 02:40:34.268 [INFO] transceiver.py:246 Stopping clock generator
2026-01-29 02:40:34.268 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=2855 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:40:34.268 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=2855 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:40:34.268 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=2855 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:40:34.268 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=2855 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:40:34.268 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=2855 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:40:34.268 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=2855 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:40:39.271 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.28.20:5700) Recv POWEROFF cmd
2026-01-29 02:40:39.272 [INFO] ctrl_if_trx.py:117 (BTS@172.18.28.20:5700) Stopping transceiver...
2026-01-29 02:40:39.273 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:40:39.275 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:40:39.275 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:40:39.275 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 02:40:39.289 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 02:40:39.289 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.28.20:5700) Recv SETFORMAT cmd
2026-01-29 02:40:39.289 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.28.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:40:39.290 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.28.20:5700) Recv SETFORMAT cmd
2026-01-29 02:40:39.290 [INFO] ctrl_if_trx.py:201 (BTS@172.18.28.20:5700) TRXD header version 1 -> 1
2026-01-29 02:40:39.291 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.28.20:5700/1) Recv RXTUNE cmd
2026-01-29 02:40:39.292 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.28.20:5700/1) Recv TXTUNE cmd
2026-01-29 02:40:39.292 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.28.20:5700/1) Recv SETFORMAT cmd
2026-01-29 02:40:39.292 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.28.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:40:39.292 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:40:39.292 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.28.20:5700/1) Recv NOMTXPOWER cmd
2026-01-29 02:40:39.293 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.28.20:5700/1) Recv SETFORMAT cmd
2026-01-29 02:40:39.293 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.28.20:5700/1) TRXD header version 1 -> 1
2026-01-29 02:40:39.294 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.28.20:5700/2) Recv RXTUNE cmd
2026-01-29 02:40:39.294 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.28.20:5700/2) Recv TXTUNE cmd
2026-01-29 02:40:39.294 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.28.20:5700/2) Recv SETFORMAT cmd
2026-01-29 02:40:39.294 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.28.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:40:39.294 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:40:39.294 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.28.20:5700/2) Recv NOMTXPOWER cmd
2026-01-29 02:40:39.294 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.28.20:5700/2) Recv SETFORMAT cmd
2026-01-29 02:40:39.294 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.28.20:5700/2) TRXD header version 1 -> 1
2026-01-29 02:40:39.295 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.28.20:5700/3) Recv RXTUNE cmd
2026-01-29 02:40:39.295 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.28.20:5700/3) Recv TXTUNE cmd
2026-01-29 02:40:39.295 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.28.20:5700/3) Recv SETFORMAT cmd
2026-01-29 02:40:39.295 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.28.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:40:39.295 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.28.20:5700/3) Recv NOMTXPOWER cmd
2026-01-29 02:40:39.295 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:40:39.295 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.28.20:5700/3) Recv SETFORMAT cmd
2026-01-29 02:40:39.295 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.28.20:5700/3) TRXD header version 1 -> 1
2026-01-29 02:40:39.297 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.28.20:5700) Recv RXTUNE cmd
2026-01-29 02:40:39.297 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETTSC
2026-01-29 02:40:39.297 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETTSC
2026-01-29 02:40:39.297 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETTSC
2026-01-29 02:40:39.297 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.28.20:5700) Recv TXTUNE cmd
2026-01-29 02:40:39.297 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETRXGAIN
2026-01-29 02:40:39.297 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETRXGAIN
2026-01-29 02:40:39.297 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETRXGAIN
2026-01-29 02:40:39.297 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETTSC
2026-01-29 02:40:39.297 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:40:39.297 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:40:39.297 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.28.20:5700) Recv NOMTXPOWER cmd
2026-01-29 02:40:39.297 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:40:39.297 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:40:39.297 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.28.20:5700) Recv POWERON CMD
2026-01-29 02:40:39.297 [INFO] ctrl_if_trx.py:109 (BTS@172.18.28.20:5700) Starting transceiver...
2026-01-29 02:40:39.297 [INFO] transceiver.py:243 Starting clock generator
2026-01-29 02:40:39.297 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-01-29 02:40:39.297 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:40:39.298 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:40:39.298 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:40:39.298 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETRXGAIN
2026-01-29 02:40:39.298 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:40:39.298 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:40:39.298 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:40:39.298 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:40:39.298 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:40:39.298 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:40:39.298 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:40:39.298 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:40:39.298 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:40:39.298 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:40:39.298 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:40:39.298 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:40:39.298 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:40:39.298 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:40:39.298 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:40:39.298 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:40:39.298 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:40:39.298 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:40:39.298 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:40:39.298 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:40:39.298 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:40:39.298 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:40:39.298 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:40:39.298 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:40:39.298 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:40:39.302 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-01-29 02:40:39.786 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-01-29 02:40:39.820 [DEBUG] fake_trx.py:278 (BTS@172.18.28.20:5700) Recv FAKE_TOA cmd
2026-01-29 02:40:39.821 [DEBUG] fake_trx.py:297 (BTS@172.18.28.20:5700) Recv FAKE_RSSI cmd
2026-01-29 02:40:39.822 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:40:39.823 [DEBUG] fake_trx.py:322 (BTS@172.18.28.20:5700) Recv FAKE_CI cmd
2026-01-29 02:40:39.849 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 02:40:39.849 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 02:40:39.849 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 02:40:39.855 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:40:39.858 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:40:39.861 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:40:39.863 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:40:39.866 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:40:39.868 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:40:39.870 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:40:39.872 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:40:39.875 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:40:39.877 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:40:39.881 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:40:39.884 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:40:39.889 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:40:39.892 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:40:39.895 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:40:39.898 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:40:39.901 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:40:39.904 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:40:39.906 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:40:39.909 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:40:39.912 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:40:39.914 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:40:39.917 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:40:39.919 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:40:39.922 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:40:39.925 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:40:39.927 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:40:39.930 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:40:39.933 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:40:39.935 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:40:39.938 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:40:39.940 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:40:39.943 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:40:39.946 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:40:39.948 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:40:39.951 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:40:39.954 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:40:39.956 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:40:39.959 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:40:39.961 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:40:39.964 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:40:39.967 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:40:39.971 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:40:39.975 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:40:39.979 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:40:39.982 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:40:39.985 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:40:39.987 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:40:39.990 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:40:39.993 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:40:39.995 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:40:39.998 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:40:40.001 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:40:40.003 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:40:40.006 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:40:40.009 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:40:40.012 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:40:40.014 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:40:40.017 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:40:40.020 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:40:40.023 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:40:40.026 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:40:40.029 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:40:40.031 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
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2026-01-29 02:40:40.256 [DEBUG] clck_gen.py:113 IND CLOCK 204
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2026-01-29 02:40:40.278 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
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2026-01-29 02:40:40.279 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:40:40.279 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:40:40.280 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:40:40.280 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:40:40.280 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:40:40.281 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:40:40.281 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:40:40.282 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:40:40.282 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:40:40.283 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:40:40.283 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:40:40.283 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:40:40.284 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:40:40.284 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:40:40.285 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:40:40.285 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:40:40.285 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:40:40.286 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:40:40.286 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:40:40.287 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:40:40.287 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:40:40.287 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:40:40.288 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:40:40.288 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:40:40.289 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:40:40.289 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:40:40.289 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:40:40.290 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:40:40.290 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:40:40.291 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:40:40.291 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:40:40.292 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:40:40.292 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:40:40.292 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:40:40.293 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:40:40.293 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:40:40.294 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:40:40.294 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:40:40.295 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:40:40.295 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:40:40.295 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:40:40.296 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:40:40.296 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:40:40.297 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:40:40.297 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:40:40.298 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:40:40.298 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:40:40.298 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:40:40.299 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:40:40.299 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:40:40.300 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:40:40.300 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 02:40:40.300 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:40:40.300 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:40:40.300 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:40:40.301 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:40:40.301 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:40:40.301 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:40:40.301 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:40:40.302 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:40:40.302 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:40:40.303 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:40:40.303 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:40:40.304 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:40:40.304 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:40:40.304 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:40:40.305 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:40:40.305 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:40:40.306 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:40:40.306 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:40:40.306 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:40:40.307 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:40:40.307 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:40:40.308 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:40:40.308 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:40:40.308 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:40:40.309 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:40:40.309 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:40:40.310 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:40:40.310 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:40:40.311 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:40:40.311 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:40:40.311 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:40:40.312 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:40:40.312 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:40:40.313 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:40:40.313 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:40:40.313 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:40:40.314 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:40:40.314 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:40:40.315 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:40:40.315 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:40:40.315 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:40:40.316 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:40:40.316 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:40:40.317 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:40:40.317 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:40:40.317 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:40:40.318 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:40:40.318 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:40:40.319 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:40:40.319 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:40:40.319 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:40:40.320 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:40:40.320 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:40:40.321 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:40:40.321 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:40:40.321 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:40:40.322 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:40:40.322 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:40:40.323 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:40:40.323 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:40:40.324 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:40:40.324 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:40:40.324 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:40:40.325 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:40:40.325 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:40:40.325 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:40:40.326 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:40:40.326 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:40:40.327 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:40:40.327 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:40:40.328 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:40:40.328 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:40:40.328 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:40:40.329 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:40:40.329 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:40:40.330 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:40:40.330 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:40:40.330 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:40:40.331 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:40:40.331 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:40:40.332 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:40:40.332 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:40:40.332 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:40:40.333 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:40:40.333 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:40:40.334 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:40:40.334 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:40:40.334 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:40:40.335 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:40:40.335 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:40:40.336 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:40:40.336 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:40:40.336 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:40:40.337 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:40:40.337 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:40:40.338 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:40:40.338 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:40:40.338 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:40:40.339 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:40:40.339 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:40:40.340 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:40:40.340 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:40:40.340 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:40:40.341 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:40:40.341 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:40:40.342 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:40:40.342 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:40:40.342 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:40:40.343 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:40:40.343 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
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2026-01-29 02:40:40.413 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:40:40.414 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:40:40.414 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:40:40.415 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:40:40.415 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:40:40.415 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:40:40.416 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:40:40.416 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:40:40.417 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:40:40.417 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:40:40.417 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:40:40.418 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:40:40.418 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:40:40.419 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:40:40.419 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:40:40.419 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:40:40.420 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:40:40.420 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:40:40.421 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:40:40.421 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:40:40.421 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:40:40.422 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:40:40.422 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:40:40.423 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:40:40.423 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:40:40.424 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:40:40.424 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:40:40.425 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:40:40.425 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:40:40.425 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:40:40.426 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:40:40.426 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:40:40.427 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:40:40.427 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:40:40.428 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:40:40.428 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:40:40.428 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:40:40.429 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:40:40.429 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:40:40.430 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:40:40.430 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:40:40.430 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:40:40.431 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:40:40.431 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:40:40.432 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:40:40.432 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:40:40.432 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:40:40.433 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:40:40.433 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:40:40.434 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:40:40.434 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:40:40.435 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:40:40.435 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:40:40.435 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:40:40.436 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:40:40.436 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:40:40.437 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:40:40.437 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:40:40.437 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:40:40.438 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:40:40.438 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:40:40.439 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:40:40.439 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:40:40.439 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:40:40.440 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:40:40.440 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:40:40.441 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:40:40.441 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:40:40.441 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:40:40.442 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:40:40.442 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:40:40.443 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:40:40.443 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:40:40.444 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:40:40.444 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:40:40.445 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:40:40.445 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:40:40.445 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:40:40.446 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:40:40.446 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:40:40.447 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:40:40.447 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:40:40.447 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:40:40.448 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:40:40.448 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:40:40.449 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:40:40.449 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:40:40.449 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:40:40.450 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:40:40.450 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:40:40.451 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:40:40.451 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:40:40.451 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:40:40.452 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:40:40.452 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:40:40.453 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:40:40.453 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:40:40.454 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:40:40.454 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:40:40.454 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:40:40.455 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:40:40.455 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:40:40.456 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:40:40.456 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:40:40.456 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:40:40.457 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:40:40.457 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:40:40.457 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:40:40.458 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:40:40.458 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:40:40.459 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:40:40.459 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:40:40.459 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:40:40.460 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:40:40.460 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:40:40.461 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:40:40.461 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:40:40.463 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 02:40:40.463 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:40:40.463 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:40:40.463 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:40:40.465 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 02:40:40.465 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:40:40.465 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:40:40.465 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:40:40.465 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.28.20:5700) Recv POWEROFF cmd
2026-01-29 02:40:40.465 [INFO] ctrl_if_trx.py:117 (BTS@172.18.28.20:5700) Stopping transceiver...
2026-01-29 02:40:40.465 [INFO] transceiver.py:246 Stopping clock generator
2026-01-29 02:40:40.465 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=252 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:40:40.465 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=252 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:40:40.465 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=252 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:40:40.465 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=252 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:40:40.465 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=252 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:40:40.466 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=252 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:40:40.466 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=252 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:40:45.467 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.28.20:5700) Recv POWEROFF cmd
2026-01-29 02:40:45.467 [INFO] ctrl_if_trx.py:117 (BTS@172.18.28.20:5700) Stopping transceiver...
2026-01-29 02:40:45.469 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:40:45.470 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:40:45.470 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:40:45.470 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 02:40:45.476 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 02:40:45.477 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.28.20:5700) Recv SETFORMAT cmd
2026-01-29 02:40:45.477 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.28.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:40:45.477 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.28.20:5700) Recv SETFORMAT cmd
2026-01-29 02:40:45.477 [INFO] ctrl_if_trx.py:201 (BTS@172.18.28.20:5700) TRXD header version 1 -> 1
2026-01-29 02:40:45.480 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.28.20:5700/1) Recv RXTUNE cmd
2026-01-29 02:40:45.480 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.28.20:5700/1) Recv TXTUNE cmd
2026-01-29 02:40:45.480 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.28.20:5700/1) Recv SETFORMAT cmd
2026-01-29 02:40:45.480 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.28.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:40:45.481 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:40:45.481 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.28.20:5700/1) Recv NOMTXPOWER cmd
2026-01-29 02:40:45.481 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.28.20:5700/1) Recv SETFORMAT cmd
2026-01-29 02:40:45.481 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.28.20:5700/1) TRXD header version 1 -> 1
2026-01-29 02:40:45.482 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.28.20:5700/2) Recv RXTUNE cmd
2026-01-29 02:40:45.482 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.28.20:5700/2) Recv TXTUNE cmd
2026-01-29 02:40:45.482 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.28.20:5700/2) Recv SETFORMAT cmd
2026-01-29 02:40:45.483 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.28.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:40:45.483 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:40:45.483 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.28.20:5700/2) Recv NOMTXPOWER cmd
2026-01-29 02:40:45.483 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.28.20:5700/2) Recv SETFORMAT cmd
2026-01-29 02:40:45.483 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.28.20:5700/2) TRXD header version 1 -> 1
2026-01-29 02:40:45.484 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.28.20:5700/3) Recv RXTUNE cmd
2026-01-29 02:40:45.484 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.28.20:5700/3) Recv TXTUNE cmd
2026-01-29 02:40:45.485 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.28.20:5700/3) Recv SETFORMAT cmd
2026-01-29 02:40:45.485 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.28.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:40:45.485 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:40:45.485 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.28.20:5700/3) Recv NOMTXPOWER cmd
2026-01-29 02:40:45.485 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.28.20:5700/3) Recv SETFORMAT cmd
2026-01-29 02:40:45.485 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.28.20:5700/3) TRXD header version 1 -> 1
2026-01-29 02:40:45.487 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.28.20:5700) Recv RXTUNE cmd
2026-01-29 02:40:45.487 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETTSC
2026-01-29 02:40:45.487 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETTSC
2026-01-29 02:40:45.487 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETTSC
2026-01-29 02:40:45.487 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.28.20:5700) Recv TXTUNE cmd
2026-01-29 02:40:45.487 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETRXGAIN
2026-01-29 02:40:45.487 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETRXGAIN
2026-01-29 02:40:45.487 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETRXGAIN
2026-01-29 02:40:45.487 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETTSC
2026-01-29 02:40:45.487 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:40:45.487 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:40:45.487 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:40:45.487 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.28.20:5700) Recv NOMTXPOWER cmd
2026-01-29 02:40:45.487 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:40:45.487 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:40:45.487 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:40:45.487 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.28.20:5700) Recv POWERON CMD
2026-01-29 02:40:45.487 [INFO] ctrl_if_trx.py:109 (BTS@172.18.28.20:5700) Starting transceiver...
2026-01-29 02:40:45.487 [INFO] transceiver.py:243 Starting clock generator
2026-01-29 02:40:45.487 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-01-29 02:40:45.488 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:40:45.488 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:40:45.488 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:40:45.488 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETRXGAIN
2026-01-29 02:40:45.488 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:40:45.488 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:40:45.488 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:40:45.488 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:40:45.488 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:40:45.488 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:40:45.488 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:40:45.488 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:40:45.488 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:40:45.488 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:40:45.488 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:40:45.488 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:40:45.488 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:40:45.488 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:40:45.488 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:40:45.488 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:40:45.488 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:40:45.488 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:40:45.488 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:40:45.488 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:40:45.488 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:40:45.488 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:40:45.488 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:40:45.492 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-01-29 02:40:45.976 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-01-29 02:40:46.008 [DEBUG] fake_trx.py:278 (BTS@172.18.28.20:5700) Recv FAKE_TOA cmd
2026-01-29 02:40:46.009 [DEBUG] fake_trx.py:297 (BTS@172.18.28.20:5700) Recv FAKE_RSSI cmd
2026-01-29 02:40:46.010 [DEBUG] fake_trx.py:322 (BTS@172.18.28.20:5700) Recv FAKE_CI cmd
2026-01-29 02:40:46.010 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:40:46.027 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 02:40:46.027 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 02:40:46.027 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 02:40:46.035 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:40:46.044 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:40:46.053 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 02:40:46.054 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:40:46.054 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:40:46.054 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:40:46.056 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 02:40:46.056 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:40:46.056 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:40:46.056 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.28.20:5700) Recv POWEROFF cmd
2026-01-29 02:40:46.056 [INFO] ctrl_if_trx.py:117 (BTS@172.18.28.20:5700) Stopping transceiver...
2026-01-29 02:40:46.056 [INFO] transceiver.py:246 Stopping clock generator
2026-01-29 02:40:46.056 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:40:46.057 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=120 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:40:46.057 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=120 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:40:46.057 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=120 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:40:46.057 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=120 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:40:46.057 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=120 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:40:46.057 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=120 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:40:46.057 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=120 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:40:46.057 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=120 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:40:46.057 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=121 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:40:46.057 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=121 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:40:46.057 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=121 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:40:46.057 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=121 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:40:46.057 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=121 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:40:46.057 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=121 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:40:46.057 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=121 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:40:46.057 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=121 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:40:51.057 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.28.20:5700) Recv POWEROFF cmd
2026-01-29 02:40:51.057 [INFO] ctrl_if_trx.py:117 (BTS@172.18.28.20:5700) Stopping transceiver...
2026-01-29 02:40:51.058 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:40:51.060 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:40:51.060 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:40:51.060 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 02:40:51.063 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 02:40:51.063 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.28.20:5700) Recv SETFORMAT cmd
2026-01-29 02:40:51.063 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.28.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:40:51.063 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.28.20:5700) Recv SETFORMAT cmd
2026-01-29 02:40:51.063 [INFO] ctrl_if_trx.py:201 (BTS@172.18.28.20:5700) TRXD header version 1 -> 1
2026-01-29 02:40:51.063 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.28.20:5700/1) Recv RXTUNE cmd
2026-01-29 02:40:51.063 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.28.20:5700/1) Recv TXTUNE cmd
2026-01-29 02:40:51.064 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.28.20:5700/1) Recv SETFORMAT cmd
2026-01-29 02:40:51.064 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.28.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:40:51.064 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:40:51.064 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.28.20:5700/1) Recv NOMTXPOWER cmd
2026-01-29 02:40:51.065 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.28.20:5700/1) Recv SETFORMAT cmd
2026-01-29 02:40:51.065 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.28.20:5700/1) TRXD header version 1 -> 1
2026-01-29 02:40:51.066 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.28.20:5700/2) Recv RXTUNE cmd
2026-01-29 02:40:51.066 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.28.20:5700/2) Recv TXTUNE cmd
2026-01-29 02:40:51.066 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.28.20:5700/2) Recv SETFORMAT cmd
2026-01-29 02:40:51.066 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.28.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:40:51.066 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:40:51.066 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.28.20:5700/2) Recv NOMTXPOWER cmd
2026-01-29 02:40:51.066 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.28.20:5700/2) Recv SETFORMAT cmd
2026-01-29 02:40:51.066 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.28.20:5700/2) TRXD header version 1 -> 1
2026-01-29 02:40:51.068 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.28.20:5700/3) Recv RXTUNE cmd
2026-01-29 02:40:51.068 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.28.20:5700/3) Recv TXTUNE cmd
2026-01-29 02:40:51.068 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.28.20:5700/3) Recv SETFORMAT cmd
2026-01-29 02:40:51.068 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.28.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:40:51.069 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:40:51.069 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.28.20:5700/3) Recv NOMTXPOWER cmd
2026-01-29 02:40:51.069 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.28.20:5700/3) Recv SETFORMAT cmd
2026-01-29 02:40:51.069 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.28.20:5700/3) TRXD header version 1 -> 1
2026-01-29 02:40:51.071 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.28.20:5700) Recv RXTUNE cmd
2026-01-29 02:40:51.071 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETTSC
2026-01-29 02:40:51.071 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETTSC
2026-01-29 02:40:51.071 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.28.20:5700) Recv TXTUNE cmd
2026-01-29 02:40:51.071 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETTSC
2026-01-29 02:40:51.071 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETRXGAIN
2026-01-29 02:40:51.071 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETRXGAIN
2026-01-29 02:40:51.071 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETTSC
2026-01-29 02:40:51.071 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETRXGAIN
2026-01-29 02:40:51.071 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:40:51.071 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:40:51.071 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.28.20:5700) Recv NOMTXPOWER cmd
2026-01-29 02:40:51.071 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:40:51.071 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:40:51.071 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:40:51.071 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.28.20:5700) Recv POWERON CMD
2026-01-29 02:40:51.071 [INFO] ctrl_if_trx.py:109 (BTS@172.18.28.20:5700) Starting transceiver...
2026-01-29 02:40:51.072 [INFO] transceiver.py:243 Starting clock generator
2026-01-29 02:40:51.072 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-01-29 02:40:51.072 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:40:51.072 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:40:51.072 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:40:51.072 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETRXGAIN
2026-01-29 02:40:51.072 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:40:51.072 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:40:51.072 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:40:51.072 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:40:51.072 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:40:51.072 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:40:51.072 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:40:51.072 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:40:51.072 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:40:51.072 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:40:51.073 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:40:51.073 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:40:51.073 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:40:51.073 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:40:51.073 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:40:51.073 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:40:51.073 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:40:51.073 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:40:51.073 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:40:51.073 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:40:51.073 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:40:51.073 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:40:51.073 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:40:51.073 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:40:51.077 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-01-29 02:40:51.560 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-01-29 02:40:51.594 [DEBUG] fake_trx.py:278 (BTS@172.18.28.20:5700) Recv FAKE_TOA cmd
2026-01-29 02:40:51.595 [DEBUG] fake_trx.py:297 (BTS@172.18.28.20:5700) Recv FAKE_RSSI cmd
2026-01-29 02:40:51.596 [DEBUG] fake_trx.py:322 (BTS@172.18.28.20:5700) Recv FAKE_CI cmd
2026-01-29 02:40:51.596 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:40:51.613 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 02:40:51.613 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 02:40:51.613 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 02:40:51.631 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 02:40:51.631 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:40:51.631 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:40:51.631 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:40:51.634 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 02:40:51.634 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:40:51.635 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:40:51.635 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:40:51.635 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.28.20:5700) Recv POWEROFF cmd
2026-01-29 02:40:51.635 [INFO] ctrl_if_trx.py:117 (BTS@172.18.28.20:5700) Stopping transceiver...
2026-01-29 02:40:51.635 [INFO] transceiver.py:246 Stopping clock generator
2026-01-29 02:40:51.635 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=120 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:40:51.636 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=120 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:40:51.636 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=120 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:40:51.636 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=120 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:40:51.636 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=120 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:40:51.636 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=120 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:40:51.636 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=120 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:40:56.638 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.28.20:5700) Recv POWEROFF cmd
2026-01-29 02:40:56.638 [INFO] ctrl_if_trx.py:117 (BTS@172.18.28.20:5700) Stopping transceiver...
2026-01-29 02:40:56.638 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:40:56.638 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:40:56.638 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:40:56.639 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 02:40:56.647 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 02:40:56.649 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.28.20:5700) Recv SETFORMAT cmd
2026-01-29 02:40:56.650 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.28.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:40:56.650 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.28.20:5700) Recv SETFORMAT cmd
2026-01-29 02:40:56.650 [INFO] ctrl_if_trx.py:201 (BTS@172.18.28.20:5700) TRXD header version 1 -> 1
2026-01-29 02:40:56.654 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.28.20:5700/1) Recv RXTUNE cmd
2026-01-29 02:40:56.655 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.28.20:5700/1) Recv TXTUNE cmd
2026-01-29 02:40:56.655 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.28.20:5700/1) Recv SETFORMAT cmd
2026-01-29 02:40:56.655 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.28.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:40:56.656 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:40:56.656 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.28.20:5700/1) Recv NOMTXPOWER cmd
2026-01-29 02:40:56.657 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.28.20:5700/1) Recv SETFORMAT cmd
2026-01-29 02:40:56.657 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.28.20:5700/1) TRXD header version 1 -> 1
2026-01-29 02:40:56.658 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.28.20:5700/2) Recv RXTUNE cmd
2026-01-29 02:40:56.658 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.28.20:5700/2) Recv TXTUNE cmd
2026-01-29 02:40:56.659 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.28.20:5700/2) Recv SETFORMAT cmd
2026-01-29 02:40:56.659 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.28.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:40:56.659 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:40:56.660 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.28.20:5700/2) Recv NOMTXPOWER cmd
2026-01-29 02:40:56.660 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.28.20:5700/2) Recv SETFORMAT cmd
2026-01-29 02:40:56.660 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.28.20:5700/2) TRXD header version 1 -> 1
2026-01-29 02:40:56.661 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.28.20:5700/3) Recv RXTUNE cmd
2026-01-29 02:40:56.661 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.28.20:5700/3) Recv TXTUNE cmd
2026-01-29 02:40:56.661 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.28.20:5700/3) Recv SETFORMAT cmd
2026-01-29 02:40:56.661 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.28.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:40:56.662 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:40:56.662 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.28.20:5700/3) Recv NOMTXPOWER cmd
2026-01-29 02:40:56.662 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.28.20:5700/3) Recv SETFORMAT cmd
2026-01-29 02:40:56.662 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.28.20:5700/3) TRXD header version 1 -> 1
2026-01-29 02:40:56.665 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.28.20:5700) Recv RXTUNE cmd
2026-01-29 02:40:56.665 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETTSC
2026-01-29 02:40:56.665 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETTSC
2026-01-29 02:40:56.665 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETTSC
2026-01-29 02:40:56.665 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.28.20:5700) Recv TXTUNE cmd
2026-01-29 02:40:56.665 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETRXGAIN
2026-01-29 02:40:56.665 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETRXGAIN
2026-01-29 02:40:56.665 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETRXGAIN
2026-01-29 02:40:56.665 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETTSC
2026-01-29 02:40:56.665 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:40:56.665 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:40:56.666 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:40:56.666 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.28.20:5700) Recv NOMTXPOWER cmd
2026-01-29 02:40:56.666 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:40:56.666 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:40:56.666 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:40:56.666 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.28.20:5700) Recv POWERON CMD
2026-01-29 02:40:56.666 [INFO] ctrl_if_trx.py:109 (BTS@172.18.28.20:5700) Starting transceiver...
2026-01-29 02:40:56.666 [INFO] transceiver.py:243 Starting clock generator
2026-01-29 02:40:56.666 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-01-29 02:40:56.666 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:40:56.666 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:40:56.666 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:40:56.666 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETRXGAIN
2026-01-29 02:40:56.666 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:40:56.666 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:40:56.666 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:40:56.666 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:40:56.667 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:40:56.667 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:40:56.667 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:40:56.667 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:40:56.667 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:40:56.667 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:40:56.667 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:40:56.667 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:40:56.667 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:40:56.667 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:40:56.667 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:40:56.667 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:40:56.667 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:40:56.667 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:40:56.667 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:40:56.667 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:40:56.667 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:40:56.667 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:40:56.667 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:40:56.671 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-01-29 02:40:57.155 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-01-29 02:40:57.196 [DEBUG] fake_trx.py:278 (BTS@172.18.28.20:5700) Recv FAKE_TOA cmd
2026-01-29 02:40:57.199 [DEBUG] fake_trx.py:297 (BTS@172.18.28.20:5700) Recv FAKE_RSSI cmd
2026-01-29 02:40:57.200 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:40:57.201 [DEBUG] fake_trx.py:322 (BTS@172.18.28.20:5700) Recv FAKE_CI cmd
2026-01-29 02:40:57.216 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 02:40:57.216 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 02:40:57.217 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 02:40:57.238 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 02:40:57.238 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 02:40:57.238 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 02:40:57.246 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 02:40:57.246 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 02:40:57.246 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 02:40:57.253 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 02:40:57.254 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 02:40:57.254 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 02:40:57.261 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 02:40:57.261 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 02:40:57.261 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 02:40:57.269 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 02:40:57.269 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 02:40:57.269 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 02:40:57.276 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 02:40:57.276 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 02:40:57.277 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 02:40:57.284 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 02:40:57.284 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 02:40:57.284 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 02:40:57.291 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 02:40:57.292 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 02:40:57.292 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 02:40:57.299 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 02:40:57.299 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 02:40:57.299 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 02:40:57.306 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 02:40:57.306 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 02:40:57.306 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 02:40:57.314 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 02:40:57.314 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 02:40:57.314 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 02:40:57.321 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 02:40:57.321 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 02:40:57.321 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 02:40:57.326 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 02:40:57.326 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:40:57.326 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:40:57.326 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:40:57.327 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 02:40:57.327 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:40:57.327 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:40:57.327 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:40:57.327 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.28.20:5700) Recv POWEROFF cmd
2026-01-29 02:40:57.327 [INFO] ctrl_if_trx.py:117 (BTS@172.18.28.20:5700) Stopping transceiver...
2026-01-29 02:40:57.327 [INFO] transceiver.py:246 Stopping clock generator
2026-01-29 02:40:57.327 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=141 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:40:57.327 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=141 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:40:57.327 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=141 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:40:57.327 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=141 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:40:57.327 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=141 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:40:57.327 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=141 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:40:57.327 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=141 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:41:02.329 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.28.20:5700) Recv POWEROFF cmd
2026-01-29 02:41:02.329 [INFO] ctrl_if_trx.py:117 (BTS@172.18.28.20:5700) Stopping transceiver...
2026-01-29 02:41:02.331 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:41:02.332 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:41:02.332 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:41:02.332 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 02:41:02.343 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 02:41:02.345 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.28.20:5700) Recv SETFORMAT cmd
2026-01-29 02:41:02.345 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.28.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:41:02.345 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.28.20:5700) Recv SETFORMAT cmd
2026-01-29 02:41:02.346 [INFO] ctrl_if_trx.py:201 (BTS@172.18.28.20:5700) TRXD header version 1 -> 1
2026-01-29 02:41:02.349 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.28.20:5700/1) Recv RXTUNE cmd
2026-01-29 02:41:02.349 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.28.20:5700/1) Recv TXTUNE cmd
2026-01-29 02:41:02.350 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.28.20:5700/1) Recv SETFORMAT cmd
2026-01-29 02:41:02.350 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.28.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:41:02.351 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:41:02.351 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.28.20:5700/1) Recv NOMTXPOWER cmd
2026-01-29 02:41:02.352 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.28.20:5700/1) Recv SETFORMAT cmd
2026-01-29 02:41:02.352 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.28.20:5700/1) TRXD header version 1 -> 1
2026-01-29 02:41:02.353 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.28.20:5700/2) Recv RXTUNE cmd
2026-01-29 02:41:02.354 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.28.20:5700/2) Recv TXTUNE cmd
2026-01-29 02:41:02.354 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.28.20:5700/2) Recv SETFORMAT cmd
2026-01-29 02:41:02.354 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.28.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:41:02.354 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:41:02.354 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.28.20:5700/2) Recv NOMTXPOWER cmd
2026-01-29 02:41:02.355 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.28.20:5700/2) Recv SETFORMAT cmd
2026-01-29 02:41:02.355 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.28.20:5700/2) TRXD header version 1 -> 1
2026-01-29 02:41:02.357 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.28.20:5700/3) Recv RXTUNE cmd
2026-01-29 02:41:02.357 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.28.20:5700/3) Recv TXTUNE cmd
2026-01-29 02:41:02.357 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.28.20:5700/3) Recv SETFORMAT cmd
2026-01-29 02:41:02.358 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.28.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:41:02.358 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:41:02.358 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.28.20:5700/3) Recv NOMTXPOWER cmd
2026-01-29 02:41:02.358 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.28.20:5700/3) Recv SETFORMAT cmd
2026-01-29 02:41:02.358 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.28.20:5700/3) TRXD header version 1 -> 1
2026-01-29 02:41:02.362 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.28.20:5700) Recv RXTUNE cmd
2026-01-29 02:41:02.362 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETTSC
2026-01-29 02:41:02.362 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETTSC
2026-01-29 02:41:02.362 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETTSC
2026-01-29 02:41:02.362 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.28.20:5700) Recv TXTUNE cmd
2026-01-29 02:41:02.362 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETRXGAIN
2026-01-29 02:41:02.362 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETRXGAIN
2026-01-29 02:41:02.362 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETRXGAIN
2026-01-29 02:41:02.362 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETTSC
2026-01-29 02:41:02.363 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:41:02.363 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:41:02.363 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:41:02.363 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.28.20:5700) Recv NOMTXPOWER cmd
2026-01-29 02:41:02.363 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:41:02.363 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:41:02.363 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:41:02.363 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.28.20:5700) Recv POWERON CMD
2026-01-29 02:41:02.363 [INFO] ctrl_if_trx.py:109 (BTS@172.18.28.20:5700) Starting transceiver...
2026-01-29 02:41:02.363 [INFO] transceiver.py:243 Starting clock generator
2026-01-29 02:41:02.363 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-01-29 02:41:02.363 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:41:02.363 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:41:02.363 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:41:02.364 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETRXGAIN
2026-01-29 02:41:02.364 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:41:02.364 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:41:02.364 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:41:02.364 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:41:02.364 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:41:02.364 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:41:02.364 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:41:02.364 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:41:02.364 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:41:02.364 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:41:02.364 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:41:02.364 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:41:02.364 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:41:02.364 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:41:02.364 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:41:02.364 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:41:02.364 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:41:02.364 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:41:02.365 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:41:02.365 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:41:02.365 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:41:02.365 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:41:02.365 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:41:02.368 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-01-29 02:41:02.851 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-01-29 02:41:02.932 [DEBUG] fake_trx.py:278 (BTS@172.18.28.20:5700) Recv FAKE_TOA cmd
2026-01-29 02:41:02.935 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:41:02.936 [DEBUG] fake_trx.py:297 (BTS@172.18.28.20:5700) Recv FAKE_RSSI cmd
2026-01-29 02:41:02.937 [DEBUG] fake_trx.py:322 (BTS@172.18.28.20:5700) Recv FAKE_CI cmd
2026-01-29 02:41:02.960 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 02:41:02.960 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 02:41:02.960 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 02:41:02.965 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:41:02.965 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 02:41:02.965 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 02:41:02.965 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.28.22:6700) Recv POWERON CMD
2026-01-29 02:41:02.965 [INFO] ctrl_if_trx.py:109 (MS@172.18.28.22:6700) Starting transceiver...
2026-01-29 02:41:02.994 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:41:03.000 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 02:41:03.001 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 02:41:03.001 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:41:03.001 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:41:03.053 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:41:03.328 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-01-29 02:41:03.366 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 02:41:03.367 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:41:03.368 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:41:03.373 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:41:03.806 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-01-29 02:41:04.284 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-01-29 02:41:04.367 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 02:41:04.368 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:41:04.369 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:41:04.374 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:41:04.762 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-01-29 02:41:05.240 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-01-29 02:41:05.369 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 02:41:05.369 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:41:05.369 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:41:05.375 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:41:05.718 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-01-29 02:41:06.197 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-01-29 02:41:06.369 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 02:41:06.370 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:41:06.370 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:41:06.376 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:41:06.675 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-01-29 02:41:07.054 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:41:07.057 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:41:07.057 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 02:41:07.057 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 02:41:07.072 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 02:41:07.072 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 02:41:07.072 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 02:41:07.074 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:41:07.074 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 02:41:07.074 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 02:41:07.074 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.28.22:6700) Recv POWERON CMD
2026-01-29 02:41:07.074 [INFO] ctrl_if_trx.py:109 (MS@172.18.28.22:6700) Starting transceiver...
2026-01-29 02:41:07.094 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:41:07.099 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 02:41:07.099 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 02:41:07.099 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:41:07.099 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:41:07.152 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-01-29 02:41:07.370 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 02:41:07.370 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:41:07.370 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:41:07.372 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:41:07.377 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:41:07.630 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-01-29 02:41:08.108 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-01-29 02:41:08.585 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-01-29 02:41:09.063 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-01-29 02:41:09.540 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-01-29 02:41:10.018 [DEBUG] clck_gen.py:113 IND CLOCK 1632
2026-01-29 02:41:10.496 [DEBUG] clck_gen.py:113 IND CLOCK 1734
2026-01-29 02:41:10.974 [DEBUG] clck_gen.py:113 IND CLOCK 1836
2026-01-29 02:41:11.372 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:41:11.375 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:41:11.375 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 02:41:11.375 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 02:41:11.385 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 02:41:11.385 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 02:41:11.385 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 02:41:11.386 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:41:11.386 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 02:41:11.386 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 02:41:11.386 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.28.22:6700) Recv POWERON CMD
2026-01-29 02:41:11.386 [INFO] ctrl_if_trx.py:109 (MS@172.18.28.22:6700) Starting transceiver...
2026-01-29 02:41:11.391 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:41:11.392 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 02:41:11.392 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 02:41:11.392 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:41:11.392 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:41:11.446 [DEBUG] clck_gen.py:113 IND CLOCK 1938
2026-01-29 02:41:11.882 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:41:11.924 [DEBUG] clck_gen.py:113 IND CLOCK 2040
2026-01-29 02:41:12.402 [DEBUG] clck_gen.py:113 IND CLOCK 2142
2026-01-29 02:41:12.880 [DEBUG] clck_gen.py:113 IND CLOCK 2244
2026-01-29 02:41:13.357 [DEBUG] clck_gen.py:113 IND CLOCK 2346
2026-01-29 02:41:13.836 [DEBUG] clck_gen.py:113 IND CLOCK 2448
2026-01-29 02:41:14.314 [DEBUG] clck_gen.py:113 IND CLOCK 2550
2026-01-29 02:41:14.792 [DEBUG] clck_gen.py:113 IND CLOCK 2652
2026-01-29 02:41:15.269 [DEBUG] clck_gen.py:113 IND CLOCK 2754
2026-01-29 02:41:15.748 [DEBUG] clck_gen.py:113 IND CLOCK 2856
2026-01-29 02:41:15.883 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:41:15.886 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:41:15.887 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 02:41:15.887 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 02:41:15.905 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 02:41:15.906 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 02:41:15.906 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 02:41:15.907 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:41:15.907 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 02:41:15.907 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 02:41:15.907 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.28.22:6700) Recv POWERON CMD
2026-01-29 02:41:15.907 [INFO] ctrl_if_trx.py:109 (MS@172.18.28.22:6700) Starting transceiver...
2026-01-29 02:41:15.934 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:41:15.935 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 02:41:15.935 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 02:41:15.935 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:41:15.935 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:41:16.203 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:41:16.225 [DEBUG] clck_gen.py:113 IND CLOCK 2958
2026-01-29 02:41:16.703 [DEBUG] clck_gen.py:113 IND CLOCK 3060
2026-01-29 02:41:17.181 [DEBUG] clck_gen.py:113 IND CLOCK 3162
2026-01-29 02:41:17.659 [DEBUG] clck_gen.py:113 IND CLOCK 3264
2026-01-29 02:41:18.137 [DEBUG] clck_gen.py:113 IND CLOCK 3366
2026-01-29 02:41:18.615 [DEBUG] clck_gen.py:113 IND CLOCK 3468
2026-01-29 02:41:19.092 [DEBUG] clck_gen.py:113 IND CLOCK 3570
2026-01-29 02:41:19.570 [DEBUG] clck_gen.py:113 IND CLOCK 3672
2026-01-29 02:41:20.048 [DEBUG] clck_gen.py:113 IND CLOCK 3774
2026-01-29 02:41:20.204 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:41:20.207 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:41:20.207 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 02:41:20.208 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 02:41:20.221 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 02:41:20.221 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 02:41:20.221 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 02:41:20.223 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:41:20.223 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 02:41:20.223 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 02:41:20.223 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.28.22:6700) Recv POWERON CMD
2026-01-29 02:41:20.223 [INFO] ctrl_if_trx.py:109 (MS@172.18.28.22:6700) Starting transceiver...
2026-01-29 02:41:20.230 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:41:20.231 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 02:41:20.231 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 02:41:20.231 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:41:20.231 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:41:20.526 [DEBUG] clck_gen.py:113 IND CLOCK 3876
2026-01-29 02:41:20.866 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:41:21.004 [DEBUG] clck_gen.py:113 IND CLOCK 3978
2026-01-29 02:41:21.482 [DEBUG] clck_gen.py:113 IND CLOCK 4080
2026-01-29 02:41:21.960 [DEBUG] clck_gen.py:113 IND CLOCK 4182
2026-01-29 02:41:22.438 [DEBUG] clck_gen.py:113 IND CLOCK 4284
2026-01-29 02:41:22.916 [DEBUG] clck_gen.py:113 IND CLOCK 4386
2026-01-29 02:41:23.394 [DEBUG] clck_gen.py:113 IND CLOCK 4488
2026-01-29 02:41:23.871 [DEBUG] clck_gen.py:113 IND CLOCK 4590
2026-01-29 02:41:24.349 [DEBUG] clck_gen.py:113 IND CLOCK 4692
2026-01-29 02:41:24.827 [DEBUG] clck_gen.py:113 IND CLOCK 4794
2026-01-29 02:41:24.870 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:41:24.872 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:41:24.873 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 02:41:24.873 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 02:41:24.892 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 02:41:24.892 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 02:41:24.892 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 02:41:24.893 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:41:24.893 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 02:41:24.893 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 02:41:24.893 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.28.22:6700) Recv POWERON CMD
2026-01-29 02:41:24.893 [INFO] ctrl_if_trx.py:109 (MS@172.18.28.22:6700) Starting transceiver...
2026-01-29 02:41:24.923 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:41:24.928 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.28.22:6700) Recv SETFH cmd
2026-01-29 02:41:24.928 [INFO] transceiver.py:201 (MS@172.18.28.22:6700) Frequency hopping configured: hsn=2, maio=0, ma_len=2
2026-01-29 02:41:24.928 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:41:24.929 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:41:25.306 [DEBUG] clck_gen.py:113 IND CLOCK 4896
2026-01-29 02:41:25.319 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:41:25.784 [DEBUG] clck_gen.py:113 IND CLOCK 4998
2026-01-29 02:41:26.262 [DEBUG] clck_gen.py:113 IND CLOCK 5100
2026-01-29 02:41:26.741 [DEBUG] clck_gen.py:113 IND CLOCK 5202
2026-01-29 02:41:27.219 [DEBUG] clck_gen.py:113 IND CLOCK 5304
2026-01-29 02:41:27.697 [DEBUG] clck_gen.py:113 IND CLOCK 5406
2026-01-29 02:41:28.176 [DEBUG] clck_gen.py:113 IND CLOCK 5508
2026-01-29 02:41:28.654 [DEBUG] clck_gen.py:113 IND CLOCK 5610
2026-01-29 02:41:29.133 [DEBUG] clck_gen.py:113 IND CLOCK 5712
2026-01-29 02:41:29.322 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:41:29.324 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:41:29.325 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 02:41:29.325 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 02:41:29.325 [INFO] transceiver.py:205 (MS@172.18.28.22:6700) Frequency hopping disabled
2026-01-29 02:41:29.339 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 02:41:29.339 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 02:41:29.339 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 02:41:29.341 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:41:29.341 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 02:41:29.341 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 02:41:29.341 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.28.22:6700) Recv POWERON CMD
2026-01-29 02:41:29.341 [INFO] ctrl_if_trx.py:109 (MS@172.18.28.22:6700) Starting transceiver...
2026-01-29 02:41:29.371 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:41:29.372 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.28.22:6700) Recv SETFH cmd
2026-01-29 02:41:29.372 [INFO] transceiver.py:201 (MS@172.18.28.22:6700) Frequency hopping configured: hsn=3, maio=3, ma_len=4
2026-01-29 02:41:29.372 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:41:29.372 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:41:29.611 [DEBUG] clck_gen.py:113 IND CLOCK 5814
2026-01-29 02:41:29.767 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:41:30.090 [DEBUG] clck_gen.py:113 IND CLOCK 5916
2026-01-29 02:41:30.569 [DEBUG] clck_gen.py:113 IND CLOCK 6018
2026-01-29 02:41:31.048 [DEBUG] clck_gen.py:113 IND CLOCK 6120
2026-01-29 02:41:31.527 [DEBUG] clck_gen.py:113 IND CLOCK 6222
2026-01-29 02:41:32.006 [DEBUG] clck_gen.py:113 IND CLOCK 6324
2026-01-29 02:41:32.485 [DEBUG] clck_gen.py:113 IND CLOCK 6426
2026-01-29 02:41:32.964 [DEBUG] clck_gen.py:113 IND CLOCK 6528
2026-01-29 02:41:33.443 [DEBUG] clck_gen.py:113 IND CLOCK 6630
2026-01-29 02:41:33.770 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:41:33.773 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:41:33.774 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 02:41:33.774 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 02:41:33.774 [INFO] transceiver.py:205 (MS@172.18.28.22:6700) Frequency hopping disabled
2026-01-29 02:41:33.794 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 02:41:33.794 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 02:41:33.794 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 02:41:33.796 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:41:33.796 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 02:41:33.796 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 02:41:33.796 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.28.22:6700) Recv POWERON CMD
2026-01-29 02:41:33.796 [INFO] ctrl_if_trx.py:109 (MS@172.18.28.22:6700) Starting transceiver...
2026-01-29 02:41:33.817 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:41:33.817 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:41:33.820 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 02:41:33.820 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 02:41:33.820 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:41:33.820 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:41:33.921 [DEBUG] clck_gen.py:113 IND CLOCK 6732
2026-01-29 02:41:34.220 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:41:34.399 [DEBUG] clck_gen.py:113 IND CLOCK 6834
2026-01-29 02:41:34.877 [DEBUG] clck_gen.py:113 IND CLOCK 6936
2026-01-29 02:41:35.356 [DEBUG] clck_gen.py:113 IND CLOCK 7038
2026-01-29 02:41:35.834 [DEBUG] clck_gen.py:113 IND CLOCK 7140
2026-01-29 02:41:36.311 [DEBUG] clck_gen.py:113 IND CLOCK 7242
2026-01-29 02:41:36.790 [DEBUG] clck_gen.py:113 IND CLOCK 7344
2026-01-29 02:41:37.267 [DEBUG] clck_gen.py:113 IND CLOCK 7446
2026-01-29 02:41:37.745 [DEBUG] clck_gen.py:113 IND CLOCK 7548
2026-01-29 02:41:38.222 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:41:38.224 [DEBUG] clck_gen.py:113 IND CLOCK 7650
2026-01-29 02:41:38.224 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:41:38.225 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 02:41:38.225 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 02:41:38.243 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 02:41:38.243 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 02:41:38.244 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 02:41:38.244 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:41:38.245 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 02:41:38.245 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 02:41:38.245 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.28.22:6700) Recv POWERON CMD
2026-01-29 02:41:38.245 [INFO] ctrl_if_trx.py:109 (MS@172.18.28.22:6700) Starting transceiver...
2026-01-29 02:41:38.270 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:41:38.274 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 02:41:38.274 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 02:41:38.274 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:41:38.274 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:41:38.666 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:41:38.701 [DEBUG] clck_gen.py:113 IND CLOCK 7752
2026-01-29 02:41:39.179 [DEBUG] clck_gen.py:113 IND CLOCK 7854
2026-01-29 02:41:39.658 [DEBUG] clck_gen.py:113 IND CLOCK 7956
2026-01-29 02:41:40.136 [DEBUG] clck_gen.py:113 IND CLOCK 8058
2026-01-29 02:41:40.614 [DEBUG] clck_gen.py:113 IND CLOCK 8160
2026-01-29 02:41:41.093 [DEBUG] clck_gen.py:113 IND CLOCK 8262
2026-01-29 02:41:41.571 [DEBUG] clck_gen.py:113 IND CLOCK 8364
2026-01-29 02:41:42.049 [DEBUG] clck_gen.py:113 IND CLOCK 8466
2026-01-29 02:41:42.528 [DEBUG] clck_gen.py:113 IND CLOCK 8568
2026-01-29 02:41:42.669 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:41:42.671 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:41:42.672 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 02:41:42.672 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 02:41:42.692 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 02:41:42.692 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 02:41:42.692 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 02:41:42.693 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:41:42.693 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 02:41:42.693 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 02:41:42.693 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.28.22:6700) Recv POWERON CMD
2026-01-29 02:41:42.693 [INFO] ctrl_if_trx.py:109 (MS@172.18.28.22:6700) Starting transceiver...
2026-01-29 02:41:42.711 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:41:42.712 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:41:42.715 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 02:41:42.715 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 02:41:42.715 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:41:42.716 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:41:43.006 [DEBUG] clck_gen.py:113 IND CLOCK 8670
2026-01-29 02:41:43.480 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:41:43.484 [DEBUG] clck_gen.py:113 IND CLOCK 8772
2026-01-29 02:41:43.961 [DEBUG] clck_gen.py:113 IND CLOCK 8874
2026-01-29 02:41:44.439 [DEBUG] clck_gen.py:113 IND CLOCK 8976
2026-01-29 02:41:44.917 [DEBUG] clck_gen.py:113 IND CLOCK 9078
2026-01-29 02:41:45.395 [DEBUG] clck_gen.py:113 IND CLOCK 9180
2026-01-29 02:41:45.872 [DEBUG] clck_gen.py:113 IND CLOCK 9282
2026-01-29 02:41:46.350 [DEBUG] clck_gen.py:113 IND CLOCK 9384
2026-01-29 02:41:46.828 [DEBUG] clck_gen.py:113 IND CLOCK 9486
2026-01-29 02:41:47.306 [DEBUG] clck_gen.py:113 IND CLOCK 9588
2026-01-29 02:41:47.483 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:41:47.486 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:41:47.486 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 02:41:47.487 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 02:41:47.505 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 02:41:47.505 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 02:41:47.505 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 02:41:47.507 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:41:47.507 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 02:41:47.507 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 02:41:47.507 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.28.22:6700) Recv POWERON CMD
2026-01-29 02:41:47.507 [INFO] ctrl_if_trx.py:109 (MS@172.18.28.22:6700) Starting transceiver...
2026-01-29 02:41:47.545 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:41:47.550 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.28.22:6700) Recv SETFH cmd
2026-01-29 02:41:47.551 [INFO] transceiver.py:201 (MS@172.18.28.22:6700) Frequency hopping configured: hsn=5, maio=0, ma_len=4
2026-01-29 02:41:47.551 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:41:47.551 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:41:47.785 [DEBUG] clck_gen.py:113 IND CLOCK 9690
2026-01-29 02:41:48.263 [DEBUG] clck_gen.py:113 IND CLOCK 9792
2026-01-29 02:41:48.360 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:41:48.742 [DEBUG] clck_gen.py:113 IND CLOCK 9894
2026-01-29 02:41:49.221 [DEBUG] clck_gen.py:113 IND CLOCK 9996
2026-01-29 02:41:49.700 [DEBUG] clck_gen.py:113 IND CLOCK 10098
2026-01-29 02:41:50.178 [DEBUG] clck_gen.py:113 IND CLOCK 10200
2026-01-29 02:41:50.658 [DEBUG] clck_gen.py:113 IND CLOCK 10302
2026-01-29 02:41:51.138 [DEBUG] clck_gen.py:113 IND CLOCK 10404
2026-01-29 02:41:51.617 [DEBUG] clck_gen.py:113 IND CLOCK 10506
2026-01-29 02:41:52.095 [DEBUG] clck_gen.py:113 IND CLOCK 10608
2026-01-29 02:41:52.363 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:41:52.365 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:41:52.366 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 02:41:52.366 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 02:41:52.366 [INFO] transceiver.py:205 (MS@172.18.28.22:6700) Frequency hopping disabled
2026-01-29 02:41:52.385 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 02:41:52.385 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 02:41:52.385 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 02:41:52.386 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:41:52.386 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 02:41:52.386 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 02:41:52.386 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.28.22:6700) Recv POWERON CMD
2026-01-29 02:41:52.386 [INFO] ctrl_if_trx.py:109 (MS@172.18.28.22:6700) Starting transceiver...
2026-01-29 02:41:52.425 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:41:52.430 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.28.22:6700) Recv SETFH cmd
2026-01-29 02:41:52.430 [INFO] transceiver.py:201 (MS@172.18.28.22:6700) Frequency hopping configured: hsn=5, maio=0, ma_len=4
2026-01-29 02:41:52.431 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:41:52.431 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:41:52.573 [DEBUG] clck_gen.py:113 IND CLOCK 10710
2026-01-29 02:41:52.811 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:41:53.052 [DEBUG] clck_gen.py:113 IND CLOCK 10812
2026-01-29 02:41:53.529 [DEBUG] clck_gen.py:113 IND CLOCK 10914
2026-01-29 02:41:54.008 [DEBUG] clck_gen.py:113 IND CLOCK 11016
2026-01-29 02:41:54.487 [DEBUG] clck_gen.py:113 IND CLOCK 11118
2026-01-29 02:41:54.967 [DEBUG] clck_gen.py:113 IND CLOCK 11220
2026-01-29 02:41:55.446 [DEBUG] clck_gen.py:113 IND CLOCK 11322
2026-01-29 02:41:55.925 [DEBUG] clck_gen.py:113 IND CLOCK 11424
2026-01-29 02:41:56.404 [DEBUG] clck_gen.py:113 IND CLOCK 11526
2026-01-29 02:41:56.815 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:41:56.818 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:41:56.818 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 02:41:56.818 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 02:41:56.819 [INFO] transceiver.py:205 (MS@172.18.28.22:6700) Frequency hopping disabled
2026-01-29 02:41:56.832 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 02:41:56.832 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 02:41:56.832 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 02:41:56.833 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:41:56.833 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 02:41:56.833 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 02:41:56.833 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.28.22:6700) Recv POWERON CMD
2026-01-29 02:41:56.833 [INFO] ctrl_if_trx.py:109 (MS@172.18.28.22:6700) Starting transceiver...
2026-01-29 02:41:56.879 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:41:56.883 [DEBUG] clck_gen.py:113 IND CLOCK 11628
2026-01-29 02:41:56.885 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.28.22:6700) Recv SETFH cmd
2026-01-29 02:41:56.885 [INFO] transceiver.py:201 (MS@172.18.28.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2026-01-29 02:41:56.885 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:41:56.886 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:41:57.040 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:41:57.362 [DEBUG] clck_gen.py:113 IND CLOCK 11730
2026-01-29 02:41:57.840 [DEBUG] clck_gen.py:113 IND CLOCK 11832
2026-01-29 02:41:58.318 [DEBUG] clck_gen.py:113 IND CLOCK 11934
2026-01-29 02:41:58.797 [DEBUG] clck_gen.py:113 IND CLOCK 12036
2026-01-29 02:41:59.274 [DEBUG] clck_gen.py:113 IND CLOCK 12138
2026-01-29 02:41:59.752 [DEBUG] clck_gen.py:113 IND CLOCK 12240
2026-01-29 02:42:00.231 [DEBUG] clck_gen.py:113 IND CLOCK 12342
2026-01-29 02:42:00.709 [DEBUG] clck_gen.py:113 IND CLOCK 12444
2026-01-29 02:42:01.060 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:42:01.063 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:42:01.063 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 02:42:01.064 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 02:42:01.064 [INFO] transceiver.py:205 (MS@172.18.28.22:6700) Frequency hopping disabled
2026-01-29 02:42:01.081 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 02:42:01.081 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 02:42:01.081 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 02:42:01.083 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:42:01.083 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 02:42:01.083 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 02:42:01.083 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.28.22:6700) Recv POWERON CMD
2026-01-29 02:42:01.083 [INFO] ctrl_if_trx.py:109 (MS@172.18.28.22:6700) Starting transceiver...
2026-01-29 02:42:01.132 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:42:01.137 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.28.22:6700) Recv SETFH cmd
2026-01-29 02:42:01.137 [INFO] transceiver.py:201 (MS@172.18.28.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2026-01-29 02:42:01.137 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:42:01.137 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:42:01.186 [DEBUG] clck_gen.py:113 IND CLOCK 12546
2026-01-29 02:42:01.360 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:42:01.665 [DEBUG] clck_gen.py:113 IND CLOCK 12648
2026-01-29 02:42:02.143 [DEBUG] clck_gen.py:113 IND CLOCK 12750
2026-01-29 02:42:02.622 [DEBUG] clck_gen.py:113 IND CLOCK 12852
2026-01-29 02:42:03.100 [DEBUG] clck_gen.py:113 IND CLOCK 12954
2026-01-29 02:42:03.579 [DEBUG] clck_gen.py:113 IND CLOCK 13056
2026-01-29 02:42:04.054 [DEBUG] clck_gen.py:113 IND CLOCK 13158
2026-01-29 02:42:04.523 [DEBUG] clck_gen.py:113 IND CLOCK 13260
2026-01-29 02:42:04.996 [DEBUG] clck_gen.py:113 IND CLOCK 13362
2026-01-29 02:42:05.361 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:42:05.364 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:42:05.364 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 02:42:05.365 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 02:42:05.365 [INFO] transceiver.py:205 (MS@172.18.28.22:6700) Frequency hopping disabled
2026-01-29 02:42:05.374 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 02:42:05.374 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 02:42:05.374 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 02:42:05.376 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:42:05.376 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 02:42:05.376 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 02:42:05.376 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.28.22:6700) Recv POWERON CMD
2026-01-29 02:42:05.376 [INFO] ctrl_if_trx.py:109 (MS@172.18.28.22:6700) Starting transceiver...
2026-01-29 02:42:05.414 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:42:05.420 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.28.22:6700) Recv SETFH cmd
2026-01-29 02:42:05.420 [INFO] transceiver.py:201 (MS@172.18.28.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2026-01-29 02:42:05.420 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:42:05.421 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:42:05.473 [DEBUG] clck_gen.py:113 IND CLOCK 13464
2026-01-29 02:42:05.667 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:42:05.952 [DEBUG] clck_gen.py:113 IND CLOCK 13566
2026-01-29 02:42:06.431 [DEBUG] clck_gen.py:113 IND CLOCK 13668
2026-01-29 02:42:06.909 [DEBUG] clck_gen.py:113 IND CLOCK 13770
2026-01-29 02:42:07.388 [DEBUG] clck_gen.py:113 IND CLOCK 13872
2026-01-29 02:42:07.866 [DEBUG] clck_gen.py:113 IND CLOCK 13974
2026-01-29 02:42:08.346 [DEBUG] clck_gen.py:113 IND CLOCK 14076
2026-01-29 02:42:08.822 [DEBUG] clck_gen.py:113 IND CLOCK 14178
2026-01-29 02:42:09.301 [DEBUG] clck_gen.py:113 IND CLOCK 14280
2026-01-29 02:42:09.668 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:42:09.671 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:42:09.672 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 02:42:09.672 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 02:42:09.672 [INFO] transceiver.py:205 (MS@172.18.28.22:6700) Frequency hopping disabled
2026-01-29 02:42:09.692 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 02:42:09.692 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 02:42:09.692 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 02:42:09.694 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:42:09.694 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 02:42:09.694 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 02:42:09.694 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.28.22:6700) Recv POWERON CMD
2026-01-29 02:42:09.694 [INFO] ctrl_if_trx.py:109 (MS@172.18.28.22:6700) Starting transceiver...
2026-01-29 02:42:09.722 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:42:09.724 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.28.22:6700) Recv SETFH cmd
2026-01-29 02:42:09.724 [INFO] transceiver.py:201 (MS@172.18.28.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2026-01-29 02:42:09.724 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:42:09.724 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:42:09.779 [DEBUG] clck_gen.py:113 IND CLOCK 14382
2026-01-29 02:42:09.991 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:42:10.258 [DEBUG] clck_gen.py:113 IND CLOCK 14484
2026-01-29 02:42:10.737 [DEBUG] clck_gen.py:113 IND CLOCK 14586
2026-01-29 02:42:11.215 [DEBUG] clck_gen.py:113 IND CLOCK 14688
2026-01-29 02:42:11.694 [DEBUG] clck_gen.py:113 IND CLOCK 14790
2026-01-29 02:42:12.172 [DEBUG] clck_gen.py:113 IND CLOCK 14892
2026-01-29 02:42:12.650 [DEBUG] clck_gen.py:113 IND CLOCK 14994
2026-01-29 02:42:13.129 [DEBUG] clck_gen.py:113 IND CLOCK 15096
2026-01-29 02:42:13.607 [DEBUG] clck_gen.py:113 IND CLOCK 15198
2026-01-29 02:42:13.992 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:42:13.995 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:42:13.995 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 02:42:13.996 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 02:42:13.996 [INFO] transceiver.py:205 (MS@172.18.28.22:6700) Frequency hopping disabled
2026-01-29 02:42:14.014 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 02:42:14.014 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 02:42:14.014 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 02:42:14.016 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:42:14.016 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 02:42:14.016 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 02:42:14.016 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.28.22:6700) Recv POWERON CMD
2026-01-29 02:42:14.016 [INFO] ctrl_if_trx.py:109 (MS@172.18.28.22:6700) Starting transceiver...
2026-01-29 02:42:14.024 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:42:14.026 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.28.22:6700) Recv SETFH cmd
2026-01-29 02:42:14.026 [INFO] transceiver.py:201 (MS@172.18.28.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2026-01-29 02:42:14.026 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:42:14.026 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:42:14.085 [DEBUG] clck_gen.py:113 IND CLOCK 15300
2026-01-29 02:42:14.476 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:42:14.563 [DEBUG] clck_gen.py:113 IND CLOCK 15402
2026-01-29 02:42:15.042 [DEBUG] clck_gen.py:113 IND CLOCK 15504
2026-01-29 02:42:15.521 [DEBUG] clck_gen.py:113 IND CLOCK 15606
2026-01-29 02:42:16.000 [DEBUG] clck_gen.py:113 IND CLOCK 15708
2026-01-29 02:42:16.478 [DEBUG] clck_gen.py:113 IND CLOCK 15810
2026-01-29 02:42:16.956 [DEBUG] clck_gen.py:113 IND CLOCK 15912
2026-01-29 02:42:17.435 [DEBUG] clck_gen.py:113 IND CLOCK 16014
2026-01-29 02:42:17.913 [DEBUG] clck_gen.py:113 IND CLOCK 16116
2026-01-29 02:42:18.392 [DEBUG] clck_gen.py:113 IND CLOCK 16218
2026-01-29 02:42:18.477 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:42:18.480 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:42:18.481 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 02:42:18.481 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 02:42:18.481 [INFO] transceiver.py:205 (MS@172.18.28.22:6700) Frequency hopping disabled
2026-01-29 02:42:18.500 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 02:42:18.500 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 02:42:18.500 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 02:42:18.501 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:42:18.501 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 02:42:18.501 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 02:42:18.501 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.28.22:6700) Recv POWERON CMD
2026-01-29 02:42:18.501 [INFO] ctrl_if_trx.py:109 (MS@172.18.28.22:6700) Starting transceiver...
2026-01-29 02:42:18.535 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:42:18.540 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.28.22:6700) Recv SETFH cmd
2026-01-29 02:42:18.541 [INFO] transceiver.py:201 (MS@172.18.28.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2026-01-29 02:42:18.541 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:42:18.542 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:42:18.802 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:42:18.870 [DEBUG] clck_gen.py:113 IND CLOCK 16320
2026-01-29 02:42:19.349 [DEBUG] clck_gen.py:113 IND CLOCK 16422
2026-01-29 02:42:19.827 [DEBUG] clck_gen.py:113 IND CLOCK 16524
2026-01-29 02:42:20.306 [DEBUG] clck_gen.py:113 IND CLOCK 16626
2026-01-29 02:42:20.784 [DEBUG] clck_gen.py:113 IND CLOCK 16728
2026-01-29 02:42:21.263 [DEBUG] clck_gen.py:113 IND CLOCK 16830
2026-01-29 02:42:21.742 [DEBUG] clck_gen.py:113 IND CLOCK 16932
2026-01-29 02:42:22.220 [DEBUG] clck_gen.py:113 IND CLOCK 17034
2026-01-29 02:42:22.699 [DEBUG] clck_gen.py:113 IND CLOCK 17136
2026-01-29 02:42:22.803 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:42:22.806 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:42:22.807 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 02:42:22.807 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 02:42:22.807 [INFO] transceiver.py:205 (MS@172.18.28.22:6700) Frequency hopping disabled
2026-01-29 02:42:22.807 [WARNING] transceiver.py:257 (MS@172.18.28.22:6700) RX TRXD message (fn=17161 tn=7 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:42:22.816 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 02:42:22.816 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 02:42:22.816 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 02:42:22.817 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:42:22.817 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 02:42:22.817 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 02:42:22.817 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.28.22:6700) Recv POWERON CMD
2026-01-29 02:42:22.817 [INFO] ctrl_if_trx.py:109 (MS@172.18.28.22:6700) Starting transceiver...
2026-01-29 02:42:22.836 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:42:22.839 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.28.22:6700) Recv SETFH cmd
2026-01-29 02:42:22.840 [INFO] transceiver.py:201 (MS@172.18.28.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2026-01-29 02:42:22.840 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:42:22.840 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:42:23.128 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:42:23.177 [DEBUG] clck_gen.py:113 IND CLOCK 17238
2026-01-29 02:42:23.655 [DEBUG] clck_gen.py:113 IND CLOCK 17340
2026-01-29 02:42:24.133 [DEBUG] clck_gen.py:113 IND CLOCK 17442
2026-01-29 02:42:24.612 [DEBUG] clck_gen.py:113 IND CLOCK 17544
2026-01-29 02:42:25.091 [DEBUG] clck_gen.py:113 IND CLOCK 17646
2026-01-29 02:42:25.570 [DEBUG] clck_gen.py:113 IND CLOCK 17748
2026-01-29 02:42:26.049 [DEBUG] clck_gen.py:113 IND CLOCK 17850
2026-01-29 02:42:26.528 [DEBUG] clck_gen.py:113 IND CLOCK 17952
2026-01-29 02:42:27.006 [DEBUG] clck_gen.py:113 IND CLOCK 18054
2026-01-29 02:42:27.129 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:42:27.131 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:42:27.132 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 02:42:27.132 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 02:42:27.132 [INFO] transceiver.py:205 (MS@172.18.28.22:6700) Frequency hopping disabled
2026-01-29 02:42:27.151 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 02:42:27.151 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 02:42:27.151 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 02:42:27.153 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:42:27.153 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 02:42:27.153 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 02:42:27.153 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.28.22:6700) Recv POWERON CMD
2026-01-29 02:42:27.153 [INFO] ctrl_if_trx.py:109 (MS@172.18.28.22:6700) Starting transceiver...
2026-01-29 02:42:27.195 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:42:27.201 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.28.22:6700) Recv SETFH cmd
2026-01-29 02:42:27.201 [INFO] transceiver.py:201 (MS@172.18.28.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2026-01-29 02:42:27.201 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:42:27.202 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:42:27.452 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:42:27.484 [DEBUG] clck_gen.py:113 IND CLOCK 18156
2026-01-29 02:42:27.963 [DEBUG] clck_gen.py:113 IND CLOCK 18258
2026-01-29 02:42:28.441 [DEBUG] clck_gen.py:113 IND CLOCK 18360
2026-01-29 02:42:28.920 [DEBUG] clck_gen.py:113 IND CLOCK 18462
2026-01-29 02:42:29.399 [DEBUG] clck_gen.py:113 IND CLOCK 18564
2026-01-29 02:42:29.873 [DEBUG] clck_gen.py:113 IND CLOCK 18666
2026-01-29 02:42:30.342 [DEBUG] clck_gen.py:113 IND CLOCK 18768
2026-01-29 02:42:30.815 [DEBUG] clck_gen.py:113 IND CLOCK 18870
2026-01-29 02:42:31.293 [DEBUG] clck_gen.py:113 IND CLOCK 18972
2026-01-29 02:42:31.454 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:42:31.456 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:42:31.457 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 02:42:31.457 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 02:42:31.457 [INFO] transceiver.py:205 (MS@172.18.28.22:6700) Frequency hopping disabled
2026-01-29 02:42:31.471 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 02:42:31.471 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:42:31.471 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:42:31.472 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:42:31.475 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 02:42:31.475 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:42:31.476 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:42:31.476 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:42:31.476 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.28.20:5700) Recv POWEROFF cmd
2026-01-29 02:42:31.476 [INFO] ctrl_if_trx.py:117 (BTS@172.18.28.20:5700) Stopping transceiver...
2026-01-29 02:42:31.476 [INFO] transceiver.py:246 Stopping clock generator
2026-01-29 02:42:31.476 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=19012 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:42:31.477 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=19012 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:42:31.477 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=19012 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:42:31.477 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=19012 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:42:31.477 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=19012 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:42:31.477 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=19012 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:42:31.477 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=19012 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:42:31.477 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=19013 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:42:31.477 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=19013 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:42:31.477 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=19013 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:42:31.477 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=19013 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:42:31.478 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=19013 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:42:31.478 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=19013 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:42:31.478 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=19013 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:42:31.478 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=19013 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:42:36.474 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.28.20:5700) Recv POWEROFF cmd
2026-01-29 02:42:36.475 [INFO] ctrl_if_trx.py:117 (BTS@172.18.28.20:5700) Stopping transceiver...
2026-01-29 02:42:36.476 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:42:36.477 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:42:36.479 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:42:36.482 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 02:42:36.495 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 02:42:36.496 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.28.20:5700) Recv SETFORMAT cmd
2026-01-29 02:42:36.496 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.28.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:42:36.496 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.28.20:5700) Recv SETFORMAT cmd
2026-01-29 02:42:36.496 [INFO] ctrl_if_trx.py:201 (BTS@172.18.28.20:5700) TRXD header version 1 -> 1
2026-01-29 02:42:36.500 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.28.20:5700/1) Recv RXTUNE cmd
2026-01-29 02:42:36.500 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.28.20:5700/1) Recv TXTUNE cmd
2026-01-29 02:42:36.501 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.28.20:5700/1) Recv SETFORMAT cmd
2026-01-29 02:42:36.501 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.28.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:42:36.501 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:42:36.501 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.28.20:5700/1) Recv NOMTXPOWER cmd
2026-01-29 02:42:36.501 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.28.20:5700/1) Recv SETFORMAT cmd
2026-01-29 02:42:36.501 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.28.20:5700/1) TRXD header version 1 -> 1
2026-01-29 02:42:36.503 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.28.20:5700/2) Recv RXTUNE cmd
2026-01-29 02:42:36.503 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.28.20:5700/2) Recv TXTUNE cmd
2026-01-29 02:42:36.504 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.28.20:5700/2) Recv SETFORMAT cmd
2026-01-29 02:42:36.504 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.28.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:42:36.504 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:42:36.504 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.28.20:5700/2) Recv NOMTXPOWER cmd
2026-01-29 02:42:36.504 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.28.20:5700/2) Recv SETFORMAT cmd
2026-01-29 02:42:36.504 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.28.20:5700/2) TRXD header version 1 -> 1
2026-01-29 02:42:36.505 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.28.20:5700/3) Recv RXTUNE cmd
2026-01-29 02:42:36.506 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.28.20:5700/3) Recv TXTUNE cmd
2026-01-29 02:42:36.506 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.28.20:5700/3) Recv SETFORMAT cmd
2026-01-29 02:42:36.506 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.28.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:42:36.506 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:42:36.506 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.28.20:5700/3) Recv NOMTXPOWER cmd
2026-01-29 02:42:36.506 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.28.20:5700/3) Recv SETFORMAT cmd
2026-01-29 02:42:36.506 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.28.20:5700/3) TRXD header version 1 -> 1
2026-01-29 02:42:36.508 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.28.20:5700) Recv RXTUNE cmd
2026-01-29 02:42:36.508 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETTSC
2026-01-29 02:42:36.508 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETTSC
2026-01-29 02:42:36.508 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETTSC
2026-01-29 02:42:36.508 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.28.20:5700) Recv TXTUNE cmd
2026-01-29 02:42:36.508 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETRXGAIN
2026-01-29 02:42:36.508 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETRXGAIN
2026-01-29 02:42:36.508 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETRXGAIN
2026-01-29 02:42:36.508 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETTSC
2026-01-29 02:42:36.508 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:42:36.508 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:42:36.508 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:42:36.508 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.28.20:5700) Recv NOMTXPOWER cmd
2026-01-29 02:42:36.508 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:42:36.508 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:42:36.508 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:42:36.508 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.28.20:5700) Recv POWERON CMD
2026-01-29 02:42:36.508 [INFO] ctrl_if_trx.py:109 (BTS@172.18.28.20:5700) Starting transceiver...
2026-01-29 02:42:36.508 [INFO] transceiver.py:243 Starting clock generator
2026-01-29 02:42:36.508 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-01-29 02:42:36.508 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:42:36.508 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:42:36.508 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:42:36.508 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETRXGAIN
2026-01-29 02:42:36.509 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:42:36.509 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:42:36.509 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:42:36.509 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:42:36.509 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:42:36.509 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:42:36.509 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:42:36.509 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:42:36.509 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:42:36.509 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:42:36.509 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:42:36.509 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:42:36.509 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:42:36.509 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:42:36.509 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:42:36.509 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:42:36.509 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:42:36.509 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:42:36.509 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:42:36.509 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:42:36.509 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:42:36.509 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:42:36.509 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:42:36.509 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:42:36.509 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 02:42:36.509 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:42:36.509 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.28.20:5700) Recv POWEROFF cmd
2026-01-29 02:42:36.509 [INFO] ctrl_if_trx.py:117 (BTS@172.18.28.20:5700) Stopping transceiver...
2026-01-29 02:42:36.509 [INFO] transceiver.py:246 Stopping clock generator
2026-01-29 02:42:36.510 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:42:41.513 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.28.20:5700) Recv POWEROFF cmd
2026-01-29 02:42:41.513 [INFO] ctrl_if_trx.py:117 (BTS@172.18.28.20:5700) Stopping transceiver...
2026-01-29 02:42:41.514 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:42:41.516 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:42:41.517 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:42:41.517 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 02:42:41.523 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 02:42:41.523 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.28.20:5700) Recv SETFORMAT cmd
2026-01-29 02:42:41.523 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.28.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:42:41.523 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.28.20:5700) Recv SETFORMAT cmd
2026-01-29 02:42:41.523 [INFO] ctrl_if_trx.py:201 (BTS@172.18.28.20:5700) TRXD header version 1 -> 1
2026-01-29 02:42:41.524 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.28.20:5700/1) Recv RXTUNE cmd
2026-01-29 02:42:41.524 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.28.20:5700/1) Recv TXTUNE cmd
2026-01-29 02:42:41.524 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.28.20:5700/1) Recv SETFORMAT cmd
2026-01-29 02:42:41.524 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.28.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:42:41.524 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:42:41.524 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.28.20:5700/1) Recv NOMTXPOWER cmd
2026-01-29 02:42:41.525 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.28.20:5700/1) Recv SETFORMAT cmd
2026-01-29 02:42:41.525 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.28.20:5700/1) TRXD header version 1 -> 1
2026-01-29 02:42:41.525 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.28.20:5700/2) Recv RXTUNE cmd
2026-01-29 02:42:41.525 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.28.20:5700/2) Recv TXTUNE cmd
2026-01-29 02:42:41.525 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.28.20:5700/2) Recv SETFORMAT cmd
2026-01-29 02:42:41.525 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.28.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:42:41.525 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:42:41.525 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.28.20:5700/2) Recv NOMTXPOWER cmd
2026-01-29 02:42:41.525 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.28.20:5700/2) Recv SETFORMAT cmd
2026-01-29 02:42:41.525 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.28.20:5700/2) TRXD header version 1 -> 1
2026-01-29 02:42:41.526 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.28.20:5700/3) Recv RXTUNE cmd
2026-01-29 02:42:41.526 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.28.20:5700/3) Recv TXTUNE cmd
2026-01-29 02:42:41.526 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.28.20:5700/3) Recv SETFORMAT cmd
2026-01-29 02:42:41.526 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.28.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:42:41.526 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:42:41.526 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.28.20:5700/3) Recv NOMTXPOWER cmd
2026-01-29 02:42:41.526 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.28.20:5700/3) Recv SETFORMAT cmd
2026-01-29 02:42:41.526 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.28.20:5700/3) TRXD header version 1 -> 1
2026-01-29 02:42:41.527 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.28.20:5700) Recv RXTUNE cmd
2026-01-29 02:42:41.527 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETTSC
2026-01-29 02:42:41.527 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETTSC
2026-01-29 02:42:41.527 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETTSC
2026-01-29 02:42:41.527 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.28.20:5700) Recv TXTUNE cmd
2026-01-29 02:42:41.527 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETRXGAIN
2026-01-29 02:42:41.527 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETRXGAIN
2026-01-29 02:42:41.527 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETRXGAIN
2026-01-29 02:42:41.527 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETTSC
2026-01-29 02:42:41.527 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:42:41.527 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:42:41.527 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.28.20:5700) Recv NOMTXPOWER cmd
2026-01-29 02:42:41.527 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:42:41.527 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:42:41.527 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:42:41.527 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.28.20:5700) Recv POWERON CMD
2026-01-29 02:42:41.527 [INFO] ctrl_if_trx.py:109 (BTS@172.18.28.20:5700) Starting transceiver...
2026-01-29 02:42:41.527 [INFO] transceiver.py:243 Starting clock generator
2026-01-29 02:42:41.528 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-01-29 02:42:41.528 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:42:41.528 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:42:41.528 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:42:41.528 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETRXGAIN
2026-01-29 02:42:41.528 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:42:41.528 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:42:41.528 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:42:41.528 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:42:41.528 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:42:41.528 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:42:41.528 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:42:41.528 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:42:41.528 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:42:41.528 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:42:41.528 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:42:41.528 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:42:41.528 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:42:41.528 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:42:41.528 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:42:41.528 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:42:41.528 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:42:41.528 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:42:41.528 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:42:41.528 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:42:41.528 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:42:41.528 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:42:41.528 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:42:41.528 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:42:41.532 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-01-29 02:42:42.009 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-01-29 02:42:42.040 [DEBUG] fake_trx.py:278 (BTS@172.18.28.20:5700) Recv FAKE_TOA cmd
2026-01-29 02:42:42.041 [DEBUG] fake_trx.py:297 (BTS@172.18.28.20:5700) Recv FAKE_RSSI cmd
2026-01-29 02:42:42.041 [DEBUG] fake_trx.py:322 (BTS@172.18.28.20:5700) Recv FAKE_CI cmd
2026-01-29 02:42:42.042 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:42:42.047 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 02:42:42.047 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 02:42:42.048 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 02:42:42.049 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:42:42.049 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 02:42:42.049 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 02:42:42.049 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.28.22:6700) Recv POWERON CMD
2026-01-29 02:42:42.049 [INFO] ctrl_if_trx.py:109 (MS@172.18.28.22:6700) Starting transceiver...
2026-01-29 02:42:42.052 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:42:42.053 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 02:42:42.053 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 02:42:42.053 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:42:42.053 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:42:42.211 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:42:42.213 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:42:42.214 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 02:42:42.214 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 02:42:42.226 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 02:42:42.226 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 02:42:42.227 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 02:42:42.229 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:42:42.229 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 02:42:42.229 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 02:42:42.229 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.28.22:6700) Recv POWERON CMD
2026-01-29 02:42:42.229 [INFO] ctrl_if_trx.py:109 (MS@172.18.28.22:6700) Starting transceiver...
2026-01-29 02:42:42.270 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:42:42.275 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 02:42:42.275 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 02:42:42.275 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:42:42.275 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:42:42.483 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-01-29 02:42:42.530 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:42:42.530 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 02:42:42.531 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:42:42.532 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:42:42.700 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:42:42.703 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:42:42.704 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 02:42:42.704 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 02:42:42.722 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 02:42:42.722 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 02:42:42.722 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 02:42:42.725 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:42:42.725 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 02:42:42.725 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 02:42:42.725 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.28.22:6700) Recv POWERON CMD
2026-01-29 02:42:42.725 [INFO] ctrl_if_trx.py:109 (MS@172.18.28.22:6700) Starting transceiver...
2026-01-29 02:42:42.770 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:42:42.772 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 02:42:42.772 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 02:42:42.772 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:42:42.772 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:42:42.915 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:42:42.916 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:42:42.916 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 02:42:42.916 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 02:42:42.922 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 02:42:42.922 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 02:42:42.922 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 02:42:42.924 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:42:42.924 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 02:42:42.924 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 02:42:42.924 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.28.22:6700) Recv POWERON CMD
2026-01-29 02:42:42.924 [INFO] ctrl_if_trx.py:109 (MS@172.18.28.22:6700) Starting transceiver...
2026-01-29 02:42:42.955 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-01-29 02:42:42.966 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:42:42.969 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 02:42:42.969 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 02:42:42.969 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:42:42.969 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:42:43.404 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:42:43.405 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:42:43.405 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 02:42:43.405 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 02:42:43.411 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 02:42:43.411 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 02:42:43.412 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 02:42:43.414 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:42:43.414 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 02:42:43.414 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 02:42:43.414 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.28.22:6700) Recv POWERON CMD
2026-01-29 02:42:43.414 [INFO] ctrl_if_trx.py:109 (MS@172.18.28.22:6700) Starting transceiver...
2026-01-29 02:42:43.430 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-01-29 02:42:43.454 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:42:43.455 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 02:42:43.455 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 02:42:43.455 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:42:43.455 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:42:43.531 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 02:42:43.531 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:42:43.531 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:42:43.532 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:42:43.904 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-01-29 02:42:43.934 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:42:43.935 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:42:43.935 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 02:42:43.935 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 02:42:43.941 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 02:42:43.941 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 02:42:43.941 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 02:42:43.943 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:42:43.943 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 02:42:43.943 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 02:42:43.943 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.28.22:6700) Recv POWERON CMD
2026-01-29 02:42:43.943 [INFO] ctrl_if_trx.py:109 (MS@172.18.28.22:6700) Starting transceiver...
2026-01-29 02:42:43.990 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:42:43.991 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.28.22:6700) Recv SETFH cmd
2026-01-29 02:42:43.991 [INFO] transceiver.py:201 (MS@172.18.28.22:6700) Frequency hopping configured: hsn=2, maio=0, ma_len=2
2026-01-29 02:42:43.991 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:42:43.992 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:42:44.374 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-01-29 02:42:44.474 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:42:44.475 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:42:44.475 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 02:42:44.475 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 02:42:44.475 [INFO] transceiver.py:205 (MS@172.18.28.22:6700) Frequency hopping disabled
2026-01-29 02:42:44.481 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 02:42:44.481 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 02:42:44.481 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 02:42:44.483 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:42:44.483 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 02:42:44.483 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 02:42:44.483 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.28.22:6700) Recv POWERON CMD
2026-01-29 02:42:44.483 [INFO] ctrl_if_trx.py:109 (MS@172.18.28.22:6700) Starting transceiver...
2026-01-29 02:42:44.530 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:42:44.531 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.28.22:6700) Recv SETFH cmd
2026-01-29 02:42:44.531 [INFO] transceiver.py:201 (MS@172.18.28.22:6700) Frequency hopping configured: hsn=3, maio=3, ma_len=4
2026-01-29 02:42:44.531 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:42:44.531 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:42:44.532 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:42:44.532 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 02:42:44.532 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:42:44.533 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:42:44.843 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-01-29 02:42:45.016 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:42:45.018 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:42:45.019 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 02:42:45.019 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 02:42:45.019 [INFO] transceiver.py:205 (MS@172.18.28.22:6700) Frequency hopping disabled
2026-01-29 02:42:45.038 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 02:42:45.038 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 02:42:45.038 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 02:42:45.040 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:42:45.040 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 02:42:45.040 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 02:42:45.040 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.28.22:6700) Recv POWERON CMD
2026-01-29 02:42:45.040 [INFO] ctrl_if_trx.py:109 (MS@172.18.28.22:6700) Starting transceiver...
2026-01-29 02:42:45.086 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:42:45.087 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:42:45.091 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 02:42:45.092 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 02:42:45.092 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:42:45.092 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:42:45.315 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-01-29 02:42:45.533 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 02:42:45.533 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:42:45.533 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:42:45.533 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:42:45.558 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:42:45.561 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:42:45.562 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 02:42:45.562 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 02:42:45.582 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 02:42:45.582 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 02:42:45.583 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 02:42:45.585 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:42:45.585 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 02:42:45.585 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 02:42:45.585 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.28.22:6700) Recv POWERON CMD
2026-01-29 02:42:45.585 [INFO] ctrl_if_trx.py:109 (MS@172.18.28.22:6700) Starting transceiver...
2026-01-29 02:42:45.626 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:42:45.631 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 02:42:45.632 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 02:42:45.632 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:42:45.633 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:42:45.789 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-01-29 02:42:46.102 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:42:46.105 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:42:46.106 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 02:42:46.106 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 02:42:46.125 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 02:42:46.125 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 02:42:46.125 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 02:42:46.127 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:42:46.127 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 02:42:46.127 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 02:42:46.127 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.28.22:6700) Recv POWERON CMD
2026-01-29 02:42:46.127 [INFO] ctrl_if_trx.py:109 (MS@172.18.28.22:6700) Starting transceiver...
2026-01-29 02:42:46.174 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:42:46.175 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:42:46.180 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 02:42:46.181 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 02:42:46.181 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:42:46.181 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:42:46.264 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-01-29 02:42:46.534 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 02:42:46.534 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:42:46.534 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:42:46.534 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:42:46.737 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-01-29 02:42:47.009 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:42:47.011 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:42:47.011 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 02:42:47.012 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 02:42:47.030 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 02:42:47.031 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 02:42:47.031 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 02:42:47.033 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:42:47.033 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 02:42:47.033 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 02:42:47.033 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.28.22:6700) Recv POWERON CMD
2026-01-29 02:42:47.033 [INFO] ctrl_if_trx.py:109 (MS@172.18.28.22:6700) Starting transceiver...
2026-01-29 02:42:47.074 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:42:47.081 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.28.22:6700) Recv SETFH cmd
2026-01-29 02:42:47.081 [INFO] transceiver.py:201 (MS@172.18.28.22:6700) Frequency hopping configured: hsn=5, maio=0, ma_len=4
2026-01-29 02:42:47.081 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:42:47.081 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:42:47.210 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-01-29 02:42:47.488 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:42:47.491 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:42:47.492 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 02:42:47.492 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 02:42:47.492 [INFO] transceiver.py:205 (MS@172.18.28.22:6700) Frequency hopping disabled
2026-01-29 02:42:47.501 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 02:42:47.501 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 02:42:47.501 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 02:42:47.503 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:42:47.503 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 02:42:47.503 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 02:42:47.503 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.28.22:6700) Recv POWERON CMD
2026-01-29 02:42:47.503 [INFO] ctrl_if_trx.py:109 (MS@172.18.28.22:6700) Starting transceiver...
2026-01-29 02:42:47.533 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:42:47.534 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.28.22:6700) Recv SETFH cmd
2026-01-29 02:42:47.534 [INFO] transceiver.py:201 (MS@172.18.28.22:6700) Frequency hopping configured: hsn=5, maio=0, ma_len=4
2026-01-29 02:42:47.534 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:42:47.534 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:42:47.679 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-01-29 02:42:48.026 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:42:48.026 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:42:48.027 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 02:42:48.027 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 02:42:48.027 [INFO] transceiver.py:205 (MS@172.18.28.22:6700) Frequency hopping disabled
2026-01-29 02:42:48.033 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 02:42:48.033 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 02:42:48.033 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 02:42:48.035 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:42:48.035 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 02:42:48.035 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 02:42:48.035 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.28.22:6700) Recv POWERON CMD
2026-01-29 02:42:48.035 [INFO] ctrl_if_trx.py:109 (MS@172.18.28.22:6700) Starting transceiver...
2026-01-29 02:42:48.078 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:42:48.079 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.28.22:6700) Recv SETFH cmd
2026-01-29 02:42:48.079 [INFO] transceiver.py:201 (MS@172.18.28.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2026-01-29 02:42:48.079 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:42:48.079 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:42:48.148 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-01-29 02:42:48.301 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:42:48.304 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:42:48.305 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 02:42:48.305 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 02:42:48.305 [INFO] transceiver.py:205 (MS@172.18.28.22:6700) Frequency hopping disabled
2026-01-29 02:42:48.324 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 02:42:48.324 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 02:42:48.324 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 02:42:48.326 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:42:48.327 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 02:42:48.327 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 02:42:48.327 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.28.22:6700) Recv POWERON CMD
2026-01-29 02:42:48.327 [INFO] ctrl_if_trx.py:109 (MS@172.18.28.22:6700) Starting transceiver...
2026-01-29 02:42:48.381 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:42:48.386 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.28.22:6700) Recv SETFH cmd
2026-01-29 02:42:48.387 [INFO] transceiver.py:201 (MS@172.18.28.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2026-01-29 02:42:48.387 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:42:48.387 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:42:48.623 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-01-29 02:42:48.798 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:42:48.801 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:42:48.801 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 02:42:48.801 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 02:42:48.801 [INFO] transceiver.py:205 (MS@172.18.28.22:6700) Frequency hopping disabled
2026-01-29 02:42:48.811 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 02:42:48.811 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 02:42:48.811 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 02:42:48.813 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:42:48.813 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 02:42:48.813 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 02:42:48.813 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.28.22:6700) Recv POWERON CMD
2026-01-29 02:42:48.813 [INFO] ctrl_if_trx.py:109 (MS@172.18.28.22:6700) Starting transceiver...
2026-01-29 02:42:48.859 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:42:48.864 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.28.22:6700) Recv SETFH cmd
2026-01-29 02:42:48.865 [INFO] transceiver.py:201 (MS@172.18.28.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2026-01-29 02:42:48.865 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:42:48.865 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:42:49.094 [DEBUG] clck_gen.py:113 IND CLOCK 1632
2026-01-29 02:42:49.287 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:42:49.290 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:42:49.291 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 02:42:49.291 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 02:42:49.291 [INFO] transceiver.py:205 (MS@172.18.28.22:6700) Frequency hopping disabled
2026-01-29 02:42:49.301 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 02:42:49.301 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 02:42:49.301 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 02:42:49.302 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:42:49.302 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 02:42:49.302 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 02:42:49.303 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.28.22:6700) Recv POWERON CMD
2026-01-29 02:42:49.303 [INFO] ctrl_if_trx.py:109 (MS@172.18.28.22:6700) Starting transceiver...
2026-01-29 02:42:49.346 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:42:49.352 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.28.22:6700) Recv SETFH cmd
2026-01-29 02:42:49.352 [INFO] transceiver.py:201 (MS@172.18.28.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2026-01-29 02:42:49.353 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:42:49.353 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:42:49.568 [DEBUG] clck_gen.py:113 IND CLOCK 1734
2026-01-29 02:42:49.795 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:42:49.797 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:42:49.798 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 02:42:49.798 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 02:42:49.798 [INFO] transceiver.py:205 (MS@172.18.28.22:6700) Frequency hopping disabled
2026-01-29 02:42:49.819 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 02:42:49.819 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 02:42:49.819 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 02:42:49.820 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:42:49.821 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 02:42:49.821 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 02:42:49.821 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.28.22:6700) Recv POWERON CMD
2026-01-29 02:42:49.821 [INFO] ctrl_if_trx.py:109 (MS@172.18.28.22:6700) Starting transceiver...
2026-01-29 02:42:49.862 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:42:49.864 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.28.22:6700) Recv SETFH cmd
2026-01-29 02:42:49.864 [INFO] transceiver.py:201 (MS@172.18.28.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2026-01-29 02:42:49.864 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:42:49.864 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:42:49.953 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:42:49.954 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:42:49.954 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 02:42:49.954 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 02:42:49.954 [INFO] transceiver.py:205 (MS@172.18.28.22:6700) Frequency hopping disabled
2026-01-29 02:42:49.960 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 02:42:49.960 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 02:42:49.960 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 02:42:49.962 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:42:49.962 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 02:42:49.962 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 02:42:49.962 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.28.22:6700) Recv POWERON CMD
2026-01-29 02:42:49.962 [INFO] ctrl_if_trx.py:109 (MS@172.18.28.22:6700) Starting transceiver...
2026-01-29 02:42:50.006 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:42:50.007 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.28.22:6700) Recv SETFH cmd
2026-01-29 02:42:50.007 [INFO] transceiver.py:201 (MS@172.18.28.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2026-01-29 02:42:50.007 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:42:50.007 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:42:50.041 [DEBUG] clck_gen.py:113 IND CLOCK 1836
2026-01-29 02:42:50.449 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:42:50.450 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:42:50.450 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 02:42:50.450 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 02:42:50.450 [INFO] transceiver.py:205 (MS@172.18.28.22:6700) Frequency hopping disabled
2026-01-29 02:42:50.456 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 02:42:50.456 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 02:42:50.456 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 02:42:50.457 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:42:50.457 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 02:42:50.457 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 02:42:50.457 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.28.22:6700) Recv POWERON CMD
2026-01-29 02:42:50.457 [INFO] ctrl_if_trx.py:109 (MS@172.18.28.22:6700) Starting transceiver...
2026-01-29 02:42:50.509 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:42:50.510 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.28.22:6700) Recv SETFH cmd
2026-01-29 02:42:50.510 [INFO] transceiver.py:201 (MS@172.18.28.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2026-01-29 02:42:50.510 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:42:50.510 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:42:50.510 [DEBUG] clck_gen.py:113 IND CLOCK 1938
2026-01-29 02:42:50.933 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:42:50.934 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:42:50.934 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 02:42:50.934 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 02:42:50.934 [INFO] transceiver.py:205 (MS@172.18.28.22:6700) Frequency hopping disabled
2026-01-29 02:42:50.940 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 02:42:50.941 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 02:42:50.941 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 02:42:50.942 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:42:50.942 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 02:42:50.942 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 02:42:50.942 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.28.22:6700) Recv POWERON CMD
2026-01-29 02:42:50.942 [INFO] ctrl_if_trx.py:109 (MS@172.18.28.22:6700) Starting transceiver...
2026-01-29 02:42:50.979 [DEBUG] clck_gen.py:113 IND CLOCK 2040
2026-01-29 02:42:50.986 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:42:50.987 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.28.22:6700) Recv SETFH cmd
2026-01-29 02:42:50.987 [INFO] transceiver.py:201 (MS@172.18.28.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2026-01-29 02:42:50.987 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:42:50.987 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:42:51.423 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:42:51.424 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:42:51.424 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 02:42:51.424 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 02:42:51.424 [INFO] transceiver.py:205 (MS@172.18.28.22:6700) Frequency hopping disabled
2026-01-29 02:42:51.426 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 02:42:51.426 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:42:51.426 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:42:51.426 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:42:51.426 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 02:42:51.427 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:42:51.427 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:42:51.427 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:42:51.427 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.28.20:5700) Recv POWEROFF cmd
2026-01-29 02:42:51.427 [INFO] ctrl_if_trx.py:117 (BTS@172.18.28.20:5700) Stopping transceiver...
2026-01-29 02:42:51.427 [INFO] transceiver.py:246 Stopping clock generator
2026-01-29 02:42:51.427 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=2139 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:42:51.427 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=2139 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:42:51.427 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=2139 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:42:51.427 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=2139 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:42:51.427 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=2139 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:42:51.427 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=2139 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:42:56.427 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.28.20:5700) Recv POWEROFF cmd
2026-01-29 02:42:56.427 [INFO] ctrl_if_trx.py:117 (BTS@172.18.28.20:5700) Stopping transceiver...
2026-01-29 02:42:56.427 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:42:56.427 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:42:56.428 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:42:56.428 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 02:42:56.431 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 02:42:56.432 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.28.20:5700) Recv SETFORMAT cmd
2026-01-29 02:42:56.432 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.28.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:42:56.432 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.28.20:5700) Recv SETFORMAT cmd
2026-01-29 02:42:56.432 [INFO] ctrl_if_trx.py:201 (BTS@172.18.28.20:5700) TRXD header version 1 -> 1
2026-01-29 02:42:56.432 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.28.20:5700/1) Recv RXTUNE cmd
2026-01-29 02:42:56.432 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.28.20:5700/1) Recv TXTUNE cmd
2026-01-29 02:42:56.432 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.28.20:5700/1) Recv SETFORMAT cmd
2026-01-29 02:42:56.432 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.28.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:42:56.432 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:42:56.433 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.28.20:5700/1) Recv NOMTXPOWER cmd
2026-01-29 02:42:56.433 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.28.20:5700/1) Recv SETFORMAT cmd
2026-01-29 02:42:56.433 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.28.20:5700/1) TRXD header version 1 -> 1
2026-01-29 02:42:56.433 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.28.20:5700/2) Recv RXTUNE cmd
2026-01-29 02:42:56.433 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.28.20:5700/2) Recv TXTUNE cmd
2026-01-29 02:42:56.433 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.28.20:5700/2) Recv SETFORMAT cmd
2026-01-29 02:42:56.433 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.28.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:42:56.433 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:42:56.433 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.28.20:5700/2) Recv NOMTXPOWER cmd
2026-01-29 02:42:56.433 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.28.20:5700/2) Recv SETFORMAT cmd
2026-01-29 02:42:56.433 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.28.20:5700/2) TRXD header version 1 -> 1
2026-01-29 02:42:56.434 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.28.20:5700/3) Recv RXTUNE cmd
2026-01-29 02:42:56.434 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.28.20:5700/3) Recv TXTUNE cmd
2026-01-29 02:42:56.434 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.28.20:5700/3) Recv SETFORMAT cmd
2026-01-29 02:42:56.434 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.28.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:42:56.434 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:42:56.434 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.28.20:5700/3) Recv NOMTXPOWER cmd
2026-01-29 02:42:56.434 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.28.20:5700/3) Recv SETFORMAT cmd
2026-01-29 02:42:56.434 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.28.20:5700/3) TRXD header version 1 -> 1
2026-01-29 02:42:56.436 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.28.20:5700) Recv RXTUNE cmd
2026-01-29 02:42:56.436 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETTSC
2026-01-29 02:42:56.436 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETTSC
2026-01-29 02:42:56.436 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETTSC
2026-01-29 02:42:56.436 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.28.20:5700) Recv TXTUNE cmd
2026-01-29 02:42:56.436 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETRXGAIN
2026-01-29 02:42:56.436 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETRXGAIN
2026-01-29 02:42:56.436 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETRXGAIN
2026-01-29 02:42:56.436 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETTSC
2026-01-29 02:42:56.436 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:42:56.436 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:42:56.436 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.28.20:5700) Recv NOMTXPOWER cmd
2026-01-29 02:42:56.436 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:42:56.436 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:42:56.436 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:42:56.436 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.28.20:5700) Recv POWERON CMD
2026-01-29 02:42:56.436 [INFO] ctrl_if_trx.py:109 (BTS@172.18.28.20:5700) Starting transceiver...
2026-01-29 02:42:56.436 [INFO] transceiver.py:243 Starting clock generator
2026-01-29 02:42:56.436 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-01-29 02:42:56.436 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:42:56.436 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:42:56.436 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:42:56.436 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETRXGAIN
2026-01-29 02:42:56.436 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:42:56.436 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:42:56.436 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:42:56.436 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:42:56.436 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:42:56.436 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:42:56.436 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:42:56.436 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:42:56.436 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:42:56.436 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:42:56.436 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:42:56.436 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:42:56.436 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:42:56.436 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:42:56.436 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:42:56.436 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:42:56.436 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:42:56.436 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:42:56.437 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:42:56.437 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:42:56.437 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:42:56.437 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:42:56.437 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:42:56.437 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:42:56.441 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-01-29 02:42:56.916 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-01-29 02:42:56.949 [DEBUG] fake_trx.py:278 (BTS@172.18.28.20:5700) Recv FAKE_TOA cmd
2026-01-29 02:42:56.949 [DEBUG] fake_trx.py:297 (BTS@172.18.28.20:5700) Recv FAKE_RSSI cmd
2026-01-29 02:42:56.950 [DEBUG] fake_trx.py:322 (BTS@172.18.28.20:5700) Recv FAKE_CI cmd
2026-01-29 02:42:56.950 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:42:56.956 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 02:42:56.956 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 02:42:56.956 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 02:42:56.957 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:42:56.958 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 02:42:56.958 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 02:42:56.958 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.28.22:6700) Recv POWERON CMD
2026-01-29 02:42:56.958 [INFO] ctrl_if_trx.py:109 (MS@172.18.28.22:6700) Starting transceiver...
2026-01-29 02:42:56.959 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:42:56.960 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 02:42:56.960 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 02:42:56.960 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:42:56.960 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:42:57.389 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-01-29 02:42:57.438 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 02:42:57.438 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:42:57.439 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:42:57.440 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:42:57.589 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:42:57.593 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:42:57.864 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-01-29 02:42:58.065 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:42:58.068 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:42:58.069 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 02:42:58.069 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 02:42:58.078 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 02:42:58.078 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 02:42:58.078 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 02:42:58.080 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:42:58.080 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 02:42:58.080 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 02:42:58.080 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.28.22:6700) Recv POWERON CMD
2026-01-29 02:42:58.080 [INFO] ctrl_if_trx.py:109 (MS@172.18.28.22:6700) Starting transceiver...
2026-01-29 02:42:58.122 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:42:58.127 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 02:42:58.128 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 02:42:58.128 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:42:58.129 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:42:58.339 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-01-29 02:42:58.438 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 02:42:58.439 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:42:58.440 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:42:58.441 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:42:58.814 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-01-29 02:42:59.030 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:42:59.035 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:42:59.290 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-01-29 02:42:59.439 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 02:42:59.439 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:42:59.440 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:42:59.442 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:42:59.510 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:42:59.513 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:42:59.513 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 02:42:59.513 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 02:42:59.513 [WARNING] transceiver.py:257 (MS@172.18.28.22:6700) RX TRXD message (fn=662 tn=3 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:42:59.522 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 02:42:59.522 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 02:42:59.522 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 02:42:59.523 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:42:59.524 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 02:42:59.524 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 02:42:59.524 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.28.22:6700) Recv POWERON CMD
2026-01-29 02:42:59.524 [INFO] ctrl_if_trx.py:109 (MS@172.18.28.22:6700) Starting transceiver...
2026-01-29 02:42:59.572 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:42:59.578 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 02:42:59.578 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 02:42:59.578 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:42:59.578 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:42:59.762 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-01-29 02:43:00.198 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:43:00.202 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:43:00.236 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-01-29 02:43:00.440 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 02:43:00.440 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:43:00.441 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:43:00.443 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:43:00.666 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:43:00.667 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:43:00.667 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 02:43:00.667 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 02:43:00.673 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 02:43:00.673 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 02:43:00.673 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 02:43:00.675 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:43:00.675 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 02:43:00.675 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 02:43:00.675 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.28.22:6700) Recv POWERON CMD
2026-01-29 02:43:00.675 [INFO] ctrl_if_trx.py:109 (MS@172.18.28.22:6700) Starting transceiver...
2026-01-29 02:43:00.710 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-01-29 02:43:00.718 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:43:00.724 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 02:43:00.724 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 02:43:00.725 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:43:00.725 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:43:01.186 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-01-29 02:43:01.441 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 02:43:01.441 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:43:01.441 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:43:01.444 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:43:01.642 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:43:01.646 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:43:01.663 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-01-29 02:43:02.118 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:43:02.121 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:43:02.122 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 02:43:02.122 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 02:43:02.133 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-01-29 02:43:02.141 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 02:43:02.141 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 02:43:02.141 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 02:43:02.143 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:43:02.143 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 02:43:02.143 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 02:43:02.143 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.28.22:6700) Recv POWERON CMD
2026-01-29 02:43:02.143 [INFO] ctrl_if_trx.py:109 (MS@172.18.28.22:6700) Starting transceiver...
2026-01-29 02:43:02.186 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:43:02.191 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 02:43:02.191 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 02:43:02.191 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:43:02.192 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:43:02.608 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-01-29 02:43:03.083 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-01-29 02:43:03.197 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:43:03.201 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:43:03.561 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-01-29 02:43:03.689 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:43:03.692 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:43:03.692 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 02:43:03.693 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 02:43:03.711 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 02:43:03.711 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 02:43:03.712 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 02:43:03.714 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:43:03.714 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 02:43:03.714 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 02:43:03.714 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.28.22:6700) Recv POWERON CMD
2026-01-29 02:43:03.714 [INFO] ctrl_if_trx.py:109 (MS@172.18.28.22:6700) Starting transceiver...
2026-01-29 02:43:03.754 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:43:03.759 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.28.22:6700) Recv SETFH cmd
2026-01-29 02:43:03.759 [INFO] transceiver.py:201 (MS@172.18.28.22:6700) Frequency hopping configured: hsn=2, maio=0, ma_len=2
2026-01-29 02:43:03.760 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:43:03.760 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:43:04.039 [DEBUG] clck_gen.py:113 IND CLOCK 1632
2026-01-29 02:43:04.518 [DEBUG] clck_gen.py:113 IND CLOCK 1734
2026-01-29 02:43:04.725 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:43:04.729 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:43:04.997 [DEBUG] clck_gen.py:113 IND CLOCK 1836
2026-01-29 02:43:05.212 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:43:05.215 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:43:05.215 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 02:43:05.215 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 02:43:05.215 [INFO] transceiver.py:205 (MS@172.18.28.22:6700) Frequency hopping disabled
2026-01-29 02:43:05.215 [WARNING] transceiver.py:257 (MS@172.18.28.22:6700) RX TRXD message (fn=1885 tn=5 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:43:05.235 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 02:43:05.235 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 02:43:05.235 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 02:43:05.237 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:43:05.237 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 02:43:05.237 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 02:43:05.237 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.28.22:6700) Recv POWERON CMD
2026-01-29 02:43:05.237 [INFO] ctrl_if_trx.py:109 (MS@172.18.28.22:6700) Starting transceiver...
2026-01-29 02:43:05.279 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:43:05.284 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.28.22:6700) Recv SETFH cmd
2026-01-29 02:43:05.284 [INFO] transceiver.py:201 (MS@172.18.28.22:6700) Frequency hopping configured: hsn=3, maio=3, ma_len=4
2026-01-29 02:43:05.285 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:43:05.285 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:43:05.474 [DEBUG] clck_gen.py:113 IND CLOCK 1938
2026-01-29 02:43:05.953 [DEBUG] clck_gen.py:113 IND CLOCK 2040
2026-01-29 02:43:06.248 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:43:06.253 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:43:06.432 [DEBUG] clck_gen.py:113 IND CLOCK 2142
2026-01-29 02:43:06.736 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:43:06.739 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:43:06.739 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 02:43:06.740 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 02:43:06.740 [INFO] transceiver.py:205 (MS@172.18.28.22:6700) Frequency hopping disabled
2026-01-29 02:43:06.759 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 02:43:06.759 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 02:43:06.759 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 02:43:06.761 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:43:06.761 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 02:43:06.761 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 02:43:06.761 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.28.22:6700) Recv POWERON CMD
2026-01-29 02:43:06.761 [INFO] ctrl_if_trx.py:109 (MS@172.18.28.22:6700) Starting transceiver...
2026-01-29 02:43:06.807 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:43:06.808 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:43:06.812 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 02:43:06.813 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 02:43:06.813 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:43:06.814 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:43:06.911 [DEBUG] clck_gen.py:113 IND CLOCK 2244
2026-01-29 02:43:07.389 [DEBUG] clck_gen.py:113 IND CLOCK 2346
2026-01-29 02:43:07.771 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:43:07.775 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:43:07.867 [DEBUG] clck_gen.py:113 IND CLOCK 2448
2026-01-29 02:43:08.258 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:43:08.261 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:43:08.261 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 02:43:08.261 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 02:43:08.261 [WARNING] transceiver.py:257 (MS@172.18.28.22:6700) RX TRXD message (fn=2535 tn=5 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:43:08.280 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 02:43:08.280 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 02:43:08.281 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 02:43:08.282 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:43:08.283 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 02:43:08.283 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 02:43:08.283 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.28.22:6700) Recv POWERON CMD
2026-01-29 02:43:08.283 [INFO] ctrl_if_trx.py:109 (MS@172.18.28.22:6700) Starting transceiver...
2026-01-29 02:43:08.339 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:43:08.341 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 02:43:08.341 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 02:43:08.341 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:43:08.341 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:43:08.346 [DEBUG] clck_gen.py:113 IND CLOCK 2550
2026-01-29 02:43:08.824 [DEBUG] clck_gen.py:113 IND CLOCK 2652
2026-01-29 02:43:09.293 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:43:09.298 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:43:09.302 [DEBUG] clck_gen.py:113 IND CLOCK 2754
2026-01-29 02:43:09.780 [DEBUG] clck_gen.py:113 IND CLOCK 2856
2026-01-29 02:43:09.782 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:43:09.785 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:43:09.785 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 02:43:09.786 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 02:43:09.802 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 02:43:09.802 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 02:43:09.802 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 02:43:09.804 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:43:09.805 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 02:43:09.805 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 02:43:09.805 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.28.22:6700) Recv POWERON CMD
2026-01-29 02:43:09.805 [INFO] ctrl_if_trx.py:109 (MS@172.18.28.22:6700) Starting transceiver...
2026-01-29 02:43:09.846 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:43:09.847 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:43:09.853 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 02:43:09.853 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 02:43:09.854 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:43:09.854 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:43:10.258 [DEBUG] clck_gen.py:113 IND CLOCK 2958
2026-01-29 02:43:10.736 [DEBUG] clck_gen.py:113 IND CLOCK 3060
2026-01-29 02:43:11.183 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:43:11.187 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:43:11.213 [DEBUG] clck_gen.py:113 IND CLOCK 3162
2026-01-29 02:43:11.669 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:43:11.672 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:43:11.672 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 02:43:11.673 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 02:43:11.691 [DEBUG] clck_gen.py:113 IND CLOCK 3264
2026-01-29 02:43:11.693 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 02:43:11.693 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 02:43:11.693 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 02:43:11.695 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:43:11.695 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 02:43:11.695 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 02:43:11.695 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.28.22:6700) Recv POWERON CMD
2026-01-29 02:43:11.695 [INFO] ctrl_if_trx.py:109 (MS@172.18.28.22:6700) Starting transceiver...
2026-01-29 02:43:11.738 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:43:11.744 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.28.22:6700) Recv SETFH cmd
2026-01-29 02:43:11.744 [INFO] transceiver.py:201 (MS@172.18.28.22:6700) Frequency hopping configured: hsn=5, maio=0, ma_len=4
2026-01-29 02:43:11.745 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:43:11.745 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:43:12.169 [DEBUG] clck_gen.py:113 IND CLOCK 3366
2026-01-29 02:43:12.644 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:43:12.648 [DEBUG] clck_gen.py:113 IND CLOCK 3468
2026-01-29 02:43:12.649 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:43:13.127 [DEBUG] clck_gen.py:113 IND CLOCK 3570
2026-01-29 02:43:13.141 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:43:13.144 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:43:13.145 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 02:43:13.145 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 02:43:13.145 [INFO] transceiver.py:205 (MS@172.18.28.22:6700) Frequency hopping disabled
2026-01-29 02:43:13.158 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 02:43:13.158 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 02:43:13.158 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 02:43:13.161 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:43:13.161 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 02:43:13.161 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 02:43:13.161 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.28.22:6700) Recv POWERON CMD
2026-01-29 02:43:13.161 [INFO] ctrl_if_trx.py:109 (MS@172.18.28.22:6700) Starting transceiver...
2026-01-29 02:43:13.202 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:43:13.208 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.28.22:6700) Recv SETFH cmd
2026-01-29 02:43:13.208 [INFO] transceiver.py:201 (MS@172.18.28.22:6700) Frequency hopping configured: hsn=5, maio=0, ma_len=4
2026-01-29 02:43:13.209 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:43:13.210 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:43:13.605 [DEBUG] clck_gen.py:113 IND CLOCK 3672
2026-01-29 02:43:14.084 [DEBUG] clck_gen.py:113 IND CLOCK 3774
2026-01-29 02:43:14.177 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:43:14.182 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:43:14.563 [DEBUG] clck_gen.py:113 IND CLOCK 3876
2026-01-29 02:43:14.664 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:43:14.667 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:43:14.667 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 02:43:14.667 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 02:43:14.667 [INFO] transceiver.py:205 (MS@172.18.28.22:6700) Frequency hopping disabled
2026-01-29 02:43:14.687 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 02:43:14.687 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 02:43:14.688 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 02:43:14.689 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:43:14.689 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 02:43:14.689 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 02:43:14.689 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.28.22:6700) Recv POWERON CMD
2026-01-29 02:43:14.689 [INFO] ctrl_if_trx.py:109 (MS@172.18.28.22:6700) Starting transceiver...
2026-01-29 02:43:14.730 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:43:14.735 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.28.22:6700) Recv SETFH cmd
2026-01-29 02:43:14.735 [INFO] transceiver.py:201 (MS@172.18.28.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2026-01-29 02:43:14.736 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:43:14.736 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:43:15.038 [DEBUG] clck_gen.py:113 IND CLOCK 3978
2026-01-29 02:43:15.517 [DEBUG] clck_gen.py:113 IND CLOCK 4080
2026-01-29 02:43:15.674 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:43:15.678 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:43:15.995 [DEBUG] clck_gen.py:113 IND CLOCK 4182
2026-01-29 02:43:16.151 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:43:16.154 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:43:16.154 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 02:43:16.154 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 02:43:16.155 [INFO] transceiver.py:205 (MS@172.18.28.22:6700) Frequency hopping disabled
2026-01-29 02:43:16.164 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 02:43:16.164 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 02:43:16.164 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 02:43:16.166 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:43:16.166 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 02:43:16.166 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 02:43:16.166 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.28.22:6700) Recv POWERON CMD
2026-01-29 02:43:16.166 [INFO] ctrl_if_trx.py:109 (MS@172.18.28.22:6700) Starting transceiver...
2026-01-29 02:43:16.210 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:43:16.215 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.28.22:6700) Recv SETFH cmd
2026-01-29 02:43:16.215 [INFO] transceiver.py:201 (MS@172.18.28.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2026-01-29 02:43:16.216 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:43:16.216 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:43:16.474 [DEBUG] clck_gen.py:113 IND CLOCK 4284
2026-01-29 02:43:16.953 [DEBUG] clck_gen.py:113 IND CLOCK 4386
2026-01-29 02:43:17.128 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:43:17.132 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:43:17.431 [DEBUG] clck_gen.py:113 IND CLOCK 4488
2026-01-29 02:43:17.625 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:43:17.628 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:43:17.629 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 02:43:17.629 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 02:43:17.629 [INFO] transceiver.py:205 (MS@172.18.28.22:6700) Frequency hopping disabled
2026-01-29 02:43:17.645 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 02:43:17.645 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 02:43:17.645 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 02:43:17.646 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:43:17.646 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 02:43:17.646 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 02:43:17.646 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.28.22:6700) Recv POWERON CMD
2026-01-29 02:43:17.646 [INFO] ctrl_if_trx.py:109 (MS@172.18.28.22:6700) Starting transceiver...
2026-01-29 02:43:17.690 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:43:17.696 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.28.22:6700) Recv SETFH cmd
2026-01-29 02:43:17.696 [INFO] transceiver.py:201 (MS@172.18.28.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2026-01-29 02:43:17.696 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:43:17.697 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:43:17.909 [DEBUG] clck_gen.py:113 IND CLOCK 4590
2026-01-29 02:43:18.388 [DEBUG] clck_gen.py:113 IND CLOCK 4692
2026-01-29 02:43:18.581 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:43:18.585 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:43:18.866 [DEBUG] clck_gen.py:113 IND CLOCK 4794
2026-01-29 02:43:19.058 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:43:19.062 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:43:19.062 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 02:43:19.062 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 02:43:19.062 [INFO] transceiver.py:205 (MS@172.18.28.22:6700) Frequency hopping disabled
2026-01-29 02:43:19.082 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 02:43:19.082 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 02:43:19.083 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 02:43:19.084 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:43:19.084 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 02:43:19.084 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 02:43:19.084 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.28.22:6700) Recv POWERON CMD
2026-01-29 02:43:19.085 [INFO] ctrl_if_trx.py:109 (MS@172.18.28.22:6700) Starting transceiver...
2026-01-29 02:43:19.126 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:43:19.132 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.28.22:6700) Recv SETFH cmd
2026-01-29 02:43:19.132 [INFO] transceiver.py:201 (MS@172.18.28.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2026-01-29 02:43:19.132 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:43:19.133 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:43:19.339 [DEBUG] clck_gen.py:113 IND CLOCK 4896
2026-01-29 02:43:19.816 [DEBUG] clck_gen.py:113 IND CLOCK 4998
2026-01-29 02:43:20.027 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:43:20.032 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:43:20.294 [DEBUG] clck_gen.py:113 IND CLOCK 5100
2026-01-29 02:43:20.505 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:43:20.507 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:43:20.508 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 02:43:20.508 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 02:43:20.508 [INFO] transceiver.py:205 (MS@172.18.28.22:6700) Frequency hopping disabled
2026-01-29 02:43:20.527 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 02:43:20.527 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 02:43:20.527 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 02:43:20.529 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:43:20.529 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 02:43:20.529 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 02:43:20.529 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.28.22:6700) Recv POWERON CMD
2026-01-29 02:43:20.529 [INFO] ctrl_if_trx.py:109 (MS@172.18.28.22:6700) Starting transceiver...
2026-01-29 02:43:20.577 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:43:20.582 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.28.22:6700) Recv SETFH cmd
2026-01-29 02:43:20.582 [INFO] transceiver.py:201 (MS@172.18.28.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2026-01-29 02:43:20.582 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:43:20.582 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:43:20.772 [DEBUG] clck_gen.py:113 IND CLOCK 5202
2026-01-29 02:43:21.164 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:43:21.168 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:43:21.251 [DEBUG] clck_gen.py:113 IND CLOCK 5304
2026-01-29 02:43:21.641 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:43:21.644 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:43:21.645 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 02:43:21.645 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 02:43:21.645 [INFO] transceiver.py:205 (MS@172.18.28.22:6700) Frequency hopping disabled
2026-01-29 02:43:21.664 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 02:43:21.664 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 02:43:21.664 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 02:43:21.666 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:43:21.666 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 02:43:21.667 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 02:43:21.667 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.28.22:6700) Recv POWERON CMD
2026-01-29 02:43:21.667 [INFO] ctrl_if_trx.py:109 (MS@172.18.28.22:6700) Starting transceiver...
2026-01-29 02:43:21.723 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:43:21.728 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.28.22:6700) Recv SETFH cmd
2026-01-29 02:43:21.729 [INFO] transceiver.py:201 (MS@172.18.28.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2026-01-29 02:43:21.729 [DEBUG] clck_gen.py:113 IND CLOCK 5406
2026-01-29 02:43:21.729 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:43:21.730 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:43:22.207 [DEBUG] clck_gen.py:113 IND CLOCK 5508
2026-01-29 02:43:22.636 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:43:22.640 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:43:22.686 [DEBUG] clck_gen.py:113 IND CLOCK 5610
2026-01-29 02:43:23.096 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:43:23.099 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:43:23.099 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 02:43:23.100 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 02:43:23.100 [INFO] transceiver.py:205 (MS@172.18.28.22:6700) Frequency hopping disabled
2026-01-29 02:43:23.109 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 02:43:23.109 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 02:43:23.109 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 02:43:23.111 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:43:23.111 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 02:43:23.111 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 02:43:23.111 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.28.22:6700) Recv POWERON CMD
2026-01-29 02:43:23.111 [INFO] ctrl_if_trx.py:109 (MS@172.18.28.22:6700) Starting transceiver...
2026-01-29 02:43:23.158 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:43:23.162 [DEBUG] clck_gen.py:113 IND CLOCK 5712
2026-01-29 02:43:23.163 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.28.22:6700) Recv SETFH cmd
2026-01-29 02:43:23.163 [INFO] transceiver.py:201 (MS@172.18.28.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2026-01-29 02:43:23.164 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:43:23.164 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:43:23.638 [DEBUG] clck_gen.py:113 IND CLOCK 5814
2026-01-29 02:43:24.067 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:43:24.071 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:43:24.117 [DEBUG] clck_gen.py:113 IND CLOCK 5916
2026-01-29 02:43:24.545 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:43:24.548 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:43:24.548 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 02:43:24.548 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 02:43:24.549 [INFO] transceiver.py:205 (MS@172.18.28.22:6700) Frequency hopping disabled
2026-01-29 02:43:24.561 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 02:43:24.561 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 02:43:24.561 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 02:43:24.564 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:43:24.564 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 02:43:24.564 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 02:43:24.564 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.28.22:6700) Recv POWERON CMD
2026-01-29 02:43:24.565 [INFO] ctrl_if_trx.py:109 (MS@172.18.28.22:6700) Starting transceiver...
2026-01-29 02:43:24.595 [DEBUG] clck_gen.py:113 IND CLOCK 6018
2026-01-29 02:43:24.606 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:43:24.611 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.28.22:6700) Recv SETFH cmd
2026-01-29 02:43:24.611 [INFO] transceiver.py:201 (MS@172.18.28.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2026-01-29 02:43:24.612 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:43:24.612 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:43:25.074 [DEBUG] clck_gen.py:113 IND CLOCK 6120
2026-01-29 02:43:25.521 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:43:25.525 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:43:25.552 [DEBUG] clck_gen.py:113 IND CLOCK 6222
2026-01-29 02:43:26.000 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:43:26.002 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:43:26.003 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 02:43:26.003 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 02:43:26.003 [INFO] transceiver.py:205 (MS@172.18.28.22:6700) Frequency hopping disabled
2026-01-29 02:43:26.012 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 02:43:26.013 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:43:26.013 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:43:26.013 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:43:26.016 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 02:43:26.016 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:43:26.016 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:43:26.017 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.28.20:5700) Recv POWEROFF cmd
2026-01-29 02:43:26.017 [INFO] ctrl_if_trx.py:117 (BTS@172.18.28.20:5700) Stopping transceiver...
2026-01-29 02:43:26.017 [INFO] transceiver.py:246 Stopping clock generator
2026-01-29 02:43:26.017 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:43:26.017 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=6323 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:43:26.017 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=6323 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:43:26.018 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=6323 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:43:26.018 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=6323 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:43:26.018 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=6323 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:43:26.018 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=6323 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:43:26.018 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=6323 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:43:26.018 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=6323 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:43:26.018 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=6324 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:43:26.018 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=6324 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:43:26.018 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=6324 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:43:26.018 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=6324 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:43:26.019 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=6324 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:43:26.019 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=6324 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:43:31.016 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.28.20:5700) Recv POWEROFF cmd
2026-01-29 02:43:31.016 [INFO] ctrl_if_trx.py:117 (BTS@172.18.28.20:5700) Stopping transceiver...
2026-01-29 02:43:31.017 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:43:31.018 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:43:31.018 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:43:31.019 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 02:43:31.027 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 02:43:31.028 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.28.20:5700) Recv SETFORMAT cmd
2026-01-29 02:43:31.029 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.28.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:43:31.029 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.28.20:5700) Recv SETFORMAT cmd
2026-01-29 02:43:31.029 [INFO] ctrl_if_trx.py:201 (BTS@172.18.28.20:5700) TRXD header version 1 -> 1
2026-01-29 02:43:31.033 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.28.20:5700/1) Recv RXTUNE cmd
2026-01-29 02:43:31.033 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.28.20:5700/1) Recv TXTUNE cmd
2026-01-29 02:43:31.033 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.28.20:5700/1) Recv SETFORMAT cmd
2026-01-29 02:43:31.033 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.28.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:43:31.033 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:43:31.033 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.28.20:5700/1) Recv NOMTXPOWER cmd
2026-01-29 02:43:31.034 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.28.20:5700/1) Recv SETFORMAT cmd
2026-01-29 02:43:31.034 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.28.20:5700/1) TRXD header version 1 -> 1
2026-01-29 02:43:31.037 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.28.20:5700/2) Recv RXTUNE cmd
2026-01-29 02:43:31.037 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.28.20:5700/2) Recv TXTUNE cmd
2026-01-29 02:43:31.037 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.28.20:5700/2) Recv SETFORMAT cmd
2026-01-29 02:43:31.037 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.28.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:43:31.038 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:43:31.038 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.28.20:5700/2) Recv NOMTXPOWER cmd
2026-01-29 02:43:31.038 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.28.20:5700/2) Recv SETFORMAT cmd
2026-01-29 02:43:31.038 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.28.20:5700/2) TRXD header version 1 -> 1
2026-01-29 02:43:31.040 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.28.20:5700/3) Recv RXTUNE cmd
2026-01-29 02:43:31.040 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.28.20:5700/3) Recv TXTUNE cmd
2026-01-29 02:43:31.040 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.28.20:5700/3) Recv SETFORMAT cmd
2026-01-29 02:43:31.040 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.28.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:43:31.040 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:43:31.041 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.28.20:5700/3) Recv NOMTXPOWER cmd
2026-01-29 02:43:31.041 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.28.20:5700/3) Recv SETFORMAT cmd
2026-01-29 02:43:31.041 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.28.20:5700/3) TRXD header version 1 -> 1
2026-01-29 02:43:31.044 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.28.20:5700) Recv RXTUNE cmd
2026-01-29 02:43:31.044 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETTSC
2026-01-29 02:43:31.044 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETTSC
2026-01-29 02:43:31.044 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.28.20:5700) Recv TXTUNE cmd
2026-01-29 02:43:31.044 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETTSC
2026-01-29 02:43:31.044 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETRXGAIN
2026-01-29 02:43:31.044 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETRXGAIN
2026-01-29 02:43:31.044 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETTSC
2026-01-29 02:43:31.044 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETRXGAIN
2026-01-29 02:43:31.044 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:43:31.044 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:43:31.044 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.28.20:5700) Recv NOMTXPOWER cmd
2026-01-29 02:43:31.044 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:43:31.044 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:43:31.044 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:43:31.044 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.28.20:5700) Recv POWERON CMD
2026-01-29 02:43:31.044 [INFO] ctrl_if_trx.py:109 (BTS@172.18.28.20:5700) Starting transceiver...
2026-01-29 02:43:31.044 [INFO] transceiver.py:243 Starting clock generator
2026-01-29 02:43:31.044 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-01-29 02:43:31.045 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:43:31.045 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:43:31.045 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:43:31.045 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETRXGAIN
2026-01-29 02:43:31.045 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:43:31.045 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:43:31.045 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:43:31.045 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:43:31.045 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:43:31.045 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:43:31.045 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:43:31.045 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:43:31.045 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:43:31.045 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:43:31.045 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:43:31.045 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:43:31.045 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:43:31.045 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:43:31.045 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:43:31.045 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:43:31.045 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:43:31.045 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:43:31.045 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:43:31.046 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:43:31.046 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:43:31.046 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:43:31.046 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:43:31.046 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:43:31.049 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-01-29 02:43:31.523 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-01-29 02:43:31.582 [DEBUG] fake_trx.py:278 (BTS@172.18.28.20:5700) Recv FAKE_TOA cmd
2026-01-29 02:43:31.584 [DEBUG] fake_trx.py:297 (BTS@172.18.28.20:5700) Recv FAKE_RSSI cmd
2026-01-29 02:43:31.587 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:43:31.587 [DEBUG] fake_trx.py:322 (BTS@172.18.28.20:5700) Recv FAKE_CI cmd
2026-01-29 02:43:31.611 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 02:43:31.612 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 02:43:31.612 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 02:43:31.619 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:43:31.620 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 02:43:31.620 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 02:43:31.620 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.28.22:6700) Recv POWERON CMD
2026-01-29 02:43:31.620 [INFO] ctrl_if_trx.py:109 (MS@172.18.28.22:6700) Starting transceiver...
2026-01-29 02:43:31.663 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:43:31.669 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 02:43:31.670 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 02:43:31.670 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:43:31.670 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:43:31.995 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-01-29 02:43:32.047 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 02:43:32.048 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:43:32.050 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:43:32.054 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:43:32.475 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-01-29 02:43:32.952 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-01-29 02:43:33.049 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 02:43:33.049 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:43:33.050 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:43:33.055 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:43:33.431 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-01-29 02:43:33.909 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-01-29 02:43:34.050 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:43:34.050 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 02:43:34.051 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:43:34.057 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:43:34.388 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-01-29 02:43:34.866 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-01-29 02:43:35.051 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:43:35.051 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 02:43:35.052 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:43:35.058 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:43:35.344 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-01-29 02:43:35.546 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:43:35.549 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:43:35.549 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 02:43:35.549 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 02:43:35.568 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 02:43:35.568 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 02:43:35.568 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 02:43:35.571 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:43:35.571 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 02:43:35.571 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 02:43:35.571 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.28.22:6700) Recv POWERON CMD
2026-01-29 02:43:35.571 [INFO] ctrl_if_trx.py:109 (MS@172.18.28.22:6700) Starting transceiver...
2026-01-29 02:43:35.618 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:43:35.624 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 02:43:35.625 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 02:43:35.625 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:43:35.625 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:43:35.821 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-01-29 02:43:36.052 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 02:43:36.052 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:43:36.053 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:43:36.059 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:43:36.299 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-01-29 02:43:36.777 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-01-29 02:43:37.255 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-01-29 02:43:37.733 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-01-29 02:43:38.210 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-01-29 02:43:38.688 [DEBUG] clck_gen.py:113 IND CLOCK 1632
2026-01-29 02:43:39.166 [DEBUG] clck_gen.py:113 IND CLOCK 1734
2026-01-29 02:43:39.644 [DEBUG] clck_gen.py:113 IND CLOCK 1836
2026-01-29 02:43:39.864 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:43:39.867 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:43:39.868 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 02:43:39.868 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 02:43:39.887 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 02:43:39.887 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 02:43:39.887 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 02:43:39.889 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:43:39.889 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 02:43:39.890 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 02:43:39.890 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.28.22:6700) Recv POWERON CMD
2026-01-29 02:43:39.890 [INFO] ctrl_if_trx.py:109 (MS@172.18.28.22:6700) Starting transceiver...
2026-01-29 02:43:39.930 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:43:39.936 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 02:43:39.936 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 02:43:39.937 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:43:39.937 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:43:40.122 [DEBUG] clck_gen.py:113 IND CLOCK 1938
2026-01-29 02:43:40.600 [DEBUG] clck_gen.py:113 IND CLOCK 2040
2026-01-29 02:43:41.078 [DEBUG] clck_gen.py:113 IND CLOCK 2142
2026-01-29 02:43:41.557 [DEBUG] clck_gen.py:113 IND CLOCK 2244
2026-01-29 02:43:42.035 [DEBUG] clck_gen.py:113 IND CLOCK 2346
2026-01-29 02:43:42.514 [DEBUG] clck_gen.py:113 IND CLOCK 2448
2026-01-29 02:43:42.992 [DEBUG] clck_gen.py:113 IND CLOCK 2550
2026-01-29 02:43:43.470 [DEBUG] clck_gen.py:113 IND CLOCK 2652
2026-01-29 02:43:43.907 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:43:43.910 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:43:43.911 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 02:43:43.911 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 02:43:43.930 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 02:43:43.930 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 02:43:43.930 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 02:43:43.932 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:43:43.932 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 02:43:43.933 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 02:43:43.933 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.28.22:6700) Recv POWERON CMD
2026-01-29 02:43:43.933 [INFO] ctrl_if_trx.py:109 (MS@172.18.28.22:6700) Starting transceiver...
2026-01-29 02:43:43.947 [DEBUG] clck_gen.py:113 IND CLOCK 2754
2026-01-29 02:43:43.974 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:43:43.980 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 02:43:43.980 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 02:43:43.981 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:43:43.981 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:43:44.426 [DEBUG] clck_gen.py:113 IND CLOCK 2856
2026-01-29 02:43:44.903 [DEBUG] clck_gen.py:113 IND CLOCK 2958
2026-01-29 02:43:45.382 [DEBUG] clck_gen.py:113 IND CLOCK 3060
2026-01-29 02:43:45.859 [DEBUG] clck_gen.py:113 IND CLOCK 3162
2026-01-29 02:43:46.337 [DEBUG] clck_gen.py:113 IND CLOCK 3264
2026-01-29 02:43:46.815 [DEBUG] clck_gen.py:113 IND CLOCK 3366
2026-01-29 02:43:47.294 [DEBUG] clck_gen.py:113 IND CLOCK 3468
2026-01-29 02:43:47.772 [DEBUG] clck_gen.py:113 IND CLOCK 3570
2026-01-29 02:43:48.227 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:43:48.230 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:43:48.231 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 02:43:48.231 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 02:43:48.240 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 02:43:48.240 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 02:43:48.240 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 02:43:48.242 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:43:48.243 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 02:43:48.243 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 02:43:48.243 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.28.22:6700) Recv POWERON CMD
2026-01-29 02:43:48.243 [INFO] ctrl_if_trx.py:109 (MS@172.18.28.22:6700) Starting transceiver...
2026-01-29 02:43:48.249 [DEBUG] clck_gen.py:113 IND CLOCK 3672
2026-01-29 02:43:48.296 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:43:48.301 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 02:43:48.302 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 02:43:48.302 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:43:48.302 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:43:48.727 [DEBUG] clck_gen.py:113 IND CLOCK 3774
2026-01-29 02:43:49.205 [DEBUG] clck_gen.py:113 IND CLOCK 3876
2026-01-29 02:43:49.684 [DEBUG] clck_gen.py:113 IND CLOCK 3978
2026-01-29 02:43:50.162 [DEBUG] clck_gen.py:113 IND CLOCK 4080
2026-01-29 02:43:50.640 [DEBUG] clck_gen.py:113 IND CLOCK 4182
2026-01-29 02:43:51.118 [DEBUG] clck_gen.py:113 IND CLOCK 4284
2026-01-29 02:43:51.596 [DEBUG] clck_gen.py:113 IND CLOCK 4386
2026-01-29 02:43:52.075 [DEBUG] clck_gen.py:113 IND CLOCK 4488
2026-01-29 02:43:52.554 [DEBUG] clck_gen.py:113 IND CLOCK 4590
2026-01-29 02:43:52.958 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:43:52.961 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:43:52.961 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 02:43:52.961 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 02:43:52.979 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 02:43:52.979 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 02:43:52.979 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 02:43:52.981 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:43:52.981 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 02:43:52.981 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 02:43:52.981 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.28.22:6700) Recv POWERON CMD
2026-01-29 02:43:52.981 [INFO] ctrl_if_trx.py:109 (MS@172.18.28.22:6700) Starting transceiver...
2026-01-29 02:43:53.025 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:43:53.030 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.28.22:6700) Recv SETFH cmd
2026-01-29 02:43:53.030 [INFO] transceiver.py:201 (MS@172.18.28.22:6700) Frequency hopping configured: hsn=2, maio=0, ma_len=2
2026-01-29 02:43:53.030 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:43:53.031 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:43:53.032 [DEBUG] clck_gen.py:113 IND CLOCK 4692
2026-01-29 02:43:53.509 [DEBUG] clck_gen.py:113 IND CLOCK 4794
2026-01-29 02:43:53.987 [DEBUG] clck_gen.py:113 IND CLOCK 4896
2026-01-29 02:43:54.465 [DEBUG] clck_gen.py:113 IND CLOCK 4998
2026-01-29 02:43:54.944 [DEBUG] clck_gen.py:113 IND CLOCK 5100
2026-01-29 02:43:55.422 [DEBUG] clck_gen.py:113 IND CLOCK 5202
2026-01-29 02:43:55.901 [DEBUG] clck_gen.py:113 IND CLOCK 5304
2026-01-29 02:43:56.379 [DEBUG] clck_gen.py:113 IND CLOCK 5406
2026-01-29 02:43:56.858 [DEBUG] clck_gen.py:113 IND CLOCK 5508
2026-01-29 02:43:57.336 [DEBUG] clck_gen.py:113 IND CLOCK 5610
2026-01-29 02:43:57.414 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:43:57.417 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:43:57.417 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 02:43:57.417 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 02:43:57.417 [INFO] transceiver.py:205 (MS@172.18.28.22:6700) Frequency hopping disabled
2026-01-29 02:43:57.433 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 02:43:57.433 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 02:43:57.433 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 02:43:57.435 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:43:57.435 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 02:43:57.435 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 02:43:57.435 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.28.22:6700) Recv POWERON CMD
2026-01-29 02:43:57.435 [INFO] ctrl_if_trx.py:109 (MS@172.18.28.22:6700) Starting transceiver...
2026-01-29 02:43:57.478 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:43:57.484 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.28.22:6700) Recv SETFH cmd
2026-01-29 02:43:57.484 [INFO] transceiver.py:201 (MS@172.18.28.22:6700) Frequency hopping configured: hsn=3, maio=3, ma_len=4
2026-01-29 02:43:57.484 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:43:57.484 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:43:57.808 [DEBUG] clck_gen.py:113 IND CLOCK 5712
2026-01-29 02:43:58.281 [DEBUG] clck_gen.py:113 IND CLOCK 5814
2026-01-29 02:43:58.759 [DEBUG] clck_gen.py:113 IND CLOCK 5916
2026-01-29 02:43:59.238 [DEBUG] clck_gen.py:113 IND CLOCK 6018
2026-01-29 02:43:59.717 [DEBUG] clck_gen.py:113 IND CLOCK 6120
2026-01-29 02:44:00.195 [DEBUG] clck_gen.py:113 IND CLOCK 6222
2026-01-29 02:44:00.674 [DEBUG] clck_gen.py:113 IND CLOCK 6324
2026-01-29 02:44:01.153 [DEBUG] clck_gen.py:113 IND CLOCK 6426
2026-01-29 02:44:01.632 [DEBUG] clck_gen.py:113 IND CLOCK 6528
2026-01-29 02:44:01.852 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:44:01.855 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:44:01.856 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 02:44:01.856 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 02:44:01.856 [INFO] transceiver.py:205 (MS@172.18.28.22:6700) Frequency hopping disabled
2026-01-29 02:44:01.873 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 02:44:01.874 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 02:44:01.874 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 02:44:01.876 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:44:01.876 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 02:44:01.876 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 02:44:01.876 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.28.22:6700) Recv POWERON CMD
2026-01-29 02:44:01.876 [INFO] ctrl_if_trx.py:109 (MS@172.18.28.22:6700) Starting transceiver...
2026-01-29 02:44:01.922 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:44:01.923 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:44:01.928 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 02:44:01.928 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 02:44:01.929 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:44:01.929 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:44:02.110 [DEBUG] clck_gen.py:113 IND CLOCK 6630
2026-01-29 02:44:02.588 [DEBUG] clck_gen.py:113 IND CLOCK 6732
2026-01-29 02:44:03.066 [DEBUG] clck_gen.py:113 IND CLOCK 6834
2026-01-29 02:44:03.545 [DEBUG] clck_gen.py:113 IND CLOCK 6936
2026-01-29 02:44:04.022 [DEBUG] clck_gen.py:113 IND CLOCK 7038
2026-01-29 02:44:04.500 [DEBUG] clck_gen.py:113 IND CLOCK 7140
2026-01-29 02:44:04.979 [DEBUG] clck_gen.py:113 IND CLOCK 7242
2026-01-29 02:44:05.457 [DEBUG] clck_gen.py:113 IND CLOCK 7344
2026-01-29 02:44:05.935 [DEBUG] clck_gen.py:113 IND CLOCK 7446
2026-01-29 02:44:06.299 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:44:06.303 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:44:06.303 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 02:44:06.303 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 02:44:06.321 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 02:44:06.321 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 02:44:06.321 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 02:44:06.323 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:44:06.323 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 02:44:06.323 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 02:44:06.324 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.28.22:6700) Recv POWERON CMD
2026-01-29 02:44:06.324 [INFO] ctrl_if_trx.py:109 (MS@172.18.28.22:6700) Starting transceiver...
2026-01-29 02:44:06.366 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:44:06.372 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 02:44:06.372 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 02:44:06.372 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:44:06.373 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:44:06.412 [DEBUG] clck_gen.py:113 IND CLOCK 7548
2026-01-29 02:44:06.890 [DEBUG] clck_gen.py:113 IND CLOCK 7650
2026-01-29 02:44:07.369 [DEBUG] clck_gen.py:113 IND CLOCK 7752
2026-01-29 02:44:07.848 [DEBUG] clck_gen.py:113 IND CLOCK 7854
2026-01-29 02:44:08.326 [DEBUG] clck_gen.py:113 IND CLOCK 7956
2026-01-29 02:44:08.804 [DEBUG] clck_gen.py:113 IND CLOCK 8058
2026-01-29 02:44:09.282 [DEBUG] clck_gen.py:113 IND CLOCK 8160
2026-01-29 02:44:09.761 [DEBUG] clck_gen.py:113 IND CLOCK 8262
2026-01-29 02:44:10.239 [DEBUG] clck_gen.py:113 IND CLOCK 8364
2026-01-29 02:44:10.718 [DEBUG] clck_gen.py:113 IND CLOCK 8466
2026-01-29 02:44:10.754 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:44:10.756 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:44:10.757 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 02:44:10.757 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 02:44:10.775 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 02:44:10.775 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 02:44:10.775 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 02:44:10.777 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:44:10.777 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 02:44:10.777 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 02:44:10.777 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.28.22:6700) Recv POWERON CMD
2026-01-29 02:44:10.777 [INFO] ctrl_if_trx.py:109 (MS@172.18.28.22:6700) Starting transceiver...
2026-01-29 02:44:10.819 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:44:10.819 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:44:10.824 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 02:44:10.825 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 02:44:10.825 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:44:10.826 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:44:11.195 [DEBUG] clck_gen.py:113 IND CLOCK 8568
2026-01-29 02:44:11.673 [DEBUG] clck_gen.py:113 IND CLOCK 8670
2026-01-29 02:44:12.152 [DEBUG] clck_gen.py:113 IND CLOCK 8772
2026-01-29 02:44:12.630 [DEBUG] clck_gen.py:113 IND CLOCK 8874
2026-01-29 02:44:13.106 [DEBUG] clck_gen.py:113 IND CLOCK 8976
2026-01-29 02:44:13.585 [DEBUG] clck_gen.py:113 IND CLOCK 9078
2026-01-29 02:44:14.063 [DEBUG] clck_gen.py:113 IND CLOCK 9180
2026-01-29 02:44:14.541 [DEBUG] clck_gen.py:113 IND CLOCK 9282
2026-01-29 02:44:15.019 [DEBUG] clck_gen.py:113 IND CLOCK 9384
2026-01-29 02:44:15.078 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:44:15.081 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:44:15.081 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 02:44:15.081 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 02:44:15.099 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 02:44:15.099 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 02:44:15.099 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 02:44:15.101 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:44:15.101 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 02:44:15.101 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 02:44:15.102 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.28.22:6700) Recv POWERON CMD
2026-01-29 02:44:15.102 [INFO] ctrl_if_trx.py:109 (MS@172.18.28.22:6700) Starting transceiver...
2026-01-29 02:44:15.146 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:44:15.152 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.28.22:6700) Recv SETFH cmd
2026-01-29 02:44:15.152 [INFO] transceiver.py:201 (MS@172.18.28.22:6700) Frequency hopping configured: hsn=5, maio=0, ma_len=4
2026-01-29 02:44:15.153 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:44:15.153 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:44:15.497 [DEBUG] clck_gen.py:113 IND CLOCK 9486
2026-01-29 02:44:15.976 [DEBUG] clck_gen.py:113 IND CLOCK 9588
2026-01-29 02:44:16.456 [DEBUG] clck_gen.py:113 IND CLOCK 9690
2026-01-29 02:44:16.934 [DEBUG] clck_gen.py:113 IND CLOCK 9792
2026-01-29 02:44:17.413 [DEBUG] clck_gen.py:113 IND CLOCK 9894
2026-01-29 02:44:17.893 [DEBUG] clck_gen.py:113 IND CLOCK 9996
2026-01-29 02:44:18.371 [DEBUG] clck_gen.py:113 IND CLOCK 10098
2026-01-29 02:44:18.850 [DEBUG] clck_gen.py:113 IND CLOCK 10200
2026-01-29 02:44:19.329 [DEBUG] clck_gen.py:113 IND CLOCK 10302
2026-01-29 02:44:19.471 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:44:19.474 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:44:19.474 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 02:44:19.474 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 02:44:19.475 [INFO] transceiver.py:205 (MS@172.18.28.22:6700) Frequency hopping disabled
2026-01-29 02:44:19.492 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 02:44:19.492 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 02:44:19.492 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 02:44:19.494 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:44:19.494 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 02:44:19.494 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 02:44:19.494 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.28.22:6700) Recv POWERON CMD
2026-01-29 02:44:19.495 [INFO] ctrl_if_trx.py:109 (MS@172.18.28.22:6700) Starting transceiver...
2026-01-29 02:44:19.542 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:44:19.548 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.28.22:6700) Recv SETFH cmd
2026-01-29 02:44:19.548 [INFO] transceiver.py:201 (MS@172.18.28.22:6700) Frequency hopping configured: hsn=5, maio=0, ma_len=4
2026-01-29 02:44:19.549 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:44:19.549 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:44:19.806 [DEBUG] clck_gen.py:113 IND CLOCK 10404
2026-01-29 02:44:20.285 [DEBUG] clck_gen.py:113 IND CLOCK 10506
2026-01-29 02:44:20.764 [DEBUG] clck_gen.py:113 IND CLOCK 10608
2026-01-29 02:44:21.243 [DEBUG] clck_gen.py:113 IND CLOCK 10710
2026-01-29 02:44:21.722 [DEBUG] clck_gen.py:113 IND CLOCK 10812
2026-01-29 02:44:22.202 [DEBUG] clck_gen.py:113 IND CLOCK 10914
2026-01-29 02:44:22.681 [DEBUG] clck_gen.py:113 IND CLOCK 11016
2026-01-29 02:44:23.160 [DEBUG] clck_gen.py:113 IND CLOCK 11118
2026-01-29 02:44:23.638 [DEBUG] clck_gen.py:113 IND CLOCK 11220
2026-01-29 02:44:23.924 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:44:23.927 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:44:23.928 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 02:44:23.928 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 02:44:23.928 [INFO] transceiver.py:205 (MS@172.18.28.22:6700) Frequency hopping disabled
2026-01-29 02:44:23.947 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 02:44:23.947 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 02:44:23.947 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 02:44:23.950 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:44:23.950 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 02:44:23.950 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 02:44:23.950 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.28.22:6700) Recv POWERON CMD
2026-01-29 02:44:23.950 [INFO] ctrl_if_trx.py:109 (MS@172.18.28.22:6700) Starting transceiver...
2026-01-29 02:44:23.990 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:44:23.996 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.28.22:6700) Recv SETFH cmd
2026-01-29 02:44:23.996 [INFO] transceiver.py:201 (MS@172.18.28.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2026-01-29 02:44:23.996 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:44:23.996 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:44:24.116 [DEBUG] clck_gen.py:113 IND CLOCK 11322
2026-01-29 02:44:24.594 [DEBUG] clck_gen.py:113 IND CLOCK 11424
2026-01-29 02:44:25.072 [DEBUG] clck_gen.py:113 IND CLOCK 11526
2026-01-29 02:44:25.551 [DEBUG] clck_gen.py:113 IND CLOCK 11628
2026-01-29 02:44:26.030 [DEBUG] clck_gen.py:113 IND CLOCK 11730
2026-01-29 02:44:26.508 [DEBUG] clck_gen.py:113 IND CLOCK 11832
2026-01-29 02:44:26.986 [DEBUG] clck_gen.py:113 IND CLOCK 11934
2026-01-29 02:44:27.464 [DEBUG] clck_gen.py:113 IND CLOCK 12036
2026-01-29 02:44:27.942 [DEBUG] clck_gen.py:113 IND CLOCK 12138
2026-01-29 02:44:28.098 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:44:28.100 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:44:28.101 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 02:44:28.101 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 02:44:28.101 [INFO] transceiver.py:205 (MS@172.18.28.22:6700) Frequency hopping disabled
2026-01-29 02:44:28.120 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 02:44:28.120 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 02:44:28.120 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 02:44:28.122 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:44:28.122 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 02:44:28.122 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 02:44:28.122 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.28.22:6700) Recv POWERON CMD
2026-01-29 02:44:28.122 [INFO] ctrl_if_trx.py:109 (MS@172.18.28.22:6700) Starting transceiver...
2026-01-29 02:44:28.177 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:44:28.183 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.28.22:6700) Recv SETFH cmd
2026-01-29 02:44:28.183 [INFO] transceiver.py:201 (MS@172.18.28.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2026-01-29 02:44:28.183 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:44:28.183 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:44:28.420 [DEBUG] clck_gen.py:113 IND CLOCK 12240
2026-01-29 02:44:28.899 [DEBUG] clck_gen.py:113 IND CLOCK 12342
2026-01-29 02:44:29.377 [DEBUG] clck_gen.py:113 IND CLOCK 12444
2026-01-29 02:44:29.856 [DEBUG] clck_gen.py:113 IND CLOCK 12546
2026-01-29 02:44:30.335 [DEBUG] clck_gen.py:113 IND CLOCK 12648
2026-01-29 02:44:30.814 [DEBUG] clck_gen.py:113 IND CLOCK 12750
2026-01-29 02:44:31.292 [DEBUG] clck_gen.py:113 IND CLOCK 12852
2026-01-29 02:44:31.770 [DEBUG] clck_gen.py:113 IND CLOCK 12954
2026-01-29 02:44:32.249 [DEBUG] clck_gen.py:113 IND CLOCK 13056
2026-01-29 02:44:32.423 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:44:32.426 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:44:32.427 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 02:44:32.427 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 02:44:32.427 [INFO] transceiver.py:205 (MS@172.18.28.22:6700) Frequency hopping disabled
2026-01-29 02:44:32.445 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 02:44:32.445 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 02:44:32.445 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 02:44:32.447 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:44:32.447 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 02:44:32.447 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 02:44:32.448 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.28.22:6700) Recv POWERON CMD
2026-01-29 02:44:32.448 [INFO] ctrl_if_trx.py:109 (MS@172.18.28.22:6700) Starting transceiver...
2026-01-29 02:44:32.514 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:44:32.520 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.28.22:6700) Recv SETFH cmd
2026-01-29 02:44:32.521 [INFO] transceiver.py:201 (MS@172.18.28.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2026-01-29 02:44:32.521 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:44:32.522 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:44:32.727 [DEBUG] clck_gen.py:113 IND CLOCK 13158
2026-01-29 02:44:33.205 [DEBUG] clck_gen.py:113 IND CLOCK 13260
2026-01-29 02:44:33.683 [DEBUG] clck_gen.py:113 IND CLOCK 13362
2026-01-29 02:44:34.163 [DEBUG] clck_gen.py:113 IND CLOCK 13464
2026-01-29 02:44:34.641 [DEBUG] clck_gen.py:113 IND CLOCK 13566
2026-01-29 02:44:35.120 [DEBUG] clck_gen.py:113 IND CLOCK 13668
2026-01-29 02:44:35.598 [DEBUG] clck_gen.py:113 IND CLOCK 13770
2026-01-29 02:44:36.077 [DEBUG] clck_gen.py:113 IND CLOCK 13872
2026-01-29 02:44:36.554 [DEBUG] clck_gen.py:113 IND CLOCK 13974
2026-01-29 02:44:36.749 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:44:36.752 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:44:36.753 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 02:44:36.753 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 02:44:36.753 [INFO] transceiver.py:205 (MS@172.18.28.22:6700) Frequency hopping disabled
2026-01-29 02:44:36.764 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 02:44:36.764 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 02:44:36.764 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 02:44:36.766 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:44:36.766 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 02:44:36.766 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 02:44:36.767 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.28.22:6700) Recv POWERON CMD
2026-01-29 02:44:36.767 [INFO] ctrl_if_trx.py:109 (MS@172.18.28.22:6700) Starting transceiver...
2026-01-29 02:44:36.810 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:44:36.816 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.28.22:6700) Recv SETFH cmd
2026-01-29 02:44:36.816 [INFO] transceiver.py:201 (MS@172.18.28.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2026-01-29 02:44:36.816 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:44:36.816 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:44:37.033 [DEBUG] clck_gen.py:113 IND CLOCK 14076
2026-01-29 02:44:37.511 [DEBUG] clck_gen.py:113 IND CLOCK 14178
2026-01-29 02:44:37.989 [DEBUG] clck_gen.py:113 IND CLOCK 14280
2026-01-29 02:44:38.467 [DEBUG] clck_gen.py:113 IND CLOCK 14382
2026-01-29 02:44:38.946 [DEBUG] clck_gen.py:113 IND CLOCK 14484
2026-01-29 02:44:39.425 [DEBUG] clck_gen.py:113 IND CLOCK 14586
2026-01-29 02:44:39.903 [DEBUG] clck_gen.py:113 IND CLOCK 14688
2026-01-29 02:44:40.381 [DEBUG] clck_gen.py:113 IND CLOCK 14790
2026-01-29 02:44:40.859 [DEBUG] clck_gen.py:113 IND CLOCK 14892
2026-01-29 02:44:41.071 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:44:41.074 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:44:41.074 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 02:44:41.075 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 02:44:41.075 [INFO] transceiver.py:205 (MS@172.18.28.22:6700) Frequency hopping disabled
2026-01-29 02:44:41.092 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 02:44:41.092 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 02:44:41.092 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 02:44:41.094 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:44:41.094 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 02:44:41.094 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 02:44:41.094 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.28.22:6700) Recv POWERON CMD
2026-01-29 02:44:41.094 [INFO] ctrl_if_trx.py:109 (MS@172.18.28.22:6700) Starting transceiver...
2026-01-29 02:44:41.142 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:44:41.147 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.28.22:6700) Recv SETFH cmd
2026-01-29 02:44:41.147 [INFO] transceiver.py:201 (MS@172.18.28.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2026-01-29 02:44:41.148 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:44:41.148 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:44:41.338 [DEBUG] clck_gen.py:113 IND CLOCK 14994
2026-01-29 02:44:41.817 [DEBUG] clck_gen.py:113 IND CLOCK 15096
2026-01-29 02:44:42.295 [DEBUG] clck_gen.py:113 IND CLOCK 15198
2026-01-29 02:44:42.773 [DEBUG] clck_gen.py:113 IND CLOCK 15300
2026-01-29 02:44:43.251 [DEBUG] clck_gen.py:113 IND CLOCK 15402
2026-01-29 02:44:43.730 [DEBUG] clck_gen.py:113 IND CLOCK 15504
2026-01-29 02:44:44.208 [DEBUG] clck_gen.py:113 IND CLOCK 15606
2026-01-29 02:44:44.686 [DEBUG] clck_gen.py:113 IND CLOCK 15708
2026-01-29 02:44:45.077 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:44:45.080 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:44:45.080 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 02:44:45.081 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 02:44:45.081 [INFO] transceiver.py:205 (MS@172.18.28.22:6700) Frequency hopping disabled
2026-01-29 02:44:45.100 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 02:44:45.100 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 02:44:45.100 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 02:44:45.102 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:44:45.102 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 02:44:45.102 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 02:44:45.102 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.28.22:6700) Recv POWERON CMD
2026-01-29 02:44:45.102 [INFO] ctrl_if_trx.py:109 (MS@172.18.28.22:6700) Starting transceiver...
2026-01-29 02:44:45.158 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:44:45.163 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.28.22:6700) Recv SETFH cmd
2026-01-29 02:44:45.163 [INFO] transceiver.py:201 (MS@172.18.28.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2026-01-29 02:44:45.164 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:44:45.164 [DEBUG] clck_gen.py:113 IND CLOCK 15810
2026-01-29 02:44:45.164 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:44:45.642 [DEBUG] clck_gen.py:113 IND CLOCK 15912
2026-01-29 02:44:46.121 [DEBUG] clck_gen.py:113 IND CLOCK 16014
2026-01-29 02:44:46.599 [DEBUG] clck_gen.py:113 IND CLOCK 16116
2026-01-29 02:44:47.076 [DEBUG] clck_gen.py:113 IND CLOCK 16218
2026-01-29 02:44:47.555 [DEBUG] clck_gen.py:113 IND CLOCK 16320
2026-01-29 02:44:48.033 [DEBUG] clck_gen.py:113 IND CLOCK 16422
2026-01-29 02:44:48.512 [DEBUG] clck_gen.py:113 IND CLOCK 16524
2026-01-29 02:44:48.990 [DEBUG] clck_gen.py:113 IND CLOCK 16626
2026-01-29 02:44:49.400 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:44:49.403 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:44:49.404 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 02:44:49.404 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 02:44:49.404 [INFO] transceiver.py:205 (MS@172.18.28.22:6700) Frequency hopping disabled
2026-01-29 02:44:49.423 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 02:44:49.423 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 02:44:49.424 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 02:44:49.426 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:44:49.426 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 02:44:49.426 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 02:44:49.426 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.28.22:6700) Recv POWERON CMD
2026-01-29 02:44:49.426 [INFO] ctrl_if_trx.py:109 (MS@172.18.28.22:6700) Starting transceiver...
2026-01-29 02:44:49.466 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:44:49.468 [DEBUG] clck_gen.py:113 IND CLOCK 16728
2026-01-29 02:44:49.473 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.28.22:6700) Recv SETFH cmd
2026-01-29 02:44:49.473 [INFO] transceiver.py:201 (MS@172.18.28.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2026-01-29 02:44:49.473 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:44:49.474 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:44:49.942 [DEBUG] clck_gen.py:113 IND CLOCK 16830
2026-01-29 02:44:50.420 [DEBUG] clck_gen.py:113 IND CLOCK 16932
2026-01-29 02:44:50.899 [DEBUG] clck_gen.py:113 IND CLOCK 17034
2026-01-29 02:44:51.378 [DEBUG] clck_gen.py:113 IND CLOCK 17136
2026-01-29 02:44:51.857 [DEBUG] clck_gen.py:113 IND CLOCK 17238
2026-01-29 02:44:52.335 [DEBUG] clck_gen.py:113 IND CLOCK 17340
2026-01-29 02:44:52.814 [DEBUG] clck_gen.py:113 IND CLOCK 17442
2026-01-29 02:44:53.293 [DEBUG] clck_gen.py:113 IND CLOCK 17544
2026-01-29 02:44:53.722 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:44:53.725 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:44:53.725 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 02:44:53.725 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 02:44:53.725 [INFO] transceiver.py:205 (MS@172.18.28.22:6700) Frequency hopping disabled
2026-01-29 02:44:53.735 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 02:44:53.735 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 02:44:53.735 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 02:44:53.737 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:44:53.737 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 02:44:53.737 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 02:44:53.737 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.28.22:6700) Recv POWERON CMD
2026-01-29 02:44:53.737 [INFO] ctrl_if_trx.py:109 (MS@172.18.28.22:6700) Starting transceiver...
2026-01-29 02:44:53.770 [DEBUG] clck_gen.py:113 IND CLOCK 17646
2026-01-29 02:44:53.782 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:44:53.789 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.28.22:6700) Recv SETFH cmd
2026-01-29 02:44:53.789 [INFO] transceiver.py:201 (MS@172.18.28.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2026-01-29 02:44:53.790 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:44:53.790 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:44:54.248 [DEBUG] clck_gen.py:113 IND CLOCK 17748
2026-01-29 02:44:54.727 [DEBUG] clck_gen.py:113 IND CLOCK 17850
2026-01-29 02:44:55.205 [DEBUG] clck_gen.py:113 IND CLOCK 17952
2026-01-29 02:44:55.683 [DEBUG] clck_gen.py:113 IND CLOCK 18054
2026-01-29 02:44:56.162 [DEBUG] clck_gen.py:113 IND CLOCK 18156
2026-01-29 02:44:56.640 [DEBUG] clck_gen.py:113 IND CLOCK 18258
2026-01-29 02:44:57.118 [DEBUG] clck_gen.py:113 IND CLOCK 18360
2026-01-29 02:44:57.597 [DEBUG] clck_gen.py:113 IND CLOCK 18462
2026-01-29 02:44:58.045 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:44:58.048 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:44:58.048 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 02:44:58.048 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 02:44:58.048 [INFO] transceiver.py:205 (MS@172.18.28.22:6700) Frequency hopping disabled
2026-01-29 02:44:58.061 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 02:44:58.061 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:44:58.061 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:44:58.061 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:44:58.065 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 02:44:58.065 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:44:58.065 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:44:58.065 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:44:58.065 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.28.20:5700) Recv POWEROFF cmd
2026-01-29 02:44:58.065 [INFO] ctrl_if_trx.py:117 (BTS@172.18.28.20:5700) Stopping transceiver...
2026-01-29 02:44:58.065 [INFO] transceiver.py:246 Stopping clock generator
2026-01-29 02:44:58.065 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=18564 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:44:58.065 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=18564 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:44:58.065 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=18564 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:44:58.065 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=18564 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:44:58.065 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=18564 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:44:58.065 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=18564 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:44:58.065 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=18564 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:44:58.065 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=18565 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:44:58.065 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=18565 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:44:58.065 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=18565 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:44:58.065 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=18565 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:44:58.065 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=18565 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:44:58.065 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=18565 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:44:58.065 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=18565 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:44:58.065 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=18565 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:45:03.064 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.28.20:5700) Recv POWEROFF cmd
2026-01-29 02:45:03.065 [INFO] ctrl_if_trx.py:117 (BTS@172.18.28.20:5700) Stopping transceiver...
2026-01-29 02:45:03.066 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:45:03.068 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:45:03.069 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:45:03.072 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 02:45:03.085 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 02:45:03.086 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.28.20:5700) Recv SETFORMAT cmd
2026-01-29 02:45:03.086 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.28.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:45:03.086 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.28.20:5700) Recv SETFORMAT cmd
2026-01-29 02:45:03.086 [INFO] ctrl_if_trx.py:201 (BTS@172.18.28.20:5700) TRXD header version 1 -> 1
2026-01-29 02:45:03.088 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.28.20:5700/1) Recv RXTUNE cmd
2026-01-29 02:45:03.088 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.28.20:5700/1) Recv TXTUNE cmd
2026-01-29 02:45:03.088 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.28.20:5700/1) Recv SETFORMAT cmd
2026-01-29 02:45:03.088 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.28.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:45:03.088 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:45:03.088 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.28.20:5700/1) Recv NOMTXPOWER cmd
2026-01-29 02:45:03.088 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.28.20:5700/1) Recv SETFORMAT cmd
2026-01-29 02:45:03.088 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.28.20:5700/1) TRXD header version 1 -> 1
2026-01-29 02:45:03.090 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.28.20:5700/2) Recv RXTUNE cmd
2026-01-29 02:45:03.091 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.28.20:5700/2) Recv TXTUNE cmd
2026-01-29 02:45:03.091 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.28.20:5700/2) Recv SETFORMAT cmd
2026-01-29 02:45:03.091 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.28.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:45:03.091 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:45:03.091 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.28.20:5700/2) Recv NOMTXPOWER cmd
2026-01-29 02:45:03.091 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.28.20:5700/2) Recv SETFORMAT cmd
2026-01-29 02:45:03.091 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.28.20:5700/2) TRXD header version 1 -> 1
2026-01-29 02:45:03.093 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.28.20:5700/3) Recv RXTUNE cmd
2026-01-29 02:45:03.093 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.28.20:5700/3) Recv TXTUNE cmd
2026-01-29 02:45:03.093 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.28.20:5700/3) Recv SETFORMAT cmd
2026-01-29 02:45:03.093 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.28.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:45:03.093 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:45:03.093 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.28.20:5700/3) Recv NOMTXPOWER cmd
2026-01-29 02:45:03.093 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.28.20:5700/3) Recv SETFORMAT cmd
2026-01-29 02:45:03.093 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.28.20:5700/3) TRXD header version 1 -> 1
2026-01-29 02:45:03.096 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.28.20:5700) Recv RXTUNE cmd
2026-01-29 02:45:03.096 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETTSC
2026-01-29 02:45:03.096 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETTSC
2026-01-29 02:45:03.096 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETTSC
2026-01-29 02:45:03.096 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.28.20:5700) Recv TXTUNE cmd
2026-01-29 02:45:03.096 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETRXGAIN
2026-01-29 02:45:03.096 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETRXGAIN
2026-01-29 02:45:03.096 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETRXGAIN
2026-01-29 02:45:03.096 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETTSC
2026-01-29 02:45:03.096 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:45:03.096 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:45:03.096 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.28.20:5700) Recv NOMTXPOWER cmd
2026-01-29 02:45:03.096 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:45:03.096 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:45:03.096 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:45:03.096 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.28.20:5700) Recv POWERON CMD
2026-01-29 02:45:03.096 [INFO] ctrl_if_trx.py:109 (BTS@172.18.28.20:5700) Starting transceiver...
2026-01-29 02:45:03.097 [INFO] transceiver.py:243 Starting clock generator
2026-01-29 02:45:03.097 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-01-29 02:45:03.097 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:45:03.097 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:45:03.097 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:45:03.097 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETRXGAIN
2026-01-29 02:45:03.098 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:45:03.098 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:45:03.098 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:45:03.098 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:45:03.098 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:45:03.098 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:45:03.098 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:45:03.098 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:45:03.098 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:45:03.098 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:45:03.098 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:45:03.098 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:45:03.098 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:45:03.098 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:45:03.098 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:45:03.098 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:45:03.098 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:45:03.098 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:45:03.099 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:45:03.099 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:45:03.099 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:45:03.099 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:45:03.099 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:45:03.099 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 02:45:03.099 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:45:03.099 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.28.20:5700) Recv POWEROFF cmd
2026-01-29 02:45:03.099 [INFO] ctrl_if_trx.py:117 (BTS@172.18.28.20:5700) Stopping transceiver...
2026-01-29 02:45:03.099 [INFO] transceiver.py:246 Stopping clock generator
2026-01-29 02:45:03.099 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:45:03.099 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:45:08.102 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.28.20:5700) Recv POWEROFF cmd
2026-01-29 02:45:08.102 [INFO] ctrl_if_trx.py:117 (BTS@172.18.28.20:5700) Stopping transceiver...
2026-01-29 02:45:08.107 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:45:08.107 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:45:08.107 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:45:08.107 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 02:45:08.115 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 02:45:08.116 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.28.20:5700) Recv SETFORMAT cmd
2026-01-29 02:45:08.116 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.28.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:45:08.116 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.28.20:5700) Recv SETFORMAT cmd
2026-01-29 02:45:08.116 [INFO] ctrl_if_trx.py:201 (BTS@172.18.28.20:5700) TRXD header version 1 -> 1
2026-01-29 02:45:08.120 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.28.20:5700/1) Recv RXTUNE cmd
2026-01-29 02:45:08.120 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.28.20:5700/1) Recv TXTUNE cmd
2026-01-29 02:45:08.120 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.28.20:5700/1) Recv SETFORMAT cmd
2026-01-29 02:45:08.120 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.28.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:45:08.121 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:45:08.121 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.28.20:5700/1) Recv NOMTXPOWER cmd
2026-01-29 02:45:08.121 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.28.20:5700/1) Recv SETFORMAT cmd
2026-01-29 02:45:08.121 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.28.20:5700/1) TRXD header version 1 -> 1
2026-01-29 02:45:08.124 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.28.20:5700/2) Recv RXTUNE cmd
2026-01-29 02:45:08.124 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.28.20:5700/2) Recv TXTUNE cmd
2026-01-29 02:45:08.124 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.28.20:5700/2) Recv SETFORMAT cmd
2026-01-29 02:45:08.124 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.28.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:45:08.124 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:45:08.124 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.28.20:5700/2) Recv NOMTXPOWER cmd
2026-01-29 02:45:08.124 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.28.20:5700/2) Recv SETFORMAT cmd
2026-01-29 02:45:08.124 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.28.20:5700/2) TRXD header version 1 -> 1
2026-01-29 02:45:08.127 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.28.20:5700/3) Recv RXTUNE cmd
2026-01-29 02:45:08.127 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.28.20:5700/3) Recv TXTUNE cmd
2026-01-29 02:45:08.127 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.28.20:5700/3) Recv SETFORMAT cmd
2026-01-29 02:45:08.127 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.28.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:45:08.127 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:45:08.127 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.28.20:5700/3) Recv NOMTXPOWER cmd
2026-01-29 02:45:08.127 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.28.20:5700/3) Recv SETFORMAT cmd
2026-01-29 02:45:08.127 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.28.20:5700/3) TRXD header version 1 -> 1
2026-01-29 02:45:08.131 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.28.20:5700) Recv RXTUNE cmd
2026-01-29 02:45:08.131 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETTSC
2026-01-29 02:45:08.131 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETTSC
2026-01-29 02:45:08.131 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETTSC
2026-01-29 02:45:08.131 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.28.20:5700) Recv TXTUNE cmd
2026-01-29 02:45:08.131 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETRXGAIN
2026-01-29 02:45:08.131 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETRXGAIN
2026-01-29 02:45:08.131 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETRXGAIN
2026-01-29 02:45:08.131 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETTSC
2026-01-29 02:45:08.131 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:45:08.131 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:45:08.131 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:45:08.131 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.28.20:5700) Recv NOMTXPOWER cmd
2026-01-29 02:45:08.131 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:45:08.131 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:45:08.131 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:45:08.131 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.28.20:5700) Recv POWERON CMD
2026-01-29 02:45:08.132 [INFO] ctrl_if_trx.py:109 (BTS@172.18.28.20:5700) Starting transceiver...
2026-01-29 02:45:08.132 [INFO] transceiver.py:243 Starting clock generator
2026-01-29 02:45:08.132 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-01-29 02:45:08.132 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:45:08.132 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:45:08.132 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:45:08.132 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETRXGAIN
2026-01-29 02:45:08.132 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:45:08.132 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:45:08.132 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:45:08.132 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:45:08.132 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:45:08.133 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:45:08.133 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:45:08.133 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:45:08.133 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:45:08.133 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:45:08.133 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:45:08.133 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:45:08.133 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:45:08.133 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:45:08.133 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:45:08.133 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:45:08.133 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:45:08.133 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:45:08.133 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:45:08.133 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:45:08.133 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:45:08.133 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:45:08.133 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:45:08.137 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-01-29 02:45:08.611 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-01-29 02:45:08.666 [DEBUG] fake_trx.py:278 (BTS@172.18.28.20:5700) Recv FAKE_TOA cmd
2026-01-29 02:45:08.667 [DEBUG] fake_trx.py:297 (BTS@172.18.28.20:5700) Recv FAKE_RSSI cmd
2026-01-29 02:45:08.668 [DEBUG] fake_trx.py:322 (BTS@172.18.28.20:5700) Recv FAKE_CI cmd
2026-01-29 02:45:08.669 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:45:08.681 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 02:45:08.681 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 02:45:08.681 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 02:45:08.688 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:45:08.688 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 02:45:08.688 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 02:45:08.688 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.28.22:6700) Recv POWERON CMD
2026-01-29 02:45:08.688 [INFO] ctrl_if_trx.py:109 (MS@172.18.28.22:6700) Starting transceiver...
2026-01-29 02:45:08.705 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:45:08.712 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 02:45:08.712 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 02:45:08.712 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:45:08.712 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:45:09.086 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-01-29 02:45:09.137 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 02:45:09.137 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:45:09.139 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:45:09.143 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:45:09.565 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-01-29 02:45:10.042 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-01-29 02:45:10.137 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 02:45:10.138 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:45:10.140 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:45:10.144 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:45:10.521 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-01-29 02:45:10.998 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-01-29 02:45:11.138 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 02:45:11.138 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:45:11.141 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:45:11.145 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:45:11.477 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-01-29 02:45:11.955 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-01-29 02:45:12.139 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 02:45:12.139 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:45:12.142 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:45:12.147 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:45:12.433 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-01-29 02:45:12.767 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:45:12.770 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:45:12.771 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 02:45:12.771 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 02:45:12.788 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 02:45:12.788 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 02:45:12.788 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 02:45:12.790 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:45:12.790 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 02:45:12.790 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 02:45:12.790 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.28.22:6700) Recv POWERON CMD
2026-01-29 02:45:12.790 [INFO] ctrl_if_trx.py:109 (MS@172.18.28.22:6700) Starting transceiver...
2026-01-29 02:45:12.830 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:45:12.836 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 02:45:12.837 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 02:45:12.838 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:45:12.838 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:45:12.911 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-01-29 02:45:13.140 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:45:13.140 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 02:45:13.143 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:45:13.147 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:45:13.389 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-01-29 02:45:13.867 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-01-29 02:45:14.344 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-01-29 02:45:14.822 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-01-29 02:45:15.300 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-01-29 02:45:15.778 [DEBUG] clck_gen.py:113 IND CLOCK 1632
2026-01-29 02:45:16.256 [DEBUG] clck_gen.py:113 IND CLOCK 1734
2026-01-29 02:45:16.734 [DEBUG] clck_gen.py:113 IND CLOCK 1836
2026-01-29 02:45:17.087 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:45:17.089 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:45:17.090 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 02:45:17.090 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 02:45:17.108 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 02:45:17.108 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 02:45:17.109 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 02:45:17.111 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:45:17.111 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 02:45:17.111 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 02:45:17.111 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.28.22:6700) Recv POWERON CMD
2026-01-29 02:45:17.111 [INFO] ctrl_if_trx.py:109 (MS@172.18.28.22:6700) Starting transceiver...
2026-01-29 02:45:17.182 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:45:17.185 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 02:45:17.185 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 02:45:17.185 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:45:17.185 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:45:17.212 [DEBUG] clck_gen.py:113 IND CLOCK 1938
2026-01-29 02:45:17.690 [DEBUG] clck_gen.py:113 IND CLOCK 2040
2026-01-29 02:45:18.168 [DEBUG] clck_gen.py:113 IND CLOCK 2142
2026-01-29 02:45:18.646 [DEBUG] clck_gen.py:113 IND CLOCK 2244
2026-01-29 02:45:19.125 [DEBUG] clck_gen.py:113 IND CLOCK 2346
2026-01-29 02:45:19.603 [DEBUG] clck_gen.py:113 IND CLOCK 2448
2026-01-29 02:45:20.081 [DEBUG] clck_gen.py:113 IND CLOCK 2550
2026-01-29 02:45:20.559 [DEBUG] clck_gen.py:113 IND CLOCK 2652
2026-01-29 02:45:21.037 [DEBUG] clck_gen.py:113 IND CLOCK 2754
2026-01-29 02:45:21.515 [DEBUG] clck_gen.py:113 IND CLOCK 2856
2026-01-29 02:45:21.606 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:45:21.608 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:45:21.609 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 02:45:21.609 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 02:45:21.627 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 02:45:21.627 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 02:45:21.627 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 02:45:21.630 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:45:21.630 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 02:45:21.630 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 02:45:21.630 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.28.22:6700) Recv POWERON CMD
2026-01-29 02:45:21.630 [INFO] ctrl_if_trx.py:109 (MS@172.18.28.22:6700) Starting transceiver...
2026-01-29 02:45:21.670 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:45:21.675 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 02:45:21.675 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 02:45:21.675 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:45:21.675 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:45:21.991 [DEBUG] clck_gen.py:113 IND CLOCK 2958
2026-01-29 02:45:22.469 [DEBUG] clck_gen.py:113 IND CLOCK 3060
2026-01-29 02:45:22.947 [DEBUG] clck_gen.py:113 IND CLOCK 3162
2026-01-29 02:45:23.425 [DEBUG] clck_gen.py:113 IND CLOCK 3264
2026-01-29 02:45:23.903 [DEBUG] clck_gen.py:113 IND CLOCK 3366
2026-01-29 02:45:24.380 [DEBUG] clck_gen.py:113 IND CLOCK 3468
2026-01-29 02:45:24.858 [DEBUG] clck_gen.py:113 IND CLOCK 3570
2026-01-29 02:45:25.336 [DEBUG] clck_gen.py:113 IND CLOCK 3672
2026-01-29 02:45:25.814 [DEBUG] clck_gen.py:113 IND CLOCK 3774
2026-01-29 02:45:25.925 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:45:25.927 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:45:25.928 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 02:45:25.928 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 02:45:25.946 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 02:45:25.946 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 02:45:25.946 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 02:45:25.948 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:45:25.948 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 02:45:25.948 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 02:45:25.948 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.28.22:6700) Recv POWERON CMD
2026-01-29 02:45:25.948 [INFO] ctrl_if_trx.py:109 (MS@172.18.28.22:6700) Starting transceiver...
2026-01-29 02:45:25.999 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:45:26.004 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 02:45:26.005 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 02:45:26.005 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:45:26.005 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:45:26.289 [DEBUG] clck_gen.py:113 IND CLOCK 3876
2026-01-29 02:45:26.767 [DEBUG] clck_gen.py:113 IND CLOCK 3978
2026-01-29 02:45:27.246 [DEBUG] clck_gen.py:113 IND CLOCK 4080
2026-01-29 02:45:27.724 [DEBUG] clck_gen.py:113 IND CLOCK 4182
2026-01-29 02:45:28.202 [DEBUG] clck_gen.py:113 IND CLOCK 4284
2026-01-29 02:45:28.680 [DEBUG] clck_gen.py:113 IND CLOCK 4386
2026-01-29 02:45:29.158 [DEBUG] clck_gen.py:113 IND CLOCK 4488
2026-01-29 02:45:29.637 [DEBUG] clck_gen.py:113 IND CLOCK 4590
2026-01-29 02:45:30.114 [DEBUG] clck_gen.py:113 IND CLOCK 4692
2026-01-29 02:45:30.593 [DEBUG] clck_gen.py:113 IND CLOCK 4794
2026-01-29 02:45:30.605 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:45:30.607 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:45:30.608 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 02:45:30.608 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 02:45:30.626 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 02:45:30.626 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 02:45:30.626 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 02:45:30.628 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:45:30.628 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 02:45:30.628 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 02:45:30.628 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.28.22:6700) Recv POWERON CMD
2026-01-29 02:45:30.628 [INFO] ctrl_if_trx.py:109 (MS@172.18.28.22:6700) Starting transceiver...
2026-01-29 02:45:30.670 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:45:30.676 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.28.22:6700) Recv SETFH cmd
2026-01-29 02:45:30.676 [INFO] transceiver.py:201 (MS@172.18.28.22:6700) Frequency hopping configured: hsn=2, maio=0, ma_len=2
2026-01-29 02:45:30.676 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:45:30.677 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:45:31.071 [DEBUG] clck_gen.py:113 IND CLOCK 4896
2026-01-29 02:45:31.549 [DEBUG] clck_gen.py:113 IND CLOCK 4998
2026-01-29 02:45:32.028 [DEBUG] clck_gen.py:113 IND CLOCK 5100
2026-01-29 02:45:32.506 [DEBUG] clck_gen.py:113 IND CLOCK 5202
2026-01-29 02:45:32.985 [DEBUG] clck_gen.py:113 IND CLOCK 5304
2026-01-29 02:45:33.463 [DEBUG] clck_gen.py:113 IND CLOCK 5406
2026-01-29 02:45:33.942 [DEBUG] clck_gen.py:113 IND CLOCK 5508
2026-01-29 02:45:34.421 [DEBUG] clck_gen.py:113 IND CLOCK 5610
2026-01-29 02:45:34.900 [DEBUG] clck_gen.py:113 IND CLOCK 5712
2026-01-29 02:45:35.059 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:45:35.062 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:45:35.062 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 02:45:35.062 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 02:45:35.062 [INFO] transceiver.py:205 (MS@172.18.28.22:6700) Frequency hopping disabled
2026-01-29 02:45:35.080 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 02:45:35.080 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 02:45:35.080 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 02:45:35.082 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:45:35.082 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 02:45:35.082 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 02:45:35.082 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.28.22:6700) Recv POWERON CMD
2026-01-29 02:45:35.082 [INFO] ctrl_if_trx.py:109 (MS@172.18.28.22:6700) Starting transceiver...
2026-01-29 02:45:35.136 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:45:35.141 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.28.22:6700) Recv SETFH cmd
2026-01-29 02:45:35.141 [INFO] transceiver.py:201 (MS@172.18.28.22:6700) Frequency hopping configured: hsn=3, maio=3, ma_len=4
2026-01-29 02:45:35.142 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:45:35.142 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:45:35.378 [DEBUG] clck_gen.py:113 IND CLOCK 5814
2026-01-29 02:45:35.858 [DEBUG] clck_gen.py:113 IND CLOCK 5916
2026-01-29 02:45:36.337 [DEBUG] clck_gen.py:113 IND CLOCK 6018
2026-01-29 02:45:36.816 [DEBUG] clck_gen.py:113 IND CLOCK 6120
2026-01-29 02:45:37.295 [DEBUG] clck_gen.py:113 IND CLOCK 6222
2026-01-29 02:45:37.774 [DEBUG] clck_gen.py:113 IND CLOCK 6324
2026-01-29 02:45:38.253 [DEBUG] clck_gen.py:113 IND CLOCK 6426
2026-01-29 02:45:38.730 [DEBUG] clck_gen.py:113 IND CLOCK 6528
2026-01-29 02:45:39.209 [DEBUG] clck_gen.py:113 IND CLOCK 6630
2026-01-29 02:45:39.512 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:45:39.515 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:45:39.516 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 02:45:39.516 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 02:45:39.516 [INFO] transceiver.py:205 (MS@172.18.28.22:6700) Frequency hopping disabled
2026-01-29 02:45:39.534 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 02:45:39.534 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 02:45:39.535 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 02:45:39.537 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:45:39.537 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 02:45:39.537 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 02:45:39.537 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.28.22:6700) Recv POWERON CMD
2026-01-29 02:45:39.537 [INFO] ctrl_if_trx.py:109 (MS@172.18.28.22:6700) Starting transceiver...
2026-01-29 02:45:39.584 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:45:39.585 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:45:39.589 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 02:45:39.589 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 02:45:39.590 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:45:39.590 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:45:39.687 [DEBUG] clck_gen.py:113 IND CLOCK 6732
2026-01-29 02:45:40.165 [DEBUG] clck_gen.py:113 IND CLOCK 6834
2026-01-29 02:45:40.644 [DEBUG] clck_gen.py:113 IND CLOCK 6936
2026-01-29 02:45:41.122 [DEBUG] clck_gen.py:113 IND CLOCK 7038
2026-01-29 02:45:41.600 [DEBUG] clck_gen.py:113 IND CLOCK 7140
2026-01-29 02:45:42.078 [DEBUG] clck_gen.py:113 IND CLOCK 7242
2026-01-29 02:45:42.557 [DEBUG] clck_gen.py:113 IND CLOCK 7344
2026-01-29 02:45:43.035 [DEBUG] clck_gen.py:113 IND CLOCK 7446
2026-01-29 02:45:43.514 [DEBUG] clck_gen.py:113 IND CLOCK 7548
2026-01-29 02:45:43.961 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:45:43.965 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:45:43.965 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 02:45:43.965 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 02:45:43.983 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 02:45:43.983 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 02:45:43.983 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 02:45:43.985 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:45:43.985 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 02:45:43.985 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 02:45:43.985 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.28.22:6700) Recv POWERON CMD
2026-01-29 02:45:43.985 [INFO] ctrl_if_trx.py:109 (MS@172.18.28.22:6700) Starting transceiver...
2026-01-29 02:45:43.991 [DEBUG] clck_gen.py:113 IND CLOCK 7650
2026-01-29 02:45:44.039 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:45:44.044 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 02:45:44.044 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 02:45:44.045 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:45:44.045 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:45:44.468 [DEBUG] clck_gen.py:113 IND CLOCK 7752
2026-01-29 02:45:44.944 [DEBUG] clck_gen.py:113 IND CLOCK 7854
2026-01-29 02:45:45.421 [DEBUG] clck_gen.py:113 IND CLOCK 7956
2026-01-29 02:45:45.899 [DEBUG] clck_gen.py:113 IND CLOCK 8058
2026-01-29 02:45:46.377 [DEBUG] clck_gen.py:113 IND CLOCK 8160
2026-01-29 02:45:46.855 [DEBUG] clck_gen.py:113 IND CLOCK 8262
2026-01-29 02:45:47.333 [DEBUG] clck_gen.py:113 IND CLOCK 8364
2026-01-29 02:45:47.811 [DEBUG] clck_gen.py:113 IND CLOCK 8466
2026-01-29 02:45:48.290 [DEBUG] clck_gen.py:113 IND CLOCK 8568
2026-01-29 02:45:48.406 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:45:48.409 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:45:48.409 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 02:45:48.410 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 02:45:48.427 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 02:45:48.427 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 02:45:48.428 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 02:45:48.429 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:45:48.430 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 02:45:48.430 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 02:45:48.430 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.28.22:6700) Recv POWERON CMD
2026-01-29 02:45:48.430 [INFO] ctrl_if_trx.py:109 (MS@172.18.28.22:6700) Starting transceiver...
2026-01-29 02:45:48.475 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:45:48.476 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:45:48.480 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 02:45:48.481 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 02:45:48.481 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:45:48.482 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:45:48.767 [DEBUG] clck_gen.py:113 IND CLOCK 8670
2026-01-29 02:45:49.246 [DEBUG] clck_gen.py:113 IND CLOCK 8772
2026-01-29 02:45:49.724 [DEBUG] clck_gen.py:113 IND CLOCK 8874
2026-01-29 02:45:50.202 [DEBUG] clck_gen.py:113 IND CLOCK 8976
2026-01-29 02:45:50.680 [DEBUG] clck_gen.py:113 IND CLOCK 9078
2026-01-29 02:45:51.158 [DEBUG] clck_gen.py:113 IND CLOCK 9180
2026-01-29 02:45:51.636 [DEBUG] clck_gen.py:113 IND CLOCK 9282
2026-01-29 02:45:52.115 [DEBUG] clck_gen.py:113 IND CLOCK 9384
2026-01-29 02:45:52.594 [DEBUG] clck_gen.py:113 IND CLOCK 9486
2026-01-29 02:45:53.072 [DEBUG] clck_gen.py:113 IND CLOCK 9588
2026-01-29 02:45:53.549 [DEBUG] clck_gen.py:113 IND CLOCK 9690
2026-01-29 02:45:53.712 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:45:53.715 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:45:53.715 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 02:45:53.715 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 02:45:53.733 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 02:45:53.734 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 02:45:53.734 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 02:45:53.736 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:45:53.736 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 02:45:53.736 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 02:45:53.736 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.28.22:6700) Recv POWERON CMD
2026-01-29 02:45:53.736 [INFO] ctrl_if_trx.py:109 (MS@172.18.28.22:6700) Starting transceiver...
2026-01-29 02:45:53.785 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:45:53.790 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.28.22:6700) Recv SETFH cmd
2026-01-29 02:45:53.791 [INFO] transceiver.py:201 (MS@172.18.28.22:6700) Frequency hopping configured: hsn=5, maio=0, ma_len=4
2026-01-29 02:45:53.791 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:45:53.791 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:45:54.027 [DEBUG] clck_gen.py:113 IND CLOCK 9792
2026-01-29 02:45:54.506 [DEBUG] clck_gen.py:113 IND CLOCK 9894
2026-01-29 02:45:54.986 [DEBUG] clck_gen.py:113 IND CLOCK 9996
2026-01-29 02:45:55.465 [DEBUG] clck_gen.py:113 IND CLOCK 10098
2026-01-29 02:45:55.944 [DEBUG] clck_gen.py:113 IND CLOCK 10200
2026-01-29 02:45:56.422 [DEBUG] clck_gen.py:113 IND CLOCK 10302
2026-01-29 02:45:56.901 [DEBUG] clck_gen.py:113 IND CLOCK 10404
2026-01-29 02:45:57.380 [DEBUG] clck_gen.py:113 IND CLOCK 10506
2026-01-29 02:45:57.859 [DEBUG] clck_gen.py:113 IND CLOCK 10608
2026-01-29 02:45:58.337 [DEBUG] clck_gen.py:113 IND CLOCK 10710
2026-01-29 02:45:58.590 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:45:58.594 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:45:58.594 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 02:45:58.594 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 02:45:58.595 [INFO] transceiver.py:205 (MS@172.18.28.22:6700) Frequency hopping disabled
2026-01-29 02:45:58.608 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 02:45:58.608 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 02:45:58.608 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 02:45:58.611 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:45:58.611 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 02:45:58.611 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 02:45:58.611 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.28.22:6700) Recv POWERON CMD
2026-01-29 02:45:58.611 [INFO] ctrl_if_trx.py:109 (MS@172.18.28.22:6700) Starting transceiver...
2026-01-29 02:45:58.654 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:45:58.660 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.28.22:6700) Recv SETFH cmd
2026-01-29 02:45:58.661 [INFO] transceiver.py:201 (MS@172.18.28.22:6700) Frequency hopping configured: hsn=5, maio=0, ma_len=4
2026-01-29 02:45:58.661 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:45:58.662 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:45:58.816 [DEBUG] clck_gen.py:113 IND CLOCK 10812
2026-01-29 02:45:59.295 [DEBUG] clck_gen.py:113 IND CLOCK 10914
2026-01-29 02:45:59.775 [DEBUG] clck_gen.py:113 IND CLOCK 11016
2026-01-29 02:46:00.255 [DEBUG] clck_gen.py:113 IND CLOCK 11118
2026-01-29 02:46:00.735 [DEBUG] clck_gen.py:113 IND CLOCK 11220
2026-01-29 02:46:01.214 [DEBUG] clck_gen.py:113 IND CLOCK 11322
2026-01-29 02:46:01.693 [DEBUG] clck_gen.py:113 IND CLOCK 11424
2026-01-29 02:46:02.171 [DEBUG] clck_gen.py:113 IND CLOCK 11526
2026-01-29 02:46:02.650 [DEBUG] clck_gen.py:113 IND CLOCK 11628
2026-01-29 02:46:03.044 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:46:03.047 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:46:03.048 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 02:46:03.048 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 02:46:03.048 [INFO] transceiver.py:205 (MS@172.18.28.22:6700) Frequency hopping disabled
2026-01-29 02:46:03.068 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 02:46:03.068 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 02:46:03.068 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 02:46:03.070 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:46:03.070 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 02:46:03.071 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 02:46:03.071 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.28.22:6700) Recv POWERON CMD
2026-01-29 02:46:03.071 [INFO] ctrl_if_trx.py:109 (MS@172.18.28.22:6700) Starting transceiver...
2026-01-29 02:46:03.122 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:46:03.127 [DEBUG] clck_gen.py:113 IND CLOCK 11730
2026-01-29 02:46:03.128 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.28.22:6700) Recv SETFH cmd
2026-01-29 02:46:03.128 [INFO] transceiver.py:201 (MS@172.18.28.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2026-01-29 02:46:03.129 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:46:03.129 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:46:03.606 [DEBUG] clck_gen.py:113 IND CLOCK 11832
2026-01-29 02:46:04.085 [DEBUG] clck_gen.py:113 IND CLOCK 11934
2026-01-29 02:46:04.563 [DEBUG] clck_gen.py:113 IND CLOCK 12036
2026-01-29 02:46:05.042 [DEBUG] clck_gen.py:113 IND CLOCK 12138
2026-01-29 02:46:05.520 [DEBUG] clck_gen.py:113 IND CLOCK 12240
2026-01-29 02:46:05.998 [DEBUG] clck_gen.py:113 IND CLOCK 12342
2026-01-29 02:46:06.476 [DEBUG] clck_gen.py:113 IND CLOCK 12444
2026-01-29 02:46:06.955 [DEBUG] clck_gen.py:113 IND CLOCK 12546
2026-01-29 02:46:07.241 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:46:07.244 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:46:07.244 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 02:46:07.245 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 02:46:07.245 [INFO] transceiver.py:205 (MS@172.18.28.22:6700) Frequency hopping disabled
2026-01-29 02:46:07.257 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 02:46:07.257 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 02:46:07.257 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 02:46:07.260 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:46:07.260 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 02:46:07.260 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 02:46:07.260 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.28.22:6700) Recv POWERON CMD
2026-01-29 02:46:07.260 [INFO] ctrl_if_trx.py:109 (MS@172.18.28.22:6700) Starting transceiver...
2026-01-29 02:46:07.302 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:46:07.308 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.28.22:6700) Recv SETFH cmd
2026-01-29 02:46:07.308 [INFO] transceiver.py:201 (MS@172.18.28.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2026-01-29 02:46:07.308 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:46:07.308 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:46:07.433 [DEBUG] clck_gen.py:113 IND CLOCK 12648
2026-01-29 02:46:07.911 [DEBUG] clck_gen.py:113 IND CLOCK 12750
2026-01-29 02:46:08.390 [DEBUG] clck_gen.py:113 IND CLOCK 12852
2026-01-29 02:46:08.867 [DEBUG] clck_gen.py:113 IND CLOCK 12954
2026-01-29 02:46:09.346 [DEBUG] clck_gen.py:113 IND CLOCK 13056
2026-01-29 02:46:09.824 [DEBUG] clck_gen.py:113 IND CLOCK 13158
2026-01-29 02:46:10.302 [DEBUG] clck_gen.py:113 IND CLOCK 13260
2026-01-29 02:46:10.780 [DEBUG] clck_gen.py:113 IND CLOCK 13362
2026-01-29 02:46:11.259 [DEBUG] clck_gen.py:113 IND CLOCK 13464
2026-01-29 02:46:11.565 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:46:11.568 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:46:11.568 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 02:46:11.568 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 02:46:11.568 [INFO] transceiver.py:205 (MS@172.18.28.22:6700) Frequency hopping disabled
2026-01-29 02:46:11.585 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 02:46:11.585 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 02:46:11.586 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 02:46:11.588 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:46:11.588 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 02:46:11.588 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 02:46:11.588 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.28.22:6700) Recv POWERON CMD
2026-01-29 02:46:11.588 [INFO] ctrl_if_trx.py:109 (MS@172.18.28.22:6700) Starting transceiver...
2026-01-29 02:46:11.633 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:46:11.639 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.28.22:6700) Recv SETFH cmd
2026-01-29 02:46:11.639 [INFO] transceiver.py:201 (MS@172.18.28.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2026-01-29 02:46:11.639 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:46:11.640 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:46:11.737 [DEBUG] clck_gen.py:113 IND CLOCK 13566
2026-01-29 02:46:12.215 [DEBUG] clck_gen.py:113 IND CLOCK 13668
2026-01-29 02:46:12.694 [DEBUG] clck_gen.py:113 IND CLOCK 13770
2026-01-29 02:46:13.173 [DEBUG] clck_gen.py:113 IND CLOCK 13872
2026-01-29 02:46:13.652 [DEBUG] clck_gen.py:113 IND CLOCK 13974
2026-01-29 02:46:14.130 [DEBUG] clck_gen.py:113 IND CLOCK 14076
2026-01-29 02:46:14.608 [DEBUG] clck_gen.py:113 IND CLOCK 14178
2026-01-29 02:46:15.086 [DEBUG] clck_gen.py:113 IND CLOCK 14280
2026-01-29 02:46:15.565 [DEBUG] clck_gen.py:113 IND CLOCK 14382
2026-01-29 02:46:15.888 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:46:15.891 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:46:15.891 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 02:46:15.891 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 02:46:15.891 [INFO] transceiver.py:205 (MS@172.18.28.22:6700) Frequency hopping disabled
2026-01-29 02:46:15.908 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 02:46:15.908 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 02:46:15.909 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 02:46:15.911 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:46:15.911 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 02:46:15.911 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 02:46:15.911 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.28.22:6700) Recv POWERON CMD
2026-01-29 02:46:15.911 [INFO] ctrl_if_trx.py:109 (MS@172.18.28.22:6700) Starting transceiver...
2026-01-29 02:46:15.954 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:46:15.960 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.28.22:6700) Recv SETFH cmd
2026-01-29 02:46:15.960 [INFO] transceiver.py:201 (MS@172.18.28.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2026-01-29 02:46:15.960 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:46:15.961 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:46:16.042 [DEBUG] clck_gen.py:113 IND CLOCK 14484
2026-01-29 02:46:16.521 [DEBUG] clck_gen.py:113 IND CLOCK 14586
2026-01-29 02:46:17.000 [DEBUG] clck_gen.py:113 IND CLOCK 14688
2026-01-29 02:46:17.478 [DEBUG] clck_gen.py:113 IND CLOCK 14790
2026-01-29 02:46:17.956 [DEBUG] clck_gen.py:113 IND CLOCK 14892
2026-01-29 02:46:18.435 [DEBUG] clck_gen.py:113 IND CLOCK 14994
2026-01-29 02:46:18.914 [DEBUG] clck_gen.py:113 IND CLOCK 15096
2026-01-29 02:46:19.392 [DEBUG] clck_gen.py:113 IND CLOCK 15198
2026-01-29 02:46:19.871 [DEBUG] clck_gen.py:113 IND CLOCK 15300
2026-01-29 02:46:20.212 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:46:20.215 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:46:20.216 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 02:46:20.216 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 02:46:20.216 [INFO] transceiver.py:205 (MS@172.18.28.22:6700) Frequency hopping disabled
2026-01-29 02:46:20.234 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 02:46:20.234 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 02:46:20.234 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 02:46:20.237 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:46:20.237 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 02:46:20.237 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 02:46:20.237 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.28.22:6700) Recv POWERON CMD
2026-01-29 02:46:20.237 [INFO] ctrl_if_trx.py:109 (MS@172.18.28.22:6700) Starting transceiver...
2026-01-29 02:46:20.278 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:46:20.284 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.28.22:6700) Recv SETFH cmd
2026-01-29 02:46:20.284 [INFO] transceiver.py:201 (MS@172.18.28.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2026-01-29 02:46:20.284 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:46:20.284 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:46:20.348 [DEBUG] clck_gen.py:113 IND CLOCK 15402
2026-01-29 02:46:20.827 [DEBUG] clck_gen.py:113 IND CLOCK 15504
2026-01-29 02:46:21.306 [DEBUG] clck_gen.py:113 IND CLOCK 15606
2026-01-29 02:46:21.785 [DEBUG] clck_gen.py:113 IND CLOCK 15708
2026-01-29 02:46:22.263 [DEBUG] clck_gen.py:113 IND CLOCK 15810
2026-01-29 02:46:22.741 [DEBUG] clck_gen.py:113 IND CLOCK 15912
2026-01-29 02:46:23.219 [DEBUG] clck_gen.py:113 IND CLOCK 16014
2026-01-29 02:46:23.693 [DEBUG] clck_gen.py:113 IND CLOCK 16116
2026-01-29 02:46:24.172 [DEBUG] clck_gen.py:113 IND CLOCK 16218
2026-01-29 02:46:24.651 [DEBUG] clck_gen.py:113 IND CLOCK 16320
2026-01-29 02:46:24.698 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:46:24.700 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:46:24.701 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 02:46:24.701 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 02:46:24.701 [INFO] transceiver.py:205 (MS@172.18.28.22:6700) Frequency hopping disabled
2026-01-29 02:46:24.720 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 02:46:24.720 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 02:46:24.720 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 02:46:24.722 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:46:24.722 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 02:46:24.722 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 02:46:24.723 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.28.22:6700) Recv POWERON CMD
2026-01-29 02:46:24.723 [INFO] ctrl_if_trx.py:109 (MS@172.18.28.22:6700) Starting transceiver...
2026-01-29 02:46:24.766 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:46:24.773 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.28.22:6700) Recv SETFH cmd
2026-01-29 02:46:24.773 [INFO] transceiver.py:201 (MS@172.18.28.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2026-01-29 02:46:24.773 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:46:24.773 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:46:25.128 [DEBUG] clck_gen.py:113 IND CLOCK 16422
2026-01-29 02:46:25.607 [DEBUG] clck_gen.py:113 IND CLOCK 16524
2026-01-29 02:46:26.085 [DEBUG] clck_gen.py:113 IND CLOCK 16626
2026-01-29 02:46:26.564 [DEBUG] clck_gen.py:113 IND CLOCK 16728
2026-01-29 02:46:27.043 [DEBUG] clck_gen.py:113 IND CLOCK 16830
2026-01-29 02:46:27.522 [DEBUG] clck_gen.py:113 IND CLOCK 16932
2026-01-29 02:46:28.000 [DEBUG] clck_gen.py:113 IND CLOCK 17034
2026-01-29 02:46:28.479 [DEBUG] clck_gen.py:113 IND CLOCK 17136
2026-01-29 02:46:28.958 [DEBUG] clck_gen.py:113 IND CLOCK 17238
2026-01-29 02:46:29.017 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:46:29.020 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:46:29.020 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 02:46:29.020 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 02:46:29.020 [INFO] transceiver.py:205 (MS@172.18.28.22:6700) Frequency hopping disabled
2026-01-29 02:46:29.033 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 02:46:29.033 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 02:46:29.033 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 02:46:29.036 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:46:29.036 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 02:46:29.036 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 02:46:29.036 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.28.22:6700) Recv POWERON CMD
2026-01-29 02:46:29.036 [INFO] ctrl_if_trx.py:109 (MS@172.18.28.22:6700) Starting transceiver...
2026-01-29 02:46:29.078 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:46:29.084 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.28.22:6700) Recv SETFH cmd
2026-01-29 02:46:29.085 [INFO] transceiver.py:201 (MS@172.18.28.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2026-01-29 02:46:29.085 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:46:29.085 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:46:29.436 [DEBUG] clck_gen.py:113 IND CLOCK 17340
2026-01-29 02:46:29.915 [DEBUG] clck_gen.py:113 IND CLOCK 17442
2026-01-29 02:46:30.394 [DEBUG] clck_gen.py:113 IND CLOCK 17544
2026-01-29 02:46:30.872 [DEBUG] clck_gen.py:113 IND CLOCK 17646
2026-01-29 02:46:31.351 [DEBUG] clck_gen.py:113 IND CLOCK 17748
2026-01-29 02:46:31.830 [DEBUG] clck_gen.py:113 IND CLOCK 17850
2026-01-29 02:46:32.309 [DEBUG] clck_gen.py:113 IND CLOCK 17952
2026-01-29 02:46:32.787 [DEBUG] clck_gen.py:113 IND CLOCK 18054
2026-01-29 02:46:33.266 [DEBUG] clck_gen.py:113 IND CLOCK 18156
2026-01-29 02:46:33.344 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:46:33.347 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:46:33.348 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 02:46:33.348 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 02:46:33.348 [INFO] transceiver.py:205 (MS@172.18.28.22:6700) Frequency hopping disabled
2026-01-29 02:46:33.366 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 02:46:33.366 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 02:46:33.367 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 02:46:33.368 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:46:33.368 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 02:46:33.368 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 02:46:33.369 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.28.22:6700) Recv POWERON CMD
2026-01-29 02:46:33.369 [INFO] ctrl_if_trx.py:109 (MS@172.18.28.22:6700) Starting transceiver...
2026-01-29 02:46:33.414 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:46:33.419 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.28.22:6700) Recv SETFH cmd
2026-01-29 02:46:33.419 [INFO] transceiver.py:201 (MS@172.18.28.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2026-01-29 02:46:33.420 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:46:33.420 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:46:33.742 [DEBUG] clck_gen.py:113 IND CLOCK 18258
2026-01-29 02:46:34.220 [DEBUG] clck_gen.py:113 IND CLOCK 18360
2026-01-29 02:46:34.698 [DEBUG] clck_gen.py:113 IND CLOCK 18462
2026-01-29 02:46:35.177 [DEBUG] clck_gen.py:113 IND CLOCK 18564
2026-01-29 02:46:35.656 [DEBUG] clck_gen.py:113 IND CLOCK 18666
2026-01-29 02:46:36.135 [DEBUG] clck_gen.py:113 IND CLOCK 18768
2026-01-29 02:46:36.613 [DEBUG] clck_gen.py:113 IND CLOCK 18870
2026-01-29 02:46:37.092 [DEBUG] clck_gen.py:113 IND CLOCK 18972
2026-01-29 02:46:37.570 [DEBUG] clck_gen.py:113 IND CLOCK 19074
2026-01-29 02:46:37.668 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:46:37.670 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:46:37.671 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 02:46:37.671 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 02:46:37.671 [INFO] transceiver.py:205 (MS@172.18.28.22:6700) Frequency hopping disabled
2026-01-29 02:46:37.684 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 02:46:37.684 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:46:37.685 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:46:37.685 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:46:37.687 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 02:46:37.687 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:46:37.687 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:46:37.687 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:46:37.687 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.28.20:5700) Recv POWEROFF cmd
2026-01-29 02:46:37.687 [INFO] ctrl_if_trx.py:117 (BTS@172.18.28.20:5700) Stopping transceiver...
2026-01-29 02:46:37.687 [INFO] transceiver.py:246 Stopping clock generator
2026-01-29 02:46:37.687 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=19101 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:46:37.687 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=19101 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:46:37.687 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=19101 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:46:37.687 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=19101 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:46:37.687 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=19101 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:46:37.687 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=19101 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:46:42.687 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.28.20:5700) Recv POWEROFF cmd
2026-01-29 02:46:42.687 [INFO] ctrl_if_trx.py:117 (BTS@172.18.28.20:5700) Stopping transceiver...
2026-01-29 02:46:42.689 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:46:42.690 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:46:42.690 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:46:42.690 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 02:46:42.698 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 02:46:42.699 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.28.20:5700) Recv SETFORMAT cmd
2026-01-29 02:46:42.699 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.28.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:46:42.699 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.28.20:5700) Recv SETFORMAT cmd
2026-01-29 02:46:42.699 [INFO] ctrl_if_trx.py:201 (BTS@172.18.28.20:5700) TRXD header version 1 -> 1
2026-01-29 02:46:42.702 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.28.20:5700/1) Recv RXTUNE cmd
2026-01-29 02:46:42.702 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.28.20:5700/1) Recv TXTUNE cmd
2026-01-29 02:46:42.702 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.28.20:5700/1) Recv SETFORMAT cmd
2026-01-29 02:46:42.702 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.28.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:46:42.703 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:46:42.703 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.28.20:5700/1) Recv NOMTXPOWER cmd
2026-01-29 02:46:42.704 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.28.20:5700/1) Recv SETFORMAT cmd
2026-01-29 02:46:42.704 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.28.20:5700/1) TRXD header version 1 -> 1
2026-01-29 02:46:42.704 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.28.20:5700/2) Recv RXTUNE cmd
2026-01-29 02:46:42.705 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.28.20:5700/2) Recv TXTUNE cmd
2026-01-29 02:46:42.705 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.28.20:5700/2) Recv SETFORMAT cmd
2026-01-29 02:46:42.705 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.28.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:46:42.705 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:46:42.705 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.28.20:5700/2) Recv NOMTXPOWER cmd
2026-01-29 02:46:42.705 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.28.20:5700/2) Recv SETFORMAT cmd
2026-01-29 02:46:42.705 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.28.20:5700/2) TRXD header version 1 -> 1
2026-01-29 02:46:42.707 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.28.20:5700/3) Recv RXTUNE cmd
2026-01-29 02:46:42.707 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.28.20:5700/3) Recv TXTUNE cmd
2026-01-29 02:46:42.707 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.28.20:5700/3) Recv SETFORMAT cmd
2026-01-29 02:46:42.707 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.28.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:46:42.708 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:46:42.708 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.28.20:5700/3) Recv NOMTXPOWER cmd
2026-01-29 02:46:42.708 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.28.20:5700/3) Recv SETFORMAT cmd
2026-01-29 02:46:42.708 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.28.20:5700/3) TRXD header version 1 -> 1
2026-01-29 02:46:42.711 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.28.20:5700) Recv RXTUNE cmd
2026-01-29 02:46:42.711 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETTSC
2026-01-29 02:46:42.711 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETTSC
2026-01-29 02:46:42.711 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETTSC
2026-01-29 02:46:42.711 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.28.20:5700) Recv TXTUNE cmd
2026-01-29 02:46:42.711 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETRXGAIN
2026-01-29 02:46:42.711 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETRXGAIN
2026-01-29 02:46:42.711 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETRXGAIN
2026-01-29 02:46:42.711 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETTSC
2026-01-29 02:46:42.711 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:46:42.711 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:46:42.711 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:46:42.711 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.28.20:5700) Recv NOMTXPOWER cmd
2026-01-29 02:46:42.711 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:46:42.711 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:46:42.711 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:46:42.711 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.28.20:5700) Recv POWERON CMD
2026-01-29 02:46:42.711 [INFO] ctrl_if_trx.py:109 (BTS@172.18.28.20:5700) Starting transceiver...
2026-01-29 02:46:42.711 [INFO] transceiver.py:243 Starting clock generator
2026-01-29 02:46:42.711 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-01-29 02:46:42.712 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:46:42.712 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:46:42.712 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:46:42.712 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETRXGAIN
2026-01-29 02:46:42.713 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:46:42.713 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:46:42.713 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:46:42.713 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:46:42.713 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:46:42.713 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:46:42.713 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:46:42.713 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:46:42.713 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:46:42.713 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:46:42.713 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:46:42.713 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:46:42.713 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:46:42.713 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:46:42.713 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:46:42.713 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:46:42.713 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:46:42.713 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:46:42.714 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:46:42.714 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:46:42.714 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:46:42.714 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:46:42.714 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:46:42.714 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:46:42.714 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 02:46:42.714 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:46:42.714 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.28.20:5700) Recv POWEROFF cmd
2026-01-29 02:46:42.714 [INFO] ctrl_if_trx.py:117 (BTS@172.18.28.20:5700) Stopping transceiver...
2026-01-29 02:46:42.714 [INFO] transceiver.py:246 Stopping clock generator
2026-01-29 02:46:42.714 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:46:47.717 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.28.20:5700) Recv POWEROFF cmd
2026-01-29 02:46:47.717 [INFO] ctrl_if_trx.py:117 (BTS@172.18.28.20:5700) Stopping transceiver...
2026-01-29 02:46:47.719 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:46:47.720 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:46:47.721 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:46:47.722 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 02:46:47.729 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 02:46:47.729 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.28.20:5700) Recv SETFORMAT cmd
2026-01-29 02:46:47.730 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.28.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:46:47.730 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.28.20:5700) Recv SETFORMAT cmd
2026-01-29 02:46:47.730 [INFO] ctrl_if_trx.py:201 (BTS@172.18.28.20:5700) TRXD header version 1 -> 1
2026-01-29 02:46:47.732 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.28.20:5700/1) Recv RXTUNE cmd
2026-01-29 02:46:47.732 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.28.20:5700/1) Recv TXTUNE cmd
2026-01-29 02:46:47.733 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.28.20:5700/1) Recv SETFORMAT cmd
2026-01-29 02:46:47.733 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.28.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:46:47.733 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:46:47.734 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.28.20:5700/1) Recv NOMTXPOWER cmd
2026-01-29 02:46:47.734 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.28.20:5700/1) Recv SETFORMAT cmd
2026-01-29 02:46:47.734 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.28.20:5700/1) TRXD header version 1 -> 1
2026-01-29 02:46:47.735 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.28.20:5700/2) Recv RXTUNE cmd
2026-01-29 02:46:47.735 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.28.20:5700/2) Recv TXTUNE cmd
2026-01-29 02:46:47.735 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.28.20:5700/2) Recv SETFORMAT cmd
2026-01-29 02:46:47.735 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.28.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:46:47.735 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:46:47.735 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.28.20:5700/2) Recv NOMTXPOWER cmd
2026-01-29 02:46:47.735 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.28.20:5700/2) Recv SETFORMAT cmd
2026-01-29 02:46:47.735 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.28.20:5700/2) TRXD header version 1 -> 1
2026-01-29 02:46:47.737 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.28.20:5700/3) Recv RXTUNE cmd
2026-01-29 02:46:47.737 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.28.20:5700/3) Recv TXTUNE cmd
2026-01-29 02:46:47.737 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.28.20:5700/3) Recv SETFORMAT cmd
2026-01-29 02:46:47.737 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.28.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:46:47.737 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:46:47.737 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.28.20:5700/3) Recv NOMTXPOWER cmd
2026-01-29 02:46:47.737 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.28.20:5700/3) Recv SETFORMAT cmd
2026-01-29 02:46:47.737 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.28.20:5700/3) TRXD header version 1 -> 1
2026-01-29 02:46:47.740 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.28.20:5700) Recv RXTUNE cmd
2026-01-29 02:46:47.740 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETTSC
2026-01-29 02:46:47.740 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETTSC
2026-01-29 02:46:47.740 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETTSC
2026-01-29 02:46:47.740 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.28.20:5700) Recv TXTUNE cmd
2026-01-29 02:46:47.740 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETRXGAIN
2026-01-29 02:46:47.740 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETRXGAIN
2026-01-29 02:46:47.740 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETRXGAIN
2026-01-29 02:46:47.740 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETTSC
2026-01-29 02:46:47.740 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:46:47.740 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:46:47.740 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:46:47.740 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.28.20:5700) Recv NOMTXPOWER cmd
2026-01-29 02:46:47.740 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:46:47.740 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:46:47.740 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:46:47.740 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.28.20:5700) Recv POWERON CMD
2026-01-29 02:46:47.740 [INFO] ctrl_if_trx.py:109 (BTS@172.18.28.20:5700) Starting transceiver...
2026-01-29 02:46:47.740 [INFO] transceiver.py:243 Starting clock generator
2026-01-29 02:46:47.740 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-01-29 02:46:47.741 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:46:47.741 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:46:47.741 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:46:47.741 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETRXGAIN
2026-01-29 02:46:47.741 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:46:47.741 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:46:47.741 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:46:47.741 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:46:47.741 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:46:47.741 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:46:47.741 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:46:47.741 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:46:47.741 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:46:47.741 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:46:47.741 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:46:47.741 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:46:47.741 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:46:47.741 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:46:47.741 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:46:47.741 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:46:47.741 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:46:47.741 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:46:47.741 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:46:47.742 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:46:47.742 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:46:47.742 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:46:47.742 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:46:47.745 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-01-29 02:46:48.229 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-01-29 02:46:48.265 [DEBUG] fake_trx.py:278 (BTS@172.18.28.20:5700) Recv FAKE_TOA cmd
2026-01-29 02:46:48.268 [DEBUG] fake_trx.py:297 (BTS@172.18.28.20:5700) Recv FAKE_RSSI cmd
2026-01-29 02:46:48.269 [DEBUG] fake_trx.py:322 (BTS@172.18.28.20:5700) Recv FAKE_CI cmd
2026-01-29 02:46:48.270 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:46:48.294 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 02:46:48.294 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 02:46:48.294 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 02:46:48.299 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:46:48.299 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 02:46:48.299 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 02:46:48.299 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.28.22:6700) Recv POWERON CMD
2026-01-29 02:46:48.299 [INFO] ctrl_if_trx.py:109 (MS@172.18.28.22:6700) Starting transceiver...
2026-01-29 02:46:48.325 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:46:48.330 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 02:46:48.330 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 02:46:48.331 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:46:48.331 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:46:48.706 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-01-29 02:46:48.743 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:46:48.744 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 02:46:48.744 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:46:48.747 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:46:49.184 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-01-29 02:46:49.386 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:46:49.390 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:46:49.390 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 02:46:49.390 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 02:46:49.406 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 02:46:49.406 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 02:46:49.407 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 02:46:49.409 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:46:49.409 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 02:46:49.409 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 02:46:49.409 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.28.22:6700) Recv POWERON CMD
2026-01-29 02:46:49.409 [INFO] ctrl_if_trx.py:109 (MS@172.18.28.22:6700) Starting transceiver...
2026-01-29 02:46:49.450 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:46:49.455 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 02:46:49.456 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 02:46:49.456 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:46:49.456 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:46:49.662 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-01-29 02:46:49.745 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 02:46:49.745 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:46:49.745 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:46:49.749 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:46:50.140 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-01-29 02:46:50.617 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-01-29 02:46:50.746 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 02:46:50.746 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:46:50.746 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:46:50.750 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:46:50.838 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:46:50.841 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:46:50.842 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 02:46:50.842 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 02:46:50.851 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 02:46:50.851 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 02:46:50.851 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 02:46:50.853 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:46:50.853 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 02:46:50.853 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 02:46:50.853 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.28.22:6700) Recv POWERON CMD
2026-01-29 02:46:50.853 [INFO] ctrl_if_trx.py:109 (MS@172.18.28.22:6700) Starting transceiver...
2026-01-29 02:46:50.901 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:46:50.906 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 02:46:50.906 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 02:46:50.906 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:46:50.906 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:46:51.095 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-01-29 02:46:51.573 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-01-29 02:46:51.747 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:46:51.747 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:46:51.747 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 02:46:51.752 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:46:52.010 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:46:52.013 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:46:52.013 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 02:46:52.013 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 02:46:52.026 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 02:46:52.026 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 02:46:52.026 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 02:46:52.031 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:46:52.031 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 02:46:52.031 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 02:46:52.031 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.28.22:6700) Recv POWERON CMD
2026-01-29 02:46:52.031 [INFO] ctrl_if_trx.py:109 (MS@172.18.28.22:6700) Starting transceiver...
2026-01-29 02:46:52.050 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-01-29 02:46:52.074 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:46:52.080 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 02:46:52.081 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 02:46:52.082 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:46:52.082 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:46:52.528 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-01-29 02:46:52.748 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 02:46:52.748 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:46:52.748 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:46:52.752 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:46:53.006 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-01-29 02:46:53.462 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:46:53.465 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:46:53.466 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 02:46:53.466 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 02:46:53.483 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-01-29 02:46:53.484 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 02:46:53.484 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 02:46:53.484 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 02:46:53.486 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:46:53.486 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 02:46:53.486 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 02:46:53.486 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.28.22:6700) Recv POWERON CMD
2026-01-29 02:46:53.486 [INFO] ctrl_if_trx.py:109 (MS@172.18.28.22:6700) Starting transceiver...
2026-01-29 02:46:53.531 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:46:53.537 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 02:46:53.538 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 02:46:53.538 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:46:53.539 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:46:53.961 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-01-29 02:46:54.439 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-01-29 02:46:54.917 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-01-29 02:46:55.045 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:46:55.047 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:46:55.048 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 02:46:55.048 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 02:46:55.048 [WARNING] transceiver.py:257 (MS@172.18.28.22:6700) RX TRXD message (fn=1560 tn=1 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:46:55.065 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 02:46:55.065 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 02:46:55.065 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 02:46:55.068 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:46:55.068 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 02:46:55.068 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 02:46:55.068 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.28.22:6700) Recv POWERON CMD
2026-01-29 02:46:55.068 [INFO] ctrl_if_trx.py:109 (MS@172.18.28.22:6700) Starting transceiver...
2026-01-29 02:46:55.110 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:46:55.116 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.28.22:6700) Recv SETFH cmd
2026-01-29 02:46:55.116 [INFO] transceiver.py:201 (MS@172.18.28.22:6700) Frequency hopping configured: hsn=2, maio=0, ma_len=2
2026-01-29 02:46:55.116 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:46:55.116 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:46:55.395 [DEBUG] clck_gen.py:113 IND CLOCK 1632
2026-01-29 02:46:55.874 [DEBUG] clck_gen.py:113 IND CLOCK 1734
2026-01-29 02:46:56.353 [DEBUG] clck_gen.py:113 IND CLOCK 1836
2026-01-29 02:46:56.568 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:46:56.571 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:46:56.571 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 02:46:56.571 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 02:46:56.572 [INFO] transceiver.py:205 (MS@172.18.28.22:6700) Frequency hopping disabled
2026-01-29 02:46:56.589 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 02:46:56.589 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 02:46:56.590 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 02:46:56.592 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:46:56.592 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 02:46:56.592 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 02:46:56.592 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.28.22:6700) Recv POWERON CMD
2026-01-29 02:46:56.592 [INFO] ctrl_if_trx.py:109 (MS@172.18.28.22:6700) Starting transceiver...
2026-01-29 02:46:56.636 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:46:56.641 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.28.22:6700) Recv SETFH cmd
2026-01-29 02:46:56.641 [INFO] transceiver.py:201 (MS@172.18.28.22:6700) Frequency hopping configured: hsn=3, maio=3, ma_len=4
2026-01-29 02:46:56.642 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:46:56.642 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:46:56.831 [DEBUG] clck_gen.py:113 IND CLOCK 1938
2026-01-29 02:46:57.310 [DEBUG] clck_gen.py:113 IND CLOCK 2040
2026-01-29 02:46:57.788 [DEBUG] clck_gen.py:113 IND CLOCK 2142
2026-01-29 02:46:58.091 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:46:58.094 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:46:58.095 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 02:46:58.095 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 02:46:58.095 [INFO] transceiver.py:205 (MS@172.18.28.22:6700) Frequency hopping disabled
2026-01-29 02:46:58.112 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 02:46:58.112 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 02:46:58.112 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 02:46:58.115 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:46:58.115 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 02:46:58.115 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 02:46:58.115 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.28.22:6700) Recv POWERON CMD
2026-01-29 02:46:58.115 [INFO] ctrl_if_trx.py:109 (MS@172.18.28.22:6700) Starting transceiver...
2026-01-29 02:46:58.163 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:46:58.163 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:46:58.164 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 02:46:58.164 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 02:46:58.164 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:46:58.164 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:46:58.266 [DEBUG] clck_gen.py:113 IND CLOCK 2244
2026-01-29 02:46:58.744 [DEBUG] clck_gen.py:113 IND CLOCK 2346
2026-01-29 02:46:59.222 [DEBUG] clck_gen.py:113 IND CLOCK 2448
2026-01-29 02:46:59.614 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:46:59.616 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:46:59.617 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 02:46:59.617 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 02:46:59.634 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 02:46:59.634 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 02:46:59.634 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 02:46:59.636 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:46:59.636 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 02:46:59.636 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 02:46:59.637 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.28.22:6700) Recv POWERON CMD
2026-01-29 02:46:59.637 [INFO] ctrl_if_trx.py:109 (MS@172.18.28.22:6700) Starting transceiver...
2026-01-29 02:46:59.682 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:46:59.687 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 02:46:59.687 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 02:46:59.687 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:46:59.687 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:46:59.700 [DEBUG] clck_gen.py:113 IND CLOCK 2550
2026-01-29 02:47:00.178 [DEBUG] clck_gen.py:113 IND CLOCK 2652
2026-01-29 02:47:00.657 [DEBUG] clck_gen.py:113 IND CLOCK 2754
2026-01-29 02:47:01.135 [DEBUG] clck_gen.py:113 IND CLOCK 2856
2026-01-29 02:47:01.136 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:47:01.139 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:47:01.139 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 02:47:01.139 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 02:47:01.157 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 02:47:01.157 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 02:47:01.157 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 02:47:01.160 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:47:01.160 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 02:47:01.160 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 02:47:01.160 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.28.22:6700) Recv POWERON CMD
2026-01-29 02:47:01.160 [INFO] ctrl_if_trx.py:109 (MS@172.18.28.22:6700) Starting transceiver...
2026-01-29 02:47:01.202 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:47:01.203 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:47:01.209 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 02:47:01.209 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 02:47:01.209 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:47:01.209 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:47:01.613 [DEBUG] clck_gen.py:113 IND CLOCK 2958
2026-01-29 02:47:02.091 [DEBUG] clck_gen.py:113 IND CLOCK 3060
2026-01-29 02:47:02.537 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:47:02.540 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:47:02.540 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 02:47:02.541 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 02:47:02.558 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 02:47:02.558 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 02:47:02.558 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 02:47:02.561 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:47:02.561 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 02:47:02.561 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 02:47:02.561 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.28.22:6700) Recv POWERON CMD
2026-01-29 02:47:02.561 [INFO] ctrl_if_trx.py:109 (MS@172.18.28.22:6700) Starting transceiver...
2026-01-29 02:47:02.568 [DEBUG] clck_gen.py:113 IND CLOCK 3162
2026-01-29 02:47:02.616 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:47:02.617 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.28.22:6700) Recv SETFH cmd
2026-01-29 02:47:02.617 [INFO] transceiver.py:201 (MS@172.18.28.22:6700) Frequency hopping configured: hsn=5, maio=0, ma_len=4
2026-01-29 02:47:02.617 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:47:02.617 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:47:03.047 [DEBUG] clck_gen.py:113 IND CLOCK 3264
2026-01-29 02:47:03.526 [DEBUG] clck_gen.py:113 IND CLOCK 3366
2026-01-29 02:47:04.001 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:47:04.003 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:47:04.004 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 02:47:04.004 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 02:47:04.004 [INFO] transceiver.py:205 (MS@172.18.28.22:6700) Frequency hopping disabled
2026-01-29 02:47:04.005 [DEBUG] clck_gen.py:113 IND CLOCK 3468
2026-01-29 02:47:04.021 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 02:47:04.021 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 02:47:04.021 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 02:47:04.024 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:47:04.024 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 02:47:04.024 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 02:47:04.024 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.28.22:6700) Recv POWERON CMD
2026-01-29 02:47:04.024 [INFO] ctrl_if_trx.py:109 (MS@172.18.28.22:6700) Starting transceiver...
2026-01-29 02:47:04.070 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:47:04.076 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.28.22:6700) Recv SETFH cmd
2026-01-29 02:47:04.076 [INFO] transceiver.py:201 (MS@172.18.28.22:6700) Frequency hopping configured: hsn=5, maio=0, ma_len=4
2026-01-29 02:47:04.077 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:47:04.077 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:47:04.483 [DEBUG] clck_gen.py:113 IND CLOCK 3570
2026-01-29 02:47:04.962 [DEBUG] clck_gen.py:113 IND CLOCK 3672
2026-01-29 02:47:05.435 [DEBUG] clck_gen.py:113 IND CLOCK 3774
2026-01-29 02:47:05.525 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:47:05.527 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:47:05.528 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 02:47:05.528 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 02:47:05.528 [INFO] transceiver.py:205 (MS@172.18.28.22:6700) Frequency hopping disabled
2026-01-29 02:47:05.548 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 02:47:05.548 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 02:47:05.548 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 02:47:05.550 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:47:05.550 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 02:47:05.550 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 02:47:05.550 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.28.22:6700) Recv POWERON CMD
2026-01-29 02:47:05.550 [INFO] ctrl_if_trx.py:109 (MS@172.18.28.22:6700) Starting transceiver...
2026-01-29 02:47:05.590 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:47:05.596 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.28.22:6700) Recv SETFH cmd
2026-01-29 02:47:05.596 [INFO] transceiver.py:201 (MS@172.18.28.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2026-01-29 02:47:05.596 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:47:05.596 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:47:05.905 [DEBUG] clck_gen.py:113 IND CLOCK 3876
2026-01-29 02:47:06.376 [DEBUG] clck_gen.py:113 IND CLOCK 3978
2026-01-29 02:47:06.854 [DEBUG] clck_gen.py:113 IND CLOCK 4080
2026-01-29 02:47:07.010 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:47:07.013 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:47:07.014 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 02:47:07.014 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 02:47:07.014 [INFO] transceiver.py:205 (MS@172.18.28.22:6700) Frequency hopping disabled
2026-01-29 02:47:07.032 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 02:47:07.032 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 02:47:07.032 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 02:47:07.034 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:47:07.035 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 02:47:07.035 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 02:47:07.035 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.28.22:6700) Recv POWERON CMD
2026-01-29 02:47:07.035 [INFO] ctrl_if_trx.py:109 (MS@172.18.28.22:6700) Starting transceiver...
2026-01-29 02:47:07.090 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:47:07.091 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.28.22:6700) Recv SETFH cmd
2026-01-29 02:47:07.091 [INFO] transceiver.py:201 (MS@172.18.28.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2026-01-29 02:47:07.091 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:47:07.091 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:47:07.332 [DEBUG] clck_gen.py:113 IND CLOCK 4182
2026-01-29 02:47:07.810 [DEBUG] clck_gen.py:113 IND CLOCK 4284
2026-01-29 02:47:08.289 [DEBUG] clck_gen.py:113 IND CLOCK 4386
2026-01-29 02:47:08.463 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:47:08.466 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:47:08.467 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 02:47:08.467 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 02:47:08.467 [INFO] transceiver.py:205 (MS@172.18.28.22:6700) Frequency hopping disabled
2026-01-29 02:47:08.486 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 02:47:08.486 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 02:47:08.487 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 02:47:08.489 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:47:08.489 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 02:47:08.489 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 02:47:08.489 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.28.22:6700) Recv POWERON CMD
2026-01-29 02:47:08.489 [INFO] ctrl_if_trx.py:109 (MS@172.18.28.22:6700) Starting transceiver...
2026-01-29 02:47:08.530 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:47:08.535 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.28.22:6700) Recv SETFH cmd
2026-01-29 02:47:08.535 [INFO] transceiver.py:201 (MS@172.18.28.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2026-01-29 02:47:08.535 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:47:08.536 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:47:08.760 [DEBUG] clck_gen.py:113 IND CLOCK 4488
2026-01-29 02:47:09.239 [DEBUG] clck_gen.py:113 IND CLOCK 4590
2026-01-29 02:47:09.717 [DEBUG] clck_gen.py:113 IND CLOCK 4692
2026-01-29 02:47:09.910 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:47:09.913 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:47:09.913 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 02:47:09.913 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 02:47:09.913 [INFO] transceiver.py:205 (MS@172.18.28.22:6700) Frequency hopping disabled
2026-01-29 02:47:09.931 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 02:47:09.931 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 02:47:09.932 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 02:47:09.934 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:47:09.934 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 02:47:09.934 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 02:47:09.934 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.28.22:6700) Recv POWERON CMD
2026-01-29 02:47:09.934 [INFO] ctrl_if_trx.py:109 (MS@172.18.28.22:6700) Starting transceiver...
2026-01-29 02:47:09.978 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:47:09.984 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.28.22:6700) Recv SETFH cmd
2026-01-29 02:47:09.984 [INFO] transceiver.py:201 (MS@172.18.28.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2026-01-29 02:47:09.985 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:47:09.985 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:47:10.195 [DEBUG] clck_gen.py:113 IND CLOCK 4794
2026-01-29 02:47:10.674 [DEBUG] clck_gen.py:113 IND CLOCK 4896
2026-01-29 02:47:11.161 [DEBUG] clck_gen.py:113 IND CLOCK 4998
2026-01-29 02:47:11.372 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:47:11.375 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:47:11.375 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 02:47:11.375 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 02:47:11.376 [INFO] transceiver.py:205 (MS@172.18.28.22:6700) Frequency hopping disabled
2026-01-29 02:47:11.384 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 02:47:11.384 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 02:47:11.384 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 02:47:11.387 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:47:11.387 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 02:47:11.387 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 02:47:11.387 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.28.22:6700) Recv POWERON CMD
2026-01-29 02:47:11.387 [INFO] ctrl_if_trx.py:109 (MS@172.18.28.22:6700) Starting transceiver...
2026-01-29 02:47:11.430 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:47:11.435 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.28.22:6700) Recv SETFH cmd
2026-01-29 02:47:11.436 [INFO] transceiver.py:201 (MS@172.18.28.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2026-01-29 02:47:11.436 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:47:11.436 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:47:11.630 [DEBUG] clck_gen.py:113 IND CLOCK 5100
2026-01-29 02:47:12.107 [DEBUG] clck_gen.py:113 IND CLOCK 5202
2026-01-29 02:47:12.498 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:47:12.501 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:47:12.502 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 02:47:12.502 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 02:47:12.502 [INFO] transceiver.py:205 (MS@172.18.28.22:6700) Frequency hopping disabled
2026-01-29 02:47:12.520 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 02:47:12.521 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 02:47:12.521 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 02:47:12.523 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:47:12.523 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 02:47:12.523 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 02:47:12.523 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.28.22:6700) Recv POWERON CMD
2026-01-29 02:47:12.523 [INFO] ctrl_if_trx.py:109 (MS@172.18.28.22:6700) Starting transceiver...
2026-01-29 02:47:12.580 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:47:12.584 [DEBUG] clck_gen.py:113 IND CLOCK 5304
2026-01-29 02:47:12.585 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.28.22:6700) Recv SETFH cmd
2026-01-29 02:47:12.585 [INFO] transceiver.py:201 (MS@172.18.28.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2026-01-29 02:47:12.586 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:47:12.586 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:47:13.062 [DEBUG] clck_gen.py:113 IND CLOCK 5406
2026-01-29 02:47:13.541 [DEBUG] clck_gen.py:113 IND CLOCK 5508
2026-01-29 02:47:13.951 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:47:13.954 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:47:13.954 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 02:47:13.954 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 02:47:13.954 [INFO] transceiver.py:205 (MS@172.18.28.22:6700) Frequency hopping disabled
2026-01-29 02:47:13.973 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 02:47:13.973 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 02:47:13.973 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 02:47:13.976 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:47:13.976 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 02:47:13.976 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 02:47:13.976 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.28.22:6700) Recv POWERON CMD
2026-01-29 02:47:13.976 [INFO] ctrl_if_trx.py:109 (MS@172.18.28.22:6700) Starting transceiver...
2026-01-29 02:47:14.019 [DEBUG] clck_gen.py:113 IND CLOCK 5610
2026-01-29 02:47:14.022 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:47:14.027 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.28.22:6700) Recv SETFH cmd
2026-01-29 02:47:14.027 [INFO] transceiver.py:201 (MS@172.18.28.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2026-01-29 02:47:14.028 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:47:14.028 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:47:14.497 [DEBUG] clck_gen.py:113 IND CLOCK 5712
2026-01-29 02:47:14.975 [DEBUG] clck_gen.py:113 IND CLOCK 5814
2026-01-29 02:47:15.404 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:47:15.407 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:47:15.408 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 02:47:15.408 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 02:47:15.408 [INFO] transceiver.py:205 (MS@172.18.28.22:6700) Frequency hopping disabled
2026-01-29 02:47:15.426 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 02:47:15.426 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 02:47:15.426 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 02:47:15.429 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:47:15.429 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 02:47:15.429 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 02:47:15.429 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.28.22:6700) Recv POWERON CMD
2026-01-29 02:47:15.429 [INFO] ctrl_if_trx.py:109 (MS@172.18.28.22:6700) Starting transceiver...
2026-01-29 02:47:15.453 [DEBUG] clck_gen.py:113 IND CLOCK 5916
2026-01-29 02:47:15.470 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:47:15.476 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.28.22:6700) Recv SETFH cmd
2026-01-29 02:47:15.476 [INFO] transceiver.py:201 (MS@172.18.28.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2026-01-29 02:47:15.477 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:47:15.477 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:47:15.932 [DEBUG] clck_gen.py:113 IND CLOCK 6018
2026-01-29 02:47:16.411 [DEBUG] clck_gen.py:113 IND CLOCK 6120
2026-01-29 02:47:16.857 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:47:16.861 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:47:16.861 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 02:47:16.862 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 02:47:16.862 [INFO] transceiver.py:205 (MS@172.18.28.22:6700) Frequency hopping disabled
2026-01-29 02:47:16.869 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 02:47:16.869 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:47:16.869 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:47:16.869 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:47:16.870 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 02:47:16.870 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:47:16.870 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:47:16.870 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:47:16.870 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.28.20:5700) Recv POWEROFF cmd
2026-01-29 02:47:16.870 [INFO] ctrl_if_trx.py:117 (BTS@172.18.28.20:5700) Stopping transceiver...
2026-01-29 02:47:16.870 [INFO] transceiver.py:246 Stopping clock generator
2026-01-29 02:47:16.870 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=6221 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:47:21.873 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.28.20:5700) Recv POWEROFF cmd
2026-01-29 02:47:21.873 [INFO] ctrl_if_trx.py:117 (BTS@172.18.28.20:5700) Stopping transceiver...
2026-01-29 02:47:21.874 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:47:21.876 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:47:21.877 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:47:21.880 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 02:47:21.893 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 02:47:21.894 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.28.20:5700) Recv SETFORMAT cmd
2026-01-29 02:47:21.894 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.28.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:47:21.894 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.28.20:5700) Recv SETFORMAT cmd
2026-01-29 02:47:21.895 [INFO] ctrl_if_trx.py:201 (BTS@172.18.28.20:5700) TRXD header version 1 -> 1
2026-01-29 02:47:21.896 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.28.20:5700/1) Recv RXTUNE cmd
2026-01-29 02:47:21.896 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.28.20:5700/1) Recv TXTUNE cmd
2026-01-29 02:47:21.897 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.28.20:5700/1) Recv SETFORMAT cmd
2026-01-29 02:47:21.897 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.28.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:47:21.897 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:47:21.897 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.28.20:5700/1) Recv NOMTXPOWER cmd
2026-01-29 02:47:21.898 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.28.20:5700/1) Recv SETFORMAT cmd
2026-01-29 02:47:21.898 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.28.20:5700/1) TRXD header version 1 -> 1
2026-01-29 02:47:21.898 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.28.20:5700/2) Recv RXTUNE cmd
2026-01-29 02:47:21.898 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.28.20:5700/2) Recv TXTUNE cmd
2026-01-29 02:47:21.899 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.28.20:5700/2) Recv SETFORMAT cmd
2026-01-29 02:47:21.899 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.28.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:47:21.899 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:47:21.899 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.28.20:5700/2) Recv NOMTXPOWER cmd
2026-01-29 02:47:21.899 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.28.20:5700/2) Recv SETFORMAT cmd
2026-01-29 02:47:21.899 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.28.20:5700/2) TRXD header version 1 -> 1
2026-01-29 02:47:21.900 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.28.20:5700/3) Recv RXTUNE cmd
2026-01-29 02:47:21.900 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.28.20:5700/3) Recv TXTUNE cmd
2026-01-29 02:47:21.900 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.28.20:5700/3) Recv SETFORMAT cmd
2026-01-29 02:47:21.900 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.28.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:47:21.900 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:47:21.900 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.28.20:5700/3) Recv NOMTXPOWER cmd
2026-01-29 02:47:21.900 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.28.20:5700/3) Recv SETFORMAT cmd
2026-01-29 02:47:21.900 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.28.20:5700/3) TRXD header version 1 -> 1
2026-01-29 02:47:21.902 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.28.20:5700) Recv RXTUNE cmd
2026-01-29 02:47:21.902 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETTSC
2026-01-29 02:47:21.903 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETTSC
2026-01-29 02:47:21.903 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETTSC
2026-01-29 02:47:21.903 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.28.20:5700) Recv TXTUNE cmd
2026-01-29 02:47:21.903 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETRXGAIN
2026-01-29 02:47:21.903 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETRXGAIN
2026-01-29 02:47:21.903 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETRXGAIN
2026-01-29 02:47:21.903 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETTSC
2026-01-29 02:47:21.903 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:47:21.903 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:47:21.903 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.28.20:5700) Recv NOMTXPOWER cmd
2026-01-29 02:47:21.903 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:47:21.903 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:47:21.903 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:47:21.903 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.28.20:5700) Recv POWERON CMD
2026-01-29 02:47:21.903 [INFO] ctrl_if_trx.py:109 (BTS@172.18.28.20:5700) Starting transceiver...
2026-01-29 02:47:21.903 [INFO] transceiver.py:243 Starting clock generator
2026-01-29 02:47:21.903 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-01-29 02:47:21.903 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:47:21.903 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:47:21.903 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:47:21.903 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETRXGAIN
2026-01-29 02:47:21.903 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:47:21.903 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:47:21.904 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:47:21.904 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:47:21.904 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:47:21.904 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:47:21.904 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:47:21.904 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:47:21.904 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:47:21.904 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:47:21.904 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:47:21.904 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:47:21.904 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:47:21.904 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:47:21.904 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:47:21.904 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:47:21.904 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:47:21.904 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:47:21.904 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:47:21.904 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:47:21.904 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:47:21.904 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:47:21.904 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:47:21.904 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:47:21.908 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-01-29 02:47:22.390 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-01-29 02:47:22.430 [DEBUG] fake_trx.py:278 (BTS@172.18.28.20:5700) Recv FAKE_TOA cmd
2026-01-29 02:47:22.432 [DEBUG] fake_trx.py:297 (BTS@172.18.28.20:5700) Recv FAKE_RSSI cmd
2026-01-29 02:47:22.435 [DEBUG] fake_trx.py:322 (BTS@172.18.28.20:5700) Recv FAKE_CI cmd
2026-01-29 02:47:22.435 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:47:22.460 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 02:47:22.460 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 02:47:22.461 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 02:47:22.465 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:47:22.465 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 02:47:22.466 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 02:47:22.466 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.28.22:6700) Recv POWERON CMD
2026-01-29 02:47:22.466 [INFO] ctrl_if_trx.py:109 (MS@172.18.28.22:6700) Starting transceiver...
2026-01-29 02:47:22.485 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD HANDOVER
2026-01-29 02:47:22.490 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 02:47:22.490 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 02:47:22.490 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:47:22.490 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:47:22.867 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-01-29 02:47:22.906 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 02:47:22.906 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:47:22.908 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:47:22.910 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:47:23.345 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-01-29 02:47:23.823 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-01-29 02:47:23.906 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 02:47:23.907 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:47:23.909 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:47:23.911 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:47:24.301 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-01-29 02:47:24.780 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-01-29 02:47:24.907 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 02:47:24.907 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:47:24.910 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:47:24.912 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:47:25.258 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-01-29 02:47:25.494 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:47:25.736 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-01-29 02:47:25.908 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 02:47:25.908 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:47:25.911 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:47:25.913 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:47:26.214 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-01-29 02:47:26.287 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:47:26.290 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:47:26.291 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 02:47:26.291 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 02:47:26.291 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 02:47:26.291 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:47:26.291 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 02:47:26.291 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 02:47:26.292 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.28.22:6700) Recv POWERON CMD
2026-01-29 02:47:26.292 [INFO] ctrl_if_trx.py:109 (MS@172.18.28.22:6700) Starting transceiver...
2026-01-29 02:47:26.306 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD HANDOVER
2026-01-29 02:47:26.309 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 02:47:26.310 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 02:47:26.310 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:47:26.310 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:47:26.692 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-01-29 02:47:26.909 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 02:47:26.909 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:47:26.912 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:47:26.914 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:47:27.170 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-01-29 02:47:27.648 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-01-29 02:47:28.126 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-01-29 02:47:28.604 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-01-29 02:47:29.082 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-01-29 02:47:29.315 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:47:29.560 [DEBUG] clck_gen.py:113 IND CLOCK 1632
2026-01-29 02:47:30.039 [DEBUG] clck_gen.py:113 IND CLOCK 1734
2026-01-29 02:47:30.186 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:47:30.189 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:47:30.190 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 02:47:30.190 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 02:47:30.208 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 02:47:30.208 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 02:47:30.208 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 02:47:30.210 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:47:30.210 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 02:47:30.210 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 02:47:30.210 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.28.22:6700) Recv POWERON CMD
2026-01-29 02:47:30.210 [INFO] ctrl_if_trx.py:109 (MS@172.18.28.22:6700) Starting transceiver...
2026-01-29 02:47:30.254 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD HANDOVER
2026-01-29 02:47:30.260 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.28.22:6700) Recv SETFH cmd
2026-01-29 02:47:30.260 [INFO] transceiver.py:201 (MS@172.18.28.22:6700) Frequency hopping configured: hsn=5, maio=0, ma_len=4
2026-01-29 02:47:30.260 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:47:30.260 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:47:30.517 [DEBUG] clck_gen.py:113 IND CLOCK 1836
2026-01-29 02:47:30.996 [DEBUG] clck_gen.py:113 IND CLOCK 1938
2026-01-29 02:47:31.475 [DEBUG] clck_gen.py:113 IND CLOCK 2040
2026-01-29 02:47:31.953 [DEBUG] clck_gen.py:113 IND CLOCK 2142
2026-01-29 02:47:32.431 [DEBUG] clck_gen.py:113 IND CLOCK 2244
2026-01-29 02:47:32.909 [DEBUG] clck_gen.py:113 IND CLOCK 2346
2026-01-29 02:47:33.266 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:47:33.383 [DEBUG] clck_gen.py:113 IND CLOCK 2448
2026-01-29 02:47:33.831 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:47:33.834 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:47:33.834 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 02:47:33.834 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 02:47:33.834 [INFO] transceiver.py:205 (MS@172.18.28.22:6700) Frequency hopping disabled
2026-01-29 02:47:33.835 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 02:47:33.835 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:47:33.835 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 02:47:33.835 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 02:47:33.835 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.28.22:6700) Recv POWERON CMD
2026-01-29 02:47:33.835 [INFO] ctrl_if_trx.py:109 (MS@172.18.28.22:6700) Starting transceiver...
2026-01-29 02:47:33.850 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD HANDOVER
2026-01-29 02:47:33.852 [DEBUG] clck_gen.py:113 IND CLOCK 2550
2026-01-29 02:47:33.854 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.28.22:6700) Recv SETFH cmd
2026-01-29 02:47:33.854 [INFO] transceiver.py:201 (MS@172.18.28.22:6700) Frequency hopping configured: hsn=5, maio=0, ma_len=4
2026-01-29 02:47:33.854 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:47:33.855 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:47:34.329 [DEBUG] clck_gen.py:113 IND CLOCK 2652
2026-01-29 02:47:34.808 [DEBUG] clck_gen.py:113 IND CLOCK 2754
2026-01-29 02:47:35.287 [DEBUG] clck_gen.py:113 IND CLOCK 2856
2026-01-29 02:47:35.766 [DEBUG] clck_gen.py:113 IND CLOCK 2958
2026-01-29 02:47:36.245 [DEBUG] clck_gen.py:113 IND CLOCK 3060
2026-01-29 02:47:36.724 [DEBUG] clck_gen.py:113 IND CLOCK 3162
2026-01-29 02:47:36.865 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:47:37.202 [DEBUG] clck_gen.py:113 IND CLOCK 3264
2026-01-29 02:47:37.681 [DEBUG] clck_gen.py:113 IND CLOCK 3366
2026-01-29 02:47:37.736 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:47:37.739 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:47:37.740 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 02:47:37.740 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 02:47:37.740 [INFO] transceiver.py:205 (MS@172.18.28.22:6700) Frequency hopping disabled
2026-01-29 02:47:37.759 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 02:47:37.759 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 02:47:37.759 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 02:47:37.761 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:47:37.761 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 02:47:37.761 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 02:47:37.761 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.28.22:6700) Recv POWERON CMD
2026-01-29 02:47:37.761 [INFO] ctrl_if_trx.py:109 (MS@172.18.28.22:6700) Starting transceiver...
2026-01-29 02:47:37.802 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD HANDOVER
2026-01-29 02:47:37.807 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 02:47:37.807 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 02:47:37.808 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:47:37.808 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:47:38.159 [DEBUG] clck_gen.py:113 IND CLOCK 3468
2026-01-29 02:47:38.636 [DEBUG] clck_gen.py:113 IND CLOCK 3570
2026-01-29 02:47:39.114 [DEBUG] clck_gen.py:113 IND CLOCK 3672
2026-01-29 02:47:39.592 [DEBUG] clck_gen.py:113 IND CLOCK 3774
2026-01-29 02:47:40.070 [DEBUG] clck_gen.py:113 IND CLOCK 3876
2026-01-29 02:47:40.549 [DEBUG] clck_gen.py:113 IND CLOCK 3978
2026-01-29 02:47:40.993 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:47:41.027 [DEBUG] clck_gen.py:113 IND CLOCK 4080
2026-01-29 02:47:41.464 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:47:41.467 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:47:41.468 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 02:47:41.468 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 02:47:41.468 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 02:47:41.469 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:47:41.469 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 02:47:41.470 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 02:47:41.470 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.28.22:6700) Recv POWERON CMD
2026-01-29 02:47:41.470 [INFO] ctrl_if_trx.py:109 (MS@172.18.28.22:6700) Starting transceiver...
2026-01-29 02:47:41.496 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD HANDOVER
2026-01-29 02:47:41.499 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 02:47:41.500 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 02:47:41.500 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:47:41.500 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:47:41.505 [DEBUG] clck_gen.py:113 IND CLOCK 4182
2026-01-29 02:47:41.983 [DEBUG] clck_gen.py:113 IND CLOCK 4284
2026-01-29 02:47:42.461 [DEBUG] clck_gen.py:113 IND CLOCK 4386
2026-01-29 02:47:42.939 [DEBUG] clck_gen.py:113 IND CLOCK 4488
2026-01-29 02:47:43.417 [DEBUG] clck_gen.py:113 IND CLOCK 4590
2026-01-29 02:47:43.895 [DEBUG] clck_gen.py:113 IND CLOCK 4692
2026-01-29 02:47:44.373 [DEBUG] clck_gen.py:113 IND CLOCK 4794
2026-01-29 02:47:44.582 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:47:44.811 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:47:44.814 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:47:44.814 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 02:47:44.814 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 02:47:44.832 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 02:47:44.833 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 02:47:44.833 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 02:47:44.835 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:47:44.835 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 02:47:44.835 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 02:47:44.835 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.28.22:6700) Recv POWERON CMD
2026-01-29 02:47:44.835 [INFO] ctrl_if_trx.py:109 (MS@172.18.28.22:6700) Starting transceiver...
2026-01-29 02:47:44.851 [DEBUG] clck_gen.py:113 IND CLOCK 4896
2026-01-29 02:47:44.882 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD HANDOVER
2026-01-29 02:47:44.887 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.28.22:6700) Recv SETFH cmd
2026-01-29 02:47:44.887 [INFO] transceiver.py:201 (MS@172.18.28.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2026-01-29 02:47:44.887 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:47:44.887 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:47:45.330 [DEBUG] clck_gen.py:113 IND CLOCK 4998
2026-01-29 02:47:45.809 [DEBUG] clck_gen.py:113 IND CLOCK 5100
2026-01-29 02:47:46.287 [DEBUG] clck_gen.py:113 IND CLOCK 5202
2026-01-29 02:47:46.766 [DEBUG] clck_gen.py:113 IND CLOCK 5304
2026-01-29 02:47:47.245 [DEBUG] clck_gen.py:113 IND CLOCK 5406
2026-01-29 02:47:47.723 [DEBUG] clck_gen.py:113 IND CLOCK 5508
2026-01-29 02:47:48.094 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:47:48.202 [DEBUG] clck_gen.py:113 IND CLOCK 5610
2026-01-29 02:47:48.594 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:47:48.597 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:47:48.597 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 02:47:48.597 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 02:47:48.598 [INFO] transceiver.py:205 (MS@172.18.28.22:6700) Frequency hopping disabled
2026-01-29 02:47:48.598 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 02:47:48.598 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:47:48.598 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 02:47:48.598 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 02:47:48.598 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.28.22:6700) Recv POWERON CMD
2026-01-29 02:47:48.598 [INFO] ctrl_if_trx.py:109 (MS@172.18.28.22:6700) Starting transceiver...
2026-01-29 02:47:48.622 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD HANDOVER
2026-01-29 02:47:48.625 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.28.22:6700) Recv SETFH cmd
2026-01-29 02:47:48.626 [INFO] transceiver.py:201 (MS@172.18.28.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2026-01-29 02:47:48.626 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:47:48.626 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:47:48.680 [DEBUG] clck_gen.py:113 IND CLOCK 5712
2026-01-29 02:47:49.158 [DEBUG] clck_gen.py:113 IND CLOCK 5814
2026-01-29 02:47:49.637 [DEBUG] clck_gen.py:113 IND CLOCK 5916
2026-01-29 02:47:50.116 [DEBUG] clck_gen.py:113 IND CLOCK 6018
2026-01-29 02:47:50.594 [DEBUG] clck_gen.py:113 IND CLOCK 6120
2026-01-29 02:47:51.073 [DEBUG] clck_gen.py:113 IND CLOCK 6222
2026-01-29 02:47:51.551 [DEBUG] clck_gen.py:113 IND CLOCK 6324
2026-01-29 02:47:51.696 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:47:51.942 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:47:51.945 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:47:51.946 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 02:47:51.946 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 02:47:51.946 [INFO] transceiver.py:205 (MS@172.18.28.22:6700) Frequency hopping disabled
2026-01-29 02:47:51.956 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 02:47:51.956 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:47:51.956 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:47:51.956 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:47:51.960 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 02:47:51.960 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:47:51.960 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:47:51.960 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:47:51.961 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.28.20:5700) Recv POWEROFF cmd
2026-01-29 02:47:51.961 [INFO] ctrl_if_trx.py:117 (BTS@172.18.28.20:5700) Stopping transceiver...
2026-01-29 02:47:51.961 [INFO] transceiver.py:246 Stopping clock generator
2026-01-29 02:47:51.961 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=6413 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:47:51.961 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=6413 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:47:51.961 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=6413 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:47:51.961 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=6413 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:47:51.962 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=6413 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:47:51.962 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=6413 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:47:51.962 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=6414 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:47:51.962 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=6414 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:47:51.962 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=6414 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:47:51.962 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=6414 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:47:51.962 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=6414 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:47:51.962 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=6414 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:47:51.962 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=6414 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:47:51.962 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=6414 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:47:56.962 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.28.20:5700) Recv POWEROFF cmd
2026-01-29 02:47:56.962 [INFO] ctrl_if_trx.py:117 (BTS@172.18.28.20:5700) Stopping transceiver...
2026-01-29 02:47:56.962 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:47:56.962 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:47:56.962 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:47:56.962 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 02:47:56.971 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 02:47:56.973 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.28.20:5700) Recv SETFORMAT cmd
2026-01-29 02:47:56.973 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.28.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:47:56.974 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.28.20:5700) Recv SETFORMAT cmd
2026-01-29 02:47:56.974 [INFO] ctrl_if_trx.py:201 (BTS@172.18.28.20:5700) TRXD header version 1 -> 1
2026-01-29 02:47:56.979 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.28.20:5700/1) Recv RXTUNE cmd
2026-01-29 02:47:56.980 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.28.20:5700/1) Recv TXTUNE cmd
2026-01-29 02:47:56.980 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.28.20:5700/1) Recv SETFORMAT cmd
2026-01-29 02:47:56.981 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.28.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:47:56.981 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:47:56.982 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.28.20:5700/1) Recv NOMTXPOWER cmd
2026-01-29 02:47:56.982 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.28.20:5700/1) Recv SETFORMAT cmd
2026-01-29 02:47:56.982 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.28.20:5700/1) TRXD header version 1 -> 1
2026-01-29 02:47:56.984 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.28.20:5700/2) Recv RXTUNE cmd
2026-01-29 02:47:56.984 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.28.20:5700/2) Recv TXTUNE cmd
2026-01-29 02:47:56.984 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.28.20:5700/2) Recv SETFORMAT cmd
2026-01-29 02:47:56.984 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.28.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:47:56.985 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:47:56.985 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.28.20:5700/2) Recv NOMTXPOWER cmd
2026-01-29 02:47:56.985 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.28.20:5700/2) Recv SETFORMAT cmd
2026-01-29 02:47:56.985 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.28.20:5700/2) TRXD header version 1 -> 1
2026-01-29 02:47:56.987 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.28.20:5700/3) Recv RXTUNE cmd
2026-01-29 02:47:56.987 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.28.20:5700/3) Recv TXTUNE cmd
2026-01-29 02:47:56.987 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.28.20:5700/3) Recv SETFORMAT cmd
2026-01-29 02:47:56.987 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.28.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:47:56.987 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:47:56.987 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.28.20:5700/3) Recv NOMTXPOWER cmd
2026-01-29 02:47:56.988 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.28.20:5700/3) Recv SETFORMAT cmd
2026-01-29 02:47:56.988 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.28.20:5700/3) TRXD header version 1 -> 1
2026-01-29 02:47:56.991 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.28.20:5700) Recv RXTUNE cmd
2026-01-29 02:47:56.991 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETTSC
2026-01-29 02:47:56.991 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETTSC
2026-01-29 02:47:56.991 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETTSC
2026-01-29 02:47:56.991 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.28.20:5700) Recv TXTUNE cmd
2026-01-29 02:47:56.991 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETRXGAIN
2026-01-29 02:47:56.991 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETRXGAIN
2026-01-29 02:47:56.991 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETRXGAIN
2026-01-29 02:47:56.991 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETTSC
2026-01-29 02:47:56.991 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:47:56.991 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:47:56.991 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.28.20:5700) Recv NOMTXPOWER cmd
2026-01-29 02:47:56.991 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:47:56.991 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:47:56.991 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:47:56.991 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.28.20:5700) Recv POWERON CMD
2026-01-29 02:47:56.991 [INFO] ctrl_if_trx.py:109 (BTS@172.18.28.20:5700) Starting transceiver...
2026-01-29 02:47:56.991 [INFO] transceiver.py:243 Starting clock generator
2026-01-29 02:47:56.992 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-01-29 02:47:56.992 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:47:56.992 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:47:56.992 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:47:56.992 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETRXGAIN
2026-01-29 02:47:56.992 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:47:56.992 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:47:56.992 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:47:56.992 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:47:56.992 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:47:56.992 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:47:56.992 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:47:56.992 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:47:56.992 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:47:56.993 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:47:56.993 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:47:56.993 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:47:56.993 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:47:56.993 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:47:56.993 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:47:56.993 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:47:56.993 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:47:56.993 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:47:56.993 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:47:56.993 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:47:56.993 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:47:56.993 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:47:56.993 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:47:56.993 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:47:56.996 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-01-29 02:47:57.479 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-01-29 02:47:57.528 [DEBUG] fake_trx.py:278 (BTS@172.18.28.20:5700) Recv FAKE_TOA cmd
2026-01-29 02:47:57.530 [DEBUG] fake_trx.py:297 (BTS@172.18.28.20:5700) Recv FAKE_RSSI cmd
2026-01-29 02:47:57.532 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:47:57.532 [DEBUG] fake_trx.py:322 (BTS@172.18.28.20:5700) Recv FAKE_CI cmd
2026-01-29 02:47:57.558 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 02:47:57.558 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 02:47:57.559 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 02:47:57.563 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:47:57.563 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 02:47:57.563 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 02:47:57.564 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.28.22:6700) Recv POWERON CMD
2026-01-29 02:47:57.564 [INFO] ctrl_if_trx.py:109 (MS@172.18.28.22:6700) Starting transceiver...
2026-01-29 02:47:57.571 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD HANDOVER
2026-01-29 02:47:57.574 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 02:47:57.574 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 02:47:57.574 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:47:57.574 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:47:57.956 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-01-29 02:47:57.996 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:47:57.997 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 02:47:57.998 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:47:58.001 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:47:58.434 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-01-29 02:47:58.912 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-01-29 02:47:58.997 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:47:58.997 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 02:47:59.000 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:47:59.001 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:47:59.391 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-01-29 02:47:59.870 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-01-29 02:47:59.998 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 02:47:59.998 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:48:00.000 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:48:00.002 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:48:00.348 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-01-29 02:48:00.575 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:48:00.825 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-01-29 02:48:00.999 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 02:48:00.999 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:48:01.001 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:48:01.004 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:48:01.304 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-01-29 02:48:01.397 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:48:01.399 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:48:01.400 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 02:48:01.400 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 02:48:01.400 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 02:48:01.400 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:48:01.401 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 02:48:01.401 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 02:48:01.401 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.28.22:6700) Recv POWERON CMD
2026-01-29 02:48:01.401 [INFO] ctrl_if_trx.py:109 (MS@172.18.28.22:6700) Starting transceiver...
2026-01-29 02:48:01.442 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD HANDOVER
2026-01-29 02:48:01.445 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 02:48:01.445 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 02:48:01.445 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:48:01.446 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:48:01.782 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-01-29 02:48:02.000 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 02:48:02.000 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:48:02.002 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:48:02.005 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:48:02.260 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-01-29 02:48:02.736 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-01-29 02:48:03.214 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-01-29 02:48:03.692 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-01-29 02:48:04.171 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-01-29 02:48:04.449 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:48:04.649 [DEBUG] clck_gen.py:113 IND CLOCK 1632
2026-01-29 02:48:05.128 [DEBUG] clck_gen.py:113 IND CLOCK 1734
2026-01-29 02:48:05.274 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:48:05.276 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:48:05.277 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 02:48:05.277 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 02:48:05.277 [WARNING] transceiver.py:257 (MS@172.18.28.22:6700) RX TRXD message (fn=1768 tn=5 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:48:05.277 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 02:48:05.277 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:48:05.278 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 02:48:05.278 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 02:48:05.278 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.28.22:6700) Recv POWERON CMD
2026-01-29 02:48:05.278 [INFO] ctrl_if_trx.py:109 (MS@172.18.28.22:6700) Starting transceiver...
2026-01-29 02:48:05.311 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD HANDOVER
2026-01-29 02:48:05.314 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 02:48:05.314 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 02:48:05.314 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:48:05.315 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:48:05.605 [DEBUG] clck_gen.py:113 IND CLOCK 1836
2026-01-29 02:48:06.084 [DEBUG] clck_gen.py:113 IND CLOCK 1938
2026-01-29 02:48:06.562 [DEBUG] clck_gen.py:113 IND CLOCK 2040
2026-01-29 02:48:07.040 [DEBUG] clck_gen.py:113 IND CLOCK 2142
2026-01-29 02:48:07.518 [DEBUG] clck_gen.py:113 IND CLOCK 2244
2026-01-29 02:48:07.996 [DEBUG] clck_gen.py:113 IND CLOCK 2346
2026-01-29 02:48:08.320 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:48:08.474 [DEBUG] clck_gen.py:113 IND CLOCK 2448
2026-01-29 02:48:08.952 [DEBUG] clck_gen.py:113 IND CLOCK 2550
2026-01-29 02:48:09.172 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:48:09.174 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:48:09.174 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 02:48:09.174 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 02:48:09.175 [WARNING] transceiver.py:257 (MS@172.18.28.22:6700) RX TRXD message (fn=2600 tn=1 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:48:09.175 [WARNING] transceiver.py:257 (MS@172.18.28.22:6700) RX TRXD message (fn=2600 tn=2 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:48:09.175 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 02:48:09.175 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:48:09.175 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 02:48:09.175 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 02:48:09.176 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.28.22:6700) Recv POWERON CMD
2026-01-29 02:48:09.176 [INFO] ctrl_if_trx.py:109 (MS@172.18.28.22:6700) Starting transceiver...
2026-01-29 02:48:09.185 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD HANDOVER
2026-01-29 02:48:09.188 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 02:48:09.188 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 02:48:09.189 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:48:09.189 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:48:09.430 [DEBUG] clck_gen.py:113 IND CLOCK 2652
2026-01-29 02:48:09.662 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:48:09.908 [DEBUG] clck_gen.py:113 IND CLOCK 2754
2026-01-29 02:48:10.146 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:48:10.148 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:48:10.149 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 02:48:10.149 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 02:48:10.168 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 02:48:10.168 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 02:48:10.168 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 02:48:10.170 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:48:10.170 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 02:48:10.170 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 02:48:10.170 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.28.22:6700) Recv POWERON CMD
2026-01-29 02:48:10.170 [INFO] ctrl_if_trx.py:109 (MS@172.18.28.22:6700) Starting transceiver...
2026-01-29 02:48:10.214 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD HANDOVER
2026-01-29 02:48:10.219 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.28.22:6700) Recv SETFH cmd
2026-01-29 02:48:10.219 [INFO] transceiver.py:201 (MS@172.18.28.22:6700) Frequency hopping configured: hsn=5, maio=0, ma_len=4
2026-01-29 02:48:10.219 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:48:10.220 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:48:10.386 [DEBUG] clck_gen.py:113 IND CLOCK 2856
2026-01-29 02:48:10.865 [DEBUG] clck_gen.py:113 IND CLOCK 2958
2026-01-29 02:48:11.344 [DEBUG] clck_gen.py:113 IND CLOCK 3060
2026-01-29 02:48:11.822 [DEBUG] clck_gen.py:113 IND CLOCK 3162
2026-01-29 02:48:12.301 [DEBUG] clck_gen.py:113 IND CLOCK 3264
2026-01-29 02:48:12.779 [DEBUG] clck_gen.py:113 IND CLOCK 3366
2026-01-29 02:48:13.229 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:48:13.258 [DEBUG] clck_gen.py:113 IND CLOCK 3468
2026-01-29 02:48:13.738 [DEBUG] clck_gen.py:113 IND CLOCK 3570
2026-01-29 02:48:13.810 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:48:13.814 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:48:13.814 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 02:48:13.814 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 02:48:13.814 [INFO] transceiver.py:205 (MS@172.18.28.22:6700) Frequency hopping disabled
2026-01-29 02:48:13.814 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 02:48:13.815 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:48:13.815 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 02:48:13.815 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 02:48:13.815 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.28.22:6700) Recv POWERON CMD
2026-01-29 02:48:13.815 [INFO] ctrl_if_trx.py:109 (MS@172.18.28.22:6700) Starting transceiver...
2026-01-29 02:48:13.829 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD HANDOVER
2026-01-29 02:48:13.833 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.28.22:6700) Recv SETFH cmd
2026-01-29 02:48:13.833 [INFO] transceiver.py:201 (MS@172.18.28.22:6700) Frequency hopping configured: hsn=5, maio=0, ma_len=4
2026-01-29 02:48:13.833 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:48:13.833 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:48:14.210 [DEBUG] clck_gen.py:113 IND CLOCK 3672
2026-01-29 02:48:14.680 [DEBUG] clck_gen.py:113 IND CLOCK 3774
2026-01-29 02:48:15.151 [DEBUG] clck_gen.py:113 IND CLOCK 3876
2026-01-29 02:48:15.622 [DEBUG] clck_gen.py:113 IND CLOCK 3978
2026-01-29 02:48:16.093 [DEBUG] clck_gen.py:113 IND CLOCK 4080
2026-01-29 02:48:16.573 [DEBUG] clck_gen.py:113 IND CLOCK 4182
2026-01-29 02:48:16.837 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:48:17.051 [DEBUG] clck_gen.py:113 IND CLOCK 4284
2026-01-29 02:48:17.530 [DEBUG] clck_gen.py:113 IND CLOCK 4386
2026-01-29 02:48:17.677 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:48:17.680 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:48:17.681 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 02:48:17.681 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 02:48:17.681 [INFO] transceiver.py:205 (MS@172.18.28.22:6700) Frequency hopping disabled
2026-01-29 02:48:17.682 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 02:48:17.682 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:48:17.682 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 02:48:17.683 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 02:48:17.683 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.28.22:6700) Recv POWERON CMD
2026-01-29 02:48:17.683 [INFO] ctrl_if_trx.py:109 (MS@172.18.28.22:6700) Starting transceiver...
2026-01-29 02:48:17.714 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD HANDOVER
2026-01-29 02:48:17.717 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.28.22:6700) Recv SETFH cmd
2026-01-29 02:48:17.717 [INFO] transceiver.py:201 (MS@172.18.28.22:6700) Frequency hopping configured: hsn=5, maio=0, ma_len=4
2026-01-29 02:48:17.718 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:48:17.718 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:48:18.010 [DEBUG] clck_gen.py:113 IND CLOCK 4488
2026-01-29 02:48:18.489 [DEBUG] clck_gen.py:113 IND CLOCK 4590
2026-01-29 02:48:18.968 [DEBUG] clck_gen.py:113 IND CLOCK 4692
2026-01-29 02:48:19.446 [DEBUG] clck_gen.py:113 IND CLOCK 4794
2026-01-29 02:48:19.919 [DEBUG] clck_gen.py:113 IND CLOCK 4896
2026-01-29 02:48:20.389 [DEBUG] clck_gen.py:113 IND CLOCK 4998
2026-01-29 02:48:20.726 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:48:20.860 [DEBUG] clck_gen.py:113 IND CLOCK 5100
2026-01-29 02:48:21.331 [DEBUG] clck_gen.py:113 IND CLOCK 5202
2026-01-29 02:48:21.550 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:48:21.553 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:48:21.553 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 02:48:21.553 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 02:48:21.553 [INFO] transceiver.py:205 (MS@172.18.28.22:6700) Frequency hopping disabled
2026-01-29 02:48:21.554 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 02:48:21.554 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:48:21.554 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 02:48:21.555 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 02:48:21.555 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.28.22:6700) Recv POWERON CMD
2026-01-29 02:48:21.555 [INFO] ctrl_if_trx.py:109 (MS@172.18.28.22:6700) Starting transceiver...
2026-01-29 02:48:21.564 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD HANDOVER
2026-01-29 02:48:21.567 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.28.22:6700) Recv SETFH cmd
2026-01-29 02:48:21.568 [INFO] transceiver.py:201 (MS@172.18.28.22:6700) Frequency hopping configured: hsn=5, maio=0, ma_len=4
2026-01-29 02:48:21.568 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:48:21.568 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:48:21.808 [DEBUG] clck_gen.py:113 IND CLOCK 5304
2026-01-29 02:48:22.045 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:48:22.288 [DEBUG] clck_gen.py:113 IND CLOCK 5406
2026-01-29 02:48:22.527 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:48:22.530 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:48:22.530 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 02:48:22.530 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 02:48:22.530 [INFO] transceiver.py:205 (MS@172.18.28.22:6700) Frequency hopping disabled
2026-01-29 02:48:22.549 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 02:48:22.549 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 02:48:22.549 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 02:48:22.551 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:48:22.551 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 02:48:22.551 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 02:48:22.551 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.28.22:6700) Recv POWERON CMD
2026-01-29 02:48:22.551 [INFO] ctrl_if_trx.py:109 (MS@172.18.28.22:6700) Starting transceiver...
2026-01-29 02:48:22.598 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD HANDOVER
2026-01-29 02:48:22.603 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 02:48:22.603 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 02:48:22.603 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:48:22.603 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:48:22.764 [DEBUG] clck_gen.py:113 IND CLOCK 5508
2026-01-29 02:48:23.242 [DEBUG] clck_gen.py:113 IND CLOCK 5610
2026-01-29 02:48:23.720 [DEBUG] clck_gen.py:113 IND CLOCK 5712
2026-01-29 02:48:24.197 [DEBUG] clck_gen.py:113 IND CLOCK 5814
2026-01-29 02:48:24.675 [DEBUG] clck_gen.py:113 IND CLOCK 5916
2026-01-29 02:48:25.153 [DEBUG] clck_gen.py:113 IND CLOCK 6018
2026-01-29 02:48:25.607 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:48:25.632 [DEBUG] clck_gen.py:113 IND CLOCK 6120
2026-01-29 02:48:26.069 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:48:26.072 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:48:26.073 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 02:48:26.073 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 02:48:26.073 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 02:48:26.073 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:48:26.074 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 02:48:26.074 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 02:48:26.074 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.28.22:6700) Recv POWERON CMD
2026-01-29 02:48:26.074 [INFO] ctrl_if_trx.py:109 (MS@172.18.28.22:6700) Starting transceiver...
2026-01-29 02:48:26.102 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD HANDOVER
2026-01-29 02:48:26.105 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 02:48:26.105 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 02:48:26.105 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:48:26.106 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:48:26.110 [DEBUG] clck_gen.py:113 IND CLOCK 6222
2026-01-29 02:48:26.588 [DEBUG] clck_gen.py:113 IND CLOCK 6324
2026-01-29 02:48:27.066 [DEBUG] clck_gen.py:113 IND CLOCK 6426
2026-01-29 02:48:27.544 [DEBUG] clck_gen.py:113 IND CLOCK 6528
2026-01-29 02:48:28.023 [DEBUG] clck_gen.py:113 IND CLOCK 6630
2026-01-29 02:48:28.501 [DEBUG] clck_gen.py:113 IND CLOCK 6732
2026-01-29 02:48:28.979 [DEBUG] clck_gen.py:113 IND CLOCK 6834
2026-01-29 02:48:29.188 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:48:29.416 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:48:29.419 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:48:29.419 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 02:48:29.419 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 02:48:29.420 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 02:48:29.420 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:48:29.420 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 02:48:29.420 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 02:48:29.421 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.28.22:6700) Recv POWERON CMD
2026-01-29 02:48:29.421 [INFO] ctrl_if_trx.py:109 (MS@172.18.28.22:6700) Starting transceiver...
2026-01-29 02:48:29.448 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD HANDOVER
2026-01-29 02:48:29.452 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 02:48:29.452 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 02:48:29.452 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:48:29.453 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:48:29.457 [DEBUG] clck_gen.py:113 IND CLOCK 6936
2026-01-29 02:48:29.935 [DEBUG] clck_gen.py:113 IND CLOCK 7038
2026-01-29 02:48:30.413 [DEBUG] clck_gen.py:113 IND CLOCK 7140
2026-01-29 02:48:30.891 [DEBUG] clck_gen.py:113 IND CLOCK 7242
2026-01-29 02:48:31.368 [DEBUG] clck_gen.py:113 IND CLOCK 7344
2026-01-29 02:48:31.846 [DEBUG] clck_gen.py:113 IND CLOCK 7446
2026-01-29 02:48:32.325 [DEBUG] clck_gen.py:113 IND CLOCK 7548
2026-01-29 02:48:32.533 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:48:32.761 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:48:32.764 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:48:32.765 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 02:48:32.765 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 02:48:32.765 [WARNING] transceiver.py:257 (MS@172.18.28.22:6700) RX TRXD message (fn=7645 tn=5 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:48:32.765 [WARNING] transceiver.py:257 (MS@172.18.28.22:6700) RX TRXD message (fn=7645 tn=6 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:48:32.765 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 02:48:32.765 [WARNING] transceiver.py:257 (MS@172.18.28.22:6700) RX TRXD message (fn=7645 tn=7 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:48:32.765 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:48:32.766 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 02:48:32.766 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 02:48:32.766 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.28.22:6700) Recv POWERON CMD
2026-01-29 02:48:32.766 [INFO] ctrl_if_trx.py:109 (MS@172.18.28.22:6700) Starting transceiver...
2026-01-29 02:48:32.794 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD HANDOVER
2026-01-29 02:48:32.797 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 02:48:32.797 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 02:48:32.798 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:48:32.798 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:48:32.802 [DEBUG] clck_gen.py:113 IND CLOCK 7650
2026-01-29 02:48:33.247 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:48:33.280 [DEBUG] clck_gen.py:113 IND CLOCK 7752
2026-01-29 02:48:33.717 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:48:33.720 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:48:33.721 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 02:48:33.721 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 02:48:33.741 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 02:48:33.741 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 02:48:33.741 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 02:48:33.743 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:48:33.743 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 02:48:33.743 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 02:48:33.743 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.28.22:6700) Recv POWERON CMD
2026-01-29 02:48:33.743 [INFO] ctrl_if_trx.py:109 (MS@172.18.28.22:6700) Starting transceiver...
2026-01-29 02:48:33.758 [DEBUG] clck_gen.py:113 IND CLOCK 7854
2026-01-29 02:48:33.786 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD HANDOVER
2026-01-29 02:48:33.791 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.28.22:6700) Recv SETFH cmd
2026-01-29 02:48:33.791 [INFO] transceiver.py:201 (MS@172.18.28.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2026-01-29 02:48:33.792 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:48:33.792 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:48:34.236 [DEBUG] clck_gen.py:113 IND CLOCK 7956
2026-01-29 02:48:34.715 [DEBUG] clck_gen.py:113 IND CLOCK 8058
2026-01-29 02:48:35.194 [DEBUG] clck_gen.py:113 IND CLOCK 8160
2026-01-29 02:48:35.673 [DEBUG] clck_gen.py:113 IND CLOCK 8262
2026-01-29 02:48:36.151 [DEBUG] clck_gen.py:113 IND CLOCK 8364
2026-01-29 02:48:36.629 [DEBUG] clck_gen.py:113 IND CLOCK 8466
2026-01-29 02:48:37.000 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:48:37.108 [DEBUG] clck_gen.py:113 IND CLOCK 8568
2026-01-29 02:48:37.499 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:48:37.501 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:48:37.502 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 02:48:37.502 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 02:48:37.502 [INFO] transceiver.py:205 (MS@172.18.28.22:6700) Frequency hopping disabled
2026-01-29 02:48:37.502 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 02:48:37.502 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:48:37.503 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 02:48:37.503 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 02:48:37.503 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.28.22:6700) Recv POWERON CMD
2026-01-29 02:48:37.503 [INFO] ctrl_if_trx.py:109 (MS@172.18.28.22:6700) Starting transceiver...
2026-01-29 02:48:37.527 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD HANDOVER
2026-01-29 02:48:37.530 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.28.22:6700) Recv SETFH cmd
2026-01-29 02:48:37.530 [INFO] transceiver.py:201 (MS@172.18.28.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2026-01-29 02:48:37.530 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:48:37.531 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:48:37.586 [DEBUG] clck_gen.py:113 IND CLOCK 8670
2026-01-29 02:48:38.064 [DEBUG] clck_gen.py:113 IND CLOCK 8772
2026-01-29 02:48:38.542 [DEBUG] clck_gen.py:113 IND CLOCK 8874
2026-01-29 02:48:39.021 [DEBUG] clck_gen.py:113 IND CLOCK 8976
2026-01-29 02:48:39.499 [DEBUG] clck_gen.py:113 IND CLOCK 9078
2026-01-29 02:48:39.975 [DEBUG] clck_gen.py:113 IND CLOCK 9180
2026-01-29 02:48:40.454 [DEBUG] clck_gen.py:113 IND CLOCK 9282
2026-01-29 02:48:40.594 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:48:40.845 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:48:40.848 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:48:40.848 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 02:48:40.848 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 02:48:40.848 [INFO] transceiver.py:205 (MS@172.18.28.22:6700) Frequency hopping disabled
2026-01-29 02:48:40.849 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 02:48:40.849 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:48:40.849 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 02:48:40.849 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 02:48:40.850 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.28.22:6700) Recv POWERON CMD
2026-01-29 02:48:40.850 [INFO] ctrl_if_trx.py:109 (MS@172.18.28.22:6700) Starting transceiver...
2026-01-29 02:48:40.872 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD HANDOVER
2026-01-29 02:48:40.875 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.28.22:6700) Recv SETFH cmd
2026-01-29 02:48:40.875 [INFO] transceiver.py:201 (MS@172.18.28.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2026-01-29 02:48:40.876 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:48:40.876 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:48:40.933 [DEBUG] clck_gen.py:113 IND CLOCK 9384
2026-01-29 02:48:41.411 [DEBUG] clck_gen.py:113 IND CLOCK 9486
2026-01-29 02:48:41.889 [DEBUG] clck_gen.py:113 IND CLOCK 9588
2026-01-29 02:48:42.368 [DEBUG] clck_gen.py:113 IND CLOCK 9690
2026-01-29 02:48:42.846 [DEBUG] clck_gen.py:113 IND CLOCK 9792
2026-01-29 02:48:43.325 [DEBUG] clck_gen.py:113 IND CLOCK 9894
2026-01-29 02:48:43.803 [DEBUG] clck_gen.py:113 IND CLOCK 9996
2026-01-29 02:48:43.944 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:48:44.195 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:48:44.198 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:48:44.198 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 02:48:44.199 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 02:48:44.199 [INFO] transceiver.py:205 (MS@172.18.28.22:6700) Frequency hopping disabled
2026-01-29 02:48:44.199 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 02:48:44.199 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:48:44.199 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 02:48:44.200 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 02:48:44.200 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.28.22:6700) Recv POWERON CMD
2026-01-29 02:48:44.200 [INFO] ctrl_if_trx.py:109 (MS@172.18.28.22:6700) Starting transceiver...
2026-01-29 02:48:44.222 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD HANDOVER
2026-01-29 02:48:44.225 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.28.22:6700) Recv SETFH cmd
2026-01-29 02:48:44.226 [INFO] transceiver.py:201 (MS@172.18.28.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2026-01-29 02:48:44.226 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:48:44.226 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:48:44.282 [DEBUG] clck_gen.py:113 IND CLOCK 10098
2026-01-29 02:48:44.760 [DEBUG] clck_gen.py:113 IND CLOCK 10200
2026-01-29 02:48:44.900 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:48:45.152 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:48:45.154 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:48:45.155 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 02:48:45.155 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 02:48:45.155 [INFO] transceiver.py:205 (MS@172.18.28.22:6700) Frequency hopping disabled
2026-01-29 02:48:45.166 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 02:48:45.166 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:48:45.166 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:48:45.166 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:48:45.169 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 02:48:45.170 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:48:45.170 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:48:45.170 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:48:45.170 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.28.20:5700) Recv POWEROFF cmd
2026-01-29 02:48:45.170 [INFO] ctrl_if_trx.py:117 (BTS@172.18.28.20:5700) Stopping transceiver...
2026-01-29 02:48:45.170 [INFO] transceiver.py:246 Stopping clock generator
2026-01-29 02:48:45.171 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=10290 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:48:45.171 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=10290 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:48:45.171 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=10290 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:48:45.171 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=10290 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:48:45.171 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=10290 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:48:45.171 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=10290 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:48:45.171 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=10290 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:48:50.170 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.28.20:5700) Recv POWEROFF cmd
2026-01-29 02:48:50.170 [INFO] ctrl_if_trx.py:117 (BTS@172.18.28.20:5700) Stopping transceiver...
2026-01-29 02:48:50.171 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:48:50.172 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:48:50.173 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:48:50.173 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 02:48:50.182 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 02:48:50.183 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.28.20:5700) Recv SETFORMAT cmd
2026-01-29 02:48:50.183 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.28.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:48:50.183 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.28.20:5700) Recv SETFORMAT cmd
2026-01-29 02:48:50.183 [INFO] ctrl_if_trx.py:201 (BTS@172.18.28.20:5700) TRXD header version 1 -> 1
2026-01-29 02:48:50.185 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.28.20:5700/1) Recv RXTUNE cmd
2026-01-29 02:48:50.185 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.28.20:5700/1) Recv TXTUNE cmd
2026-01-29 02:48:50.186 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.28.20:5700/1) Recv SETFORMAT cmd
2026-01-29 02:48:50.186 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.28.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:48:50.186 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:48:50.187 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.28.20:5700/1) Recv NOMTXPOWER cmd
2026-01-29 02:48:50.187 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.28.20:5700/1) Recv SETFORMAT cmd
2026-01-29 02:48:50.187 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.28.20:5700/1) TRXD header version 1 -> 1
2026-01-29 02:48:50.188 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.28.20:5700/2) Recv RXTUNE cmd
2026-01-29 02:48:50.188 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.28.20:5700/2) Recv TXTUNE cmd
2026-01-29 02:48:50.188 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.28.20:5700/2) Recv SETFORMAT cmd
2026-01-29 02:48:50.188 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.28.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:48:50.188 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:48:50.188 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.28.20:5700/2) Recv NOMTXPOWER cmd
2026-01-29 02:48:50.188 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.28.20:5700/2) Recv SETFORMAT cmd
2026-01-29 02:48:50.188 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.28.20:5700/2) TRXD header version 1 -> 1
2026-01-29 02:48:50.190 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.28.20:5700/3) Recv RXTUNE cmd
2026-01-29 02:48:50.190 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.28.20:5700/3) Recv TXTUNE cmd
2026-01-29 02:48:50.190 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.28.20:5700/3) Recv SETFORMAT cmd
2026-01-29 02:48:50.190 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.28.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:48:50.190 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:48:50.190 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.28.20:5700/3) Recv NOMTXPOWER cmd
2026-01-29 02:48:50.190 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.28.20:5700/3) Recv SETFORMAT cmd
2026-01-29 02:48:50.190 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.28.20:5700/3) TRXD header version 1 -> 1
2026-01-29 02:48:50.193 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.28.20:5700) Recv RXTUNE cmd
2026-01-29 02:48:50.193 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETTSC
2026-01-29 02:48:50.193 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETTSC
2026-01-29 02:48:50.193 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETTSC
2026-01-29 02:48:50.194 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.28.20:5700) Recv TXTUNE cmd
2026-01-29 02:48:50.194 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETRXGAIN
2026-01-29 02:48:50.194 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETRXGAIN
2026-01-29 02:48:50.194 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETRXGAIN
2026-01-29 02:48:50.194 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETTSC
2026-01-29 02:48:50.194 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:48:50.194 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:48:50.194 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.28.20:5700) Recv NOMTXPOWER cmd
2026-01-29 02:48:50.194 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:48:50.194 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:48:50.194 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:48:50.194 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.28.20:5700) Recv POWERON CMD
2026-01-29 02:48:50.194 [INFO] ctrl_if_trx.py:109 (BTS@172.18.28.20:5700) Starting transceiver...
2026-01-29 02:48:50.194 [INFO] transceiver.py:243 Starting clock generator
2026-01-29 02:48:50.194 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-01-29 02:48:50.194 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:48:50.194 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:48:50.194 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:48:50.195 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETRXGAIN
2026-01-29 02:48:50.195 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:48:50.195 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:48:50.195 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:48:50.195 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:48:50.195 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:48:50.195 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:48:50.195 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:48:50.195 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:48:50.195 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:48:50.195 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:48:50.195 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:48:50.195 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:48:50.195 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:48:50.195 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:48:50.195 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:48:50.195 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:48:50.195 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:48:50.195 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:48:50.195 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:48:50.195 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:48:50.195 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:48:50.195 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:48:50.195 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:48:50.195 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:48:50.199 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-01-29 02:48:50.682 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-01-29 02:48:50.725 [DEBUG] fake_trx.py:278 (BTS@172.18.28.20:5700) Recv FAKE_TOA cmd
2026-01-29 02:48:50.726 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:48:50.727 [DEBUG] fake_trx.py:297 (BTS@172.18.28.20:5700) Recv FAKE_RSSI cmd
2026-01-29 02:48:50.728 [DEBUG] fake_trx.py:322 (BTS@172.18.28.20:5700) Recv FAKE_CI cmd
2026-01-29 02:48:50.733 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 02:48:50.733 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 02:48:50.733 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 02:48:50.735 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:48:50.735 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 02:48:50.735 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 02:48:50.735 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.28.22:6700) Recv POWERON CMD
2026-01-29 02:48:50.736 [INFO] ctrl_if_trx.py:109 (MS@172.18.28.22:6700) Starting transceiver...
2026-01-29 02:48:51.161 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-01-29 02:48:51.197 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 02:48:51.197 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:48:51.198 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:48:51.201 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:48:51.635 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-01-29 02:48:52.113 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-01-29 02:48:52.197 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 02:48:52.198 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:48:52.199 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:48:52.202 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:48:52.591 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-01-29 02:48:53.068 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-01-29 02:48:53.198 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 02:48:53.199 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:48:53.200 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:48:53.203 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:48:53.545 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-01-29 02:48:54.023 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-01-29 02:48:54.199 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 02:48:54.199 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:48:54.201 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:48:54.203 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:48:54.501 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-01-29 02:48:54.979 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-01-29 02:48:55.200 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 02:48:55.201 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:48:55.202 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:48:55.204 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:48:55.457 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-01-29 02:48:55.929 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-01-29 02:48:56.399 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-01-29 02:48:56.870 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-01-29 02:48:57.341 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-01-29 02:48:57.813 [DEBUG] clck_gen.py:113 IND CLOCK 1632
2026-01-29 02:48:58.284 [DEBUG] clck_gen.py:113 IND CLOCK 1734
2026-01-29 02:48:58.755 [DEBUG] clck_gen.py:113 IND CLOCK 1836
2026-01-29 02:48:59.225 [DEBUG] clck_gen.py:113 IND CLOCK 1938
2026-01-29 02:48:59.599 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 02:48:59.599 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 02:48:59.603 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 02:48:59.603 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:48:59.603 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:48:59.603 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:48:59.606 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 02:48:59.606 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:48:59.606 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:48:59.606 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.28.20:5700) Recv POWEROFF cmd
2026-01-29 02:48:59.606 [INFO] ctrl_if_trx.py:117 (BTS@172.18.28.20:5700) Stopping transceiver...
2026-01-29 02:48:59.606 [INFO] transceiver.py:246 Stopping clock generator
2026-01-29 02:48:59.606 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:48:59.606 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=2022 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:48:59.606 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=2022 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:48:59.606 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=2022 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:48:59.606 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=2022 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:48:59.606 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=2022 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:48:59.606 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=2022 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:48:59.606 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=2022 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:48:59.606 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=2023 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:48:59.606 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=2023 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:48:59.606 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=2023 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:48:59.606 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=2023 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:48:59.606 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=2023 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:48:59.606 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=2023 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:48:59.606 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=2023 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:48:59.606 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=2023 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:49:04.607 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.28.20:5700) Recv POWEROFF cmd
2026-01-29 02:49:04.607 [INFO] ctrl_if_trx.py:117 (BTS@172.18.28.20:5700) Stopping transceiver...
2026-01-29 02:49:04.608 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:49:04.609 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:49:04.610 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:49:04.610 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 02:49:04.620 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 02:49:04.621 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.28.20:5700) Recv SETFORMAT cmd
2026-01-29 02:49:04.622 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.28.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:49:04.622 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.28.20:5700) Recv SETFORMAT cmd
2026-01-29 02:49:04.622 [INFO] ctrl_if_trx.py:201 (BTS@172.18.28.20:5700) TRXD header version 1 -> 1
2026-01-29 02:49:04.627 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.28.20:5700/1) Recv RXTUNE cmd
2026-01-29 02:49:04.627 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.28.20:5700/1) Recv TXTUNE cmd
2026-01-29 02:49:04.628 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.28.20:5700/1) Recv SETFORMAT cmd
2026-01-29 02:49:04.628 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.28.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:49:04.629 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:49:04.629 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.28.20:5700/1) Recv NOMTXPOWER cmd
2026-01-29 02:49:04.629 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.28.20:5700/1) Recv SETFORMAT cmd
2026-01-29 02:49:04.630 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.28.20:5700/1) TRXD header version 1 -> 1
2026-01-29 02:49:04.631 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.28.20:5700/2) Recv RXTUNE cmd
2026-01-29 02:49:04.631 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.28.20:5700/2) Recv TXTUNE cmd
2026-01-29 02:49:04.631 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.28.20:5700/2) Recv SETFORMAT cmd
2026-01-29 02:49:04.631 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.28.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:49:04.631 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:49:04.632 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.28.20:5700/2) Recv NOMTXPOWER cmd
2026-01-29 02:49:04.632 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.28.20:5700/2) Recv SETFORMAT cmd
2026-01-29 02:49:04.632 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.28.20:5700/2) TRXD header version 1 -> 1
2026-01-29 02:49:04.634 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.28.20:5700/3) Recv RXTUNE cmd
2026-01-29 02:49:04.634 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.28.20:5700/3) Recv TXTUNE cmd
2026-01-29 02:49:04.634 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.28.20:5700/3) Recv SETFORMAT cmd
2026-01-29 02:49:04.634 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.28.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:49:04.634 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:49:04.634 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.28.20:5700/3) Recv NOMTXPOWER cmd
2026-01-29 02:49:04.634 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.28.20:5700/3) Recv SETFORMAT cmd
2026-01-29 02:49:04.634 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.28.20:5700/3) TRXD header version 1 -> 1
2026-01-29 02:49:04.637 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.28.20:5700) Recv RXTUNE cmd
2026-01-29 02:49:04.637 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETTSC
2026-01-29 02:49:04.637 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETTSC
2026-01-29 02:49:04.637 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETTSC
2026-01-29 02:49:04.637 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.28.20:5700) Recv TXTUNE cmd
2026-01-29 02:49:04.638 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETRXGAIN
2026-01-29 02:49:04.638 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETRXGAIN
2026-01-29 02:49:04.638 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETRXGAIN
2026-01-29 02:49:04.638 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETTSC
2026-01-29 02:49:04.638 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:49:04.638 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:49:04.638 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.28.20:5700) Recv NOMTXPOWER cmd
2026-01-29 02:49:04.638 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:49:04.638 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:49:04.638 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.28.20:5700) Recv POWERON CMD
2026-01-29 02:49:04.638 [INFO] ctrl_if_trx.py:109 (BTS@172.18.28.20:5700) Starting transceiver...
2026-01-29 02:49:04.638 [INFO] transceiver.py:243 Starting clock generator
2026-01-29 02:49:04.638 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-01-29 02:49:04.638 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:49:04.638 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:49:04.638 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:49:04.638 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETRXGAIN
2026-01-29 02:49:04.638 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:49:04.638 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:49:04.638 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:49:04.638 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:49:04.639 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:49:04.639 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:49:04.639 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:49:04.639 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:49:04.639 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:49:04.639 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:49:04.639 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:49:04.639 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:49:04.639 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:49:04.639 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:49:04.639 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:49:04.639 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:49:04.639 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:49:04.639 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:49:04.639 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:49:04.639 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:49:04.639 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:49:04.639 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:49:04.639 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:49:04.639 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:49:04.639 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:49:04.643 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-01-29 02:49:05.125 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-01-29 02:49:05.160 [DEBUG] fake_trx.py:278 (BTS@172.18.28.20:5700) Recv FAKE_TOA cmd
2026-01-29 02:49:05.161 [DEBUG] fake_trx.py:297 (BTS@172.18.28.20:5700) Recv FAKE_RSSI cmd
2026-01-29 02:49:05.162 [DEBUG] fake_trx.py:322 (BTS@172.18.28.20:5700) Recv FAKE_CI cmd
2026-01-29 02:49:05.162 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:49:05.164 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 02:49:05.164 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 02:49:05.164 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 02:49:05.164 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:49:05.164 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 02:49:05.164 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 02:49:05.164 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.28.22:6700) Recv POWERON CMD
2026-01-29 02:49:05.164 [INFO] ctrl_if_trx.py:109 (MS@172.18.28.22:6700) Starting transceiver...
2026-01-29 02:49:05.599 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-01-29 02:49:05.641 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 02:49:05.641 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:49:05.643 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:49:05.645 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:49:06.068 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-01-29 02:49:06.539 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-01-29 02:49:06.642 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:49:06.642 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 02:49:06.643 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:49:06.645 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:49:07.010 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-01-29 02:49:07.481 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-01-29 02:49:07.643 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 02:49:07.643 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:49:07.644 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:49:07.646 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:49:07.952 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-01-29 02:49:08.427 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-01-29 02:49:08.644 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:49:08.644 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 02:49:08.644 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:49:08.647 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:49:08.899 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-01-29 02:49:09.377 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-01-29 02:49:09.645 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 02:49:09.645 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:49:09.646 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:49:09.647 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:49:09.855 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-01-29 02:49:10.334 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-01-29 02:49:10.809 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-01-29 02:49:11.284 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-01-29 02:49:11.756 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-01-29 02:49:12.232 [DEBUG] clck_gen.py:113 IND CLOCK 1632
2026-01-29 02:49:12.709 [DEBUG] clck_gen.py:113 IND CLOCK 1734
2026-01-29 02:49:13.181 [DEBUG] clck_gen.py:113 IND CLOCK 1836
2026-01-29 02:49:13.654 [DEBUG] clck_gen.py:113 IND CLOCK 1938
2026-01-29 02:49:13.967 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 02:49:13.967 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 02:49:13.971 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 02:49:13.972 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:49:13.972 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:49:13.972 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:49:13.975 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 02:49:13.975 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:49:13.975 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:49:13.975 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:49:13.975 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.28.20:5700) Recv POWEROFF cmd
2026-01-29 02:49:13.975 [INFO] ctrl_if_trx.py:117 (BTS@172.18.28.20:5700) Stopping transceiver...
2026-01-29 02:49:13.975 [INFO] transceiver.py:246 Stopping clock generator
2026-01-29 02:49:13.975 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=2010 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:49:13.975 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=2010 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:49:13.975 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=2010 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:49:13.975 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=2010 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:49:13.975 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=2010 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:49:13.975 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=2010 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:49:18.974 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.28.20:5700) Recv POWEROFF cmd
2026-01-29 02:49:18.974 [INFO] ctrl_if_trx.py:117 (BTS@172.18.28.20:5700) Stopping transceiver...
2026-01-29 02:49:18.978 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:49:18.978 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:49:18.978 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 02:49:18.978 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:49:18.987 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 02:49:18.989 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.28.20:5700) Recv SETFORMAT cmd
2026-01-29 02:49:18.989 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.28.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:49:18.990 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.28.20:5700) Recv SETFORMAT cmd
2026-01-29 02:49:18.990 [INFO] ctrl_if_trx.py:201 (BTS@172.18.28.20:5700) TRXD header version 1 -> 1
2026-01-29 02:49:18.995 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.28.20:5700/1) Recv RXTUNE cmd
2026-01-29 02:49:18.995 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.28.20:5700/1) Recv TXTUNE cmd
2026-01-29 02:49:18.995 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.28.20:5700/1) Recv SETFORMAT cmd
2026-01-29 02:49:18.995 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.28.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:49:18.996 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:49:18.996 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.28.20:5700/1) Recv NOMTXPOWER cmd
2026-01-29 02:49:18.996 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.28.20:5700/1) Recv SETFORMAT cmd
2026-01-29 02:49:18.996 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.28.20:5700/1) TRXD header version 1 -> 1
2026-01-29 02:49:18.999 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.28.20:5700/2) Recv RXTUNE cmd
2026-01-29 02:49:18.999 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.28.20:5700/2) Recv TXTUNE cmd
2026-01-29 02:49:18.999 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.28.20:5700/2) Recv SETFORMAT cmd
2026-01-29 02:49:18.999 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.28.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:49:18.999 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:49:18.999 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.28.20:5700/2) Recv NOMTXPOWER cmd
2026-01-29 02:49:18.999 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.28.20:5700/2) Recv SETFORMAT cmd
2026-01-29 02:49:18.999 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.28.20:5700/2) TRXD header version 1 -> 1
2026-01-29 02:49:19.001 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.28.20:5700/3) Recv RXTUNE cmd
2026-01-29 02:49:19.001 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.28.20:5700/3) Recv TXTUNE cmd
2026-01-29 02:49:19.001 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.28.20:5700/3) Recv SETFORMAT cmd
2026-01-29 02:49:19.001 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.28.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:49:19.001 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:49:19.001 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.28.20:5700/3) Recv NOMTXPOWER cmd
2026-01-29 02:49:19.001 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.28.20:5700/3) Recv SETFORMAT cmd
2026-01-29 02:49:19.001 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.28.20:5700/3) TRXD header version 1 -> 1
2026-01-29 02:49:19.002 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.28.20:5700) Recv RXTUNE cmd
2026-01-29 02:49:19.002 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETTSC
2026-01-29 02:49:19.002 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETTSC
2026-01-29 02:49:19.002 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETTSC
2026-01-29 02:49:19.002 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.28.20:5700) Recv TXTUNE cmd
2026-01-29 02:49:19.002 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETRXGAIN
2026-01-29 02:49:19.002 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETRXGAIN
2026-01-29 02:49:19.002 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETRXGAIN
2026-01-29 02:49:19.002 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETTSC
2026-01-29 02:49:19.002 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:49:19.002 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:49:19.002 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.28.20:5700) Recv NOMTXPOWER cmd
2026-01-29 02:49:19.002 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:49:19.002 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:49:19.002 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:49:19.002 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.28.20:5700) Recv POWERON CMD
2026-01-29 02:49:19.002 [INFO] ctrl_if_trx.py:109 (BTS@172.18.28.20:5700) Starting transceiver...
2026-01-29 02:49:19.002 [INFO] transceiver.py:243 Starting clock generator
2026-01-29 02:49:19.002 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-01-29 02:49:19.002 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:49:19.002 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:49:19.002 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:49:19.002 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETRXGAIN
2026-01-29 02:49:19.002 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:49:19.002 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:49:19.002 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:49:19.003 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:49:19.003 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:49:19.003 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:49:19.003 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:49:19.003 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:49:19.003 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:49:19.003 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:49:19.003 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:49:19.003 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:49:19.003 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:49:19.003 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:49:19.003 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:49:19.003 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:49:19.003 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:49:19.003 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:49:19.003 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:49:19.003 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:49:19.003 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:49:19.003 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:49:19.003 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:49:19.003 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:49:19.007 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-01-29 02:49:19.491 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-01-29 02:49:19.533 [DEBUG] fake_trx.py:278 (BTS@172.18.28.20:5700) Recv FAKE_TOA cmd
2026-01-29 02:49:19.534 [DEBUG] fake_trx.py:297 (BTS@172.18.28.20:5700) Recv FAKE_RSSI cmd
2026-01-29 02:49:19.535 [DEBUG] fake_trx.py:322 (BTS@172.18.28.20:5700) Recv FAKE_CI cmd
2026-01-29 02:49:19.535 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:49:19.537 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 02:49:19.537 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 02:49:19.537 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 02:49:19.972 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-01-29 02:49:20.004 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 02:49:20.005 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:49:20.006 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:49:20.013 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:49:20.454 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-01-29 02:49:20.539 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:49:20.539 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 02:49:20.540 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 02:49:20.540 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.28.22:6700) Recv POWERON CMD
2026-01-29 02:49:20.541 [INFO] ctrl_if_trx.py:109 (MS@172.18.28.22:6700) Starting transceiver...
2026-01-29 02:49:20.933 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-01-29 02:49:21.006 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:49:21.006 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 02:49:21.006 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:49:21.014 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:49:21.405 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-01-29 02:49:21.876 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-01-29 02:49:22.007 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:49:22.007 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 02:49:22.007 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:49:22.015 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:49:22.346 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-01-29 02:49:22.818 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-01-29 02:49:23.008 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:49:23.009 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 02:49:23.009 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:49:23.015 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:49:23.288 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-01-29 02:49:23.761 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-01-29 02:49:24.009 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 02:49:24.010 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:49:24.010 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:49:24.016 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:49:24.236 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-01-29 02:49:24.714 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-01-29 02:49:25.192 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-01-29 02:49:25.664 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-01-29 02:49:26.135 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-01-29 02:49:26.606 [DEBUG] clck_gen.py:113 IND CLOCK 1632
2026-01-29 02:49:27.082 [DEBUG] clck_gen.py:113 IND CLOCK 1734
2026-01-29 02:49:27.555 [DEBUG] clck_gen.py:113 IND CLOCK 1836
2026-01-29 02:49:28.033 [DEBUG] clck_gen.py:113 IND CLOCK 1938
2026-01-29 02:49:28.505 [DEBUG] clck_gen.py:113 IND CLOCK 2040
2026-01-29 02:49:28.981 [DEBUG] clck_gen.py:113 IND CLOCK 2142
2026-01-29 02:49:29.458 [DEBUG] clck_gen.py:113 IND CLOCK 2244
2026-01-29 02:49:29.936 [DEBUG] clck_gen.py:113 IND CLOCK 2346
2026-01-29 02:49:30.415 [DEBUG] clck_gen.py:113 IND CLOCK 2448
2026-01-29 02:49:30.893 [DEBUG] clck_gen.py:113 IND CLOCK 2550
2026-01-29 02:49:31.371 [DEBUG] clck_gen.py:113 IND CLOCK 2652
2026-01-29 02:49:31.849 [DEBUG] clck_gen.py:113 IND CLOCK 2754
2026-01-29 02:49:32.327 [DEBUG] clck_gen.py:113 IND CLOCK 2856
2026-01-29 02:49:32.353 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 02:49:32.353 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 02:49:32.358 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 02:49:32.358 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:49:32.358 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:49:32.359 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:49:32.362 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 02:49:32.362 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:49:32.362 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:49:32.362 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.28.20:5700) Recv POWEROFF cmd
2026-01-29 02:49:32.362 [INFO] ctrl_if_trx.py:117 (BTS@172.18.28.20:5700) Stopping transceiver...
2026-01-29 02:49:32.362 [INFO] transceiver.py:246 Stopping clock generator
2026-01-29 02:49:32.363 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:49:32.363 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=2864 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:49:32.363 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=2864 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:49:32.363 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=2864 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:49:32.363 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=2865 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:49:32.363 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=2865 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:49:32.363 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=2865 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:49:32.363 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=2865 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:49:32.364 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=2865 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:49:32.364 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=2865 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:49:32.364 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=2865 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:49:32.364 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=2865 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:49:37.362 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.28.20:5700) Recv POWEROFF cmd
2026-01-29 02:49:37.363 [INFO] ctrl_if_trx.py:117 (BTS@172.18.28.20:5700) Stopping transceiver...
2026-01-29 02:49:37.364 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:49:37.365 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:49:37.365 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:49:37.366 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 02:49:37.373 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 02:49:37.374 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.28.20:5700) Recv SETFORMAT cmd
2026-01-29 02:49:37.374 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.28.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:49:37.374 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.28.20:5700) Recv SETFORMAT cmd
2026-01-29 02:49:37.375 [INFO] ctrl_if_trx.py:201 (BTS@172.18.28.20:5700) TRXD header version 1 -> 1
2026-01-29 02:49:37.377 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.28.20:5700/1) Recv RXTUNE cmd
2026-01-29 02:49:37.377 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.28.20:5700/1) Recv TXTUNE cmd
2026-01-29 02:49:37.378 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.28.20:5700/1) Recv SETFORMAT cmd
2026-01-29 02:49:37.378 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.28.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:49:37.378 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:49:37.379 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.28.20:5700/1) Recv NOMTXPOWER cmd
2026-01-29 02:49:37.379 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.28.20:5700/1) Recv SETFORMAT cmd
2026-01-29 02:49:37.379 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.28.20:5700/1) TRXD header version 1 -> 1
2026-01-29 02:49:37.380 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.28.20:5700/2) Recv RXTUNE cmd
2026-01-29 02:49:37.380 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.28.20:5700/2) Recv TXTUNE cmd
2026-01-29 02:49:37.380 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.28.20:5700/2) Recv SETFORMAT cmd
2026-01-29 02:49:37.380 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.28.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:49:37.380 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:49:37.380 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.28.20:5700/2) Recv NOMTXPOWER cmd
2026-01-29 02:49:37.380 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.28.20:5700/2) Recv SETFORMAT cmd
2026-01-29 02:49:37.380 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.28.20:5700/2) TRXD header version 1 -> 1
2026-01-29 02:49:37.382 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.28.20:5700/3) Recv RXTUNE cmd
2026-01-29 02:49:37.382 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.28.20:5700/3) Recv TXTUNE cmd
2026-01-29 02:49:37.382 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.28.20:5700/3) Recv SETFORMAT cmd
2026-01-29 02:49:37.382 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.28.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:49:37.382 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:49:37.382 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.28.20:5700/3) Recv NOMTXPOWER cmd
2026-01-29 02:49:37.382 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.28.20:5700/3) Recv SETFORMAT cmd
2026-01-29 02:49:37.382 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.28.20:5700/3) TRXD header version 1 -> 1
2026-01-29 02:49:37.385 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.28.20:5700) Recv RXTUNE cmd
2026-01-29 02:49:37.385 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETTSC
2026-01-29 02:49:37.385 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETTSC
2026-01-29 02:49:37.385 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETTSC
2026-01-29 02:49:37.385 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.28.20:5700) Recv TXTUNE cmd
2026-01-29 02:49:37.385 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETRXGAIN
2026-01-29 02:49:37.385 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETRXGAIN
2026-01-29 02:49:37.385 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETRXGAIN
2026-01-29 02:49:37.385 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETTSC
2026-01-29 02:49:37.385 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:49:37.385 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:49:37.385 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.28.20:5700) Recv NOMTXPOWER cmd
2026-01-29 02:49:37.385 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:49:37.385 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:49:37.385 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:49:37.385 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.28.20:5700) Recv POWERON CMD
2026-01-29 02:49:37.385 [INFO] ctrl_if_trx.py:109 (BTS@172.18.28.20:5700) Starting transceiver...
2026-01-29 02:49:37.385 [INFO] transceiver.py:243 Starting clock generator
2026-01-29 02:49:37.385 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-01-29 02:49:37.385 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:49:37.385 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:49:37.385 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:49:37.385 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETRXGAIN
2026-01-29 02:49:37.386 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:49:37.386 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:49:37.386 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:49:37.386 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:49:37.386 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:49:37.386 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:49:37.386 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:49:37.386 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:49:37.386 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:49:37.386 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:49:37.386 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:49:37.386 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:49:37.386 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:49:37.386 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:49:37.386 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:49:37.386 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:49:37.386 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:49:37.386 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:49:37.386 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:49:37.386 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:49:37.386 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:49:37.386 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:49:37.386 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:49:37.386 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:49:37.390 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-01-29 02:49:37.873 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-01-29 02:49:37.908 [DEBUG] fake_trx.py:278 (BTS@172.18.28.20:5700) Recv FAKE_TOA cmd
2026-01-29 02:49:37.909 [DEBUG] fake_trx.py:297 (BTS@172.18.28.20:5700) Recv FAKE_RSSI cmd
2026-01-29 02:49:37.910 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:49:37.910 [DEBUG] fake_trx.py:322 (BTS@172.18.28.20:5700) Recv FAKE_CI cmd
2026-01-29 02:49:37.912 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 02:49:37.912 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 02:49:37.912 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 02:49:37.912 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:49:37.912 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 02:49:37.912 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 02:49:37.912 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.28.22:6700) Recv POWERON CMD
2026-01-29 02:49:37.912 [INFO] ctrl_if_trx.py:109 (MS@172.18.28.22:6700) Starting transceiver...
2026-01-29 02:49:38.350 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-01-29 02:49:38.388 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:49:38.388 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 02:49:38.388 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:49:38.388 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:49:38.828 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-01-29 02:49:38.916 [DEBUG] fake_trx.py:278 (BTS@172.18.28.20:5700) Recv FAKE_TOA cmd
2026-01-29 02:49:39.306 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-01-29 02:49:39.389 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:49:39.389 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:49:39.390 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 02:49:39.390 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:49:39.425 [DEBUG] fake_trx.py:278 (BTS@172.18.28.20:5700) Recv FAKE_TOA cmd
2026-01-29 02:49:39.784 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-01-29 02:49:39.935 [DEBUG] fake_trx.py:278 (BTS@172.18.28.20:5700) Recv FAKE_TOA cmd
2026-01-29 02:49:40.262 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-01-29 02:49:40.390 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:49:40.390 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:49:40.390 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 02:49:40.390 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:49:40.739 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-01-29 02:49:41.217 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-01-29 02:49:41.391 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:49:41.391 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:49:41.391 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 02:49:41.391 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:49:41.695 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-01-29 02:49:41.962 [DEBUG] fake_trx.py:278 (BTS@172.18.28.20:5700) Recv FAKE_TOA cmd
2026-01-29 02:49:42.173 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-01-29 02:49:42.391 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:49:42.392 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 02:49:42.392 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:49:42.392 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:49:42.469 [DEBUG] fake_trx.py:278 (BTS@172.18.28.20:5700) Recv FAKE_TOA cmd
2026-01-29 02:49:42.651 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-01-29 02:49:42.978 [DEBUG] fake_trx.py:278 (BTS@172.18.28.20:5700) Recv FAKE_TOA cmd
2026-01-29 02:49:43.129 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-01-29 02:49:43.484 [DEBUG] fake_trx.py:278 (BTS@172.18.28.20:5700) Recv FAKE_TOA cmd
2026-01-29 02:49:43.607 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-01-29 02:49:44.085 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-01-29 02:49:44.563 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-01-29 02:49:45.041 [DEBUG] clck_gen.py:113 IND CLOCK 1632
2026-01-29 02:49:45.492 [DEBUG] fake_trx.py:278 (BTS@172.18.28.20:5700) Recv FAKE_TOA cmd
2026-01-29 02:49:45.518 [DEBUG] clck_gen.py:113 IND CLOCK 1734
2026-01-29 02:49:45.997 [DEBUG] clck_gen.py:113 IND CLOCK 1836
2026-01-29 02:49:46.475 [DEBUG] clck_gen.py:113 IND CLOCK 1938
2026-01-29 02:49:46.953 [DEBUG] clck_gen.py:113 IND CLOCK 2040
2026-01-29 02:49:47.431 [DEBUG] clck_gen.py:113 IND CLOCK 2142
2026-01-29 02:49:47.512 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 02:49:47.512 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 02:49:47.517 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 02:49:47.517 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:49:47.517 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:49:47.517 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:49:47.521 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 02:49:47.521 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:49:47.521 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:49:47.521 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:49:47.522 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.28.20:5700) Recv POWEROFF cmd
2026-01-29 02:49:47.522 [INFO] ctrl_if_trx.py:117 (BTS@172.18.28.20:5700) Stopping transceiver...
2026-01-29 02:49:47.522 [INFO] transceiver.py:246 Stopping clock generator
2026-01-29 02:49:47.522 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=2162 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:49:47.522 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=2162 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:49:47.522 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=2162 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:49:47.523 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=2162 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:49:47.523 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=2162 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:49:47.523 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=2162 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:49:47.523 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=2163 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:49:47.523 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=2163 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:49:47.523 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=2163 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:49:47.523 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=2163 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:49:47.523 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=2163 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:49:47.523 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=2163 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:49:47.523 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=2163 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:49:47.523 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=2163 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:49:52.521 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.28.20:5700) Recv POWEROFF cmd
2026-01-29 02:49:52.521 [INFO] ctrl_if_trx.py:117 (BTS@172.18.28.20:5700) Stopping transceiver...
2026-01-29 02:49:52.522 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:49:52.524 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:49:52.525 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:49:52.525 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 02:49:52.530 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 02:49:52.532 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.28.20:5700) Recv SETFORMAT cmd
2026-01-29 02:49:52.532 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.28.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:49:52.532 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.28.20:5700) Recv SETFORMAT cmd
2026-01-29 02:49:52.532 [INFO] ctrl_if_trx.py:201 (BTS@172.18.28.20:5700) TRXD header version 1 -> 1
2026-01-29 02:49:52.536 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.28.20:5700/1) Recv RXTUNE cmd
2026-01-29 02:49:52.536 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.28.20:5700/1) Recv TXTUNE cmd
2026-01-29 02:49:52.536 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.28.20:5700/1) Recv SETFORMAT cmd
2026-01-29 02:49:52.537 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.28.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:49:52.537 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:49:52.537 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.28.20:5700/1) Recv NOMTXPOWER cmd
2026-01-29 02:49:52.538 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.28.20:5700/1) Recv SETFORMAT cmd
2026-01-29 02:49:52.538 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.28.20:5700/1) TRXD header version 1 -> 1
2026-01-29 02:49:52.539 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.28.20:5700/2) Recv RXTUNE cmd
2026-01-29 02:49:52.539 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.28.20:5700/2) Recv TXTUNE cmd
2026-01-29 02:49:52.539 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.28.20:5700/2) Recv SETFORMAT cmd
2026-01-29 02:49:52.539 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.28.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:49:52.539 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:49:52.539 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.28.20:5700/2) Recv NOMTXPOWER cmd
2026-01-29 02:49:52.539 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.28.20:5700/2) Recv SETFORMAT cmd
2026-01-29 02:49:52.539 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.28.20:5700/2) TRXD header version 1 -> 1
2026-01-29 02:49:52.541 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.28.20:5700/3) Recv RXTUNE cmd
2026-01-29 02:49:52.541 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.28.20:5700/3) Recv TXTUNE cmd
2026-01-29 02:49:52.541 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.28.20:5700/3) Recv SETFORMAT cmd
2026-01-29 02:49:52.542 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.28.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:49:52.542 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:49:52.542 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.28.20:5700/3) Recv NOMTXPOWER cmd
2026-01-29 02:49:52.542 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.28.20:5700/3) Recv SETFORMAT cmd
2026-01-29 02:49:52.542 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.28.20:5700/3) TRXD header version 1 -> 1
2026-01-29 02:49:52.545 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.28.20:5700) Recv RXTUNE cmd
2026-01-29 02:49:52.545 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETTSC
2026-01-29 02:49:52.545 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETTSC
2026-01-29 02:49:52.545 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETTSC
2026-01-29 02:49:52.545 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.28.20:5700) Recv TXTUNE cmd
2026-01-29 02:49:52.545 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETRXGAIN
2026-01-29 02:49:52.545 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETRXGAIN
2026-01-29 02:49:52.545 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETRXGAIN
2026-01-29 02:49:52.545 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETTSC
2026-01-29 02:49:52.545 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:49:52.546 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:49:52.546 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:49:52.546 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.28.20:5700) Recv NOMTXPOWER cmd
2026-01-29 02:49:52.546 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:49:52.546 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:49:52.546 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.28.20:5700) Recv POWERON CMD
2026-01-29 02:49:52.546 [INFO] ctrl_if_trx.py:109 (BTS@172.18.28.20:5700) Starting transceiver...
2026-01-29 02:49:52.546 [INFO] transceiver.py:243 Starting clock generator
2026-01-29 02:49:52.546 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-01-29 02:49:52.546 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:49:52.546 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:49:52.546 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:49:52.546 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETRXGAIN
2026-01-29 02:49:52.546 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:49:52.546 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:49:52.546 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:49:52.546 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:49:52.546 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:49:52.546 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:49:52.546 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:49:52.546 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:49:52.546 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:49:52.546 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:49:52.546 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:49:52.546 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:49:52.546 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:49:52.546 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:49:52.546 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:49:52.546 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:49:52.547 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:49:52.547 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:49:52.547 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:49:52.547 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:49:52.547 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:49:52.547 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:49:52.547 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:49:52.547 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:49:52.551 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-01-29 02:49:53.034 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-01-29 02:49:53.071 [DEBUG] fake_trx.py:278 (BTS@172.18.28.20:5700) Recv FAKE_TOA cmd
2026-01-29 02:49:53.072 [DEBUG] fake_trx.py:297 (BTS@172.18.28.20:5700) Recv FAKE_RSSI cmd
2026-01-29 02:49:53.074 [DEBUG] fake_trx.py:322 (BTS@172.18.28.20:5700) Recv FAKE_CI cmd
2026-01-29 02:49:53.074 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:49:53.100 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 02:49:53.101 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 02:49:53.101 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 02:49:53.105 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:49:53.106 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 02:49:53.106 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 02:49:53.107 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.28.22:6700) Recv POWERON CMD
2026-01-29 02:49:53.107 [INFO] ctrl_if_trx.py:109 (MS@172.18.28.22:6700) Starting transceiver...
2026-01-29 02:49:53.131 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD HANDOVER
2026-01-29 02:49:53.137 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 02:49:53.137 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 02:49:53.138 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:49:53.138 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:49:53.197 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:49:53.202 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:49:53.205 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:49:53.205 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 02:49:53.205 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 02:49:53.224 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 02:49:53.224 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 02:49:53.224 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 02:49:53.225 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:49:53.225 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 02:49:53.225 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 02:49:53.225 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.28.22:6700) Recv POWERON CMD
2026-01-29 02:49:53.225 [INFO] ctrl_if_trx.py:109 (MS@172.18.28.22:6700) Starting transceiver...
2026-01-29 02:49:53.274 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD HANDOVER
2026-01-29 02:49:53.279 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 02:49:53.280 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 02:49:53.280 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:49:53.281 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:49:53.451 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:49:53.456 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:49:53.459 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:49:53.459 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 02:49:53.459 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 02:49:53.478 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 02:49:53.478 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 02:49:53.478 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 02:49:53.480 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:49:53.480 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 02:49:53.480 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 02:49:53.480 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.28.22:6700) Recv POWERON CMD
2026-01-29 02:49:53.480 [INFO] ctrl_if_trx.py:109 (MS@172.18.28.22:6700) Starting transceiver...
2026-01-29 02:49:53.508 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD HANDOVER
2026-01-29 02:49:53.511 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-01-29 02:49:53.512 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 02:49:53.513 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 02:49:53.514 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:49:53.514 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:49:53.549 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 02:49:53.549 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:49:53.551 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:49:53.552 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:49:53.719 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:49:53.723 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:49:53.726 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:49:53.727 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 02:49:53.728 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 02:49:53.742 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 02:49:53.742 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 02:49:53.742 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 02:49:53.743 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:49:53.743 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 02:49:53.743 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 02:49:53.743 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.28.22:6700) Recv POWERON CMD
2026-01-29 02:49:53.743 [INFO] ctrl_if_trx.py:109 (MS@172.18.28.22:6700) Starting transceiver...
2026-01-29 02:49:53.796 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD HANDOVER
2026-01-29 02:49:53.801 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 02:49:53.801 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 02:49:53.801 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:49:53.801 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:49:53.973 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:49:53.978 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:49:53.980 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:49:53.981 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 02:49:53.981 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 02:49:53.988 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-01-29 02:49:53.999 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 02:49:53.999 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 02:49:53.999 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 02:49:54.001 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:49:54.001 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 02:49:54.001 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 02:49:54.001 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.28.22:6700) Recv POWERON CMD
2026-01-29 02:49:54.001 [INFO] ctrl_if_trx.py:109 (MS@172.18.28.22:6700) Starting transceiver...
2026-01-29 02:49:54.039 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD HANDOVER
2026-01-29 02:49:54.043 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 02:49:54.044 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 02:49:54.044 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:49:54.045 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:49:54.045 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:49:54.049 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:49:54.051 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:49:54.051 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 02:49:54.051 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 02:49:54.062 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 02:49:54.062 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 02:49:54.062 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 02:49:54.063 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:49:54.063 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 02:49:54.063 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 02:49:54.063 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.28.22:6700) Recv POWERON CMD
2026-01-29 02:49:54.063 [INFO] ctrl_if_trx.py:109 (MS@172.18.28.22:6700) Starting transceiver...
2026-01-29 02:49:54.078 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD HANDOVER
2026-01-29 02:49:54.080 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.28.22:6700) Recv SETFH cmd
2026-01-29 02:49:54.080 [INFO] transceiver.py:201 (MS@172.18.28.22:6700) Frequency hopping configured: hsn=2, maio=0, ma_len=2
2026-01-29 02:49:54.080 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:49:54.080 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:49:54.081 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:49:54.083 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:49:54.084 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:49:54.084 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 02:49:54.084 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 02:49:54.084 [INFO] transceiver.py:205 (MS@172.18.28.22:6700) Frequency hopping disabled
2026-01-29 02:49:54.095 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 02:49:54.095 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 02:49:54.095 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 02:49:54.096 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:49:54.096 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 02:49:54.096 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 02:49:54.096 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.28.22:6700) Recv POWERON CMD
2026-01-29 02:49:54.096 [INFO] ctrl_if_trx.py:109 (MS@172.18.28.22:6700) Starting transceiver...
2026-01-29 02:49:54.128 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD HANDOVER
2026-01-29 02:49:54.133 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.28.22:6700) Recv SETFH cmd
2026-01-29 02:49:54.133 [INFO] transceiver.py:201 (MS@172.18.28.22:6700) Frequency hopping configured: hsn=3, maio=3, ma_len=4
2026-01-29 02:49:54.133 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:49:54.133 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:49:54.137 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:49:54.141 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:49:54.144 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:49:54.144 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 02:49:54.144 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 02:49:54.145 [INFO] transceiver.py:205 (MS@172.18.28.22:6700) Frequency hopping disabled
2026-01-29 02:49:54.165 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 02:49:54.165 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 02:49:54.165 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 02:49:54.166 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:49:54.166 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 02:49:54.166 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 02:49:54.166 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.28.22:6700) Recv POWERON CMD
2026-01-29 02:49:54.166 [INFO] ctrl_if_trx.py:109 (MS@172.18.28.22:6700) Starting transceiver...
2026-01-29 02:49:54.170 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:49:54.170 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD HANDOVER
2026-01-29 02:49:54.171 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 02:49:54.171 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 02:49:54.171 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:49:54.171 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:49:54.173 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:49:54.174 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:49:54.174 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:49:54.174 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 02:49:54.174 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 02:49:54.181 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 02:49:54.181 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 02:49:54.181 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 02:49:54.182 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:49:54.182 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 02:49:54.182 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 02:49:54.182 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.28.22:6700) Recv POWERON CMD
2026-01-29 02:49:54.182 [INFO] ctrl_if_trx.py:109 (MS@172.18.28.22:6700) Starting transceiver...
2026-01-29 02:49:54.226 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD HANDOVER
2026-01-29 02:49:54.230 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 02:49:54.230 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 02:49:54.230 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:49:54.231 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:49:54.239 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:49:54.242 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:49:54.245 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:49:54.245 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 02:49:54.246 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 02:49:54.262 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 02:49:54.263 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 02:49:54.263 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 02:49:54.264 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:49:54.264 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 02:49:54.264 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 02:49:54.264 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.28.22:6700) Recv POWERON CMD
2026-01-29 02:49:54.264 [INFO] ctrl_if_trx.py:109 (MS@172.18.28.22:6700) Starting transceiver...
2026-01-29 02:49:54.267 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:49:54.267 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD HANDOVER
2026-01-29 02:49:54.268 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 02:49:54.268 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 02:49:54.268 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:49:54.268 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:49:54.270 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:49:54.271 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:49:54.272 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:49:54.272 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 02:49:54.272 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 02:49:54.277 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 02:49:54.277 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 02:49:54.278 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 02:49:54.278 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:49:54.279 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 02:49:54.279 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 02:49:54.279 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.28.22:6700) Recv POWERON CMD
2026-01-29 02:49:54.279 [INFO] ctrl_if_trx.py:109 (MS@172.18.28.22:6700) Starting transceiver...
2026-01-29 02:49:54.320 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD HANDOVER
2026-01-29 02:49:54.325 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.28.22:6700) Recv SETFH cmd
2026-01-29 02:49:54.325 [INFO] transceiver.py:201 (MS@172.18.28.22:6700) Frequency hopping configured: hsn=5, maio=0, ma_len=4
2026-01-29 02:49:54.325 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:49:54.326 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:49:54.326 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:49:54.330 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:49:54.332 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:49:54.332 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 02:49:54.332 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 02:49:54.332 [INFO] transceiver.py:205 (MS@172.18.28.22:6700) Frequency hopping disabled
2026-01-29 02:49:54.348 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 02:49:54.348 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 02:49:54.348 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 02:49:54.349 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:49:54.349 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 02:49:54.349 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 02:49:54.349 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.28.22:6700) Recv POWERON CMD
2026-01-29 02:49:54.349 [INFO] ctrl_if_trx.py:109 (MS@172.18.28.22:6700) Starting transceiver...
2026-01-29 02:49:54.359 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD HANDOVER
2026-01-29 02:49:54.360 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.28.22:6700) Recv SETFH cmd
2026-01-29 02:49:54.360 [INFO] transceiver.py:201 (MS@172.18.28.22:6700) Frequency hopping configured: hsn=5, maio=0, ma_len=4
2026-01-29 02:49:54.360 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:49:54.360 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:49:54.372 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:49:54.373 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:49:54.374 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:49:54.375 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 02:49:54.375 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 02:49:54.375 [INFO] transceiver.py:205 (MS@172.18.28.22:6700) Frequency hopping disabled
2026-01-29 02:49:54.384 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 02:49:54.384 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 02:49:54.384 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 02:49:54.385 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:49:54.385 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 02:49:54.385 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 02:49:54.385 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.28.22:6700) Recv POWERON CMD
2026-01-29 02:49:54.385 [INFO] ctrl_if_trx.py:109 (MS@172.18.28.22:6700) Starting transceiver...
2026-01-29 02:49:54.407 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD HANDOVER
2026-01-29 02:49:54.410 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.28.22:6700) Recv SETFH cmd
2026-01-29 02:49:54.410 [INFO] transceiver.py:201 (MS@172.18.28.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2026-01-29 02:49:54.410 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:49:54.410 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:49:54.460 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-01-29 02:49:54.521 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:49:54.525 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:49:54.528 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:49:54.528 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 02:49:54.528 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 02:49:54.528 [INFO] transceiver.py:205 (MS@172.18.28.22:6700) Frequency hopping disabled
2026-01-29 02:49:54.548 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 02:49:54.548 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 02:49:54.548 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 02:49:54.549 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:49:54.549 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 02:49:54.549 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 02:49:54.549 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.28.22:6700) Recv POWERON CMD
2026-01-29 02:49:54.549 [INFO] ctrl_if_trx.py:109 (MS@172.18.28.22:6700) Starting transceiver...
2026-01-29 02:49:54.550 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:49:54.550 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 02:49:54.551 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:49:54.553 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:49:54.600 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD HANDOVER
2026-01-29 02:49:54.604 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.28.22:6700) Recv SETFH cmd
2026-01-29 02:49:54.604 [INFO] transceiver.py:201 (MS@172.18.28.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2026-01-29 02:49:54.605 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:49:54.605 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:49:54.775 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:49:54.778 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:49:54.781 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:49:54.782 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 02:49:54.782 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 02:49:54.782 [INFO] transceiver.py:205 (MS@172.18.28.22:6700) Frequency hopping disabled
2026-01-29 02:49:54.801 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 02:49:54.801 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 02:49:54.801 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 02:49:54.802 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:49:54.803 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 02:49:54.803 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 02:49:54.803 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.28.22:6700) Recv POWERON CMD
2026-01-29 02:49:54.803 [INFO] ctrl_if_trx.py:109 (MS@172.18.28.22:6700) Starting transceiver...
2026-01-29 02:49:54.837 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD HANDOVER
2026-01-29 02:49:54.841 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.28.22:6700) Recv SETFH cmd
2026-01-29 02:49:54.841 [INFO] transceiver.py:201 (MS@172.18.28.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2026-01-29 02:49:54.841 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:49:54.841 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:49:54.935 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-01-29 02:49:55.044 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:49:55.048 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:49:55.050 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:49:55.051 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 02:49:55.051 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 02:49:55.052 [INFO] transceiver.py:205 (MS@172.18.28.22:6700) Frequency hopping disabled
2026-01-29 02:49:55.067 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 02:49:55.067 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 02:49:55.067 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 02:49:55.068 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:49:55.068 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 02:49:55.068 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 02:49:55.068 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.28.22:6700) Recv POWERON CMD
2026-01-29 02:49:55.068 [INFO] ctrl_if_trx.py:109 (MS@172.18.28.22:6700) Starting transceiver...
2026-01-29 02:49:55.070 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD HANDOVER
2026-01-29 02:49:55.071 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.28.22:6700) Recv SETFH cmd
2026-01-29 02:49:55.071 [INFO] transceiver.py:201 (MS@172.18.28.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2026-01-29 02:49:55.071 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:49:55.071 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:49:55.287 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:49:55.292 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:49:55.295 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:49:55.295 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 02:49:55.295 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 02:49:55.295 [INFO] transceiver.py:205 (MS@172.18.28.22:6700) Frequency hopping disabled
2026-01-29 02:49:55.314 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 02:49:55.314 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 02:49:55.314 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 02:49:55.315 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:49:55.315 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 02:49:55.315 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 02:49:55.315 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.28.22:6700) Recv POWERON CMD
2026-01-29 02:49:55.315 [INFO] ctrl_if_trx.py:109 (MS@172.18.28.22:6700) Starting transceiver...
2026-01-29 02:49:55.359 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD HANDOVER
2026-01-29 02:49:55.365 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.28.22:6700) Recv SETFH cmd
2026-01-29 02:49:55.365 [INFO] transceiver.py:201 (MS@172.18.28.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2026-01-29 02:49:55.365 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:49:55.366 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:49:55.412 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-01-29 02:49:55.548 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:49:55.550 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 02:49:55.551 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:49:55.552 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:49:55.552 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:49:55.554 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:49:55.555 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:49:55.555 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 02:49:55.556 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 02:49:55.556 [INFO] transceiver.py:205 (MS@172.18.28.22:6700) Frequency hopping disabled
2026-01-29 02:49:55.573 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 02:49:55.573 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 02:49:55.573 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 02:49:55.574 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:49:55.574 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 02:49:55.574 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 02:49:55.574 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.28.22:6700) Recv POWERON CMD
2026-01-29 02:49:55.574 [INFO] ctrl_if_trx.py:109 (MS@172.18.28.22:6700) Starting transceiver...
2026-01-29 02:49:55.596 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD HANDOVER
2026-01-29 02:49:55.599 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.28.22:6700) Recv SETFH cmd
2026-01-29 02:49:55.599 [INFO] transceiver.py:201 (MS@172.18.28.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2026-01-29 02:49:55.599 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:49:55.599 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:49:55.801 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:49:55.805 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:49:55.808 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:49:55.808 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 02:49:55.809 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 02:49:55.809 [INFO] transceiver.py:205 (MS@172.18.28.22:6700) Frequency hopping disabled
2026-01-29 02:49:55.821 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 02:49:55.821 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 02:49:55.821 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 02:49:55.823 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:49:55.823 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 02:49:55.823 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 02:49:55.823 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.28.22:6700) Recv POWERON CMD
2026-01-29 02:49:55.823 [INFO] ctrl_if_trx.py:109 (MS@172.18.28.22:6700) Starting transceiver...
2026-01-29 02:49:55.829 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD HANDOVER
2026-01-29 02:49:55.830 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.28.22:6700) Recv SETFH cmd
2026-01-29 02:49:55.830 [INFO] transceiver.py:201 (MS@172.18.28.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2026-01-29 02:49:55.830 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:49:55.830 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:49:55.889 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-01-29 02:49:56.071 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:49:56.076 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:49:56.079 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:49:56.079 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 02:49:56.079 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 02:49:56.079 [INFO] transceiver.py:205 (MS@172.18.28.22:6700) Frequency hopping disabled
2026-01-29 02:49:56.099 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 02:49:56.099 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 02:49:56.099 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 02:49:56.100 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:49:56.100 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 02:49:56.100 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 02:49:56.100 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.28.22:6700) Recv POWERON CMD
2026-01-29 02:49:56.100 [INFO] ctrl_if_trx.py:109 (MS@172.18.28.22:6700) Starting transceiver...
2026-01-29 02:49:56.127 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD HANDOVER
2026-01-29 02:49:56.132 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.28.22:6700) Recv SETFH cmd
2026-01-29 02:49:56.132 [INFO] transceiver.py:201 (MS@172.18.28.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2026-01-29 02:49:56.133 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:49:56.133 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:49:56.315 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:49:56.319 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:49:56.321 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:49:56.322 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 02:49:56.322 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 02:49:56.322 [INFO] transceiver.py:205 (MS@172.18.28.22:6700) Frequency hopping disabled
2026-01-29 02:49:56.330 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 02:49:56.330 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:49:56.330 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:49:56.330 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:49:56.333 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 02:49:56.334 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:49:56.334 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:49:56.334 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:49:56.334 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.28.20:5700) Recv POWEROFF cmd
2026-01-29 02:49:56.334 [INFO] ctrl_if_trx.py:117 (BTS@172.18.28.20:5700) Stopping transceiver...
2026-01-29 02:49:56.334 [INFO] transceiver.py:246 Stopping clock generator
2026-01-29 02:49:56.335 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=811 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:49:56.335 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=811 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:49:56.335 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=811 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:49:56.335 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=811 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:49:56.335 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=811 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:49:56.335 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=811 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:49:56.335 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=811 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:49:56.336 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=812 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:49:56.336 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=812 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:49:56.336 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=812 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:49:56.336 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=812 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:49:56.336 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=812 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:49:56.336 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=812 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:49:56.336 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=812 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:49:56.336 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=812 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:50:01.334 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.28.20:5700) Recv POWEROFF cmd
2026-01-29 02:50:01.334 [INFO] ctrl_if_trx.py:117 (BTS@172.18.28.20:5700) Stopping transceiver...
2026-01-29 02:50:01.336 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:50:01.337 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:50:01.338 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:50:01.338 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 02:50:01.346 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 02:50:01.346 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.28.20:5700) Recv SETFORMAT cmd
2026-01-29 02:50:01.346 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.28.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:50:01.346 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.28.20:5700) Recv SETFORMAT cmd
2026-01-29 02:50:01.346 [INFO] ctrl_if_trx.py:201 (BTS@172.18.28.20:5700) TRXD header version 1 -> 1
2026-01-29 02:50:01.348 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.28.20:5700/1) Recv RXTUNE cmd
2026-01-29 02:50:01.348 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.28.20:5700/1) Recv TXTUNE cmd
2026-01-29 02:50:01.348 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.28.20:5700/1) Recv SETFORMAT cmd
2026-01-29 02:50:01.348 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.28.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:50:01.349 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:50:01.349 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.28.20:5700/1) Recv NOMTXPOWER cmd
2026-01-29 02:50:01.349 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.28.20:5700/1) Recv SETFORMAT cmd
2026-01-29 02:50:01.349 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.28.20:5700/1) TRXD header version 1 -> 1
2026-01-29 02:50:01.350 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.28.20:5700/2) Recv RXTUNE cmd
2026-01-29 02:50:01.350 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.28.20:5700/2) Recv TXTUNE cmd
2026-01-29 02:50:01.350 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.28.20:5700/2) Recv SETFORMAT cmd
2026-01-29 02:50:01.351 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.28.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:50:01.351 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:50:01.351 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.28.20:5700/2) Recv NOMTXPOWER cmd
2026-01-29 02:50:01.351 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.28.20:5700/2) Recv SETFORMAT cmd
2026-01-29 02:50:01.351 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.28.20:5700/2) TRXD header version 1 -> 1
2026-01-29 02:50:01.352 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.28.20:5700/3) Recv RXTUNE cmd
2026-01-29 02:50:01.352 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.28.20:5700/3) Recv TXTUNE cmd
2026-01-29 02:50:01.352 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.28.20:5700/3) Recv SETFORMAT cmd
2026-01-29 02:50:01.352 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.28.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:50:01.352 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:50:01.352 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.28.20:5700/3) Recv NOMTXPOWER cmd
2026-01-29 02:50:01.353 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.28.20:5700/3) Recv SETFORMAT cmd
2026-01-29 02:50:01.353 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.28.20:5700/3) TRXD header version 1 -> 1
2026-01-29 02:50:01.355 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.28.20:5700) Recv RXTUNE cmd
2026-01-29 02:50:01.355 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETTSC
2026-01-29 02:50:01.355 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETTSC
2026-01-29 02:50:01.355 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETTSC
2026-01-29 02:50:01.355 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.28.20:5700) Recv TXTUNE cmd
2026-01-29 02:50:01.355 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETRXGAIN
2026-01-29 02:50:01.355 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETRXGAIN
2026-01-29 02:50:01.355 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETRXGAIN
2026-01-29 02:50:01.355 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETTSC
2026-01-29 02:50:01.355 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:50:01.355 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:50:01.355 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:50:01.355 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.28.20:5700) Recv NOMTXPOWER cmd
2026-01-29 02:50:01.355 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:50:01.355 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:50:01.355 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:50:01.355 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.28.20:5700) Recv POWERON CMD
2026-01-29 02:50:01.355 [INFO] ctrl_if_trx.py:109 (BTS@172.18.28.20:5700) Starting transceiver...
2026-01-29 02:50:01.355 [INFO] transceiver.py:243 Starting clock generator
2026-01-29 02:50:01.355 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-01-29 02:50:01.355 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:50:01.355 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:50:01.355 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:50:01.356 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETRXGAIN
2026-01-29 02:50:01.356 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:50:01.356 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:50:01.356 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:50:01.356 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:50:01.356 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:50:01.356 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:50:01.356 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:50:01.356 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:50:01.356 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:50:01.356 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:50:01.356 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:50:01.356 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:50:01.356 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:50:01.356 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:50:01.356 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:50:01.356 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:50:01.356 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:50:01.356 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:50:01.356 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:50:01.356 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:50:01.356 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:50:01.356 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:50:01.356 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:50:01.360 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-01-29 02:50:01.837 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-01-29 02:50:01.869 [DEBUG] fake_trx.py:278 (BTS@172.18.28.20:5700) Recv FAKE_TOA cmd
2026-01-29 02:50:01.869 [DEBUG] fake_trx.py:297 (BTS@172.18.28.20:5700) Recv FAKE_RSSI cmd
2026-01-29 02:50:01.870 [DEBUG] fake_trx.py:322 (BTS@172.18.28.20:5700) Recv FAKE_CI cmd
2026-01-29 02:50:01.870 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:50:01.875 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 02:50:01.875 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 02:50:01.875 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 02:50:01.876 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:50:01.876 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 02:50:01.876 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 02:50:01.876 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.28.22:6700) Recv POWERON CMD
2026-01-29 02:50:01.876 [INFO] ctrl_if_trx.py:109 (MS@172.18.28.22:6700) Starting transceiver...
2026-01-29 02:50:01.881 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD HANDOVER
2026-01-29 02:50:01.882 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 02:50:01.882 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 02:50:01.882 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:50:01.882 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:50:01.934 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:50:02.306 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-01-29 02:50:02.358 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 02:50:02.358 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:50:02.358 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:50:02.360 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:50:02.783 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-01-29 02:50:03.262 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-01-29 02:50:03.359 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 02:50:03.359 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:50:03.359 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:50:03.360 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:50:03.740 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-01-29 02:50:03.937 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 02:50:03.937 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 02:50:03.940 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 02:50:03.940 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:50:03.941 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:50:03.941 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:50:03.944 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 02:50:03.944 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:50:03.944 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:50:03.944 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:50:03.944 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.28.20:5700) Recv POWEROFF cmd
2026-01-29 02:50:03.944 [INFO] ctrl_if_trx.py:117 (BTS@172.18.28.20:5700) Stopping transceiver...
2026-01-29 02:50:03.944 [INFO] transceiver.py:246 Stopping clock generator
2026-01-29 02:50:03.944 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=555 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:50:03.944 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=555 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:50:08.944 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.28.20:5700) Recv POWEROFF cmd
2026-01-29 02:50:08.944 [INFO] ctrl_if_trx.py:117 (BTS@172.18.28.20:5700) Stopping transceiver...
2026-01-29 02:50:08.946 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:50:08.947 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:50:08.948 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:50:08.948 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 02:50:08.955 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 02:50:08.955 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.28.20:5700) Recv SETFORMAT cmd
2026-01-29 02:50:08.955 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.28.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:50:08.956 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.28.20:5700) Recv SETFORMAT cmd
2026-01-29 02:50:08.956 [INFO] ctrl_if_trx.py:201 (BTS@172.18.28.20:5700) TRXD header version 1 -> 1
2026-01-29 02:50:08.958 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.28.20:5700/1) Recv RXTUNE cmd
2026-01-29 02:50:08.958 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.28.20:5700/1) Recv TXTUNE cmd
2026-01-29 02:50:08.958 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.28.20:5700/1) Recv SETFORMAT cmd
2026-01-29 02:50:08.959 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.28.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:50:08.959 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:50:08.959 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.28.20:5700/1) Recv NOMTXPOWER cmd
2026-01-29 02:50:08.959 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.28.20:5700/1) Recv SETFORMAT cmd
2026-01-29 02:50:08.959 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.28.20:5700/1) TRXD header version 1 -> 1
2026-01-29 02:50:08.961 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.28.20:5700/2) Recv RXTUNE cmd
2026-01-29 02:50:08.961 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.28.20:5700/2) Recv TXTUNE cmd
2026-01-29 02:50:08.961 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.28.20:5700/2) Recv SETFORMAT cmd
2026-01-29 02:50:08.961 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.28.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:50:08.961 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:50:08.962 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.28.20:5700/2) Recv NOMTXPOWER cmd
2026-01-29 02:50:08.962 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.28.20:5700/2) Recv SETFORMAT cmd
2026-01-29 02:50:08.962 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.28.20:5700/2) TRXD header version 1 -> 1
2026-01-29 02:50:08.964 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.28.20:5700/3) Recv RXTUNE cmd
2026-01-29 02:50:08.964 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.28.20:5700/3) Recv TXTUNE cmd
2026-01-29 02:50:08.964 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.28.20:5700/3) Recv SETFORMAT cmd
2026-01-29 02:50:08.964 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.28.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:50:08.964 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:50:08.964 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.28.20:5700/3) Recv NOMTXPOWER cmd
2026-01-29 02:50:08.964 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.28.20:5700/3) Recv SETFORMAT cmd
2026-01-29 02:50:08.964 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.28.20:5700/3) TRXD header version 1 -> 1
2026-01-29 02:50:08.966 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.28.20:5700) Recv RXTUNE cmd
2026-01-29 02:50:08.966 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETTSC
2026-01-29 02:50:08.966 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETTSC
2026-01-29 02:50:08.966 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETTSC
2026-01-29 02:50:08.967 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.28.20:5700) Recv TXTUNE cmd
2026-01-29 02:50:08.967 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETRXGAIN
2026-01-29 02:50:08.967 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETRXGAIN
2026-01-29 02:50:08.967 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETRXGAIN
2026-01-29 02:50:08.967 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETTSC
2026-01-29 02:50:08.967 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:50:08.967 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:50:08.967 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.28.20:5700) Recv NOMTXPOWER cmd
2026-01-29 02:50:08.967 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:50:08.967 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:50:08.967 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:50:08.967 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.28.20:5700) Recv POWERON CMD
2026-01-29 02:50:08.967 [INFO] ctrl_if_trx.py:109 (BTS@172.18.28.20:5700) Starting transceiver...
2026-01-29 02:50:08.967 [INFO] transceiver.py:243 Starting clock generator
2026-01-29 02:50:08.967 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-01-29 02:50:08.967 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:50:08.967 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:50:08.967 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:50:08.967 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETRXGAIN
2026-01-29 02:50:08.968 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:50:08.968 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:50:08.968 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:50:08.968 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:50:08.968 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:50:08.968 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:50:08.969 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:50:08.969 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:50:08.969 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:50:08.969 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:50:08.969 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:50:08.969 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:50:08.969 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:50:08.969 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:50:08.969 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:50:08.969 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:50:08.969 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:50:08.969 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:50:08.969 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:50:08.969 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:50:08.969 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:50:08.969 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:50:08.969 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:50:08.969 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:50:08.969 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 02:50:08.969 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:50:08.969 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.28.20:5700) Recv POWEROFF cmd
2026-01-29 02:50:08.969 [INFO] ctrl_if_trx.py:117 (BTS@172.18.28.20:5700) Stopping transceiver...
2026-01-29 02:50:08.969 [INFO] transceiver.py:246 Stopping clock generator
2026-01-29 02:50:08.969 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:50:13.972 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.28.20:5700) Recv POWEROFF cmd
2026-01-29 02:50:13.972 [INFO] ctrl_if_trx.py:117 (BTS@172.18.28.20:5700) Stopping transceiver...
2026-01-29 02:50:13.974 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:50:13.975 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:50:13.975 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:50:13.975 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 02:50:13.982 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 02:50:13.983 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.28.20:5700) Recv SETFORMAT cmd
2026-01-29 02:50:13.984 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.28.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:50:13.984 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.28.20:5700) Recv SETFORMAT cmd
2026-01-29 02:50:13.984 [INFO] ctrl_if_trx.py:201 (BTS@172.18.28.20:5700) TRXD header version 1 -> 1
2026-01-29 02:50:13.987 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.28.20:5700/1) Recv RXTUNE cmd
2026-01-29 02:50:13.987 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.28.20:5700/1) Recv TXTUNE cmd
2026-01-29 02:50:13.987 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.28.20:5700/1) Recv SETFORMAT cmd
2026-01-29 02:50:13.988 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.28.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:50:13.988 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:50:13.988 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.28.20:5700/1) Recv NOMTXPOWER cmd
2026-01-29 02:50:13.989 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.28.20:5700/1) Recv SETFORMAT cmd
2026-01-29 02:50:13.989 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.28.20:5700/1) TRXD header version 1 -> 1
2026-01-29 02:50:13.989 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.28.20:5700/2) Recv RXTUNE cmd
2026-01-29 02:50:13.989 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.28.20:5700/2) Recv TXTUNE cmd
2026-01-29 02:50:13.990 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.28.20:5700/2) Recv SETFORMAT cmd
2026-01-29 02:50:13.990 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.28.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:50:13.990 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:50:13.990 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.28.20:5700/2) Recv NOMTXPOWER cmd
2026-01-29 02:50:13.990 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.28.20:5700/2) Recv SETFORMAT cmd
2026-01-29 02:50:13.990 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.28.20:5700/2) TRXD header version 1 -> 1
2026-01-29 02:50:13.991 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.28.20:5700/3) Recv RXTUNE cmd
2026-01-29 02:50:13.991 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.28.20:5700/3) Recv TXTUNE cmd
2026-01-29 02:50:13.992 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.28.20:5700/3) Recv SETFORMAT cmd
2026-01-29 02:50:13.992 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.28.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:50:13.992 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:50:13.992 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.28.20:5700/3) Recv NOMTXPOWER cmd
2026-01-29 02:50:13.992 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.28.20:5700/3) Recv SETFORMAT cmd
2026-01-29 02:50:13.992 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.28.20:5700/3) TRXD header version 1 -> 1
2026-01-29 02:50:13.994 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.28.20:5700) Recv RXTUNE cmd
2026-01-29 02:50:13.994 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETTSC
2026-01-29 02:50:13.994 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETTSC
2026-01-29 02:50:13.994 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETTSC
2026-01-29 02:50:13.994 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.28.20:5700) Recv TXTUNE cmd
2026-01-29 02:50:13.994 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETRXGAIN
2026-01-29 02:50:13.994 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETRXGAIN
2026-01-29 02:50:13.994 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETRXGAIN
2026-01-29 02:50:13.994 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETTSC
2026-01-29 02:50:13.994 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:50:13.995 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:50:13.995 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:50:13.995 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.28.20:5700) Recv NOMTXPOWER cmd
2026-01-29 02:50:13.995 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:50:13.995 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:50:13.995 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:50:13.995 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.28.20:5700) Recv POWERON CMD
2026-01-29 02:50:13.995 [INFO] ctrl_if_trx.py:109 (BTS@172.18.28.20:5700) Starting transceiver...
2026-01-29 02:50:13.995 [INFO] transceiver.py:243 Starting clock generator
2026-01-29 02:50:13.995 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-01-29 02:50:13.995 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:50:13.995 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:50:13.995 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:50:13.995 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETRXGAIN
2026-01-29 02:50:13.995 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:50:13.995 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:50:13.995 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:50:13.995 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:50:13.995 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:50:13.995 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:50:13.995 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:50:13.995 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:50:13.995 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:50:13.995 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:50:13.995 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:50:13.996 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:50:13.996 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:50:13.996 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:50:13.996 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:50:13.996 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:50:13.996 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:50:13.996 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:50:13.996 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:50:13.996 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:50:13.996 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:50:13.996 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:50:13.996 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:50:14.000 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-01-29 02:50:14.484 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-01-29 02:50:14.525 [DEBUG] fake_trx.py:278 (BTS@172.18.28.20:5700) Recv FAKE_TOA cmd
2026-01-29 02:50:14.527 [DEBUG] fake_trx.py:297 (BTS@172.18.28.20:5700) Recv FAKE_RSSI cmd
2026-01-29 02:50:14.527 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:50:14.528 [DEBUG] fake_trx.py:322 (BTS@172.18.28.20:5700) Recv FAKE_CI cmd
2026-01-29 02:50:14.963 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-01-29 02:50:14.998 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:50:14.998 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 02:50:14.999 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:50:15.002 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:50:15.445 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-01-29 02:50:15.926 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-01-29 02:50:15.999 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 02:50:16.000 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:50:16.000 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:50:16.004 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:50:16.407 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-01-29 02:50:16.886 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-01-29 02:50:17.000 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:50:17.001 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 02:50:17.001 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:50:17.005 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:50:17.354 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-01-29 02:50:17.823 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-01-29 02:50:18.001 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:50:18.001 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 02:50:18.001 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:50:18.005 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:50:18.293 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-01-29 02:50:18.761 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-01-29 02:50:19.002 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:50:19.002 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 02:50:19.002 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:50:19.006 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:50:19.234 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-01-29 02:50:19.716 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-01-29 02:50:20.014 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 02:50:20.014 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:50:20.014 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:50:20.014 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:50:20.016 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 02:50:20.016 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:50:20.016 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:50:20.016 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.28.20:5700) Recv POWEROFF cmd
2026-01-29 02:50:20.016 [INFO] ctrl_if_trx.py:117 (BTS@172.18.28.20:5700) Stopping transceiver...
2026-01-29 02:50:20.017 [INFO] transceiver.py:246 Stopping clock generator
2026-01-29 02:50:20.017 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:50:20.017 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=1290 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:50:20.017 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=1290 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:50:20.017 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=1290 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:50:20.017 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=1290 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:50:20.017 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=1290 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:50:20.017 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=1290 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:50:20.017 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=1290 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:50:20.017 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=1290 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:50:20.017 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=1291 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:50:20.017 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=1291 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:50:20.017 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=1291 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:50:20.017 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=1291 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:50:20.017 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=1291 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:50:20.017 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=1291 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:50:20.017 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=1291 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:50:20.017 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=1291 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:50:25.018 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.28.20:5700) Recv POWEROFF cmd
2026-01-29 02:50:25.018 [INFO] ctrl_if_trx.py:117 (BTS@172.18.28.20:5700) Stopping transceiver...
2026-01-29 02:50:25.022 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:50:25.022 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:50:25.022 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 02:50:25.022 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:50:25.031 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 02:50:25.033 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.28.20:5700) Recv SETFORMAT cmd
2026-01-29 02:50:25.033 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.28.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:50:25.034 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.28.20:5700) Recv SETFORMAT cmd
2026-01-29 02:50:25.034 [INFO] ctrl_if_trx.py:201 (BTS@172.18.28.20:5700) TRXD header version 1 -> 1
2026-01-29 02:50:25.037 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.28.20:5700/1) Recv RXTUNE cmd
2026-01-29 02:50:25.038 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.28.20:5700/1) Recv TXTUNE cmd
2026-01-29 02:50:25.038 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.28.20:5700/1) Recv SETFORMAT cmd
2026-01-29 02:50:25.038 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.28.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:50:25.038 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:50:25.039 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.28.20:5700/1) Recv NOMTXPOWER cmd
2026-01-29 02:50:25.039 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.28.20:5700/1) Recv SETFORMAT cmd
2026-01-29 02:50:25.039 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.28.20:5700/1) TRXD header version 1 -> 1
2026-01-29 02:50:25.041 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.28.20:5700/2) Recv RXTUNE cmd
2026-01-29 02:50:25.041 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.28.20:5700/2) Recv TXTUNE cmd
2026-01-29 02:50:25.042 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.28.20:5700/2) Recv SETFORMAT cmd
2026-01-29 02:50:25.042 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.28.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:50:25.042 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:50:25.042 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.28.20:5700/2) Recv NOMTXPOWER cmd
2026-01-29 02:50:25.042 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.28.20:5700/2) Recv SETFORMAT cmd
2026-01-29 02:50:25.042 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.28.20:5700/2) TRXD header version 1 -> 1
2026-01-29 02:50:25.045 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.28.20:5700/3) Recv RXTUNE cmd
2026-01-29 02:50:25.045 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.28.20:5700/3) Recv TXTUNE cmd
2026-01-29 02:50:25.045 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.28.20:5700/3) Recv SETFORMAT cmd
2026-01-29 02:50:25.045 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.28.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:50:25.045 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:50:25.046 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.28.20:5700/3) Recv NOMTXPOWER cmd
2026-01-29 02:50:25.046 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.28.20:5700/3) Recv SETFORMAT cmd
2026-01-29 02:50:25.046 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.28.20:5700/3) TRXD header version 1 -> 1
2026-01-29 02:50:25.049 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.28.20:5700) Recv RXTUNE cmd
2026-01-29 02:50:25.049 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETTSC
2026-01-29 02:50:25.049 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETTSC
2026-01-29 02:50:25.049 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETTSC
2026-01-29 02:50:25.049 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.28.20:5700) Recv TXTUNE cmd
2026-01-29 02:50:25.049 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETRXGAIN
2026-01-29 02:50:25.049 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETRXGAIN
2026-01-29 02:50:25.049 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETRXGAIN
2026-01-29 02:50:25.049 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETTSC
2026-01-29 02:50:25.049 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:50:25.049 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:50:25.049 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:50:25.049 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.28.20:5700) Recv NOMTXPOWER cmd
2026-01-29 02:50:25.050 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:50:25.050 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:50:25.050 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:50:25.050 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.28.20:5700) Recv POWERON CMD
2026-01-29 02:50:25.050 [INFO] ctrl_if_trx.py:109 (BTS@172.18.28.20:5700) Starting transceiver...
2026-01-29 02:50:25.050 [INFO] transceiver.py:243 Starting clock generator
2026-01-29 02:50:25.050 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-01-29 02:50:25.050 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:50:25.050 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:50:25.050 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:50:25.050 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETRXGAIN
2026-01-29 02:50:25.050 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:50:25.050 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:50:25.050 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:50:25.050 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:50:25.051 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:50:25.051 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:50:25.051 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:50:25.051 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:50:25.051 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:50:25.051 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:50:25.051 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:50:25.051 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:50:25.051 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:50:25.051 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:50:25.051 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:50:25.051 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:50:25.051 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:50:25.051 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:50:25.051 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:50:25.051 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:50:25.051 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:50:25.051 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:50:25.051 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:50:25.055 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-01-29 02:50:25.539 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-01-29 02:50:25.585 [DEBUG] fake_trx.py:278 (BTS@172.18.28.20:5700) Recv FAKE_TOA cmd
2026-01-29 02:50:25.587 [DEBUG] fake_trx.py:297 (BTS@172.18.28.20:5700) Recv FAKE_RSSI cmd
2026-01-29 02:50:25.590 [DEBUG] fake_trx.py:322 (BTS@172.18.28.20:5700) Recv FAKE_CI cmd
2026-01-29 02:50:25.590 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:50:26.020 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-01-29 02:50:26.053 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 02:50:26.053 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:50:26.056 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:50:26.060 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:50:26.501 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-01-29 02:50:26.982 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-01-29 02:50:27.054 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 02:50:27.054 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:50:27.057 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:50:27.061 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:50:27.464 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-01-29 02:50:27.945 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-01-29 02:50:28.055 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 02:50:28.055 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:50:28.058 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:50:28.062 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:50:28.423 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-01-29 02:50:28.901 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-01-29 02:50:29.057 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 02:50:29.057 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:50:29.059 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:50:29.064 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:50:29.382 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-01-29 02:50:29.863 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-01-29 02:50:30.059 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:50:30.059 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 02:50:30.061 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:50:30.065 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:50:30.345 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-01-29 02:50:30.601 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 02:50:30.601 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:50:30.601 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:50:30.601 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:50:30.603 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 02:50:30.603 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:50:30.603 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:50:30.603 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.28.20:5700) Recv POWEROFF cmd
2026-01-29 02:50:30.603 [INFO] ctrl_if_trx.py:117 (BTS@172.18.28.20:5700) Stopping transceiver...
2026-01-29 02:50:30.603 [INFO] transceiver.py:246 Stopping clock generator
2026-01-29 02:50:30.603 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:50:30.603 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=1179 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:50:30.603 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=1179 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:50:30.603 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=1179 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:50:30.603 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=1179 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:50:30.603 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=1179 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:50:30.603 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=1179 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:50:30.603 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=1179 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:50:30.603 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=1179 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:50:35.604 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.28.20:5700) Recv POWEROFF cmd
2026-01-29 02:50:35.604 [INFO] ctrl_if_trx.py:117 (BTS@172.18.28.20:5700) Stopping transceiver...
2026-01-29 02:50:35.606 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:50:35.607 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:50:35.607 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:50:35.608 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 02:50:35.617 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 02:50:35.619 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.28.20:5700) Recv SETFORMAT cmd
2026-01-29 02:50:35.619 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.28.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:50:35.620 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.28.20:5700) Recv SETFORMAT cmd
2026-01-29 02:50:35.620 [INFO] ctrl_if_trx.py:201 (BTS@172.18.28.20:5700) TRXD header version 1 -> 1
2026-01-29 02:50:35.625 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.28.20:5700/1) Recv RXTUNE cmd
2026-01-29 02:50:35.625 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.28.20:5700/1) Recv TXTUNE cmd
2026-01-29 02:50:35.626 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.28.20:5700/1) Recv SETFORMAT cmd
2026-01-29 02:50:35.626 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.28.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:50:35.626 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:50:35.627 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.28.20:5700/1) Recv NOMTXPOWER cmd
2026-01-29 02:50:35.627 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.28.20:5700/1) Recv SETFORMAT cmd
2026-01-29 02:50:35.627 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.28.20:5700/1) TRXD header version 1 -> 1
2026-01-29 02:50:35.628 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.28.20:5700/2) Recv RXTUNE cmd
2026-01-29 02:50:35.629 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.28.20:5700/2) Recv TXTUNE cmd
2026-01-29 02:50:35.629 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.28.20:5700/2) Recv SETFORMAT cmd
2026-01-29 02:50:35.629 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.28.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:50:35.629 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:50:35.630 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.28.20:5700/2) Recv NOMTXPOWER cmd
2026-01-29 02:50:35.630 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.28.20:5700/2) Recv SETFORMAT cmd
2026-01-29 02:50:35.630 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.28.20:5700/2) TRXD header version 1 -> 1
2026-01-29 02:50:35.631 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.28.20:5700/3) Recv RXTUNE cmd
2026-01-29 02:50:35.631 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.28.20:5700/3) Recv TXTUNE cmd
2026-01-29 02:50:35.631 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.28.20:5700/3) Recv SETFORMAT cmd
2026-01-29 02:50:35.631 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.28.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:50:35.631 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:50:35.631 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.28.20:5700/3) Recv NOMTXPOWER cmd
2026-01-29 02:50:35.632 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.28.20:5700/3) Recv SETFORMAT cmd
2026-01-29 02:50:35.632 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.28.20:5700/3) TRXD header version 1 -> 1
2026-01-29 02:50:35.634 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.28.20:5700) Recv RXTUNE cmd
2026-01-29 02:50:35.634 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETTSC
2026-01-29 02:50:35.634 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETTSC
2026-01-29 02:50:35.634 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETTSC
2026-01-29 02:50:35.634 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.28.20:5700) Recv TXTUNE cmd
2026-01-29 02:50:35.634 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETRXGAIN
2026-01-29 02:50:35.634 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETRXGAIN
2026-01-29 02:50:35.634 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETRXGAIN
2026-01-29 02:50:35.635 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETTSC
2026-01-29 02:50:35.635 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:50:35.635 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:50:35.635 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.28.20:5700) Recv NOMTXPOWER cmd
2026-01-29 02:50:35.635 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:50:35.635 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:50:35.635 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:50:35.635 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.28.20:5700) Recv POWERON CMD
2026-01-29 02:50:35.635 [INFO] ctrl_if_trx.py:109 (BTS@172.18.28.20:5700) Starting transceiver...
2026-01-29 02:50:35.635 [INFO] transceiver.py:243 Starting clock generator
2026-01-29 02:50:35.635 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-01-29 02:50:35.635 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:50:35.635 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:50:35.635 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:50:35.635 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETRXGAIN
2026-01-29 02:50:35.636 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:50:35.636 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:50:35.636 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:50:35.636 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:50:35.636 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:50:35.636 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:50:35.636 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:50:35.636 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:50:35.636 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:50:35.636 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:50:35.636 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:50:35.636 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:50:35.636 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:50:35.636 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:50:35.636 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:50:35.637 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:50:35.637 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:50:35.637 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:50:35.637 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:50:35.637 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:50:35.637 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:50:35.637 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:50:35.637 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:50:35.637 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:50:35.637 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 02:50:35.637 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:50:35.637 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.28.20:5700) Recv POWEROFF cmd
2026-01-29 02:50:35.637 [INFO] ctrl_if_trx.py:117 (BTS@172.18.28.20:5700) Stopping transceiver...
2026-01-29 02:50:35.637 [INFO] transceiver.py:246 Stopping clock generator
2026-01-29 02:50:35.637 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:50:35.637 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:50:40.640 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.28.20:5700) Recv POWEROFF cmd
2026-01-29 02:50:40.640 [INFO] ctrl_if_trx.py:117 (BTS@172.18.28.20:5700) Stopping transceiver...
2026-01-29 02:50:40.642 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:50:40.644 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:50:40.644 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:50:40.644 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 02:50:40.654 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 02:50:40.656 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.28.20:5700) Recv SETFORMAT cmd
2026-01-29 02:50:40.656 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.28.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:50:40.657 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.28.20:5700) Recv SETFORMAT cmd
2026-01-29 02:50:40.657 [INFO] ctrl_if_trx.py:201 (BTS@172.18.28.20:5700) TRXD header version 1 -> 1
2026-01-29 02:50:40.661 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.28.20:5700/1) Recv RXTUNE cmd
2026-01-29 02:50:40.662 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.28.20:5700/1) Recv TXTUNE cmd
2026-01-29 02:50:40.662 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.28.20:5700/1) Recv SETFORMAT cmd
2026-01-29 02:50:40.662 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.28.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:50:40.663 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:50:40.663 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.28.20:5700/1) Recv NOMTXPOWER cmd
2026-01-29 02:50:40.664 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.28.20:5700/1) Recv SETFORMAT cmd
2026-01-29 02:50:40.664 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.28.20:5700/1) TRXD header version 1 -> 1
2026-01-29 02:50:40.665 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.28.20:5700/2) Recv RXTUNE cmd
2026-01-29 02:50:40.665 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.28.20:5700/2) Recv TXTUNE cmd
2026-01-29 02:50:40.666 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.28.20:5700/2) Recv SETFORMAT cmd
2026-01-29 02:50:40.666 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.28.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:50:40.666 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:50:40.666 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.28.20:5700/2) Recv NOMTXPOWER cmd
2026-01-29 02:50:40.667 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.28.20:5700/2) Recv SETFORMAT cmd
2026-01-29 02:50:40.667 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.28.20:5700/2) TRXD header version 1 -> 1
2026-01-29 02:50:40.668 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.28.20:5700/3) Recv RXTUNE cmd
2026-01-29 02:50:40.668 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.28.20:5700/3) Recv TXTUNE cmd
2026-01-29 02:50:40.668 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.28.20:5700/3) Recv SETFORMAT cmd
2026-01-29 02:50:40.668 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.28.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:50:40.668 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:50:40.668 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.28.20:5700/3) Recv NOMTXPOWER cmd
2026-01-29 02:50:40.668 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.28.20:5700/3) Recv SETFORMAT cmd
2026-01-29 02:50:40.668 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.28.20:5700/3) TRXD header version 1 -> 1
2026-01-29 02:50:40.671 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.28.20:5700) Recv RXTUNE cmd
2026-01-29 02:50:40.671 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETTSC
2026-01-29 02:50:40.671 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETTSC
2026-01-29 02:50:40.671 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETTSC
2026-01-29 02:50:40.671 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.28.20:5700) Recv TXTUNE cmd
2026-01-29 02:50:40.671 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETRXGAIN
2026-01-29 02:50:40.672 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETRXGAIN
2026-01-29 02:50:40.672 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETRXGAIN
2026-01-29 02:50:40.672 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETTSC
2026-01-29 02:50:40.672 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:50:40.672 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:50:40.672 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.28.20:5700) Recv NOMTXPOWER cmd
2026-01-29 02:50:40.672 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:50:40.672 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:50:40.672 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:50:40.672 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.28.20:5700) Recv POWERON CMD
2026-01-29 02:50:40.672 [INFO] ctrl_if_trx.py:109 (BTS@172.18.28.20:5700) Starting transceiver...
2026-01-29 02:50:40.672 [INFO] transceiver.py:243 Starting clock generator
2026-01-29 02:50:40.672 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-01-29 02:50:40.672 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:50:40.672 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:50:40.672 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:50:40.672 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETRXGAIN
2026-01-29 02:50:40.672 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:50:40.673 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:50:40.673 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:50:40.673 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:50:40.673 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:50:40.673 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:50:40.673 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:50:40.673 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:50:40.673 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:50:40.673 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:50:40.673 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:50:40.673 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:50:40.673 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:50:40.673 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:50:40.673 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:50:40.673 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:50:40.673 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:50:40.673 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:50:40.673 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:50:40.673 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:50:40.673 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:50:40.673 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:50:40.673 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:50:40.673 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:50:40.677 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-01-29 02:50:41.158 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-01-29 02:50:41.198 [DEBUG] fake_trx.py:278 (BTS@172.18.28.20:5700) Recv FAKE_TOA cmd
2026-01-29 02:50:41.199 [DEBUG] fake_trx.py:297 (BTS@172.18.28.20:5700) Recv FAKE_RSSI cmd
2026-01-29 02:50:41.200 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:50:41.200 [DEBUG] fake_trx.py:322 (BTS@172.18.28.20:5700) Recv FAKE_CI cmd
2026-01-29 02:50:41.201 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 02:50:41.201 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 02:50:41.202 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 02:50:41.628 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-01-29 02:50:41.675 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 02:50:41.675 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:50:41.676 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:50:41.679 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:50:42.096 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-01-29 02:50:42.203 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:50:42.203 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 02:50:42.203 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 02:50:42.203 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.28.22:6700) Recv POWERON CMD
2026-01-29 02:50:42.204 [INFO] ctrl_if_trx.py:109 (MS@172.18.28.22:6700) Starting transceiver...
2026-01-29 02:50:42.570 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-01-29 02:50:42.676 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:50:42.677 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:50:42.677 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 02:50:42.680 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:50:43.048 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-01-29 02:50:43.526 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-01-29 02:50:43.677 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:50:43.678 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 02:50:43.678 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:50:43.681 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:50:44.003 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-01-29 02:50:44.481 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-01-29 02:50:44.678 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 02:50:44.679 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:50:44.679 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:50:44.682 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:50:44.959 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-01-29 02:50:45.438 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-01-29 02:50:45.679 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 02:50:45.679 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:50:45.679 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:50:45.683 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:50:45.915 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-01-29 02:50:46.394 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-01-29 02:50:46.872 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-01-29 02:50:47.344 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-01-29 02:50:47.815 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-01-29 02:50:48.286 [DEBUG] clck_gen.py:113 IND CLOCK 1632
2026-01-29 02:50:48.761 [DEBUG] clck_gen.py:113 IND CLOCK 1734
2026-01-29 02:50:49.233 [DEBUG] clck_gen.py:113 IND CLOCK 1836
2026-01-29 02:50:49.704 [DEBUG] clck_gen.py:113 IND CLOCK 1938
2026-01-29 02:50:50.177 [DEBUG] clck_gen.py:113 IND CLOCK 2040
2026-01-29 02:50:50.655 [DEBUG] clck_gen.py:113 IND CLOCK 2142
2026-01-29 02:50:51.129 [DEBUG] clck_gen.py:113 IND CLOCK 2244
2026-01-29 02:50:51.607 [DEBUG] clck_gen.py:113 IND CLOCK 2346
2026-01-29 02:50:52.086 [DEBUG] clck_gen.py:113 IND CLOCK 2448
2026-01-29 02:50:52.564 [DEBUG] clck_gen.py:113 IND CLOCK 2550
2026-01-29 02:50:53.042 [DEBUG] clck_gen.py:113 IND CLOCK 2652
2026-01-29 02:50:53.518 [DEBUG] clck_gen.py:113 IND CLOCK 2754
2026-01-29 02:50:53.996 [DEBUG] clck_gen.py:113 IND CLOCK 2856
2026-01-29 02:50:54.474 [DEBUG] clck_gen.py:113 IND CLOCK 2958
2026-01-29 02:50:54.952 [DEBUG] clck_gen.py:113 IND CLOCK 3060
2026-01-29 02:50:55.430 [DEBUG] clck_gen.py:113 IND CLOCK 3162
2026-01-29 02:50:55.908 [DEBUG] clck_gen.py:113 IND CLOCK 3264
2026-01-29 02:50:56.039 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 02:50:56.039 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 02:50:56.040 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 02:50:56.040 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:50:56.040 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:50:56.040 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:50:56.041 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 02:50:56.041 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:50:56.041 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:50:56.041 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:50:56.041 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.28.20:5700) Recv POWEROFF cmd
2026-01-29 02:50:56.041 [INFO] ctrl_if_trx.py:117 (BTS@172.18.28.20:5700) Stopping transceiver...
2026-01-29 02:50:56.041 [INFO] transceiver.py:246 Stopping clock generator
2026-01-29 02:51:01.044 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.28.20:5700) Recv POWEROFF cmd
2026-01-29 02:51:01.044 [INFO] ctrl_if_trx.py:117 (BTS@172.18.28.20:5700) Stopping transceiver...
2026-01-29 02:51:01.045 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:51:01.048 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:51:01.048 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:51:01.048 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 02:51:01.058 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 02:51:01.059 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.28.20:5700) Recv SETFORMAT cmd
2026-01-29 02:51:01.060 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.28.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:51:01.060 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.28.20:5700) Recv SETFORMAT cmd
2026-01-29 02:51:01.060 [INFO] ctrl_if_trx.py:201 (BTS@172.18.28.20:5700) TRXD header version 1 -> 1
2026-01-29 02:51:01.063 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.28.20:5700/1) Recv RXTUNE cmd
2026-01-29 02:51:01.063 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.28.20:5700/1) Recv TXTUNE cmd
2026-01-29 02:51:01.064 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.28.20:5700/1) Recv SETFORMAT cmd
2026-01-29 02:51:01.064 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.28.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:51:01.064 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:51:01.065 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.28.20:5700/1) Recv NOMTXPOWER cmd
2026-01-29 02:51:01.065 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.28.20:5700/1) Recv SETFORMAT cmd
2026-01-29 02:51:01.065 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.28.20:5700/1) TRXD header version 1 -> 1
2026-01-29 02:51:01.066 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.28.20:5700/2) Recv RXTUNE cmd
2026-01-29 02:51:01.067 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.28.20:5700/2) Recv TXTUNE cmd
2026-01-29 02:51:01.067 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.28.20:5700/2) Recv SETFORMAT cmd
2026-01-29 02:51:01.067 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.28.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:51:01.067 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:51:01.068 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.28.20:5700/2) Recv NOMTXPOWER cmd
2026-01-29 02:51:01.068 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.28.20:5700/2) Recv SETFORMAT cmd
2026-01-29 02:51:01.068 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.28.20:5700/2) TRXD header version 1 -> 1
2026-01-29 02:51:01.069 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.28.20:5700/3) Recv RXTUNE cmd
2026-01-29 02:51:01.069 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.28.20:5700/3) Recv TXTUNE cmd
2026-01-29 02:51:01.069 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.28.20:5700/3) Recv SETFORMAT cmd
2026-01-29 02:51:01.069 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.28.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:51:01.070 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:51:01.070 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.28.20:5700/3) Recv NOMTXPOWER cmd
2026-01-29 02:51:01.070 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.28.20:5700/3) Recv SETFORMAT cmd
2026-01-29 02:51:01.070 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.28.20:5700/3) TRXD header version 1 -> 1
2026-01-29 02:51:01.073 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.28.20:5700) Recv RXTUNE cmd
2026-01-29 02:51:01.073 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETTSC
2026-01-29 02:51:01.073 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETTSC
2026-01-29 02:51:01.073 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETTSC
2026-01-29 02:51:01.073 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.28.20:5700) Recv TXTUNE cmd
2026-01-29 02:51:01.073 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETRXGAIN
2026-01-29 02:51:01.073 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETRXGAIN
2026-01-29 02:51:01.073 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETRXGAIN
2026-01-29 02:51:01.073 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETTSC
2026-01-29 02:51:01.073 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:51:01.073 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:51:01.073 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.28.20:5700) Recv NOMTXPOWER cmd
2026-01-29 02:51:01.073 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:51:01.073 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:51:01.073 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:51:01.073 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.28.20:5700) Recv POWERON CMD
2026-01-29 02:51:01.073 [INFO] ctrl_if_trx.py:109 (BTS@172.18.28.20:5700) Starting transceiver...
2026-01-29 02:51:01.073 [INFO] transceiver.py:243 Starting clock generator
2026-01-29 02:51:01.074 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-01-29 02:51:01.074 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:51:01.074 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:51:01.074 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:51:01.074 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETRXGAIN
2026-01-29 02:51:01.074 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:51:01.074 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:51:01.074 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:51:01.074 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:51:01.074 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:51:01.074 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:51:01.074 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:51:01.074 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:51:01.074 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:51:01.074 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:51:01.074 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:51:01.074 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:51:01.075 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:51:01.075 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:51:01.075 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:51:01.075 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:51:01.075 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:51:01.075 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:51:01.075 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:51:01.075 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:51:01.075 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:51:01.075 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:51:01.075 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:51:01.075 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:51:01.079 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-01-29 02:51:01.564 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-01-29 02:51:01.600 [DEBUG] fake_trx.py:278 (BTS@172.18.28.20:5700) Recv FAKE_TOA cmd
2026-01-29 02:51:01.601 [DEBUG] fake_trx.py:297 (BTS@172.18.28.20:5700) Recv FAKE_RSSI cmd
2026-01-29 02:51:01.602 [DEBUG] fake_trx.py:322 (BTS@172.18.28.20:5700) Recv FAKE_CI cmd
2026-01-29 02:51:01.602 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:51:01.617 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 02:51:01.618 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 02:51:01.618 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 02:51:01.624 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:51:01.624 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 02:51:01.624 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 02:51:01.624 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.28.22:6700) Recv POWERON CMD
2026-01-29 02:51:01.624 [INFO] ctrl_if_trx.py:109 (MS@172.18.28.22:6700) Starting transceiver...
2026-01-29 02:51:01.656 [DEBUG] fake_trx.py:297 (BTS@172.18.28.20:5700) Recv FAKE_RSSI cmd
2026-01-29 02:51:01.660 [DEBUG] fake_trx.py:278 (BTS@172.18.28.20:5700) Recv FAKE_TOA cmd
2026-01-29 02:51:01.667 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:51:01.672 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 02:51:01.673 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 02:51:01.673 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:51:01.674 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:51:02.042 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-01-29 02:51:02.077 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:51:02.077 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 02:51:02.079 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:51:02.082 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:51:02.520 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-01-29 02:51:02.543 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 02:51:02.543 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 02:51:02.547 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 02:51:02.547 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:51:02.547 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:51:02.547 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:51:02.550 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 02:51:02.550 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:51:02.550 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:51:02.551 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.28.20:5700) Recv POWEROFF cmd
2026-01-29 02:51:02.551 [INFO] ctrl_if_trx.py:117 (BTS@172.18.28.20:5700) Stopping transceiver...
2026-01-29 02:51:02.551 [INFO] transceiver.py:246 Stopping clock generator
2026-01-29 02:51:02.551 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:51:02.551 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=314 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:51:02.551 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=314 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:51:02.552 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=314 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:51:02.552 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=314 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:51:02.552 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=314 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:51:02.552 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=314 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:51:02.552 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=314 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:51:07.550 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.28.20:5700) Recv POWEROFF cmd
2026-01-29 02:51:07.550 [INFO] ctrl_if_trx.py:117 (BTS@172.18.28.20:5700) Stopping transceiver...
2026-01-29 02:51:07.553 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:51:07.553 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:51:07.553 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 02:51:07.553 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:51:07.561 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 02:51:07.561 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.28.20:5700) Recv SETFORMAT cmd
2026-01-29 02:51:07.561 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.28.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:51:07.562 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.28.20:5700) Recv SETFORMAT cmd
2026-01-29 02:51:07.562 [INFO] ctrl_if_trx.py:201 (BTS@172.18.28.20:5700) TRXD header version 1 -> 1
2026-01-29 02:51:07.565 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.28.20:5700/1) Recv RXTUNE cmd
2026-01-29 02:51:07.566 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.28.20:5700/1) Recv TXTUNE cmd
2026-01-29 02:51:07.566 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.28.20:5700/1) Recv SETFORMAT cmd
2026-01-29 02:51:07.566 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.28.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:51:07.567 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:51:07.567 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.28.20:5700/1) Recv NOMTXPOWER cmd
2026-01-29 02:51:07.568 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.28.20:5700/1) Recv SETFORMAT cmd
2026-01-29 02:51:07.568 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.28.20:5700/1) TRXD header version 1 -> 1
2026-01-29 02:51:07.569 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.28.20:5700/2) Recv RXTUNE cmd
2026-01-29 02:51:07.569 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.28.20:5700/2) Recv TXTUNE cmd
2026-01-29 02:51:07.569 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.28.20:5700/2) Recv SETFORMAT cmd
2026-01-29 02:51:07.569 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.28.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:51:07.570 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:51:07.570 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.28.20:5700/2) Recv NOMTXPOWER cmd
2026-01-29 02:51:07.570 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.28.20:5700/2) Recv SETFORMAT cmd
2026-01-29 02:51:07.570 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.28.20:5700/2) TRXD header version 1 -> 1
2026-01-29 02:51:07.572 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.28.20:5700/3) Recv RXTUNE cmd
2026-01-29 02:51:07.572 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.28.20:5700/3) Recv TXTUNE cmd
2026-01-29 02:51:07.572 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.28.20:5700/3) Recv SETFORMAT cmd
2026-01-29 02:51:07.572 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.28.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:51:07.572 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:51:07.572 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.28.20:5700/3) Recv NOMTXPOWER cmd
2026-01-29 02:51:07.573 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.28.20:5700/3) Recv SETFORMAT cmd
2026-01-29 02:51:07.573 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.28.20:5700/3) TRXD header version 1 -> 1
2026-01-29 02:51:07.575 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.28.20:5700) Recv RXTUNE cmd
2026-01-29 02:51:07.575 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETTSC
2026-01-29 02:51:07.575 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETTSC
2026-01-29 02:51:07.575 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETTSC
2026-01-29 02:51:07.575 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.28.20:5700) Recv TXTUNE cmd
2026-01-29 02:51:07.575 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETRXGAIN
2026-01-29 02:51:07.575 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETRXGAIN
2026-01-29 02:51:07.575 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETRXGAIN
2026-01-29 02:51:07.575 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETTSC
2026-01-29 02:51:07.576 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:51:07.576 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:51:07.576 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.28.20:5700) Recv NOMTXPOWER cmd
2026-01-29 02:51:07.576 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:51:07.576 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:51:07.576 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:51:07.576 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.28.20:5700) Recv POWERON CMD
2026-01-29 02:51:07.576 [INFO] ctrl_if_trx.py:109 (BTS@172.18.28.20:5700) Starting transceiver...
2026-01-29 02:51:07.576 [INFO] transceiver.py:243 Starting clock generator
2026-01-29 02:51:07.576 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-01-29 02:51:07.576 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:51:07.576 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:51:07.576 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:51:07.576 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETRXGAIN
2026-01-29 02:51:07.576 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:51:07.576 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:51:07.576 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:51:07.576 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:51:07.576 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:51:07.577 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:51:07.577 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:51:07.577 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:51:07.577 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:51:07.577 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:51:07.577 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:51:07.577 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:51:07.577 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:51:07.577 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:51:07.577 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:51:07.577 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:51:07.577 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:51:07.577 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:51:07.577 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:51:07.577 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:51:07.577 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:51:07.577 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:51:07.577 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:51:07.577 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:51:07.581 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-01-29 02:51:08.065 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-01-29 02:51:08.102 [DEBUG] fake_trx.py:278 (BTS@172.18.28.20:5700) Recv FAKE_TOA cmd
2026-01-29 02:51:08.105 [DEBUG] fake_trx.py:297 (BTS@172.18.28.20:5700) Recv FAKE_RSSI cmd
2026-01-29 02:51:08.106 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:51:08.107 [DEBUG] fake_trx.py:322 (BTS@172.18.28.20:5700) Recv FAKE_CI cmd
2026-01-29 02:51:08.130 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 02:51:08.130 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 02:51:08.131 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 02:51:08.136 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:51:08.136 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 02:51:08.137 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 02:51:08.137 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.28.22:6700) Recv POWERON CMD
2026-01-29 02:51:08.137 [INFO] ctrl_if_trx.py:109 (MS@172.18.28.22:6700) Starting transceiver...
2026-01-29 02:51:08.158 [DEBUG] fake_trx.py:297 (BTS@172.18.28.20:5700) Recv FAKE_RSSI cmd
2026-01-29 02:51:08.161 [DEBUG] fake_trx.py:278 (BTS@172.18.28.20:5700) Recv FAKE_TOA cmd
2026-01-29 02:51:08.167 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:51:08.171 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 02:51:08.172 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 02:51:08.172 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:51:08.172 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:51:08.542 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-01-29 02:51:08.579 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 02:51:08.579 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:51:08.580 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:51:08.583 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:51:09.020 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-01-29 02:51:09.044 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 02:51:09.044 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 02:51:09.048 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 02:51:09.048 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:51:09.048 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:51:09.048 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:51:09.052 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 02:51:09.052 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:51:09.052 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:51:09.052 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:51:09.053 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.28.20:5700) Recv POWEROFF cmd
2026-01-29 02:51:09.053 [INFO] ctrl_if_trx.py:117 (BTS@172.18.28.20:5700) Stopping transceiver...
2026-01-29 02:51:09.053 [INFO] transceiver.py:246 Stopping clock generator
2026-01-29 02:51:09.053 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=314 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:51:09.053 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=314 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:51:09.053 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=314 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:51:09.053 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=314 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:51:09.054 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=314 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:51:09.054 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=314 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:51:09.054 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=315 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:51:09.054 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=315 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:51:09.054 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=315 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:51:09.054 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=315 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:51:09.054 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=315 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:51:09.054 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=315 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:51:09.054 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=315 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:51:09.054 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=315 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:51:14.052 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.28.20:5700) Recv POWEROFF cmd
2026-01-29 02:51:14.052 [INFO] ctrl_if_trx.py:117 (BTS@172.18.28.20:5700) Stopping transceiver...
2026-01-29 02:51:14.054 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:51:14.055 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:51:14.056 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:51:14.056 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 02:51:14.066 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 02:51:14.066 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.28.20:5700) Recv SETFORMAT cmd
2026-01-29 02:51:14.066 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.28.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:51:14.067 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.28.20:5700) Recv SETFORMAT cmd
2026-01-29 02:51:14.067 [INFO] ctrl_if_trx.py:201 (BTS@172.18.28.20:5700) TRXD header version 1 -> 1
2026-01-29 02:51:14.068 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.28.20:5700/1) Recv RXTUNE cmd
2026-01-29 02:51:14.068 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.28.20:5700/1) Recv TXTUNE cmd
2026-01-29 02:51:14.069 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.28.20:5700/1) Recv SETFORMAT cmd
2026-01-29 02:51:14.069 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.28.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:51:14.069 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:51:14.069 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.28.20:5700/1) Recv NOMTXPOWER cmd
2026-01-29 02:51:14.069 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.28.20:5700/1) Recv SETFORMAT cmd
2026-01-29 02:51:14.069 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.28.20:5700/1) TRXD header version 1 -> 1
2026-01-29 02:51:14.070 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.28.20:5700/2) Recv RXTUNE cmd
2026-01-29 02:51:14.070 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.28.20:5700/2) Recv TXTUNE cmd
2026-01-29 02:51:14.070 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.28.20:5700/2) Recv SETFORMAT cmd
2026-01-29 02:51:14.070 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.28.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:51:14.070 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:51:14.070 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.28.20:5700/2) Recv NOMTXPOWER cmd
2026-01-29 02:51:14.070 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.28.20:5700/2) Recv SETFORMAT cmd
2026-01-29 02:51:14.070 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.28.20:5700/2) TRXD header version 1 -> 1
2026-01-29 02:51:14.072 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.28.20:5700/3) Recv RXTUNE cmd
2026-01-29 02:51:14.072 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.28.20:5700/3) Recv TXTUNE cmd
2026-01-29 02:51:14.072 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.28.20:5700/3) Recv SETFORMAT cmd
2026-01-29 02:51:14.072 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.28.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:51:14.072 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:51:14.072 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.28.20:5700/3) Recv NOMTXPOWER cmd
2026-01-29 02:51:14.072 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.28.20:5700/3) Recv SETFORMAT cmd
2026-01-29 02:51:14.072 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.28.20:5700/3) TRXD header version 1 -> 1
2026-01-29 02:51:14.073 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.28.20:5700) Recv RXTUNE cmd
2026-01-29 02:51:14.073 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETTSC
2026-01-29 02:51:14.073 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETTSC
2026-01-29 02:51:14.073 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETTSC
2026-01-29 02:51:14.073 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.28.20:5700) Recv TXTUNE cmd
2026-01-29 02:51:14.073 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETRXGAIN
2026-01-29 02:51:14.073 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETRXGAIN
2026-01-29 02:51:14.073 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETRXGAIN
2026-01-29 02:51:14.073 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETTSC
2026-01-29 02:51:14.073 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:51:14.073 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:51:14.073 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:51:14.073 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.28.20:5700) Recv NOMTXPOWER cmd
2026-01-29 02:51:14.074 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:51:14.074 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:51:14.074 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:51:14.074 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.28.20:5700) Recv POWERON CMD
2026-01-29 02:51:14.074 [INFO] ctrl_if_trx.py:109 (BTS@172.18.28.20:5700) Starting transceiver...
2026-01-29 02:51:14.074 [INFO] transceiver.py:243 Starting clock generator
2026-01-29 02:51:14.074 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-01-29 02:51:14.074 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:51:14.074 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:51:14.074 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:51:14.074 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETRXGAIN
2026-01-29 02:51:14.074 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:51:14.074 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:51:14.074 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:51:14.074 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:51:14.074 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:51:14.074 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:51:14.074 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:51:14.074 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:51:14.074 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:51:14.074 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:51:14.074 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:51:14.074 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:51:14.074 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:51:14.074 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:51:14.074 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:51:14.074 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:51:14.074 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:51:14.074 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:51:14.074 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:51:14.074 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:51:14.074 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:51:14.074 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:51:14.074 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:51:14.078 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-01-29 02:51:14.562 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-01-29 02:51:14.592 [DEBUG] fake_trx.py:278 (BTS@172.18.28.20:5700) Recv FAKE_TOA cmd
2026-01-29 02:51:14.594 [DEBUG] fake_trx.py:297 (BTS@172.18.28.20:5700) Recv FAKE_RSSI cmd
2026-01-29 02:51:14.595 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:51:14.595 [DEBUG] fake_trx.py:322 (BTS@172.18.28.20:5700) Recv FAKE_CI cmd
2026-01-29 02:51:14.621 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 02:51:14.622 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 02:51:14.622 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 02:51:14.627 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:51:14.627 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 02:51:14.628 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 02:51:14.628 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.28.22:6700) Recv POWERON CMD
2026-01-29 02:51:14.628 [INFO] ctrl_if_trx.py:109 (MS@172.18.28.22:6700) Starting transceiver...
2026-01-29 02:51:14.654 [DEBUG] fake_trx.py:297 (BTS@172.18.28.20:5700) Recv FAKE_RSSI cmd
2026-01-29 02:51:14.658 [DEBUG] fake_trx.py:278 (BTS@172.18.28.20:5700) Recv FAKE_TOA cmd
2026-01-29 02:51:14.667 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:51:14.674 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.28.22:6700) Recv SETFH cmd
2026-01-29 02:51:14.674 [INFO] transceiver.py:201 (MS@172.18.28.22:6700) Frequency hopping configured: hsn=5, maio=0, ma_len=4
2026-01-29 02:51:14.674 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:51:14.675 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:51:15.040 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-01-29 02:51:15.076 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:51:15.076 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 02:51:15.076 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:51:15.078 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:51:15.519 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-01-29 02:51:15.740 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 02:51:15.740 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 02:51:15.740 [INFO] transceiver.py:205 (MS@172.18.28.22:6700) Frequency hopping disabled
2026-01-29 02:51:15.740 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 02:51:15.741 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:51:15.741 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:51:15.741 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:51:15.743 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 02:51:15.743 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:51:15.743 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:51:15.743 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:51:15.743 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.28.20:5700) Recv POWEROFF cmd
2026-01-29 02:51:15.743 [INFO] ctrl_if_trx.py:117 (BTS@172.18.28.20:5700) Stopping transceiver...
2026-01-29 02:51:15.743 [INFO] transceiver.py:246 Stopping clock generator
2026-01-29 02:51:15.743 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=352 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:51:15.744 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=352 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:51:15.744 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=352 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:51:15.744 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=352 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:51:15.744 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=352 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:51:15.744 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=352 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:51:15.744 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=353 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:51:15.744 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=353 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:51:15.744 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=353 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:51:15.744 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=353 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:51:15.744 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=353 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:51:15.744 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=353 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:51:15.744 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=353 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:51:15.744 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=353 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:51:15.744 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=354 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:51:15.744 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=354 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:51:15.744 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=354 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:51:15.744 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=354 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:51:15.744 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=354 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:51:15.744 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=354 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:51:15.744 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=354 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:51:15.744 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=354 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:51:15.744 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=355 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:51:15.745 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=355 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:51:15.745 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=355 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:51:15.745 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=355 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:51:15.745 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=355 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:51:15.745 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=355 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:51:15.745 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=355 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:51:15.745 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=355 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:51:15.745 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=356 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:51:15.745 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=356 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:51:15.745 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=356 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:51:15.745 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=356 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:51:15.745 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=356 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:51:15.745 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=356 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:51:15.745 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=356 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:51:15.745 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=356 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:51:20.774 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.28.20:5700) Recv POWEROFF cmd
2026-01-29 02:51:20.774 [INFO] ctrl_if_trx.py:117 (BTS@172.18.28.20:5700) Stopping transceiver...
2026-01-29 02:51:20.776 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:51:20.777 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:51:20.778 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:51:20.779 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 02:51:20.792 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 02:51:20.794 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.28.20:5700) Recv SETFORMAT cmd
2026-01-29 02:51:20.794 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.28.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:51:20.795 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.28.20:5700) Recv SETFORMAT cmd
2026-01-29 02:51:20.795 [INFO] ctrl_if_trx.py:201 (BTS@172.18.28.20:5700) TRXD header version 1 -> 1
2026-01-29 02:51:20.801 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.28.20:5700/1) Recv RXTUNE cmd
2026-01-29 02:51:20.801 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.28.20:5700/1) Recv TXTUNE cmd
2026-01-29 02:51:20.802 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.28.20:5700/1) Recv SETFORMAT cmd
2026-01-29 02:51:20.802 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.28.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:51:20.802 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:51:20.803 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.28.20:5700/1) Recv NOMTXPOWER cmd
2026-01-29 02:51:20.803 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.28.20:5700/1) Recv SETFORMAT cmd
2026-01-29 02:51:20.803 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.28.20:5700/1) TRXD header version 1 -> 1
2026-01-29 02:51:20.804 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.28.20:5700/2) Recv RXTUNE cmd
2026-01-29 02:51:20.805 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.28.20:5700/2) Recv TXTUNE cmd
2026-01-29 02:51:20.805 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.28.20:5700/2) Recv SETFORMAT cmd
2026-01-29 02:51:20.805 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.28.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:51:20.805 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:51:20.806 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.28.20:5700/2) Recv NOMTXPOWER cmd
2026-01-29 02:51:20.806 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.28.20:5700/2) Recv SETFORMAT cmd
2026-01-29 02:51:20.806 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.28.20:5700/2) TRXD header version 1 -> 1
2026-01-29 02:51:20.807 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.28.20:5700/3) Recv RXTUNE cmd
2026-01-29 02:51:20.807 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.28.20:5700/3) Recv TXTUNE cmd
2026-01-29 02:51:20.808 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.28.20:5700/3) Recv SETFORMAT cmd
2026-01-29 02:51:20.808 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.28.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:51:20.808 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:51:20.808 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.28.20:5700/3) Recv NOMTXPOWER cmd
2026-01-29 02:51:20.808 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.28.20:5700/3) Recv SETFORMAT cmd
2026-01-29 02:51:20.808 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.28.20:5700/3) TRXD header version 1 -> 1
2026-01-29 02:51:20.811 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.28.20:5700) Recv RXTUNE cmd
2026-01-29 02:51:20.811 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETTSC
2026-01-29 02:51:20.811 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETTSC
2026-01-29 02:51:20.811 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETTSC
2026-01-29 02:51:20.811 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.28.20:5700) Recv TXTUNE cmd
2026-01-29 02:51:20.811 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETRXGAIN
2026-01-29 02:51:20.811 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETRXGAIN
2026-01-29 02:51:20.811 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETRXGAIN
2026-01-29 02:51:20.811 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETTSC
2026-01-29 02:51:20.811 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:51:20.811 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:51:20.811 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.28.20:5700) Recv NOMTXPOWER cmd
2026-01-29 02:51:20.811 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:51:20.811 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:51:20.811 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:51:20.812 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.28.20:5700) Recv POWERON CMD
2026-01-29 02:51:20.812 [INFO] ctrl_if_trx.py:109 (BTS@172.18.28.20:5700) Starting transceiver...
2026-01-29 02:51:20.812 [INFO] transceiver.py:243 Starting clock generator
2026-01-29 02:51:20.812 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-01-29 02:51:20.812 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:51:20.812 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:51:20.812 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:51:20.812 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETRXGAIN
2026-01-29 02:51:20.812 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:51:20.812 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:51:20.812 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:51:20.812 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:51:20.812 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:51:20.812 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:51:20.813 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:51:20.813 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:51:20.813 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:51:20.813 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:51:20.813 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:51:20.813 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:51:20.813 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:51:20.813 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:51:20.813 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:51:20.813 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:51:20.813 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:51:20.813 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:51:20.813 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:51:20.813 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:51:20.813 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:51:20.813 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:51:20.813 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:51:20.813 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:51:20.817 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-01-29 02:51:21.300 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-01-29 02:51:21.337 [DEBUG] fake_trx.py:278 (BTS@172.18.28.20:5700) Recv FAKE_TOA cmd
2026-01-29 02:51:21.339 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:51:21.339 [DEBUG] fake_trx.py:297 (BTS@172.18.28.20:5700) Recv FAKE_RSSI cmd
2026-01-29 02:51:21.340 [DEBUG] fake_trx.py:322 (BTS@172.18.28.20:5700) Recv FAKE_CI cmd
2026-01-29 02:51:21.355 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 02:51:21.356 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 02:51:21.356 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 02:51:21.361 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:51:21.361 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 02:51:21.361 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 02:51:21.361 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.28.22:6700) Recv POWERON CMD
2026-01-29 02:51:21.361 [INFO] ctrl_if_trx.py:109 (MS@172.18.28.22:6700) Starting transceiver...
2026-01-29 02:51:21.392 [DEBUG] fake_trx.py:297 (BTS@172.18.28.20:5700) Recv FAKE_RSSI cmd
2026-01-29 02:51:21.395 [DEBUG] fake_trx.py:278 (BTS@172.18.28.20:5700) Recv FAKE_TOA cmd
2026-01-29 02:51:21.399 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:51:21.401 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.28.22:6700) Recv SETFH cmd
2026-01-29 02:51:21.401 [INFO] transceiver.py:201 (MS@172.18.28.22:6700) Frequency hopping configured: hsn=5, maio=0, ma_len=4
2026-01-29 02:51:21.401 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:51:21.401 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:51:21.776 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-01-29 02:51:21.814 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 02:51:21.815 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:51:21.815 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:51:21.817 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:51:22.255 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-01-29 02:51:22.457 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 02:51:22.457 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 02:51:22.457 [INFO] transceiver.py:205 (MS@172.18.28.22:6700) Frequency hopping disabled
2026-01-29 02:51:22.461 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 02:51:22.461 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:51:22.461 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:51:22.461 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:51:22.465 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 02:51:22.465 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:51:22.465 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:51:22.465 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:51:22.465 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.28.20:5700) Recv POWEROFF cmd
2026-01-29 02:51:22.465 [INFO] ctrl_if_trx.py:117 (BTS@172.18.28.20:5700) Stopping transceiver...
2026-01-29 02:51:22.466 [INFO] transceiver.py:246 Stopping clock generator
2026-01-29 02:51:22.466 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=353 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:51:22.466 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=353 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:51:22.466 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=353 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:51:22.467 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=353 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:51:22.467 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=353 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:51:22.467 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=353 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:51:27.466 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.28.20:5700) Recv POWEROFF cmd
2026-01-29 02:51:27.466 [INFO] ctrl_if_trx.py:117 (BTS@172.18.28.20:5700) Stopping transceiver...
2026-01-29 02:51:27.466 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:51:27.466 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:51:27.466 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:51:27.466 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 02:51:27.470 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 02:51:27.472 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.28.20:5700) Recv SETFORMAT cmd
2026-01-29 02:51:27.472 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.28.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:51:27.472 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.28.20:5700) Recv SETFORMAT cmd
2026-01-29 02:51:27.473 [INFO] ctrl_if_trx.py:201 (BTS@172.18.28.20:5700) TRXD header version 1 -> 1
2026-01-29 02:51:27.478 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.28.20:5700/1) Recv RXTUNE cmd
2026-01-29 02:51:27.478 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.28.20:5700/1) Recv TXTUNE cmd
2026-01-29 02:51:27.478 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.28.20:5700/1) Recv SETFORMAT cmd
2026-01-29 02:51:27.478 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.28.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:51:27.479 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:51:27.479 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.28.20:5700/1) Recv NOMTXPOWER cmd
2026-01-29 02:51:27.479 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.28.20:5700/1) Recv SETFORMAT cmd
2026-01-29 02:51:27.479 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.28.20:5700/1) TRXD header version 1 -> 1
2026-01-29 02:51:27.482 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.28.20:5700/2) Recv RXTUNE cmd
2026-01-29 02:51:27.482 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.28.20:5700/2) Recv TXTUNE cmd
2026-01-29 02:51:27.482 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.28.20:5700/2) Recv SETFORMAT cmd
2026-01-29 02:51:27.482 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.28.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:51:27.483 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:51:27.483 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.28.20:5700/2) Recv NOMTXPOWER cmd
2026-01-29 02:51:27.483 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.28.20:5700/2) Recv SETFORMAT cmd
2026-01-29 02:51:27.483 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.28.20:5700/2) TRXD header version 1 -> 1
2026-01-29 02:51:27.486 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.28.20:5700/3) Recv RXTUNE cmd
2026-01-29 02:51:27.486 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.28.20:5700/3) Recv TXTUNE cmd
2026-01-29 02:51:27.486 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.28.20:5700/3) Recv SETFORMAT cmd
2026-01-29 02:51:27.486 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.28.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:51:27.486 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:51:27.486 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.28.20:5700/3) Recv NOMTXPOWER cmd
2026-01-29 02:51:27.486 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.28.20:5700/3) Recv SETFORMAT cmd
2026-01-29 02:51:27.486 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.28.20:5700/3) TRXD header version 1 -> 1
2026-01-29 02:51:27.490 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.28.20:5700) Recv RXTUNE cmd
2026-01-29 02:51:27.490 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETTSC
2026-01-29 02:51:27.490 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETTSC
2026-01-29 02:51:27.490 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETTSC
2026-01-29 02:51:27.490 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.28.20:5700) Recv TXTUNE cmd
2026-01-29 02:51:27.490 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETRXGAIN
2026-01-29 02:51:27.490 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETRXGAIN
2026-01-29 02:51:27.490 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETRXGAIN
2026-01-29 02:51:27.490 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETTSC
2026-01-29 02:51:27.490 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:51:27.491 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:51:27.491 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:51:27.491 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.28.20:5700) Recv NOMTXPOWER cmd
2026-01-29 02:51:27.491 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:51:27.491 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:51:27.491 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:51:27.491 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.28.20:5700) Recv POWERON CMD
2026-01-29 02:51:27.491 [INFO] ctrl_if_trx.py:109 (BTS@172.18.28.20:5700) Starting transceiver...
2026-01-29 02:51:27.491 [INFO] transceiver.py:243 Starting clock generator
2026-01-29 02:51:27.491 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-01-29 02:51:27.491 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:51:27.491 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:51:27.491 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:51:27.491 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETRXGAIN
2026-01-29 02:51:27.491 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:51:27.492 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:51:27.492 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:51:27.492 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:51:27.492 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:51:27.492 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:51:27.492 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:51:27.492 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:51:27.492 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:51:27.492 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:51:27.492 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:51:27.492 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:51:27.492 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:51:27.492 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:51:27.492 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:51:27.492 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:51:27.492 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:51:27.492 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:51:27.492 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:51:27.492 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:51:27.493 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:51:27.493 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:51:27.493 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:51:27.496 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-01-29 02:51:27.980 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-01-29 02:51:28.026 [DEBUG] fake_trx.py:278 (BTS@172.18.28.20:5700) Recv FAKE_TOA cmd
2026-01-29 02:51:28.028 [DEBUG] fake_trx.py:297 (BTS@172.18.28.20:5700) Recv FAKE_RSSI cmd
2026-01-29 02:51:28.029 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:51:28.030 [DEBUG] fake_trx.py:322 (BTS@172.18.28.20:5700) Recv FAKE_CI cmd
2026-01-29 02:51:28.054 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 02:51:28.054 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 02:51:28.054 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 02:51:28.059 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:51:28.059 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 02:51:28.059 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 02:51:28.060 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.28.22:6700) Recv POWERON CMD
2026-01-29 02:51:28.060 [INFO] ctrl_if_trx.py:109 (MS@172.18.28.22:6700) Starting transceiver...
2026-01-29 02:51:28.072 [DEBUG] fake_trx.py:297 (BTS@172.18.28.20:5700) Recv FAKE_RSSI cmd
2026-01-29 02:51:28.075 [DEBUG] fake_trx.py:278 (BTS@172.18.28.20:5700) Recv FAKE_TOA cmd
2026-01-29 02:51:28.079 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:51:28.083 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.28.22:6700) Recv SETFH cmd
2026-01-29 02:51:28.083 [INFO] transceiver.py:201 (MS@172.18.28.22:6700) Frequency hopping configured: hsn=5, maio=0, ma_len=4
2026-01-29 02:51:28.083 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:51:28.083 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:51:28.458 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-01-29 02:51:28.495 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:51:28.495 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 02:51:28.496 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:51:28.501 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:51:28.936 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-01-29 02:51:29.139 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 02:51:29.139 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 02:51:29.139 [INFO] transceiver.py:205 (MS@172.18.28.22:6700) Frequency hopping disabled
2026-01-29 02:51:29.143 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 02:51:29.143 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:51:29.143 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:51:29.143 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:51:29.144 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 02:51:29.144 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:51:29.144 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:51:29.144 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:51:29.144 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.28.20:5700) Recv POWEROFF cmd
2026-01-29 02:51:29.144 [INFO] ctrl_if_trx.py:117 (BTS@172.18.28.20:5700) Stopping transceiver...
2026-01-29 02:51:29.144 [INFO] transceiver.py:246 Stopping clock generator
2026-01-29 02:51:34.146 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.28.20:5700) Recv POWEROFF cmd
2026-01-29 02:51:34.146 [INFO] ctrl_if_trx.py:117 (BTS@172.18.28.20:5700) Stopping transceiver...
2026-01-29 02:51:34.150 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:51:34.150 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:51:34.150 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 02:51:34.150 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:51:34.159 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 02:51:34.161 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.28.20:5700) Recv SETFORMAT cmd
2026-01-29 02:51:34.161 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.28.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:51:34.161 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.28.20:5700) Recv SETFORMAT cmd
2026-01-29 02:51:34.162 [INFO] ctrl_if_trx.py:201 (BTS@172.18.28.20:5700) TRXD header version 1 -> 1
2026-01-29 02:51:34.166 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.28.20:5700/1) Recv RXTUNE cmd
2026-01-29 02:51:34.166 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.28.20:5700/1) Recv TXTUNE cmd
2026-01-29 02:51:34.167 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.28.20:5700/1) Recv SETFORMAT cmd
2026-01-29 02:51:34.167 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.28.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:51:34.167 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:51:34.167 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.28.20:5700/1) Recv NOMTXPOWER cmd
2026-01-29 02:51:34.168 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.28.20:5700/1) Recv SETFORMAT cmd
2026-01-29 02:51:34.168 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.28.20:5700/1) TRXD header version 1 -> 1
2026-01-29 02:51:34.169 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.28.20:5700/2) Recv RXTUNE cmd
2026-01-29 02:51:34.170 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.28.20:5700/2) Recv TXTUNE cmd
2026-01-29 02:51:34.170 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.28.20:5700/2) Recv SETFORMAT cmd
2026-01-29 02:51:34.170 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.28.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:51:34.170 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:51:34.170 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.28.20:5700/2) Recv NOMTXPOWER cmd
2026-01-29 02:51:34.170 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.28.20:5700/2) Recv SETFORMAT cmd
2026-01-29 02:51:34.170 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.28.20:5700/2) TRXD header version 1 -> 1
2026-01-29 02:51:34.172 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.28.20:5700/3) Recv RXTUNE cmd
2026-01-29 02:51:34.172 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.28.20:5700/3) Recv TXTUNE cmd
2026-01-29 02:51:34.173 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.28.20:5700/3) Recv SETFORMAT cmd
2026-01-29 02:51:34.173 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.28.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:51:34.173 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:51:34.173 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.28.20:5700/3) Recv NOMTXPOWER cmd
2026-01-29 02:51:34.173 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.28.20:5700/3) Recv SETFORMAT cmd
2026-01-29 02:51:34.173 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.28.20:5700/3) TRXD header version 1 -> 1
2026-01-29 02:51:34.176 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.28.20:5700) Recv RXTUNE cmd
2026-01-29 02:51:34.176 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETTSC
2026-01-29 02:51:34.176 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETTSC
2026-01-29 02:51:34.176 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETTSC
2026-01-29 02:51:34.176 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.28.20:5700) Recv TXTUNE cmd
2026-01-29 02:51:34.176 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETRXGAIN
2026-01-29 02:51:34.176 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETRXGAIN
2026-01-29 02:51:34.176 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETRXGAIN
2026-01-29 02:51:34.176 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETTSC
2026-01-29 02:51:34.176 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:51:34.176 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:51:34.176 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:51:34.176 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.28.20:5700) Recv NOMTXPOWER cmd
2026-01-29 02:51:34.176 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:51:34.176 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:51:34.176 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:51:34.176 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.28.20:5700) Recv POWERON CMD
2026-01-29 02:51:34.176 [INFO] ctrl_if_trx.py:109 (BTS@172.18.28.20:5700) Starting transceiver...
2026-01-29 02:51:34.176 [INFO] transceiver.py:243 Starting clock generator
2026-01-29 02:51:34.176 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-01-29 02:51:34.177 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:51:34.177 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:51:34.177 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:51:34.177 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETRXGAIN
2026-01-29 02:51:34.177 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:51:34.177 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:51:34.177 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:51:34.177 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:51:34.177 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:51:34.177 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:51:34.177 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:51:34.177 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:51:34.177 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:51:34.177 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:51:34.177 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:51:34.177 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:51:34.177 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:51:34.177 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:51:34.177 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:51:34.177 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:51:34.178 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:51:34.178 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:51:34.178 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:51:34.178 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:51:34.178 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:51:34.178 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:51:34.178 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:51:34.181 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-01-29 02:51:34.665 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-01-29 02:51:34.700 [DEBUG] fake_trx.py:278 (BTS@172.18.28.20:5700) Recv FAKE_TOA cmd
2026-01-29 02:51:34.702 [DEBUG] fake_trx.py:297 (BTS@172.18.28.20:5700) Recv FAKE_RSSI cmd
2026-01-29 02:51:34.703 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:51:34.703 [DEBUG] fake_trx.py:322 (BTS@172.18.28.20:5700) Recv FAKE_CI cmd
2026-01-29 02:51:34.720 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 02:51:34.720 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 02:51:34.720 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 02:51:34.726 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:51:34.726 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 02:51:34.726 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 02:51:34.726 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.28.22:6700) Recv POWERON CMD
2026-01-29 02:51:34.727 [INFO] ctrl_if_trx.py:109 (MS@172.18.28.22:6700) Starting transceiver...
2026-01-29 02:51:34.758 [DEBUG] fake_trx.py:297 (BTS@172.18.28.20:5700) Recv FAKE_RSSI cmd
2026-01-29 02:51:34.762 [DEBUG] fake_trx.py:278 (BTS@172.18.28.20:5700) Recv FAKE_TOA cmd
2026-01-29 02:51:34.769 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:51:34.774 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 02:51:34.774 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 02:51:34.774 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:51:34.774 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:51:35.143 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-01-29 02:51:35.179 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 02:51:35.180 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:51:35.181 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:51:35.184 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:51:35.621 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-01-29 02:51:35.644 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 02:51:35.644 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 02:51:35.648 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 02:51:35.648 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:51:35.648 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:51:35.648 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:51:35.651 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 02:51:35.651 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:51:35.651 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:51:35.651 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:51:35.651 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.28.20:5700) Recv POWEROFF cmd
2026-01-29 02:51:35.651 [INFO] ctrl_if_trx.py:117 (BTS@172.18.28.20:5700) Stopping transceiver...
2026-01-29 02:51:35.651 [INFO] transceiver.py:246 Stopping clock generator
2026-01-29 02:51:35.651 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=313 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:51:35.651 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=314 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:51:35.652 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=314 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:51:35.652 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=314 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:51:35.652 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=314 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:51:35.652 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=314 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:51:35.652 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=314 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:51:35.652 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=314 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:51:35.652 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=314 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:51:40.654 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.28.20:5700) Recv POWEROFF cmd
2026-01-29 02:51:40.654 [INFO] ctrl_if_trx.py:117 (BTS@172.18.28.20:5700) Stopping transceiver...
2026-01-29 02:51:40.654 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:51:40.654 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:51:40.654 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 02:51:40.654 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:51:40.663 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 02:51:40.665 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.28.20:5700) Recv SETFORMAT cmd
2026-01-29 02:51:40.665 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.28.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:51:40.666 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.28.20:5700) Recv SETFORMAT cmd
2026-01-29 02:51:40.666 [INFO] ctrl_if_trx.py:201 (BTS@172.18.28.20:5700) TRXD header version 1 -> 1
2026-01-29 02:51:40.670 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.28.20:5700/1) Recv RXTUNE cmd
2026-01-29 02:51:40.670 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.28.20:5700/1) Recv TXTUNE cmd
2026-01-29 02:51:40.670 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.28.20:5700/1) Recv SETFORMAT cmd
2026-01-29 02:51:40.671 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.28.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:51:40.671 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:51:40.671 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.28.20:5700/1) Recv NOMTXPOWER cmd
2026-01-29 02:51:40.672 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.28.20:5700/1) Recv SETFORMAT cmd
2026-01-29 02:51:40.672 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.28.20:5700/1) TRXD header version 1 -> 1
2026-01-29 02:51:40.673 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.28.20:5700/2) Recv RXTUNE cmd
2026-01-29 02:51:40.674 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.28.20:5700/2) Recv TXTUNE cmd
2026-01-29 02:51:40.674 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.28.20:5700/2) Recv SETFORMAT cmd
2026-01-29 02:51:40.674 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.28.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:51:40.674 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:51:40.675 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.28.20:5700/2) Recv NOMTXPOWER cmd
2026-01-29 02:51:40.675 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.28.20:5700/2) Recv SETFORMAT cmd
2026-01-29 02:51:40.675 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.28.20:5700/2) TRXD header version 1 -> 1
2026-01-29 02:51:40.676 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.28.20:5700/3) Recv RXTUNE cmd
2026-01-29 02:51:40.677 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.28.20:5700/3) Recv TXTUNE cmd
2026-01-29 02:51:40.677 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.28.20:5700/3) Recv SETFORMAT cmd
2026-01-29 02:51:40.677 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.28.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:51:40.677 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:51:40.677 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.28.20:5700/3) Recv NOMTXPOWER cmd
2026-01-29 02:51:40.677 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.28.20:5700/3) Recv SETFORMAT cmd
2026-01-29 02:51:40.677 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.28.20:5700/3) TRXD header version 1 -> 1
2026-01-29 02:51:40.680 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.28.20:5700) Recv RXTUNE cmd
2026-01-29 02:51:40.680 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETTSC
2026-01-29 02:51:40.680 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETTSC
2026-01-29 02:51:40.680 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETTSC
2026-01-29 02:51:40.680 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.28.20:5700) Recv TXTUNE cmd
2026-01-29 02:51:40.680 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETRXGAIN
2026-01-29 02:51:40.680 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETRXGAIN
2026-01-29 02:51:40.680 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETRXGAIN
2026-01-29 02:51:40.680 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETTSC
2026-01-29 02:51:40.680 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:51:40.680 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:51:40.681 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.28.20:5700) Recv NOMTXPOWER cmd
2026-01-29 02:51:40.681 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:51:40.681 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:51:40.681 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:51:40.681 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.28.20:5700) Recv POWERON CMD
2026-01-29 02:51:40.681 [INFO] ctrl_if_trx.py:109 (BTS@172.18.28.20:5700) Starting transceiver...
2026-01-29 02:51:40.681 [INFO] transceiver.py:243 Starting clock generator
2026-01-29 02:51:40.681 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-01-29 02:51:40.681 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:51:40.681 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:51:40.681 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:51:40.681 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETRXGAIN
2026-01-29 02:51:40.681 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:51:40.681 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:51:40.681 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:51:40.681 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:51:40.681 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:51:40.681 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:51:40.682 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:51:40.682 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:51:40.682 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:51:40.682 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:51:40.682 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:51:40.682 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:51:40.682 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:51:40.682 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:51:40.682 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:51:40.682 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:51:40.682 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:51:40.682 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:51:40.682 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:51:40.682 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:51:40.682 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:51:40.682 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:51:40.682 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:51:40.682 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:51:40.686 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-01-29 02:51:41.168 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-01-29 02:51:41.208 [DEBUG] fake_trx.py:278 (BTS@172.18.28.20:5700) Recv FAKE_TOA cmd
2026-01-29 02:51:41.210 [DEBUG] fake_trx.py:297 (BTS@172.18.28.20:5700) Recv FAKE_RSSI cmd
2026-01-29 02:51:41.212 [DEBUG] fake_trx.py:322 (BTS@172.18.28.20:5700) Recv FAKE_CI cmd
2026-01-29 02:51:41.212 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:51:41.243 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 02:51:41.243 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 02:51:41.243 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 02:51:41.248 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:51:41.248 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 02:51:41.249 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 02:51:41.249 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.28.22:6700) Recv POWERON CMD
2026-01-29 02:51:41.249 [INFO] ctrl_if_trx.py:109 (MS@172.18.28.22:6700) Starting transceiver...
2026-01-29 02:51:41.259 [DEBUG] fake_trx.py:297 (BTS@172.18.28.20:5700) Recv FAKE_RSSI cmd
2026-01-29 02:51:41.262 [DEBUG] fake_trx.py:278 (BTS@172.18.28.20:5700) Recv FAKE_TOA cmd
2026-01-29 02:51:41.267 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:51:41.270 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.28.22:6700) Recv SETFH cmd
2026-01-29 02:51:41.270 [INFO] transceiver.py:201 (MS@172.18.28.22:6700) Frequency hopping configured: hsn=5, maio=0, ma_len=4
2026-01-29 02:51:41.271 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:51:41.271 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:51:41.647 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-01-29 02:51:41.684 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:51:41.684 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 02:51:41.685 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:51:41.689 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:51:42.127 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-01-29 02:51:42.330 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 02:51:42.330 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 02:51:42.330 [INFO] transceiver.py:205 (MS@172.18.28.22:6700) Frequency hopping disabled
2026-01-29 02:51:42.334 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 02:51:42.334 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:51:42.334 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:51:42.334 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:51:42.335 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:51:42.335 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 02:51:42.335 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:51:42.335 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.28.20:5700) Recv POWEROFF cmd
2026-01-29 02:51:42.335 [INFO] ctrl_if_trx.py:117 (BTS@172.18.28.20:5700) Stopping transceiver...
2026-01-29 02:51:42.335 [INFO] transceiver.py:246 Stopping clock generator
2026-01-29 02:51:42.335 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:51:42.335 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=353 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:51:42.335 [WARNING] transceiver.py:257 (TRX2@172.18.28.20:5700/2) RX TRXD message (ver=1 fn=353 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:51:42.335 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=353 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:51:42.335 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=353 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:51:42.335 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=353 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:51:42.335 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=353 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:51:42.335 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=353 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:51:42.335 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=353 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:51:42.335 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=353 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:51:47.338 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.28.20:5700) Recv POWEROFF cmd
2026-01-29 02:51:47.338 [INFO] ctrl_if_trx.py:117 (BTS@172.18.28.20:5700) Stopping transceiver...
2026-01-29 02:51:47.342 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:51:47.342 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:51:47.342 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 02:51:47.342 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:51:47.351 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 02:51:47.353 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.28.20:5700) Recv SETFORMAT cmd
2026-01-29 02:51:47.354 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.28.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:51:47.354 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.28.20:5700) Recv SETFORMAT cmd
2026-01-29 02:51:47.355 [INFO] ctrl_if_trx.py:201 (BTS@172.18.28.20:5700) TRXD header version 1 -> 1
2026-01-29 02:51:47.359 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.28.20:5700/1) Recv RXTUNE cmd
2026-01-29 02:51:47.360 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.28.20:5700/1) Recv TXTUNE cmd
2026-01-29 02:51:47.360 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.28.20:5700/1) Recv SETFORMAT cmd
2026-01-29 02:51:47.360 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.28.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:51:47.361 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:51:47.361 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.28.20:5700/1) Recv NOMTXPOWER cmd
2026-01-29 02:51:47.362 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.28.20:5700/1) Recv SETFORMAT cmd
2026-01-29 02:51:47.362 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.28.20:5700/1) TRXD header version 1 -> 1
2026-01-29 02:51:47.363 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.28.20:5700/2) Recv RXTUNE cmd
2026-01-29 02:51:47.363 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.28.20:5700/2) Recv TXTUNE cmd
2026-01-29 02:51:47.364 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.28.20:5700/2) Recv SETFORMAT cmd
2026-01-29 02:51:47.364 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.28.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:51:47.364 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:51:47.364 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.28.20:5700/2) Recv NOMTXPOWER cmd
2026-01-29 02:51:47.365 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.28.20:5700/2) Recv SETFORMAT cmd
2026-01-29 02:51:47.365 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.28.20:5700/2) TRXD header version 1 -> 1
2026-01-29 02:51:47.366 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.28.20:5700/3) Recv RXTUNE cmd
2026-01-29 02:51:47.367 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.28.20:5700/3) Recv TXTUNE cmd
2026-01-29 02:51:47.367 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.28.20:5700/3) Recv SETFORMAT cmd
2026-01-29 02:51:47.367 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.28.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:51:47.367 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:51:47.367 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.28.20:5700/3) Recv NOMTXPOWER cmd
2026-01-29 02:51:47.367 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.28.20:5700/3) Recv SETFORMAT cmd
2026-01-29 02:51:47.367 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.28.20:5700/3) TRXD header version 1 -> 1
2026-01-29 02:51:47.370 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.28.20:5700) Recv RXTUNE cmd
2026-01-29 02:51:47.370 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETTSC
2026-01-29 02:51:47.370 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETTSC
2026-01-29 02:51:47.370 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETTSC
2026-01-29 02:51:47.370 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.28.20:5700) Recv TXTUNE cmd
2026-01-29 02:51:47.370 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETRXGAIN
2026-01-29 02:51:47.370 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETRXGAIN
2026-01-29 02:51:47.370 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETRXGAIN
2026-01-29 02:51:47.370 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETTSC
2026-01-29 02:51:47.370 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:51:47.370 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:51:47.370 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:51:47.370 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.28.20:5700) Recv NOMTXPOWER cmd
2026-01-29 02:51:47.370 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:51:47.370 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:51:47.370 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:51:47.370 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.28.20:5700) Recv POWERON CMD
2026-01-29 02:51:47.371 [INFO] ctrl_if_trx.py:109 (BTS@172.18.28.20:5700) Starting transceiver...
2026-01-29 02:51:47.371 [INFO] transceiver.py:243 Starting clock generator
2026-01-29 02:51:47.371 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-01-29 02:51:47.371 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:51:47.371 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:51:47.371 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:51:47.371 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETRXGAIN
2026-01-29 02:51:47.371 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:51:47.371 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:51:47.371 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:51:47.371 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:51:47.371 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:51:47.371 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:51:47.371 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:51:47.371 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:51:47.371 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:51:47.372 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:51:47.372 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:51:47.372 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:51:47.372 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:51:47.372 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:51:47.372 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:51:47.372 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:51:47.372 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:51:47.372 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:51:47.372 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:51:47.372 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:51:47.372 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:51:47.372 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:51:47.372 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:51:47.375 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-01-29 02:51:47.859 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-01-29 02:51:47.899 [DEBUG] fake_trx.py:278 (BTS@172.18.28.20:5700) Recv FAKE_TOA cmd
2026-01-29 02:51:47.901 [DEBUG] fake_trx.py:297 (BTS@172.18.28.20:5700) Recv FAKE_RSSI cmd
2026-01-29 02:51:47.903 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:51:47.903 [DEBUG] fake_trx.py:322 (BTS@172.18.28.20:5700) Recv FAKE_CI cmd
2026-01-29 02:51:47.932 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 02:51:47.932 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 02:51:47.932 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 02:51:47.940 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:51:47.941 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 02:51:47.941 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 02:51:47.941 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.28.22:6700) Recv POWERON CMD
2026-01-29 02:51:47.941 [INFO] ctrl_if_trx.py:109 (MS@172.18.28.22:6700) Starting transceiver...
2026-01-29 02:51:47.952 [DEBUG] fake_trx.py:297 (BTS@172.18.28.20:5700) Recv FAKE_RSSI cmd
2026-01-29 02:51:47.955 [DEBUG] fake_trx.py:278 (BTS@172.18.28.20:5700) Recv FAKE_TOA cmd
2026-01-29 02:51:47.959 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:51:47.962 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 02:51:47.962 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 02:51:47.962 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:51:47.962 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:51:48.336 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-01-29 02:51:48.373 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 02:51:48.374 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:51:48.375 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:51:48.377 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:51:48.814 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-01-29 02:51:49.292 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-01-29 02:51:49.375 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 02:51:49.375 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:51:49.375 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:51:49.378 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:51:49.770 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-01-29 02:51:50.248 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-01-29 02:51:50.376 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:51:50.376 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:51:50.376 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 02:51:50.380 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:51:50.725 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-01-29 02:51:51.203 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-01-29 02:51:51.377 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 02:51:51.377 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:51:51.377 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:51:51.380 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:51:51.681 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-01-29 02:51:52.159 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-01-29 02:51:52.378 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:51:52.379 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:51:52.379 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 02:51:52.381 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:51:52.636 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-01-29 02:51:53.115 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-01-29 02:51:53.592 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-01-29 02:51:54.069 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-01-29 02:51:54.547 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-01-29 02:51:55.025 [DEBUG] clck_gen.py:113 IND CLOCK 1632
2026-01-29 02:51:55.503 [DEBUG] clck_gen.py:113 IND CLOCK 1734
2026-01-29 02:51:55.964 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:51:55.967 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:51:55.967 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 02:51:55.968 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 02:51:55.981 [DEBUG] clck_gen.py:113 IND CLOCK 1836
2026-01-29 02:51:55.985 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 02:51:55.986 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 02:51:55.986 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 02:51:55.987 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:51:55.987 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 02:51:55.987 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 02:51:55.987 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.28.22:6700) Recv POWERON CMD
2026-01-29 02:51:55.987 [INFO] ctrl_if_trx.py:109 (MS@172.18.28.22:6700) Starting transceiver...
2026-01-29 02:51:56.026 [DEBUG] fake_trx.py:297 (BTS@172.18.28.20:5700) Recv FAKE_RSSI cmd
2026-01-29 02:51:56.030 [DEBUG] fake_trx.py:278 (BTS@172.18.28.20:5700) Recv FAKE_TOA cmd
2026-01-29 02:51:56.036 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:51:56.040 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 02:51:56.041 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 02:51:56.041 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:51:56.041 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:51:56.457 [DEBUG] clck_gen.py:113 IND CLOCK 1938
2026-01-29 02:51:56.935 [DEBUG] clck_gen.py:113 IND CLOCK 2040
2026-01-29 02:51:57.413 [DEBUG] clck_gen.py:113 IND CLOCK 2142
2026-01-29 02:51:57.890 [DEBUG] clck_gen.py:113 IND CLOCK 2244
2026-01-29 02:51:58.368 [DEBUG] clck_gen.py:113 IND CLOCK 2346
2026-01-29 02:51:58.846 [DEBUG] clck_gen.py:113 IND CLOCK 2448
2026-01-29 02:51:59.324 [DEBUG] clck_gen.py:113 IND CLOCK 2550
2026-01-29 02:51:59.802 [DEBUG] clck_gen.py:113 IND CLOCK 2652
2026-01-29 02:52:00.279 [DEBUG] clck_gen.py:113 IND CLOCK 2754
2026-01-29 02:52:00.757 [DEBUG] clck_gen.py:113 IND CLOCK 2856
2026-01-29 02:52:01.235 [DEBUG] clck_gen.py:113 IND CLOCK 2958
2026-01-29 02:52:01.713 [DEBUG] clck_gen.py:113 IND CLOCK 3060
2026-01-29 02:52:02.191 [DEBUG] clck_gen.py:113 IND CLOCK 3162
2026-01-29 02:52:02.668 [DEBUG] clck_gen.py:113 IND CLOCK 3264
2026-01-29 02:52:03.146 [DEBUG] clck_gen.py:113 IND CLOCK 3366
2026-01-29 02:52:03.624 [DEBUG] clck_gen.py:113 IND CLOCK 3468
2026-01-29 02:52:04.044 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:52:04.047 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:52:04.047 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 02:52:04.047 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 02:52:04.066 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 02:52:04.066 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 02:52:04.066 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 02:52:04.068 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:52:04.068 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 02:52:04.068 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 02:52:04.068 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.28.22:6700) Recv POWERON CMD
2026-01-29 02:52:04.068 [INFO] ctrl_if_trx.py:109 (MS@172.18.28.22:6700) Starting transceiver...
2026-01-29 02:52:04.094 [DEBUG] fake_trx.py:297 (BTS@172.18.28.20:5700) Recv FAKE_RSSI cmd
2026-01-29 02:52:04.098 [DEBUG] fake_trx.py:278 (BTS@172.18.28.20:5700) Recv FAKE_TOA cmd
2026-01-29 02:52:04.101 [DEBUG] clck_gen.py:113 IND CLOCK 3570
2026-01-29 02:52:04.104 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:52:04.107 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 02:52:04.108 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 02:52:04.108 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:52:04.108 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:52:04.579 [DEBUG] clck_gen.py:113 IND CLOCK 3672
2026-01-29 02:52:05.057 [DEBUG] clck_gen.py:113 IND CLOCK 3774
2026-01-29 02:52:05.536 [DEBUG] clck_gen.py:113 IND CLOCK 3876
2026-01-29 02:52:06.014 [DEBUG] clck_gen.py:113 IND CLOCK 3978
2026-01-29 02:52:06.491 [DEBUG] clck_gen.py:113 IND CLOCK 4080
2026-01-29 02:52:06.969 [DEBUG] clck_gen.py:113 IND CLOCK 4182
2026-01-29 02:52:07.447 [DEBUG] clck_gen.py:113 IND CLOCK 4284
2026-01-29 02:52:07.924 [DEBUG] clck_gen.py:113 IND CLOCK 4386
2026-01-29 02:52:08.402 [DEBUG] clck_gen.py:113 IND CLOCK 4488
2026-01-29 02:52:08.880 [DEBUG] clck_gen.py:113 IND CLOCK 4590
2026-01-29 02:52:09.358 [DEBUG] clck_gen.py:113 IND CLOCK 4692
2026-01-29 02:52:09.836 [DEBUG] clck_gen.py:113 IND CLOCK 4794
2026-01-29 02:52:10.313 [DEBUG] clck_gen.py:113 IND CLOCK 4896
2026-01-29 02:52:10.791 [DEBUG] clck_gen.py:113 IND CLOCK 4998
2026-01-29 02:52:11.269 [DEBUG] clck_gen.py:113 IND CLOCK 5100
2026-01-29 02:52:11.747 [DEBUG] clck_gen.py:113 IND CLOCK 5202
2026-01-29 02:52:12.110 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:52:12.113 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:52:12.113 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 02:52:12.113 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 02:52:12.131 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 02:52:12.131 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 02:52:12.131 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 02:52:12.132 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:52:12.132 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 02:52:12.133 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 02:52:12.133 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.28.22:6700) Recv POWERON CMD
2026-01-29 02:52:12.133 [INFO] ctrl_if_trx.py:109 (MS@172.18.28.22:6700) Starting transceiver...
2026-01-29 02:52:12.166 [DEBUG] fake_trx.py:297 (BTS@172.18.28.20:5700) Recv FAKE_RSSI cmd
2026-01-29 02:52:12.170 [DEBUG] fake_trx.py:278 (BTS@172.18.28.20:5700) Recv FAKE_TOA cmd
2026-01-29 02:52:12.176 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:52:12.180 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 02:52:12.180 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 02:52:12.180 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:52:12.180 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:52:12.225 [DEBUG] clck_gen.py:113 IND CLOCK 5304
2026-01-29 02:52:12.703 [DEBUG] clck_gen.py:113 IND CLOCK 5406
2026-01-29 02:52:13.181 [DEBUG] clck_gen.py:113 IND CLOCK 5508
2026-01-29 02:52:13.659 [DEBUG] clck_gen.py:113 IND CLOCK 5610
2026-01-29 02:52:14.137 [DEBUG] clck_gen.py:113 IND CLOCK 5712
2026-01-29 02:52:14.614 [DEBUG] clck_gen.py:113 IND CLOCK 5814
2026-01-29 02:52:15.092 [DEBUG] clck_gen.py:113 IND CLOCK 5916
2026-01-29 02:52:15.570 [DEBUG] clck_gen.py:113 IND CLOCK 6018
2026-01-29 02:52:16.048 [DEBUG] clck_gen.py:113 IND CLOCK 6120
2026-01-29 02:52:16.526 [DEBUG] clck_gen.py:113 IND CLOCK 6222
2026-01-29 02:52:17.003 [DEBUG] clck_gen.py:113 IND CLOCK 6324
2026-01-29 02:52:17.481 [DEBUG] clck_gen.py:113 IND CLOCK 6426
2026-01-29 02:52:17.959 [DEBUG] clck_gen.py:113 IND CLOCK 6528
2026-01-29 02:52:18.436 [DEBUG] clck_gen.py:113 IND CLOCK 6630
2026-01-29 02:52:18.914 [DEBUG] clck_gen.py:113 IND CLOCK 6732
2026-01-29 02:52:19.392 [DEBUG] clck_gen.py:113 IND CLOCK 6834
2026-01-29 02:52:19.870 [DEBUG] clck_gen.py:113 IND CLOCK 6936
2026-01-29 02:52:20.182 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:52:20.185 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:52:20.185 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 02:52:20.185 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 02:52:20.195 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 02:52:20.196 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:52:20.196 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:52:20.196 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:52:20.198 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 02:52:20.198 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:52:20.198 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:52:20.198 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:52:20.198 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.28.20:5700) Recv POWEROFF cmd
2026-01-29 02:52:20.198 [INFO] ctrl_if_trx.py:117 (BTS@172.18.28.20:5700) Stopping transceiver...
2026-01-29 02:52:20.198 [INFO] transceiver.py:246 Stopping clock generator
2026-01-29 02:52:20.198 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=7009 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:52:20.198 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=7009 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:52:20.198 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=7009 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:52:20.198 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=7009 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:52:20.198 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=7009 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:52:20.198 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=7009 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:52:20.198 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=7009 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:52:25.198 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.28.20:5700) Recv POWEROFF cmd
2026-01-29 02:52:25.198 [INFO] ctrl_if_trx.py:117 (BTS@172.18.28.20:5700) Stopping transceiver...
2026-01-29 02:52:25.202 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:52:25.202 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:52:25.202 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:52:25.202 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 02:52:25.211 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 02:52:25.212 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.28.20:5700) Recv SETFORMAT cmd
2026-01-29 02:52:25.212 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.28.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:52:25.212 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.28.20:5700) Recv SETFORMAT cmd
2026-01-29 02:52:25.212 [INFO] ctrl_if_trx.py:201 (BTS@172.18.28.20:5700) TRXD header version 1 -> 1
2026-01-29 02:52:25.217 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.28.20:5700/1) Recv RXTUNE cmd
2026-01-29 02:52:25.217 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.28.20:5700/1) Recv TXTUNE cmd
2026-01-29 02:52:25.217 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.28.20:5700/1) Recv SETFORMAT cmd
2026-01-29 02:52:25.217 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.28.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:52:25.217 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:52:25.217 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.28.20:5700/1) Recv NOMTXPOWER cmd
2026-01-29 02:52:25.218 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.28.20:5700/1) Recv SETFORMAT cmd
2026-01-29 02:52:25.218 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.28.20:5700/1) TRXD header version 1 -> 1
2026-01-29 02:52:25.221 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.28.20:5700/2) Recv RXTUNE cmd
2026-01-29 02:52:25.221 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.28.20:5700/2) Recv TXTUNE cmd
2026-01-29 02:52:25.221 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.28.20:5700/2) Recv SETFORMAT cmd
2026-01-29 02:52:25.221 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.28.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:52:25.221 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:52:25.221 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.28.20:5700/2) Recv NOMTXPOWER cmd
2026-01-29 02:52:25.222 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.28.20:5700/2) Recv SETFORMAT cmd
2026-01-29 02:52:25.222 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.28.20:5700/2) TRXD header version 1 -> 1
2026-01-29 02:52:25.224 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.28.20:5700/3) Recv RXTUNE cmd
2026-01-29 02:52:25.224 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.28.20:5700/3) Recv TXTUNE cmd
2026-01-29 02:52:25.224 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.28.20:5700/3) Recv SETFORMAT cmd
2026-01-29 02:52:25.224 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.28.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:52:25.224 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:52:25.224 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.28.20:5700/3) Recv NOMTXPOWER cmd
2026-01-29 02:52:25.225 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.28.20:5700/3) Recv SETFORMAT cmd
2026-01-29 02:52:25.225 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.28.20:5700/3) TRXD header version 1 -> 1
2026-01-29 02:52:25.228 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.28.20:5700) Recv RXTUNE cmd
2026-01-29 02:52:25.228 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETTSC
2026-01-29 02:52:25.228 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETTSC
2026-01-29 02:52:25.228 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETTSC
2026-01-29 02:52:25.228 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.28.20:5700) Recv TXTUNE cmd
2026-01-29 02:52:25.228 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETRXGAIN
2026-01-29 02:52:25.228 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETRXGAIN
2026-01-29 02:52:25.228 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETRXGAIN
2026-01-29 02:52:25.228 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETTSC
2026-01-29 02:52:25.228 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:52:25.228 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:52:25.228 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:52:25.228 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.28.20:5700) Recv NOMTXPOWER cmd
2026-01-29 02:52:25.229 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:52:25.229 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:52:25.229 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:52:25.229 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.28.20:5700) Recv POWERON CMD
2026-01-29 02:52:25.229 [INFO] ctrl_if_trx.py:109 (BTS@172.18.28.20:5700) Starting transceiver...
2026-01-29 02:52:25.229 [INFO] transceiver.py:243 Starting clock generator
2026-01-29 02:52:25.229 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-01-29 02:52:25.229 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:52:25.229 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:52:25.229 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:52:25.229 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETRXGAIN
2026-01-29 02:52:25.229 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:52:25.229 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:52:25.229 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:52:25.229 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:52:25.229 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:52:25.230 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:52:25.230 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:52:25.230 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:52:25.230 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:52:25.230 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:52:25.230 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:52:25.230 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:52:25.230 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:52:25.230 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:52:25.230 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:52:25.230 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:52:25.230 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:52:25.230 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:52:25.230 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:52:25.230 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:52:25.230 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:52:25.230 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:52:25.230 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:52:25.234 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-01-29 02:52:25.718 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-01-29 02:52:25.757 [DEBUG] fake_trx.py:278 (BTS@172.18.28.20:5700) Recv FAKE_TOA cmd
2026-01-29 02:52:25.758 [DEBUG] fake_trx.py:297 (BTS@172.18.28.20:5700) Recv FAKE_RSSI cmd
2026-01-29 02:52:25.760 [DEBUG] fake_trx.py:322 (BTS@172.18.28.20:5700) Recv FAKE_CI cmd
2026-01-29 02:52:25.760 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:52:25.782 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 02:52:25.782 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 02:52:25.783 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 02:52:25.788 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:52:25.788 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 02:52:25.788 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 02:52:25.788 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.28.22:6700) Recv POWERON CMD
2026-01-29 02:52:25.788 [INFO] ctrl_if_trx.py:109 (MS@172.18.28.22:6700) Starting transceiver...
2026-01-29 02:52:25.810 [DEBUG] fake_trx.py:297 (BTS@172.18.28.20:5700) Recv FAKE_RSSI cmd
2026-01-29 02:52:25.813 [DEBUG] fake_trx.py:278 (BTS@172.18.28.20:5700) Recv FAKE_TOA cmd
2026-01-29 02:52:25.819 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:52:25.825 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.28.22:6700) Recv SETFH cmd
2026-01-29 02:52:25.826 [INFO] transceiver.py:201 (MS@172.18.28.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2026-01-29 02:52:25.826 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:52:25.826 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:52:26.196 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-01-29 02:52:26.232 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 02:52:26.232 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:52:26.233 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:52:26.238 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:52:26.674 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-01-29 02:52:27.153 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-01-29 02:52:27.233 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:52:27.233 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 02:52:27.235 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:52:27.239 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:52:27.631 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-01-29 02:52:28.110 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-01-29 02:52:28.234 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 02:52:28.234 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:52:28.235 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:52:28.240 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:52:28.339 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 02:52:28.339 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 02:52:28.339 [INFO] transceiver.py:205 (MS@172.18.28.22:6700) Frequency hopping disabled
2026-01-29 02:52:28.342 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 02:52:28.342 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:52:28.342 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:52:28.342 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:52:28.343 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 02:52:28.343 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:52:28.343 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:52:28.343 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:52:28.343 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.28.20:5700) Recv POWEROFF cmd
2026-01-29 02:52:28.343 [INFO] ctrl_if_trx.py:117 (BTS@172.18.28.20:5700) Stopping transceiver...
2026-01-29 02:52:28.343 [INFO] transceiver.py:246 Stopping clock generator
2026-01-29 02:52:28.343 [WARNING] transceiver.py:257 (TRX3@172.18.28.20:5700/3) RX TRXD message (ver=1 fn=664 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:52:28.343 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=664 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:52:28.343 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=664 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:52:28.343 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=664 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:52:28.343 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=664 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:52:28.343 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=664 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:52:28.343 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=664 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:52:28.343 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=664 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:52:33.346 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.28.20:5700) Recv POWEROFF cmd
2026-01-29 02:52:33.346 [INFO] ctrl_if_trx.py:117 (BTS@172.18.28.20:5700) Stopping transceiver...
2026-01-29 02:52:33.348 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:52:33.349 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:52:33.351 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:52:33.351 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 02:52:33.360 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 02:52:33.362 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.28.20:5700) Recv SETFORMAT cmd
2026-01-29 02:52:33.362 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.28.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:52:33.362 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.28.20:5700) Recv SETFORMAT cmd
2026-01-29 02:52:33.362 [INFO] ctrl_if_trx.py:201 (BTS@172.18.28.20:5700) TRXD header version 1 -> 1
2026-01-29 02:52:33.365 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.28.20:5700/1) Recv RXTUNE cmd
2026-01-29 02:52:33.366 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.28.20:5700/1) Recv TXTUNE cmd
2026-01-29 02:52:33.366 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.28.20:5700/1) Recv SETFORMAT cmd
2026-01-29 02:52:33.366 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.28.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:52:33.367 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:52:33.367 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.28.20:5700/1) Recv NOMTXPOWER cmd
2026-01-29 02:52:33.368 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.28.20:5700/1) Recv SETFORMAT cmd
2026-01-29 02:52:33.368 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.28.20:5700/1) TRXD header version 1 -> 1
2026-01-29 02:52:33.369 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.28.20:5700/2) Recv RXTUNE cmd
2026-01-29 02:52:33.369 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.28.20:5700/2) Recv TXTUNE cmd
2026-01-29 02:52:33.370 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.28.20:5700/2) Recv SETFORMAT cmd
2026-01-29 02:52:33.370 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.28.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:52:33.370 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:52:33.370 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.28.20:5700/2) Recv NOMTXPOWER cmd
2026-01-29 02:52:33.370 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.28.20:5700/2) Recv SETFORMAT cmd
2026-01-29 02:52:33.370 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.28.20:5700/2) TRXD header version 1 -> 1
2026-01-29 02:52:33.372 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.28.20:5700/3) Recv RXTUNE cmd
2026-01-29 02:52:33.372 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.28.20:5700/3) Recv TXTUNE cmd
2026-01-29 02:52:33.372 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.28.20:5700/3) Recv SETFORMAT cmd
2026-01-29 02:52:33.372 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.28.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:52:33.372 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:52:33.372 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.28.20:5700/3) Recv NOMTXPOWER cmd
2026-01-29 02:52:33.372 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.28.20:5700/3) Recv SETFORMAT cmd
2026-01-29 02:52:33.372 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.28.20:5700/3) TRXD header version 1 -> 1
2026-01-29 02:52:33.376 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.28.20:5700) Recv RXTUNE cmd
2026-01-29 02:52:33.376 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETTSC
2026-01-29 02:52:33.376 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETTSC
2026-01-29 02:52:33.376 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETTSC
2026-01-29 02:52:33.376 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.28.20:5700) Recv TXTUNE cmd
2026-01-29 02:52:33.376 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETRXGAIN
2026-01-29 02:52:33.376 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETRXGAIN
2026-01-29 02:52:33.376 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETRXGAIN
2026-01-29 02:52:33.376 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETTSC
2026-01-29 02:52:33.376 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:52:33.376 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:52:33.376 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.28.20:5700) Recv NOMTXPOWER cmd
2026-01-29 02:52:33.377 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:52:33.377 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:52:33.377 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:52:33.377 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.28.20:5700) Recv POWERON CMD
2026-01-29 02:52:33.377 [INFO] ctrl_if_trx.py:109 (BTS@172.18.28.20:5700) Starting transceiver...
2026-01-29 02:52:33.377 [INFO] transceiver.py:243 Starting clock generator
2026-01-29 02:52:33.377 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-01-29 02:52:33.377 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:52:33.377 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:52:33.377 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:52:33.377 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETRXGAIN
2026-01-29 02:52:33.377 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:52:33.377 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:52:33.378 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:52:33.378 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:52:33.378 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:52:33.378 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:52:33.378 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:52:33.378 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:52:33.378 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:52:33.378 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:52:33.378 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:52:33.378 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:52:33.378 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:52:33.378 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:52:33.378 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:52:33.378 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:52:33.378 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:52:33.378 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:52:33.378 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:52:33.378 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:52:33.378 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:52:33.378 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:52:33.379 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:52:33.379 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:52:33.382 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-01-29 02:52:33.863 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-01-29 02:52:33.910 [DEBUG] fake_trx.py:278 (BTS@172.18.28.20:5700) Recv FAKE_TOA cmd
2026-01-29 02:52:33.912 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:52:33.913 [DEBUG] fake_trx.py:297 (BTS@172.18.28.20:5700) Recv FAKE_RSSI cmd
2026-01-29 02:52:33.917 [DEBUG] fake_trx.py:322 (BTS@172.18.28.20:5700) Recv FAKE_CI cmd
2026-01-29 02:52:33.940 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 02:52:33.940 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 02:52:33.941 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 02:52:33.947 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:52:33.948 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 02:52:33.948 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 02:52:33.949 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.28.22:6700) Recv POWERON CMD
2026-01-29 02:52:33.949 [INFO] ctrl_if_trx.py:109 (MS@172.18.28.22:6700) Starting transceiver...
2026-01-29 02:52:33.955 [DEBUG] fake_trx.py:297 (BTS@172.18.28.20:5700) Recv FAKE_RSSI cmd
2026-01-29 02:52:33.958 [DEBUG] fake_trx.py:278 (BTS@172.18.28.20:5700) Recv FAKE_TOA cmd
2026-01-29 02:52:33.963 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:52:33.966 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.28.22:6700) Recv SETFH cmd
2026-01-29 02:52:33.966 [INFO] transceiver.py:201 (MS@172.18.28.22:6700) Frequency hopping configured: hsn=5, maio=0, ma_len=4
2026-01-29 02:52:33.966 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:52:33.966 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:52:34.341 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-01-29 02:52:34.380 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 02:52:34.380 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:52:34.382 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:52:34.385 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:52:34.819 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-01-29 02:52:35.022 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 02:52:35.022 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 02:52:35.022 [INFO] transceiver.py:205 (MS@172.18.28.22:6700) Frequency hopping disabled
2026-01-29 02:52:35.026 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 02:52:35.027 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:52:35.027 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:52:35.027 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:52:35.028 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 02:52:35.028 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:52:35.028 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:52:35.028 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.28.20:5700) Recv POWEROFF cmd
2026-01-29 02:52:35.028 [INFO] ctrl_if_trx.py:117 (BTS@172.18.28.20:5700) Stopping transceiver...
2026-01-29 02:52:35.028 [INFO] transceiver.py:246 Stopping clock generator
2026-01-29 02:52:35.028 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:52:35.028 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=353 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:52:35.028 [WARNING] transceiver.py:257 (TRX2@172.18.28.20:5700/2) RX TRXD message (ver=1 fn=353 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:52:35.028 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=353 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:52:35.028 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=353 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:52:35.028 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=353 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:52:35.028 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=353 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:52:35.028 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=353 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:52:35.028 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=353 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:52:35.028 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=353 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:52:40.030 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.28.20:5700) Recv POWEROFF cmd
2026-01-29 02:52:40.030 [INFO] ctrl_if_trx.py:117 (BTS@172.18.28.20:5700) Stopping transceiver...
2026-01-29 02:52:40.032 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:52:40.033 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:52:40.035 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:52:40.037 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 02:52:40.045 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 02:52:40.045 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.28.20:5700) Recv SETFORMAT cmd
2026-01-29 02:52:40.046 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.28.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:52:40.046 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.28.20:5700) Recv SETFORMAT cmd
2026-01-29 02:52:40.046 [INFO] ctrl_if_trx.py:201 (BTS@172.18.28.20:5700) TRXD header version 1 -> 1
2026-01-29 02:52:40.048 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.28.20:5700/1) Recv RXTUNE cmd
2026-01-29 02:52:40.048 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.28.20:5700/1) Recv TXTUNE cmd
2026-01-29 02:52:40.048 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.28.20:5700/1) Recv SETFORMAT cmd
2026-01-29 02:52:40.048 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.28.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:52:40.049 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:52:40.049 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.28.20:5700/1) Recv NOMTXPOWER cmd
2026-01-29 02:52:40.049 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.28.20:5700/1) Recv SETFORMAT cmd
2026-01-29 02:52:40.049 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.28.20:5700/1) TRXD header version 1 -> 1
2026-01-29 02:52:40.050 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.28.20:5700/2) Recv RXTUNE cmd
2026-01-29 02:52:40.050 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.28.20:5700/2) Recv TXTUNE cmd
2026-01-29 02:52:40.050 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.28.20:5700/2) Recv SETFORMAT cmd
2026-01-29 02:52:40.050 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.28.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:52:40.051 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:52:40.051 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.28.20:5700/2) Recv NOMTXPOWER cmd
2026-01-29 02:52:40.051 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.28.20:5700/2) Recv SETFORMAT cmd
2026-01-29 02:52:40.051 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.28.20:5700/2) TRXD header version 1 -> 1
2026-01-29 02:52:40.052 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.28.20:5700/3) Recv RXTUNE cmd
2026-01-29 02:52:40.052 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.28.20:5700/3) Recv TXTUNE cmd
2026-01-29 02:52:40.052 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.28.20:5700/3) Recv SETFORMAT cmd
2026-01-29 02:52:40.052 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.28.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:52:40.052 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:52:40.052 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.28.20:5700/3) Recv NOMTXPOWER cmd
2026-01-29 02:52:40.052 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.28.20:5700/3) Recv SETFORMAT cmd
2026-01-29 02:52:40.052 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.28.20:5700/3) TRXD header version 1 -> 1
2026-01-29 02:52:40.054 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.28.20:5700) Recv RXTUNE cmd
2026-01-29 02:52:40.054 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETTSC
2026-01-29 02:52:40.054 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETTSC
2026-01-29 02:52:40.054 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETTSC
2026-01-29 02:52:40.054 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.28.20:5700) Recv TXTUNE cmd
2026-01-29 02:52:40.055 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETRXGAIN
2026-01-29 02:52:40.055 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETRXGAIN
2026-01-29 02:52:40.055 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETRXGAIN
2026-01-29 02:52:40.055 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETTSC
2026-01-29 02:52:40.055 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:52:40.055 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:52:40.055 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.28.20:5700) Recv NOMTXPOWER cmd
2026-01-29 02:52:40.055 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:52:40.055 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:52:40.055 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:52:40.055 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.28.20:5700) Recv POWERON CMD
2026-01-29 02:52:40.055 [INFO] ctrl_if_trx.py:109 (BTS@172.18.28.20:5700) Starting transceiver...
2026-01-29 02:52:40.055 [INFO] transceiver.py:243 Starting clock generator
2026-01-29 02:52:40.055 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-01-29 02:52:40.055 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:52:40.055 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:52:40.055 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:52:40.055 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETRXGAIN
2026-01-29 02:52:40.055 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:52:40.055 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:52:40.055 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:52:40.055 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:52:40.055 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:52:40.055 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:52:40.055 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:52:40.056 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:52:40.056 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:52:40.056 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:52:40.056 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:52:40.056 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:52:40.056 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:52:40.056 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:52:40.056 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:52:40.056 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:52:40.056 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:52:40.056 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:52:40.056 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:52:40.056 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:52:40.056 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:52:40.056 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:52:40.056 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:52:40.056 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:52:40.060 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-01-29 02:52:40.544 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-01-29 02:52:40.580 [DEBUG] fake_trx.py:278 (BTS@172.18.28.20:5700) Recv FAKE_TOA cmd
2026-01-29 02:52:40.581 [DEBUG] fake_trx.py:297 (BTS@172.18.28.20:5700) Recv FAKE_RSSI cmd
2026-01-29 02:52:40.583 [DEBUG] fake_trx.py:322 (BTS@172.18.28.20:5700) Recv FAKE_CI cmd
2026-01-29 02:52:40.583 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:52:40.596 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 02:52:40.596 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 02:52:40.596 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 02:52:40.600 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:52:40.600 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 02:52:40.600 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 02:52:40.601 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.28.22:6700) Recv POWERON CMD
2026-01-29 02:52:40.601 [INFO] ctrl_if_trx.py:109 (MS@172.18.28.22:6700) Starting transceiver...
2026-01-29 02:52:40.638 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:52:40.641 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 02:52:40.642 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 02:52:40.642 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:52:40.643 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:52:41.021 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-01-29 02:52:41.057 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 02:52:41.057 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:52:41.059 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:52:41.063 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:52:41.499 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-01-29 02:52:41.977 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-01-29 02:52:42.058 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 02:52:42.059 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:52:42.060 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:52:42.064 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:52:42.455 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-01-29 02:52:42.933 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-01-29 02:52:43.059 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 02:52:43.059 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:52:43.061 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:52:43.064 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:52:43.412 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-01-29 02:52:43.890 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-01-29 02:52:44.060 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 02:52:44.060 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:52:44.062 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:52:44.065 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:52:44.367 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-01-29 02:52:44.845 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-01-29 02:52:45.060 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 02:52:45.061 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:52:45.063 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:52:45.065 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:52:45.324 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-01-29 02:52:45.802 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-01-29 02:52:46.279 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-01-29 02:52:46.757 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-01-29 02:52:47.235 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-01-29 02:52:47.713 [DEBUG] clck_gen.py:113 IND CLOCK 1632
2026-01-29 02:52:48.191 [DEBUG] clck_gen.py:113 IND CLOCK 1734
2026-01-29 02:52:48.647 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:52:48.650 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:52:48.652 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 02:52:48.652 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 02:52:48.669 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 02:52:48.669 [DEBUG] clck_gen.py:113 IND CLOCK 1836
2026-01-29 02:52:48.669 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:52:48.669 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:52:48.670 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:52:48.672 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 02:52:48.672 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:52:48.672 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:52:48.672 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.28.20:5700) Recv POWEROFF cmd
2026-01-29 02:52:48.672 [INFO] ctrl_if_trx.py:117 (BTS@172.18.28.20:5700) Stopping transceiver...
2026-01-29 02:52:48.672 [INFO] transceiver.py:246 Stopping clock generator
2026-01-29 02:52:48.672 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:52:48.672 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=1839 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:52:48.672 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=1839 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:52:48.672 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=1839 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:52:48.672 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=1839 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:52:48.672 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=1839 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:52:48.672 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=1839 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:52:48.672 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=1839 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:52:48.672 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=1839 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:52:48.672 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=1840 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:52:48.672 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=1840 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:52:48.672 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=1840 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:52:48.672 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=1840 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:52:48.672 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=1840 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:52:48.672 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=1840 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:52:48.672 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=1840 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:52:48.672 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=1840 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:52:53.673 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.28.20:5700) Recv POWEROFF cmd
2026-01-29 02:52:53.673 [INFO] ctrl_if_trx.py:117 (BTS@172.18.28.20:5700) Stopping transceiver...
2026-01-29 02:52:53.674 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:52:53.676 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:52:53.676 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:52:53.677 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 02:52:53.684 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 02:52:53.684 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.28.20:5700) Recv SETFORMAT cmd
2026-01-29 02:52:53.684 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.28.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:52:53.684 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.28.20:5700) Recv SETFORMAT cmd
2026-01-29 02:52:53.685 [INFO] ctrl_if_trx.py:201 (BTS@172.18.28.20:5700) TRXD header version 1 -> 1
2026-01-29 02:52:53.686 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.28.20:5700/1) Recv RXTUNE cmd
2026-01-29 02:52:53.687 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.28.20:5700/1) Recv TXTUNE cmd
2026-01-29 02:52:53.687 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.28.20:5700/1) Recv SETFORMAT cmd
2026-01-29 02:52:53.687 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.28.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:52:53.688 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:52:53.688 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.28.20:5700/1) Recv NOMTXPOWER cmd
2026-01-29 02:52:53.688 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.28.20:5700/1) Recv SETFORMAT cmd
2026-01-29 02:52:53.688 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.28.20:5700/1) TRXD header version 1 -> 1
2026-01-29 02:52:53.689 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.28.20:5700/2) Recv RXTUNE cmd
2026-01-29 02:52:53.689 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.28.20:5700/2) Recv TXTUNE cmd
2026-01-29 02:52:53.689 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.28.20:5700/2) Recv SETFORMAT cmd
2026-01-29 02:52:53.689 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.28.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:52:53.690 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:52:53.690 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.28.20:5700/2) Recv NOMTXPOWER cmd
2026-01-29 02:52:53.690 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.28.20:5700/2) Recv SETFORMAT cmd
2026-01-29 02:52:53.690 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.28.20:5700/2) TRXD header version 1 -> 1
2026-01-29 02:52:53.692 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.28.20:5700/3) Recv RXTUNE cmd
2026-01-29 02:52:53.692 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.28.20:5700/3) Recv TXTUNE cmd
2026-01-29 02:52:53.692 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.28.20:5700/3) Recv SETFORMAT cmd
2026-01-29 02:52:53.692 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.28.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:52:53.692 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:52:53.692 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.28.20:5700/3) Recv NOMTXPOWER cmd
2026-01-29 02:52:53.692 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.28.20:5700/3) Recv SETFORMAT cmd
2026-01-29 02:52:53.692 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.28.20:5700/3) TRXD header version 1 -> 1
2026-01-29 02:52:53.695 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.28.20:5700) Recv RXTUNE cmd
2026-01-29 02:52:53.695 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETTSC
2026-01-29 02:52:53.695 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETTSC
2026-01-29 02:52:53.695 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETTSC
2026-01-29 02:52:53.695 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.28.20:5700) Recv TXTUNE cmd
2026-01-29 02:52:53.695 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETRXGAIN
2026-01-29 02:52:53.695 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETRXGAIN
2026-01-29 02:52:53.695 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETRXGAIN
2026-01-29 02:52:53.695 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETTSC
2026-01-29 02:52:53.695 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:52:53.695 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:52:53.695 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:52:53.695 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.28.20:5700) Recv NOMTXPOWER cmd
2026-01-29 02:52:53.695 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:52:53.695 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:52:53.695 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:52:53.695 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.28.20:5700) Recv POWERON CMD
2026-01-29 02:52:53.695 [INFO] ctrl_if_trx.py:109 (BTS@172.18.28.20:5700) Starting transceiver...
2026-01-29 02:52:53.695 [INFO] transceiver.py:243 Starting clock generator
2026-01-29 02:52:53.696 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-01-29 02:52:53.696 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:52:53.696 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:52:53.696 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:52:53.696 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETRXGAIN
2026-01-29 02:52:53.696 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:52:53.696 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:52:53.696 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:52:53.696 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:52:53.696 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:52:53.696 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:52:53.696 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:52:53.696 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:52:53.696 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:52:53.696 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:52:53.696 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:52:53.697 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:52:53.697 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:52:53.697 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:52:53.697 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:52:53.697 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:52:53.697 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:52:53.697 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:52:53.697 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:52:53.697 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:52:53.697 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:52:53.697 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:52:53.697 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:52:53.700 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-01-29 02:52:54.184 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-01-29 02:52:54.224 [DEBUG] fake_trx.py:278 (BTS@172.18.28.20:5700) Recv FAKE_TOA cmd
2026-01-29 02:52:54.226 [DEBUG] fake_trx.py:297 (BTS@172.18.28.20:5700) Recv FAKE_RSSI cmd
2026-01-29 02:52:54.228 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:52:54.228 [DEBUG] fake_trx.py:322 (BTS@172.18.28.20:5700) Recv FAKE_CI cmd
2026-01-29 02:52:54.247 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 02:52:54.247 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 02:52:54.248 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 02:52:54.253 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:52:54.254 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 02:52:54.254 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 02:52:54.254 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.28.22:6700) Recv POWERON CMD
2026-01-29 02:52:54.254 [INFO] ctrl_if_trx.py:109 (MS@172.18.28.22:6700) Starting transceiver...
2026-01-29 02:52:54.281 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:52:54.287 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.28.22:6700) Recv SETFH cmd
2026-01-29 02:52:54.287 [INFO] transceiver.py:201 (MS@172.18.28.22:6700) Frequency hopping configured: hsn=5, maio=0, ma_len=4
2026-01-29 02:52:54.288 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:52:54.288 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:52:54.662 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-01-29 02:52:54.699 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:52:54.699 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 02:52:54.700 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:52:54.704 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:52:55.140 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-01-29 02:52:55.620 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-01-29 02:52:55.700 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 02:52:55.700 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:52:55.700 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:52:55.706 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:52:56.099 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-01-29 02:52:56.578 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-01-29 02:52:56.701 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 02:52:56.701 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:52:56.701 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:52:56.708 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:52:57.057 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-01-29 02:52:57.536 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-01-29 02:52:57.702 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:52:57.703 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:52:57.703 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 02:52:57.709 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:52:58.014 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-01-29 02:52:58.493 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-01-29 02:52:58.703 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 02:52:58.704 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:52:58.704 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:52:58.710 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:52:58.972 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-01-29 02:52:59.445 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-01-29 02:52:59.914 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-01-29 02:53:00.391 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-01-29 02:53:00.870 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-01-29 02:53:01.348 [DEBUG] clck_gen.py:113 IND CLOCK 1632
2026-01-29 02:53:01.827 [DEBUG] clck_gen.py:113 IND CLOCK 1734
2026-01-29 02:53:02.292 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:53:02.296 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:53:02.298 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 02:53:02.298 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 02:53:02.298 [INFO] transceiver.py:205 (MS@172.18.28.22:6700) Frequency hopping disabled
2026-01-29 02:53:02.306 [DEBUG] clck_gen.py:113 IND CLOCK 1836
2026-01-29 02:53:02.316 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 02:53:02.316 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:53:02.317 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:53:02.317 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:53:02.319 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 02:53:02.319 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:53:02.319 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:53:02.319 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:53:02.320 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.28.20:5700) Recv POWEROFF cmd
2026-01-29 02:53:02.320 [INFO] ctrl_if_trx.py:117 (BTS@172.18.28.20:5700) Stopping transceiver...
2026-01-29 02:53:02.320 [INFO] transceiver.py:246 Stopping clock generator
2026-01-29 02:53:02.320 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=1840 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:53:02.320 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=1840 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:53:02.320 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=1840 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:53:02.320 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=1840 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:53:02.320 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=1840 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:53:02.320 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=1840 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:53:02.321 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=1840 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:53:07.320 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.28.20:5700) Recv POWEROFF cmd
2026-01-29 02:53:07.320 [INFO] ctrl_if_trx.py:117 (BTS@172.18.28.20:5700) Stopping transceiver...
2026-01-29 02:53:07.322 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:53:07.323 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:53:07.323 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:53:07.323 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 02:53:07.330 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 02:53:07.331 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.28.20:5700) Recv SETFORMAT cmd
2026-01-29 02:53:07.331 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.28.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:53:07.331 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.28.20:5700) Recv SETFORMAT cmd
2026-01-29 02:53:07.331 [INFO] ctrl_if_trx.py:201 (BTS@172.18.28.20:5700) TRXD header version 1 -> 1
2026-01-29 02:53:07.333 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.28.20:5700/1) Recv RXTUNE cmd
2026-01-29 02:53:07.333 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.28.20:5700/1) Recv TXTUNE cmd
2026-01-29 02:53:07.333 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.28.20:5700/1) Recv SETFORMAT cmd
2026-01-29 02:53:07.333 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.28.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:53:07.334 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:53:07.334 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.28.20:5700/1) Recv NOMTXPOWER cmd
2026-01-29 02:53:07.334 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.28.20:5700/1) Recv SETFORMAT cmd
2026-01-29 02:53:07.334 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.28.20:5700/1) TRXD header version 1 -> 1
2026-01-29 02:53:07.335 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.28.20:5700/2) Recv RXTUNE cmd
2026-01-29 02:53:07.335 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.28.20:5700/2) Recv TXTUNE cmd
2026-01-29 02:53:07.335 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.28.20:5700/2) Recv SETFORMAT cmd
2026-01-29 02:53:07.335 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.28.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:53:07.335 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:53:07.336 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.28.20:5700/2) Recv NOMTXPOWER cmd
2026-01-29 02:53:07.336 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.28.20:5700/2) Recv SETFORMAT cmd
2026-01-29 02:53:07.336 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.28.20:5700/2) TRXD header version 1 -> 1
2026-01-29 02:53:07.337 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.28.20:5700/3) Recv RXTUNE cmd
2026-01-29 02:53:07.337 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.28.20:5700/3) Recv TXTUNE cmd
2026-01-29 02:53:07.337 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.28.20:5700/3) Recv SETFORMAT cmd
2026-01-29 02:53:07.337 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.28.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:53:07.337 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:53:07.337 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.28.20:5700/3) Recv NOMTXPOWER cmd
2026-01-29 02:53:07.338 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.28.20:5700/3) Recv SETFORMAT cmd
2026-01-29 02:53:07.338 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.28.20:5700/3) TRXD header version 1 -> 1
2026-01-29 02:53:07.340 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.28.20:5700) Recv RXTUNE cmd
2026-01-29 02:53:07.340 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETTSC
2026-01-29 02:53:07.340 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETTSC
2026-01-29 02:53:07.340 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETTSC
2026-01-29 02:53:07.340 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.28.20:5700) Recv TXTUNE cmd
2026-01-29 02:53:07.340 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETRXGAIN
2026-01-29 02:53:07.340 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETRXGAIN
2026-01-29 02:53:07.340 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETRXGAIN
2026-01-29 02:53:07.340 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETTSC
2026-01-29 02:53:07.340 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:53:07.340 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:53:07.340 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.28.20:5700) Recv NOMTXPOWER cmd
2026-01-29 02:53:07.340 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:53:07.340 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:53:07.340 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:53:07.340 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.28.20:5700) Recv POWERON CMD
2026-01-29 02:53:07.340 [INFO] ctrl_if_trx.py:109 (BTS@172.18.28.20:5700) Starting transceiver...
2026-01-29 02:53:07.340 [INFO] transceiver.py:243 Starting clock generator
2026-01-29 02:53:07.340 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-01-29 02:53:07.340 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:53:07.340 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:53:07.340 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:53:07.341 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETRXGAIN
2026-01-29 02:53:07.341 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:53:07.341 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:53:07.341 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:53:07.341 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:53:07.341 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:53:07.341 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:53:07.341 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:53:07.341 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:53:07.341 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:53:07.341 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:53:07.341 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:53:07.341 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:53:07.341 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:53:07.341 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:53:07.341 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:53:07.341 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:53:07.341 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:53:07.341 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:53:07.341 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:53:07.341 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:53:07.341 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:53:07.341 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:53:07.341 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:53:07.341 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:53:07.345 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-01-29 02:53:07.828 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-01-29 02:53:07.857 [DEBUG] fake_trx.py:278 (BTS@172.18.28.20:5700) Recv FAKE_TOA cmd
2026-01-29 02:53:07.858 [DEBUG] fake_trx.py:297 (BTS@172.18.28.20:5700) Recv FAKE_RSSI cmd
2026-01-29 02:53:07.859 [DEBUG] fake_trx.py:322 (BTS@172.18.28.20:5700) Recv FAKE_CI cmd
2026-01-29 02:53:07.859 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:53:07.874 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 02:53:07.874 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 02:53:07.875 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 02:53:07.880 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:53:07.880 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 02:53:07.880 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 02:53:07.880 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.28.22:6700) Recv POWERON CMD
2026-01-29 02:53:07.880 [INFO] ctrl_if_trx.py:109 (MS@172.18.28.22:6700) Starting transceiver...
2026-01-29 02:53:08.082 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 02:53:08.082 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 02:53:08.085 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 02:53:08.085 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:53:08.085 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:53:08.085 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:53:08.088 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 02:53:08.088 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:53:08.088 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:53:08.088 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:53:08.088 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.28.20:5700) Recv POWEROFF cmd
2026-01-29 02:53:08.088 [INFO] ctrl_if_trx.py:117 (BTS@172.18.28.20:5700) Stopping transceiver...
2026-01-29 02:53:08.088 [INFO] transceiver.py:246 Stopping clock generator
2026-01-29 02:53:08.088 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=159 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:53:08.088 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=159 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:53:08.088 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=159 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:53:08.088 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=159 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:53:08.088 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=159 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:53:08.088 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=159 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:53:08.088 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=160 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:53:08.088 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=160 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:53:08.088 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=160 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:53:08.088 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=160 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:53:08.088 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=160 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:53:08.088 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=160 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:53:08.088 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=160 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:53:08.089 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=160 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:53:13.089 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.28.20:5700) Recv POWEROFF cmd
2026-01-29 02:53:13.089 [INFO] ctrl_if_trx.py:117 (BTS@172.18.28.20:5700) Stopping transceiver...
2026-01-29 02:53:13.091 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:53:13.092 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:53:13.093 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:53:13.093 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 02:53:13.102 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 02:53:13.103 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.28.20:5700) Recv SETFORMAT cmd
2026-01-29 02:53:13.104 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.28.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:53:13.104 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.28.20:5700) Recv SETFORMAT cmd
2026-01-29 02:53:13.104 [INFO] ctrl_if_trx.py:201 (BTS@172.18.28.20:5700) TRXD header version 1 -> 1
2026-01-29 02:53:13.108 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.28.20:5700/1) Recv RXTUNE cmd
2026-01-29 02:53:13.109 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.28.20:5700/1) Recv TXTUNE cmd
2026-01-29 02:53:13.109 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.28.20:5700/1) Recv SETFORMAT cmd
2026-01-29 02:53:13.109 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.28.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:53:13.110 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:53:13.110 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.28.20:5700/1) Recv NOMTXPOWER cmd
2026-01-29 02:53:13.111 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.28.20:5700/1) Recv SETFORMAT cmd
2026-01-29 02:53:13.111 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.28.20:5700/1) TRXD header version 1 -> 1
2026-01-29 02:53:13.112 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.28.20:5700/2) Recv RXTUNE cmd
2026-01-29 02:53:13.112 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.28.20:5700/2) Recv TXTUNE cmd
2026-01-29 02:53:13.112 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.28.20:5700/2) Recv SETFORMAT cmd
2026-01-29 02:53:13.112 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.28.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:53:13.113 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:53:13.113 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.28.20:5700/2) Recv NOMTXPOWER cmd
2026-01-29 02:53:13.113 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.28.20:5700/2) Recv SETFORMAT cmd
2026-01-29 02:53:13.113 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.28.20:5700/2) TRXD header version 1 -> 1
2026-01-29 02:53:13.114 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.28.20:5700/3) Recv RXTUNE cmd
2026-01-29 02:53:13.114 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.28.20:5700/3) Recv TXTUNE cmd
2026-01-29 02:53:13.114 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.28.20:5700/3) Recv SETFORMAT cmd
2026-01-29 02:53:13.114 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.28.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:53:13.115 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:53:13.115 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.28.20:5700/3) Recv NOMTXPOWER cmd
2026-01-29 02:53:13.115 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.28.20:5700/3) Recv SETFORMAT cmd
2026-01-29 02:53:13.115 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.28.20:5700/3) TRXD header version 1 -> 1
2026-01-29 02:53:13.117 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.28.20:5700) Recv RXTUNE cmd
2026-01-29 02:53:13.117 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETTSC
2026-01-29 02:53:13.117 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETTSC
2026-01-29 02:53:13.117 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETTSC
2026-01-29 02:53:13.117 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.28.20:5700) Recv TXTUNE cmd
2026-01-29 02:53:13.117 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETRXGAIN
2026-01-29 02:53:13.118 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETRXGAIN
2026-01-29 02:53:13.118 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETRXGAIN
2026-01-29 02:53:13.118 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETTSC
2026-01-29 02:53:13.118 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:53:13.118 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:53:13.118 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:53:13.118 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.28.20:5700) Recv NOMTXPOWER cmd
2026-01-29 02:53:13.118 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:53:13.118 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.28.20:5700) Recv POWERON CMD
2026-01-29 02:53:13.118 [INFO] ctrl_if_trx.py:109 (BTS@172.18.28.20:5700) Starting transceiver...
2026-01-29 02:53:13.118 [INFO] transceiver.py:243 Starting clock generator
2026-01-29 02:53:13.118 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-01-29 02:53:13.118 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:53:13.118 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:53:13.118 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:53:13.118 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETRXGAIN
2026-01-29 02:53:13.118 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:53:13.118 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:53:13.119 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:53:13.119 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:53:13.119 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:53:13.119 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:53:13.119 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:53:13.119 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:53:13.119 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:53:13.119 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:53:13.119 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:53:13.119 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:53:13.119 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:53:13.119 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:53:13.119 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:53:13.119 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:53:13.119 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:53:13.119 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:53:13.119 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:53:13.119 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:53:13.119 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:53:13.119 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:53:13.119 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:53:13.119 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:53:13.119 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:53:13.123 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-01-29 02:53:13.607 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-01-29 02:53:13.650 [DEBUG] fake_trx.py:278 (BTS@172.18.28.20:5700) Recv FAKE_TOA cmd
2026-01-29 02:53:13.653 [DEBUG] fake_trx.py:297 (BTS@172.18.28.20:5700) Recv FAKE_RSSI cmd
2026-01-29 02:53:13.655 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:53:13.655 [DEBUG] fake_trx.py:322 (BTS@172.18.28.20:5700) Recv FAKE_CI cmd
2026-01-29 02:53:13.678 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 02:53:13.678 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 02:53:13.678 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 02:53:13.687 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:53:13.687 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 02:53:13.687 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 02:53:13.687 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.28.22:6700) Recv POWERON CMD
2026-01-29 02:53:13.687 [INFO] ctrl_if_trx.py:109 (MS@172.18.28.22:6700) Starting transceiver...
2026-01-29 02:53:14.084 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-01-29 02:53:14.120 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 02:53:14.121 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:53:14.122 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:53:14.126 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:53:14.562 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-01-29 02:53:15.040 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-01-29 02:53:15.122 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 02:53:15.122 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:53:15.123 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:53:15.128 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:53:15.518 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-01-29 02:53:15.996 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-01-29 02:53:16.123 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 02:53:16.123 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:53:16.124 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:53:16.128 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:53:16.473 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-01-29 02:53:16.952 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-01-29 02:53:17.123 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 02:53:17.124 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:53:17.124 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:53:17.130 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:53:17.429 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-01-29 02:53:17.907 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-01-29 02:53:18.124 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 02:53:18.125 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:53:18.125 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:53:18.130 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:53:18.171 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 02:53:18.172 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:53:18.172 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:53:18.172 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:53:18.175 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 02:53:18.175 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:53:18.175 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:53:18.175 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:53:18.175 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.28.20:5700) Recv POWEROFF cmd
2026-01-29 02:53:18.175 [INFO] ctrl_if_trx.py:117 (BTS@172.18.28.20:5700) Stopping transceiver...
2026-01-29 02:53:18.176 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=1080 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:53:18.176 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=1080 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:53:18.176 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=1080 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:53:18.176 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=1080 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:53:18.176 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=1080 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:53:18.176 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=1080 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:53:18.176 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=1080 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:53:18.388 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-01-29 02:53:18.873 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-01-29 02:53:19.359 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-01-29 02:53:19.844 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-01-29 02:53:20.329 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-01-29 02:53:20.815 [DEBUG] clck_gen.py:113 IND CLOCK 1632
2026-01-29 02:53:21.300 [DEBUG] clck_gen.py:113 IND CLOCK 1734
2026-01-29 02:53:21.786 [DEBUG] clck_gen.py:113 IND CLOCK 1836
2026-01-29 02:53:22.272 [DEBUG] clck_gen.py:113 IND CLOCK 1938
2026-01-29 02:53:22.758 [DEBUG] clck_gen.py:113 IND CLOCK 2040
2026-01-29 02:53:23.174 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.28.20:5700) Recv POWEROFF cmd
2026-01-29 02:53:23.174 [INFO] ctrl_if_trx.py:117 (BTS@172.18.28.20:5700) Stopping transceiver...
2026-01-29 02:53:23.175 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 02:53:23.175 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 02:53:23.175 [INFO] transceiver.py:246 Stopping clock generator
2026-01-29 02:53:23.176 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:53:23.177 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:53:23.179 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:53:23.179 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 02:53:23.182 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 02:53:23.182 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.28.20:5700) Recv SETFORMAT cmd
2026-01-29 02:53:23.182 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.28.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:53:23.182 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.28.20:5700) Recv SETFORMAT cmd
2026-01-29 02:53:23.182 [INFO] ctrl_if_trx.py:201 (BTS@172.18.28.20:5700) TRXD header version 1 -> 1
2026-01-29 02:53:23.183 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.28.20:5700/1) Recv RXTUNE cmd
2026-01-29 02:53:23.183 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.28.20:5700/1) Recv TXTUNE cmd
2026-01-29 02:53:23.183 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.28.20:5700/1) Recv SETFORMAT cmd
2026-01-29 02:53:23.183 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.28.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:53:23.183 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:53:23.183 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.28.20:5700/1) Recv NOMTXPOWER cmd
2026-01-29 02:53:23.183 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.28.20:5700/1) Recv SETFORMAT cmd
2026-01-29 02:53:23.183 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.28.20:5700/1) TRXD header version 1 -> 1
2026-01-29 02:53:23.184 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.28.20:5700/2) Recv RXTUNE cmd
2026-01-29 02:53:23.184 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.28.20:5700/2) Recv TXTUNE cmd
2026-01-29 02:53:23.184 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.28.20:5700/2) Recv SETFORMAT cmd
2026-01-29 02:53:23.184 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.28.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:53:23.184 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:53:23.184 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.28.20:5700/2) Recv NOMTXPOWER cmd
2026-01-29 02:53:23.184 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.28.20:5700/2) Recv SETFORMAT cmd
2026-01-29 02:53:23.184 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.28.20:5700/2) TRXD header version 1 -> 1
2026-01-29 02:53:23.185 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.28.20:5700/3) Recv RXTUNE cmd
2026-01-29 02:53:23.185 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.28.20:5700/3) Recv TXTUNE cmd
2026-01-29 02:53:23.185 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.28.20:5700/3) Recv SETFORMAT cmd
2026-01-29 02:53:23.185 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.28.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:53:23.185 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:53:23.185 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.28.20:5700/3) Recv NOMTXPOWER cmd
2026-01-29 02:53:23.185 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.28.20:5700/3) Recv SETFORMAT cmd
2026-01-29 02:53:23.185 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.28.20:5700/3) TRXD header version 1 -> 1
2026-01-29 02:53:23.186 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.28.20:5700) Recv RXTUNE cmd
2026-01-29 02:53:23.186 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETTSC
2026-01-29 02:53:23.186 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETTSC
2026-01-29 02:53:23.186 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETTSC
2026-01-29 02:53:23.186 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.28.20:5700) Recv TXTUNE cmd
2026-01-29 02:53:23.186 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETRXGAIN
2026-01-29 02:53:23.186 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETRXGAIN
2026-01-29 02:53:23.186 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETRXGAIN
2026-01-29 02:53:23.186 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETTSC
2026-01-29 02:53:23.186 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:53:23.186 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:53:23.186 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:53:23.186 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.28.20:5700) Recv NOMTXPOWER cmd
2026-01-29 02:53:23.186 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:53:23.186 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:53:23.186 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:53:23.187 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.28.20:5700) Recv POWERON CMD
2026-01-29 02:53:23.187 [INFO] ctrl_if_trx.py:109 (BTS@172.18.28.20:5700) Starting transceiver...
2026-01-29 02:53:23.187 [INFO] transceiver.py:243 Starting clock generator
2026-01-29 02:53:23.187 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-01-29 02:53:23.187 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:53:23.187 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:53:23.187 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:53:23.187 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETRXGAIN
2026-01-29 02:53:23.187 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:53:23.187 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:53:23.187 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:53:23.187 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:53:23.187 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:53:23.187 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:53:23.187 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:53:23.187 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:53:23.187 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:53:23.187 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:53:23.187 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:53:23.188 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:53:23.188 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:53:23.188 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:53:23.188 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:53:23.188 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:53:23.188 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:53:23.188 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:53:23.188 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:53:23.188 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:53:23.188 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:53:23.188 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:53:23.188 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:53:23.188 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 02:53:23.188 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:53:23.188 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.28.20:5700) Recv POWEROFF cmd
2026-01-29 02:53:23.188 [INFO] ctrl_if_trx.py:117 (BTS@172.18.28.20:5700) Stopping transceiver...
2026-01-29 02:53:23.188 [INFO] transceiver.py:246 Stopping clock generator
2026-01-29 02:53:23.188 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:53:23.188 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:53:28.191 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.28.20:5700) Recv POWEROFF cmd
2026-01-29 02:53:28.191 [INFO] ctrl_if_trx.py:117 (BTS@172.18.28.20:5700) Stopping transceiver...
2026-01-29 02:53:28.193 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:53:28.193 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:53:28.194 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:53:28.194 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 02:53:28.203 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 02:53:28.204 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.28.20:5700) Recv SETFORMAT cmd
2026-01-29 02:53:28.204 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.28.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:53:28.205 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.28.20:5700) Recv SETFORMAT cmd
2026-01-29 02:53:28.205 [INFO] ctrl_if_trx.py:201 (BTS@172.18.28.20:5700) TRXD header version 1 -> 1
2026-01-29 02:53:28.208 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.28.20:5700/1) Recv RXTUNE cmd
2026-01-29 02:53:28.208 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.28.20:5700/1) Recv TXTUNE cmd
2026-01-29 02:53:28.209 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.28.20:5700/1) Recv SETFORMAT cmd
2026-01-29 02:53:28.209 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.28.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:53:28.209 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:53:28.210 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.28.20:5700/1) Recv NOMTXPOWER cmd
2026-01-29 02:53:28.210 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.28.20:5700/1) Recv SETFORMAT cmd
2026-01-29 02:53:28.210 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.28.20:5700/1) TRXD header version 1 -> 1
2026-01-29 02:53:28.211 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.28.20:5700/2) Recv RXTUNE cmd
2026-01-29 02:53:28.211 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.28.20:5700/2) Recv TXTUNE cmd
2026-01-29 02:53:28.212 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.28.20:5700/2) Recv SETFORMAT cmd
2026-01-29 02:53:28.212 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.28.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:53:28.212 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:53:28.212 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.28.20:5700/2) Recv NOMTXPOWER cmd
2026-01-29 02:53:28.213 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.28.20:5700/2) Recv SETFORMAT cmd
2026-01-29 02:53:28.213 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.28.20:5700/2) TRXD header version 1 -> 1
2026-01-29 02:53:28.214 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.28.20:5700/3) Recv RXTUNE cmd
2026-01-29 02:53:28.214 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.28.20:5700/3) Recv TXTUNE cmd
2026-01-29 02:53:28.214 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.28.20:5700/3) Recv SETFORMAT cmd
2026-01-29 02:53:28.214 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.28.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:53:28.214 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:53:28.214 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.28.20:5700/3) Recv NOMTXPOWER cmd
2026-01-29 02:53:28.214 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.28.20:5700/3) Recv SETFORMAT cmd
2026-01-29 02:53:28.214 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.28.20:5700/3) TRXD header version 1 -> 1
2026-01-29 02:53:28.217 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.28.20:5700) Recv RXTUNE cmd
2026-01-29 02:53:28.217 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETTSC
2026-01-29 02:53:28.217 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETTSC
2026-01-29 02:53:28.217 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETTSC
2026-01-29 02:53:28.217 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.28.20:5700) Recv TXTUNE cmd
2026-01-29 02:53:28.217 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETRXGAIN
2026-01-29 02:53:28.217 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETRXGAIN
2026-01-29 02:53:28.217 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETRXGAIN
2026-01-29 02:53:28.217 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETTSC
2026-01-29 02:53:28.217 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:53:28.217 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:53:28.217 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:53:28.217 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.28.20:5700) Recv NOMTXPOWER cmd
2026-01-29 02:53:28.217 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:53:28.217 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:53:28.217 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:53:28.217 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.28.20:5700) Recv POWERON CMD
2026-01-29 02:53:28.217 [INFO] ctrl_if_trx.py:109 (BTS@172.18.28.20:5700) Starting transceiver...
2026-01-29 02:53:28.217 [INFO] transceiver.py:243 Starting clock generator
2026-01-29 02:53:28.217 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-01-29 02:53:28.217 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:53:28.217 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:53:28.218 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:53:28.218 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETRXGAIN
2026-01-29 02:53:28.218 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:53:28.218 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:53:28.218 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:53:28.218 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:53:28.218 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:53:28.218 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:53:28.218 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:53:28.218 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:53:28.218 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:53:28.218 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:53:28.218 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:53:28.218 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:53:28.218 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:53:28.218 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:53:28.218 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:53:28.218 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:53:28.218 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:53:28.218 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:53:28.218 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:53:28.218 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:53:28.218 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:53:28.218 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:53:28.218 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:53:28.222 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-01-29 02:53:28.706 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-01-29 02:53:28.742 [DEBUG] fake_trx.py:278 (BTS@172.18.28.20:5700) Recv FAKE_TOA cmd
2026-01-29 02:53:28.743 [DEBUG] fake_trx.py:297 (BTS@172.18.28.20:5700) Recv FAKE_RSSI cmd
2026-01-29 02:53:28.744 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:53:28.744 [DEBUG] fake_trx.py:322 (BTS@172.18.28.20:5700) Recv FAKE_CI cmd
2026-01-29 02:53:28.755 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 02:53:28.755 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 02:53:28.755 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 02:53:28.761 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:53:28.761 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 02:53:28.761 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 02:53:28.761 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.28.22:6700) Recv POWERON CMD
2026-01-29 02:53:28.761 [INFO] ctrl_if_trx.py:109 (MS@172.18.28.22:6700) Starting transceiver...
2026-01-29 02:53:29.183 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-01-29 02:53:29.220 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 02:53:29.220 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:53:29.221 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:53:29.224 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:53:29.660 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-01-29 02:53:30.138 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-01-29 02:53:30.220 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 02:53:30.221 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:53:30.222 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:53:30.225 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:53:30.616 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-01-29 02:53:31.094 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-01-29 02:53:31.222 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 02:53:31.222 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:53:31.222 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:53:31.226 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:53:31.571 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-01-29 02:53:32.049 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-01-29 02:53:32.223 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:53:32.223 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:53:32.224 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 02:53:32.228 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:53:32.526 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-01-29 02:53:33.004 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-01-29 02:53:33.224 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 02:53:33.224 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:53:33.225 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:53:33.229 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:53:33.482 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-01-29 02:53:33.960 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-01-29 02:53:34.259 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 02:53:34.438 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-01-29 02:53:34.915 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-01-29 02:53:35.259 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 02:53:35.389 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-01-29 02:53:35.858 [DEBUG] clck_gen.py:113 IND CLOCK 1632
2026-01-29 02:53:36.260 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 02:53:36.335 [DEBUG] clck_gen.py:113 IND CLOCK 1734
2026-01-29 02:53:36.813 [DEBUG] clck_gen.py:113 IND CLOCK 1836
2026-01-29 02:53:37.261 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 02:53:37.291 [DEBUG] clck_gen.py:113 IND CLOCK 1938
2026-01-29 02:53:37.769 [DEBUG] clck_gen.py:113 IND CLOCK 2040
2026-01-29 02:53:38.246 [DEBUG] clck_gen.py:113 IND CLOCK 2142
2026-01-29 02:53:38.261 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 02:53:38.262 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 02:53:38.721 [DEBUG] clck_gen.py:113 IND CLOCK 2244
2026-01-29 02:53:39.199 [DEBUG] clck_gen.py:113 IND CLOCK 2346
2026-01-29 02:53:39.677 [DEBUG] clck_gen.py:113 IND CLOCK 2448
2026-01-29 02:53:40.155 [DEBUG] clck_gen.py:113 IND CLOCK 2550
2026-01-29 02:53:40.637 [DEBUG] clck_gen.py:113 IND CLOCK 2652
2026-01-29 02:53:41.117 [DEBUG] clck_gen.py:113 IND CLOCK 2754
2026-01-29 02:53:41.311 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 02:53:41.596 [DEBUG] clck_gen.py:113 IND CLOCK 2856
2026-01-29 02:53:42.074 [DEBUG] clck_gen.py:113 IND CLOCK 2958
2026-01-29 02:53:42.311 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 02:53:42.552 [DEBUG] clck_gen.py:113 IND CLOCK 3060
2026-01-29 02:53:43.029 [DEBUG] clck_gen.py:113 IND CLOCK 3162
2026-01-29 02:53:43.311 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 02:53:43.507 [DEBUG] clck_gen.py:113 IND CLOCK 3264
2026-01-29 02:53:43.985 [DEBUG] clck_gen.py:113 IND CLOCK 3366
2026-01-29 02:53:44.312 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 02:53:44.462 [DEBUG] clck_gen.py:113 IND CLOCK 3468
2026-01-29 02:53:44.940 [DEBUG] clck_gen.py:113 IND CLOCK 3570
2026-01-29 02:53:45.314 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 02:53:45.418 [DEBUG] clck_gen.py:113 IND CLOCK 3672
2026-01-29 02:53:45.895 [DEBUG] clck_gen.py:113 IND CLOCK 3774
2026-01-29 02:53:46.314 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 02:53:46.373 [DEBUG] clck_gen.py:113 IND CLOCK 3876
2026-01-29 02:53:46.851 [DEBUG] clck_gen.py:113 IND CLOCK 3978
2026-01-29 02:53:47.328 [DEBUG] clck_gen.py:113 IND CLOCK 4080
2026-01-29 02:53:47.805 [DEBUG] clck_gen.py:113 IND CLOCK 4182
2026-01-29 02:53:48.282 [DEBUG] clck_gen.py:113 IND CLOCK 4284
2026-01-29 02:53:48.390 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 02:53:48.390 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 02:53:48.401 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 02:53:48.401 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:53:48.401 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:53:48.401 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:53:48.401 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 02:53:48.401 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:53:48.401 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:53:48.401 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:53:48.401 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.28.20:5700) Recv POWEROFF cmd
2026-01-29 02:53:48.401 [INFO] ctrl_if_trx.py:117 (BTS@172.18.28.20:5700) Stopping transceiver...
2026-01-29 02:53:48.401 [INFO] transceiver.py:246 Stopping clock generator
2026-01-29 02:53:53.403 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.28.20:5700) Recv POWEROFF cmd
2026-01-29 02:53:53.403 [INFO] ctrl_if_trx.py:117 (BTS@172.18.28.20:5700) Stopping transceiver...
2026-01-29 02:53:53.403 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:53:53.404 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:53:53.404 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:53:53.405 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 02:53:53.408 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 02:53:53.408 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.28.20:5700) Recv SETFORMAT cmd
2026-01-29 02:53:53.408 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.28.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:53:53.408 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.28.20:5700) Recv SETFORMAT cmd
2026-01-29 02:53:53.408 [INFO] ctrl_if_trx.py:201 (BTS@172.18.28.20:5700) TRXD header version 1 -> 1
2026-01-29 02:53:53.409 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.28.20:5700/1) Recv RXTUNE cmd
2026-01-29 02:53:53.409 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.28.20:5700/1) Recv TXTUNE cmd
2026-01-29 02:53:53.409 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.28.20:5700/1) Recv SETFORMAT cmd
2026-01-29 02:53:53.409 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.28.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:53:53.409 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:53:53.409 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.28.20:5700/1) Recv NOMTXPOWER cmd
2026-01-29 02:53:53.409 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.28.20:5700/1) Recv SETFORMAT cmd
2026-01-29 02:53:53.409 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.28.20:5700/1) TRXD header version 1 -> 1
2026-01-29 02:53:53.410 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.28.20:5700/2) Recv RXTUNE cmd
2026-01-29 02:53:53.410 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.28.20:5700/2) Recv TXTUNE cmd
2026-01-29 02:53:53.410 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.28.20:5700/2) Recv SETFORMAT cmd
2026-01-29 02:53:53.410 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.28.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:53:53.410 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:53:53.410 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.28.20:5700/2) Recv NOMTXPOWER cmd
2026-01-29 02:53:53.410 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.28.20:5700/2) Recv SETFORMAT cmd
2026-01-29 02:53:53.410 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.28.20:5700/2) TRXD header version 1 -> 1
2026-01-29 02:53:53.411 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.28.20:5700/3) Recv RXTUNE cmd
2026-01-29 02:53:53.411 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.28.20:5700/3) Recv TXTUNE cmd
2026-01-29 02:53:53.411 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.28.20:5700/3) Recv SETFORMAT cmd
2026-01-29 02:53:53.411 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.28.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:53:53.411 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:53:53.411 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.28.20:5700/3) Recv NOMTXPOWER cmd
2026-01-29 02:53:53.411 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.28.20:5700/3) Recv SETFORMAT cmd
2026-01-29 02:53:53.411 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.28.20:5700/3) TRXD header version 1 -> 1
2026-01-29 02:53:53.413 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.28.20:5700) Recv RXTUNE cmd
2026-01-29 02:53:53.413 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETTSC
2026-01-29 02:53:53.413 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETTSC
2026-01-29 02:53:53.413 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETTSC
2026-01-29 02:53:53.413 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.28.20:5700) Recv TXTUNE cmd
2026-01-29 02:53:53.414 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETRXGAIN
2026-01-29 02:53:53.414 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETRXGAIN
2026-01-29 02:53:53.414 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETRXGAIN
2026-01-29 02:53:53.414 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETTSC
2026-01-29 02:53:53.414 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:53:53.414 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:53:53.414 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.28.20:5700) Recv NOMTXPOWER cmd
2026-01-29 02:53:53.414 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:53:53.414 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:53:53.414 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:53:53.414 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.28.20:5700) Recv POWERON CMD
2026-01-29 02:53:53.414 [INFO] ctrl_if_trx.py:109 (BTS@172.18.28.20:5700) Starting transceiver...
2026-01-29 02:53:53.414 [INFO] transceiver.py:243 Starting clock generator
2026-01-29 02:53:53.414 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-01-29 02:53:53.414 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:53:53.414 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:53:53.414 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:53:53.414 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETRXGAIN
2026-01-29 02:53:53.414 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:53:53.415 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:53:53.415 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:53:53.415 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:53:53.415 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:53:53.415 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:53:53.415 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:53:53.415 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:53:53.415 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:53:53.415 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:53:53.415 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:53:53.415 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:53:53.415 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:53:53.415 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:53:53.415 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:53:53.415 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:53:53.415 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:53:53.415 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:53:53.415 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:53:53.415 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:53:53.415 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:53:53.415 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:53:53.415 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:53:53.415 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:53:53.419 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-01-29 02:53:53.902 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-01-29 02:53:53.946 [DEBUG] fake_trx.py:278 (BTS@172.18.28.20:5700) Recv FAKE_TOA cmd
2026-01-29 02:53:53.948 [DEBUG] fake_trx.py:297 (BTS@172.18.28.20:5700) Recv FAKE_RSSI cmd
2026-01-29 02:53:53.950 [DEBUG] fake_trx.py:322 (BTS@172.18.28.20:5700) Recv FAKE_CI cmd
2026-01-29 02:53:53.950 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:53:53.968 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 02:53:53.969 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 02:53:53.969 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 02:53:53.974 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:53:53.974 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 02:53:53.974 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 02:53:53.974 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.28.22:6700) Recv POWERON CMD
2026-01-29 02:53:53.974 [INFO] ctrl_if_trx.py:109 (MS@172.18.28.22:6700) Starting transceiver...
2026-01-29 02:53:53.994 [DEBUG] fake_trx.py:297 (BTS@172.18.28.20:5700) Recv FAKE_RSSI cmd
2026-01-29 02:53:53.998 [DEBUG] fake_trx.py:278 (BTS@172.18.28.20:5700) Recv FAKE_TOA cmd
2026-01-29 02:53:54.004 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD NOHANDOVER
2026-01-29 02:53:54.007 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 02:53:54.008 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 02:53:54.008 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:53:54.008 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:53:54.378 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-01-29 02:53:54.417 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 02:53:54.418 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:53:54.420 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:53:54.425 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:53:54.858 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-01-29 02:53:55.301 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD NOHANDOVER
2026-01-29 02:53:55.305 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:53:55.305 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 02:53:55.305 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 02:53:55.315 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 02:53:55.315 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:53:55.315 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:53:55.315 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:53:55.318 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 02:53:55.318 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:53:55.318 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:53:55.318 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:53:55.318 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.28.20:5700) Recv POWEROFF cmd
2026-01-29 02:53:55.318 [INFO] ctrl_if_trx.py:117 (BTS@172.18.28.20:5700) Stopping transceiver...
2026-01-29 02:53:55.318 [INFO] transceiver.py:246 Stopping clock generator
2026-01-29 02:53:55.318 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=407 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:53:55.318 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=407 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:53:55.318 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=407 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:53:55.318 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=407 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:53:55.318 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=407 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:53:55.318 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=407 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:53:55.318 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=407 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:54:00.318 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.28.20:5700) Recv POWEROFF cmd
2026-01-29 02:54:00.318 [INFO] ctrl_if_trx.py:117 (BTS@172.18.28.20:5700) Stopping transceiver...
2026-01-29 02:54:00.322 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:54:00.322 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 02:54:00.322 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:54:00.322 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:54:00.331 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 02:54:00.333 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.28.20:5700) Recv SETFORMAT cmd
2026-01-29 02:54:00.333 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.28.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:54:00.334 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.28.20:5700) Recv SETFORMAT cmd
2026-01-29 02:54:00.334 [INFO] ctrl_if_trx.py:201 (BTS@172.18.28.20:5700) TRXD header version 1 -> 1
2026-01-29 02:54:00.338 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.28.20:5700/1) Recv RXTUNE cmd
2026-01-29 02:54:00.339 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.28.20:5700/1) Recv TXTUNE cmd
2026-01-29 02:54:00.339 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.28.20:5700/1) Recv SETFORMAT cmd
2026-01-29 02:54:00.340 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.28.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:54:00.340 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:54:00.340 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.28.20:5700/1) Recv NOMTXPOWER cmd
2026-01-29 02:54:00.341 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.28.20:5700/1) Recv SETFORMAT cmd
2026-01-29 02:54:00.341 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.28.20:5700/1) TRXD header version 1 -> 1
2026-01-29 02:54:00.342 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.28.20:5700/2) Recv RXTUNE cmd
2026-01-29 02:54:00.343 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.28.20:5700/2) Recv TXTUNE cmd
2026-01-29 02:54:00.343 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.28.20:5700/2) Recv SETFORMAT cmd
2026-01-29 02:54:00.343 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.28.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:54:00.343 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:54:00.344 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.28.20:5700/2) Recv NOMTXPOWER cmd
2026-01-29 02:54:00.344 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.28.20:5700/2) Recv SETFORMAT cmd
2026-01-29 02:54:00.344 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.28.20:5700/2) TRXD header version 1 -> 1
2026-01-29 02:54:00.346 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.28.20:5700/3) Recv RXTUNE cmd
2026-01-29 02:54:00.346 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.28.20:5700/3) Recv TXTUNE cmd
2026-01-29 02:54:00.346 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.28.20:5700/3) Recv SETFORMAT cmd
2026-01-29 02:54:00.346 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.28.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:54:00.346 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:54:00.346 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.28.20:5700/3) Recv NOMTXPOWER cmd
2026-01-29 02:54:00.347 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.28.20:5700/3) Recv SETFORMAT cmd
2026-01-29 02:54:00.347 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.28.20:5700/3) TRXD header version 1 -> 1
2026-01-29 02:54:00.349 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.28.20:5700) Recv RXTUNE cmd
2026-01-29 02:54:00.349 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETTSC
2026-01-29 02:54:00.349 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETTSC
2026-01-29 02:54:00.349 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETTSC
2026-01-29 02:54:00.349 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.28.20:5700) Recv TXTUNE cmd
2026-01-29 02:54:00.349 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETRXGAIN
2026-01-29 02:54:00.349 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETRXGAIN
2026-01-29 02:54:00.349 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETRXGAIN
2026-01-29 02:54:00.350 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETTSC
2026-01-29 02:54:00.350 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:54:00.350 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:54:00.350 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:54:00.350 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.28.20:5700) Recv NOMTXPOWER cmd
2026-01-29 02:54:00.350 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:54:00.350 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:54:00.350 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:54:00.350 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.28.20:5700) Recv POWERON CMD
2026-01-29 02:54:00.350 [INFO] ctrl_if_trx.py:109 (BTS@172.18.28.20:5700) Starting transceiver...
2026-01-29 02:54:00.350 [INFO] transceiver.py:243 Starting clock generator
2026-01-29 02:54:00.350 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-01-29 02:54:00.350 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:54:00.350 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:54:00.350 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:54:00.350 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETRXGAIN
2026-01-29 02:54:00.350 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:54:00.350 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:54:00.351 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:54:00.351 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:54:00.351 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:54:00.351 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:54:00.351 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:54:00.351 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:54:00.351 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:54:00.351 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:54:00.351 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:54:00.351 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:54:00.351 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:54:00.351 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:54:00.351 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:54:00.351 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:54:00.351 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:54:00.351 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:54:00.351 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:54:00.351 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:54:00.351 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:54:00.351 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:54:00.351 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:54:00.355 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-01-29 02:54:00.839 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-01-29 02:54:00.874 [DEBUG] fake_trx.py:278 (BTS@172.18.28.20:5700) Recv FAKE_TOA cmd
2026-01-29 02:54:00.875 [DEBUG] fake_trx.py:297 (BTS@172.18.28.20:5700) Recv FAKE_RSSI cmd
2026-01-29 02:54:00.876 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:54:00.876 [DEBUG] fake_trx.py:322 (BTS@172.18.28.20:5700) Recv FAKE_CI cmd
2026-01-29 02:54:00.888 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 02:54:00.889 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 02:54:00.889 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 02:54:00.893 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:54:00.894 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 02:54:00.894 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 02:54:00.894 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.28.22:6700) Recv POWERON CMD
2026-01-29 02:54:00.894 [INFO] ctrl_if_trx.py:109 (MS@172.18.28.22:6700) Starting transceiver...
2026-01-29 02:54:00.930 [DEBUG] fake_trx.py:297 (BTS@172.18.28.20:5700) Recv FAKE_RSSI cmd
2026-01-29 02:54:00.934 [DEBUG] fake_trx.py:278 (BTS@172.18.28.20:5700) Recv FAKE_TOA cmd
2026-01-29 02:54:00.943 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD NOHANDOVER
2026-01-29 02:54:00.948 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 02:54:00.948 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 02:54:00.948 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:54:00.948 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:54:01.316 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-01-29 02:54:01.353 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:54:01.354 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 02:54:01.354 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:54:01.356 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:54:01.794 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-01-29 02:54:02.238 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD NOHANDOVER
2026-01-29 02:54:02.241 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:54:02.241 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 02:54:02.242 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 02:54:02.250 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 02:54:02.251 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:54:02.251 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:54:02.251 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:54:02.254 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 02:54:02.254 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:54:02.254 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:54:02.254 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:54:02.254 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.28.20:5700) Recv POWEROFF cmd
2026-01-29 02:54:02.255 [INFO] ctrl_if_trx.py:117 (BTS@172.18.28.20:5700) Stopping transceiver...
2026-01-29 02:54:02.255 [INFO] transceiver.py:246 Stopping clock generator
2026-01-29 02:54:02.255 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=407 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:54:02.255 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=407 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:54:02.255 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=407 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:54:02.255 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=407 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:54:02.256 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=407 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:54:02.256 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=407 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:54:02.256 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=407 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:54:02.256 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=407 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:54:07.254 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.28.20:5700) Recv POWEROFF cmd
2026-01-29 02:54:07.254 [INFO] ctrl_if_trx.py:117 (BTS@172.18.28.20:5700) Stopping transceiver...
2026-01-29 02:54:07.256 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:54:07.257 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:54:07.257 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:54:07.257 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 02:54:07.267 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 02:54:07.268 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.28.20:5700) Recv SETFORMAT cmd
2026-01-29 02:54:07.268 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.28.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:54:07.269 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.28.20:5700) Recv SETFORMAT cmd
2026-01-29 02:54:07.269 [INFO] ctrl_if_trx.py:201 (BTS@172.18.28.20:5700) TRXD header version 1 -> 1
2026-01-29 02:54:07.273 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.28.20:5700/1) Recv RXTUNE cmd
2026-01-29 02:54:07.273 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.28.20:5700/1) Recv TXTUNE cmd
2026-01-29 02:54:07.274 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.28.20:5700/1) Recv SETFORMAT cmd
2026-01-29 02:54:07.274 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.28.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:54:07.274 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:54:07.275 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.28.20:5700/1) Recv NOMTXPOWER cmd
2026-01-29 02:54:07.275 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.28.20:5700/1) Recv SETFORMAT cmd
2026-01-29 02:54:07.275 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.28.20:5700/1) TRXD header version 1 -> 1
2026-01-29 02:54:07.276 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.28.20:5700/2) Recv RXTUNE cmd
2026-01-29 02:54:07.276 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.28.20:5700/2) Recv TXTUNE cmd
2026-01-29 02:54:07.277 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.28.20:5700/2) Recv SETFORMAT cmd
2026-01-29 02:54:07.277 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.28.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:54:07.277 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:54:07.277 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.28.20:5700/2) Recv NOMTXPOWER cmd
2026-01-29 02:54:07.277 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.28.20:5700/2) Recv SETFORMAT cmd
2026-01-29 02:54:07.277 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.28.20:5700/2) TRXD header version 1 -> 1
2026-01-29 02:54:07.279 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.28.20:5700/3) Recv RXTUNE cmd
2026-01-29 02:54:07.279 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.28.20:5700/3) Recv TXTUNE cmd
2026-01-29 02:54:07.279 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.28.20:5700/3) Recv SETFORMAT cmd
2026-01-29 02:54:07.279 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.28.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:54:07.279 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:54:07.279 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.28.20:5700/3) Recv NOMTXPOWER cmd
2026-01-29 02:54:07.279 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.28.20:5700/3) Recv SETFORMAT cmd
2026-01-29 02:54:07.280 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.28.20:5700/3) TRXD header version 1 -> 1
2026-01-29 02:54:07.282 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.28.20:5700) Recv RXTUNE cmd
2026-01-29 02:54:07.282 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETTSC
2026-01-29 02:54:07.282 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETTSC
2026-01-29 02:54:07.282 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETTSC
2026-01-29 02:54:07.282 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.28.20:5700) Recv TXTUNE cmd
2026-01-29 02:54:07.282 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETRXGAIN
2026-01-29 02:54:07.282 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETRXGAIN
2026-01-29 02:54:07.282 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETRXGAIN
2026-01-29 02:54:07.282 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETTSC
2026-01-29 02:54:07.283 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:54:07.283 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:54:07.283 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:54:07.283 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.28.20:5700) Recv NOMTXPOWER cmd
2026-01-29 02:54:07.283 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:54:07.283 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:54:07.283 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:54:07.283 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.28.20:5700) Recv POWERON CMD
2026-01-29 02:54:07.283 [INFO] ctrl_if_trx.py:109 (BTS@172.18.28.20:5700) Starting transceiver...
2026-01-29 02:54:07.283 [INFO] transceiver.py:243 Starting clock generator
2026-01-29 02:54:07.283 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-01-29 02:54:07.283 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:54:07.283 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:54:07.283 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:54:07.283 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETRXGAIN
2026-01-29 02:54:07.283 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:54:07.283 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:54:07.283 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:54:07.283 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:54:07.283 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:54:07.283 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:54:07.284 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:54:07.284 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:54:07.284 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:54:07.284 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:54:07.284 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:54:07.284 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:54:07.284 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:54:07.284 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:54:07.284 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:54:07.284 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:54:07.284 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:54:07.284 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:54:07.284 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:54:07.284 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:54:07.284 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:54:07.284 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:54:07.284 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:54:07.288 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-01-29 02:54:07.771 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-01-29 02:54:07.803 [DEBUG] fake_trx.py:278 (BTS@172.18.28.20:5700) Recv FAKE_TOA cmd
2026-01-29 02:54:07.804 [DEBUG] fake_trx.py:297 (BTS@172.18.28.20:5700) Recv FAKE_RSSI cmd
2026-01-29 02:54:07.805 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:54:07.805 [DEBUG] fake_trx.py:322 (BTS@172.18.28.20:5700) Recv FAKE_CI cmd
2026-01-29 02:54:07.813 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 02:54:07.814 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 02:54:07.814 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 02:54:07.816 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:54:07.816 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 02:54:07.816 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 02:54:07.816 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.28.22:6700) Recv POWERON CMD
2026-01-29 02:54:07.816 [INFO] ctrl_if_trx.py:109 (MS@172.18.28.22:6700) Starting transceiver...
2026-01-29 02:54:07.868 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:54:07.873 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 02:54:07.873 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 02:54:07.874 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:54:07.874 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:54:08.249 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-01-29 02:54:08.285 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 02:54:08.286 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:54:08.287 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:54:08.290 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:54:08.726 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-01-29 02:54:09.204 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-01-29 02:54:09.286 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 02:54:09.287 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:54:09.288 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:54:09.291 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:54:09.682 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-01-29 02:54:10.159 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-01-29 02:54:10.287 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 02:54:10.287 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:54:10.289 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:54:10.292 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:54:10.637 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-01-29 02:54:11.115 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-01-29 02:54:11.287 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 02:54:11.288 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:54:11.290 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:54:11.294 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:54:11.593 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-01-29 02:54:12.072 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-01-29 02:54:12.289 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 02:54:12.289 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:54:12.290 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:54:12.294 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:54:12.550 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-01-29 02:54:13.028 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-01-29 02:54:13.506 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-01-29 02:54:13.984 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-01-29 02:54:14.462 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-01-29 02:54:14.939 [DEBUG] clck_gen.py:113 IND CLOCK 1632
2026-01-29 02:54:15.417 [DEBUG] clck_gen.py:113 IND CLOCK 1734
2026-01-29 02:54:15.896 [DEBUG] clck_gen.py:113 IND CLOCK 1836
2026-01-29 02:54:16.374 [DEBUG] clck_gen.py:113 IND CLOCK 1938
2026-01-29 02:54:16.851 [DEBUG] clck_gen.py:113 IND CLOCK 2040
2026-01-29 02:54:17.329 [DEBUG] clck_gen.py:113 IND CLOCK 2142
2026-01-29 02:54:17.806 [DEBUG] clck_gen.py:113 IND CLOCK 2244
2026-01-29 02:54:18.284 [DEBUG] clck_gen.py:113 IND CLOCK 2346
2026-01-29 02:54:18.762 [DEBUG] clck_gen.py:113 IND CLOCK 2448
2026-01-29 02:54:19.240 [DEBUG] clck_gen.py:113 IND CLOCK 2550
2026-01-29 02:54:19.718 [DEBUG] clck_gen.py:113 IND CLOCK 2652
2026-01-29 02:54:20.196 [DEBUG] clck_gen.py:113 IND CLOCK 2754
2026-01-29 02:54:20.673 [DEBUG] clck_gen.py:113 IND CLOCK 2856
2026-01-29 02:54:21.151 [DEBUG] clck_gen.py:113 IND CLOCK 2958
2026-01-29 02:54:21.629 [DEBUG] clck_gen.py:113 IND CLOCK 3060
2026-01-29 02:54:22.107 [DEBUG] clck_gen.py:113 IND CLOCK 3162
2026-01-29 02:54:22.586 [DEBUG] clck_gen.py:113 IND CLOCK 3264
2026-01-29 02:54:23.063 [DEBUG] clck_gen.py:113 IND CLOCK 3366
2026-01-29 02:54:23.541 [DEBUG] clck_gen.py:113 IND CLOCK 3468
2026-01-29 02:54:23.844 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:54:23.850 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:54:23.851 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 02:54:23.851 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 02:54:23.865 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 02:54:23.865 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 02:54:23.865 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 02:54:23.866 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:54:23.866 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 02:54:23.866 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 02:54:23.866 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.28.22:6700) Recv POWERON CMD
2026-01-29 02:54:23.866 [INFO] ctrl_if_trx.py:109 (MS@172.18.28.22:6700) Starting transceiver...
2026-01-29 02:54:23.916 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:54:23.917 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.28.22:6700) Recv SETFH cmd
2026-01-29 02:54:23.917 [INFO] transceiver.py:201 (MS@172.18.28.22:6700) Frequency hopping configured: hsn=2, maio=0, ma_len=2
2026-01-29 02:54:23.917 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:54:23.917 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:54:24.019 [DEBUG] clck_gen.py:113 IND CLOCK 3570
2026-01-29 02:54:24.497 [DEBUG] clck_gen.py:113 IND CLOCK 3672
2026-01-29 02:54:24.976 [DEBUG] clck_gen.py:113 IND CLOCK 3774
2026-01-29 02:54:25.454 [DEBUG] clck_gen.py:113 IND CLOCK 3876
2026-01-29 02:54:25.931 [DEBUG] clck_gen.py:113 IND CLOCK 3978
2026-01-29 02:54:26.410 [DEBUG] clck_gen.py:113 IND CLOCK 4080
2026-01-29 02:54:26.889 [DEBUG] clck_gen.py:113 IND CLOCK 4182
2026-01-29 02:54:27.367 [DEBUG] clck_gen.py:113 IND CLOCK 4284
2026-01-29 02:54:27.846 [DEBUG] clck_gen.py:113 IND CLOCK 4386
2026-01-29 02:54:28.324 [DEBUG] clck_gen.py:113 IND CLOCK 4488
2026-01-29 02:54:28.802 [DEBUG] clck_gen.py:113 IND CLOCK 4590
2026-01-29 02:54:29.281 [DEBUG] clck_gen.py:113 IND CLOCK 4692
2026-01-29 02:54:29.759 [DEBUG] clck_gen.py:113 IND CLOCK 4794
2026-01-29 02:54:30.237 [DEBUG] clck_gen.py:113 IND CLOCK 4896
2026-01-29 02:54:30.716 [DEBUG] clck_gen.py:113 IND CLOCK 4998
2026-01-29 02:54:31.194 [DEBUG] clck_gen.py:113 IND CLOCK 5100
2026-01-29 02:54:31.672 [DEBUG] clck_gen.py:113 IND CLOCK 5202
2026-01-29 02:54:32.151 [DEBUG] clck_gen.py:113 IND CLOCK 5304
2026-01-29 02:54:32.629 [DEBUG] clck_gen.py:113 IND CLOCK 5406
2026-01-29 02:54:33.107 [DEBUG] clck_gen.py:113 IND CLOCK 5508
2026-01-29 02:54:33.585 [DEBUG] clck_gen.py:113 IND CLOCK 5610
2026-01-29 02:54:34.064 [DEBUG] clck_gen.py:113 IND CLOCK 5712
2026-01-29 02:54:34.542 [DEBUG] clck_gen.py:113 IND CLOCK 5814
2026-01-29 02:54:35.020 [DEBUG] clck_gen.py:113 IND CLOCK 5916
2026-01-29 02:54:35.499 [DEBUG] clck_gen.py:113 IND CLOCK 6018
2026-01-29 02:54:35.977 [DEBUG] clck_gen.py:113 IND CLOCK 6120
2026-01-29 02:54:36.456 [DEBUG] clck_gen.py:113 IND CLOCK 6222
2026-01-29 02:54:36.934 [DEBUG] clck_gen.py:113 IND CLOCK 6324
2026-01-29 02:54:37.413 [DEBUG] clck_gen.py:113 IND CLOCK 6426
2026-01-29 02:54:37.892 [DEBUG] clck_gen.py:113 IND CLOCK 6528
2026-01-29 02:54:38.370 [DEBUG] clck_gen.py:113 IND CLOCK 6630
2026-01-29 02:54:38.848 [DEBUG] clck_gen.py:113 IND CLOCK 6732
2026-01-29 02:54:39.326 [DEBUG] clck_gen.py:113 IND CLOCK 6834
2026-01-29 02:54:39.515 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:54:39.520 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:54:39.520 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 02:54:39.520 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 02:54:39.520 [INFO] transceiver.py:205 (MS@172.18.28.22:6700) Frequency hopping disabled
2026-01-29 02:54:39.533 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 02:54:39.533 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 02:54:39.533 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 02:54:39.534 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:54:39.534 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 02:54:39.534 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 02:54:39.534 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.28.22:6700) Recv POWERON CMD
2026-01-29 02:54:39.534 [INFO] ctrl_if_trx.py:109 (MS@172.18.28.22:6700) Starting transceiver...
2026-01-29 02:54:39.562 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:54:39.569 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.28.22:6700) Recv SETFH cmd
2026-01-29 02:54:39.569 [INFO] transceiver.py:201 (MS@172.18.28.22:6700) Frequency hopping configured: hsn=3, maio=3, ma_len=4
2026-01-29 02:54:39.569 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:54:39.570 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:54:39.804 [DEBUG] clck_gen.py:113 IND CLOCK 6936
2026-01-29 02:54:40.283 [DEBUG] clck_gen.py:113 IND CLOCK 7038
2026-01-29 02:54:40.762 [DEBUG] clck_gen.py:113 IND CLOCK 7140
2026-01-29 02:54:41.240 [DEBUG] clck_gen.py:113 IND CLOCK 7242
2026-01-29 02:54:41.718 [DEBUG] clck_gen.py:113 IND CLOCK 7344
2026-01-29 02:54:42.197 [DEBUG] clck_gen.py:113 IND CLOCK 7446
2026-01-29 02:54:42.675 [DEBUG] clck_gen.py:113 IND CLOCK 7548
2026-01-29 02:54:43.153 [DEBUG] clck_gen.py:113 IND CLOCK 7650
2026-01-29 02:54:43.632 [DEBUG] clck_gen.py:113 IND CLOCK 7752
2026-01-29 02:54:44.110 [DEBUG] clck_gen.py:113 IND CLOCK 7854
2026-01-29 02:54:44.589 [DEBUG] clck_gen.py:113 IND CLOCK 7956
2026-01-29 02:54:45.068 [DEBUG] clck_gen.py:113 IND CLOCK 8058
2026-01-29 02:54:45.546 [DEBUG] clck_gen.py:113 IND CLOCK 8160
2026-01-29 02:54:46.026 [DEBUG] clck_gen.py:113 IND CLOCK 8262
2026-01-29 02:54:46.504 [DEBUG] clck_gen.py:113 IND CLOCK 8364
2026-01-29 02:54:46.983 [DEBUG] clck_gen.py:113 IND CLOCK 8466
2026-01-29 02:54:47.462 [DEBUG] clck_gen.py:113 IND CLOCK 8568
2026-01-29 02:54:47.941 [DEBUG] clck_gen.py:113 IND CLOCK 8670
2026-01-29 02:54:48.420 [DEBUG] clck_gen.py:113 IND CLOCK 8772
2026-01-29 02:54:48.898 [DEBUG] clck_gen.py:113 IND CLOCK 8874
2026-01-29 02:54:49.376 [DEBUG] clck_gen.py:113 IND CLOCK 8976
2026-01-29 02:54:49.855 [DEBUG] clck_gen.py:113 IND CLOCK 9078
2026-01-29 02:54:50.334 [DEBUG] clck_gen.py:113 IND CLOCK 9180
2026-01-29 02:54:50.812 [DEBUG] clck_gen.py:113 IND CLOCK 9282
2026-01-29 02:54:51.291 [DEBUG] clck_gen.py:113 IND CLOCK 9384
2026-01-29 02:54:51.770 [DEBUG] clck_gen.py:113 IND CLOCK 9486
2026-01-29 02:54:52.249 [DEBUG] clck_gen.py:113 IND CLOCK 9588
2026-01-29 02:54:52.728 [DEBUG] clck_gen.py:113 IND CLOCK 9690
2026-01-29 02:54:53.206 [DEBUG] clck_gen.py:113 IND CLOCK 9792
2026-01-29 02:54:53.684 [DEBUG] clck_gen.py:113 IND CLOCK 9894
2026-01-29 02:54:54.163 [DEBUG] clck_gen.py:113 IND CLOCK 9996
2026-01-29 02:54:54.642 [DEBUG] clck_gen.py:113 IND CLOCK 10098
2026-01-29 02:54:55.120 [DEBUG] clck_gen.py:113 IND CLOCK 10200
2026-01-29 02:54:55.193 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:54:55.198 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:54:55.198 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 02:54:55.199 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 02:54:55.199 [INFO] transceiver.py:205 (MS@172.18.28.22:6700) Frequency hopping disabled
2026-01-29 02:54:55.210 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 02:54:55.211 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 02:54:55.211 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 02:54:55.212 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:54:55.212 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 02:54:55.212 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 02:54:55.212 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.28.22:6700) Recv POWERON CMD
2026-01-29 02:54:55.212 [INFO] ctrl_if_trx.py:109 (MS@172.18.28.22:6700) Starting transceiver...
2026-01-29 02:54:55.262 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:54:55.263 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:54:55.268 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 02:54:55.269 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 02:54:55.269 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:54:55.270 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:54:55.598 [DEBUG] clck_gen.py:113 IND CLOCK 10302
2026-01-29 02:54:56.076 [DEBUG] clck_gen.py:113 IND CLOCK 10404
2026-01-29 02:54:56.548 [DEBUG] clck_gen.py:113 IND CLOCK 10506
2026-01-29 02:54:57.018 [DEBUG] clck_gen.py:113 IND CLOCK 10608
2026-01-29 02:54:57.490 [DEBUG] clck_gen.py:113 IND CLOCK 10710
2026-01-29 02:54:57.964 [DEBUG] clck_gen.py:113 IND CLOCK 10812
2026-01-29 02:54:58.439 [DEBUG] clck_gen.py:113 IND CLOCK 10914
2026-01-29 02:54:58.915 [DEBUG] clck_gen.py:113 IND CLOCK 11016
2026-01-29 02:54:59.389 [DEBUG] clck_gen.py:113 IND CLOCK 11118
2026-01-29 02:54:59.864 [DEBUG] clck_gen.py:113 IND CLOCK 11220
2026-01-29 02:55:00.341 [DEBUG] clck_gen.py:113 IND CLOCK 11322
2026-01-29 02:55:00.813 [DEBUG] clck_gen.py:113 IND CLOCK 11424
2026-01-29 02:55:01.288 [DEBUG] clck_gen.py:113 IND CLOCK 11526
2026-01-29 02:55:01.763 [DEBUG] clck_gen.py:113 IND CLOCK 11628
2026-01-29 02:55:02.236 [DEBUG] clck_gen.py:113 IND CLOCK 11730
2026-01-29 02:55:02.710 [DEBUG] clck_gen.py:113 IND CLOCK 11832
2026-01-29 02:55:03.184 [DEBUG] clck_gen.py:113 IND CLOCK 11934
2026-01-29 02:55:03.658 [DEBUG] clck_gen.py:113 IND CLOCK 12036
2026-01-29 02:55:04.133 [DEBUG] clck_gen.py:113 IND CLOCK 12138
2026-01-29 02:55:04.609 [DEBUG] clck_gen.py:113 IND CLOCK 12240
2026-01-29 02:55:05.083 [DEBUG] clck_gen.py:113 IND CLOCK 12342
2026-01-29 02:55:05.559 [DEBUG] clck_gen.py:113 IND CLOCK 12444
2026-01-29 02:55:06.035 [DEBUG] clck_gen.py:113 IND CLOCK 12546
2026-01-29 02:55:06.511 [DEBUG] clck_gen.py:113 IND CLOCK 12648
2026-01-29 02:55:06.986 [DEBUG] clck_gen.py:113 IND CLOCK 12750
2026-01-29 02:55:07.462 [DEBUG] clck_gen.py:113 IND CLOCK 12852
2026-01-29 02:55:07.937 [DEBUG] clck_gen.py:113 IND CLOCK 12954
2026-01-29 02:55:08.414 [DEBUG] clck_gen.py:113 IND CLOCK 13056
2026-01-29 02:55:08.886 [DEBUG] clck_gen.py:113 IND CLOCK 13158
2026-01-29 02:55:09.362 [DEBUG] clck_gen.py:113 IND CLOCK 13260
2026-01-29 02:55:09.836 [DEBUG] clck_gen.py:113 IND CLOCK 13362
2026-01-29 02:55:10.311 [DEBUG] clck_gen.py:113 IND CLOCK 13464
2026-01-29 02:55:10.739 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:55:10.745 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:55:10.746 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 02:55:10.746 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 02:55:10.746 [WARNING] transceiver.py:257 (MS@172.18.28.22:6700) RX TRXD message (fn=13560 tn=2 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:55:10.756 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 02:55:10.756 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:55:10.756 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:55:10.756 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:55:10.760 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 02:55:10.760 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:55:10.760 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:55:10.760 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:55:10.760 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.28.20:5700) Recv POWEROFF cmd
2026-01-29 02:55:10.760 [INFO] ctrl_if_trx.py:117 (BTS@172.18.28.20:5700) Stopping transceiver...
2026-01-29 02:55:10.760 [INFO] transceiver.py:246 Stopping clock generator
2026-01-29 02:55:10.761 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=13563 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:55:10.761 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=13563 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:55:10.761 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=13563 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:55:10.761 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=13563 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:55:10.761 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=13563 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:55:10.761 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=13563 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:55:10.761 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=13563 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:55:15.756 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.28.20:5700) Recv POWEROFF cmd
2026-01-29 02:55:15.756 [INFO] ctrl_if_trx.py:117 (BTS@172.18.28.20:5700) Stopping transceiver...
2026-01-29 02:55:15.757 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:55:15.757 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:55:15.757 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:55:15.758 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 02:55:15.761 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 02:55:15.761 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.28.20:5700) Recv SETFORMAT cmd
2026-01-29 02:55:15.761 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.28.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:55:15.761 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.28.20:5700) Recv SETFORMAT cmd
2026-01-29 02:55:15.761 [INFO] ctrl_if_trx.py:201 (BTS@172.18.28.20:5700) TRXD header version 1 -> 1
2026-01-29 02:55:15.762 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.28.20:5700/1) Recv RXTUNE cmd
2026-01-29 02:55:15.762 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.28.20:5700/1) Recv TXTUNE cmd
2026-01-29 02:55:15.762 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.28.20:5700/1) Recv SETFORMAT cmd
2026-01-29 02:55:15.762 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.28.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:55:15.762 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:55:15.762 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.28.20:5700/1) Recv NOMTXPOWER cmd
2026-01-29 02:55:15.762 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.28.20:5700/1) Recv SETFORMAT cmd
2026-01-29 02:55:15.762 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.28.20:5700/1) TRXD header version 1 -> 1
2026-01-29 02:55:15.763 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.28.20:5700/2) Recv RXTUNE cmd
2026-01-29 02:55:15.763 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.28.20:5700/2) Recv TXTUNE cmd
2026-01-29 02:55:15.763 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.28.20:5700/2) Recv SETFORMAT cmd
2026-01-29 02:55:15.763 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.28.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:55:15.763 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:55:15.763 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.28.20:5700/2) Recv NOMTXPOWER cmd
2026-01-29 02:55:15.763 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.28.20:5700/2) Recv SETFORMAT cmd
2026-01-29 02:55:15.763 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.28.20:5700/2) TRXD header version 1 -> 1
2026-01-29 02:55:15.764 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.28.20:5700/3) Recv RXTUNE cmd
2026-01-29 02:55:15.764 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.28.20:5700/3) Recv TXTUNE cmd
2026-01-29 02:55:15.764 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.28.20:5700/3) Recv SETFORMAT cmd
2026-01-29 02:55:15.764 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.28.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:55:15.764 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:55:15.764 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.28.20:5700/3) Recv NOMTXPOWER cmd
2026-01-29 02:55:15.764 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.28.20:5700/3) Recv SETFORMAT cmd
2026-01-29 02:55:15.764 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.28.20:5700/3) TRXD header version 1 -> 1
2026-01-29 02:55:15.765 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.28.20:5700) Recv RXTUNE cmd
2026-01-29 02:55:15.765 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETTSC
2026-01-29 02:55:15.765 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETTSC
2026-01-29 02:55:15.765 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETTSC
2026-01-29 02:55:15.765 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.28.20:5700) Recv TXTUNE cmd
2026-01-29 02:55:15.765 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETRXGAIN
2026-01-29 02:55:15.765 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETRXGAIN
2026-01-29 02:55:15.765 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETRXGAIN
2026-01-29 02:55:15.765 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETTSC
2026-01-29 02:55:15.765 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:55:15.765 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:55:15.765 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:55:15.765 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.28.20:5700) Recv NOMTXPOWER cmd
2026-01-29 02:55:15.765 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:55:15.765 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:55:15.765 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:55:15.765 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.28.20:5700) Recv POWERON CMD
2026-01-29 02:55:15.765 [INFO] ctrl_if_trx.py:109 (BTS@172.18.28.20:5700) Starting transceiver...
2026-01-29 02:55:15.765 [INFO] transceiver.py:243 Starting clock generator
2026-01-29 02:55:15.765 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-01-29 02:55:15.765 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:55:15.765 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:55:15.765 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:55:15.766 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETRXGAIN
2026-01-29 02:55:15.766 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:55:15.766 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:55:15.766 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:55:15.766 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:55:15.766 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:55:15.766 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:55:15.766 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:55:15.766 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:55:15.766 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:55:15.766 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:55:15.766 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:55:15.766 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:55:15.766 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:55:15.766 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:55:15.766 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:55:15.766 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:55:15.766 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:55:15.766 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:55:15.766 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:55:15.766 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:55:15.766 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:55:15.766 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:55:15.766 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:55:15.766 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 02:55:15.766 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:55:15.766 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.28.20:5700) Recv POWEROFF cmd
2026-01-29 02:55:15.766 [INFO] ctrl_if_trx.py:117 (BTS@172.18.28.20:5700) Stopping transceiver...
2026-01-29 02:55:15.766 [INFO] transceiver.py:246 Stopping clock generator
2026-01-29 02:55:15.767 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:55:15.767 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:55:20.768 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.28.20:5700) Recv POWEROFF cmd
2026-01-29 02:55:20.768 [INFO] ctrl_if_trx.py:117 (BTS@172.18.28.20:5700) Stopping transceiver...
2026-01-29 02:55:20.768 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:55:20.768 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:55:20.769 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:55:20.769 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 02:55:20.772 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 02:55:20.772 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.28.20:5700) Recv SETFORMAT cmd
2026-01-29 02:55:20.772 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.28.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:55:20.772 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.28.20:5700) Recv SETFORMAT cmd
2026-01-29 02:55:20.772 [INFO] ctrl_if_trx.py:201 (BTS@172.18.28.20:5700) TRXD header version 1 -> 1
2026-01-29 02:55:20.773 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.28.20:5700/1) Recv RXTUNE cmd
2026-01-29 02:55:20.773 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.28.20:5700/1) Recv TXTUNE cmd
2026-01-29 02:55:20.773 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.28.20:5700/1) Recv SETFORMAT cmd
2026-01-29 02:55:20.773 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.28.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:55:20.773 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:55:20.773 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.28.20:5700/1) Recv NOMTXPOWER cmd
2026-01-29 02:55:20.773 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.28.20:5700/1) Recv SETFORMAT cmd
2026-01-29 02:55:20.773 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.28.20:5700/1) TRXD header version 1 -> 1
2026-01-29 02:55:20.774 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.28.20:5700/2) Recv RXTUNE cmd
2026-01-29 02:55:20.774 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.28.20:5700/2) Recv TXTUNE cmd
2026-01-29 02:55:20.774 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.28.20:5700/2) Recv SETFORMAT cmd
2026-01-29 02:55:20.774 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.28.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:55:20.774 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:55:20.774 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.28.20:5700/2) Recv NOMTXPOWER cmd
2026-01-29 02:55:20.774 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.28.20:5700/2) Recv SETFORMAT cmd
2026-01-29 02:55:20.774 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.28.20:5700/2) TRXD header version 1 -> 1
2026-01-29 02:55:20.775 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.28.20:5700/3) Recv RXTUNE cmd
2026-01-29 02:55:20.775 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.28.20:5700/3) Recv TXTUNE cmd
2026-01-29 02:55:20.775 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.28.20:5700/3) Recv SETFORMAT cmd
2026-01-29 02:55:20.775 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.28.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:55:20.775 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:55:20.775 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.28.20:5700/3) Recv NOMTXPOWER cmd
2026-01-29 02:55:20.775 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.28.20:5700/3) Recv SETFORMAT cmd
2026-01-29 02:55:20.775 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.28.20:5700/3) TRXD header version 1 -> 1
2026-01-29 02:55:20.776 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.28.20:5700) Recv RXTUNE cmd
2026-01-29 02:55:20.776 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETTSC
2026-01-29 02:55:20.776 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETTSC
2026-01-29 02:55:20.776 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETTSC
2026-01-29 02:55:20.776 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.28.20:5700) Recv TXTUNE cmd
2026-01-29 02:55:20.776 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETRXGAIN
2026-01-29 02:55:20.776 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETRXGAIN
2026-01-29 02:55:20.776 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETRXGAIN
2026-01-29 02:55:20.776 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETTSC
2026-01-29 02:55:20.776 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:55:20.776 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:55:20.776 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.28.20:5700) Recv NOMTXPOWER cmd
2026-01-29 02:55:20.776 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:55:20.776 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:55:20.776 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:55:20.776 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.28.20:5700) Recv POWERON CMD
2026-01-29 02:55:20.776 [INFO] ctrl_if_trx.py:109 (BTS@172.18.28.20:5700) Starting transceiver...
2026-01-29 02:55:20.776 [INFO] transceiver.py:243 Starting clock generator
2026-01-29 02:55:20.776 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-01-29 02:55:20.776 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:55:20.776 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:55:20.776 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:55:20.776 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETRXGAIN
2026-01-29 02:55:20.776 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:55:20.776 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:55:20.776 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:55:20.777 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:55:20.777 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:55:20.777 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:55:20.777 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:55:20.777 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:55:20.777 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:55:20.777 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:55:20.777 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:55:20.777 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:55:20.777 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:55:20.777 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:55:20.777 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:55:20.777 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:55:20.777 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:55:20.777 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:55:20.777 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:55:20.777 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:55:20.777 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:55:20.777 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:55:20.777 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:55:20.777 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:55:20.781 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-01-29 02:55:21.260 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-01-29 02:55:21.300 [DEBUG] fake_trx.py:278 (BTS@172.18.28.20:5700) Recv FAKE_TOA cmd
2026-01-29 02:55:21.301 [DEBUG] fake_trx.py:297 (BTS@172.18.28.20:5700) Recv FAKE_RSSI cmd
2026-01-29 02:55:21.302 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:55:21.303 [DEBUG] fake_trx.py:322 (BTS@172.18.28.20:5700) Recv FAKE_CI cmd
2026-01-29 02:55:21.337 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 02:55:21.337 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 02:55:21.338 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 02:55:21.342 [DEBUG] fake_trx.py:297 (BTS@172.18.28.20:5700) Recv FAKE_RSSI cmd
2026-01-29 02:55:21.343 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:55:21.343 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 02:55:21.343 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 02:55:21.343 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.28.22:6700) Recv POWERON CMD
2026-01-29 02:55:21.343 [INFO] ctrl_if_trx.py:109 (MS@172.18.28.22:6700) Starting transceiver...
2026-01-29 02:55:21.353 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:55:21.357 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 02:55:21.357 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 02:55:21.358 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:55:21.358 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:55:21.734 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-01-29 02:55:21.779 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:55:21.779 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 02:55:21.779 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:55:21.781 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:55:22.204 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-01-29 02:55:22.680 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-01-29 02:55:22.780 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 02:55:22.780 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:55:22.780 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:55:22.781 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:55:23.155 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-01-29 02:55:23.628 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-01-29 02:55:23.781 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 02:55:23.781 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:55:23.781 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:55:23.782 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:55:24.121 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-01-29 02:55:24.598 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-01-29 02:55:24.781 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:55:24.781 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 02:55:24.781 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:55:24.782 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:55:25.070 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-01-29 02:55:25.543 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-01-29 02:55:25.782 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 02:55:25.783 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:55:25.783 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:55:25.783 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:55:26.022 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-01-29 02:55:26.500 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-01-29 02:55:26.978 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-01-29 02:55:27.456 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-01-29 02:55:27.934 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-01-29 02:55:28.411 [DEBUG] clck_gen.py:113 IND CLOCK 1632
2026-01-29 02:55:28.889 [DEBUG] clck_gen.py:113 IND CLOCK 1734
2026-01-29 02:55:29.367 [DEBUG] clck_gen.py:113 IND CLOCK 1836
2026-01-29 02:55:29.845 [DEBUG] clck_gen.py:113 IND CLOCK 1938
2026-01-29 02:55:30.323 [DEBUG] clck_gen.py:113 IND CLOCK 2040
2026-01-29 02:55:30.801 [DEBUG] clck_gen.py:113 IND CLOCK 2142
2026-01-29 02:55:31.279 [DEBUG] clck_gen.py:113 IND CLOCK 2244
2026-01-29 02:55:31.739 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:55:31.744 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:55:31.744 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 02:55:31.745 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 02:55:31.755 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 02:55:31.755 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:55:31.756 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:55:31.756 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:55:31.756 [DEBUG] clck_gen.py:113 IND CLOCK 2346
2026-01-29 02:55:31.759 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 02:55:31.759 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:55:31.759 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:55:31.759 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:55:31.759 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.28.20:5700) Recv POWEROFF cmd
2026-01-29 02:55:31.759 [INFO] ctrl_if_trx.py:117 (BTS@172.18.28.20:5700) Stopping transceiver...
2026-01-29 02:55:31.759 [INFO] transceiver.py:246 Stopping clock generator
2026-01-29 02:55:36.762 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.28.20:5700) Recv POWEROFF cmd
2026-01-29 02:55:36.762 [INFO] ctrl_if_trx.py:117 (BTS@172.18.28.20:5700) Stopping transceiver...
2026-01-29 02:55:36.762 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:55:36.762 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:55:36.762 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:55:36.762 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 02:55:36.771 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 02:55:36.773 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.28.20:5700) Recv SETFORMAT cmd
2026-01-29 02:55:36.773 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.28.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:55:36.774 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.28.20:5700) Recv SETFORMAT cmd
2026-01-29 02:55:36.774 [INFO] ctrl_if_trx.py:201 (BTS@172.18.28.20:5700) TRXD header version 1 -> 1
2026-01-29 02:55:36.779 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.28.20:5700/1) Recv RXTUNE cmd
2026-01-29 02:55:36.780 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.28.20:5700/1) Recv TXTUNE cmd
2026-01-29 02:55:36.780 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.28.20:5700/1) Recv SETFORMAT cmd
2026-01-29 02:55:36.780 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.28.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:55:36.780 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:55:36.780 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.28.20:5700/1) Recv NOMTXPOWER cmd
2026-01-29 02:55:36.781 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.28.20:5700/1) Recv SETFORMAT cmd
2026-01-29 02:55:36.781 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.28.20:5700/1) TRXD header version 1 -> 1
2026-01-29 02:55:36.784 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.28.20:5700/2) Recv RXTUNE cmd
2026-01-29 02:55:36.784 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.28.20:5700/2) Recv TXTUNE cmd
2026-01-29 02:55:36.784 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.28.20:5700/2) Recv SETFORMAT cmd
2026-01-29 02:55:36.784 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.28.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:55:36.784 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:55:36.784 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.28.20:5700/2) Recv NOMTXPOWER cmd
2026-01-29 02:55:36.784 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.28.20:5700/2) Recv SETFORMAT cmd
2026-01-29 02:55:36.784 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.28.20:5700/2) TRXD header version 1 -> 1
2026-01-29 02:55:36.787 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.28.20:5700/3) Recv RXTUNE cmd
2026-01-29 02:55:36.787 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.28.20:5700/3) Recv TXTUNE cmd
2026-01-29 02:55:36.787 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.28.20:5700/3) Recv SETFORMAT cmd
2026-01-29 02:55:36.787 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.28.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:55:36.787 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:55:36.787 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.28.20:5700/3) Recv NOMTXPOWER cmd
2026-01-29 02:55:36.788 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.28.20:5700/3) Recv SETFORMAT cmd
2026-01-29 02:55:36.788 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.28.20:5700/3) TRXD header version 1 -> 1
2026-01-29 02:55:36.791 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.28.20:5700) Recv RXTUNE cmd
2026-01-29 02:55:36.791 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETTSC
2026-01-29 02:55:36.791 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETTSC
2026-01-29 02:55:36.791 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETTSC
2026-01-29 02:55:36.791 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.28.20:5700) Recv TXTUNE cmd
2026-01-29 02:55:36.791 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETRXGAIN
2026-01-29 02:55:36.791 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETRXGAIN
2026-01-29 02:55:36.791 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETRXGAIN
2026-01-29 02:55:36.791 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETTSC
2026-01-29 02:55:36.791 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:55:36.791 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:55:36.791 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:55:36.791 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.28.20:5700) Recv NOMTXPOWER cmd
2026-01-29 02:55:36.791 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:55:36.791 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:55:36.791 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:55:36.792 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.28.20:5700) Recv POWERON CMD
2026-01-29 02:55:36.792 [INFO] ctrl_if_trx.py:109 (BTS@172.18.28.20:5700) Starting transceiver...
2026-01-29 02:55:36.792 [INFO] transceiver.py:243 Starting clock generator
2026-01-29 02:55:36.792 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-01-29 02:55:36.792 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:55:36.792 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:55:36.792 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:55:36.792 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETRXGAIN
2026-01-29 02:55:36.792 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:55:36.792 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:55:36.792 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:55:36.792 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:55:36.792 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:55:36.792 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:55:36.792 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:55:36.793 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:55:36.793 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:55:36.793 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:55:36.793 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:55:36.793 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:55:36.793 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:55:36.793 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:55:36.793 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:55:36.793 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:55:36.793 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:55:36.793 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:55:36.793 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:55:36.793 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:55:36.793 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:55:36.793 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:55:36.793 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:55:36.796 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-01-29 02:55:37.277 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-01-29 02:55:37.318 [DEBUG] fake_trx.py:278 (BTS@172.18.28.20:5700) Recv FAKE_TOA cmd
2026-01-29 02:55:37.318 [DEBUG] fake_trx.py:297 (BTS@172.18.28.20:5700) Recv FAKE_RSSI cmd
2026-01-29 02:55:37.320 [DEBUG] fake_trx.py:322 (BTS@172.18.28.20:5700) Recv FAKE_CI cmd
2026-01-29 02:55:37.321 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:55:37.352 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 02:55:37.352 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 02:55:37.352 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 02:55:37.359 [DEBUG] fake_trx.py:297 (BTS@172.18.28.20:5700) Recv FAKE_RSSI cmd
2026-01-29 02:55:37.361 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:55:37.361 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 02:55:37.361 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 02:55:37.362 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.28.22:6700) Recv POWERON CMD
2026-01-29 02:55:37.362 [INFO] ctrl_if_trx.py:109 (MS@172.18.28.22:6700) Starting transceiver...
2026-01-29 02:55:37.370 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:55:37.373 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 02:55:37.374 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 02:55:37.374 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:55:37.374 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:55:37.755 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-01-29 02:55:37.796 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:55:37.796 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 02:55:37.797 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:55:37.800 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:55:38.233 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-01-29 02:55:38.710 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-01-29 02:55:38.797 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 02:55:38.797 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:55:38.798 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:55:38.801 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:55:39.188 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-01-29 02:55:39.666 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-01-29 02:55:39.798 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:55:39.799 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:55:39.799 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 02:55:39.801 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:55:40.144 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-01-29 02:55:40.622 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-01-29 02:55:40.799 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:55:40.799 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 02:55:40.800 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:55:40.802 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:55:41.100 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-01-29 02:55:41.578 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-01-29 02:55:41.800 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 02:55:41.800 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:55:41.801 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:55:41.803 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:55:42.056 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-01-29 02:55:42.534 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-01-29 02:55:43.012 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-01-29 02:55:43.490 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-01-29 02:55:43.968 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-01-29 02:55:44.446 [DEBUG] clck_gen.py:113 IND CLOCK 1632
2026-01-29 02:55:44.923 [DEBUG] clck_gen.py:113 IND CLOCK 1734
2026-01-29 02:55:45.401 [DEBUG] clck_gen.py:113 IND CLOCK 1836
2026-01-29 02:55:45.879 [DEBUG] clck_gen.py:113 IND CLOCK 1938
2026-01-29 02:55:46.357 [DEBUG] clck_gen.py:113 IND CLOCK 2040
2026-01-29 02:55:46.835 [DEBUG] clck_gen.py:113 IND CLOCK 2142
2026-01-29 02:55:47.313 [DEBUG] clck_gen.py:113 IND CLOCK 2244
2026-01-29 02:55:47.758 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:55:47.761 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:55:47.762 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 02:55:47.762 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 02:55:47.762 [WARNING] transceiver.py:257 (MS@172.18.28.22:6700) RX TRXD message (fn=2343 tn=2 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:55:47.773 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 02:55:47.773 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:55:47.773 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:55:47.773 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:55:47.777 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 02:55:47.777 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:55:47.777 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:55:47.777 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:55:47.777 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.28.20:5700) Recv POWEROFF cmd
2026-01-29 02:55:47.777 [INFO] ctrl_if_trx.py:117 (BTS@172.18.28.20:5700) Stopping transceiver...
2026-01-29 02:55:47.777 [INFO] transceiver.py:246 Stopping clock generator
2026-01-29 02:55:47.777 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=2345 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:55:47.777 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=2345 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:55:47.777 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=2345 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:55:47.777 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=2345 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:55:47.777 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=2345 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:55:47.777 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=2345 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:55:47.777 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=2346 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:55:47.777 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=2346 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:55:47.777 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=2346 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:55:47.777 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=2346 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:55:47.777 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=2346 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:55:47.777 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=2346 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:55:47.777 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=2346 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:55:47.777 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=2346 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:55:52.776 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.28.20:5700) Recv POWEROFF cmd
2026-01-29 02:55:52.777 [INFO] ctrl_if_trx.py:117 (BTS@172.18.28.20:5700) Stopping transceiver...
2026-01-29 02:55:52.778 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:55:52.780 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:55:52.780 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:55:52.781 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 02:55:52.790 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 02:55:52.791 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.28.20:5700) Recv SETFORMAT cmd
2026-01-29 02:55:52.791 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.28.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:55:52.791 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.28.20:5700) Recv SETFORMAT cmd
2026-01-29 02:55:52.791 [INFO] ctrl_if_trx.py:201 (BTS@172.18.28.20:5700) TRXD header version 1 -> 1
2026-01-29 02:55:52.796 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.28.20:5700/1) Recv RXTUNE cmd
2026-01-29 02:55:52.796 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.28.20:5700/1) Recv TXTUNE cmd
2026-01-29 02:55:52.796 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.28.20:5700/1) Recv SETFORMAT cmd
2026-01-29 02:55:52.796 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.28.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:55:52.796 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:55:52.797 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.28.20:5700/1) Recv NOMTXPOWER cmd
2026-01-29 02:55:52.797 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.28.20:5700/1) Recv SETFORMAT cmd
2026-01-29 02:55:52.797 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.28.20:5700/1) TRXD header version 1 -> 1
2026-01-29 02:55:52.800 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.28.20:5700/2) Recv RXTUNE cmd
2026-01-29 02:55:52.800 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.28.20:5700/2) Recv TXTUNE cmd
2026-01-29 02:55:52.800 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.28.20:5700/2) Recv SETFORMAT cmd
2026-01-29 02:55:52.800 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.28.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:55:52.800 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:55:52.800 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.28.20:5700/2) Recv NOMTXPOWER cmd
2026-01-29 02:55:52.801 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.28.20:5700/2) Recv SETFORMAT cmd
2026-01-29 02:55:52.801 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.28.20:5700/2) TRXD header version 1 -> 1
2026-01-29 02:55:52.803 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.28.20:5700/3) Recv RXTUNE cmd
2026-01-29 02:55:52.803 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.28.20:5700/3) Recv TXTUNE cmd
2026-01-29 02:55:52.803 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.28.20:5700/3) Recv SETFORMAT cmd
2026-01-29 02:55:52.803 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.28.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:55:52.804 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:55:52.804 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.28.20:5700/3) Recv NOMTXPOWER cmd
2026-01-29 02:55:52.804 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.28.20:5700/3) Recv SETFORMAT cmd
2026-01-29 02:55:52.804 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.28.20:5700/3) TRXD header version 1 -> 1
2026-01-29 02:55:52.807 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.28.20:5700) Recv RXTUNE cmd
2026-01-29 02:55:52.807 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETTSC
2026-01-29 02:55:52.807 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETTSC
2026-01-29 02:55:52.807 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.28.20:5700) Recv TXTUNE cmd
2026-01-29 02:55:52.807 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETTSC
2026-01-29 02:55:52.807 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETRXGAIN
2026-01-29 02:55:52.807 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETRXGAIN
2026-01-29 02:55:52.808 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETTSC
2026-01-29 02:55:52.808 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETRXGAIN
2026-01-29 02:55:52.808 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:55:52.808 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:55:52.808 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.28.20:5700) Recv NOMTXPOWER cmd
2026-01-29 02:55:52.808 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:55:52.808 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:55:52.808 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:55:52.808 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.28.20:5700) Recv POWERON CMD
2026-01-29 02:55:52.808 [INFO] ctrl_if_trx.py:109 (BTS@172.18.28.20:5700) Starting transceiver...
2026-01-29 02:55:52.808 [INFO] transceiver.py:243 Starting clock generator
2026-01-29 02:55:52.808 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-01-29 02:55:52.808 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:55:52.808 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:55:52.808 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:55:52.809 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETRXGAIN
2026-01-29 02:55:52.809 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:55:52.809 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:55:52.809 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:55:52.809 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:55:52.809 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:55:52.809 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:55:52.809 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:55:52.809 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:55:52.809 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:55:52.809 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:55:52.809 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:55:52.809 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:55:52.809 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:55:52.809 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:55:52.809 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:55:52.809 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:55:52.809 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:55:52.809 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:55:52.809 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:55:52.809 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:55:52.810 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:55:52.810 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:55:52.810 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:55:52.810 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:55:52.813 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-01-29 02:55:53.295 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-01-29 02:55:53.334 [DEBUG] fake_trx.py:278 (BTS@172.18.28.20:5700) Recv FAKE_TOA cmd
2026-01-29 02:55:53.336 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:55:53.337 [DEBUG] fake_trx.py:297 (BTS@172.18.28.20:5700) Recv FAKE_RSSI cmd
2026-01-29 02:55:53.339 [DEBUG] fake_trx.py:322 (BTS@172.18.28.20:5700) Recv FAKE_CI cmd
2026-01-29 02:55:53.357 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 02:55:53.357 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 02:55:53.357 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 02:55:53.360 [DEBUG] fake_trx.py:297 (BTS@172.18.28.20:5700) Recv FAKE_RSSI cmd
2026-01-29 02:55:53.362 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:55:53.362 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 02:55:53.362 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 02:55:53.362 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.28.22:6700) Recv POWERON CMD
2026-01-29 02:55:53.362 [INFO] ctrl_if_trx.py:109 (MS@172.18.28.22:6700) Starting transceiver...
2026-01-29 02:55:53.386 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:55:53.389 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 02:55:53.389 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 02:55:53.389 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:55:53.389 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:55:53.772 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-01-29 02:55:53.812 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:55:53.812 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 02:55:53.813 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:55:53.817 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:55:54.250 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-01-29 02:55:54.267 [DEBUG] fake_trx.py:269 (MS@172.18.28.22:6700) Recv SETTA cmd
2026-01-29 02:55:54.728 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-01-29 02:55:54.812 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:55:54.813 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 02:55:54.814 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:55:54.818 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:55:55.206 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-01-29 02:55:55.684 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-01-29 02:55:55.813 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 02:55:55.814 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:55:55.815 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:55:55.819 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:55:56.161 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-01-29 02:55:56.640 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-01-29 02:55:56.815 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 02:55:56.815 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:55:56.815 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:55:56.820 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:55:57.118 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-01-29 02:55:57.596 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-01-29 02:55:57.816 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:55:57.816 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:55:57.816 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 02:55:57.821 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:55:58.074 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-01-29 02:55:58.552 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-01-29 02:55:59.030 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-01-29 02:55:59.508 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-01-29 02:55:59.986 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-01-29 02:56:00.463 [DEBUG] clck_gen.py:113 IND CLOCK 1632
2026-01-29 02:56:00.940 [DEBUG] clck_gen.py:113 IND CLOCK 1734
2026-01-29 02:56:01.418 [DEBUG] clck_gen.py:113 IND CLOCK 1836
2026-01-29 02:56:01.895 [DEBUG] clck_gen.py:113 IND CLOCK 1938
2026-01-29 02:56:02.369 [DEBUG] clck_gen.py:113 IND CLOCK 2040
2026-01-29 02:56:02.847 [DEBUG] clck_gen.py:113 IND CLOCK 2142
2026-01-29 02:56:03.325 [DEBUG] clck_gen.py:113 IND CLOCK 2244
2026-01-29 02:56:03.803 [DEBUG] clck_gen.py:113 IND CLOCK 2346
2026-01-29 02:56:04.281 [DEBUG] clck_gen.py:113 IND CLOCK 2448
2026-01-29 02:56:04.759 [DEBUG] clck_gen.py:113 IND CLOCK 2550
2026-01-29 02:56:05.236 [DEBUG] clck_gen.py:113 IND CLOCK 2652
2026-01-29 02:56:05.714 [DEBUG] clck_gen.py:113 IND CLOCK 2754
2026-01-29 02:56:06.193 [DEBUG] clck_gen.py:113 IND CLOCK 2856
2026-01-29 02:56:06.671 [DEBUG] clck_gen.py:113 IND CLOCK 2958
2026-01-29 02:56:07.149 [DEBUG] clck_gen.py:113 IND CLOCK 3060
2026-01-29 02:56:07.627 [DEBUG] clck_gen.py:113 IND CLOCK 3162
2026-01-29 02:56:08.105 [DEBUG] clck_gen.py:113 IND CLOCK 3264
2026-01-29 02:56:08.583 [DEBUG] clck_gen.py:113 IND CLOCK 3366
2026-01-29 02:56:09.061 [DEBUG] clck_gen.py:113 IND CLOCK 3468
2026-01-29 02:56:09.539 [DEBUG] clck_gen.py:113 IND CLOCK 3570
2026-01-29 02:56:10.017 [DEBUG] clck_gen.py:113 IND CLOCK 3672
2026-01-29 02:56:10.495 [DEBUG] clck_gen.py:113 IND CLOCK 3774
2026-01-29 02:56:10.973 [DEBUG] clck_gen.py:113 IND CLOCK 3876
2026-01-29 02:56:11.450 [DEBUG] clck_gen.py:113 IND CLOCK 3978
2026-01-29 02:56:11.928 [DEBUG] clck_gen.py:113 IND CLOCK 4080
2026-01-29 02:56:12.406 [DEBUG] clck_gen.py:113 IND CLOCK 4182
2026-01-29 02:56:12.884 [DEBUG] clck_gen.py:113 IND CLOCK 4284
2026-01-29 02:56:12.977 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:56:12.984 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:56:12.985 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 02:56:12.985 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 02:56:12.995 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 02:56:12.995 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:56:12.995 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:56:12.995 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:56:12.999 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 02:56:12.999 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:56:12.999 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:56:12.999 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.28.20:5700) Recv POWEROFF cmd
2026-01-29 02:56:12.999 [INFO] ctrl_if_trx.py:117 (BTS@172.18.28.20:5700) Stopping transceiver...
2026-01-29 02:56:12.999 [INFO] transceiver.py:246 Stopping clock generator
2026-01-29 02:56:13.000 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:56:13.000 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=4310 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:56:13.000 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=4310 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:56:13.000 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=4310 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:56:13.000 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=4310 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:56:13.000 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=4310 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:56:13.000 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=4310 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:56:13.000 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=4310 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:56:17.999 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.28.20:5700) Recv POWEROFF cmd
2026-01-29 02:56:17.999 [INFO] ctrl_if_trx.py:117 (BTS@172.18.28.20:5700) Stopping transceiver...
2026-01-29 02:56:18.000 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:56:18.002 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:56:18.002 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:56:18.002 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 02:56:18.009 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 02:56:18.010 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.28.20:5700) Recv SETFORMAT cmd
2026-01-29 02:56:18.010 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.28.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:56:18.011 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.28.20:5700) Recv SETFORMAT cmd
2026-01-29 02:56:18.011 [INFO] ctrl_if_trx.py:201 (BTS@172.18.28.20:5700) TRXD header version 1 -> 1
2026-01-29 02:56:18.013 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.28.20:5700/1) Recv RXTUNE cmd
2026-01-29 02:56:18.013 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.28.20:5700/1) Recv TXTUNE cmd
2026-01-29 02:56:18.014 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.28.20:5700/1) Recv SETFORMAT cmd
2026-01-29 02:56:18.014 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.28.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:56:18.014 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:56:18.014 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.28.20:5700/1) Recv NOMTXPOWER cmd
2026-01-29 02:56:18.014 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.28.20:5700/1) Recv SETFORMAT cmd
2026-01-29 02:56:18.014 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.28.20:5700/1) TRXD header version 1 -> 1
2026-01-29 02:56:18.017 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.28.20:5700/2) Recv RXTUNE cmd
2026-01-29 02:56:18.017 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.28.20:5700/2) Recv TXTUNE cmd
2026-01-29 02:56:18.017 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.28.20:5700/2) Recv SETFORMAT cmd
2026-01-29 02:56:18.018 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.28.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:56:18.018 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:56:18.018 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.28.20:5700/2) Recv NOMTXPOWER cmd
2026-01-29 02:56:18.018 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.28.20:5700/2) Recv SETFORMAT cmd
2026-01-29 02:56:18.018 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.28.20:5700/2) TRXD header version 1 -> 1
2026-01-29 02:56:18.021 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.28.20:5700/3) Recv RXTUNE cmd
2026-01-29 02:56:18.021 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.28.20:5700/3) Recv TXTUNE cmd
2026-01-29 02:56:18.021 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.28.20:5700/3) Recv SETFORMAT cmd
2026-01-29 02:56:18.021 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.28.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:56:18.021 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:56:18.021 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.28.20:5700/3) Recv NOMTXPOWER cmd
2026-01-29 02:56:18.021 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.28.20:5700/3) Recv SETFORMAT cmd
2026-01-29 02:56:18.021 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.28.20:5700/3) TRXD header version 1 -> 1
2026-01-29 02:56:18.025 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.28.20:5700) Recv RXTUNE cmd
2026-01-29 02:56:18.025 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETTSC
2026-01-29 02:56:18.025 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETTSC
2026-01-29 02:56:18.025 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETTSC
2026-01-29 02:56:18.025 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.28.20:5700) Recv TXTUNE cmd
2026-01-29 02:56:18.025 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETRXGAIN
2026-01-29 02:56:18.025 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETRXGAIN
2026-01-29 02:56:18.025 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETRXGAIN
2026-01-29 02:56:18.025 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETTSC
2026-01-29 02:56:18.025 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:56:18.025 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:56:18.025 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:56:18.025 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.28.20:5700) Recv NOMTXPOWER cmd
2026-01-29 02:56:18.026 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:56:18.026 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:56:18.026 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:56:18.026 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.28.20:5700) Recv POWERON CMD
2026-01-29 02:56:18.026 [INFO] ctrl_if_trx.py:109 (BTS@172.18.28.20:5700) Starting transceiver...
2026-01-29 02:56:18.026 [INFO] transceiver.py:243 Starting clock generator
2026-01-29 02:56:18.026 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-01-29 02:56:18.026 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:56:18.026 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:56:18.026 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:56:18.026 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETRXGAIN
2026-01-29 02:56:18.026 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:56:18.027 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:56:18.027 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:56:18.027 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:56:18.027 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:56:18.027 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:56:18.027 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:56:18.027 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:56:18.027 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:56:18.027 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:56:18.027 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:56:18.027 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:56:18.027 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:56:18.027 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:56:18.027 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:56:18.027 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:56:18.027 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:56:18.027 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:56:18.027 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:56:18.027 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:56:18.027 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:56:18.028 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:56:18.028 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:56:18.031 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-01-29 02:56:18.513 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-01-29 02:56:18.547 [DEBUG] fake_trx.py:278 (BTS@172.18.28.20:5700) Recv FAKE_TOA cmd
2026-01-29 02:56:18.548 [DEBUG] fake_trx.py:297 (BTS@172.18.28.20:5700) Recv FAKE_RSSI cmd
2026-01-29 02:56:18.550 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:56:18.550 [DEBUG] fake_trx.py:322 (BTS@172.18.28.20:5700) Recv FAKE_CI cmd
2026-01-29 02:56:18.573 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 02:56:18.573 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 02:56:18.573 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 02:56:18.579 [DEBUG] fake_trx.py:297 (BTS@172.18.28.20:5700) Recv FAKE_RSSI cmd
2026-01-29 02:56:18.581 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:56:18.581 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 02:56:18.581 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 02:56:18.581 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.28.22:6700) Recv POWERON CMD
2026-01-29 02:56:18.581 [INFO] ctrl_if_trx.py:109 (MS@172.18.28.22:6700) Starting transceiver...
2026-01-29 02:56:18.610 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:56:18.616 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 02:56:18.617 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 02:56:18.617 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:56:18.617 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:56:18.991 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-01-29 02:56:19.029 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 02:56:19.030 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:56:19.032 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:56:19.034 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:56:19.469 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-01-29 02:56:19.485 [DEBUG] fake_trx.py:269 (MS@172.18.28.22:6700) Recv SETTA cmd
2026-01-29 02:56:19.947 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-01-29 02:56:20.030 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 02:56:20.031 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:56:20.033 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:56:20.035 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:56:20.425 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-01-29 02:56:20.459 [DEBUG] fake_trx.py:269 (MS@172.18.28.22:6700) Recv SETTA cmd
2026-01-29 02:56:20.903 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-01-29 02:56:21.032 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 02:56:21.032 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:56:21.034 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:56:21.036 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:56:21.382 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-01-29 02:56:21.434 [DEBUG] fake_trx.py:269 (MS@172.18.28.22:6700) Recv SETTA cmd
2026-01-29 02:56:21.860 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-01-29 02:56:22.033 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 02:56:22.034 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:56:22.035 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:56:22.036 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:56:22.338 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-01-29 02:56:22.409 [DEBUG] fake_trx.py:269 (MS@172.18.28.22:6700) Recv SETTA cmd
2026-01-29 02:56:22.816 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-01-29 02:56:23.034 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 02:56:23.034 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:56:23.036 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:56:23.037 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:56:23.293 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-01-29 02:56:23.383 [DEBUG] fake_trx.py:269 (MS@172.18.28.22:6700) Recv SETTA cmd
2026-01-29 02:56:23.771 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-01-29 02:56:24.250 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-01-29 02:56:24.358 [DEBUG] fake_trx.py:269 (MS@172.18.28.22:6700) Recv SETTA cmd
2026-01-29 02:56:24.728 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-01-29 02:56:25.206 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-01-29 02:56:25.332 [DEBUG] fake_trx.py:269 (MS@172.18.28.22:6700) Recv SETTA cmd
2026-01-29 02:56:25.683 [DEBUG] clck_gen.py:113 IND CLOCK 1632
2026-01-29 02:56:26.161 [DEBUG] clck_gen.py:113 IND CLOCK 1734
2026-01-29 02:56:26.307 [DEBUG] fake_trx.py:269 (MS@172.18.28.22:6700) Recv SETTA cmd
2026-01-29 02:56:26.640 [DEBUG] clck_gen.py:113 IND CLOCK 1836
2026-01-29 02:56:27.118 [DEBUG] clck_gen.py:113 IND CLOCK 1938
2026-01-29 02:56:27.281 [DEBUG] fake_trx.py:269 (MS@172.18.28.22:6700) Recv SETTA cmd
2026-01-29 02:56:27.596 [DEBUG] clck_gen.py:113 IND CLOCK 2040
2026-01-29 02:56:28.074 [DEBUG] clck_gen.py:113 IND CLOCK 2142
2026-01-29 02:56:28.256 [DEBUG] fake_trx.py:269 (MS@172.18.28.22:6700) Recv SETTA cmd
2026-01-29 02:56:28.551 [DEBUG] clck_gen.py:113 IND CLOCK 2244
2026-01-29 02:56:28.995 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:56:28.999 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:56:28.999 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 02:56:28.999 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 02:56:29.012 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 02:56:29.012 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:56:29.012 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:56:29.012 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:56:29.015 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 02:56:29.015 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:56:29.015 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:56:29.015 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:56:29.015 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.28.20:5700) Recv POWEROFF cmd
2026-01-29 02:56:29.015 [INFO] ctrl_if_trx.py:117 (BTS@172.18.28.20:5700) Stopping transceiver...
2026-01-29 02:56:29.015 [INFO] transceiver.py:246 Stopping clock generator
2026-01-29 02:56:29.015 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=2346 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:56:29.015 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=2346 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:56:29.015 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=2346 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:56:29.015 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=2346 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:56:29.015 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=2346 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:56:29.015 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=2346 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:56:29.015 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=2346 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:56:34.014 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.28.20:5700) Recv POWEROFF cmd
2026-01-29 02:56:34.014 [INFO] ctrl_if_trx.py:117 (BTS@172.18.28.20:5700) Stopping transceiver...
2026-01-29 02:56:34.016 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:56:34.016 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:56:34.017 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:56:34.017 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 02:56:34.025 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 02:56:34.027 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.28.20:5700) Recv SETFORMAT cmd
2026-01-29 02:56:34.027 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.28.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:56:34.027 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.28.20:5700) Recv SETFORMAT cmd
2026-01-29 02:56:34.027 [INFO] ctrl_if_trx.py:201 (BTS@172.18.28.20:5700) TRXD header version 1 -> 1
2026-01-29 02:56:34.031 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.28.20:5700/1) Recv RXTUNE cmd
2026-01-29 02:56:34.031 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.28.20:5700/1) Recv TXTUNE cmd
2026-01-29 02:56:34.031 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.28.20:5700/1) Recv SETFORMAT cmd
2026-01-29 02:56:34.032 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.28.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:56:34.032 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:56:34.032 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.28.20:5700/1) Recv NOMTXPOWER cmd
2026-01-29 02:56:34.033 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.28.20:5700/1) Recv SETFORMAT cmd
2026-01-29 02:56:34.033 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.28.20:5700/1) TRXD header version 1 -> 1
2026-01-29 02:56:34.034 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.28.20:5700/2) Recv RXTUNE cmd
2026-01-29 02:56:34.034 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.28.20:5700/2) Recv TXTUNE cmd
2026-01-29 02:56:34.034 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.28.20:5700/2) Recv SETFORMAT cmd
2026-01-29 02:56:34.034 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.28.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:56:34.035 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:56:34.035 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.28.20:5700/2) Recv NOMTXPOWER cmd
2026-01-29 02:56:34.035 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.28.20:5700/2) Recv SETFORMAT cmd
2026-01-29 02:56:34.035 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.28.20:5700/2) TRXD header version 1 -> 1
2026-01-29 02:56:34.036 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.28.20:5700/3) Recv RXTUNE cmd
2026-01-29 02:56:34.036 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.28.20:5700/3) Recv TXTUNE cmd
2026-01-29 02:56:34.036 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.28.20:5700/3) Recv SETFORMAT cmd
2026-01-29 02:56:34.036 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.28.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:56:34.036 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:56:34.036 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.28.20:5700/3) Recv NOMTXPOWER cmd
2026-01-29 02:56:34.037 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.28.20:5700/3) Recv SETFORMAT cmd
2026-01-29 02:56:34.037 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.28.20:5700/3) TRXD header version 1 -> 1
2026-01-29 02:56:34.039 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.28.20:5700) Recv RXTUNE cmd
2026-01-29 02:56:34.039 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETTSC
2026-01-29 02:56:34.039 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETTSC
2026-01-29 02:56:34.039 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETTSC
2026-01-29 02:56:34.039 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.28.20:5700) Recv TXTUNE cmd
2026-01-29 02:56:34.039 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETRXGAIN
2026-01-29 02:56:34.039 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETRXGAIN
2026-01-29 02:56:34.039 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETRXGAIN
2026-01-29 02:56:34.039 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETTSC
2026-01-29 02:56:34.039 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:56:34.039 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:56:34.039 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.28.20:5700) Recv NOMTXPOWER cmd
2026-01-29 02:56:34.039 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:56:34.040 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:56:34.040 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:56:34.040 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.28.20:5700) Recv POWERON CMD
2026-01-29 02:56:34.040 [INFO] ctrl_if_trx.py:109 (BTS@172.18.28.20:5700) Starting transceiver...
2026-01-29 02:56:34.040 [INFO] transceiver.py:243 Starting clock generator
2026-01-29 02:56:34.040 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-01-29 02:56:34.040 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:56:34.040 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:56:34.040 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:56:34.040 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETRXGAIN
2026-01-29 02:56:34.040 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:56:34.040 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:56:34.040 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:56:34.040 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:56:34.040 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:56:34.040 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:56:34.040 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:56:34.040 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:56:34.040 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:56:34.040 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:56:34.040 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:56:34.041 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:56:34.041 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:56:34.041 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:56:34.041 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:56:34.041 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:56:34.041 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:56:34.041 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:56:34.041 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:56:34.041 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:56:34.041 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:56:34.041 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:56:34.041 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:56:34.041 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:56:34.044 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-01-29 02:56:34.527 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-01-29 02:56:34.570 [DEBUG] fake_trx.py:278 (BTS@172.18.28.20:5700) Recv FAKE_TOA cmd
2026-01-29 02:56:34.573 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:56:34.573 [DEBUG] fake_trx.py:297 (BTS@172.18.28.20:5700) Recv FAKE_RSSI cmd
2026-01-29 02:56:34.575 [DEBUG] fake_trx.py:322 (BTS@172.18.28.20:5700) Recv FAKE_CI cmd
2026-01-29 02:56:34.596 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 02:56:34.596 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 02:56:34.596 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 02:56:34.601 [DEBUG] fake_trx.py:297 (BTS@172.18.28.20:5700) Recv FAKE_RSSI cmd
2026-01-29 02:56:34.605 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:56:34.605 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 02:56:34.605 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 02:56:34.606 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.28.22:6700) Recv POWERON CMD
2026-01-29 02:56:34.606 [INFO] ctrl_if_trx.py:109 (MS@172.18.28.22:6700) Starting transceiver...
2026-01-29 02:56:34.624 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:56:34.629 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 02:56:34.629 [DEBUG] fake_trx.py:297 (BTS@172.18.28.20:5700) Recv FAKE_RSSI cmd
2026-01-29 02:56:34.629 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 02:56:34.630 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:56:34.630 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:56:35.005 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-01-29 02:56:35.042 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 02:56:35.043 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:56:35.043 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:56:35.045 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:56:35.483 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-01-29 02:56:35.499 [DEBUG] fake_trx.py:269 (MS@172.18.28.22:6700) Recv SETTA cmd
2026-01-29 02:56:35.500 [DEBUG] fake_trx.py:297 (BTS@172.18.28.20:5700) Recv FAKE_RSSI cmd
2026-01-29 02:56:35.961 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-01-29 02:56:36.043 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 02:56:36.043 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:56:36.044 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:56:36.046 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:56:36.439 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-01-29 02:56:36.918 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-01-29 02:56:37.043 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 02:56:37.044 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:56:37.044 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:56:37.046 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:56:37.396 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-01-29 02:56:37.874 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-01-29 02:56:38.044 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 02:56:38.045 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:56:38.045 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:56:38.048 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:56:38.352 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-01-29 02:56:38.829 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-01-29 02:56:39.045 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 02:56:39.045 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:56:39.046 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:56:39.049 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:56:39.307 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-01-29 02:56:39.786 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-01-29 02:56:40.263 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-01-29 02:56:40.741 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-01-29 02:56:41.219 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-01-29 02:56:41.349 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:56:41.351 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:56:41.352 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 02:56:41.352 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 02:56:41.363 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 02:56:41.363 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:56:41.364 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:56:41.364 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:56:41.367 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 02:56:41.367 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:56:41.367 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:56:41.367 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.28.20:5700) Recv POWEROFF cmd
2026-01-29 02:56:41.367 [INFO] ctrl_if_trx.py:117 (BTS@172.18.28.20:5700) Stopping transceiver...
2026-01-29 02:56:41.367 [INFO] transceiver.py:246 Stopping clock generator
2026-01-29 02:56:41.367 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:56:41.368 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=1564 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:56:41.368 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=1564 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:56:41.368 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=1564 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:56:41.368 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=1564 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:56:41.368 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=1564 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:56:41.368 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=1564 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:56:41.368 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=1564 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:56:41.368 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=1564 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:56:46.366 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.28.20:5700) Recv POWEROFF cmd
2026-01-29 02:56:46.366 [INFO] ctrl_if_trx.py:117 (BTS@172.18.28.20:5700) Stopping transceiver...
2026-01-29 02:56:46.368 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:56:46.369 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:56:46.370 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:56:46.370 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 02:56:46.375 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 02:56:46.376 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.28.20:5700) Recv SETFORMAT cmd
2026-01-29 02:56:46.376 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.28.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:56:46.376 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.28.20:5700) Recv SETFORMAT cmd
2026-01-29 02:56:46.376 [INFO] ctrl_if_trx.py:201 (BTS@172.18.28.20:5700) TRXD header version 1 -> 1
2026-01-29 02:56:46.380 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.28.20:5700/1) Recv RXTUNE cmd
2026-01-29 02:56:46.380 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.28.20:5700/1) Recv TXTUNE cmd
2026-01-29 02:56:46.381 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.28.20:5700/1) Recv SETFORMAT cmd
2026-01-29 02:56:46.381 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.28.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:56:46.381 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:56:46.381 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.28.20:5700/1) Recv NOMTXPOWER cmd
2026-01-29 02:56:46.382 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.28.20:5700/1) Recv SETFORMAT cmd
2026-01-29 02:56:46.382 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.28.20:5700/1) TRXD header version 1 -> 1
2026-01-29 02:56:46.383 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.28.20:5700/2) Recv RXTUNE cmd
2026-01-29 02:56:46.383 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.28.20:5700/2) Recv TXTUNE cmd
2026-01-29 02:56:46.383 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.28.20:5700/2) Recv SETFORMAT cmd
2026-01-29 02:56:46.383 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.28.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:56:46.383 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:56:46.383 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.28.20:5700/2) Recv NOMTXPOWER cmd
2026-01-29 02:56:46.383 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.28.20:5700/2) Recv SETFORMAT cmd
2026-01-29 02:56:46.384 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.28.20:5700/2) TRXD header version 1 -> 1
2026-01-29 02:56:46.385 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.28.20:5700/3) Recv RXTUNE cmd
2026-01-29 02:56:46.385 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.28.20:5700/3) Recv TXTUNE cmd
2026-01-29 02:56:46.385 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.28.20:5700/3) Recv SETFORMAT cmd
2026-01-29 02:56:46.385 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.28.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:56:46.386 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:56:46.386 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.28.20:5700/3) Recv NOMTXPOWER cmd
2026-01-29 02:56:46.386 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.28.20:5700/3) Recv SETFORMAT cmd
2026-01-29 02:56:46.386 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.28.20:5700/3) TRXD header version 1 -> 1
2026-01-29 02:56:46.388 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.28.20:5700) Recv RXTUNE cmd
2026-01-29 02:56:46.388 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETTSC
2026-01-29 02:56:46.388 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETTSC
2026-01-29 02:56:46.388 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.28.20:5700) Recv TXTUNE cmd
2026-01-29 02:56:46.388 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETTSC
2026-01-29 02:56:46.388 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETRXGAIN
2026-01-29 02:56:46.388 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETRXGAIN
2026-01-29 02:56:46.388 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETTSC
2026-01-29 02:56:46.388 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETRXGAIN
2026-01-29 02:56:46.388 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:56:46.388 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:56:46.388 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.28.20:5700) Recv NOMTXPOWER cmd
2026-01-29 02:56:46.388 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:56:46.388 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:56:46.388 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:56:46.388 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.28.20:5700) Recv POWERON CMD
2026-01-29 02:56:46.388 [INFO] ctrl_if_trx.py:109 (BTS@172.18.28.20:5700) Starting transceiver...
2026-01-29 02:56:46.388 [INFO] transceiver.py:243 Starting clock generator
2026-01-29 02:56:46.388 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-01-29 02:56:46.389 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:56:46.389 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:56:46.389 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:56:46.389 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETRXGAIN
2026-01-29 02:56:46.389 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:56:46.389 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:56:46.389 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:56:46.389 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:56:46.389 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:56:46.389 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:56:46.389 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:56:46.389 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:56:46.389 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:56:46.389 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:56:46.389 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:56:46.389 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:56:46.389 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:56:46.389 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:56:46.389 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:56:46.389 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:56:46.389 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:56:46.389 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:56:46.389 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:56:46.389 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:56:46.389 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:56:46.389 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:56:46.389 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:56:46.389 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:56:46.393 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-01-29 02:56:46.875 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-01-29 02:56:46.917 [DEBUG] fake_trx.py:278 (BTS@172.18.28.20:5700) Recv FAKE_TOA cmd
2026-01-29 02:56:46.919 [DEBUG] fake_trx.py:297 (BTS@172.18.28.20:5700) Recv FAKE_RSSI cmd
2026-01-29 02:56:46.921 [DEBUG] fake_trx.py:322 (BTS@172.18.28.20:5700) Recv FAKE_CI cmd
2026-01-29 02:56:46.921 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:56:46.945 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 02:56:46.945 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 02:56:46.945 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 02:56:46.950 [DEBUG] fake_trx.py:297 (BTS@172.18.28.20:5700) Recv FAKE_RSSI cmd
2026-01-29 02:56:46.952 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:56:46.952 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 02:56:46.952 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 02:56:46.952 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.28.22:6700) Recv POWERON CMD
2026-01-29 02:56:46.952 [INFO] ctrl_if_trx.py:109 (MS@172.18.28.22:6700) Starting transceiver...
2026-01-29 02:56:46.970 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:56:46.974 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 02:56:46.974 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 02:56:46.975 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:56:46.975 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:56:47.352 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-01-29 02:56:47.391 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 02:56:47.391 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:56:47.392 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:56:47.395 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:56:47.830 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-01-29 02:56:47.846 [DEBUG] fake_trx.py:269 (MS@172.18.28.22:6700) Recv SETTA cmd
2026-01-29 02:56:48.308 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-01-29 02:56:48.391 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 02:56:48.392 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:56:48.392 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:56:48.396 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:56:48.786 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-01-29 02:56:49.264 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-01-29 02:56:49.393 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:56:49.393 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:56:49.393 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 02:56:49.397 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:56:49.743 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-01-29 02:56:50.222 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-01-29 02:56:50.394 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:56:50.394 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:56:50.394 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 02:56:50.398 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:56:50.700 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-01-29 02:56:51.177 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-01-29 02:56:51.394 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 02:56:51.395 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:56:51.395 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:56:51.399 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:56:51.657 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-01-29 02:56:52.135 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-01-29 02:56:52.613 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-01-29 02:56:53.091 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-01-29 02:56:53.568 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-01-29 02:56:54.047 [DEBUG] clck_gen.py:113 IND CLOCK 1632
2026-01-29 02:56:54.525 [DEBUG] clck_gen.py:113 IND CLOCK 1734
2026-01-29 02:56:55.003 [DEBUG] clck_gen.py:113 IND CLOCK 1836
2026-01-29 02:56:55.482 [DEBUG] clck_gen.py:113 IND CLOCK 1938
2026-01-29 02:56:55.960 [DEBUG] clck_gen.py:113 IND CLOCK 2040
2026-01-29 02:56:56.438 [DEBUG] clck_gen.py:113 IND CLOCK 2142
2026-01-29 02:56:56.916 [DEBUG] clck_gen.py:113 IND CLOCK 2244
2026-01-29 02:56:56.976 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:56:56.979 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:56:56.980 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 02:56:56.980 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 02:56:56.991 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 02:56:56.992 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:56:56.992 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:56:56.992 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:56:56.995 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 02:56:56.995 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:56:56.995 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:56:56.995 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:56:56.995 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.28.20:5700) Recv POWEROFF cmd
2026-01-29 02:56:56.995 [INFO] ctrl_if_trx.py:117 (BTS@172.18.28.20:5700) Stopping transceiver...
2026-01-29 02:56:56.995 [INFO] transceiver.py:246 Stopping clock generator
2026-01-29 02:56:56.995 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=2262 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:56:56.995 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=2262 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:56:56.995 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=2262 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:56:56.995 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=2262 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:56:56.995 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=2262 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:56:56.995 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=2262 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:56:56.995 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=2262 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:56:56.995 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=2263 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:56:56.995 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=2263 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:56:56.995 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=2263 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:56:56.995 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=2263 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:56:56.995 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=2263 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:56:56.995 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=2263 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:56:56.995 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=2263 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:56:56.995 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=2263 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:57:01.999 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.28.20:5700) Recv POWEROFF cmd
2026-01-29 02:57:02.000 [INFO] ctrl_if_trx.py:117 (BTS@172.18.28.20:5700) Stopping transceiver...
2026-01-29 02:57:02.000 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:57:02.000 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:57:02.000 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 02:57:02.000 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:57:02.007 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 02:57:02.008 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.28.20:5700) Recv SETFORMAT cmd
2026-01-29 02:57:02.008 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.28.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:57:02.009 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.28.20:5700) Recv SETFORMAT cmd
2026-01-29 02:57:02.009 [INFO] ctrl_if_trx.py:201 (BTS@172.18.28.20:5700) TRXD header version 1 -> 1
2026-01-29 02:57:02.011 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.28.20:5700/1) Recv RXTUNE cmd
2026-01-29 02:57:02.012 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.28.20:5700/1) Recv TXTUNE cmd
2026-01-29 02:57:02.012 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.28.20:5700/1) Recv SETFORMAT cmd
2026-01-29 02:57:02.013 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.28.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:57:02.013 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:57:02.013 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.28.20:5700/1) Recv NOMTXPOWER cmd
2026-01-29 02:57:02.014 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.28.20:5700/1) Recv SETFORMAT cmd
2026-01-29 02:57:02.014 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.28.20:5700/1) TRXD header version 1 -> 1
2026-01-29 02:57:02.015 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.28.20:5700/2) Recv RXTUNE cmd
2026-01-29 02:57:02.016 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.28.20:5700/2) Recv TXTUNE cmd
2026-01-29 02:57:02.016 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.28.20:5700/2) Recv SETFORMAT cmd
2026-01-29 02:57:02.016 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.28.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:57:02.017 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:57:02.017 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.28.20:5700/2) Recv NOMTXPOWER cmd
2026-01-29 02:57:02.017 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.28.20:5700/2) Recv SETFORMAT cmd
2026-01-29 02:57:02.017 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.28.20:5700/2) TRXD header version 1 -> 1
2026-01-29 02:57:02.019 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.28.20:5700/3) Recv RXTUNE cmd
2026-01-29 02:57:02.019 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.28.20:5700/3) Recv TXTUNE cmd
2026-01-29 02:57:02.019 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.28.20:5700/3) Recv SETFORMAT cmd
2026-01-29 02:57:02.019 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.28.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:57:02.019 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:57:02.019 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.28.20:5700/3) Recv NOMTXPOWER cmd
2026-01-29 02:57:02.019 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.28.20:5700/3) Recv SETFORMAT cmd
2026-01-29 02:57:02.019 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.28.20:5700/3) TRXD header version 1 -> 1
2026-01-29 02:57:02.023 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.28.20:5700) Recv RXTUNE cmd
2026-01-29 02:57:02.023 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETTSC
2026-01-29 02:57:02.023 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETTSC
2026-01-29 02:57:02.023 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETTSC
2026-01-29 02:57:02.023 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.28.20:5700) Recv TXTUNE cmd
2026-01-29 02:57:02.023 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETRXGAIN
2026-01-29 02:57:02.023 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETRXGAIN
2026-01-29 02:57:02.023 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETRXGAIN
2026-01-29 02:57:02.023 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETTSC
2026-01-29 02:57:02.023 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:57:02.023 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:57:02.023 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:57:02.023 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.28.20:5700) Recv NOMTXPOWER cmd
2026-01-29 02:57:02.023 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:57:02.023 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:57:02.023 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:57:02.023 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.28.20:5700) Recv POWERON CMD
2026-01-29 02:57:02.023 [INFO] ctrl_if_trx.py:109 (BTS@172.18.28.20:5700) Starting transceiver...
2026-01-29 02:57:02.023 [INFO] transceiver.py:243 Starting clock generator
2026-01-29 02:57:02.024 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-01-29 02:57:02.024 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:57:02.024 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:57:02.024 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:57:02.024 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETRXGAIN
2026-01-29 02:57:02.024 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:57:02.024 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:57:02.024 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:57:02.024 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:57:02.024 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:57:02.024 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:57:02.024 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:57:02.025 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:57:02.025 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:57:02.025 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:57:02.025 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:57:02.025 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:57:02.025 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:57:02.025 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:57:02.025 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:57:02.025 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:57:02.025 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:57:02.025 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:57:02.025 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:57:02.025 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:57:02.025 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:57:02.025 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:57:02.025 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:57:02.029 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-01-29 02:57:02.511 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-01-29 02:57:02.558 [DEBUG] fake_trx.py:278 (BTS@172.18.28.20:5700) Recv FAKE_TOA cmd
2026-01-29 02:57:02.560 [DEBUG] fake_trx.py:297 (BTS@172.18.28.20:5700) Recv FAKE_RSSI cmd
2026-01-29 02:57:02.562 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:57:02.562 [DEBUG] fake_trx.py:322 (BTS@172.18.28.20:5700) Recv FAKE_CI cmd
2026-01-29 02:57:02.589 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 02:57:02.589 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 02:57:02.589 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 02:57:02.592 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:57:02.593 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 02:57:02.593 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 02:57:02.593 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.28.22:6700) Recv POWERON CMD
2026-01-29 02:57:02.593 [INFO] ctrl_if_trx.py:109 (MS@172.18.28.22:6700) Starting transceiver...
2026-01-29 02:57:02.605 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:57:02.608 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 02:57:02.608 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 02:57:02.608 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:57:02.609 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:57:02.988 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-01-29 02:57:02.991 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:57:02.994 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:57:02.994 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 02:57:02.995 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 02:57:03.012 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 02:57:03.012 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 02:57:03.013 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 02:57:03.014 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:57:03.014 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 02:57:03.014 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 02:57:03.014 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.28.22:6700) Recv POWERON CMD
2026-01-29 02:57:03.014 [INFO] ctrl_if_trx.py:109 (MS@172.18.28.22:6700) Starting transceiver...
2026-01-29 02:57:03.027 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 02:57:03.027 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:57:03.028 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:57:03.032 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:57:03.034 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:57:03.038 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.28.22:6700) Recv SETFH cmd
2026-01-29 02:57:03.038 [INFO] transceiver.py:201 (MS@172.18.28.22:6700) Frequency hopping configured: hsn=5, maio=0, ma_len=4
2026-01-29 02:57:03.038 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:57:03.038 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:57:03.466 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-01-29 02:57:03.724 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:57:03.728 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:57:03.728 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 02:57:03.728 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 02:57:03.728 [INFO] transceiver.py:205 (MS@172.18.28.22:6700) Frequency hopping disabled
2026-01-29 02:57:03.738 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 02:57:03.738 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 02:57:03.738 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 02:57:03.739 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:57:03.739 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 02:57:03.739 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 02:57:03.739 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.28.22:6700) Recv POWERON CMD
2026-01-29 02:57:03.739 [INFO] ctrl_if_trx.py:109 (MS@172.18.28.22:6700) Starting transceiver...
2026-01-29 02:57:03.745 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:57:03.746 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 02:57:03.746 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 02:57:03.746 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:57:03.746 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:57:03.904 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:57:03.906 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:57:03.907 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 02:57:03.907 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 02:57:03.916 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 02:57:03.916 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 02:57:03.916 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 02:57:03.917 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:57:03.917 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 02:57:03.917 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 02:57:03.917 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.28.22:6700) Recv POWERON CMD
2026-01-29 02:57:03.917 [INFO] ctrl_if_trx.py:109 (MS@172.18.28.22:6700) Starting transceiver...
2026-01-29 02:57:03.936 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:57:03.940 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.28.22:6700) Recv SETFH cmd
2026-01-29 02:57:03.941 [INFO] transceiver.py:201 (MS@172.18.28.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2026-01-29 02:57:03.941 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:57:03.941 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:57:03.944 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-01-29 02:57:04.027 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:57:04.027 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 02:57:04.029 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:57:04.033 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:57:04.335 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:57:04.338 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:57:04.338 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 02:57:04.338 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 02:57:04.338 [INFO] transceiver.py:205 (MS@172.18.28.22:6700) Frequency hopping disabled
2026-01-29 02:57:04.345 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 02:57:04.345 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:57:04.345 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:57:04.345 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:57:04.346 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 02:57:04.346 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:57:04.346 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:57:04.346 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:57:04.346 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.28.20:5700) Recv POWEROFF cmd
2026-01-29 02:57:04.346 [INFO] ctrl_if_trx.py:117 (BTS@172.18.28.20:5700) Stopping transceiver...
2026-01-29 02:57:04.346 [INFO] transceiver.py:246 Stopping clock generator
2026-01-29 02:57:04.346 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=497 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:57:04.346 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=497 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:57:04.346 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=497 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:57:04.346 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=497 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:57:04.346 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=497 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:57:04.346 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=497 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:57:04.346 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=497 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:57:09.349 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.28.20:5700) Recv POWEROFF cmd
2026-01-29 02:57:09.349 [INFO] ctrl_if_trx.py:117 (BTS@172.18.28.20:5700) Stopping transceiver...
2026-01-29 02:57:09.351 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:57:09.352 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:57:09.353 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:57:09.353 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 02:57:09.358 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 02:57:09.359 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.28.20:5700) Recv SETFORMAT cmd
2026-01-29 02:57:09.360 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.28.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:57:09.360 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.28.20:5700) Recv SETFORMAT cmd
2026-01-29 02:57:09.360 [INFO] ctrl_if_trx.py:201 (BTS@172.18.28.20:5700) TRXD header version 1 -> 1
2026-01-29 02:57:09.362 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.28.20:5700/1) Recv RXTUNE cmd
2026-01-29 02:57:09.362 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.28.20:5700/1) Recv TXTUNE cmd
2026-01-29 02:57:09.363 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.28.20:5700/1) Recv SETFORMAT cmd
2026-01-29 02:57:09.363 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.28.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:57:09.363 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:57:09.364 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.28.20:5700/1) Recv NOMTXPOWER cmd
2026-01-29 02:57:09.364 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.28.20:5700/1) Recv SETFORMAT cmd
2026-01-29 02:57:09.364 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.28.20:5700/1) TRXD header version 1 -> 1
2026-01-29 02:57:09.365 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.28.20:5700/2) Recv RXTUNE cmd
2026-01-29 02:57:09.365 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.28.20:5700/2) Recv TXTUNE cmd
2026-01-29 02:57:09.366 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.28.20:5700/2) Recv SETFORMAT cmd
2026-01-29 02:57:09.366 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.28.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:57:09.366 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:57:09.366 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.28.20:5700/2) Recv NOMTXPOWER cmd
2026-01-29 02:57:09.366 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.28.20:5700/2) Recv SETFORMAT cmd
2026-01-29 02:57:09.366 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.28.20:5700/2) TRXD header version 1 -> 1
2026-01-29 02:57:09.367 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.28.20:5700/3) Recv RXTUNE cmd
2026-01-29 02:57:09.367 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.28.20:5700/3) Recv TXTUNE cmd
2026-01-29 02:57:09.367 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.28.20:5700/3) Recv SETFORMAT cmd
2026-01-29 02:57:09.367 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.28.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:57:09.367 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:57:09.367 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.28.20:5700/3) Recv NOMTXPOWER cmd
2026-01-29 02:57:09.368 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.28.20:5700/3) Recv SETFORMAT cmd
2026-01-29 02:57:09.368 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.28.20:5700/3) TRXD header version 1 -> 1
2026-01-29 02:57:09.370 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.28.20:5700) Recv RXTUNE cmd
2026-01-29 02:57:09.370 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETTSC
2026-01-29 02:57:09.370 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETTSC
2026-01-29 02:57:09.370 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETTSC
2026-01-29 02:57:09.370 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.28.20:5700) Recv TXTUNE cmd
2026-01-29 02:57:09.370 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETRXGAIN
2026-01-29 02:57:09.370 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETRXGAIN
2026-01-29 02:57:09.370 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETRXGAIN
2026-01-29 02:57:09.370 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETTSC
2026-01-29 02:57:09.370 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:57:09.370 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:57:09.370 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.28.20:5700) Recv NOMTXPOWER cmd
2026-01-29 02:57:09.370 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:57:09.370 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:57:09.370 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:57:09.370 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.28.20:5700) Recv POWERON CMD
2026-01-29 02:57:09.370 [INFO] ctrl_if_trx.py:109 (BTS@172.18.28.20:5700) Starting transceiver...
2026-01-29 02:57:09.370 [INFO] transceiver.py:243 Starting clock generator
2026-01-29 02:57:09.370 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-01-29 02:57:09.370 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:57:09.370 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:57:09.370 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:57:09.370 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETRXGAIN
2026-01-29 02:57:09.370 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:57:09.371 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:57:09.371 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:57:09.371 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:57:09.371 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:57:09.371 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:57:09.371 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:57:09.371 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:57:09.371 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:57:09.371 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:57:09.371 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:57:09.371 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:57:09.371 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:57:09.371 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:57:09.371 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:57:09.371 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:57:09.371 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:57:09.371 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:57:09.371 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:57:09.371 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:57:09.371 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:57:09.371 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:57:09.371 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:57:09.371 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:57:09.375 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-01-29 02:57:09.860 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-01-29 02:57:09.886 [DEBUG] fake_trx.py:278 (BTS@172.18.28.20:5700) Recv FAKE_TOA cmd
2026-01-29 02:57:09.887 [DEBUG] fake_trx.py:297 (BTS@172.18.28.20:5700) Recv FAKE_RSSI cmd
2026-01-29 02:57:09.888 [DEBUG] fake_trx.py:322 (BTS@172.18.28.20:5700) Recv FAKE_CI cmd
2026-01-29 02:57:09.888 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:57:09.906 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 02:57:09.907 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 02:57:09.907 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 02:57:09.912 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:57:09.912 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 02:57:09.913 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 02:57:09.913 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.28.22:6700) Recv POWERON CMD
2026-01-29 02:57:09.913 [INFO] ctrl_if_trx.py:109 (MS@172.18.28.22:6700) Starting transceiver...
2026-01-29 02:57:09.952 [DEBUG] fake_trx.py:278 (BTS@172.18.28.20:5700) Recv FAKE_TOA cmd
2026-01-29 02:57:09.956 [DEBUG] fake_trx.py:269 (MS@172.18.28.22:6700) Recv SETTA cmd
2026-01-29 02:57:09.966 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:57:09.969 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 02:57:09.970 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 02:57:09.970 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:57:09.970 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:57:10.337 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-01-29 02:57:10.373 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:57:10.373 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 02:57:10.373 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:57:10.375 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:57:10.815 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-01-29 02:57:10.833 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:57:10.836 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:57:10.836 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 02:57:10.836 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 02:57:10.845 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 02:57:10.845 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:57:10.845 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:57:10.845 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:57:10.847 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 02:57:10.847 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:57:10.847 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:57:10.847 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:57:10.847 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.28.20:5700) Recv POWEROFF cmd
2026-01-29 02:57:10.847 [INFO] ctrl_if_trx.py:117 (BTS@172.18.28.20:5700) Stopping transceiver...
2026-01-29 02:57:10.847 [INFO] transceiver.py:246 Stopping clock generator
2026-01-29 02:57:10.847 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=314 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:57:10.847 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=314 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:57:10.848 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=314 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:57:10.848 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=314 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:57:10.848 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=314 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:57:10.848 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=314 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:57:15.849 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.28.20:5700) Recv POWEROFF cmd
2026-01-29 02:57:15.849 [INFO] ctrl_if_trx.py:117 (BTS@172.18.28.20:5700) Stopping transceiver...
2026-01-29 02:57:15.850 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:57:15.851 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:57:15.852 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:57:15.852 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 02:57:15.859 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 02:57:15.859 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.28.20:5700) Recv SETFORMAT cmd
2026-01-29 02:57:15.860 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.28.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:57:15.860 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.28.20:5700) Recv SETFORMAT cmd
2026-01-29 02:57:15.860 [INFO] ctrl_if_trx.py:201 (BTS@172.18.28.20:5700) TRXD header version 1 -> 1
2026-01-29 02:57:15.862 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.28.20:5700/1) Recv RXTUNE cmd
2026-01-29 02:57:15.862 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.28.20:5700/1) Recv TXTUNE cmd
2026-01-29 02:57:15.863 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.28.20:5700/1) Recv SETFORMAT cmd
2026-01-29 02:57:15.863 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.28.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:57:15.863 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:57:15.863 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.28.20:5700/1) Recv NOMTXPOWER cmd
2026-01-29 02:57:15.864 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.28.20:5700/1) Recv SETFORMAT cmd
2026-01-29 02:57:15.864 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.28.20:5700/1) TRXD header version 1 -> 1
2026-01-29 02:57:15.864 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.28.20:5700/2) Recv RXTUNE cmd
2026-01-29 02:57:15.864 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.28.20:5700/2) Recv TXTUNE cmd
2026-01-29 02:57:15.864 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.28.20:5700/2) Recv SETFORMAT cmd
2026-01-29 02:57:15.865 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.28.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:57:15.865 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:57:15.865 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.28.20:5700/2) Recv NOMTXPOWER cmd
2026-01-29 02:57:15.865 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.28.20:5700/2) Recv SETFORMAT cmd
2026-01-29 02:57:15.865 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.28.20:5700/2) TRXD header version 1 -> 1
2026-01-29 02:57:15.866 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.28.20:5700/3) Recv RXTUNE cmd
2026-01-29 02:57:15.867 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.28.20:5700/3) Recv TXTUNE cmd
2026-01-29 02:57:15.867 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.28.20:5700/3) Recv SETFORMAT cmd
2026-01-29 02:57:15.867 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.28.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:57:15.867 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:57:15.867 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.28.20:5700/3) Recv NOMTXPOWER cmd
2026-01-29 02:57:15.867 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.28.20:5700/3) Recv SETFORMAT cmd
2026-01-29 02:57:15.867 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.28.20:5700/3) TRXD header version 1 -> 1
2026-01-29 02:57:15.869 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.28.20:5700) Recv RXTUNE cmd
2026-01-29 02:57:15.869 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETTSC
2026-01-29 02:57:15.869 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETTSC
2026-01-29 02:57:15.869 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETTSC
2026-01-29 02:57:15.869 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.28.20:5700) Recv TXTUNE cmd
2026-01-29 02:57:15.869 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETRXGAIN
2026-01-29 02:57:15.869 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETRXGAIN
2026-01-29 02:57:15.869 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETRXGAIN
2026-01-29 02:57:15.869 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETTSC
2026-01-29 02:57:15.869 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:57:15.869 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:57:15.869 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:57:15.870 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.28.20:5700) Recv NOMTXPOWER cmd
2026-01-29 02:57:15.870 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:57:15.870 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:57:15.870 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:57:15.870 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.28.20:5700) Recv POWERON CMD
2026-01-29 02:57:15.870 [INFO] ctrl_if_trx.py:109 (BTS@172.18.28.20:5700) Starting transceiver...
2026-01-29 02:57:15.870 [INFO] transceiver.py:243 Starting clock generator
2026-01-29 02:57:15.870 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-01-29 02:57:15.870 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:57:15.870 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:57:15.870 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:57:15.870 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETRXGAIN
2026-01-29 02:57:15.870 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:57:15.870 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:57:15.870 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:57:15.870 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:57:15.870 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:57:15.870 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:57:15.870 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:57:15.870 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:57:15.870 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:57:15.870 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:57:15.870 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:57:15.870 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:57:15.871 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:57:15.871 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:57:15.871 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:57:15.871 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:57:15.871 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:57:15.871 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:57:15.871 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:57:15.871 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:57:15.871 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:57:15.871 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:57:15.871 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:57:15.875 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-01-29 02:57:16.358 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-01-29 02:57:16.396 [DEBUG] fake_trx.py:278 (BTS@172.18.28.20:5700) Recv FAKE_TOA cmd
2026-01-29 02:57:16.399 [DEBUG] fake_trx.py:297 (BTS@172.18.28.20:5700) Recv FAKE_RSSI cmd
2026-01-29 02:57:16.400 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:57:16.401 [DEBUG] fake_trx.py:322 (BTS@172.18.28.20:5700) Recv FAKE_CI cmd
2026-01-29 02:57:16.419 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 02:57:16.419 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 02:57:16.420 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 02:57:16.424 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:57:16.424 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 02:57:16.425 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 02:57:16.425 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.28.22:6700) Recv POWERON CMD
2026-01-29 02:57:16.425 [INFO] ctrl_if_trx.py:109 (MS@172.18.28.22:6700) Starting transceiver...
2026-01-29 02:57:16.455 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:57:16.461 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 02:57:16.462 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 02:57:16.462 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:57:16.462 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:57:16.560 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:57:16.836 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-01-29 02:57:16.872 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 02:57:16.873 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:57:16.873 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:57:16.876 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:57:17.314 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-01-29 02:57:17.792 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-01-29 02:57:17.873 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 02:57:17.874 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:57:17.874 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:57:17.876 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:57:18.270 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-01-29 02:57:18.748 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-01-29 02:57:18.874 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 02:57:18.874 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:57:18.874 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:57:18.877 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:57:19.226 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-01-29 02:57:19.565 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:57:19.568 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:57:19.570 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 02:57:19.570 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 02:57:19.590 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 02:57:19.590 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 02:57:19.590 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 02:57:19.591 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:57:19.591 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 02:57:19.591 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 02:57:19.591 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.28.22:6700) Recv POWERON CMD
2026-01-29 02:57:19.591 [INFO] ctrl_if_trx.py:109 (MS@172.18.28.22:6700) Starting transceiver...
2026-01-29 02:57:19.597 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:57:19.598 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.28.22:6700) Recv SETFH cmd
2026-01-29 02:57:19.598 [INFO] transceiver.py:201 (MS@172.18.28.22:6700) Frequency hopping configured: hsn=5, maio=0, ma_len=4
2026-01-29 02:57:19.598 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:57:19.598 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:57:19.703 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-01-29 02:57:19.747 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:57:19.874 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 02:57:19.875 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:57:19.875 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:57:19.878 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:57:20.182 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-01-29 02:57:20.661 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-01-29 02:57:20.875 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 02:57:20.875 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:57:20.876 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:57:20.880 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:57:21.141 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-01-29 02:57:21.620 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-01-29 02:57:22.099 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-01-29 02:57:22.578 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-01-29 02:57:22.752 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:57:22.754 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:57:22.756 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 02:57:22.756 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 02:57:22.756 [INFO] transceiver.py:205 (MS@172.18.28.22:6700) Frequency hopping disabled
2026-01-29 02:57:22.776 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 02:57:22.776 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 02:57:22.777 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 02:57:22.777 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:57:22.778 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 02:57:22.778 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 02:57:22.778 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.28.22:6700) Recv POWERON CMD
2026-01-29 02:57:22.778 [INFO] ctrl_if_trx.py:109 (MS@172.18.28.22:6700) Starting transceiver...
2026-01-29 02:57:22.815 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:57:22.817 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 02:57:22.817 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 02:57:22.818 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:57:22.818 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:57:23.043 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:57:23.055 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-01-29 02:57:23.533 [DEBUG] clck_gen.py:113 IND CLOCK 1632
2026-01-29 02:57:24.011 [DEBUG] clck_gen.py:113 IND CLOCK 1734
2026-01-29 02:57:24.489 [DEBUG] clck_gen.py:113 IND CLOCK 1836
2026-01-29 02:57:24.967 [DEBUG] clck_gen.py:113 IND CLOCK 1938
2026-01-29 02:57:25.445 [DEBUG] clck_gen.py:113 IND CLOCK 2040
2026-01-29 02:57:25.922 [DEBUG] clck_gen.py:113 IND CLOCK 2142
2026-01-29 02:57:26.047 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:57:26.050 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:57:26.051 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 02:57:26.051 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 02:57:26.071 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 02:57:26.071 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 02:57:26.071 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 02:57:26.073 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:57:26.073 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 02:57:26.073 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 02:57:26.073 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.28.22:6700) Recv POWERON CMD
2026-01-29 02:57:26.073 [INFO] ctrl_if_trx.py:109 (MS@172.18.28.22:6700) Starting transceiver...
2026-01-29 02:57:26.110 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:57:26.116 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.28.22:6700) Recv SETFH cmd
2026-01-29 02:57:26.116 [INFO] transceiver.py:201 (MS@172.18.28.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2026-01-29 02:57:26.116 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:57:26.116 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:57:26.312 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:57:26.400 [DEBUG] clck_gen.py:113 IND CLOCK 2244
2026-01-29 02:57:26.879 [DEBUG] clck_gen.py:113 IND CLOCK 2346
2026-01-29 02:57:27.358 [DEBUG] clck_gen.py:113 IND CLOCK 2448
2026-01-29 02:57:27.836 [DEBUG] clck_gen.py:113 IND CLOCK 2550
2026-01-29 02:57:28.315 [DEBUG] clck_gen.py:113 IND CLOCK 2652
2026-01-29 02:57:28.793 [DEBUG] clck_gen.py:113 IND CLOCK 2754
2026-01-29 02:57:29.271 [DEBUG] clck_gen.py:113 IND CLOCK 2856
2026-01-29 02:57:29.318 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:57:29.321 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:57:29.322 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 02:57:29.323 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 02:57:29.323 [INFO] transceiver.py:205 (MS@172.18.28.22:6700) Frequency hopping disabled
2026-01-29 02:57:29.333 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 02:57:29.333 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:57:29.333 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:57:29.333 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:57:29.336 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 02:57:29.337 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:57:29.337 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:57:29.337 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.28.20:5700) Recv POWEROFF cmd
2026-01-29 02:57:29.337 [INFO] ctrl_if_trx.py:117 (BTS@172.18.28.20:5700) Stopping transceiver...
2026-01-29 02:57:29.337 [INFO] transceiver.py:246 Stopping clock generator
2026-01-29 02:57:29.337 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:57:29.337 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=2872 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:57:29.337 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=2872 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:57:29.337 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=2872 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:57:29.337 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=2872 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:57:29.337 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=2872 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:57:29.337 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=2872 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:57:29.337 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=2872 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:57:34.335 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.28.20:5700) Recv POWEROFF cmd
2026-01-29 02:57:34.335 [INFO] ctrl_if_trx.py:117 (BTS@172.18.28.20:5700) Stopping transceiver...
2026-01-29 02:57:34.337 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:57:34.338 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:57:34.338 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:57:34.338 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 02:57:34.347 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 02:57:34.348 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.28.20:5700) Recv SETFORMAT cmd
2026-01-29 02:57:34.348 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.28.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:57:34.348 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.28.20:5700) Recv SETFORMAT cmd
2026-01-29 02:57:34.349 [INFO] ctrl_if_trx.py:201 (BTS@172.18.28.20:5700) TRXD header version 1 -> 1
2026-01-29 02:57:34.351 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.28.20:5700/1) Recv RXTUNE cmd
2026-01-29 02:57:34.351 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.28.20:5700/1) Recv TXTUNE cmd
2026-01-29 02:57:34.351 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.28.20:5700/1) Recv SETFORMAT cmd
2026-01-29 02:57:34.352 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.28.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:57:34.352 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:57:34.352 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.28.20:5700/1) Recv NOMTXPOWER cmd
2026-01-29 02:57:34.353 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.28.20:5700/1) Recv SETFORMAT cmd
2026-01-29 02:57:34.353 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.28.20:5700/1) TRXD header version 1 -> 1
2026-01-29 02:57:34.353 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.28.20:5700/2) Recv RXTUNE cmd
2026-01-29 02:57:34.353 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.28.20:5700/2) Recv TXTUNE cmd
2026-01-29 02:57:34.354 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.28.20:5700/2) Recv SETFORMAT cmd
2026-01-29 02:57:34.354 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.28.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:57:34.354 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:57:34.354 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.28.20:5700/2) Recv NOMTXPOWER cmd
2026-01-29 02:57:34.354 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.28.20:5700/2) Recv SETFORMAT cmd
2026-01-29 02:57:34.354 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.28.20:5700/2) TRXD header version 1 -> 1
2026-01-29 02:57:34.356 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.28.20:5700/3) Recv RXTUNE cmd
2026-01-29 02:57:34.356 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.28.20:5700/3) Recv TXTUNE cmd
2026-01-29 02:57:34.356 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.28.20:5700/3) Recv SETFORMAT cmd
2026-01-29 02:57:34.356 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.28.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:57:34.356 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:57:34.356 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.28.20:5700/3) Recv NOMTXPOWER cmd
2026-01-29 02:57:34.356 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.28.20:5700/3) Recv SETFORMAT cmd
2026-01-29 02:57:34.356 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.28.20:5700/3) TRXD header version 1 -> 1
2026-01-29 02:57:34.358 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.28.20:5700) Recv RXTUNE cmd
2026-01-29 02:57:34.358 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETTSC
2026-01-29 02:57:34.358 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETTSC
2026-01-29 02:57:34.359 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETTSC
2026-01-29 02:57:34.359 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.28.20:5700) Recv TXTUNE cmd
2026-01-29 02:57:34.359 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETRXGAIN
2026-01-29 02:57:34.359 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETRXGAIN
2026-01-29 02:57:34.359 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETRXGAIN
2026-01-29 02:57:34.359 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETTSC
2026-01-29 02:57:34.359 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:57:34.359 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:57:34.359 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:57:34.359 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.28.20:5700) Recv NOMTXPOWER cmd
2026-01-29 02:57:34.359 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:57:34.359 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:57:34.359 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:57:34.359 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.28.20:5700) Recv POWERON CMD
2026-01-29 02:57:34.359 [INFO] ctrl_if_trx.py:109 (BTS@172.18.28.20:5700) Starting transceiver...
2026-01-29 02:57:34.359 [INFO] transceiver.py:243 Starting clock generator
2026-01-29 02:57:34.359 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-01-29 02:57:34.359 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:57:34.359 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:57:34.359 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:57:34.359 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETRXGAIN
2026-01-29 02:57:34.359 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:57:34.360 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:57:34.360 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:57:34.360 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:57:34.360 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:57:34.360 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:57:34.360 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:57:34.360 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:57:34.360 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:57:34.360 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:57:34.360 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:57:34.360 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:57:34.360 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:57:34.360 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:57:34.360 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:57:34.360 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:57:34.360 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:57:34.360 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:57:34.360 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:57:34.360 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:57:34.360 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:57:34.360 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:57:34.360 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:57:34.364 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-01-29 02:57:34.847 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-01-29 02:57:34.886 [DEBUG] fake_trx.py:278 (BTS@172.18.28.20:5700) Recv FAKE_TOA cmd
2026-01-29 02:57:34.887 [DEBUG] fake_trx.py:297 (BTS@172.18.28.20:5700) Recv FAKE_RSSI cmd
2026-01-29 02:57:34.889 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:57:34.889 [DEBUG] fake_trx.py:322 (BTS@172.18.28.20:5700) Recv FAKE_CI cmd
2026-01-29 02:57:34.892 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 02:57:34.892 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 02:57:34.893 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 02:57:34.893 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:57:34.894 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 02:57:34.894 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 02:57:34.894 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.28.22:6700) Recv POWERON CMD
2026-01-29 02:57:34.894 [INFO] ctrl_if_trx.py:109 (MS@172.18.28.22:6700) Starting transceiver...
2026-01-29 02:57:35.324 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-01-29 02:57:35.361 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 02:57:35.362 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:57:35.362 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:57:35.365 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:57:35.802 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-01-29 02:57:36.279 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-01-29 02:57:36.363 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 02:57:36.363 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:57:36.363 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:57:36.367 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:57:36.758 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-01-29 02:57:37.236 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-01-29 02:57:37.364 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:57:37.364 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 02:57:37.364 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:57:37.367 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:57:37.713 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-01-29 02:57:38.191 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-01-29 02:57:38.364 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:57:38.364 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 02:57:38.365 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:57:38.368 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:57:38.669 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-01-29 02:57:39.147 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-01-29 02:57:39.365 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:57:39.365 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 02:57:39.367 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:57:39.368 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:57:39.624 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-01-29 02:57:40.102 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-01-29 02:57:40.580 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-01-29 02:57:41.058 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-01-29 02:57:41.536 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-01-29 02:57:42.014 [DEBUG] clck_gen.py:113 IND CLOCK 1632
2026-01-29 02:57:42.492 [DEBUG] clck_gen.py:113 IND CLOCK 1734
2026-01-29 02:57:42.970 [DEBUG] clck_gen.py:113 IND CLOCK 1836
2026-01-29 02:57:43.448 [DEBUG] clck_gen.py:113 IND CLOCK 1938
2026-01-29 02:57:43.925 [DEBUG] clck_gen.py:113 IND CLOCK 2040
2026-01-29 02:57:44.403 [DEBUG] clck_gen.py:113 IND CLOCK 2142
2026-01-29 02:57:44.881 [DEBUG] clck_gen.py:113 IND CLOCK 2244
2026-01-29 02:57:45.359 [DEBUG] clck_gen.py:113 IND CLOCK 2346
2026-01-29 02:57:45.836 [DEBUG] clck_gen.py:113 IND CLOCK 2448
2026-01-29 02:57:46.314 [DEBUG] clck_gen.py:113 IND CLOCK 2550
2026-01-29 02:57:46.792 [DEBUG] clck_gen.py:113 IND CLOCK 2652
2026-01-29 02:57:47.270 [DEBUG] clck_gen.py:113 IND CLOCK 2754
2026-01-29 02:57:47.748 [DEBUG] clck_gen.py:113 IND CLOCK 2856
2026-01-29 02:57:48.226 [DEBUG] clck_gen.py:113 IND CLOCK 2958
2026-01-29 02:57:48.704 [DEBUG] clck_gen.py:113 IND CLOCK 3060
2026-01-29 02:57:48.989 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 02:57:48.989 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 02:57:48.999 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 02:57:48.999 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:57:48.999 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:57:48.999 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:57:49.002 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 02:57:49.002 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:57:49.002 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:57:49.002 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:57:49.002 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.28.20:5700) Recv POWEROFF cmd
2026-01-29 02:57:49.003 [INFO] ctrl_if_trx.py:117 (BTS@172.18.28.20:5700) Stopping transceiver...
2026-01-29 02:57:49.003 [INFO] transceiver.py:246 Stopping clock generator
2026-01-29 02:57:49.003 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=3126 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:57:49.003 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=3126 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:57:49.003 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=3126 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:57:49.003 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=3126 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:57:49.003 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=3126 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:57:49.003 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=3126 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:57:54.002 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.28.20:5700) Recv POWEROFF cmd
2026-01-29 02:57:54.002 [INFO] ctrl_if_trx.py:117 (BTS@172.18.28.20:5700) Stopping transceiver...
2026-01-29 02:57:54.004 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:57:54.005 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:57:54.006 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:57:54.006 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 02:57:54.014 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 02:57:54.015 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.28.20:5700) Recv SETFORMAT cmd
2026-01-29 02:57:54.015 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.28.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:57:54.016 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.28.20:5700) Recv SETFORMAT cmd
2026-01-29 02:57:54.016 [INFO] ctrl_if_trx.py:201 (BTS@172.18.28.20:5700) TRXD header version 1 -> 1
2026-01-29 02:57:54.018 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.28.20:5700/1) Recv RXTUNE cmd
2026-01-29 02:57:54.018 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.28.20:5700/1) Recv TXTUNE cmd
2026-01-29 02:57:54.019 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.28.20:5700/1) Recv SETFORMAT cmd
2026-01-29 02:57:54.019 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.28.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:57:54.019 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:57:54.019 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.28.20:5700/1) Recv NOMTXPOWER cmd
2026-01-29 02:57:54.019 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.28.20:5700/1) Recv SETFORMAT cmd
2026-01-29 02:57:54.019 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.28.20:5700/1) TRXD header version 1 -> 1
2026-01-29 02:57:54.021 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.28.20:5700/2) Recv RXTUNE cmd
2026-01-29 02:57:54.021 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.28.20:5700/2) Recv TXTUNE cmd
2026-01-29 02:57:54.021 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.28.20:5700/2) Recv SETFORMAT cmd
2026-01-29 02:57:54.021 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.28.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:57:54.021 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:57:54.021 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.28.20:5700/2) Recv NOMTXPOWER cmd
2026-01-29 02:57:54.022 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.28.20:5700/2) Recv SETFORMAT cmd
2026-01-29 02:57:54.022 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.28.20:5700/2) TRXD header version 1 -> 1
2026-01-29 02:57:54.023 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.28.20:5700/3) Recv RXTUNE cmd
2026-01-29 02:57:54.023 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.28.20:5700/3) Recv TXTUNE cmd
2026-01-29 02:57:54.023 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.28.20:5700/3) Recv SETFORMAT cmd
2026-01-29 02:57:54.023 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.28.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:57:54.023 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:57:54.023 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.28.20:5700/3) Recv NOMTXPOWER cmd
2026-01-29 02:57:54.023 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.28.20:5700/3) Recv SETFORMAT cmd
2026-01-29 02:57:54.023 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.28.20:5700/3) TRXD header version 1 -> 1
2026-01-29 02:57:54.025 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.28.20:5700) Recv RXTUNE cmd
2026-01-29 02:57:54.025 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETTSC
2026-01-29 02:57:54.025 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETTSC
2026-01-29 02:57:54.025 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETTSC
2026-01-29 02:57:54.025 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.28.20:5700) Recv TXTUNE cmd
2026-01-29 02:57:54.026 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETRXGAIN
2026-01-29 02:57:54.026 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETRXGAIN
2026-01-29 02:57:54.026 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETRXGAIN
2026-01-29 02:57:54.026 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETTSC
2026-01-29 02:57:54.026 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:57:54.026 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:57:54.026 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:57:54.026 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.28.20:5700) Recv NOMTXPOWER cmd
2026-01-29 02:57:54.026 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:57:54.026 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:57:54.026 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:57:54.026 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.28.20:5700) Recv POWERON CMD
2026-01-29 02:57:54.026 [INFO] ctrl_if_trx.py:109 (BTS@172.18.28.20:5700) Starting transceiver...
2026-01-29 02:57:54.026 [INFO] transceiver.py:243 Starting clock generator
2026-01-29 02:57:54.026 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-01-29 02:57:54.026 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:57:54.026 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:57:54.026 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:57:54.026 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETRXGAIN
2026-01-29 02:57:54.026 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:57:54.026 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:57:54.026 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:57:54.026 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:57:54.026 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:57:54.026 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:57:54.026 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:57:54.026 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:57:54.027 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:57:54.027 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:57:54.027 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:57:54.027 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:57:54.027 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:57:54.027 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:57:54.027 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:57:54.027 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:57:54.027 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:57:54.027 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:57:54.027 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:57:54.027 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:57:54.027 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:57:54.027 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:57:54.027 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:57:54.031 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-01-29 02:57:54.515 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-01-29 02:57:54.546 [DEBUG] fake_trx.py:278 (BTS@172.18.28.20:5700) Recv FAKE_TOA cmd
2026-01-29 02:57:54.547 [DEBUG] fake_trx.py:297 (BTS@172.18.28.20:5700) Recv FAKE_RSSI cmd
2026-01-29 02:57:54.547 [DEBUG] fake_trx.py:322 (BTS@172.18.28.20:5700) Recv FAKE_CI cmd
2026-01-29 02:57:54.549 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:57:54.563 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 02:57:54.563 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 02:57:54.564 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 02:57:54.569 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:57:54.569 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 02:57:54.570 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 02:57:54.570 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.28.22:6700) Recv POWERON CMD
2026-01-29 02:57:54.570 [INFO] ctrl_if_trx.py:109 (MS@172.18.28.22:6700) Starting transceiver...
2026-01-29 02:57:54.611 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:57:54.617 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.28.22:6700) Recv SETFH cmd
2026-01-29 02:57:54.617 [INFO] transceiver.py:201 (MS@172.18.28.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2026-01-29 02:57:54.618 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:57:54.618 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:57:54.993 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-01-29 02:57:55.029 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:57:55.029 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 02:57:55.029 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:57:55.031 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:57:55.472 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-01-29 02:57:55.950 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-01-29 02:57:56.030 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 02:57:56.031 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:57:56.031 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:57:56.032 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:57:56.429 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-01-29 02:57:56.618 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:57:56.618 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 02:57:56.618 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 02:57:56.618 [INFO] transceiver.py:205 (MS@172.18.28.22:6700) Frequency hopping disabled
2026-01-29 02:57:56.619 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 02:57:56.621 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:57:56.622 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 02:57:56.622 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 02:57:56.622 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.28.22:6700) Recv POWERON CMD
2026-01-29 02:57:56.622 [INFO] ctrl_if_trx.py:109 (MS@172.18.28.22:6700) Starting transceiver...
2026-01-29 02:57:56.907 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-01-29 02:57:57.031 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:57:57.032 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:57:57.032 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 02:57:57.033 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:57:57.385 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-01-29 02:57:57.863 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-01-29 02:57:58.032 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:57:58.033 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:57:58.033 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 02:57:58.033 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:57:58.340 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-01-29 02:57:58.818 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-01-29 02:57:59.033 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:57:59.034 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:57:59.034 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 02:57:59.034 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:57:59.296 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-01-29 02:57:59.774 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-01-29 02:58:00.252 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-01-29 02:58:00.730 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-01-29 02:58:01.208 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-01-29 02:58:01.686 [DEBUG] clck_gen.py:113 IND CLOCK 1632
2026-01-29 02:58:02.164 [DEBUG] clck_gen.py:113 IND CLOCK 1734
2026-01-29 02:58:02.642 [DEBUG] clck_gen.py:113 IND CLOCK 1836
2026-01-29 02:58:03.120 [DEBUG] clck_gen.py:113 IND CLOCK 1938
2026-01-29 02:58:03.597 [DEBUG] clck_gen.py:113 IND CLOCK 2040
2026-01-29 02:58:04.076 [DEBUG] clck_gen.py:113 IND CLOCK 2142
2026-01-29 02:58:04.553 [DEBUG] clck_gen.py:113 IND CLOCK 2244
2026-01-29 02:58:05.031 [DEBUG] clck_gen.py:113 IND CLOCK 2346
2026-01-29 02:58:05.509 [DEBUG] clck_gen.py:113 IND CLOCK 2448
2026-01-29 02:58:05.987 [DEBUG] clck_gen.py:113 IND CLOCK 2550
2026-01-29 02:58:06.465 [DEBUG] clck_gen.py:113 IND CLOCK 2652
2026-01-29 02:58:06.943 [DEBUG] clck_gen.py:113 IND CLOCK 2754
2026-01-29 02:58:07.421 [DEBUG] clck_gen.py:113 IND CLOCK 2856
2026-01-29 02:58:07.899 [DEBUG] clck_gen.py:113 IND CLOCK 2958
2026-01-29 02:58:08.376 [DEBUG] clck_gen.py:113 IND CLOCK 3060
2026-01-29 02:58:08.854 [DEBUG] clck_gen.py:113 IND CLOCK 3162
2026-01-29 02:58:09.332 [DEBUG] clck_gen.py:113 IND CLOCK 3264
2026-01-29 02:58:09.810 [DEBUG] clck_gen.py:113 IND CLOCK 3366
2026-01-29 02:58:10.288 [DEBUG] clck_gen.py:113 IND CLOCK 3468
2026-01-29 02:58:10.766 [DEBUG] clck_gen.py:113 IND CLOCK 3570
2026-01-29 02:58:11.243 [DEBUG] clck_gen.py:113 IND CLOCK 3672
2026-01-29 02:58:11.721 [DEBUG] clck_gen.py:113 IND CLOCK 3774
2026-01-29 02:58:12.199 [DEBUG] clck_gen.py:113 IND CLOCK 3876
2026-01-29 02:58:12.676 [DEBUG] clck_gen.py:113 IND CLOCK 3978
2026-01-29 02:58:13.154 [DEBUG] clck_gen.py:113 IND CLOCK 4080
2026-01-29 02:58:13.632 [DEBUG] clck_gen.py:113 IND CLOCK 4182
2026-01-29 02:58:14.110 [DEBUG] clck_gen.py:113 IND CLOCK 4284
2026-01-29 02:58:14.588 [DEBUG] clck_gen.py:113 IND CLOCK 4386
2026-01-29 02:58:15.065 [DEBUG] clck_gen.py:113 IND CLOCK 4488
2026-01-29 02:58:15.543 [DEBUG] clck_gen.py:113 IND CLOCK 4590
2026-01-29 02:58:16.022 [DEBUG] clck_gen.py:113 IND CLOCK 4692
2026-01-29 02:58:16.499 [DEBUG] clck_gen.py:113 IND CLOCK 4794
2026-01-29 02:58:16.976 [DEBUG] clck_gen.py:113 IND CLOCK 4896
2026-01-29 02:58:17.454 [DEBUG] clck_gen.py:113 IND CLOCK 4998
2026-01-29 02:58:17.932 [DEBUG] clck_gen.py:113 IND CLOCK 5100
2026-01-29 02:58:18.411 [DEBUG] clck_gen.py:113 IND CLOCK 5202
2026-01-29 02:58:18.889 [DEBUG] clck_gen.py:113 IND CLOCK 5304
2026-01-29 02:58:19.367 [DEBUG] clck_gen.py:113 IND CLOCK 5406
2026-01-29 02:58:19.636 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:58:19.640 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 02:58:19.640 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 02:58:19.654 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 02:58:19.654 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:58:19.657 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:58:19.657 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:58:19.658 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 02:58:19.658 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:58:19.658 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.28.20:5700) Recv POWEROFF cmd
2026-01-29 02:58:19.658 [INFO] ctrl_if_trx.py:117 (BTS@172.18.28.20:5700) Stopping transceiver...
2026-01-29 02:58:19.658 [INFO] transceiver.py:246 Stopping clock generator
2026-01-29 02:58:19.658 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:58:19.659 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:58:19.659 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=5470 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:58:19.659 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=5470 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:58:19.659 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=5470 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:58:19.659 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=5470 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:58:19.659 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=5470 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:58:19.659 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=5470 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:58:19.659 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=5471 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:58:19.659 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=5471 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:58:19.660 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=5471 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:58:19.660 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=5471 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:58:19.660 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=5471 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:58:19.660 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=5471 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:58:19.660 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=5471 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:58:19.660 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=5471 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:58:24.658 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.28.20:5700) Recv POWEROFF cmd
2026-01-29 02:58:24.658 [INFO] ctrl_if_trx.py:117 (BTS@172.18.28.20:5700) Stopping transceiver...
2026-01-29 02:58:24.660 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:58:24.661 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:58:24.662 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:58:24.662 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 02:58:24.668 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 02:58:24.669 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.28.20:5700) Recv SETFORMAT cmd
2026-01-29 02:58:24.669 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.28.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:58:24.670 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.28.20:5700) Recv SETFORMAT cmd
2026-01-29 02:58:24.670 [INFO] ctrl_if_trx.py:201 (BTS@172.18.28.20:5700) TRXD header version 1 -> 1
2026-01-29 02:58:24.674 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.28.20:5700/1) Recv RXTUNE cmd
2026-01-29 02:58:24.674 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.28.20:5700/1) Recv TXTUNE cmd
2026-01-29 02:58:24.675 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.28.20:5700/1) Recv SETFORMAT cmd
2026-01-29 02:58:24.675 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.28.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:58:24.675 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:58:24.675 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.28.20:5700/1) Recv NOMTXPOWER cmd
2026-01-29 02:58:24.675 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.28.20:5700/1) Recv SETFORMAT cmd
2026-01-29 02:58:24.675 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.28.20:5700/1) TRXD header version 1 -> 1
2026-01-29 02:58:24.678 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.28.20:5700/2) Recv RXTUNE cmd
2026-01-29 02:58:24.678 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.28.20:5700/2) Recv TXTUNE cmd
2026-01-29 02:58:24.678 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.28.20:5700/2) Recv SETFORMAT cmd
2026-01-29 02:58:24.678 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.28.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:58:24.679 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:58:24.679 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.28.20:5700/2) Recv NOMTXPOWER cmd
2026-01-29 02:58:24.679 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.28.20:5700/2) Recv SETFORMAT cmd
2026-01-29 02:58:24.679 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.28.20:5700/2) TRXD header version 1 -> 1
2026-01-29 02:58:24.681 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.28.20:5700/3) Recv RXTUNE cmd
2026-01-29 02:58:24.681 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.28.20:5700/3) Recv TXTUNE cmd
2026-01-29 02:58:24.681 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.28.20:5700/3) Recv SETFORMAT cmd
2026-01-29 02:58:24.681 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.28.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:58:24.681 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:58:24.682 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.28.20:5700/3) Recv NOMTXPOWER cmd
2026-01-29 02:58:24.682 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.28.20:5700/3) Recv SETFORMAT cmd
2026-01-29 02:58:24.682 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.28.20:5700/3) TRXD header version 1 -> 1
2026-01-29 02:58:24.685 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.28.20:5700) Recv RXTUNE cmd
2026-01-29 02:58:24.685 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETTSC
2026-01-29 02:58:24.685 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETTSC
2026-01-29 02:58:24.685 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETTSC
2026-01-29 02:58:24.685 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.28.20:5700) Recv TXTUNE cmd
2026-01-29 02:58:24.685 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETRXGAIN
2026-01-29 02:58:24.685 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETRXGAIN
2026-01-29 02:58:24.685 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETRXGAIN
2026-01-29 02:58:24.685 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETTSC
2026-01-29 02:58:24.685 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:58:24.685 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:58:24.685 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.28.20:5700) Recv NOMTXPOWER cmd
2026-01-29 02:58:24.685 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:58:24.685 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:58:24.685 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:58:24.685 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.28.20:5700) Recv POWERON CMD
2026-01-29 02:58:24.685 [INFO] ctrl_if_trx.py:109 (BTS@172.18.28.20:5700) Starting transceiver...
2026-01-29 02:58:24.685 [INFO] transceiver.py:243 Starting clock generator
2026-01-29 02:58:24.685 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-01-29 02:58:24.686 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:58:24.686 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:58:24.686 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:58:24.686 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETRXGAIN
2026-01-29 02:58:24.686 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:58:24.686 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:58:24.686 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:58:24.686 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:58:24.686 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:58:24.686 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:58:24.686 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:58:24.686 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:58:24.686 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:58:24.686 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:58:24.686 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:58:24.686 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:58:24.686 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:58:24.686 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:58:24.686 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:58:24.687 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:58:24.687 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:58:24.687 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:58:24.687 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:58:24.687 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:58:24.687 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:58:24.687 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:58:24.687 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:58:24.687 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:58:24.690 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-01-29 02:58:25.171 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-01-29 02:58:25.214 [DEBUG] fake_trx.py:278 (BTS@172.18.28.20:5700) Recv FAKE_TOA cmd
2026-01-29 02:58:25.216 [DEBUG] fake_trx.py:297 (BTS@172.18.28.20:5700) Recv FAKE_RSSI cmd
2026-01-29 02:58:25.218 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:58:25.219 [DEBUG] fake_trx.py:322 (BTS@172.18.28.20:5700) Recv FAKE_CI cmd
2026-01-29 02:58:25.222 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 02:58:25.222 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 02:58:25.222 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 02:58:25.222 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:58:25.223 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 02:58:25.223 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 02:58:25.223 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.28.22:6700) Recv POWERON CMD
2026-01-29 02:58:25.223 [INFO] ctrl_if_trx.py:109 (MS@172.18.28.22:6700) Starting transceiver...
2026-01-29 02:58:25.649 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-01-29 02:58:25.688 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 02:58:25.689 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:58:25.690 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:58:25.693 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:58:26.126 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-01-29 02:58:26.604 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-01-29 02:58:26.690 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:58:26.690 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 02:58:26.691 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:58:26.694 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:58:27.082 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-01-29 02:58:27.560 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-01-29 02:58:27.690 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 02:58:27.691 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:58:27.693 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:58:27.695 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:58:28.038 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-01-29 02:58:28.516 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-01-29 02:58:28.692 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 02:58:28.692 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:58:28.694 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:58:28.696 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:58:28.994 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-01-29 02:58:29.472 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-01-29 02:58:29.693 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 02:58:29.693 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:58:29.695 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:58:29.697 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:58:29.950 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-01-29 02:58:30.428 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-01-29 02:58:30.905 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-01-29 02:58:31.383 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-01-29 02:58:31.860 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-01-29 02:58:32.338 [DEBUG] clck_gen.py:113 IND CLOCK 1632
2026-01-29 02:58:32.816 [DEBUG] clck_gen.py:113 IND CLOCK 1734
2026-01-29 02:58:33.293 [DEBUG] clck_gen.py:113 IND CLOCK 1836
2026-01-29 02:58:33.771 [DEBUG] clck_gen.py:113 IND CLOCK 1938
2026-01-29 02:58:34.249 [DEBUG] clck_gen.py:113 IND CLOCK 2040
2026-01-29 02:58:34.726 [DEBUG] clck_gen.py:113 IND CLOCK 2142
2026-01-29 02:58:35.204 [DEBUG] clck_gen.py:113 IND CLOCK 2244
2026-01-29 02:58:35.682 [DEBUG] clck_gen.py:113 IND CLOCK 2346
2026-01-29 02:58:36.160 [DEBUG] clck_gen.py:113 IND CLOCK 2448
2026-01-29 02:58:36.635 [DEBUG] clck_gen.py:113 IND CLOCK 2550
2026-01-29 02:58:37.113 [DEBUG] clck_gen.py:113 IND CLOCK 2652
2026-01-29 02:58:37.590 [DEBUG] clck_gen.py:113 IND CLOCK 2754
2026-01-29 02:58:38.069 [DEBUG] clck_gen.py:113 IND CLOCK 2856
2026-01-29 02:58:38.546 [DEBUG] clck_gen.py:113 IND CLOCK 2958
2026-01-29 02:58:39.024 [DEBUG] clck_gen.py:113 IND CLOCK 3060
2026-01-29 02:58:39.501 [DEBUG] clck_gen.py:113 IND CLOCK 3162
2026-01-29 02:58:39.979 [DEBUG] clck_gen.py:113 IND CLOCK 3264
2026-01-29 02:58:40.457 [DEBUG] clck_gen.py:113 IND CLOCK 3366
2026-01-29 02:58:40.935 [DEBUG] clck_gen.py:113 IND CLOCK 3468
2026-01-29 02:58:41.413 [DEBUG] clck_gen.py:113 IND CLOCK 3570
2026-01-29 02:58:41.891 [DEBUG] clck_gen.py:113 IND CLOCK 3672
2026-01-29 02:58:42.369 [DEBUG] clck_gen.py:113 IND CLOCK 3774
2026-01-29 02:58:42.847 [DEBUG] clck_gen.py:113 IND CLOCK 3876
2026-01-29 02:58:43.325 [DEBUG] clck_gen.py:113 IND CLOCK 3978
2026-01-29 02:58:43.802 [DEBUG] clck_gen.py:113 IND CLOCK 4080
2026-01-29 02:58:44.280 [DEBUG] clck_gen.py:113 IND CLOCK 4182
2026-01-29 02:58:44.757 [DEBUG] clck_gen.py:113 IND CLOCK 4284
2026-01-29 02:58:45.235 [DEBUG] clck_gen.py:113 IND CLOCK 4386
2026-01-29 02:58:45.713 [DEBUG] clck_gen.py:113 IND CLOCK 4488
2026-01-29 02:58:46.192 [DEBUG] clck_gen.py:113 IND CLOCK 4590
2026-01-29 02:58:46.670 [DEBUG] clck_gen.py:113 IND CLOCK 4692
2026-01-29 02:58:46.705 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 02:58:46.706 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 02:58:46.709 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 02:58:46.709 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:58:46.709 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:58:46.709 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:58:46.710 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 02:58:46.710 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:58:46.710 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:58:46.710 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:58:46.710 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.28.20:5700) Recv POWEROFF cmd
2026-01-29 02:58:46.710 [INFO] ctrl_if_trx.py:117 (BTS@172.18.28.20:5700) Stopping transceiver...
2026-01-29 02:58:46.710 [INFO] transceiver.py:246 Stopping clock generator
2026-01-29 02:58:46.710 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=4702 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:58:46.710 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=4702 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:58:46.710 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=4702 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:58:46.710 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=4702 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:58:46.710 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=4702 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:58:46.710 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=4702 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:58:46.710 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=4702 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:58:46.710 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=4702 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:58:51.713 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.28.20:5700) Recv POWEROFF cmd
2026-01-29 02:58:51.713 [INFO] ctrl_if_trx.py:117 (BTS@172.18.28.20:5700) Stopping transceiver...
2026-01-29 02:58:51.714 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:58:51.716 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:58:51.717 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:58:51.717 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 02:58:51.722 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 02:58:51.723 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.28.20:5700) Recv SETFORMAT cmd
2026-01-29 02:58:51.723 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.28.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:58:51.723 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.28.20:5700) Recv SETFORMAT cmd
2026-01-29 02:58:51.723 [INFO] ctrl_if_trx.py:201 (BTS@172.18.28.20:5700) TRXD header version 1 -> 1
2026-01-29 02:58:51.726 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.28.20:5700/1) Recv RXTUNE cmd
2026-01-29 02:58:51.727 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.28.20:5700/1) Recv TXTUNE cmd
2026-01-29 02:58:51.727 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.28.20:5700/1) Recv SETFORMAT cmd
2026-01-29 02:58:51.728 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.28.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:58:51.728 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:58:51.728 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.28.20:5700/1) Recv NOMTXPOWER cmd
2026-01-29 02:58:51.728 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.28.20:5700/1) Recv SETFORMAT cmd
2026-01-29 02:58:51.729 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.28.20:5700/1) TRXD header version 1 -> 1
2026-01-29 02:58:51.730 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.28.20:5700/2) Recv RXTUNE cmd
2026-01-29 02:58:51.730 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.28.20:5700/2) Recv TXTUNE cmd
2026-01-29 02:58:51.730 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.28.20:5700/2) Recv SETFORMAT cmd
2026-01-29 02:58:51.730 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.28.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:58:51.730 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:58:51.730 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.28.20:5700/2) Recv NOMTXPOWER cmd
2026-01-29 02:58:51.731 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.28.20:5700/2) Recv SETFORMAT cmd
2026-01-29 02:58:51.731 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.28.20:5700/2) TRXD header version 1 -> 1
2026-01-29 02:58:51.732 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.28.20:5700/3) Recv RXTUNE cmd
2026-01-29 02:58:51.732 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.28.20:5700/3) Recv TXTUNE cmd
2026-01-29 02:58:51.733 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.28.20:5700/3) Recv SETFORMAT cmd
2026-01-29 02:58:51.733 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.28.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:58:51.733 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:58:51.733 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.28.20:5700/3) Recv NOMTXPOWER cmd
2026-01-29 02:58:51.733 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.28.20:5700/3) Recv SETFORMAT cmd
2026-01-29 02:58:51.733 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.28.20:5700/3) TRXD header version 1 -> 1
2026-01-29 02:58:51.735 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.28.20:5700) Recv RXTUNE cmd
2026-01-29 02:58:51.735 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETTSC
2026-01-29 02:58:51.735 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETTSC
2026-01-29 02:58:51.735 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETTSC
2026-01-29 02:58:51.735 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.28.20:5700) Recv TXTUNE cmd
2026-01-29 02:58:51.736 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETRXGAIN
2026-01-29 02:58:51.736 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETRXGAIN
2026-01-29 02:58:51.736 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETRXGAIN
2026-01-29 02:58:51.736 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETTSC
2026-01-29 02:58:51.736 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:58:51.736 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:58:51.736 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:58:51.736 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.28.20:5700) Recv NOMTXPOWER cmd
2026-01-29 02:58:51.736 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:58:51.736 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:58:51.736 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:58:51.736 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.28.20:5700) Recv POWERON CMD
2026-01-29 02:58:51.736 [INFO] ctrl_if_trx.py:109 (BTS@172.18.28.20:5700) Starting transceiver...
2026-01-29 02:58:51.736 [INFO] transceiver.py:243 Starting clock generator
2026-01-29 02:58:51.736 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:58:51.736 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-01-29 02:58:51.736 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:58:51.736 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:58:51.736 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETRXGAIN
2026-01-29 02:58:51.736 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:58:51.736 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:58:51.737 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:58:51.737 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:58:51.737 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:58:51.737 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:58:51.737 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:58:51.737 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:58:51.737 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:58:51.737 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:58:51.737 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:58:51.737 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:58:51.737 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:58:51.737 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:58:51.737 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:58:51.737 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:58:51.737 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:58:51.737 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:58:51.737 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:58:51.737 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:58:51.737 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:58:51.737 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:58:51.737 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:58:51.741 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-01-29 02:58:52.224 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-01-29 02:58:52.270 [DEBUG] fake_trx.py:278 (BTS@172.18.28.20:5700) Recv FAKE_TOA cmd
2026-01-29 02:58:52.272 [DEBUG] fake_trx.py:297 (BTS@172.18.28.20:5700) Recv FAKE_RSSI cmd
2026-01-29 02:58:52.273 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:58:52.274 [DEBUG] fake_trx.py:322 (BTS@172.18.28.20:5700) Recv FAKE_CI cmd
2026-01-29 02:58:52.277 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 02:58:52.277 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 02:58:52.278 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 02:58:52.278 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:58:52.278 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 02:58:52.278 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 02:58:52.278 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.28.22:6700) Recv POWERON CMD
2026-01-29 02:58:52.278 [INFO] ctrl_if_trx.py:109 (MS@172.18.28.22:6700) Starting transceiver...
2026-01-29 02:58:52.702 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-01-29 02:58:52.739 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 02:58:52.739 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:58:52.740 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:58:52.744 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:58:53.180 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-01-29 02:58:53.657 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-01-29 02:58:53.740 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 02:58:53.740 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:58:53.741 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:58:53.745 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:58:54.135 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-01-29 02:58:54.613 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-01-29 02:58:54.740 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 02:58:54.741 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:58:54.741 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:58:54.746 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:58:55.091 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-01-29 02:58:55.569 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-01-29 02:58:55.741 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 02:58:55.741 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:58:55.742 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:58:55.747 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:58:56.047 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-01-29 02:58:56.525 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-01-29 02:58:56.742 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:58:56.742 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:58:56.743 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 02:58:56.748 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:58:57.003 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-01-29 02:58:57.481 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-01-29 02:58:57.959 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-01-29 02:58:58.437 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-01-29 02:58:58.914 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-01-29 02:58:59.392 [DEBUG] clck_gen.py:113 IND CLOCK 1632
2026-01-29 02:58:59.870 [DEBUG] clck_gen.py:113 IND CLOCK 1734
2026-01-29 02:59:00.348 [DEBUG] clck_gen.py:113 IND CLOCK 1836
2026-01-29 02:59:00.826 [DEBUG] clck_gen.py:113 IND CLOCK 1938
2026-01-29 02:59:01.300 [DEBUG] clck_gen.py:113 IND CLOCK 2040
2026-01-29 02:59:01.774 [DEBUG] clck_gen.py:113 IND CLOCK 2142
2026-01-29 02:59:02.252 [DEBUG] clck_gen.py:113 IND CLOCK 2244
2026-01-29 02:59:02.730 [DEBUG] clck_gen.py:113 IND CLOCK 2346
2026-01-29 02:59:03.208 [DEBUG] clck_gen.py:113 IND CLOCK 2448
2026-01-29 02:59:03.686 [DEBUG] clck_gen.py:113 IND CLOCK 2550
2026-01-29 02:59:04.164 [DEBUG] clck_gen.py:113 IND CLOCK 2652
2026-01-29 02:59:04.642 [DEBUG] clck_gen.py:113 IND CLOCK 2754
2026-01-29 02:59:05.119 [DEBUG] clck_gen.py:113 IND CLOCK 2856
2026-01-29 02:59:05.598 [DEBUG] clck_gen.py:113 IND CLOCK 2958
2026-01-29 02:59:06.075 [DEBUG] clck_gen.py:113 IND CLOCK 3060
2026-01-29 02:59:06.552 [DEBUG] clck_gen.py:113 IND CLOCK 3162
2026-01-29 02:59:07.029 [DEBUG] clck_gen.py:113 IND CLOCK 3264
2026-01-29 02:59:07.507 [DEBUG] clck_gen.py:113 IND CLOCK 3366
2026-01-29 02:59:07.984 [DEBUG] clck_gen.py:113 IND CLOCK 3468
2026-01-29 02:59:08.457 [DEBUG] clck_gen.py:113 IND CLOCK 3570
2026-01-29 02:59:08.934 [DEBUG] clck_gen.py:113 IND CLOCK 3672
2026-01-29 02:59:09.412 [DEBUG] clck_gen.py:113 IND CLOCK 3774
2026-01-29 02:59:09.889 [DEBUG] clck_gen.py:113 IND CLOCK 3876
2026-01-29 02:59:10.367 [DEBUG] clck_gen.py:113 IND CLOCK 3978
2026-01-29 02:59:10.844 [DEBUG] clck_gen.py:113 IND CLOCK 4080
2026-01-29 02:59:11.322 [DEBUG] clck_gen.py:113 IND CLOCK 4182
2026-01-29 02:59:11.800 [DEBUG] clck_gen.py:113 IND CLOCK 4284
2026-01-29 02:59:12.278 [DEBUG] clck_gen.py:113 IND CLOCK 4386
2026-01-29 02:59:12.756 [DEBUG] clck_gen.py:113 IND CLOCK 4488
2026-01-29 02:59:13.234 [DEBUG] clck_gen.py:113 IND CLOCK 4590
2026-01-29 02:59:13.712 [DEBUG] clck_gen.py:113 IND CLOCK 4692
2026-01-29 02:59:13.754 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 02:59:13.754 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 02:59:13.755 [WARNING] transceiver.py:257 (MS@172.18.28.22:6700) RX TRXD message (fn=4703 tn=2 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:59:13.758 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 02:59:13.759 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:59:13.759 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:59:13.759 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:59:13.762 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 02:59:13.762 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:59:13.762 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.28.20:5700) Recv POWEROFF cmd
2026-01-29 02:59:13.762 [INFO] ctrl_if_trx.py:117 (BTS@172.18.28.20:5700) Stopping transceiver...
2026-01-29 02:59:13.762 [INFO] transceiver.py:246 Stopping clock generator
2026-01-29 02:59:13.762 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:59:13.762 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:59:13.762 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=4704 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:59:13.762 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=4704 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:59:13.762 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=4704 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:59:13.762 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=4704 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:59:13.762 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=4704 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:59:13.762 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=4704 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:59:13.762 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=4704 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:59:18.762 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.28.20:5700) Recv POWEROFF cmd
2026-01-29 02:59:18.762 [INFO] ctrl_if_trx.py:117 (BTS@172.18.28.20:5700) Stopping transceiver...
2026-01-29 02:59:18.766 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:59:18.766 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:59:18.766 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 02:59:18.766 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:59:18.775 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 02:59:18.777 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.28.20:5700) Recv SETFORMAT cmd
2026-01-29 02:59:18.777 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.28.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:59:18.778 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.28.20:5700) Recv SETFORMAT cmd
2026-01-29 02:59:18.778 [INFO] ctrl_if_trx.py:201 (BTS@172.18.28.20:5700) TRXD header version 1 -> 1
2026-01-29 02:59:18.783 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.28.20:5700/1) Recv RXTUNE cmd
2026-01-29 02:59:18.783 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.28.20:5700/1) Recv TXTUNE cmd
2026-01-29 02:59:18.784 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.28.20:5700/1) Recv SETFORMAT cmd
2026-01-29 02:59:18.784 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.28.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:59:18.785 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:59:18.785 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.28.20:5700/1) Recv NOMTXPOWER cmd
2026-01-29 02:59:18.786 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.28.20:5700/1) Recv SETFORMAT cmd
2026-01-29 02:59:18.786 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.28.20:5700/1) TRXD header version 1 -> 1
2026-01-29 02:59:18.787 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.28.20:5700/2) Recv RXTUNE cmd
2026-01-29 02:59:18.787 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.28.20:5700/2) Recv TXTUNE cmd
2026-01-29 02:59:18.788 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.28.20:5700/2) Recv SETFORMAT cmd
2026-01-29 02:59:18.788 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.28.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:59:18.788 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:59:18.788 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.28.20:5700/2) Recv NOMTXPOWER cmd
2026-01-29 02:59:18.789 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.28.20:5700/2) Recv SETFORMAT cmd
2026-01-29 02:59:18.789 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.28.20:5700/2) TRXD header version 1 -> 1
2026-01-29 02:59:18.790 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.28.20:5700/3) Recv RXTUNE cmd
2026-01-29 02:59:18.790 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.28.20:5700/3) Recv TXTUNE cmd
2026-01-29 02:59:18.790 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.28.20:5700/3) Recv SETFORMAT cmd
2026-01-29 02:59:18.790 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.28.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:59:18.790 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:59:18.790 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.28.20:5700/3) Recv NOMTXPOWER cmd
2026-01-29 02:59:18.790 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.28.20:5700/3) Recv SETFORMAT cmd
2026-01-29 02:59:18.791 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.28.20:5700/3) TRXD header version 1 -> 1
2026-01-29 02:59:18.794 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.28.20:5700) Recv RXTUNE cmd
2026-01-29 02:59:18.794 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETTSC
2026-01-29 02:59:18.794 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETTSC
2026-01-29 02:59:18.794 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETTSC
2026-01-29 02:59:18.794 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.28.20:5700) Recv TXTUNE cmd
2026-01-29 02:59:18.794 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETRXGAIN
2026-01-29 02:59:18.794 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETRXGAIN
2026-01-29 02:59:18.794 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETRXGAIN
2026-01-29 02:59:18.794 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETTSC
2026-01-29 02:59:18.794 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:59:18.794 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:59:18.794 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.28.20:5700) Recv NOMTXPOWER cmd
2026-01-29 02:59:18.794 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:59:18.794 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:59:18.794 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:59:18.794 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.28.20:5700) Recv POWERON CMD
2026-01-29 02:59:18.794 [INFO] ctrl_if_trx.py:109 (BTS@172.18.28.20:5700) Starting transceiver...
2026-01-29 02:59:18.794 [INFO] transceiver.py:243 Starting clock generator
2026-01-29 02:59:18.795 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-01-29 02:59:18.795 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:59:18.795 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:59:18.795 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:59:18.795 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETRXGAIN
2026-01-29 02:59:18.795 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:59:18.795 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:59:18.795 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:59:18.795 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:59:18.795 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:59:18.795 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:59:18.795 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:59:18.795 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:59:18.795 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:59:18.795 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:59:18.796 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:59:18.796 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:59:18.796 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:59:18.796 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:59:18.796 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:59:18.796 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:59:18.796 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:59:18.796 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:59:18.796 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:59:18.796 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:59:18.796 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:59:18.796 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:59:18.796 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:59:18.796 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:59:18.800 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-01-29 02:59:19.283 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-01-29 02:59:19.327 [DEBUG] fake_trx.py:278 (BTS@172.18.28.20:5700) Recv FAKE_TOA cmd
2026-01-29 02:59:19.329 [DEBUG] fake_trx.py:297 (BTS@172.18.28.20:5700) Recv FAKE_RSSI cmd
2026-01-29 02:59:19.330 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:59:19.332 [DEBUG] fake_trx.py:322 (BTS@172.18.28.20:5700) Recv FAKE_CI cmd
2026-01-29 02:59:19.335 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 02:59:19.335 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 02:59:19.336 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 02:59:19.336 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:59:19.337 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 02:59:19.337 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 02:59:19.338 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.28.22:6700) Recv POWERON CMD
2026-01-29 02:59:19.338 [INFO] ctrl_if_trx.py:109 (MS@172.18.28.22:6700) Starting transceiver...
2026-01-29 02:59:19.760 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-01-29 02:59:19.797 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 02:59:19.798 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:59:19.798 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:59:19.799 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:59:20.237 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-01-29 02:59:20.715 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-01-29 02:59:20.798 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 02:59:20.799 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:59:20.799 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:59:20.800 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:59:21.193 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-01-29 02:59:21.671 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-01-29 02:59:21.799 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 02:59:21.799 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:59:21.800 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:59:21.800 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:59:22.149 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-01-29 02:59:22.626 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-01-29 02:59:22.800 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 02:59:22.800 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:59:22.800 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:59:22.802 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:59:23.104 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-01-29 02:59:23.582 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-01-29 02:59:23.801 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:59:23.802 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:59:23.802 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 02:59:23.803 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:59:24.060 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-01-29 02:59:24.538 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-01-29 02:59:25.016 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-01-29 02:59:25.493 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-01-29 02:59:25.971 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-01-29 02:59:26.448 [DEBUG] clck_gen.py:113 IND CLOCK 1632
2026-01-29 02:59:26.931 [DEBUG] clck_gen.py:113 IND CLOCK 1734
2026-01-29 02:59:27.410 [DEBUG] clck_gen.py:113 IND CLOCK 1836
2026-01-29 02:59:27.887 [DEBUG] clck_gen.py:113 IND CLOCK 1938
2026-01-29 02:59:28.365 [DEBUG] clck_gen.py:113 IND CLOCK 2040
2026-01-29 02:59:28.843 [DEBUG] clck_gen.py:113 IND CLOCK 2142
2026-01-29 02:59:29.321 [DEBUG] clck_gen.py:113 IND CLOCK 2244
2026-01-29 02:59:29.799 [DEBUG] clck_gen.py:113 IND CLOCK 2346
2026-01-29 02:59:30.277 [DEBUG] clck_gen.py:113 IND CLOCK 2448
2026-01-29 02:59:30.754 [DEBUG] clck_gen.py:113 IND CLOCK 2550
2026-01-29 02:59:31.232 [DEBUG] clck_gen.py:113 IND CLOCK 2652
2026-01-29 02:59:31.710 [DEBUG] clck_gen.py:113 IND CLOCK 2754
2026-01-29 02:59:32.188 [DEBUG] clck_gen.py:113 IND CLOCK 2856
2026-01-29 02:59:32.665 [DEBUG] clck_gen.py:113 IND CLOCK 2958
2026-01-29 02:59:33.143 [DEBUG] clck_gen.py:113 IND CLOCK 3060
2026-01-29 02:59:33.621 [DEBUG] clck_gen.py:113 IND CLOCK 3162
2026-01-29 02:59:34.098 [DEBUG] clck_gen.py:113 IND CLOCK 3264
2026-01-29 02:59:34.576 [DEBUG] clck_gen.py:113 IND CLOCK 3366
2026-01-29 02:59:35.054 [DEBUG] clck_gen.py:113 IND CLOCK 3468
2026-01-29 02:59:35.532 [DEBUG] clck_gen.py:113 IND CLOCK 3570
2026-01-29 02:59:36.009 [DEBUG] clck_gen.py:113 IND CLOCK 3672
2026-01-29 02:59:36.487 [DEBUG] clck_gen.py:113 IND CLOCK 3774
2026-01-29 02:59:36.965 [DEBUG] clck_gen.py:113 IND CLOCK 3876
2026-01-29 02:59:37.443 [DEBUG] clck_gen.py:113 IND CLOCK 3978
2026-01-29 02:59:37.921 [DEBUG] clck_gen.py:113 IND CLOCK 4080
2026-01-29 02:59:38.398 [DEBUG] clck_gen.py:113 IND CLOCK 4182
2026-01-29 02:59:38.875 [DEBUG] clck_gen.py:113 IND CLOCK 4284
2026-01-29 02:59:39.353 [DEBUG] clck_gen.py:113 IND CLOCK 4386
2026-01-29 02:59:39.830 [DEBUG] clck_gen.py:113 IND CLOCK 4488
2026-01-29 02:59:40.308 [DEBUG] clck_gen.py:113 IND CLOCK 4590
2026-01-29 02:59:40.786 [DEBUG] clck_gen.py:113 IND CLOCK 4692
2026-01-29 02:59:41.265 [DEBUG] clck_gen.py:113 IND CLOCK 4794
2026-01-29 02:59:41.742 [DEBUG] clck_gen.py:113 IND CLOCK 4896
2026-01-29 02:59:42.220 [DEBUG] clck_gen.py:113 IND CLOCK 4998
2026-01-29 02:59:42.698 [DEBUG] clck_gen.py:113 IND CLOCK 5100
2026-01-29 02:59:43.176 [DEBUG] clck_gen.py:113 IND CLOCK 5202
2026-01-29 02:59:43.653 [DEBUG] clck_gen.py:113 IND CLOCK 5304
2026-01-29 02:59:44.131 [DEBUG] clck_gen.py:113 IND CLOCK 5406
2026-01-29 02:59:44.610 [DEBUG] clck_gen.py:113 IND CLOCK 5508
2026-01-29 02:59:45.088 [DEBUG] clck_gen.py:113 IND CLOCK 5610
2026-01-29 02:59:45.565 [DEBUG] clck_gen.py:113 IND CLOCK 5712
2026-01-29 02:59:46.043 [DEBUG] clck_gen.py:113 IND CLOCK 5814
2026-01-29 02:59:46.521 [DEBUG] clck_gen.py:113 IND CLOCK 5916
2026-01-29 02:59:46.999 [DEBUG] clck_gen.py:113 IND CLOCK 6018
2026-01-29 02:59:47.477 [DEBUG] clck_gen.py:113 IND CLOCK 6120
2026-01-29 02:59:47.955 [DEBUG] clck_gen.py:113 IND CLOCK 6222
2026-01-29 02:59:48.433 [DEBUG] clck_gen.py:113 IND CLOCK 6324
2026-01-29 02:59:48.910 [DEBUG] clck_gen.py:113 IND CLOCK 6426
2026-01-29 02:59:49.388 [DEBUG] clck_gen.py:113 IND CLOCK 6528
2026-01-29 02:59:49.866 [DEBUG] clck_gen.py:113 IND CLOCK 6630
2026-01-29 02:59:50.344 [DEBUG] clck_gen.py:113 IND CLOCK 6732
2026-01-29 02:59:50.822 [DEBUG] clck_gen.py:113 IND CLOCK 6834
2026-01-29 02:59:51.301 [DEBUG] clck_gen.py:113 IND CLOCK 6936
2026-01-29 02:59:51.779 [DEBUG] clck_gen.py:113 IND CLOCK 7038
2026-01-29 02:59:52.257 [DEBUG] clck_gen.py:113 IND CLOCK 7140
2026-01-29 02:59:52.735 [DEBUG] clck_gen.py:113 IND CLOCK 7242
2026-01-29 02:59:52.818 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 02:59:52.818 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 02:59:52.821 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 02:59:52.821 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:59:52.821 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:59:52.821 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:59:52.822 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 02:59:52.822 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:59:52.822 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:59:52.822 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.28.20:5700) Recv POWEROFF cmd
2026-01-29 02:59:52.822 [INFO] ctrl_if_trx.py:117 (BTS@172.18.28.20:5700) Stopping transceiver...
2026-01-29 02:59:52.822 [INFO] transceiver.py:246 Stopping clock generator
2026-01-29 02:59:52.822 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:59:52.822 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=7262 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:59:52.822 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=7262 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:59:52.822 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=7262 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:59:52.822 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=7262 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:59:57.825 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.28.20:5700) Recv POWEROFF cmd
2026-01-29 02:59:57.825 [INFO] ctrl_if_trx.py:117 (BTS@172.18.28.20:5700) Stopping transceiver...
2026-01-29 02:59:57.829 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:59:57.829 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:59:57.829 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 02:59:57.829 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:59:57.839 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 02:59:57.841 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.28.20:5700) Recv SETFORMAT cmd
2026-01-29 02:59:57.841 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.28.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:59:57.842 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.28.20:5700) Recv SETFORMAT cmd
2026-01-29 02:59:57.842 [INFO] ctrl_if_trx.py:201 (BTS@172.18.28.20:5700) TRXD header version 1 -> 1
2026-01-29 02:59:57.846 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.28.20:5700/1) Recv RXTUNE cmd
2026-01-29 02:59:57.846 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.28.20:5700/1) Recv TXTUNE cmd
2026-01-29 02:59:57.847 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.28.20:5700/1) Recv SETFORMAT cmd
2026-01-29 02:59:57.847 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.28.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:59:57.847 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:59:57.848 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.28.20:5700/1) Recv NOMTXPOWER cmd
2026-01-29 02:59:57.848 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.28.20:5700/1) Recv SETFORMAT cmd
2026-01-29 02:59:57.848 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.28.20:5700/1) TRXD header version 1 -> 1
2026-01-29 02:59:57.850 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.28.20:5700/2) Recv RXTUNE cmd
2026-01-29 02:59:57.850 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.28.20:5700/2) Recv TXTUNE cmd
2026-01-29 02:59:57.850 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.28.20:5700/2) Recv SETFORMAT cmd
2026-01-29 02:59:57.851 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.28.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:59:57.851 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:59:57.851 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.28.20:5700/2) Recv NOMTXPOWER cmd
2026-01-29 02:59:57.851 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.28.20:5700/2) Recv SETFORMAT cmd
2026-01-29 02:59:57.851 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.28.20:5700/2) TRXD header version 1 -> 1
2026-01-29 02:59:57.853 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.28.20:5700/3) Recv RXTUNE cmd
2026-01-29 02:59:57.853 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.28.20:5700/3) Recv TXTUNE cmd
2026-01-29 02:59:57.853 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.28.20:5700/3) Recv SETFORMAT cmd
2026-01-29 02:59:57.853 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.28.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:59:57.853 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:59:57.853 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.28.20:5700/3) Recv NOMTXPOWER cmd
2026-01-29 02:59:57.853 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.28.20:5700/3) Recv SETFORMAT cmd
2026-01-29 02:59:57.853 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.28.20:5700/3) TRXD header version 1 -> 1
2026-01-29 02:59:57.856 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.28.20:5700) Recv RXTUNE cmd
2026-01-29 02:59:57.856 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETTSC
2026-01-29 02:59:57.856 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETTSC
2026-01-29 02:59:57.856 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETTSC
2026-01-29 02:59:57.856 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.28.20:5700) Recv TXTUNE cmd
2026-01-29 02:59:57.856 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETRXGAIN
2026-01-29 02:59:57.856 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETRXGAIN
2026-01-29 02:59:57.856 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETRXGAIN
2026-01-29 02:59:57.856 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETTSC
2026-01-29 02:59:57.856 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:59:57.856 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:59:57.856 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.28.20:5700) Recv NOMTXPOWER cmd
2026-01-29 02:59:57.857 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:59:57.857 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:59:57.857 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:59:57.857 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.28.20:5700) Recv POWERON CMD
2026-01-29 02:59:57.857 [INFO] ctrl_if_trx.py:109 (BTS@172.18.28.20:5700) Starting transceiver...
2026-01-29 02:59:57.857 [INFO] transceiver.py:243 Starting clock generator
2026-01-29 02:59:57.857 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-01-29 02:59:57.857 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:59:57.857 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:59:57.857 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:59:57.857 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETRXGAIN
2026-01-29 02:59:57.857 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:59:57.857 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:59:57.857 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:59:57.857 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:59:57.857 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:59:57.857 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:59:57.857 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:59:57.857 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:59:57.857 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:59:57.858 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:59:57.858 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:59:57.858 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:59:57.858 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:59:57.858 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:59:57.858 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:59:57.858 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:59:57.858 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:59:57.858 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:59:57.858 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:59:57.858 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:59:57.858 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:59:57.858 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:59:57.858 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:59:57.858 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 02:59:57.862 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-01-29 02:59:58.344 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-01-29 02:59:58.390 [DEBUG] fake_trx.py:278 (BTS@172.18.28.20:5700) Recv FAKE_TOA cmd
2026-01-29 02:59:58.393 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:59:58.393 [DEBUG] fake_trx.py:297 (BTS@172.18.28.20:5700) Recv FAKE_RSSI cmd
2026-01-29 02:59:58.397 [DEBUG] fake_trx.py:322 (BTS@172.18.28.20:5700) Recv FAKE_CI cmd
2026-01-29 02:59:58.401 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 02:59:58.401 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 02:59:58.402 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 02:59:58.402 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 02:59:58.403 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 02:59:58.403 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 02:59:58.404 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.28.22:6700) Recv POWERON CMD
2026-01-29 02:59:58.404 [INFO] ctrl_if_trx.py:109 (MS@172.18.28.22:6700) Starting transceiver...
2026-01-29 02:59:58.821 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-01-29 02:59:58.859 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 02:59:58.860 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:59:58.861 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:59:58.864 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:59:59.299 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-01-29 02:59:59.777 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-01-29 02:59:59.860 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 02:59:59.861 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:59:59.862 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:59:59.865 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:00:00.255 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-01-29 03:00:00.732 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-01-29 03:00:00.862 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 03:00:00.862 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:00:00.862 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:00:00.866 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:00:01.209 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-01-29 03:00:01.687 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-01-29 03:00:01.863 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:00:01.863 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 03:00:01.863 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:00:01.867 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:00:02.165 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-01-29 03:00:02.643 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-01-29 03:00:02.864 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 03:00:02.864 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:00:02.865 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:00:02.868 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:00:03.120 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-01-29 03:00:03.598 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-01-29 03:00:04.076 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-01-29 03:00:04.553 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-01-29 03:00:05.031 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-01-29 03:00:05.509 [DEBUG] clck_gen.py:113 IND CLOCK 1632
2026-01-29 03:00:05.987 [DEBUG] clck_gen.py:113 IND CLOCK 1734
2026-01-29 03:00:06.464 [DEBUG] clck_gen.py:113 IND CLOCK 1836
2026-01-29 03:00:06.942 [DEBUG] clck_gen.py:113 IND CLOCK 1938
2026-01-29 03:00:07.420 [DEBUG] clck_gen.py:113 IND CLOCK 2040
2026-01-29 03:00:07.898 [DEBUG] clck_gen.py:113 IND CLOCK 2142
2026-01-29 03:00:08.375 [DEBUG] clck_gen.py:113 IND CLOCK 2244
2026-01-29 03:00:08.852 [DEBUG] clck_gen.py:113 IND CLOCK 2346
2026-01-29 03:00:09.330 [DEBUG] clck_gen.py:113 IND CLOCK 2448
2026-01-29 03:00:09.808 [DEBUG] clck_gen.py:113 IND CLOCK 2550
2026-01-29 03:00:10.286 [DEBUG] clck_gen.py:113 IND CLOCK 2652
2026-01-29 03:00:10.763 [DEBUG] clck_gen.py:113 IND CLOCK 2754
2026-01-29 03:00:11.242 [DEBUG] clck_gen.py:113 IND CLOCK 2856
2026-01-29 03:00:11.719 [DEBUG] clck_gen.py:113 IND CLOCK 2958
2026-01-29 03:00:12.197 [DEBUG] clck_gen.py:113 IND CLOCK 3060
2026-01-29 03:00:12.675 [DEBUG] clck_gen.py:113 IND CLOCK 3162
2026-01-29 03:00:13.153 [DEBUG] clck_gen.py:113 IND CLOCK 3264
2026-01-29 03:00:13.628 [DEBUG] clck_gen.py:113 IND CLOCK 3366
2026-01-29 03:00:14.101 [DEBUG] clck_gen.py:113 IND CLOCK 3468
2026-01-29 03:00:14.575 [DEBUG] clck_gen.py:113 IND CLOCK 3570
2026-01-29 03:00:15.053 [DEBUG] clck_gen.py:113 IND CLOCK 3672
2026-01-29 03:00:15.529 [DEBUG] clck_gen.py:113 IND CLOCK 3774
2026-01-29 03:00:16.005 [DEBUG] clck_gen.py:113 IND CLOCK 3876
2026-01-29 03:00:16.483 [DEBUG] clck_gen.py:113 IND CLOCK 3978
2026-01-29 03:00:16.954 [DEBUG] clck_gen.py:113 IND CLOCK 4080
2026-01-29 03:00:17.429 [DEBUG] clck_gen.py:113 IND CLOCK 4182
2026-01-29 03:00:17.905 [DEBUG] clck_gen.py:113 IND CLOCK 4284
2026-01-29 03:00:18.381 [DEBUG] clck_gen.py:113 IND CLOCK 4386
2026-01-29 03:00:18.859 [DEBUG] clck_gen.py:113 IND CLOCK 4488
2026-01-29 03:00:19.337 [DEBUG] clck_gen.py:113 IND CLOCK 4590
2026-01-29 03:00:19.815 [DEBUG] clck_gen.py:113 IND CLOCK 4692
2026-01-29 03:00:20.293 [DEBUG] clck_gen.py:113 IND CLOCK 4794
2026-01-29 03:00:20.771 [DEBUG] clck_gen.py:113 IND CLOCK 4896
2026-01-29 03:00:21.249 [DEBUG] clck_gen.py:113 IND CLOCK 4998
2026-01-29 03:00:21.727 [DEBUG] clck_gen.py:113 IND CLOCK 5100
2026-01-29 03:00:22.206 [DEBUG] clck_gen.py:113 IND CLOCK 5202
2026-01-29 03:00:22.683 [DEBUG] clck_gen.py:113 IND CLOCK 5304
2026-01-29 03:00:23.161 [DEBUG] clck_gen.py:113 IND CLOCK 5406
2026-01-29 03:00:23.638 [DEBUG] clck_gen.py:113 IND CLOCK 5508
2026-01-29 03:00:24.116 [DEBUG] clck_gen.py:113 IND CLOCK 5610
2026-01-29 03:00:24.594 [DEBUG] clck_gen.py:113 IND CLOCK 5712
2026-01-29 03:00:25.073 [DEBUG] clck_gen.py:113 IND CLOCK 5814
2026-01-29 03:00:25.551 [DEBUG] clck_gen.py:113 IND CLOCK 5916
2026-01-29 03:00:25.878 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 03:00:25.878 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 03:00:25.883 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 03:00:25.883 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:00:25.883 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:00:25.883 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:00:25.887 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 03:00:25.887 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 03:00:25.887 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 03:00:25.887 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 03:00:25.887 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.28.20:5700) Recv POWEROFF cmd
2026-01-29 03:00:25.887 [INFO] ctrl_if_trx.py:117 (BTS@172.18.28.20:5700) Stopping transceiver...
2026-01-29 03:00:25.888 [INFO] transceiver.py:246 Stopping clock generator
2026-01-29 03:00:25.888 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=5990 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:00:25.888 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=5990 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:00:25.888 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=5990 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:00:25.888 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=5990 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:00:25.889 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=5990 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:00:25.889 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=5990 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:00:25.889 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=5991 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:00:25.889 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=5991 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:00:25.889 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=5991 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:00:25.889 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=5991 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:00:25.889 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=5991 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:00:25.889 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=5991 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:00:25.889 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=5991 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:00:25.889 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=5991 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:00:30.886 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.28.20:5700) Recv POWEROFF cmd
2026-01-29 03:00:30.886 [INFO] ctrl_if_trx.py:117 (BTS@172.18.28.20:5700) Stopping transceiver...
2026-01-29 03:00:30.890 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 03:00:30.890 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 03:00:30.890 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 03:00:30.890 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 03:00:30.899 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 03:00:30.901 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.28.20:5700) Recv SETFORMAT cmd
2026-01-29 03:00:30.901 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.28.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:00:30.901 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.28.20:5700) Recv SETFORMAT cmd
2026-01-29 03:00:30.902 [INFO] ctrl_if_trx.py:201 (BTS@172.18.28.20:5700) TRXD header version 1 -> 1
2026-01-29 03:00:30.906 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.28.20:5700/1) Recv RXTUNE cmd
2026-01-29 03:00:30.906 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.28.20:5700/1) Recv TXTUNE cmd
2026-01-29 03:00:30.906 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.28.20:5700/1) Recv SETFORMAT cmd
2026-01-29 03:00:30.906 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.28.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:00:30.906 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 03:00:30.907 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.28.20:5700/1) Recv NOMTXPOWER cmd
2026-01-29 03:00:30.907 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.28.20:5700/1) Recv SETFORMAT cmd
2026-01-29 03:00:30.907 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.28.20:5700/1) TRXD header version 1 -> 1
2026-01-29 03:00:30.910 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.28.20:5700/2) Recv RXTUNE cmd
2026-01-29 03:00:30.910 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.28.20:5700/2) Recv TXTUNE cmd
2026-01-29 03:00:30.910 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.28.20:5700/2) Recv SETFORMAT cmd
2026-01-29 03:00:30.910 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.28.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:00:30.910 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 03:00:30.910 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.28.20:5700/2) Recv NOMTXPOWER cmd
2026-01-29 03:00:30.910 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.28.20:5700/2) Recv SETFORMAT cmd
2026-01-29 03:00:30.910 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.28.20:5700/2) TRXD header version 1 -> 1
2026-01-29 03:00:30.913 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.28.20:5700/3) Recv RXTUNE cmd
2026-01-29 03:00:30.913 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.28.20:5700/3) Recv TXTUNE cmd
2026-01-29 03:00:30.913 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.28.20:5700/3) Recv SETFORMAT cmd
2026-01-29 03:00:30.913 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.28.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:00:30.913 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 03:00:30.913 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.28.20:5700/3) Recv NOMTXPOWER cmd
2026-01-29 03:00:30.914 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.28.20:5700/3) Recv SETFORMAT cmd
2026-01-29 03:00:30.914 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.28.20:5700/3) TRXD header version 1 -> 1
2026-01-29 03:00:30.917 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.28.20:5700) Recv RXTUNE cmd
2026-01-29 03:00:30.917 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETTSC
2026-01-29 03:00:30.917 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETTSC
2026-01-29 03:00:30.917 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETTSC
2026-01-29 03:00:30.917 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.28.20:5700) Recv TXTUNE cmd
2026-01-29 03:00:30.917 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETRXGAIN
2026-01-29 03:00:30.917 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETRXGAIN
2026-01-29 03:00:30.917 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETRXGAIN
2026-01-29 03:00:30.917 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETTSC
2026-01-29 03:00:30.917 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:00:30.917 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:00:30.917 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:00:30.917 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.28.20:5700) Recv NOMTXPOWER cmd
2026-01-29 03:00:30.917 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:00:30.917 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:00:30.917 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:00:30.917 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.28.20:5700) Recv POWERON CMD
2026-01-29 03:00:30.917 [INFO] ctrl_if_trx.py:109 (BTS@172.18.28.20:5700) Starting transceiver...
2026-01-29 03:00:30.917 [INFO] transceiver.py:243 Starting clock generator
2026-01-29 03:00:30.918 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-01-29 03:00:30.918 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:00:30.918 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:00:30.918 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:00:30.918 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETRXGAIN
2026-01-29 03:00:30.918 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:00:30.918 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:00:30.918 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:00:30.918 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:00:30.918 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:00:30.918 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:00:30.918 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:00:30.918 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:00:30.918 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:00:30.918 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:00:30.918 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:00:30.919 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:00:30.919 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:00:30.919 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:00:30.919 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:00:30.919 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:00:30.919 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:00:30.919 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:00:30.919 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:00:30.919 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:00:30.919 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:00:30.919 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:00:30.919 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:00:30.922 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-01-29 03:00:31.404 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-01-29 03:00:31.448 [DEBUG] fake_trx.py:278 (BTS@172.18.28.20:5700) Recv FAKE_TOA cmd
2026-01-29 03:00:31.449 [DEBUG] fake_trx.py:297 (BTS@172.18.28.20:5700) Recv FAKE_RSSI cmd
2026-01-29 03:00:31.451 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:00:31.451 [DEBUG] fake_trx.py:322 (BTS@172.18.28.20:5700) Recv FAKE_CI cmd
2026-01-29 03:00:31.461 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 03:00:31.461 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:00:31.461 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:00:31.461 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:00:31.463 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 03:00:31.463 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 03:00:31.463 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 03:00:31.463 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.28.20:5700) Recv POWEROFF cmd
2026-01-29 03:00:31.463 [INFO] ctrl_if_trx.py:117 (BTS@172.18.28.20:5700) Stopping transceiver...
2026-01-29 03:00:31.463 [INFO] transceiver.py:246 Stopping clock generator
2026-01-29 03:00:31.463 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 03:00:31.463 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=116 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:00:31.463 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=116 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:00:31.463 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=116 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:00:31.463 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=116 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:00:31.463 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=116 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:00:31.463 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=116 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:00:31.463 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=116 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:00:36.465 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.28.20:5700) Recv POWEROFF cmd
2026-01-29 03:00:36.465 [INFO] ctrl_if_trx.py:117 (BTS@172.18.28.20:5700) Stopping transceiver...
2026-01-29 03:00:36.467 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 03:00:36.468 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 03:00:36.469 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 03:00:36.469 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 03:00:36.472 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 03:00:36.472 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.28.20:5700) Recv SETFORMAT cmd
2026-01-29 03:00:36.472 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.28.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:00:36.473 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.28.20:5700) Recv SETFORMAT cmd
2026-01-29 03:00:36.473 [INFO] ctrl_if_trx.py:201 (BTS@172.18.28.20:5700) TRXD header version 1 -> 1
2026-01-29 03:00:36.473 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.28.20:5700/1) Recv RXTUNE cmd
2026-01-29 03:00:36.473 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.28.20:5700/1) Recv TXTUNE cmd
2026-01-29 03:00:36.474 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.28.20:5700/1) Recv SETFORMAT cmd
2026-01-29 03:00:36.474 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.28.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:00:36.474 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 03:00:36.474 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.28.20:5700/1) Recv NOMTXPOWER cmd
2026-01-29 03:00:36.474 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.28.20:5700/1) Recv SETFORMAT cmd
2026-01-29 03:00:36.474 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.28.20:5700/1) TRXD header version 1 -> 1
2026-01-29 03:00:36.474 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.28.20:5700/2) Recv RXTUNE cmd
2026-01-29 03:00:36.474 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.28.20:5700/2) Recv TXTUNE cmd
2026-01-29 03:00:36.475 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.28.20:5700/2) Recv SETFORMAT cmd
2026-01-29 03:00:36.475 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.28.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:00:36.475 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 03:00:36.475 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.28.20:5700/2) Recv NOMTXPOWER cmd
2026-01-29 03:00:36.475 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.28.20:5700/2) Recv SETFORMAT cmd
2026-01-29 03:00:36.475 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.28.20:5700/2) TRXD header version 1 -> 1
2026-01-29 03:00:36.476 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.28.20:5700/3) Recv RXTUNE cmd
2026-01-29 03:00:36.476 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.28.20:5700/3) Recv TXTUNE cmd
2026-01-29 03:00:36.476 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.28.20:5700/3) Recv SETFORMAT cmd
2026-01-29 03:00:36.476 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.28.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:00:36.476 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.28.20:5700/3) Recv NOMTXPOWER cmd
2026-01-29 03:00:36.476 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 03:00:36.476 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.28.20:5700/3) Recv SETFORMAT cmd
2026-01-29 03:00:36.476 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.28.20:5700/3) TRXD header version 1 -> 1
2026-01-29 03:00:36.477 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.28.20:5700) Recv RXTUNE cmd
2026-01-29 03:00:36.477 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETTSC
2026-01-29 03:00:36.477 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETTSC
2026-01-29 03:00:36.477 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETTSC
2026-01-29 03:00:36.477 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.28.20:5700) Recv TXTUNE cmd
2026-01-29 03:00:36.477 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETRXGAIN
2026-01-29 03:00:36.477 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETRXGAIN
2026-01-29 03:00:36.477 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETRXGAIN
2026-01-29 03:00:36.477 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETTSC
2026-01-29 03:00:36.478 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:00:36.478 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:00:36.478 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.28.20:5700) Recv NOMTXPOWER cmd
2026-01-29 03:00:36.478 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:00:36.478 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:00:36.478 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.28.20:5700) Recv POWERON CMD
2026-01-29 03:00:36.478 [INFO] ctrl_if_trx.py:109 (BTS@172.18.28.20:5700) Starting transceiver...
2026-01-29 03:00:36.478 [INFO] transceiver.py:243 Starting clock generator
2026-01-29 03:00:36.478 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-01-29 03:00:36.478 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:00:36.478 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:00:36.478 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:00:36.478 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETRXGAIN
2026-01-29 03:00:36.478 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:00:36.478 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:00:36.478 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:00:36.478 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:00:36.478 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:00:36.478 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:00:36.478 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:00:36.478 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:00:36.478 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:00:36.478 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:00:36.478 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:00:36.478 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:00:36.478 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:00:36.478 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:00:36.478 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:00:36.478 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:00:36.478 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:00:36.478 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:00:36.478 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:00:36.478 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:00:36.478 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:00:36.478 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:00:36.478 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:00:36.478 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:00:36.478 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:00:36.482 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-01-29 03:00:36.966 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-01-29 03:00:37.003 [DEBUG] fake_trx.py:278 (BTS@172.18.28.20:5700) Recv FAKE_TOA cmd
2026-01-29 03:00:37.005 [DEBUG] fake_trx.py:297 (BTS@172.18.28.20:5700) Recv FAKE_RSSI cmd
2026-01-29 03:00:37.007 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:00:37.007 [DEBUG] fake_trx.py:322 (BTS@172.18.28.20:5700) Recv FAKE_CI cmd
2026-01-29 03:00:37.018 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 03:00:37.018 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:00:37.019 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:00:37.019 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:00:37.022 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 03:00:37.022 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 03:00:37.022 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 03:00:37.023 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 03:00:37.023 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.28.20:5700) Recv POWEROFF cmd
2026-01-29 03:00:37.023 [INFO] ctrl_if_trx.py:117 (BTS@172.18.28.20:5700) Stopping transceiver...
2026-01-29 03:00:37.023 [INFO] transceiver.py:246 Stopping clock generator
2026-01-29 03:00:37.023 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=115 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:00:37.024 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=115 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:00:37.024 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=115 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:00:37.024 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=115 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:00:37.024 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=115 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:00:37.024 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=115 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:00:37.024 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=115 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:00:37.024 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=116 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:00:37.024 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=116 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:00:37.024 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=116 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:00:37.024 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=116 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:00:37.024 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=116 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:00:37.024 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=116 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:00:37.024 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=116 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:00:37.024 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=116 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:00:42.022 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.28.20:5700) Recv POWEROFF cmd
2026-01-29 03:00:42.022 [INFO] ctrl_if_trx.py:117 (BTS@172.18.28.20:5700) Stopping transceiver...
2026-01-29 03:00:42.024 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 03:00:42.025 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 03:00:42.025 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 03:00:42.025 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 03:00:42.031 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 03:00:42.032 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.28.20:5700) Recv SETFORMAT cmd
2026-01-29 03:00:42.033 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.28.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:00:42.033 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.28.20:5700) Recv SETFORMAT cmd
2026-01-29 03:00:42.033 [INFO] ctrl_if_trx.py:201 (BTS@172.18.28.20:5700) TRXD header version 1 -> 1
2026-01-29 03:00:42.036 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.28.20:5700/1) Recv RXTUNE cmd
2026-01-29 03:00:42.037 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.28.20:5700/1) Recv TXTUNE cmd
2026-01-29 03:00:42.037 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.28.20:5700/1) Recv SETFORMAT cmd
2026-01-29 03:00:42.037 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.28.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:00:42.038 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 03:00:42.038 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.28.20:5700/1) Recv NOMTXPOWER cmd
2026-01-29 03:00:42.039 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.28.20:5700/1) Recv SETFORMAT cmd
2026-01-29 03:00:42.039 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.28.20:5700/1) TRXD header version 1 -> 1
2026-01-29 03:00:42.040 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.28.20:5700/2) Recv RXTUNE cmd
2026-01-29 03:00:42.040 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.28.20:5700/2) Recv TXTUNE cmd
2026-01-29 03:00:42.040 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.28.20:5700/2) Recv SETFORMAT cmd
2026-01-29 03:00:42.040 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.28.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:00:42.041 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 03:00:42.041 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.28.20:5700/2) Recv NOMTXPOWER cmd
2026-01-29 03:00:42.041 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.28.20:5700/2) Recv SETFORMAT cmd
2026-01-29 03:00:42.041 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.28.20:5700/2) TRXD header version 1 -> 1
2026-01-29 03:00:42.043 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.28.20:5700/3) Recv RXTUNE cmd
2026-01-29 03:00:42.043 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.28.20:5700/3) Recv TXTUNE cmd
2026-01-29 03:00:42.044 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.28.20:5700/3) Recv SETFORMAT cmd
2026-01-29 03:00:42.044 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.28.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:00:42.044 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 03:00:42.044 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.28.20:5700/3) Recv NOMTXPOWER cmd
2026-01-29 03:00:42.044 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.28.20:5700/3) Recv SETFORMAT cmd
2026-01-29 03:00:42.044 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.28.20:5700/3) TRXD header version 1 -> 1
2026-01-29 03:00:42.047 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.28.20:5700) Recv RXTUNE cmd
2026-01-29 03:00:42.047 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETTSC
2026-01-29 03:00:42.047 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETTSC
2026-01-29 03:00:42.047 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETTSC
2026-01-29 03:00:42.047 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.28.20:5700) Recv TXTUNE cmd
2026-01-29 03:00:42.047 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETRXGAIN
2026-01-29 03:00:42.047 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETRXGAIN
2026-01-29 03:00:42.047 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETRXGAIN
2026-01-29 03:00:42.047 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETTSC
2026-01-29 03:00:42.047 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:00:42.048 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:00:42.048 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:00:42.048 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.28.20:5700) Recv NOMTXPOWER cmd
2026-01-29 03:00:42.048 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:00:42.048 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:00:42.048 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:00:42.048 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.28.20:5700) Recv POWERON CMD
2026-01-29 03:00:42.048 [INFO] ctrl_if_trx.py:109 (BTS@172.18.28.20:5700) Starting transceiver...
2026-01-29 03:00:42.048 [INFO] transceiver.py:243 Starting clock generator
2026-01-29 03:00:42.048 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-01-29 03:00:42.048 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:00:42.048 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:00:42.048 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:00:42.048 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETRXGAIN
2026-01-29 03:00:42.048 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:00:42.048 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:00:42.048 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:00:42.049 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:00:42.049 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:00:42.049 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:00:42.049 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:00:42.049 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:00:42.049 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:00:42.049 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:00:42.049 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:00:42.049 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:00:42.049 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:00:42.049 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:00:42.049 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:00:42.049 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:00:42.049 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:00:42.049 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:00:42.049 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:00:42.049 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:00:42.049 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:00:42.049 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:00:42.049 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:00:42.053 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-01-29 03:00:42.537 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-01-29 03:00:42.576 [DEBUG] fake_trx.py:278 (BTS@172.18.28.20:5700) Recv FAKE_TOA cmd
2026-01-29 03:00:42.578 [DEBUG] fake_trx.py:297 (BTS@172.18.28.20:5700) Recv FAKE_RSSI cmd
2026-01-29 03:00:42.580 [DEBUG] fake_trx.py:322 (BTS@172.18.28.20:5700) Recv FAKE_CI cmd
2026-01-29 03:00:42.580 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:00:42.590 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 03:00:42.590 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:00:42.590 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:00:42.590 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:00:42.593 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 03:00:42.593 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 03:00:42.593 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 03:00:42.593 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 03:00:42.593 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.28.20:5700) Recv POWEROFF cmd
2026-01-29 03:00:42.594 [INFO] ctrl_if_trx.py:117 (BTS@172.18.28.20:5700) Stopping transceiver...
2026-01-29 03:00:42.594 [INFO] transceiver.py:246 Stopping clock generator
2026-01-29 03:00:42.594 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=115 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:00:42.594 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=115 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:00:42.594 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=115 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:00:42.594 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=115 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:00:42.594 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=115 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:00:42.594 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=115 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:00:42.594 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=116 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:00:42.594 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=116 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:00:42.594 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=116 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:00:42.594 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=116 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:00:42.594 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=116 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:00:42.594 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=116 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:00:42.594 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=116 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:00:42.594 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=116 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:00:47.594 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.28.20:5700) Recv POWEROFF cmd
2026-01-29 03:00:47.594 [INFO] ctrl_if_trx.py:117 (BTS@172.18.28.20:5700) Stopping transceiver...
2026-01-29 03:00:47.598 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 03:00:47.598 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 03:00:47.598 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 03:00:47.598 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 03:00:47.605 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 03:00:47.605 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.28.20:5700) Recv SETFORMAT cmd
2026-01-29 03:00:47.605 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.28.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:00:47.605 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.28.20:5700) Recv SETFORMAT cmd
2026-01-29 03:00:47.605 [INFO] ctrl_if_trx.py:201 (BTS@172.18.28.20:5700) TRXD header version 1 -> 1
2026-01-29 03:00:47.608 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.28.20:5700/1) Recv RXTUNE cmd
2026-01-29 03:00:47.608 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.28.20:5700/1) Recv TXTUNE cmd
2026-01-29 03:00:47.609 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.28.20:5700/1) Recv SETFORMAT cmd
2026-01-29 03:00:47.609 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.28.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:00:47.609 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 03:00:47.610 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.28.20:5700/1) Recv NOMTXPOWER cmd
2026-01-29 03:00:47.610 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.28.20:5700/1) Recv SETFORMAT cmd
2026-01-29 03:00:47.610 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.28.20:5700/1) TRXD header version 1 -> 1
2026-01-29 03:00:47.611 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.28.20:5700/2) Recv RXTUNE cmd
2026-01-29 03:00:47.611 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.28.20:5700/2) Recv TXTUNE cmd
2026-01-29 03:00:47.612 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.28.20:5700/2) Recv SETFORMAT cmd
2026-01-29 03:00:47.612 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.28.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:00:47.612 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 03:00:47.612 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.28.20:5700/2) Recv NOMTXPOWER cmd
2026-01-29 03:00:47.612 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.28.20:5700/2) Recv SETFORMAT cmd
2026-01-29 03:00:47.612 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.28.20:5700/2) TRXD header version 1 -> 1
2026-01-29 03:00:47.614 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.28.20:5700/3) Recv RXTUNE cmd
2026-01-29 03:00:47.614 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.28.20:5700/3) Recv TXTUNE cmd
2026-01-29 03:00:47.614 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.28.20:5700/3) Recv SETFORMAT cmd
2026-01-29 03:00:47.614 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.28.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:00:47.615 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 03:00:47.615 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.28.20:5700/3) Recv NOMTXPOWER cmd
2026-01-29 03:00:47.615 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.28.20:5700/3) Recv SETFORMAT cmd
2026-01-29 03:00:47.615 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.28.20:5700/3) TRXD header version 1 -> 1
2026-01-29 03:00:47.617 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.28.20:5700) Recv RXTUNE cmd
2026-01-29 03:00:47.617 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETTSC
2026-01-29 03:00:47.618 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETTSC
2026-01-29 03:00:47.618 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETTSC
2026-01-29 03:00:47.618 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.28.20:5700) Recv TXTUNE cmd
2026-01-29 03:00:47.618 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETRXGAIN
2026-01-29 03:00:47.618 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETRXGAIN
2026-01-29 03:00:47.618 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETRXGAIN
2026-01-29 03:00:47.618 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETTSC
2026-01-29 03:00:47.618 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:00:47.618 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:00:47.618 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.28.20:5700) Recv NOMTXPOWER cmd
2026-01-29 03:00:47.618 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:00:47.618 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:00:47.618 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:00:47.618 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.28.20:5700) Recv POWERON CMD
2026-01-29 03:00:47.618 [INFO] ctrl_if_trx.py:109 (BTS@172.18.28.20:5700) Starting transceiver...
2026-01-29 03:00:47.618 [INFO] transceiver.py:243 Starting clock generator
2026-01-29 03:00:47.618 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-01-29 03:00:47.618 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:00:47.618 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:00:47.618 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:00:47.618 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETRXGAIN
2026-01-29 03:00:47.619 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:00:47.619 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:00:47.619 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:00:47.619 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:00:47.619 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:00:47.619 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:00:47.619 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:00:47.619 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:00:47.619 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:00:47.619 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:00:47.619 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:00:47.619 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:00:47.619 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:00:47.619 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:00:47.619 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:00:47.619 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:00:47.619 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:00:47.619 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:00:47.619 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:00:47.619 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:00:47.619 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:00:47.619 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:00:47.619 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:00:47.619 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:00:47.623 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-01-29 03:00:48.107 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-01-29 03:00:48.143 [DEBUG] fake_trx.py:278 (BTS@172.18.28.20:5700) Recv FAKE_TOA cmd
2026-01-29 03:00:48.145 [DEBUG] fake_trx.py:297 (BTS@172.18.28.20:5700) Recv FAKE_RSSI cmd
2026-01-29 03:00:48.145 [DEBUG] fake_trx.py:322 (BTS@172.18.28.20:5700) Recv FAKE_CI cmd
2026-01-29 03:00:48.146 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:00:48.147 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 03:00:48.147 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 03:00:48.148 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 03:00:48.148 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 03:00:48.148 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 03:00:48.149 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 03:00:48.149 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.28.22:6700) Recv POWERON CMD
2026-01-29 03:00:48.149 [INFO] ctrl_if_trx.py:109 (MS@172.18.28.22:6700) Starting transceiver...
2026-01-29 03:00:48.585 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-01-29 03:00:48.622 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:00:48.623 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 03:00:48.623 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:00:48.626 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:00:49.063 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-01-29 03:00:49.540 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-01-29 03:00:49.623 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 03:00:49.624 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:00:49.624 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:00:49.627 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:00:50.018 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-01-29 03:00:50.495 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-01-29 03:00:50.624 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 03:00:50.647 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:00:50.647 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:00:50.647 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:00:50.972 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-01-29 03:00:51.449 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-01-29 03:00:51.648 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:00:51.648 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:00:51.648 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 03:00:51.649 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:00:51.927 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-01-29 03:00:52.405 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-01-29 03:00:52.649 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 03:00:52.649 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:00:52.649 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:00:52.649 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:00:52.883 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-01-29 03:00:53.360 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-01-29 03:00:53.833 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-01-29 03:00:54.311 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-01-29 03:00:54.788 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-01-29 03:00:55.266 [DEBUG] clck_gen.py:113 IND CLOCK 1632
2026-01-29 03:00:55.744 [DEBUG] clck_gen.py:113 IND CLOCK 1734
2026-01-29 03:00:56.161 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 03:00:56.161 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 03:00:56.165 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 03:00:56.165 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:00:56.165 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:00:56.165 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:00:56.168 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 03:00:56.168 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 03:00:56.168 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 03:00:56.168 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 03:00:56.168 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.28.20:5700) Recv POWEROFF cmd
2026-01-29 03:00:56.168 [INFO] ctrl_if_trx.py:117 (BTS@172.18.28.20:5700) Stopping transceiver...
2026-01-29 03:00:56.168 [INFO] transceiver.py:246 Stopping clock generator
2026-01-29 03:00:56.168 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=1827 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:00:56.168 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=1827 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:00:56.168 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=1827 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:00:56.168 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=1827 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:00:56.168 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=1827 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:00:56.168 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=1827 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:00:56.168 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=1827 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:01:01.169 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.28.20:5700) Recv POWEROFF cmd
2026-01-29 03:01:01.169 [INFO] ctrl_if_trx.py:117 (BTS@172.18.28.20:5700) Stopping transceiver...
2026-01-29 03:01:01.170 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 03:01:01.171 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 03:01:01.171 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 03:01:01.172 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 03:01:01.179 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 03:01:01.180 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.28.20:5700) Recv SETFORMAT cmd
2026-01-29 03:01:01.180 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.28.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:01:01.180 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.28.20:5700) Recv SETFORMAT cmd
2026-01-29 03:01:01.180 [INFO] ctrl_if_trx.py:201 (BTS@172.18.28.20:5700) TRXD header version 1 -> 1
2026-01-29 03:01:01.182 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.28.20:5700/1) Recv RXTUNE cmd
2026-01-29 03:01:01.183 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.28.20:5700/1) Recv TXTUNE cmd
2026-01-29 03:01:01.183 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.28.20:5700/1) Recv SETFORMAT cmd
2026-01-29 03:01:01.183 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.28.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:01:01.184 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 03:01:01.184 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.28.20:5700/1) Recv NOMTXPOWER cmd
2026-01-29 03:01:01.184 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.28.20:5700/1) Recv SETFORMAT cmd
2026-01-29 03:01:01.184 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.28.20:5700/1) TRXD header version 1 -> 1
2026-01-29 03:01:01.186 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.28.20:5700/2) Recv RXTUNE cmd
2026-01-29 03:01:01.186 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.28.20:5700/2) Recv TXTUNE cmd
2026-01-29 03:01:01.186 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.28.20:5700/2) Recv SETFORMAT cmd
2026-01-29 03:01:01.187 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.28.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:01:01.187 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 03:01:01.187 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.28.20:5700/2) Recv NOMTXPOWER cmd
2026-01-29 03:01:01.187 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.28.20:5700/2) Recv SETFORMAT cmd
2026-01-29 03:01:01.187 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.28.20:5700/2) TRXD header version 1 -> 1
2026-01-29 03:01:01.189 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.28.20:5700/3) Recv RXTUNE cmd
2026-01-29 03:01:01.189 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.28.20:5700/3) Recv TXTUNE cmd
2026-01-29 03:01:01.189 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.28.20:5700/3) Recv SETFORMAT cmd
2026-01-29 03:01:01.189 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.28.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:01:01.189 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 03:01:01.189 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.28.20:5700/3) Recv NOMTXPOWER cmd
2026-01-29 03:01:01.189 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.28.20:5700/3) Recv SETFORMAT cmd
2026-01-29 03:01:01.189 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.28.20:5700/3) TRXD header version 1 -> 1
2026-01-29 03:01:01.192 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.28.20:5700) Recv RXTUNE cmd
2026-01-29 03:01:01.192 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETTSC
2026-01-29 03:01:01.192 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETTSC
2026-01-29 03:01:01.192 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETTSC
2026-01-29 03:01:01.193 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.28.20:5700) Recv TXTUNE cmd
2026-01-29 03:01:01.193 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETRXGAIN
2026-01-29 03:01:01.193 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETRXGAIN
2026-01-29 03:01:01.193 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETRXGAIN
2026-01-29 03:01:01.193 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETTSC
2026-01-29 03:01:01.193 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:01:01.193 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:01:01.193 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:01:01.193 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.28.20:5700) Recv NOMTXPOWER cmd
2026-01-29 03:01:01.193 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:01:01.193 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:01:01.193 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:01:01.193 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.28.20:5700) Recv POWERON CMD
2026-01-29 03:01:01.193 [INFO] ctrl_if_trx.py:109 (BTS@172.18.28.20:5700) Starting transceiver...
2026-01-29 03:01:01.193 [INFO] transceiver.py:243 Starting clock generator
2026-01-29 03:01:01.193 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-01-29 03:01:01.194 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:01:01.194 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:01:01.194 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:01:01.194 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETRXGAIN
2026-01-29 03:01:01.194 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:01:01.194 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:01:01.194 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:01:01.194 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:01:01.194 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:01:01.194 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:01:01.194 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:01:01.194 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:01:01.194 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:01:01.194 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:01:01.194 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:01:01.194 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:01:01.194 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:01:01.195 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:01:01.195 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:01:01.195 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:01:01.195 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:01:01.195 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:01:01.195 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:01:01.195 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:01:01.195 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:01:01.195 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:01:01.195 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:01:01.198 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-01-29 03:01:01.681 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-01-29 03:01:01.726 [DEBUG] fake_trx.py:278 (BTS@172.18.28.20:5700) Recv FAKE_TOA cmd
2026-01-29 03:01:01.729 [DEBUG] fake_trx.py:297 (BTS@172.18.28.20:5700) Recv FAKE_RSSI cmd
2026-01-29 03:01:01.730 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:01:01.731 [DEBUG] fake_trx.py:322 (BTS@172.18.28.20:5700) Recv FAKE_CI cmd
2026-01-29 03:01:01.734 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 03:01:01.734 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 03:01:01.735 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 03:01:01.735 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 03:01:01.736 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 03:01:01.736 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 03:01:01.736 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.28.22:6700) Recv POWERON CMD
2026-01-29 03:01:01.736 [INFO] ctrl_if_trx.py:109 (MS@172.18.28.22:6700) Starting transceiver...
2026-01-29 03:01:02.159 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-01-29 03:01:02.196 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 03:01:02.197 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:01:02.197 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:01:02.201 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:01:02.636 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-01-29 03:01:03.114 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-01-29 03:01:03.197 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 03:01:03.198 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:01:03.198 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:01:03.202 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:01:03.592 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-01-29 03:01:04.070 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-01-29 03:01:04.198 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 03:01:04.199 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:01:04.199 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:01:04.203 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:01:04.548 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-01-29 03:01:05.026 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-01-29 03:01:05.199 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:01:05.200 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:01:05.200 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 03:01:05.204 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:01:05.504 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-01-29 03:01:05.983 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-01-29 03:01:06.200 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 03:01:06.201 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:01:06.201 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:01:06.205 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:01:06.460 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-01-29 03:01:06.938 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-01-29 03:01:07.416 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-01-29 03:01:07.893 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-01-29 03:01:08.371 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-01-29 03:01:08.848 [DEBUG] clck_gen.py:113 IND CLOCK 1632
2026-01-29 03:01:09.325 [DEBUG] clck_gen.py:113 IND CLOCK 1734
2026-01-29 03:01:09.777 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 03:01:09.778 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 03:01:09.781 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 03:01:09.781 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:01:09.781 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:01:09.781 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:01:09.783 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 03:01:09.783 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 03:01:09.783 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 03:01:09.783 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 03:01:09.783 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.28.20:5700) Recv POWEROFF cmd
2026-01-29 03:01:09.783 [INFO] ctrl_if_trx.py:117 (BTS@172.18.28.20:5700) Stopping transceiver...
2026-01-29 03:01:09.783 [INFO] transceiver.py:246 Stopping clock generator
2026-01-29 03:01:09.783 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=1835 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:01:09.783 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=1835 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:01:09.783 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=1835 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:01:09.784 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=1835 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:01:09.784 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=1835 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:01:09.784 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=1835 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:01:14.783 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.28.20:5700) Recv POWEROFF cmd
2026-01-29 03:01:14.783 [INFO] ctrl_if_trx.py:117 (BTS@172.18.28.20:5700) Stopping transceiver...
2026-01-29 03:01:14.785 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 03:01:14.786 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 03:01:14.786 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 03:01:14.786 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 03:01:14.794 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 03:01:14.794 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.28.20:5700) Recv SETFORMAT cmd
2026-01-29 03:01:14.795 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.28.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:01:14.795 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.28.20:5700) Recv SETFORMAT cmd
2026-01-29 03:01:14.795 [INFO] ctrl_if_trx.py:201 (BTS@172.18.28.20:5700) TRXD header version 1 -> 1
2026-01-29 03:01:14.797 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.28.20:5700/1) Recv RXTUNE cmd
2026-01-29 03:01:14.798 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.28.20:5700/1) Recv TXTUNE cmd
2026-01-29 03:01:14.798 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.28.20:5700/1) Recv SETFORMAT cmd
2026-01-29 03:01:14.798 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.28.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:01:14.799 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 03:01:14.799 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.28.20:5700/1) Recv NOMTXPOWER cmd
2026-01-29 03:01:14.799 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.28.20:5700/1) Recv SETFORMAT cmd
2026-01-29 03:01:14.799 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.28.20:5700/1) TRXD header version 1 -> 1
2026-01-29 03:01:14.800 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.28.20:5700/2) Recv RXTUNE cmd
2026-01-29 03:01:14.800 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.28.20:5700/2) Recv TXTUNE cmd
2026-01-29 03:01:14.800 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.28.20:5700/2) Recv SETFORMAT cmd
2026-01-29 03:01:14.800 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.28.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:01:14.801 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 03:01:14.801 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.28.20:5700/2) Recv NOMTXPOWER cmd
2026-01-29 03:01:14.801 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.28.20:5700/2) Recv SETFORMAT cmd
2026-01-29 03:01:14.801 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.28.20:5700/2) TRXD header version 1 -> 1
2026-01-29 03:01:14.802 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.28.20:5700/3) Recv RXTUNE cmd
2026-01-29 03:01:14.803 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.28.20:5700/3) Recv TXTUNE cmd
2026-01-29 03:01:14.803 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.28.20:5700/3) Recv SETFORMAT cmd
2026-01-29 03:01:14.803 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.28.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:01:14.803 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 03:01:14.803 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.28.20:5700/3) Recv NOMTXPOWER cmd
2026-01-29 03:01:14.803 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.28.20:5700/3) Recv SETFORMAT cmd
2026-01-29 03:01:14.803 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.28.20:5700/3) TRXD header version 1 -> 1
2026-01-29 03:01:14.805 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.28.20:5700) Recv RXTUNE cmd
2026-01-29 03:01:14.805 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETTSC
2026-01-29 03:01:14.805 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETTSC
2026-01-29 03:01:14.805 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.28.20:5700) Recv TXTUNE cmd
2026-01-29 03:01:14.805 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETTSC
2026-01-29 03:01:14.805 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETRXGAIN
2026-01-29 03:01:14.805 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETRXGAIN
2026-01-29 03:01:14.805 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETTSC
2026-01-29 03:01:14.805 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETRXGAIN
2026-01-29 03:01:14.806 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:01:14.806 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.28.20:5700) Recv NOMTXPOWER cmd
2026-01-29 03:01:14.806 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:01:14.806 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:01:14.806 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.28.20:5700) Recv POWERON CMD
2026-01-29 03:01:14.806 [INFO] ctrl_if_trx.py:109 (BTS@172.18.28.20:5700) Starting transceiver...
2026-01-29 03:01:14.806 [INFO] transceiver.py:243 Starting clock generator
2026-01-29 03:01:14.806 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-01-29 03:01:14.806 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:01:14.806 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:01:14.806 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:01:14.806 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETRXGAIN
2026-01-29 03:01:14.806 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:01:14.806 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:01:14.806 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:01:14.806 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:01:14.806 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:01:14.806 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:01:14.806 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:01:14.806 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:01:14.806 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:01:14.807 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:01:14.807 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:01:14.807 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:01:14.807 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:01:14.807 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:01:14.807 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:01:14.807 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:01:14.807 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:01:14.807 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:01:14.807 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:01:14.807 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:01:14.807 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:01:14.807 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:01:14.807 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:01:14.807 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:01:14.807 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:01:14.807 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:01:14.811 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-01-29 03:01:15.294 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-01-29 03:01:15.332 [DEBUG] fake_trx.py:278 (BTS@172.18.28.20:5700) Recv FAKE_TOA cmd
2026-01-29 03:01:15.334 [DEBUG] fake_trx.py:297 (BTS@172.18.28.20:5700) Recv FAKE_RSSI cmd
2026-01-29 03:01:15.336 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:01:15.336 [DEBUG] fake_trx.py:322 (BTS@172.18.28.20:5700) Recv FAKE_CI cmd
2026-01-29 03:01:15.340 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 03:01:15.340 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 03:01:15.341 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 03:01:15.342 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 03:01:15.342 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 03:01:15.342 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 03:01:15.343 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.28.22:6700) Recv POWERON CMD
2026-01-29 03:01:15.343 [INFO] ctrl_if_trx.py:109 (MS@172.18.28.22:6700) Starting transceiver...
2026-01-29 03:01:15.771 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-01-29 03:01:15.808 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 03:01:15.809 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:01:15.809 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:01:15.813 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:01:16.249 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-01-29 03:01:16.727 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-01-29 03:01:16.809 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 03:01:16.809 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:01:16.810 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:01:16.813 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:01:17.204 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-01-29 03:01:17.679 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-01-29 03:01:17.810 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 03:01:17.810 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:01:17.811 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:01:17.814 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:01:18.157 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-01-29 03:01:18.634 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-01-29 03:01:18.811 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 03:01:18.811 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:01:18.811 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:01:18.815 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:01:19.112 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-01-29 03:01:19.589 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-01-29 03:01:19.811 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 03:01:19.812 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:01:19.812 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:01:19.816 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:01:20.066 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-01-29 03:01:20.545 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-01-29 03:01:21.022 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-01-29 03:01:21.500 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-01-29 03:01:21.978 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-01-29 03:01:22.456 [DEBUG] clck_gen.py:113 IND CLOCK 1632
2026-01-29 03:01:22.934 [DEBUG] clck_gen.py:113 IND CLOCK 1734
2026-01-29 03:01:23.390 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 03:01:23.390 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 03:01:23.391 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 03:01:23.391 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:01:23.391 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:01:23.391 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:01:23.392 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 03:01:23.392 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 03:01:23.392 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 03:01:23.392 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 03:01:23.392 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.28.20:5700) Recv POWEROFF cmd
2026-01-29 03:01:23.392 [INFO] ctrl_if_trx.py:117 (BTS@172.18.28.20:5700) Stopping transceiver...
2026-01-29 03:01:23.392 [INFO] transceiver.py:246 Stopping clock generator
2026-01-29 03:01:23.392 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=1835 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:01:23.392 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=1835 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:01:23.392 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=1835 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:01:23.392 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=1835 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:01:23.392 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=1835 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:01:23.392 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=1835 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:01:28.399 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.28.20:5700) Recv POWEROFF cmd
2026-01-29 03:01:28.399 [INFO] ctrl_if_trx.py:117 (BTS@172.18.28.20:5700) Stopping transceiver...
2026-01-29 03:01:28.399 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 03:01:28.399 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 03:01:28.399 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 03:01:28.399 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 03:01:28.407 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 03:01:28.409 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.28.20:5700) Recv SETFORMAT cmd
2026-01-29 03:01:28.409 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.28.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:01:28.410 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.28.20:5700) Recv SETFORMAT cmd
2026-01-29 03:01:28.410 [INFO] ctrl_if_trx.py:201 (BTS@172.18.28.20:5700) TRXD header version 1 -> 1
2026-01-29 03:01:28.414 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.28.20:5700/1) Recv RXTUNE cmd
2026-01-29 03:01:28.414 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.28.20:5700/1) Recv TXTUNE cmd
2026-01-29 03:01:28.415 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.28.20:5700/1) Recv SETFORMAT cmd
2026-01-29 03:01:28.415 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.28.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:01:28.415 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 03:01:28.416 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.28.20:5700/1) Recv NOMTXPOWER cmd
2026-01-29 03:01:28.416 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.28.20:5700/1) Recv SETFORMAT cmd
2026-01-29 03:01:28.416 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.28.20:5700/1) TRXD header version 1 -> 1
2026-01-29 03:01:28.418 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.28.20:5700/2) Recv RXTUNE cmd
2026-01-29 03:01:28.418 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.28.20:5700/2) Recv TXTUNE cmd
2026-01-29 03:01:28.418 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.28.20:5700/2) Recv SETFORMAT cmd
2026-01-29 03:01:28.418 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.28.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:01:28.419 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 03:01:28.419 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.28.20:5700/2) Recv NOMTXPOWER cmd
2026-01-29 03:01:28.419 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.28.20:5700/2) Recv SETFORMAT cmd
2026-01-29 03:01:28.419 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.28.20:5700/2) TRXD header version 1 -> 1
2026-01-29 03:01:28.420 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.28.20:5700/3) Recv RXTUNE cmd
2026-01-29 03:01:28.420 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.28.20:5700/3) Recv TXTUNE cmd
2026-01-29 03:01:28.420 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.28.20:5700/3) Recv SETFORMAT cmd
2026-01-29 03:01:28.420 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.28.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:01:28.420 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 03:01:28.420 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.28.20:5700/3) Recv NOMTXPOWER cmd
2026-01-29 03:01:28.421 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.28.20:5700/3) Recv SETFORMAT cmd
2026-01-29 03:01:28.421 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.28.20:5700/3) TRXD header version 1 -> 1
2026-01-29 03:01:28.423 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.28.20:5700) Recv RXTUNE cmd
2026-01-29 03:01:28.423 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETTSC
2026-01-29 03:01:28.423 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETTSC
2026-01-29 03:01:28.423 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETTSC
2026-01-29 03:01:28.423 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.28.20:5700) Recv TXTUNE cmd
2026-01-29 03:01:28.423 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETRXGAIN
2026-01-29 03:01:28.423 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETRXGAIN
2026-01-29 03:01:28.423 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETRXGAIN
2026-01-29 03:01:28.423 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETTSC
2026-01-29 03:01:28.423 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:01:28.423 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:01:28.423 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:01:28.423 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.28.20:5700) Recv NOMTXPOWER cmd
2026-01-29 03:01:28.423 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:01:28.423 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:01:28.423 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:01:28.423 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.28.20:5700) Recv POWERON CMD
2026-01-29 03:01:28.423 [INFO] ctrl_if_trx.py:109 (BTS@172.18.28.20:5700) Starting transceiver...
2026-01-29 03:01:28.423 [INFO] transceiver.py:243 Starting clock generator
2026-01-29 03:01:28.423 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-01-29 03:01:28.423 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:01:28.423 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:01:28.423 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:01:28.424 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETRXGAIN
2026-01-29 03:01:28.424 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:01:28.424 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:01:28.424 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:01:28.424 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:01:28.424 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:01:28.424 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:01:28.424 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:01:28.424 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:01:28.424 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:01:28.424 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:01:28.424 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:01:28.424 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:01:28.424 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:01:28.424 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:01:28.424 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:01:28.424 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:01:28.424 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:01:28.424 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:01:28.424 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:01:28.424 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:01:28.424 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:01:28.424 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:01:28.424 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:01:28.428 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-01-29 03:01:28.911 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-01-29 03:01:28.950 [DEBUG] fake_trx.py:278 (BTS@172.18.28.20:5700) Recv FAKE_TOA cmd
2026-01-29 03:01:28.952 [DEBUG] fake_trx.py:297 (BTS@172.18.28.20:5700) Recv FAKE_RSSI cmd
2026-01-29 03:01:28.955 [DEBUG] fake_trx.py:322 (BTS@172.18.28.20:5700) Recv FAKE_CI cmd
2026-01-29 03:01:28.955 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:01:28.958 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 03:01:28.958 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 03:01:28.959 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 03:01:28.959 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 03:01:28.960 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 03:01:28.960 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 03:01:28.961 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.28.22:6700) Recv POWERON CMD
2026-01-29 03:01:28.961 [INFO] ctrl_if_trx.py:109 (MS@172.18.28.22:6700) Starting transceiver...
2026-01-29 03:01:29.388 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-01-29 03:01:29.426 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 03:01:29.426 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:01:29.427 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:01:29.429 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:01:29.866 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-01-29 03:01:30.344 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-01-29 03:01:30.426 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 03:01:30.427 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:01:30.427 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:01:30.430 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:01:30.822 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-01-29 03:01:31.300 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-01-29 03:01:31.427 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 03:01:31.428 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:01:31.428 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:01:31.430 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:01:31.778 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-01-29 03:01:32.255 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-01-29 03:01:32.429 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:01:32.429 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:01:32.429 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 03:01:32.431 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:01:32.734 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-01-29 03:01:33.211 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-01-29 03:01:33.429 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:01:33.430 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:01:33.430 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 03:01:33.432 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:01:33.689 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-01-29 03:01:34.166 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-01-29 03:01:34.644 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-01-29 03:01:35.122 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-01-29 03:01:35.600 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-01-29 03:01:36.077 [DEBUG] clck_gen.py:113 IND CLOCK 1632
2026-01-29 03:01:36.555 [DEBUG] clck_gen.py:113 IND CLOCK 1734
2026-01-29 03:01:37.008 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 03:01:37.008 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 03:01:37.012 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 03:01:37.012 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:01:37.012 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:01:37.013 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:01:37.013 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 03:01:37.013 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 03:01:37.013 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 03:01:37.013 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 03:01:37.013 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.28.20:5700) Recv POWEROFF cmd
2026-01-29 03:01:37.013 [INFO] ctrl_if_trx.py:117 (BTS@172.18.28.20:5700) Stopping transceiver...
2026-01-29 03:01:37.013 [INFO] transceiver.py:246 Stopping clock generator
2026-01-29 03:01:37.014 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=1834 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:01:37.014 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=1834 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:01:37.014 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=1834 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:01:37.014 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=1834 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:01:37.014 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=1834 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:01:37.014 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=1834 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:01:37.014 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=1834 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:01:42.016 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.28.20:5700) Recv POWEROFF cmd
2026-01-29 03:01:42.016 [INFO] ctrl_if_trx.py:117 (BTS@172.18.28.20:5700) Stopping transceiver...
2026-01-29 03:01:42.018 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 03:01:42.022 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 03:01:42.022 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 03:01:42.023 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 03:01:42.030 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 03:01:42.032 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.28.20:5700) Recv SETFORMAT cmd
2026-01-29 03:01:42.032 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.28.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:01:42.033 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.28.20:5700) Recv SETFORMAT cmd
2026-01-29 03:01:42.033 [INFO] ctrl_if_trx.py:201 (BTS@172.18.28.20:5700) TRXD header version 1 -> 1
2026-01-29 03:01:42.037 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.28.20:5700/1) Recv RXTUNE cmd
2026-01-29 03:01:42.037 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.28.20:5700/1) Recv TXTUNE cmd
2026-01-29 03:01:42.037 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.28.20:5700/1) Recv SETFORMAT cmd
2026-01-29 03:01:42.037 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.28.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:01:42.037 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 03:01:42.037 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.28.20:5700/1) Recv NOMTXPOWER cmd
2026-01-29 03:01:42.038 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.28.20:5700/1) Recv SETFORMAT cmd
2026-01-29 03:01:42.038 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.28.20:5700/1) TRXD header version 1 -> 1
2026-01-29 03:01:42.040 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.28.20:5700/2) Recv RXTUNE cmd
2026-01-29 03:01:42.041 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.28.20:5700/2) Recv TXTUNE cmd
2026-01-29 03:01:42.041 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.28.20:5700/2) Recv SETFORMAT cmd
2026-01-29 03:01:42.041 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.28.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:01:42.041 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 03:01:42.041 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.28.20:5700/2) Recv NOMTXPOWER cmd
2026-01-29 03:01:42.041 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.28.20:5700/2) Recv SETFORMAT cmd
2026-01-29 03:01:42.041 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.28.20:5700/2) TRXD header version 1 -> 1
2026-01-29 03:01:42.043 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.28.20:5700/3) Recv RXTUNE cmd
2026-01-29 03:01:42.044 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.28.20:5700/3) Recv TXTUNE cmd
2026-01-29 03:01:42.044 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.28.20:5700/3) Recv SETFORMAT cmd
2026-01-29 03:01:42.044 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.28.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:01:42.044 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 03:01:42.044 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.28.20:5700/3) Recv NOMTXPOWER cmd
2026-01-29 03:01:42.044 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.28.20:5700/3) Recv SETFORMAT cmd
2026-01-29 03:01:42.044 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.28.20:5700/3) TRXD header version 1 -> 1
2026-01-29 03:01:42.047 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.28.20:5700) Recv RXTUNE cmd
2026-01-29 03:01:42.047 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETTSC
2026-01-29 03:01:42.047 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETTSC
2026-01-29 03:01:42.047 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETTSC
2026-01-29 03:01:42.047 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.28.20:5700) Recv TXTUNE cmd
2026-01-29 03:01:42.047 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETRXGAIN
2026-01-29 03:01:42.047 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETRXGAIN
2026-01-29 03:01:42.047 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETRXGAIN
2026-01-29 03:01:42.047 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETTSC
2026-01-29 03:01:42.047 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:01:42.047 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:01:42.047 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:01:42.047 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.28.20:5700) Recv NOMTXPOWER cmd
2026-01-29 03:01:42.047 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:01:42.048 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:01:42.048 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:01:42.048 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.28.20:5700) Recv POWERON CMD
2026-01-29 03:01:42.048 [INFO] ctrl_if_trx.py:109 (BTS@172.18.28.20:5700) Starting transceiver...
2026-01-29 03:01:42.048 [INFO] transceiver.py:243 Starting clock generator
2026-01-29 03:01:42.048 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-01-29 03:01:42.048 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:01:42.048 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:01:42.048 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:01:42.048 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETRXGAIN
2026-01-29 03:01:42.048 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:01:42.048 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:01:42.048 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:01:42.048 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:01:42.048 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:01:42.048 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:01:42.048 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:01:42.048 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:01:42.048 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:01:42.049 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:01:42.049 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:01:42.049 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:01:42.049 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:01:42.049 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:01:42.049 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:01:42.049 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:01:42.049 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:01:42.049 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:01:42.049 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:01:42.049 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:01:42.049 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:01:42.049 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:01:42.049 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:01:42.053 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-01-29 03:01:42.536 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-01-29 03:01:42.579 [DEBUG] fake_trx.py:278 (BTS@172.18.28.20:5700) Recv FAKE_TOA cmd
2026-01-29 03:01:42.581 [DEBUG] fake_trx.py:297 (BTS@172.18.28.20:5700) Recv FAKE_RSSI cmd
2026-01-29 03:01:42.582 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:01:42.583 [DEBUG] fake_trx.py:322 (BTS@172.18.28.20:5700) Recv FAKE_CI cmd
2026-01-29 03:01:42.586 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 03:01:42.586 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 03:01:42.587 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 03:01:42.587 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 03:01:42.587 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 03:01:42.588 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 03:01:42.588 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.28.22:6700) Recv POWERON CMD
2026-01-29 03:01:42.588 [INFO] ctrl_if_trx.py:109 (MS@172.18.28.22:6700) Starting transceiver...
2026-01-29 03:01:43.013 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-01-29 03:01:43.050 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 03:01:43.051 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:01:43.053 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:01:43.055 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:01:43.490 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-01-29 03:01:43.967 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-01-29 03:01:44.051 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 03:01:44.052 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:01:44.053 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:01:44.056 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:01:44.445 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-01-29 03:01:44.923 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-01-29 03:01:45.052 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 03:01:45.052 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:01:45.055 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:01:45.057 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:01:45.399 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-01-29 03:01:45.877 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-01-29 03:01:46.052 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 03:01:46.053 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:01:46.055 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:01:46.057 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:01:46.354 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-01-29 03:01:46.832 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-01-29 03:01:47.054 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 03:01:47.054 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:01:47.056 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:01:47.058 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:01:47.311 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-01-29 03:01:47.789 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-01-29 03:01:48.267 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-01-29 03:01:48.744 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-01-29 03:01:49.222 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-01-29 03:01:49.700 [DEBUG] clck_gen.py:113 IND CLOCK 1632
2026-01-29 03:01:50.178 [DEBUG] clck_gen.py:113 IND CLOCK 1734
2026-01-29 03:01:50.634 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 03:01:50.635 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 03:01:50.638 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 03:01:50.639 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:01:50.639 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:01:50.639 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:01:50.643 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 03:01:50.643 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 03:01:50.643 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 03:01:50.643 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 03:01:50.643 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.28.20:5700) Recv POWEROFF cmd
2026-01-29 03:01:50.643 [INFO] ctrl_if_trx.py:117 (BTS@172.18.28.20:5700) Stopping transceiver...
2026-01-29 03:01:50.643 [INFO] transceiver.py:246 Stopping clock generator
2026-01-29 03:01:50.644 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=1836 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:01:50.644 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=1836 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:01:50.644 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=1836 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:01:50.644 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=1836 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:01:50.644 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=1836 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:01:50.644 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=1836 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:01:55.642 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.28.20:5700) Recv POWEROFF cmd
2026-01-29 03:01:55.642 [INFO] ctrl_if_trx.py:117 (BTS@172.18.28.20:5700) Stopping transceiver...
2026-01-29 03:01:55.646 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 03:01:55.646 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 03:01:55.646 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 03:01:55.646 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 03:01:55.655 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 03:01:55.657 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.28.20:5700) Recv SETFORMAT cmd
2026-01-29 03:01:55.657 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.28.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:01:55.657 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.28.20:5700) Recv SETFORMAT cmd
2026-01-29 03:01:55.658 [INFO] ctrl_if_trx.py:201 (BTS@172.18.28.20:5700) TRXD header version 1 -> 1
2026-01-29 03:01:55.661 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.28.20:5700/1) Recv RXTUNE cmd
2026-01-29 03:01:55.661 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.28.20:5700/1) Recv TXTUNE cmd
2026-01-29 03:01:55.662 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.28.20:5700/1) Recv SETFORMAT cmd
2026-01-29 03:01:55.662 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.28.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:01:55.662 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 03:01:55.663 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.28.20:5700/1) Recv NOMTXPOWER cmd
2026-01-29 03:01:55.663 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.28.20:5700/1) Recv SETFORMAT cmd
2026-01-29 03:01:55.663 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.28.20:5700/1) TRXD header version 1 -> 1
2026-01-29 03:01:55.664 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.28.20:5700/2) Recv RXTUNE cmd
2026-01-29 03:01:55.665 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.28.20:5700/2) Recv TXTUNE cmd
2026-01-29 03:01:55.665 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.28.20:5700/2) Recv SETFORMAT cmd
2026-01-29 03:01:55.665 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.28.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:01:55.665 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 03:01:55.665 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.28.20:5700/2) Recv NOMTXPOWER cmd
2026-01-29 03:01:55.665 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.28.20:5700/2) Recv SETFORMAT cmd
2026-01-29 03:01:55.665 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.28.20:5700/2) TRXD header version 1 -> 1
2026-01-29 03:01:55.668 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.28.20:5700/3) Recv RXTUNE cmd
2026-01-29 03:01:55.668 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.28.20:5700/3) Recv TXTUNE cmd
2026-01-29 03:01:55.669 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.28.20:5700/3) Recv SETFORMAT cmd
2026-01-29 03:01:55.669 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.28.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:01:55.669 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 03:01:55.669 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.28.20:5700/3) Recv NOMTXPOWER cmd
2026-01-29 03:01:55.669 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.28.20:5700/3) Recv SETFORMAT cmd
2026-01-29 03:01:55.669 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.28.20:5700/3) TRXD header version 1 -> 1
2026-01-29 03:01:55.672 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.28.20:5700) Recv RXTUNE cmd
2026-01-29 03:01:55.672 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETTSC
2026-01-29 03:01:55.672 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETTSC
2026-01-29 03:01:55.672 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETTSC
2026-01-29 03:01:55.672 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.28.20:5700) Recv TXTUNE cmd
2026-01-29 03:01:55.672 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETRXGAIN
2026-01-29 03:01:55.672 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETRXGAIN
2026-01-29 03:01:55.672 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETRXGAIN
2026-01-29 03:01:55.672 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETTSC
2026-01-29 03:01:55.672 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:01:55.672 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:01:55.672 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.28.20:5700) Recv NOMTXPOWER cmd
2026-01-29 03:01:55.672 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:01:55.672 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:01:55.672 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:01:55.672 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.28.20:5700) Recv POWERON CMD
2026-01-29 03:01:55.672 [INFO] ctrl_if_trx.py:109 (BTS@172.18.28.20:5700) Starting transceiver...
2026-01-29 03:01:55.673 [INFO] transceiver.py:243 Starting clock generator
2026-01-29 03:01:55.673 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-01-29 03:01:55.673 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:01:55.673 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:01:55.673 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:01:55.673 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETRXGAIN
2026-01-29 03:01:55.673 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:01:55.673 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:01:55.673 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:01:55.673 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:01:55.673 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:01:55.673 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:01:55.673 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:01:55.674 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:01:55.674 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:01:55.674 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:01:55.674 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:01:55.674 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:01:55.674 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:01:55.674 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:01:55.674 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:01:55.674 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:01:55.674 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:01:55.674 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:01:55.674 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:01:55.674 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:01:55.674 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:01:55.674 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:01:55.674 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:01:55.674 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:01:55.678 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-01-29 03:01:56.160 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-01-29 03:01:56.200 [DEBUG] fake_trx.py:278 (BTS@172.18.28.20:5700) Recv FAKE_TOA cmd
2026-01-29 03:01:56.202 [DEBUG] fake_trx.py:297 (BTS@172.18.28.20:5700) Recv FAKE_RSSI cmd
2026-01-29 03:01:56.202 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:01:56.204 [DEBUG] fake_trx.py:322 (BTS@172.18.28.20:5700) Recv FAKE_CI cmd
2026-01-29 03:01:56.208 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 03:01:56.208 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 03:01:56.208 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 03:01:56.209 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 03:01:56.209 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 03:01:56.209 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 03:01:56.209 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.28.22:6700) Recv POWERON CMD
2026-01-29 03:01:56.209 [INFO] ctrl_if_trx.py:109 (MS@172.18.28.22:6700) Starting transceiver...
2026-01-29 03:01:56.637 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-01-29 03:01:56.675 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 03:01:56.676 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:01:56.678 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:01:56.680 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:01:57.115 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-01-29 03:01:57.593 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-01-29 03:01:57.676 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 03:01:57.676 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:01:57.680 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:01:57.681 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:01:58.070 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-01-29 03:01:58.548 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-01-29 03:01:58.677 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 03:01:58.678 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:01:58.681 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:01:58.682 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:01:59.027 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-01-29 03:01:59.505 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-01-29 03:01:59.679 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 03:01:59.679 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:01:59.682 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:01:59.682 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:01:59.984 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-01-29 03:02:00.462 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-01-29 03:02:00.680 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 03:02:00.680 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:02:00.683 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:02:00.683 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:02:00.940 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-01-29 03:02:01.418 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-01-29 03:02:01.895 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-01-29 03:02:02.373 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-01-29 03:02:02.851 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-01-29 03:02:03.329 [DEBUG] clck_gen.py:113 IND CLOCK 1632
2026-01-29 03:02:03.807 [DEBUG] clck_gen.py:113 IND CLOCK 1734
2026-01-29 03:02:04.285 [DEBUG] clck_gen.py:113 IND CLOCK 1836
2026-01-29 03:02:04.763 [DEBUG] clck_gen.py:113 IND CLOCK 1938
2026-01-29 03:02:05.240 [DEBUG] clck_gen.py:113 IND CLOCK 2040
2026-01-29 03:02:05.718 [DEBUG] clck_gen.py:113 IND CLOCK 2142
2026-01-29 03:02:06.196 [DEBUG] clck_gen.py:113 IND CLOCK 2244
2026-01-29 03:02:06.674 [DEBUG] clck_gen.py:113 IND CLOCK 2346
2026-01-29 03:02:07.152 [DEBUG] clck_gen.py:113 IND CLOCK 2448
2026-01-29 03:02:07.630 [DEBUG] clck_gen.py:113 IND CLOCK 2550
2026-01-29 03:02:08.108 [DEBUG] clck_gen.py:113 IND CLOCK 2652
2026-01-29 03:02:08.585 [DEBUG] clck_gen.py:113 IND CLOCK 2754
2026-01-29 03:02:09.062 [DEBUG] clck_gen.py:113 IND CLOCK 2856
2026-01-29 03:02:09.540 [DEBUG] clck_gen.py:113 IND CLOCK 2958
2026-01-29 03:02:10.018 [DEBUG] clck_gen.py:113 IND CLOCK 3060
2026-01-29 03:02:10.496 [DEBUG] clck_gen.py:113 IND CLOCK 3162
2026-01-29 03:02:10.968 [DEBUG] clck_gen.py:113 IND CLOCK 3264
2026-01-29 03:02:11.446 [DEBUG] clck_gen.py:113 IND CLOCK 3366
2026-01-29 03:02:11.924 [DEBUG] clck_gen.py:113 IND CLOCK 3468
2026-01-29 03:02:12.268 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 03:02:12.268 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 03:02:12.272 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 03:02:12.272 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:02:12.273 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:02:12.273 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:02:12.276 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 03:02:12.276 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 03:02:12.276 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 03:02:12.276 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 03:02:12.276 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.28.20:5700) Recv POWEROFF cmd
2026-01-29 03:02:12.276 [INFO] ctrl_if_trx.py:117 (BTS@172.18.28.20:5700) Stopping transceiver...
2026-01-29 03:02:12.276 [INFO] transceiver.py:246 Stopping clock generator
2026-01-29 03:02:12.277 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=3546 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:02:12.277 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=3546 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:02:12.277 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=3546 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:02:12.277 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=3546 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:02:12.277 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=3546 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:02:12.277 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=3546 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:02:17.275 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.28.20:5700) Recv POWEROFF cmd
2026-01-29 03:02:17.275 [INFO] ctrl_if_trx.py:117 (BTS@172.18.28.20:5700) Stopping transceiver...
2026-01-29 03:02:17.277 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 03:02:17.278 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 03:02:17.278 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 03:02:17.278 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 03:02:17.285 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 03:02:17.286 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.28.20:5700) Recv SETFORMAT cmd
2026-01-29 03:02:17.287 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.28.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:02:17.287 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.28.20:5700) Recv SETFORMAT cmd
2026-01-29 03:02:17.287 [INFO] ctrl_if_trx.py:201 (BTS@172.18.28.20:5700) TRXD header version 1 -> 1
2026-01-29 03:02:17.289 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.28.20:5700/1) Recv RXTUNE cmd
2026-01-29 03:02:17.289 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.28.20:5700/1) Recv TXTUNE cmd
2026-01-29 03:02:17.290 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.28.20:5700/1) Recv SETFORMAT cmd
2026-01-29 03:02:17.290 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.28.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:02:17.290 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 03:02:17.290 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.28.20:5700/1) Recv NOMTXPOWER cmd
2026-01-29 03:02:17.291 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.28.20:5700/1) Recv SETFORMAT cmd
2026-01-29 03:02:17.291 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.28.20:5700/1) TRXD header version 1 -> 1
2026-01-29 03:02:17.292 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.28.20:5700/2) Recv RXTUNE cmd
2026-01-29 03:02:17.292 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.28.20:5700/2) Recv TXTUNE cmd
2026-01-29 03:02:17.292 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.28.20:5700/2) Recv SETFORMAT cmd
2026-01-29 03:02:17.292 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.28.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:02:17.292 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 03:02:17.292 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.28.20:5700/2) Recv NOMTXPOWER cmd
2026-01-29 03:02:17.292 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.28.20:5700/2) Recv SETFORMAT cmd
2026-01-29 03:02:17.292 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.28.20:5700/2) TRXD header version 1 -> 1
2026-01-29 03:02:17.294 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.28.20:5700/3) Recv RXTUNE cmd
2026-01-29 03:02:17.294 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.28.20:5700/3) Recv TXTUNE cmd
2026-01-29 03:02:17.294 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.28.20:5700/3) Recv SETFORMAT cmd
2026-01-29 03:02:17.294 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.28.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:02:17.294 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 03:02:17.294 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.28.20:5700/3) Recv NOMTXPOWER cmd
2026-01-29 03:02:17.294 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.28.20:5700/3) Recv SETFORMAT cmd
2026-01-29 03:02:17.294 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.28.20:5700/3) TRXD header version 1 -> 1
2026-01-29 03:02:17.297 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.28.20:5700) Recv RXTUNE cmd
2026-01-29 03:02:17.297 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETTSC
2026-01-29 03:02:17.297 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETTSC
2026-01-29 03:02:17.297 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETTSC
2026-01-29 03:02:17.297 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.28.20:5700) Recv TXTUNE cmd
2026-01-29 03:02:17.297 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETRXGAIN
2026-01-29 03:02:17.297 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETRXGAIN
2026-01-29 03:02:17.297 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETRXGAIN
2026-01-29 03:02:17.297 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETTSC
2026-01-29 03:02:17.297 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:02:17.297 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:02:17.297 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:02:17.297 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.28.20:5700) Recv NOMTXPOWER cmd
2026-01-29 03:02:17.297 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:02:17.297 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:02:17.297 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:02:17.297 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.28.20:5700) Recv POWERON CMD
2026-01-29 03:02:17.297 [INFO] ctrl_if_trx.py:109 (BTS@172.18.28.20:5700) Starting transceiver...
2026-01-29 03:02:17.297 [INFO] transceiver.py:243 Starting clock generator
2026-01-29 03:02:17.297 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-01-29 03:02:17.297 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:02:17.297 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:02:17.297 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:02:17.298 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETRXGAIN
2026-01-29 03:02:17.298 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:02:17.298 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:02:17.298 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:02:17.298 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:02:17.298 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:02:17.298 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:02:17.298 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:02:17.298 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:02:17.298 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:02:17.298 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:02:17.298 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:02:17.298 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:02:17.298 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:02:17.298 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:02:17.298 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:02:17.298 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:02:17.298 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:02:17.298 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:02:17.298 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:02:17.298 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:02:17.298 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:02:17.298 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:02:17.298 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:02:17.302 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-01-29 03:02:17.785 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-01-29 03:02:17.825 [DEBUG] fake_trx.py:278 (BTS@172.18.28.20:5700) Recv FAKE_TOA cmd
2026-01-29 03:02:17.827 [DEBUG] fake_trx.py:297 (BTS@172.18.28.20:5700) Recv FAKE_RSSI cmd
2026-01-29 03:02:17.829 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:02:17.830 [DEBUG] fake_trx.py:322 (BTS@172.18.28.20:5700) Recv FAKE_CI cmd
2026-01-29 03:02:17.842 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 03:02:17.842 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 03:02:17.842 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 03:02:17.842 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 03:02:17.843 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 03:02:17.843 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 03:02:17.843 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.28.22:6700) Recv POWERON CMD
2026-01-29 03:02:17.843 [INFO] ctrl_if_trx.py:109 (MS@172.18.28.22:6700) Starting transceiver...
2026-01-29 03:02:18.260 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-01-29 03:02:18.299 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 03:02:18.301 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:02:18.301 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:02:18.304 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:02:18.737 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-01-29 03:02:19.215 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-01-29 03:02:19.300 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 03:02:19.301 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:02:19.302 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:02:19.304 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:02:19.693 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-01-29 03:02:20.171 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-01-29 03:02:20.301 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 03:02:20.303 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:02:20.303 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:02:20.305 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:02:20.648 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-01-29 03:02:21.126 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-01-29 03:02:21.302 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 03:02:21.304 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:02:21.304 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:02:21.305 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:02:21.601 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-01-29 03:02:22.079 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-01-29 03:02:22.302 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 03:02:22.305 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:02:22.305 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:02:22.306 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:02:22.553 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-01-29 03:02:23.028 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-01-29 03:02:23.505 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-01-29 03:02:23.983 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-01-29 03:02:24.461 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-01-29 03:02:24.938 [DEBUG] clck_gen.py:113 IND CLOCK 1632
2026-01-29 03:02:25.416 [DEBUG] clck_gen.py:113 IND CLOCK 1734
2026-01-29 03:02:25.882 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 03:02:25.882 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 03:02:25.893 [DEBUG] clck_gen.py:113 IND CLOCK 1836
2026-01-29 03:02:25.893 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 03:02:25.894 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:02:25.894 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:02:25.894 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:02:25.897 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 03:02:25.897 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 03:02:25.897 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 03:02:25.897 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 03:02:25.897 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.28.20:5700) Recv POWEROFF cmd
2026-01-29 03:02:25.897 [INFO] ctrl_if_trx.py:117 (BTS@172.18.28.20:5700) Stopping transceiver...
2026-01-29 03:02:25.898 [INFO] transceiver.py:246 Stopping clock generator
2026-01-29 03:02:25.898 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=1839 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:02:25.898 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=1839 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:02:25.898 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=1839 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:02:25.898 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=1839 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:02:25.898 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=1839 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:02:25.898 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=1839 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:02:25.898 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=1839 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:02:25.899 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=1840 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:02:25.899 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=1840 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:02:25.899 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=1840 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:02:25.899 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=1840 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:02:25.899 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=1840 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:02:25.899 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=1840 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:02:25.899 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=1840 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:02:25.899 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=1840 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:02:30.897 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.28.20:5700) Recv POWEROFF cmd
2026-01-29 03:02:30.897 [INFO] ctrl_if_trx.py:117 (BTS@172.18.28.20:5700) Stopping transceiver...
2026-01-29 03:02:30.899 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 03:02:30.900 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 03:02:30.900 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 03:02:30.900 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 03:02:30.908 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 03:02:30.909 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.28.20:5700) Recv SETFORMAT cmd
2026-01-29 03:02:30.909 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.28.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:02:30.910 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.28.20:5700) Recv SETFORMAT cmd
2026-01-29 03:02:30.910 [INFO] ctrl_if_trx.py:201 (BTS@172.18.28.20:5700) TRXD header version 1 -> 1
2026-01-29 03:02:30.914 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.28.20:5700/1) Recv RXTUNE cmd
2026-01-29 03:02:30.914 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.28.20:5700/1) Recv TXTUNE cmd
2026-01-29 03:02:30.914 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.28.20:5700/1) Recv SETFORMAT cmd
2026-01-29 03:02:30.914 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.28.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:02:30.914 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 03:02:30.914 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.28.20:5700/1) Recv NOMTXPOWER cmd
2026-01-29 03:02:30.914 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.28.20:5700/1) Recv SETFORMAT cmd
2026-01-29 03:02:30.915 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.28.20:5700/1) TRXD header version 1 -> 1
2026-01-29 03:02:30.917 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.28.20:5700/2) Recv RXTUNE cmd
2026-01-29 03:02:30.917 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.28.20:5700/2) Recv TXTUNE cmd
2026-01-29 03:02:30.918 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.28.20:5700/2) Recv SETFORMAT cmd
2026-01-29 03:02:30.918 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.28.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:02:30.918 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 03:02:30.918 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.28.20:5700/2) Recv NOMTXPOWER cmd
2026-01-29 03:02:30.918 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.28.20:5700/2) Recv SETFORMAT cmd
2026-01-29 03:02:30.918 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.28.20:5700/2) TRXD header version 1 -> 1
2026-01-29 03:02:30.921 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.28.20:5700/3) Recv RXTUNE cmd
2026-01-29 03:02:30.921 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.28.20:5700/3) Recv TXTUNE cmd
2026-01-29 03:02:30.921 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.28.20:5700/3) Recv SETFORMAT cmd
2026-01-29 03:02:30.921 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.28.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:02:30.921 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 03:02:30.921 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.28.20:5700/3) Recv NOMTXPOWER cmd
2026-01-29 03:02:30.921 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.28.20:5700/3) Recv SETFORMAT cmd
2026-01-29 03:02:30.921 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.28.20:5700/3) TRXD header version 1 -> 1
2026-01-29 03:02:30.925 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.28.20:5700) Recv RXTUNE cmd
2026-01-29 03:02:30.925 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETTSC
2026-01-29 03:02:30.925 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETTSC
2026-01-29 03:02:30.925 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETTSC
2026-01-29 03:02:30.925 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.28.20:5700) Recv TXTUNE cmd
2026-01-29 03:02:30.925 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETRXGAIN
2026-01-29 03:02:30.925 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETRXGAIN
2026-01-29 03:02:30.925 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETRXGAIN
2026-01-29 03:02:30.925 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETTSC
2026-01-29 03:02:30.925 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:02:30.925 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:02:30.925 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:02:30.925 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.28.20:5700) Recv NOMTXPOWER cmd
2026-01-29 03:02:30.925 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:02:30.925 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:02:30.925 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:02:30.925 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.28.20:5700) Recv POWERON CMD
2026-01-29 03:02:30.925 [INFO] ctrl_if_trx.py:109 (BTS@172.18.28.20:5700) Starting transceiver...
2026-01-29 03:02:30.925 [INFO] transceiver.py:243 Starting clock generator
2026-01-29 03:02:30.926 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-01-29 03:02:30.926 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:02:30.926 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:02:30.926 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:02:30.926 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETRXGAIN
2026-01-29 03:02:30.926 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:02:30.926 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:02:30.926 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:02:30.926 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:02:30.926 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:02:30.926 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:02:30.926 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:02:30.927 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:02:30.927 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:02:30.927 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:02:30.927 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:02:30.927 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:02:30.927 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:02:30.927 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:02:30.927 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:02:30.927 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:02:30.927 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:02:30.927 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:02:30.927 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:02:30.927 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:02:30.927 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:02:30.927 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:02:30.927 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:02:30.931 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-01-29 03:02:31.415 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-01-29 03:02:31.457 [DEBUG] fake_trx.py:278 (BTS@172.18.28.20:5700) Recv FAKE_TOA cmd
2026-01-29 03:02:31.459 [DEBUG] fake_trx.py:297 (BTS@172.18.28.20:5700) Recv FAKE_RSSI cmd
2026-01-29 03:02:31.459 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:02:31.459 [DEBUG] fake_trx.py:322 (BTS@172.18.28.20:5700) Recv FAKE_CI cmd
2026-01-29 03:02:31.467 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 03:02:31.468 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 03:02:31.468 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 03:02:31.469 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 03:02:31.469 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 03:02:31.469 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 03:02:31.469 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.28.22:6700) Recv POWERON CMD
2026-01-29 03:02:31.469 [INFO] ctrl_if_trx.py:109 (MS@172.18.28.22:6700) Starting transceiver...
2026-01-29 03:02:31.893 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-01-29 03:02:31.929 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 03:02:31.929 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:02:31.931 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:02:31.935 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:02:32.371 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-01-29 03:02:32.848 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-01-29 03:02:32.930 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 03:02:32.931 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:02:32.932 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:02:32.936 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:02:33.326 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-01-29 03:02:33.804 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-01-29 03:02:33.931 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 03:02:33.931 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:02:33.933 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:02:33.937 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:02:34.281 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-01-29 03:02:34.760 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-01-29 03:02:34.932 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 03:02:34.932 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:02:34.933 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:02:34.939 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:02:35.237 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-01-29 03:02:35.715 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-01-29 03:02:35.933 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:02:35.933 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 03:02:35.935 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:02:35.940 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:02:36.193 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-01-29 03:02:36.671 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-01-29 03:02:37.148 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-01-29 03:02:37.626 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-01-29 03:02:38.104 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-01-29 03:02:38.581 [DEBUG] clck_gen.py:113 IND CLOCK 1632
2026-01-29 03:02:39.059 [DEBUG] clck_gen.py:113 IND CLOCK 1734
2026-01-29 03:02:39.537 [DEBUG] clck_gen.py:113 IND CLOCK 1836
2026-01-29 03:02:40.015 [DEBUG] clck_gen.py:113 IND CLOCK 1938
2026-01-29 03:02:40.492 [DEBUG] clck_gen.py:113 IND CLOCK 2040
2026-01-29 03:02:40.970 [DEBUG] clck_gen.py:113 IND CLOCK 2142
2026-01-29 03:02:41.448 [DEBUG] clck_gen.py:113 IND CLOCK 2244
2026-01-29 03:02:41.926 [DEBUG] clck_gen.py:113 IND CLOCK 2346
2026-01-29 03:02:42.404 [DEBUG] clck_gen.py:113 IND CLOCK 2448
2026-01-29 03:02:42.882 [DEBUG] clck_gen.py:113 IND CLOCK 2550
2026-01-29 03:02:43.360 [DEBUG] clck_gen.py:113 IND CLOCK 2652
2026-01-29 03:02:43.838 [DEBUG] clck_gen.py:113 IND CLOCK 2754
2026-01-29 03:02:44.316 [DEBUG] clck_gen.py:113 IND CLOCK 2856
2026-01-29 03:02:44.794 [DEBUG] clck_gen.py:113 IND CLOCK 2958
2026-01-29 03:02:45.272 [DEBUG] clck_gen.py:113 IND CLOCK 3060
2026-01-29 03:02:45.750 [DEBUG] clck_gen.py:113 IND CLOCK 3162
2026-01-29 03:02:46.229 [DEBUG] clck_gen.py:113 IND CLOCK 3264
2026-01-29 03:02:46.707 [DEBUG] clck_gen.py:113 IND CLOCK 3366
2026-01-29 03:02:47.185 [DEBUG] clck_gen.py:113 IND CLOCK 3468
2026-01-29 03:02:47.522 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 03:02:47.522 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 03:02:47.536 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 03:02:47.536 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:02:47.536 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:02:47.536 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:02:47.540 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 03:02:47.540 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 03:02:47.540 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 03:02:47.540 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 03:02:47.540 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.28.20:5700) Recv POWEROFF cmd
2026-01-29 03:02:47.540 [INFO] ctrl_if_trx.py:117 (BTS@172.18.28.20:5700) Stopping transceiver...
2026-01-29 03:02:47.541 [INFO] transceiver.py:246 Stopping clock generator
2026-01-29 03:02:47.541 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=3546 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:02:47.541 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=3546 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:02:47.541 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=3546 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:02:47.541 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=3546 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:02:47.541 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=3546 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:02:47.541 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=3546 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:02:47.541 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=3547 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:02:47.542 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=3547 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:02:47.542 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=3547 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:02:47.542 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=3547 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:02:47.542 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=3547 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:02:47.542 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=3547 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:02:47.542 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=3547 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:02:47.542 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=3547 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:02:52.540 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.28.20:5700) Recv POWEROFF cmd
2026-01-29 03:02:52.540 [INFO] ctrl_if_trx.py:117 (BTS@172.18.28.20:5700) Stopping transceiver...
2026-01-29 03:02:52.542 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 03:02:52.543 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 03:02:52.544 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 03:02:52.544 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 03:02:52.551 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 03:02:52.551 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.28.20:5700) Recv SETFORMAT cmd
2026-01-29 03:02:52.551 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.28.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:02:52.552 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.28.20:5700) Recv SETFORMAT cmd
2026-01-29 03:02:52.552 [INFO] ctrl_if_trx.py:201 (BTS@172.18.28.20:5700) TRXD header version 1 -> 1
2026-01-29 03:02:52.554 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.28.20:5700/1) Recv RXTUNE cmd
2026-01-29 03:02:52.554 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.28.20:5700/1) Recv TXTUNE cmd
2026-01-29 03:02:52.555 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.28.20:5700/1) Recv SETFORMAT cmd
2026-01-29 03:02:52.555 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.28.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:02:52.555 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 03:02:52.555 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.28.20:5700/1) Recv NOMTXPOWER cmd
2026-01-29 03:02:52.556 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.28.20:5700/1) Recv SETFORMAT cmd
2026-01-29 03:02:52.556 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.28.20:5700/1) TRXD header version 1 -> 1
2026-01-29 03:02:52.556 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.28.20:5700/2) Recv RXTUNE cmd
2026-01-29 03:02:52.557 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.28.20:5700/2) Recv TXTUNE cmd
2026-01-29 03:02:52.557 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.28.20:5700/2) Recv SETFORMAT cmd
2026-01-29 03:02:52.557 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.28.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:02:52.557 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 03:02:52.557 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.28.20:5700/2) Recv NOMTXPOWER cmd
2026-01-29 03:02:52.557 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.28.20:5700/2) Recv SETFORMAT cmd
2026-01-29 03:02:52.557 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.28.20:5700/2) TRXD header version 1 -> 1
2026-01-29 03:02:52.559 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.28.20:5700/3) Recv RXTUNE cmd
2026-01-29 03:02:52.559 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.28.20:5700/3) Recv TXTUNE cmd
2026-01-29 03:02:52.559 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.28.20:5700/3) Recv SETFORMAT cmd
2026-01-29 03:02:52.559 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.28.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:02:52.559 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 03:02:52.559 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.28.20:5700/3) Recv NOMTXPOWER cmd
2026-01-29 03:02:52.559 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.28.20:5700/3) Recv SETFORMAT cmd
2026-01-29 03:02:52.559 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.28.20:5700/3) TRXD header version 1 -> 1
2026-01-29 03:02:52.561 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.28.20:5700) Recv RXTUNE cmd
2026-01-29 03:02:52.561 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETTSC
2026-01-29 03:02:52.561 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETTSC
2026-01-29 03:02:52.561 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETTSC
2026-01-29 03:02:52.561 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.28.20:5700) Recv TXTUNE cmd
2026-01-29 03:02:52.561 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETRXGAIN
2026-01-29 03:02:52.561 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETRXGAIN
2026-01-29 03:02:52.561 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETRXGAIN
2026-01-29 03:02:52.562 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETTSC
2026-01-29 03:02:52.562 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:02:52.562 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:02:52.562 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.28.20:5700) Recv NOMTXPOWER cmd
2026-01-29 03:02:52.562 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:02:52.562 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:02:52.562 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:02:52.562 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.28.20:5700) Recv POWERON CMD
2026-01-29 03:02:52.562 [INFO] ctrl_if_trx.py:109 (BTS@172.18.28.20:5700) Starting transceiver...
2026-01-29 03:02:52.562 [INFO] transceiver.py:243 Starting clock generator
2026-01-29 03:02:52.562 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-01-29 03:02:52.562 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:02:52.562 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:02:52.562 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:02:52.562 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETRXGAIN
2026-01-29 03:02:52.562 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:02:52.562 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:02:52.562 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:02:52.562 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:02:52.562 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:02:52.562 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:02:52.562 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:02:52.562 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:02:52.562 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:02:52.563 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:02:52.563 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:02:52.563 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:02:52.563 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:02:52.563 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:02:52.563 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:02:52.563 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:02:52.563 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:02:52.563 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:02:52.563 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:02:52.563 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:02:52.563 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:02:52.563 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:02:52.563 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:02:52.563 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:02:52.567 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-01-29 03:02:53.049 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-01-29 03:02:53.093 [DEBUG] fake_trx.py:278 (BTS@172.18.28.20:5700) Recv FAKE_TOA cmd
2026-01-29 03:02:53.094 [DEBUG] fake_trx.py:297 (BTS@172.18.28.20:5700) Recv FAKE_RSSI cmd
2026-01-29 03:02:53.096 [DEBUG] fake_trx.py:322 (BTS@172.18.28.20:5700) Recv FAKE_CI cmd
2026-01-29 03:02:53.097 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:02:53.123 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 03:02:53.123 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 03:02:53.123 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 03:02:53.136 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 03:02:53.137 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:02:53.137 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:02:53.137 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:02:53.139 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 03:02:53.139 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 03:02:53.139 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 03:02:53.139 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 03:02:53.139 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.28.20:5700) Recv POWEROFF cmd
2026-01-29 03:02:53.139 [INFO] ctrl_if_trx.py:117 (BTS@172.18.28.20:5700) Stopping transceiver...
2026-01-29 03:02:53.139 [INFO] transceiver.py:246 Stopping clock generator
2026-01-29 03:02:53.139 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=123 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:02:53.140 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=123 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:02:53.140 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=123 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:02:53.140 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=123 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:02:53.140 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=123 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:02:53.140 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=123 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:02:53.140 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=123 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:02:58.140 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.28.20:5700) Recv POWEROFF cmd
2026-01-29 03:02:58.140 [INFO] ctrl_if_trx.py:117 (BTS@172.18.28.20:5700) Stopping transceiver...
2026-01-29 03:02:58.142 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 03:02:58.142 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 03:02:58.143 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 03:02:58.143 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 03:02:58.152 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 03:02:58.153 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.28.20:5700) Recv SETFORMAT cmd
2026-01-29 03:02:58.154 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.28.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:02:58.154 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.28.20:5700) Recv SETFORMAT cmd
2026-01-29 03:02:58.154 [INFO] ctrl_if_trx.py:201 (BTS@172.18.28.20:5700) TRXD header version 1 -> 1
2026-01-29 03:02:58.158 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.28.20:5700/1) Recv RXTUNE cmd
2026-01-29 03:02:58.159 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.28.20:5700/1) Recv TXTUNE cmd
2026-01-29 03:02:58.159 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.28.20:5700/1) Recv SETFORMAT cmd
2026-01-29 03:02:58.159 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.28.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:02:58.160 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 03:02:58.160 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.28.20:5700/1) Recv NOMTXPOWER cmd
2026-01-29 03:02:58.160 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.28.20:5700/1) Recv SETFORMAT cmd
2026-01-29 03:02:58.161 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.28.20:5700/1) TRXD header version 1 -> 1
2026-01-29 03:02:58.161 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.28.20:5700/2) Recv RXTUNE cmd
2026-01-29 03:02:58.161 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.28.20:5700/2) Recv TXTUNE cmd
2026-01-29 03:02:58.162 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.28.20:5700/2) Recv SETFORMAT cmd
2026-01-29 03:02:58.162 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.28.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:02:58.162 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 03:02:58.162 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.28.20:5700/2) Recv NOMTXPOWER cmd
2026-01-29 03:02:58.163 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.28.20:5700/2) Recv SETFORMAT cmd
2026-01-29 03:02:58.163 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.28.20:5700/2) TRXD header version 1 -> 1
2026-01-29 03:02:58.164 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.28.20:5700/3) Recv RXTUNE cmd
2026-01-29 03:02:58.164 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.28.20:5700/3) Recv TXTUNE cmd
2026-01-29 03:02:58.164 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.28.20:5700/3) Recv SETFORMAT cmd
2026-01-29 03:02:58.164 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.28.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:02:58.164 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 03:02:58.165 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.28.20:5700/3) Recv NOMTXPOWER cmd
2026-01-29 03:02:58.165 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.28.20:5700/3) Recv SETFORMAT cmd
2026-01-29 03:02:58.165 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.28.20:5700/3) TRXD header version 1 -> 1
2026-01-29 03:02:58.167 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.28.20:5700) Recv RXTUNE cmd
2026-01-29 03:02:58.167 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETTSC
2026-01-29 03:02:58.167 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETTSC
2026-01-29 03:02:58.167 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETTSC
2026-01-29 03:02:58.167 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.28.20:5700) Recv TXTUNE cmd
2026-01-29 03:02:58.167 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETRXGAIN
2026-01-29 03:02:58.167 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETRXGAIN
2026-01-29 03:02:58.167 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETRXGAIN
2026-01-29 03:02:58.167 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETTSC
2026-01-29 03:02:58.167 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:02:58.167 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:02:58.167 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:02:58.167 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.28.20:5700) Recv NOMTXPOWER cmd
2026-01-29 03:02:58.167 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:02:58.167 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:02:58.167 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:02:58.167 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.28.20:5700) Recv POWERON CMD
2026-01-29 03:02:58.167 [INFO] ctrl_if_trx.py:109 (BTS@172.18.28.20:5700) Starting transceiver...
2026-01-29 03:02:58.168 [INFO] transceiver.py:243 Starting clock generator
2026-01-29 03:02:58.168 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-01-29 03:02:58.168 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:02:58.168 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:02:58.168 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:02:58.168 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETRXGAIN
2026-01-29 03:02:58.168 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:02:58.168 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:02:58.168 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:02:58.168 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:02:58.168 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:02:58.168 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:02:58.168 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:02:58.168 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:02:58.168 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:02:58.168 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:02:58.168 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:02:58.168 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:02:58.168 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:02:58.168 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:02:58.168 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:02:58.168 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:02:58.168 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:02:58.168 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:02:58.169 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:02:58.169 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:02:58.169 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:02:58.169 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:02:58.169 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:02:58.172 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-01-29 03:02:58.656 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-01-29 03:02:58.694 [DEBUG] fake_trx.py:278 (BTS@172.18.28.20:5700) Recv FAKE_TOA cmd
2026-01-29 03:02:58.696 [DEBUG] fake_trx.py:297 (BTS@172.18.28.20:5700) Recv FAKE_RSSI cmd
2026-01-29 03:02:58.697 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:02:58.697 [DEBUG] fake_trx.py:322 (BTS@172.18.28.20:5700) Recv FAKE_CI cmd
2026-01-29 03:02:58.709 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 03:02:58.709 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 03:02:58.710 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 03:02:58.737 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 03:02:58.737 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:02:58.737 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:02:58.737 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:02:58.737 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 03:02:58.737 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 03:02:58.737 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 03:02:58.737 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 03:02:58.738 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.28.20:5700) Recv POWEROFF cmd
2026-01-29 03:02:58.738 [INFO] ctrl_if_trx.py:117 (BTS@172.18.28.20:5700) Stopping transceiver...
2026-01-29 03:02:58.738 [INFO] transceiver.py:246 Stopping clock generator
2026-01-29 03:02:58.738 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=121 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:02:58.738 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=121 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:02:58.738 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=121 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:02:58.738 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=121 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:02:58.738 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=121 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:02:58.738 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=121 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:02:58.738 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=121 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:03:03.740 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.28.20:5700) Recv POWEROFF cmd
2026-01-29 03:03:03.741 [INFO] ctrl_if_trx.py:117 (BTS@172.18.28.20:5700) Stopping transceiver...
2026-01-29 03:03:03.742 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 03:03:03.745 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 03:03:03.745 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 03:03:03.745 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 03:03:03.752 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 03:03:03.752 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.28.20:5700) Recv SETFORMAT cmd
2026-01-29 03:03:03.752 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.28.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:03:03.753 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.28.20:5700) Recv SETFORMAT cmd
2026-01-29 03:03:03.753 [INFO] ctrl_if_trx.py:201 (BTS@172.18.28.20:5700) TRXD header version 1 -> 1
2026-01-29 03:03:03.755 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.28.20:5700/1) Recv RXTUNE cmd
2026-01-29 03:03:03.755 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.28.20:5700/1) Recv TXTUNE cmd
2026-01-29 03:03:03.756 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.28.20:5700/1) Recv SETFORMAT cmd
2026-01-29 03:03:03.756 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.28.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:03:03.756 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 03:03:03.757 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.28.20:5700/1) Recv NOMTXPOWER cmd
2026-01-29 03:03:03.757 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.28.20:5700/1) Recv SETFORMAT cmd
2026-01-29 03:03:03.757 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.28.20:5700/1) TRXD header version 1 -> 1
2026-01-29 03:03:03.758 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.28.20:5700/2) Recv RXTUNE cmd
2026-01-29 03:03:03.758 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.28.20:5700/2) Recv TXTUNE cmd
2026-01-29 03:03:03.758 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.28.20:5700/2) Recv SETFORMAT cmd
2026-01-29 03:03:03.758 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.28.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:03:03.758 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 03:03:03.758 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.28.20:5700/2) Recv NOMTXPOWER cmd
2026-01-29 03:03:03.759 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.28.20:5700/2) Recv SETFORMAT cmd
2026-01-29 03:03:03.759 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.28.20:5700/2) TRXD header version 1 -> 1
2026-01-29 03:03:03.760 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.28.20:5700/3) Recv RXTUNE cmd
2026-01-29 03:03:03.760 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.28.20:5700/3) Recv TXTUNE cmd
2026-01-29 03:03:03.760 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.28.20:5700/3) Recv SETFORMAT cmd
2026-01-29 03:03:03.760 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.28.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:03:03.760 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 03:03:03.760 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.28.20:5700/3) Recv NOMTXPOWER cmd
2026-01-29 03:03:03.760 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.28.20:5700/3) Recv SETFORMAT cmd
2026-01-29 03:03:03.761 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.28.20:5700/3) TRXD header version 1 -> 1
2026-01-29 03:03:03.763 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.28.20:5700) Recv RXTUNE cmd
2026-01-29 03:03:03.763 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETTSC
2026-01-29 03:03:03.763 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETTSC
2026-01-29 03:03:03.763 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETTSC
2026-01-29 03:03:03.763 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.28.20:5700) Recv TXTUNE cmd
2026-01-29 03:03:03.763 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETRXGAIN
2026-01-29 03:03:03.763 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETRXGAIN
2026-01-29 03:03:03.763 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETRXGAIN
2026-01-29 03:03:03.763 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETTSC
2026-01-29 03:03:03.763 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:03:03.763 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:03:03.763 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:03:03.763 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.28.20:5700) Recv NOMTXPOWER cmd
2026-01-29 03:03:03.763 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:03:03.763 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:03:03.763 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:03:03.763 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.28.20:5700) Recv POWERON CMD
2026-01-29 03:03:03.763 [INFO] ctrl_if_trx.py:109 (BTS@172.18.28.20:5700) Starting transceiver...
2026-01-29 03:03:03.764 [INFO] transceiver.py:243 Starting clock generator
2026-01-29 03:03:03.764 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-01-29 03:03:03.764 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:03:03.764 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:03:03.764 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:03:03.764 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETRXGAIN
2026-01-29 03:03:03.764 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:03:03.764 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:03:03.764 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:03:03.764 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:03:03.764 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:03:03.764 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:03:03.764 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:03:03.764 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:03:03.764 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:03:03.764 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:03:03.764 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:03:03.764 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:03:03.764 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:03:03.764 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:03:03.765 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:03:03.765 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:03:03.765 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:03:03.765 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:03:03.765 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:03:03.765 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:03:03.765 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:03:03.765 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:03:03.765 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:03:03.769 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-01-29 03:03:04.252 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-01-29 03:03:04.294 [DEBUG] fake_trx.py:278 (BTS@172.18.28.20:5700) Recv FAKE_TOA cmd
2026-01-29 03:03:04.296 [DEBUG] fake_trx.py:297 (BTS@172.18.28.20:5700) Recv FAKE_RSSI cmd
2026-01-29 03:03:04.298 [DEBUG] fake_trx.py:322 (BTS@172.18.28.20:5700) Recv FAKE_CI cmd
2026-01-29 03:03:04.298 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:03:04.321 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 03:03:04.321 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 03:03:04.322 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 03:03:04.342 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 03:03:04.342 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:03:04.343 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:03:04.343 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:03:04.346 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 03:03:04.346 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 03:03:04.346 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 03:03:04.347 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 03:03:04.347 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.28.20:5700) Recv POWEROFF cmd
2026-01-29 03:03:04.347 [INFO] ctrl_if_trx.py:117 (BTS@172.18.28.20:5700) Stopping transceiver...
2026-01-29 03:03:04.347 [INFO] transceiver.py:246 Stopping clock generator
2026-01-29 03:03:04.347 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=123 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:03:04.347 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=123 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:03:04.348 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=123 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:03:04.348 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=123 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:03:04.348 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=123 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:03:04.348 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=123 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:03:04.348 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=123 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:03:04.348 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=124 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:03:04.348 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=124 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:03:04.348 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=124 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:03:04.348 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=124 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:03:04.348 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=124 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:03:04.348 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=124 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:03:04.349 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=124 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:03:04.349 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=124 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:03:09.346 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.28.20:5700) Recv POWEROFF cmd
2026-01-29 03:03:09.346 [INFO] ctrl_if_trx.py:117 (BTS@172.18.28.20:5700) Stopping transceiver...
2026-01-29 03:03:09.349 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 03:03:09.349 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 03:03:09.349 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 03:03:09.349 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 03:03:09.361 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 03:03:09.362 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.28.20:5700) Recv SETFORMAT cmd
2026-01-29 03:03:09.362 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.28.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:03:09.363 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.28.20:5700) Recv SETFORMAT cmd
2026-01-29 03:03:09.363 [INFO] ctrl_if_trx.py:201 (BTS@172.18.28.20:5700) TRXD header version 1 -> 1
2026-01-29 03:03:09.366 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.28.20:5700/1) Recv RXTUNE cmd
2026-01-29 03:03:09.367 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.28.20:5700/1) Recv TXTUNE cmd
2026-01-29 03:03:09.367 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.28.20:5700/1) Recv SETFORMAT cmd
2026-01-29 03:03:09.367 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.28.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:03:09.367 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 03:03:09.367 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.28.20:5700/1) Recv NOMTXPOWER cmd
2026-01-29 03:03:09.367 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.28.20:5700/1) Recv SETFORMAT cmd
2026-01-29 03:03:09.367 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.28.20:5700/1) TRXD header version 1 -> 1
2026-01-29 03:03:09.370 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.28.20:5700/2) Recv RXTUNE cmd
2026-01-29 03:03:09.370 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.28.20:5700/2) Recv TXTUNE cmd
2026-01-29 03:03:09.370 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.28.20:5700/2) Recv SETFORMAT cmd
2026-01-29 03:03:09.370 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.28.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:03:09.371 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 03:03:09.371 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.28.20:5700/2) Recv NOMTXPOWER cmd
2026-01-29 03:03:09.371 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.28.20:5700/2) Recv SETFORMAT cmd
2026-01-29 03:03:09.371 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.28.20:5700/2) TRXD header version 1 -> 1
2026-01-29 03:03:09.372 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.28.20:5700/3) Recv RXTUNE cmd
2026-01-29 03:03:09.372 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.28.20:5700/3) Recv TXTUNE cmd
2026-01-29 03:03:09.372 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.28.20:5700/3) Recv SETFORMAT cmd
2026-01-29 03:03:09.372 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.28.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:03:09.373 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 03:03:09.373 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.28.20:5700/3) Recv NOMTXPOWER cmd
2026-01-29 03:03:09.373 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.28.20:5700/3) Recv SETFORMAT cmd
2026-01-29 03:03:09.373 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.28.20:5700/3) TRXD header version 1 -> 1
2026-01-29 03:03:09.375 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.28.20:5700) Recv RXTUNE cmd
2026-01-29 03:03:09.375 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETTSC
2026-01-29 03:03:09.375 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETTSC
2026-01-29 03:03:09.375 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETTSC
2026-01-29 03:03:09.375 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.28.20:5700) Recv TXTUNE cmd
2026-01-29 03:03:09.375 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETRXGAIN
2026-01-29 03:03:09.375 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETRXGAIN
2026-01-29 03:03:09.375 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETRXGAIN
2026-01-29 03:03:09.375 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETTSC
2026-01-29 03:03:09.375 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:03:09.375 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:03:09.375 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.28.20:5700) Recv NOMTXPOWER cmd
2026-01-29 03:03:09.375 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:03:09.375 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:03:09.375 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:03:09.375 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.28.20:5700) Recv POWERON CMD
2026-01-29 03:03:09.375 [INFO] ctrl_if_trx.py:109 (BTS@172.18.28.20:5700) Starting transceiver...
2026-01-29 03:03:09.375 [INFO] transceiver.py:243 Starting clock generator
2026-01-29 03:03:09.375 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-01-29 03:03:09.376 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:03:09.376 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:03:09.376 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:03:09.376 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETRXGAIN
2026-01-29 03:03:09.376 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:03:09.376 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:03:09.376 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:03:09.376 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:03:09.376 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:03:09.376 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:03:09.376 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:03:09.376 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:03:09.376 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:03:09.376 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:03:09.376 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:03:09.376 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:03:09.376 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:03:09.376 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:03:09.376 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:03:09.376 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:03:09.376 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:03:09.376 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:03:09.376 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:03:09.376 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:03:09.376 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:03:09.376 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:03:09.376 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:03:09.376 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:03:09.380 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-01-29 03:03:09.864 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-01-29 03:03:09.903 [DEBUG] fake_trx.py:278 (BTS@172.18.28.20:5700) Recv FAKE_TOA cmd
2026-01-29 03:03:09.906 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:03:09.906 [DEBUG] fake_trx.py:297 (BTS@172.18.28.20:5700) Recv FAKE_RSSI cmd
2026-01-29 03:03:09.908 [DEBUG] fake_trx.py:322 (BTS@172.18.28.20:5700) Recv FAKE_CI cmd
2026-01-29 03:03:09.935 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 03:03:09.935 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 03:03:09.936 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 03:03:09.956 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 03:03:09.957 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:03:09.957 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:03:09.957 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:03:09.960 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 03:03:09.961 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 03:03:09.961 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 03:03:09.961 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 03:03:09.961 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.28.20:5700) Recv POWEROFF cmd
2026-01-29 03:03:09.961 [INFO] ctrl_if_trx.py:117 (BTS@172.18.28.20:5700) Stopping transceiver...
2026-01-29 03:03:09.961 [INFO] transceiver.py:246 Stopping clock generator
2026-01-29 03:03:09.961 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=124 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:03:09.962 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=124 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:03:09.962 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=124 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:03:09.962 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=124 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:03:09.962 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=124 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:03:09.962 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=124 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:03:09.962 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=125 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:03:09.962 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=125 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:03:09.962 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=125 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:03:09.962 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=125 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:03:09.962 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=125 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:03:09.963 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=125 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:03:09.963 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=125 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:03:09.963 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=125 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:03:14.960 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.28.20:5700) Recv POWEROFF cmd
2026-01-29 03:03:14.960 [INFO] ctrl_if_trx.py:117 (BTS@172.18.28.20:5700) Stopping transceiver...
2026-01-29 03:03:14.962 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 03:03:14.963 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 03:03:14.963 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 03:03:14.963 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 03:03:14.971 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 03:03:14.971 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.28.20:5700) Recv SETFORMAT cmd
2026-01-29 03:03:14.971 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.28.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:03:14.971 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.28.20:5700) Recv SETFORMAT cmd
2026-01-29 03:03:14.971 [INFO] ctrl_if_trx.py:201 (BTS@172.18.28.20:5700) TRXD header version 1 -> 1
2026-01-29 03:03:14.973 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.28.20:5700/1) Recv RXTUNE cmd
2026-01-29 03:03:14.973 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.28.20:5700/1) Recv TXTUNE cmd
2026-01-29 03:03:14.974 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.28.20:5700/1) Recv SETFORMAT cmd
2026-01-29 03:03:14.974 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.28.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:03:14.974 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 03:03:14.974 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.28.20:5700/1) Recv NOMTXPOWER cmd
2026-01-29 03:03:14.975 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.28.20:5700/1) Recv SETFORMAT cmd
2026-01-29 03:03:14.975 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.28.20:5700/1) TRXD header version 1 -> 1
2026-01-29 03:03:14.976 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.28.20:5700/2) Recv RXTUNE cmd
2026-01-29 03:03:14.976 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.28.20:5700/2) Recv TXTUNE cmd
2026-01-29 03:03:14.977 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.28.20:5700/2) Recv SETFORMAT cmd
2026-01-29 03:03:14.977 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.28.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:03:14.977 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 03:03:14.977 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.28.20:5700/2) Recv NOMTXPOWER cmd
2026-01-29 03:03:14.977 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.28.20:5700/2) Recv SETFORMAT cmd
2026-01-29 03:03:14.977 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.28.20:5700/2) TRXD header version 1 -> 1
2026-01-29 03:03:14.978 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.28.20:5700/3) Recv RXTUNE cmd
2026-01-29 03:03:14.978 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.28.20:5700/3) Recv TXTUNE cmd
2026-01-29 03:03:14.978 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.28.20:5700/3) Recv SETFORMAT cmd
2026-01-29 03:03:14.979 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.28.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:03:14.979 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 03:03:14.979 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.28.20:5700/3) Recv NOMTXPOWER cmd
2026-01-29 03:03:14.979 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.28.20:5700/3) Recv SETFORMAT cmd
2026-01-29 03:03:14.979 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.28.20:5700/3) TRXD header version 1 -> 1
2026-01-29 03:03:14.981 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.28.20:5700) Recv RXTUNE cmd
2026-01-29 03:03:14.981 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETTSC
2026-01-29 03:03:14.981 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETTSC
2026-01-29 03:03:14.981 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETTSC
2026-01-29 03:03:14.981 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.28.20:5700) Recv TXTUNE cmd
2026-01-29 03:03:14.981 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETRXGAIN
2026-01-29 03:03:14.981 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETRXGAIN
2026-01-29 03:03:14.981 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETRXGAIN
2026-01-29 03:03:14.982 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETTSC
2026-01-29 03:03:14.982 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:03:14.982 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:03:14.982 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.28.20:5700) Recv NOMTXPOWER cmd
2026-01-29 03:03:14.982 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:03:14.982 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:03:14.982 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:03:14.982 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.28.20:5700) Recv POWERON CMD
2026-01-29 03:03:14.982 [INFO] ctrl_if_trx.py:109 (BTS@172.18.28.20:5700) Starting transceiver...
2026-01-29 03:03:14.982 [INFO] transceiver.py:243 Starting clock generator
2026-01-29 03:03:14.982 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-01-29 03:03:14.982 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:03:14.982 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:03:14.982 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:03:14.982 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETRXGAIN
2026-01-29 03:03:14.982 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:03:14.982 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:03:14.982 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:03:14.982 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:03:14.982 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:03:14.982 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:03:14.982 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:03:14.982 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:03:14.982 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:03:14.982 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:03:14.982 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:03:14.983 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:03:14.983 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:03:14.983 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:03:14.983 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:03:14.983 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:03:14.983 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:03:14.983 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:03:14.983 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:03:14.983 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:03:14.983 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:03:14.983 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:03:14.983 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:03:14.983 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:03:14.987 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-01-29 03:03:15.470 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-01-29 03:03:15.512 [DEBUG] fake_trx.py:278 (BTS@172.18.28.20:5700) Recv FAKE_TOA cmd
2026-01-29 03:03:15.514 [DEBUG] fake_trx.py:297 (BTS@172.18.28.20:5700) Recv FAKE_RSSI cmd
2026-01-29 03:03:15.515 [DEBUG] fake_trx.py:322 (BTS@172.18.28.20:5700) Recv FAKE_CI cmd
2026-01-29 03:03:15.515 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:03:15.535 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 03:03:15.535 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 03:03:15.536 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 03:03:15.551 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 03:03:15.551 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 03:03:15.551 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 03:03:15.555 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 03:03:15.555 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:03:15.555 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:03:15.555 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:03:15.556 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 03:03:15.556 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 03:03:15.556 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 03:03:15.556 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.28.20:5700) Recv POWEROFF cmd
2026-01-29 03:03:15.556 [INFO] ctrl_if_trx.py:117 (BTS@172.18.28.20:5700) Stopping transceiver...
2026-01-29 03:03:15.556 [INFO] transceiver.py:246 Stopping clock generator
2026-01-29 03:03:15.557 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 03:03:20.559 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.28.20:5700) Recv POWEROFF cmd
2026-01-29 03:03:20.559 [INFO] ctrl_if_trx.py:117 (BTS@172.18.28.20:5700) Stopping transceiver...
2026-01-29 03:03:20.560 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 03:03:20.562 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 03:03:20.563 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 03:03:20.563 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 03:03:20.570 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 03:03:20.570 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.28.20:5700) Recv SETFORMAT cmd
2026-01-29 03:03:20.570 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.28.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:03:20.570 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.28.20:5700) Recv SETFORMAT cmd
2026-01-29 03:03:20.570 [INFO] ctrl_if_trx.py:201 (BTS@172.18.28.20:5700) TRXD header version 1 -> 1
2026-01-29 03:03:20.572 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.28.20:5700/1) Recv RXTUNE cmd
2026-01-29 03:03:20.572 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.28.20:5700/1) Recv TXTUNE cmd
2026-01-29 03:03:20.572 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.28.20:5700/1) Recv SETFORMAT cmd
2026-01-29 03:03:20.572 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.28.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:03:20.572 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 03:03:20.572 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.28.20:5700/1) Recv NOMTXPOWER cmd
2026-01-29 03:03:20.572 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.28.20:5700/1) Recv SETFORMAT cmd
2026-01-29 03:03:20.572 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.28.20:5700/1) TRXD header version 1 -> 1
2026-01-29 03:03:20.574 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.28.20:5700/2) Recv RXTUNE cmd
2026-01-29 03:03:20.574 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.28.20:5700/2) Recv TXTUNE cmd
2026-01-29 03:03:20.574 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.28.20:5700/2) Recv SETFORMAT cmd
2026-01-29 03:03:20.574 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.28.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:03:20.574 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 03:03:20.574 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.28.20:5700/2) Recv NOMTXPOWER cmd
2026-01-29 03:03:20.574 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.28.20:5700/2) Recv SETFORMAT cmd
2026-01-29 03:03:20.574 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.28.20:5700/2) TRXD header version 1 -> 1
2026-01-29 03:03:20.576 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.28.20:5700/3) Recv RXTUNE cmd
2026-01-29 03:03:20.576 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.28.20:5700/3) Recv TXTUNE cmd
2026-01-29 03:03:20.576 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.28.20:5700/3) Recv SETFORMAT cmd
2026-01-29 03:03:20.576 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.28.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:03:20.576 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 03:03:20.576 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.28.20:5700/3) Recv NOMTXPOWER cmd
2026-01-29 03:03:20.577 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.28.20:5700/3) Recv SETFORMAT cmd
2026-01-29 03:03:20.577 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.28.20:5700/3) TRXD header version 1 -> 1
2026-01-29 03:03:20.580 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.28.20:5700) Recv RXTUNE cmd
2026-01-29 03:03:20.580 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETTSC
2026-01-29 03:03:20.580 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETTSC
2026-01-29 03:03:20.580 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETTSC
2026-01-29 03:03:20.580 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.28.20:5700) Recv TXTUNE cmd
2026-01-29 03:03:20.580 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETRXGAIN
2026-01-29 03:03:20.580 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETRXGAIN
2026-01-29 03:03:20.580 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETRXGAIN
2026-01-29 03:03:20.580 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETTSC
2026-01-29 03:03:20.580 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:03:20.580 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:03:20.580 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:03:20.580 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.28.20:5700) Recv NOMTXPOWER cmd
2026-01-29 03:03:20.580 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:03:20.580 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:03:20.580 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:03:20.580 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.28.20:5700) Recv POWERON CMD
2026-01-29 03:03:20.580 [INFO] ctrl_if_trx.py:109 (BTS@172.18.28.20:5700) Starting transceiver...
2026-01-29 03:03:20.580 [INFO] transceiver.py:243 Starting clock generator
2026-01-29 03:03:20.581 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-01-29 03:03:20.581 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:03:20.581 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:03:20.581 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:03:20.581 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETRXGAIN
2026-01-29 03:03:20.581 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:03:20.581 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:03:20.581 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:03:20.581 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:03:20.582 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:03:20.582 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:03:20.582 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:03:20.582 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:03:20.582 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:03:20.582 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:03:20.582 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:03:20.582 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:03:20.582 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:03:20.582 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:03:20.582 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:03:20.582 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:03:20.582 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:03:20.582 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:03:20.582 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:03:20.582 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:03:20.582 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:03:20.582 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:03:20.582 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:03:20.585 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-01-29 03:03:21.068 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-01-29 03:03:21.113 [DEBUG] fake_trx.py:278 (BTS@172.18.28.20:5700) Recv FAKE_TOA cmd
2026-01-29 03:03:21.115 [DEBUG] fake_trx.py:297 (BTS@172.18.28.20:5700) Recv FAKE_RSSI cmd
2026-01-29 03:03:21.115 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:03:21.116 [DEBUG] fake_trx.py:322 (BTS@172.18.28.20:5700) Recv FAKE_CI cmd
2026-01-29 03:03:21.140 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 03:03:21.140 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 03:03:21.141 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 03:03:21.168 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 03:03:21.168 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 03:03:21.168 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 03:03:21.173 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 03:03:21.173 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:03:21.173 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:03:21.173 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:03:21.174 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 03:03:21.174 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 03:03:21.174 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 03:03:21.174 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 03:03:21.174 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.28.20:5700) Recv POWEROFF cmd
2026-01-29 03:03:21.174 [INFO] ctrl_if_trx.py:117 (BTS@172.18.28.20:5700) Stopping transceiver...
2026-01-29 03:03:21.174 [INFO] transceiver.py:246 Stopping clock generator
2026-01-29 03:03:26.177 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.28.20:5700) Recv POWEROFF cmd
2026-01-29 03:03:26.177 [INFO] ctrl_if_trx.py:117 (BTS@172.18.28.20:5700) Stopping transceiver...
2026-01-29 03:03:26.179 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 03:03:26.180 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 03:03:26.181 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 03:03:26.181 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 03:03:26.186 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 03:03:26.187 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.28.20:5700) Recv SETFORMAT cmd
2026-01-29 03:03:26.187 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.28.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:03:26.188 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.28.20:5700) Recv SETFORMAT cmd
2026-01-29 03:03:26.188 [INFO] ctrl_if_trx.py:201 (BTS@172.18.28.20:5700) TRXD header version 1 -> 1
2026-01-29 03:03:26.190 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.28.20:5700/1) Recv RXTUNE cmd
2026-01-29 03:03:26.190 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.28.20:5700/1) Recv TXTUNE cmd
2026-01-29 03:03:26.191 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.28.20:5700/1) Recv SETFORMAT cmd
2026-01-29 03:03:26.191 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.28.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:03:26.191 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 03:03:26.192 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.28.20:5700/1) Recv NOMTXPOWER cmd
2026-01-29 03:03:26.192 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.28.20:5700/1) Recv SETFORMAT cmd
2026-01-29 03:03:26.192 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.28.20:5700/1) TRXD header version 1 -> 1
2026-01-29 03:03:26.193 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.28.20:5700/2) Recv RXTUNE cmd
2026-01-29 03:03:26.193 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.28.20:5700/2) Recv TXTUNE cmd
2026-01-29 03:03:26.193 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.28.20:5700/2) Recv SETFORMAT cmd
2026-01-29 03:03:26.193 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.28.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:03:26.193 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 03:03:26.193 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.28.20:5700/2) Recv NOMTXPOWER cmd
2026-01-29 03:03:26.193 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.28.20:5700/2) Recv SETFORMAT cmd
2026-01-29 03:03:26.193 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.28.20:5700/2) TRXD header version 1 -> 1
2026-01-29 03:03:26.195 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.28.20:5700/3) Recv RXTUNE cmd
2026-01-29 03:03:26.195 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.28.20:5700/3) Recv TXTUNE cmd
2026-01-29 03:03:26.195 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.28.20:5700/3) Recv SETFORMAT cmd
2026-01-29 03:03:26.195 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.28.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:03:26.195 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 03:03:26.195 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.28.20:5700/3) Recv NOMTXPOWER cmd
2026-01-29 03:03:26.195 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.28.20:5700/3) Recv SETFORMAT cmd
2026-01-29 03:03:26.195 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.28.20:5700/3) TRXD header version 1 -> 1
2026-01-29 03:03:26.197 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.28.20:5700) Recv RXTUNE cmd
2026-01-29 03:03:26.197 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETTSC
2026-01-29 03:03:26.197 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETTSC
2026-01-29 03:03:26.197 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.28.20:5700) Recv TXTUNE cmd
2026-01-29 03:03:26.197 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETTSC
2026-01-29 03:03:26.197 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETRXGAIN
2026-01-29 03:03:26.197 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETRXGAIN
2026-01-29 03:03:26.197 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETTSC
2026-01-29 03:03:26.197 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETRXGAIN
2026-01-29 03:03:26.197 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:03:26.197 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:03:26.198 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.28.20:5700) Recv NOMTXPOWER cmd
2026-01-29 03:03:26.198 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:03:26.198 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:03:26.198 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:03:26.198 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.28.20:5700) Recv POWERON CMD
2026-01-29 03:03:26.198 [INFO] ctrl_if_trx.py:109 (BTS@172.18.28.20:5700) Starting transceiver...
2026-01-29 03:03:26.198 [INFO] transceiver.py:243 Starting clock generator
2026-01-29 03:03:26.198 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-01-29 03:03:26.198 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:03:26.198 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:03:26.198 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:03:26.198 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETRXGAIN
2026-01-29 03:03:26.198 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:03:26.198 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:03:26.198 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:03:26.198 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:03:26.198 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:03:26.198 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:03:26.198 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:03:26.198 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:03:26.198 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:03:26.198 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:03:26.198 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:03:26.198 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:03:26.198 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:03:26.198 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:03:26.198 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:03:26.198 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:03:26.198 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:03:26.198 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:03:26.198 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:03:26.199 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:03:26.199 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:03:26.199 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:03:26.199 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:03:26.199 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:03:26.203 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-01-29 03:03:26.686 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-01-29 03:03:26.726 [DEBUG] fake_trx.py:278 (BTS@172.18.28.20:5700) Recv FAKE_TOA cmd
2026-01-29 03:03:26.729 [DEBUG] fake_trx.py:297 (BTS@172.18.28.20:5700) Recv FAKE_RSSI cmd
2026-01-29 03:03:26.730 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:03:26.732 [DEBUG] fake_trx.py:322 (BTS@172.18.28.20:5700) Recv FAKE_CI cmd
2026-01-29 03:03:26.742 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 03:03:26.742 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 03:03:26.743 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 03:03:26.744 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 03:03:26.744 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 03:03:26.745 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 03:03:26.745 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.28.22:6700) Recv POWERON CMD
2026-01-29 03:03:26.745 [INFO] ctrl_if_trx.py:109 (MS@172.18.28.22:6700) Starting transceiver...
2026-01-29 03:03:27.163 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-01-29 03:03:27.201 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:03:27.201 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:03:27.201 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 03:03:27.201 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:03:27.641 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-01-29 03:03:28.119 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-01-29 03:03:28.201 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:03:28.202 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 03:03:28.202 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:03:28.202 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:03:28.594 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-01-29 03:03:29.063 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-01-29 03:03:29.203 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:03:29.203 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 03:03:29.203 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:03:29.203 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:03:29.536 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-01-29 03:03:30.014 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-01-29 03:03:30.203 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:03:30.203 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 03:03:30.204 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:03:30.204 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:03:30.492 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-01-29 03:03:30.970 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-01-29 03:03:31.205 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:03:31.205 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:03:31.205 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 03:03:31.205 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:03:31.448 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-01-29 03:03:31.926 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-01-29 03:03:32.404 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-01-29 03:03:32.882 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-01-29 03:03:33.360 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-01-29 03:03:33.838 [DEBUG] clck_gen.py:113 IND CLOCK 1632
2026-01-29 03:03:34.316 [DEBUG] clck_gen.py:113 IND CLOCK 1734
2026-01-29 03:03:34.793 [DEBUG] clck_gen.py:113 IND CLOCK 1836
2026-01-29 03:03:35.272 [DEBUG] clck_gen.py:113 IND CLOCK 1938
2026-01-29 03:03:35.750 [DEBUG] clck_gen.py:113 IND CLOCK 2040
2026-01-29 03:03:36.227 [DEBUG] clck_gen.py:113 IND CLOCK 2142
2026-01-29 03:03:36.705 [DEBUG] clck_gen.py:113 IND CLOCK 2244
2026-01-29 03:03:37.183 [DEBUG] clck_gen.py:113 IND CLOCK 2346
2026-01-29 03:03:37.661 [DEBUG] clck_gen.py:113 IND CLOCK 2448
2026-01-29 03:03:38.139 [DEBUG] clck_gen.py:113 IND CLOCK 2550
2026-01-29 03:03:38.616 [DEBUG] clck_gen.py:113 IND CLOCK 2652
2026-01-29 03:03:39.094 [DEBUG] clck_gen.py:113 IND CLOCK 2754
2026-01-29 03:03:39.572 [DEBUG] clck_gen.py:113 IND CLOCK 2856
2026-01-29 03:03:40.050 [DEBUG] clck_gen.py:113 IND CLOCK 2958
2026-01-29 03:03:40.528 [DEBUG] clck_gen.py:113 IND CLOCK 3060
2026-01-29 03:03:41.005 [DEBUG] clck_gen.py:113 IND CLOCK 3162
2026-01-29 03:03:41.483 [DEBUG] clck_gen.py:113 IND CLOCK 3264
2026-01-29 03:03:41.961 [DEBUG] clck_gen.py:113 IND CLOCK 3366
2026-01-29 03:03:42.438 [DEBUG] clck_gen.py:113 IND CLOCK 3468
2026-01-29 03:03:42.916 [DEBUG] clck_gen.py:113 IND CLOCK 3570
2026-01-29 03:03:43.394 [DEBUG] clck_gen.py:113 IND CLOCK 3672
2026-01-29 03:03:43.872 [DEBUG] clck_gen.py:113 IND CLOCK 3774
2026-01-29 03:03:44.349 [DEBUG] clck_gen.py:113 IND CLOCK 3876
2026-01-29 03:03:44.827 [DEBUG] clck_gen.py:113 IND CLOCK 3978
2026-01-29 03:03:45.305 [DEBUG] clck_gen.py:113 IND CLOCK 4080
2026-01-29 03:03:45.783 [DEBUG] clck_gen.py:113 IND CLOCK 4182
2026-01-29 03:03:46.261 [DEBUG] clck_gen.py:113 IND CLOCK 4284
2026-01-29 03:03:46.739 [DEBUG] clck_gen.py:113 IND CLOCK 4386
2026-01-29 03:03:47.218 [DEBUG] clck_gen.py:113 IND CLOCK 4488
2026-01-29 03:03:47.695 [DEBUG] clck_gen.py:113 IND CLOCK 4590
2026-01-29 03:03:48.173 [DEBUG] clck_gen.py:113 IND CLOCK 4692
2026-01-29 03:03:48.651 [DEBUG] clck_gen.py:113 IND CLOCK 4794
2026-01-29 03:03:49.129 [DEBUG] clck_gen.py:113 IND CLOCK 4896
2026-01-29 03:03:49.607 [DEBUG] clck_gen.py:113 IND CLOCK 4998
2026-01-29 03:03:50.085 [DEBUG] clck_gen.py:113 IND CLOCK 5100
2026-01-29 03:03:50.563 [DEBUG] clck_gen.py:113 IND CLOCK 5202
2026-01-29 03:03:51.041 [DEBUG] clck_gen.py:113 IND CLOCK 5304
2026-01-29 03:03:51.519 [DEBUG] clck_gen.py:113 IND CLOCK 5406
2026-01-29 03:03:51.997 [DEBUG] clck_gen.py:113 IND CLOCK 5508
2026-01-29 03:03:52.475 [DEBUG] clck_gen.py:113 IND CLOCK 5610
2026-01-29 03:03:52.953 [DEBUG] clck_gen.py:113 IND CLOCK 5712
2026-01-29 03:03:53.431 [DEBUG] clck_gen.py:113 IND CLOCK 5814
2026-01-29 03:03:53.908 [DEBUG] clck_gen.py:113 IND CLOCK 5916
2026-01-29 03:03:54.387 [DEBUG] clck_gen.py:113 IND CLOCK 6018
2026-01-29 03:03:54.864 [DEBUG] clck_gen.py:113 IND CLOCK 6120
2026-01-29 03:03:55.342 [DEBUG] clck_gen.py:113 IND CLOCK 6222
2026-01-29 03:03:55.820 [DEBUG] clck_gen.py:113 IND CLOCK 6324
2026-01-29 03:03:56.298 [DEBUG] clck_gen.py:113 IND CLOCK 6426
2026-01-29 03:03:56.775 [DEBUG] clck_gen.py:113 IND CLOCK 6528
2026-01-29 03:03:57.253 [DEBUG] clck_gen.py:113 IND CLOCK 6630
2026-01-29 03:03:57.731 [DEBUG] clck_gen.py:113 IND CLOCK 6732
2026-01-29 03:03:58.209 [DEBUG] clck_gen.py:113 IND CLOCK 6834
2026-01-29 03:03:58.687 [DEBUG] clck_gen.py:113 IND CLOCK 6936
2026-01-29 03:03:59.165 [DEBUG] clck_gen.py:113 IND CLOCK 7038
2026-01-29 03:03:59.642 [DEBUG] clck_gen.py:113 IND CLOCK 7140
2026-01-29 03:04:00.120 [DEBUG] clck_gen.py:113 IND CLOCK 7242
2026-01-29 03:04:00.221 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 03:04:00.222 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 03:04:00.226 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 03:04:00.226 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:04:00.226 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:04:00.226 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:04:00.229 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 03:04:00.230 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 03:04:00.230 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 03:04:00.230 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 03:04:00.230 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.28.20:5700) Recv POWEROFF cmd
2026-01-29 03:04:00.230 [INFO] ctrl_if_trx.py:117 (BTS@172.18.28.20:5700) Stopping transceiver...
2026-01-29 03:04:00.230 [INFO] transceiver.py:246 Stopping clock generator
2026-01-29 03:04:00.231 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=7267 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:04:00.231 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=7267 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:04:00.231 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=7267 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:04:00.231 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=7267 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:04:00.231 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=7267 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:04:00.231 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=7267 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:04:00.231 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=7268 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:04:00.232 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=7268 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:04:05.230 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.28.20:5700) Recv POWEROFF cmd
2026-01-29 03:04:05.230 [INFO] ctrl_if_trx.py:117 (BTS@172.18.28.20:5700) Stopping transceiver...
2026-01-29 03:04:05.231 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 03:04:05.232 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 03:04:05.232 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 03:04:05.232 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 03:04:05.235 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 03:04:05.235 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.28.20:5700) Recv SETFORMAT cmd
2026-01-29 03:04:05.236 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.28.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:04:05.236 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.28.20:5700) Recv SETFORMAT cmd
2026-01-29 03:04:05.236 [INFO] ctrl_if_trx.py:201 (BTS@172.18.28.20:5700) TRXD header version 1 -> 1
2026-01-29 03:04:05.236 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.28.20:5700/1) Recv RXTUNE cmd
2026-01-29 03:04:05.236 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.28.20:5700/1) Recv TXTUNE cmd
2026-01-29 03:04:05.236 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.28.20:5700/1) Recv SETFORMAT cmd
2026-01-29 03:04:05.236 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.28.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:04:05.237 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 03:04:05.237 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.28.20:5700/1) Recv NOMTXPOWER cmd
2026-01-29 03:04:05.237 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.28.20:5700/1) Recv SETFORMAT cmd
2026-01-29 03:04:05.237 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.28.20:5700/1) TRXD header version 1 -> 1
2026-01-29 03:04:05.237 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.28.20:5700/2) Recv RXTUNE cmd
2026-01-29 03:04:05.237 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.28.20:5700/2) Recv TXTUNE cmd
2026-01-29 03:04:05.237 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.28.20:5700/2) Recv SETFORMAT cmd
2026-01-29 03:04:05.237 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.28.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:04:05.237 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 03:04:05.237 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.28.20:5700/2) Recv NOMTXPOWER cmd
2026-01-29 03:04:05.237 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.28.20:5700/2) Recv SETFORMAT cmd
2026-01-29 03:04:05.237 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.28.20:5700/2) TRXD header version 1 -> 1
2026-01-29 03:04:05.238 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.28.20:5700/3) Recv RXTUNE cmd
2026-01-29 03:04:05.238 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.28.20:5700/3) Recv TXTUNE cmd
2026-01-29 03:04:05.238 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.28.20:5700/3) Recv SETFORMAT cmd
2026-01-29 03:04:05.238 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.28.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:04:05.238 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 03:04:05.238 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.28.20:5700/3) Recv NOMTXPOWER cmd
2026-01-29 03:04:05.238 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.28.20:5700/3) Recv SETFORMAT cmd
2026-01-29 03:04:05.238 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.28.20:5700/3) TRXD header version 1 -> 1
2026-01-29 03:04:05.239 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.28.20:5700) Recv RXTUNE cmd
2026-01-29 03:04:05.239 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETTSC
2026-01-29 03:04:05.239 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETTSC
2026-01-29 03:04:05.239 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETTSC
2026-01-29 03:04:05.239 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.28.20:5700) Recv TXTUNE cmd
2026-01-29 03:04:05.239 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETRXGAIN
2026-01-29 03:04:05.239 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETRXGAIN
2026-01-29 03:04:05.239 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETRXGAIN
2026-01-29 03:04:05.239 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETTSC
2026-01-29 03:04:05.239 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:04:05.239 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:04:05.239 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:04:05.239 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.28.20:5700) Recv NOMTXPOWER cmd
2026-01-29 03:04:05.240 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:04:05.240 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:04:05.240 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:04:05.240 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.28.20:5700) Recv POWERON CMD
2026-01-29 03:04:05.240 [INFO] ctrl_if_trx.py:109 (BTS@172.18.28.20:5700) Starting transceiver...
2026-01-29 03:04:05.240 [INFO] transceiver.py:243 Starting clock generator
2026-01-29 03:04:05.240 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-01-29 03:04:05.240 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:04:05.240 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:04:05.240 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:04:05.240 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETRXGAIN
2026-01-29 03:04:05.240 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:04:05.240 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:04:05.240 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:04:05.240 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:04:05.240 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:04:05.240 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:04:05.240 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:04:05.240 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:04:05.240 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:04:05.240 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:04:05.240 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:04:05.240 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:04:05.240 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:04:05.240 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:04:05.240 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:04:05.240 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:04:05.240 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:04:05.240 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:04:05.240 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:04:05.240 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:04:05.240 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:04:05.240 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:04:05.240 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:04:05.244 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-01-29 03:04:05.727 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-01-29 03:04:05.764 [DEBUG] fake_trx.py:278 (BTS@172.18.28.20:5700) Recv FAKE_TOA cmd
2026-01-29 03:04:05.766 [DEBUG] fake_trx.py:297 (BTS@172.18.28.20:5700) Recv FAKE_RSSI cmd
2026-01-29 03:04:05.768 [DEBUG] fake_trx.py:322 (BTS@172.18.28.20:5700) Recv FAKE_CI cmd
2026-01-29 03:04:05.769 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:04:06.204 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-01-29 03:04:06.242 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:04:06.242 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 03:04:06.243 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:04:06.245 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:04:06.685 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-01-29 03:04:07.164 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-01-29 03:04:07.243 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:04:07.243 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 03:04:07.244 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:04:07.246 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:04:07.645 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-01-29 03:04:08.126 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-01-29 03:04:08.244 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:04:08.245 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:04:08.245 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 03:04:08.247 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:04:08.606 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-01-29 03:04:08.789 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:04:08.794 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 03:04:08.794 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:04:08.794 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:04:08.794 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:04:08.797 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 03:04:08.797 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 03:04:08.797 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 03:04:08.797 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 03:04:08.797 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.28.20:5700) Recv POWEROFF cmd
2026-01-29 03:04:08.797 [INFO] ctrl_if_trx.py:117 (BTS@172.18.28.20:5700) Stopping transceiver...
2026-01-29 03:04:08.797 [INFO] transceiver.py:246 Stopping clock generator
2026-01-29 03:04:08.797 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=757 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:04:08.797 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=757 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:04:08.797 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=757 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:04:08.797 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=757 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:04:08.797 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=757 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:04:08.797 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=757 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:04:13.798 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.28.20:5700) Recv POWEROFF cmd
2026-01-29 03:04:13.798 [INFO] ctrl_if_trx.py:117 (BTS@172.18.28.20:5700) Stopping transceiver...
2026-01-29 03:04:13.799 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 03:04:13.801 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 03:04:13.802 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 03:04:13.802 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 03:04:13.810 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 03:04:13.812 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.28.20:5700) Recv SETFORMAT cmd
2026-01-29 03:04:13.812 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.28.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:04:13.813 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.28.20:5700) Recv SETFORMAT cmd
2026-01-29 03:04:13.813 [INFO] ctrl_if_trx.py:201 (BTS@172.18.28.20:5700) TRXD header version 1 -> 1
2026-01-29 03:04:13.816 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.28.20:5700/1) Recv RXTUNE cmd
2026-01-29 03:04:13.816 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.28.20:5700/1) Recv TXTUNE cmd
2026-01-29 03:04:13.816 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.28.20:5700/1) Recv SETFORMAT cmd
2026-01-29 03:04:13.816 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.28.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:04:13.816 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 03:04:13.816 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.28.20:5700/1) Recv NOMTXPOWER cmd
2026-01-29 03:04:13.816 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.28.20:5700/1) Recv SETFORMAT cmd
2026-01-29 03:04:13.816 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.28.20:5700/1) TRXD header version 1 -> 1
2026-01-29 03:04:13.819 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.28.20:5700/2) Recv RXTUNE cmd
2026-01-29 03:04:13.819 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.28.20:5700/2) Recv TXTUNE cmd
2026-01-29 03:04:13.819 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.28.20:5700/2) Recv SETFORMAT cmd
2026-01-29 03:04:13.819 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.28.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:04:13.819 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 03:04:13.819 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.28.20:5700/2) Recv NOMTXPOWER cmd
2026-01-29 03:04:13.820 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.28.20:5700/2) Recv SETFORMAT cmd
2026-01-29 03:04:13.820 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.28.20:5700/2) TRXD header version 1 -> 1
2026-01-29 03:04:13.822 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.28.20:5700/3) Recv RXTUNE cmd
2026-01-29 03:04:13.822 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.28.20:5700/3) Recv TXTUNE cmd
2026-01-29 03:04:13.822 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.28.20:5700/3) Recv SETFORMAT cmd
2026-01-29 03:04:13.822 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.28.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:04:13.822 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 03:04:13.822 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.28.20:5700/3) Recv NOMTXPOWER cmd
2026-01-29 03:04:13.822 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.28.20:5700/3) Recv SETFORMAT cmd
2026-01-29 03:04:13.822 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.28.20:5700/3) TRXD header version 1 -> 1
2026-01-29 03:04:13.825 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.28.20:5700) Recv RXTUNE cmd
2026-01-29 03:04:13.825 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETTSC
2026-01-29 03:04:13.825 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETTSC
2026-01-29 03:04:13.825 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETTSC
2026-01-29 03:04:13.825 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.28.20:5700) Recv TXTUNE cmd
2026-01-29 03:04:13.825 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETRXGAIN
2026-01-29 03:04:13.825 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETRXGAIN
2026-01-29 03:04:13.825 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETRXGAIN
2026-01-29 03:04:13.825 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETTSC
2026-01-29 03:04:13.825 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:04:13.825 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:04:13.825 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.28.20:5700) Recv NOMTXPOWER cmd
2026-01-29 03:04:13.825 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:04:13.825 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:04:13.825 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:04:13.825 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.28.20:5700) Recv POWERON CMD
2026-01-29 03:04:13.825 [INFO] ctrl_if_trx.py:109 (BTS@172.18.28.20:5700) Starting transceiver...
2026-01-29 03:04:13.825 [INFO] transceiver.py:243 Starting clock generator
2026-01-29 03:04:13.826 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-01-29 03:04:13.826 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:04:13.826 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:04:13.826 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:04:13.826 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETRXGAIN
2026-01-29 03:04:13.826 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:04:13.826 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:04:13.826 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:04:13.826 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:04:13.826 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:04:13.826 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:04:13.826 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:04:13.826 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:04:13.826 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:04:13.826 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:04:13.826 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:04:13.827 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:04:13.827 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:04:13.827 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:04:13.827 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:04:13.827 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:04:13.827 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:04:13.827 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:04:13.827 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:04:13.827 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:04:13.827 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:04:13.827 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:04:13.827 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:04:13.827 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:04:13.830 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-01-29 03:04:14.314 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-01-29 03:04:14.352 [DEBUG] fake_trx.py:278 (BTS@172.18.28.20:5700) Recv FAKE_TOA cmd
2026-01-29 03:04:14.354 [DEBUG] fake_trx.py:297 (BTS@172.18.28.20:5700) Recv FAKE_RSSI cmd
2026-01-29 03:04:14.356 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:04:14.357 [DEBUG] fake_trx.py:322 (BTS@172.18.28.20:5700) Recv FAKE_CI cmd
2026-01-29 03:04:14.792 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-01-29 03:04:14.829 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:04:14.830 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 03:04:14.830 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:04:14.833 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:04:15.273 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-01-29 03:04:15.752 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-01-29 03:04:15.831 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:04:15.831 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 03:04:15.831 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:04:15.835 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:04:16.233 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-01-29 03:04:16.715 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-01-29 03:04:16.832 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:04:16.833 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 03:04:16.833 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:04:16.837 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:04:17.195 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-01-29 03:04:17.676 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-01-29 03:04:17.834 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 03:04:17.834 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:04:17.834 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:04:17.838 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:04:18.158 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-01-29 03:04:18.639 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-01-29 03:04:18.835 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:04:18.835 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 03:04:18.835 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:04:18.839 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:04:19.120 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-01-29 03:04:19.601 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-01-29 03:04:20.080 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-01-29 03:04:20.371 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 03:04:20.372 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:04:20.372 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:04:20.372 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:04:20.375 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 03:04:20.375 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 03:04:20.375 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 03:04:20.375 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 03:04:20.375 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.28.20:5700) Recv POWEROFF cmd
2026-01-29 03:04:20.375 [INFO] ctrl_if_trx.py:117 (BTS@172.18.28.20:5700) Stopping transceiver...
2026-01-29 03:04:20.375 [INFO] transceiver.py:246 Stopping clock generator
2026-01-29 03:04:25.374 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.28.20:5700) Recv POWEROFF cmd
2026-01-29 03:04:25.374 [INFO] ctrl_if_trx.py:117 (BTS@172.18.28.20:5700) Stopping transceiver...
2026-01-29 03:04:25.377 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 03:04:25.377 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 03:04:25.377 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 03:04:25.377 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 03:04:25.386 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 03:04:25.387 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.28.20:5700) Recv SETFORMAT cmd
2026-01-29 03:04:25.387 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.28.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:04:25.388 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.28.20:5700) Recv SETFORMAT cmd
2026-01-29 03:04:25.388 [INFO] ctrl_if_trx.py:201 (BTS@172.18.28.20:5700) TRXD header version 1 -> 1
2026-01-29 03:04:25.393 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.28.20:5700/1) Recv RXTUNE cmd
2026-01-29 03:04:25.393 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.28.20:5700/1) Recv TXTUNE cmd
2026-01-29 03:04:25.393 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.28.20:5700/1) Recv SETFORMAT cmd
2026-01-29 03:04:25.393 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.28.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:04:25.393 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 03:04:25.393 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.28.20:5700/1) Recv NOMTXPOWER cmd
2026-01-29 03:04:25.394 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.28.20:5700/1) Recv SETFORMAT cmd
2026-01-29 03:04:25.394 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.28.20:5700/1) TRXD header version 1 -> 1
2026-01-29 03:04:25.396 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.28.20:5700/2) Recv RXTUNE cmd
2026-01-29 03:04:25.396 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.28.20:5700/2) Recv TXTUNE cmd
2026-01-29 03:04:25.397 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.28.20:5700/2) Recv SETFORMAT cmd
2026-01-29 03:04:25.397 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.28.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:04:25.397 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 03:04:25.397 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.28.20:5700/2) Recv NOMTXPOWER cmd
2026-01-29 03:04:25.397 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.28.20:5700/2) Recv SETFORMAT cmd
2026-01-29 03:04:25.397 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.28.20:5700/2) TRXD header version 1 -> 1
2026-01-29 03:04:25.399 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.28.20:5700/3) Recv RXTUNE cmd
2026-01-29 03:04:25.399 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.28.20:5700/3) Recv TXTUNE cmd
2026-01-29 03:04:25.399 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.28.20:5700/3) Recv SETFORMAT cmd
2026-01-29 03:04:25.399 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.28.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:04:25.399 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 03:04:25.399 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.28.20:5700/3) Recv NOMTXPOWER cmd
2026-01-29 03:04:25.399 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.28.20:5700/3) Recv SETFORMAT cmd
2026-01-29 03:04:25.399 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.28.20:5700/3) TRXD header version 1 -> 1
2026-01-29 03:04:25.402 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.28.20:5700) Recv RXTUNE cmd
2026-01-29 03:04:25.402 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETTSC
2026-01-29 03:04:25.402 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETTSC
2026-01-29 03:04:25.402 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETTSC
2026-01-29 03:04:25.402 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.28.20:5700) Recv TXTUNE cmd
2026-01-29 03:04:25.402 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETRXGAIN
2026-01-29 03:04:25.402 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETRXGAIN
2026-01-29 03:04:25.402 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETRXGAIN
2026-01-29 03:04:25.402 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETTSC
2026-01-29 03:04:25.402 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:04:25.402 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:04:25.402 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.28.20:5700) Recv NOMTXPOWER cmd
2026-01-29 03:04:25.402 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:04:25.402 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:04:25.402 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:04:25.402 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.28.20:5700) Recv POWERON CMD
2026-01-29 03:04:25.402 [INFO] ctrl_if_trx.py:109 (BTS@172.18.28.20:5700) Starting transceiver...
2026-01-29 03:04:25.402 [INFO] transceiver.py:243 Starting clock generator
2026-01-29 03:04:25.402 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-01-29 03:04:25.402 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:04:25.403 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:04:25.403 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:04:25.403 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETRXGAIN
2026-01-29 03:04:25.403 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:04:25.403 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:04:25.403 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:04:25.403 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:04:25.403 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:04:25.403 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:04:25.403 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:04:25.403 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:04:25.403 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:04:25.403 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:04:25.403 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:04:25.403 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:04:25.403 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:04:25.403 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:04:25.403 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:04:25.403 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:04:25.403 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:04:25.403 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:04:25.403 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:04:25.403 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:04:25.403 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:04:25.403 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:04:25.403 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:04:25.403 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:04:25.407 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-01-29 03:04:25.891 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-01-29 03:04:25.930 [DEBUG] fake_trx.py:278 (BTS@172.18.28.20:5700) Recv FAKE_TOA cmd
2026-01-29 03:04:25.932 [DEBUG] fake_trx.py:297 (BTS@172.18.28.20:5700) Recv FAKE_RSSI cmd
2026-01-29 03:04:25.933 [DEBUG] fake_trx.py:322 (BTS@172.18.28.20:5700) Recv FAKE_CI cmd
2026-01-29 03:04:25.934 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:04:26.368 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-01-29 03:04:26.405 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:04:26.405 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 03:04:26.405 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:04:26.408 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:04:26.846 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-01-29 03:04:27.326 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-01-29 03:04:27.406 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 03:04:27.406 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:04:27.406 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:04:27.409 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:04:27.808 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-01-29 03:04:28.289 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-01-29 03:04:28.407 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 03:04:28.407 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:04:28.407 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:04:28.410 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:04:28.768 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-01-29 03:04:29.249 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-01-29 03:04:29.408 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:04:29.408 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 03:04:29.408 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:04:29.411 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:04:29.728 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-01-29 03:04:30.206 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-01-29 03:04:30.409 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 03:04:30.409 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:04:30.409 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:04:30.412 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:04:30.685 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-01-29 03:04:31.163 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-01-29 03:04:31.641 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-01-29 03:04:31.948 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 03:04:31.948 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:04:31.948 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:04:31.948 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:04:31.950 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 03:04:31.950 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 03:04:31.950 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 03:04:31.950 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 03:04:31.950 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.28.20:5700) Recv POWEROFF cmd
2026-01-29 03:04:31.950 [INFO] ctrl_if_trx.py:117 (BTS@172.18.28.20:5700) Stopping transceiver...
2026-01-29 03:04:31.950 [INFO] transceiver.py:246 Stopping clock generator
2026-01-29 03:04:36.947 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.28.20:5700) Recv POWEROFF cmd
2026-01-29 03:04:36.947 [INFO] ctrl_if_trx.py:117 (BTS@172.18.28.20:5700) Stopping transceiver...
2026-01-29 03:04:36.948 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 03:04:36.948 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 03:04:36.948 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 03:04:36.949 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 03:04:36.952 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 03:04:36.952 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.28.20:5700) Recv SETFORMAT cmd
2026-01-29 03:04:36.952 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.28.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:04:36.952 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.28.20:5700) Recv SETFORMAT cmd
2026-01-29 03:04:36.952 [INFO] ctrl_if_trx.py:201 (BTS@172.18.28.20:5700) TRXD header version 1 -> 1
2026-01-29 03:04:36.953 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.28.20:5700/1) Recv RXTUNE cmd
2026-01-29 03:04:36.953 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.28.20:5700/1) Recv TXTUNE cmd
2026-01-29 03:04:36.953 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.28.20:5700/1) Recv SETFORMAT cmd
2026-01-29 03:04:36.953 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.28.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:04:36.953 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 03:04:36.953 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.28.20:5700/1) Recv NOMTXPOWER cmd
2026-01-29 03:04:36.953 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.28.20:5700/1) Recv SETFORMAT cmd
2026-01-29 03:04:36.953 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.28.20:5700/1) TRXD header version 1 -> 1
2026-01-29 03:04:36.954 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.28.20:5700/2) Recv RXTUNE cmd
2026-01-29 03:04:36.954 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.28.20:5700/2) Recv TXTUNE cmd
2026-01-29 03:04:36.954 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.28.20:5700/2) Recv SETFORMAT cmd
2026-01-29 03:04:36.954 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.28.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:04:36.954 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 03:04:36.954 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.28.20:5700/2) Recv NOMTXPOWER cmd
2026-01-29 03:04:36.954 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.28.20:5700/2) Recv SETFORMAT cmd
2026-01-29 03:04:36.954 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.28.20:5700/2) TRXD header version 1 -> 1
2026-01-29 03:04:36.954 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.28.20:5700/3) Recv RXTUNE cmd
2026-01-29 03:04:36.954 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.28.20:5700/3) Recv TXTUNE cmd
2026-01-29 03:04:36.955 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.28.20:5700/3) Recv SETFORMAT cmd
2026-01-29 03:04:36.955 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.28.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:04:36.955 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 03:04:36.955 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.28.20:5700/3) Recv NOMTXPOWER cmd
2026-01-29 03:04:36.955 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.28.20:5700/3) Recv SETFORMAT cmd
2026-01-29 03:04:36.955 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.28.20:5700/3) TRXD header version 1 -> 1
2026-01-29 03:04:36.956 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.28.20:5700) Recv RXTUNE cmd
2026-01-29 03:04:36.956 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETTSC
2026-01-29 03:04:36.956 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETTSC
2026-01-29 03:04:36.956 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.28.20:5700) Recv TXTUNE cmd
2026-01-29 03:04:36.956 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETTSC
2026-01-29 03:04:36.956 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETRXGAIN
2026-01-29 03:04:36.956 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETRXGAIN
2026-01-29 03:04:36.956 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETTSC
2026-01-29 03:04:36.956 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETRXGAIN
2026-01-29 03:04:36.956 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:04:36.956 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:04:36.956 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.28.20:5700) Recv NOMTXPOWER cmd
2026-01-29 03:04:36.956 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:04:36.956 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:04:36.956 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:04:36.956 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.28.20:5700) Recv POWERON CMD
2026-01-29 03:04:36.956 [INFO] ctrl_if_trx.py:109 (BTS@172.18.28.20:5700) Starting transceiver...
2026-01-29 03:04:36.956 [INFO] transceiver.py:243 Starting clock generator
2026-01-29 03:04:36.956 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-01-29 03:04:36.956 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:04:36.956 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:04:36.956 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:04:36.956 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETRXGAIN
2026-01-29 03:04:36.956 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:04:36.956 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:04:36.956 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:04:36.956 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:04:36.956 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:04:36.957 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:04:36.957 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:04:36.957 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:04:36.957 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:04:36.957 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:04:36.957 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:04:36.957 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:04:36.957 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:04:36.957 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:04:36.957 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:04:36.957 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:04:36.957 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:04:36.957 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:04:36.957 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:04:36.957 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:04:36.957 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:04:36.957 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:04:36.957 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:04:36.957 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:04:36.961 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-01-29 03:04:37.431 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-01-29 03:04:37.470 [DEBUG] fake_trx.py:278 (BTS@172.18.28.20:5700) Recv FAKE_TOA cmd
2026-01-29 03:04:37.470 [DEBUG] fake_trx.py:297 (BTS@172.18.28.20:5700) Recv FAKE_RSSI cmd
2026-01-29 03:04:37.471 [DEBUG] fake_trx.py:322 (BTS@172.18.28.20:5700) Recv FAKE_CI cmd
2026-01-29 03:04:37.471 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:04:37.899 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-01-29 03:04:37.958 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 03:04:37.959 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:04:37.959 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:04:37.961 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:04:38.366 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-01-29 03:04:38.833 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-01-29 03:04:38.959 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 03:04:38.959 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:04:38.959 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:04:38.961 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:04:39.301 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-01-29 03:04:39.768 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-01-29 03:04:39.959 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:04:39.959 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 03:04:39.959 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:04:39.962 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:04:40.235 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-01-29 03:04:40.702 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-01-29 03:04:40.960 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:04:40.960 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 03:04:40.960 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:04:40.962 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:04:41.170 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-01-29 03:04:41.637 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-01-29 03:04:41.960 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:04:41.960 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 03:04:41.960 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:04:41.962 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:04:42.104 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-01-29 03:04:42.571 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-01-29 03:04:43.038 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-01-29 03:04:43.474 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 03:04:43.474 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:04:43.474 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:04:43.474 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:04:43.476 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 03:04:43.476 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 03:04:43.477 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.28.20:5700) Recv POWEROFF cmd
2026-01-29 03:04:43.477 [INFO] ctrl_if_trx.py:117 (BTS@172.18.28.20:5700) Stopping transceiver...
2026-01-29 03:04:43.477 [INFO] transceiver.py:246 Stopping clock generator
2026-01-29 03:04:43.477 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 03:04:43.477 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 03:04:43.477 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=1423 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:04:43.477 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=1423 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:04:43.477 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=1423 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:04:43.477 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=1423 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:04:43.477 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=1423 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:04:43.477 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=1423 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:04:43.477 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=1423 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:04:48.476 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.28.20:5700) Recv POWEROFF cmd
2026-01-29 03:04:48.476 [INFO] ctrl_if_trx.py:117 (BTS@172.18.28.20:5700) Stopping transceiver...
2026-01-29 03:04:48.476 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 03:04:48.476 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 03:04:48.477 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 03:04:48.478 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 03:04:48.481 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 03:04:48.482 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.28.20:5700) Recv SETFORMAT cmd
2026-01-29 03:04:48.482 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.28.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:04:48.482 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.28.20:5700) Recv SETFORMAT cmd
2026-01-29 03:04:48.482 [INFO] ctrl_if_trx.py:201 (BTS@172.18.28.20:5700) TRXD header version 1 -> 1
2026-01-29 03:04:48.483 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.28.20:5700/1) Recv RXTUNE cmd
2026-01-29 03:04:48.483 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.28.20:5700/1) Recv TXTUNE cmd
2026-01-29 03:04:48.483 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.28.20:5700/1) Recv SETFORMAT cmd
2026-01-29 03:04:48.483 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.28.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:04:48.483 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 03:04:48.483 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.28.20:5700/1) Recv NOMTXPOWER cmd
2026-01-29 03:04:48.483 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.28.20:5700/1) Recv SETFORMAT cmd
2026-01-29 03:04:48.483 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.28.20:5700/1) TRXD header version 1 -> 1
2026-01-29 03:04:48.484 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.28.20:5700/2) Recv RXTUNE cmd
2026-01-29 03:04:48.484 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.28.20:5700/2) Recv TXTUNE cmd
2026-01-29 03:04:48.484 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.28.20:5700/2) Recv SETFORMAT cmd
2026-01-29 03:04:48.484 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.28.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:04:48.484 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 03:04:48.484 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.28.20:5700/2) Recv NOMTXPOWER cmd
2026-01-29 03:04:48.484 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.28.20:5700/2) Recv SETFORMAT cmd
2026-01-29 03:04:48.484 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.28.20:5700/2) TRXD header version 1 -> 1
2026-01-29 03:04:48.485 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.28.20:5700/3) Recv RXTUNE cmd
2026-01-29 03:04:48.485 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.28.20:5700/3) Recv TXTUNE cmd
2026-01-29 03:04:48.485 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.28.20:5700/3) Recv SETFORMAT cmd
2026-01-29 03:04:48.485 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.28.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:04:48.485 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 03:04:48.486 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.28.20:5700/3) Recv NOMTXPOWER cmd
2026-01-29 03:04:48.486 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.28.20:5700/3) Recv SETFORMAT cmd
2026-01-29 03:04:48.486 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.28.20:5700/3) TRXD header version 1 -> 1
2026-01-29 03:04:48.487 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.28.20:5700) Recv RXTUNE cmd
2026-01-29 03:04:48.487 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETTSC
2026-01-29 03:04:48.487 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETTSC
2026-01-29 03:04:48.487 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.28.20:5700) Recv TXTUNE cmd
2026-01-29 03:04:48.487 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETTSC
2026-01-29 03:04:48.487 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETRXGAIN
2026-01-29 03:04:48.487 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETRXGAIN
2026-01-29 03:04:48.487 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETTSC
2026-01-29 03:04:48.487 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETRXGAIN
2026-01-29 03:04:48.487 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:04:48.487 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:04:48.487 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.28.20:5700) Recv NOMTXPOWER cmd
2026-01-29 03:04:48.487 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:04:48.488 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:04:48.488 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.28.20:5700) Recv POWERON CMD
2026-01-29 03:04:48.488 [INFO] ctrl_if_trx.py:109 (BTS@172.18.28.20:5700) Starting transceiver...
2026-01-29 03:04:48.488 [INFO] transceiver.py:243 Starting clock generator
2026-01-29 03:04:48.488 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-01-29 03:04:48.488 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:04:48.488 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:04:48.488 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:04:48.488 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETRXGAIN
2026-01-29 03:04:48.488 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:04:48.488 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:04:48.488 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:04:48.488 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:04:48.488 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:04:48.488 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:04:48.488 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:04:48.488 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:04:48.488 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:04:48.488 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:04:48.488 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:04:48.488 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:04:48.488 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:04:48.488 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:04:48.488 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:04:48.488 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:04:48.488 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:04:48.488 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:04:48.488 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:04:48.488 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:04:48.489 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:04:48.489 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:04:48.489 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:04:48.489 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:04:48.489 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:04:48.492 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-01-29 03:04:48.962 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-01-29 03:04:49.003 [DEBUG] fake_trx.py:278 (BTS@172.18.28.20:5700) Recv FAKE_TOA cmd
2026-01-29 03:04:49.004 [DEBUG] fake_trx.py:297 (BTS@172.18.28.20:5700) Recv FAKE_RSSI cmd
2026-01-29 03:04:49.004 [DEBUG] fake_trx.py:322 (BTS@172.18.28.20:5700) Recv FAKE_CI cmd
2026-01-29 03:04:49.004 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:04:49.429 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-01-29 03:04:49.490 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 03:04:49.490 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:04:49.491 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:04:49.497 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:04:49.896 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-01-29 03:04:50.363 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-01-29 03:04:50.491 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 03:04:50.491 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:04:50.492 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:04:50.497 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:04:50.830 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-01-29 03:04:51.297 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-01-29 03:04:51.491 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:04:51.491 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 03:04:51.492 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:04:51.498 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:04:51.765 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-01-29 03:04:52.232 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-01-29 03:04:52.492 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 03:04:52.492 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:04:52.492 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:04:52.498 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:04:52.699 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-01-29 03:04:53.022 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:04:53.166 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-01-29 03:04:53.492 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:04:53.493 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 03:04:53.493 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:04:53.499 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:04:53.634 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-01-29 03:04:54.101 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-01-29 03:04:54.568 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-01-29 03:04:55.035 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-01-29 03:04:55.502 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-01-29 03:04:55.970 [DEBUG] clck_gen.py:113 IND CLOCK 1632
2026-01-29 03:04:56.437 [DEBUG] clck_gen.py:113 IND CLOCK 1734
2026-01-29 03:04:56.904 [DEBUG] clck_gen.py:113 IND CLOCK 1836
2026-01-29 03:04:57.025 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 03:04:57.025 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:04:57.025 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:04:57.025 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:04:57.027 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 03:04:57.027 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 03:04:57.027 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 03:04:57.027 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 03:04:57.027 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.28.20:5700) Recv POWEROFF cmd
2026-01-29 03:04:57.027 [INFO] ctrl_if_trx.py:117 (BTS@172.18.28.20:5700) Stopping transceiver...
2026-01-29 03:04:57.027 [INFO] transceiver.py:246 Stopping clock generator
2026-01-29 03:04:57.028 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=1865 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:04:57.028 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=1865 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:04:57.028 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=1865 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:04:57.028 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=1865 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:04:57.028 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=1865 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:05:02.026 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.28.20:5700) Recv POWEROFF cmd
2026-01-29 03:05:02.026 [INFO] ctrl_if_trx.py:117 (BTS@172.18.28.20:5700) Stopping transceiver...
2026-01-29 03:05:02.027 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 03:05:02.027 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 03:05:02.027 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 03:05:02.028 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 03:05:02.034 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 03:05:02.035 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.28.20:5700) Recv SETFORMAT cmd
2026-01-29 03:05:02.035 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.28.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:05:02.035 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.28.20:5700) Recv SETFORMAT cmd
2026-01-29 03:05:02.035 [INFO] ctrl_if_trx.py:201 (BTS@172.18.28.20:5700) TRXD header version 1 -> 1
2026-01-29 03:05:02.036 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.28.20:5700/1) Recv RXTUNE cmd
2026-01-29 03:05:02.036 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.28.20:5700/1) Recv TXTUNE cmd
2026-01-29 03:05:02.036 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.28.20:5700/1) Recv SETFORMAT cmd
2026-01-29 03:05:02.036 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.28.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:05:02.036 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 03:05:02.036 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.28.20:5700/1) Recv NOMTXPOWER cmd
2026-01-29 03:05:02.036 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.28.20:5700/1) Recv SETFORMAT cmd
2026-01-29 03:05:02.036 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.28.20:5700/1) TRXD header version 1 -> 1
2026-01-29 03:05:02.037 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.28.20:5700/2) Recv RXTUNE cmd
2026-01-29 03:05:02.037 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.28.20:5700/2) Recv TXTUNE cmd
2026-01-29 03:05:02.037 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.28.20:5700/2) Recv SETFORMAT cmd
2026-01-29 03:05:02.037 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.28.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:05:02.037 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 03:05:02.037 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.28.20:5700/2) Recv NOMTXPOWER cmd
2026-01-29 03:05:02.037 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.28.20:5700/2) Recv SETFORMAT cmd
2026-01-29 03:05:02.037 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.28.20:5700/2) TRXD header version 1 -> 1
2026-01-29 03:05:02.038 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.28.20:5700/3) Recv RXTUNE cmd
2026-01-29 03:05:02.038 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.28.20:5700/3) Recv TXTUNE cmd
2026-01-29 03:05:02.039 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.28.20:5700/3) Recv SETFORMAT cmd
2026-01-29 03:05:02.039 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.28.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:05:02.039 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 03:05:02.039 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.28.20:5700/3) Recv NOMTXPOWER cmd
2026-01-29 03:05:02.039 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.28.20:5700/3) Recv SETFORMAT cmd
2026-01-29 03:05:02.039 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.28.20:5700/3) TRXD header version 1 -> 1
2026-01-29 03:05:02.041 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.28.20:5700) Recv RXTUNE cmd
2026-01-29 03:05:02.041 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETTSC
2026-01-29 03:05:02.041 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETTSC
2026-01-29 03:05:02.041 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETTSC
2026-01-29 03:05:02.041 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.28.20:5700) Recv TXTUNE cmd
2026-01-29 03:05:02.041 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETRXGAIN
2026-01-29 03:05:02.041 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETRXGAIN
2026-01-29 03:05:02.041 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETRXGAIN
2026-01-29 03:05:02.041 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETTSC
2026-01-29 03:05:02.041 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:05:02.041 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:05:02.041 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.28.20:5700) Recv NOMTXPOWER cmd
2026-01-29 03:05:02.041 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:05:02.041 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:05:02.041 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:05:02.041 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.28.20:5700) Recv POWERON CMD
2026-01-29 03:05:02.041 [INFO] ctrl_if_trx.py:109 (BTS@172.18.28.20:5700) Starting transceiver...
2026-01-29 03:05:02.041 [INFO] transceiver.py:243 Starting clock generator
2026-01-29 03:05:02.041 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-01-29 03:05:02.041 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:05:02.041 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:05:02.041 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:05:02.041 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETRXGAIN
2026-01-29 03:05:02.041 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:05:02.041 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:05:02.041 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:05:02.041 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:05:02.041 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:05:02.041 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:05:02.041 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:05:02.041 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:05:02.041 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:05:02.041 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:05:02.041 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:05:02.041 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:05:02.041 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:05:02.041 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:05:02.041 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:05:02.041 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:05:02.041 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:05:02.041 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:05:02.041 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:05:02.041 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:05:02.041 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:05:02.041 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:05:02.041 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:05:02.041 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:05:02.046 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-01-29 03:05:02.514 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-01-29 03:05:02.559 [DEBUG] fake_trx.py:278 (BTS@172.18.28.20:5700) Recv FAKE_TOA cmd
2026-01-29 03:05:02.559 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:05:02.560 [DEBUG] fake_trx.py:297 (BTS@172.18.28.20:5700) Recv FAKE_RSSI cmd
2026-01-29 03:05:02.560 [DEBUG] fake_trx.py:322 (BTS@172.18.28.20:5700) Recv FAKE_CI cmd
2026-01-29 03:05:02.982 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-01-29 03:05:03.044 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 03:05:03.044 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:05:03.045 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:05:03.047 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:05:03.449 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-01-29 03:05:03.916 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-01-29 03:05:04.044 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:05:04.044 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 03:05:04.046 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:05:04.048 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:05:04.383 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-01-29 03:05:04.850 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-01-29 03:05:05.045 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 03:05:05.045 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:05:05.046 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:05:05.048 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:05:05.317 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-01-29 03:05:05.785 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-01-29 03:05:06.045 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:05:06.045 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 03:05:06.046 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:05:06.048 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:05:06.252 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-01-29 03:05:06.565 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 03:05:06.565 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:05:06.565 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:05:06.565 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:05:06.568 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 03:05:06.568 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 03:05:06.568 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 03:05:06.568 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 03:05:06.569 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.28.20:5700) Recv POWEROFF cmd
2026-01-29 03:05:06.569 [INFO] ctrl_if_trx.py:117 (BTS@172.18.28.20:5700) Stopping transceiver...
2026-01-29 03:05:06.569 [INFO] transceiver.py:246 Stopping clock generator
2026-01-29 03:05:06.569 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=989 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:05:06.569 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=989 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:05:06.569 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=989 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:05:06.569 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=989 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:05:06.569 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=989 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:05:06.569 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=989 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:05:11.566 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.28.20:5700) Recv POWEROFF cmd
2026-01-29 03:05:11.566 [INFO] ctrl_if_trx.py:117 (BTS@172.18.28.20:5700) Stopping transceiver...
2026-01-29 03:05:11.567 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 03:05:11.567 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 03:05:11.567 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 03:05:11.567 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 03:05:11.570 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 03:05:11.570 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.28.20:5700) Recv SETFORMAT cmd
2026-01-29 03:05:11.570 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.28.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:05:11.570 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.28.20:5700) Recv SETFORMAT cmd
2026-01-29 03:05:11.570 [INFO] ctrl_if_trx.py:201 (BTS@172.18.28.20:5700) TRXD header version 1 -> 1
2026-01-29 03:05:11.571 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.28.20:5700/1) Recv RXTUNE cmd
2026-01-29 03:05:11.571 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.28.20:5700/1) Recv TXTUNE cmd
2026-01-29 03:05:11.571 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.28.20:5700/1) Recv SETFORMAT cmd
2026-01-29 03:05:11.571 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.28.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:05:11.571 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 03:05:11.571 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.28.20:5700/1) Recv NOMTXPOWER cmd
2026-01-29 03:05:11.571 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.28.20:5700/1) Recv SETFORMAT cmd
2026-01-29 03:05:11.571 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.28.20:5700/1) TRXD header version 1 -> 1
2026-01-29 03:05:11.572 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.28.20:5700/2) Recv RXTUNE cmd
2026-01-29 03:05:11.572 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.28.20:5700/2) Recv TXTUNE cmd
2026-01-29 03:05:11.572 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.28.20:5700/2) Recv SETFORMAT cmd
2026-01-29 03:05:11.572 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.28.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:05:11.572 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 03:05:11.572 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.28.20:5700/2) Recv NOMTXPOWER cmd
2026-01-29 03:05:11.572 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.28.20:5700/2) Recv SETFORMAT cmd
2026-01-29 03:05:11.572 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.28.20:5700/2) TRXD header version 1 -> 1
2026-01-29 03:05:11.573 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.28.20:5700/3) Recv RXTUNE cmd
2026-01-29 03:05:11.573 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.28.20:5700/3) Recv TXTUNE cmd
2026-01-29 03:05:11.573 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.28.20:5700/3) Recv SETFORMAT cmd
2026-01-29 03:05:11.573 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.28.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:05:11.573 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 03:05:11.573 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.28.20:5700/3) Recv NOMTXPOWER cmd
2026-01-29 03:05:11.573 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.28.20:5700/3) Recv SETFORMAT cmd
2026-01-29 03:05:11.573 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.28.20:5700/3) TRXD header version 1 -> 1
2026-01-29 03:05:11.574 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.28.20:5700) Recv RXTUNE cmd
2026-01-29 03:05:11.574 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETTSC
2026-01-29 03:05:11.574 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETTSC
2026-01-29 03:05:11.574 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETTSC
2026-01-29 03:05:11.574 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.28.20:5700) Recv TXTUNE cmd
2026-01-29 03:05:11.574 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETRXGAIN
2026-01-29 03:05:11.574 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETRXGAIN
2026-01-29 03:05:11.574 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETRXGAIN
2026-01-29 03:05:11.574 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETTSC
2026-01-29 03:05:11.574 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:05:11.574 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:05:11.574 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.28.20:5700) Recv NOMTXPOWER cmd
2026-01-29 03:05:11.574 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:05:11.574 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:05:11.574 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:05:11.574 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.28.20:5700) Recv POWERON CMD
2026-01-29 03:05:11.574 [INFO] ctrl_if_trx.py:109 (BTS@172.18.28.20:5700) Starting transceiver...
2026-01-29 03:05:11.574 [INFO] transceiver.py:243 Starting clock generator
2026-01-29 03:05:11.574 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-01-29 03:05:11.574 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:05:11.574 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:05:11.574 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:05:11.575 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETRXGAIN
2026-01-29 03:05:11.575 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:05:11.575 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:05:11.575 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:05:11.575 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:05:11.575 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:05:11.575 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:05:11.575 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:05:11.575 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:05:11.575 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:05:11.575 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:05:11.575 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:05:11.575 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:05:11.575 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:05:11.575 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:05:11.575 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:05:11.575 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:05:11.575 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:05:11.575 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:05:11.575 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:05:11.575 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:05:11.575 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:05:11.575 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:05:11.575 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:05:11.575 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:05:11.579 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-01-29 03:05:12.048 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-01-29 03:05:12.089 [DEBUG] fake_trx.py:278 (BTS@172.18.28.20:5700) Recv FAKE_TOA cmd
2026-01-29 03:05:12.090 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:05:12.090 [DEBUG] fake_trx.py:297 (BTS@172.18.28.20:5700) Recv FAKE_RSSI cmd
2026-01-29 03:05:12.090 [DEBUG] fake_trx.py:322 (BTS@172.18.28.20:5700) Recv FAKE_CI cmd
2026-01-29 03:05:12.093 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 03:05:12.093 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:05:12.093 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:05:12.093 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:05:12.095 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 03:05:12.095 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 03:05:12.095 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 03:05:12.096 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.28.20:5700) Recv POWEROFF cmd
2026-01-29 03:05:12.096 [INFO] ctrl_if_trx.py:117 (BTS@172.18.28.20:5700) Stopping transceiver...
2026-01-29 03:05:12.096 [INFO] transceiver.py:246 Stopping clock generator
2026-01-29 03:05:12.096 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 03:05:12.096 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=114 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:05:12.096 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=114 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:05:12.096 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=114 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:05:12.096 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=114 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:05:12.096 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=114 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:05:12.096 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=114 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:05:12.096 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=114 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:05:17.094 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.28.20:5700) Recv POWEROFF cmd
2026-01-29 03:05:17.094 [INFO] ctrl_if_trx.py:117 (BTS@172.18.28.20:5700) Stopping transceiver...
2026-01-29 03:05:17.095 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 03:05:17.095 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 03:05:17.095 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 03:05:17.096 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 03:05:17.099 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 03:05:17.099 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.28.20:5700) Recv SETFORMAT cmd
2026-01-29 03:05:17.099 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.28.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:05:17.100 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.28.20:5700) Recv SETFORMAT cmd
2026-01-29 03:05:17.100 [INFO] ctrl_if_trx.py:201 (BTS@172.18.28.20:5700) TRXD header version 1 -> 1
2026-01-29 03:05:17.100 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.28.20:5700/1) Recv RXTUNE cmd
2026-01-29 03:05:17.100 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.28.20:5700/1) Recv TXTUNE cmd
2026-01-29 03:05:17.100 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.28.20:5700/1) Recv SETFORMAT cmd
2026-01-29 03:05:17.100 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.28.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:05:17.100 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 03:05:17.101 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.28.20:5700/1) Recv NOMTXPOWER cmd
2026-01-29 03:05:17.101 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.28.20:5700/1) Recv SETFORMAT cmd
2026-01-29 03:05:17.101 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.28.20:5700/1) TRXD header version 1 -> 1
2026-01-29 03:05:17.101 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.28.20:5700/2) Recv RXTUNE cmd
2026-01-29 03:05:17.102 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.28.20:5700/2) Recv TXTUNE cmd
2026-01-29 03:05:17.102 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.28.20:5700/2) Recv SETFORMAT cmd
2026-01-29 03:05:17.102 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.28.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:05:17.102 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 03:05:17.102 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.28.20:5700/2) Recv NOMTXPOWER cmd
2026-01-29 03:05:17.102 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.28.20:5700/2) Recv SETFORMAT cmd
2026-01-29 03:05:17.102 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.28.20:5700/2) TRXD header version 1 -> 1
2026-01-29 03:05:17.103 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.28.20:5700/3) Recv RXTUNE cmd
2026-01-29 03:05:17.103 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.28.20:5700/3) Recv TXTUNE cmd
2026-01-29 03:05:17.103 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.28.20:5700/3) Recv SETFORMAT cmd
2026-01-29 03:05:17.103 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.28.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:05:17.103 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 03:05:17.103 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.28.20:5700/3) Recv NOMTXPOWER cmd
2026-01-29 03:05:17.103 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.28.20:5700/3) Recv SETFORMAT cmd
2026-01-29 03:05:17.103 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.28.20:5700/3) TRXD header version 1 -> 1
2026-01-29 03:05:17.104 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.28.20:5700) Recv RXTUNE cmd
2026-01-29 03:05:17.104 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETTSC
2026-01-29 03:05:17.104 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETTSC
2026-01-29 03:05:17.104 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.28.20:5700) Recv TXTUNE cmd
2026-01-29 03:05:17.104 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETTSC
2026-01-29 03:05:17.105 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETRXGAIN
2026-01-29 03:05:17.105 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETRXGAIN
2026-01-29 03:05:17.105 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETTSC
2026-01-29 03:05:17.105 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETRXGAIN
2026-01-29 03:05:17.105 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:05:17.105 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:05:17.105 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.28.20:5700) Recv NOMTXPOWER cmd
2026-01-29 03:05:17.105 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:05:17.105 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:05:17.105 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:05:17.105 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.28.20:5700) Recv POWERON CMD
2026-01-29 03:05:17.105 [INFO] ctrl_if_trx.py:109 (BTS@172.18.28.20:5700) Starting transceiver...
2026-01-29 03:05:17.105 [INFO] transceiver.py:243 Starting clock generator
2026-01-29 03:05:17.105 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-01-29 03:05:17.105 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:05:17.105 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:05:17.105 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:05:17.105 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETRXGAIN
2026-01-29 03:05:17.105 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:05:17.105 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:05:17.105 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:05:17.105 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:05:17.105 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:05:17.105 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:05:17.105 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:05:17.105 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:05:17.105 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:05:17.105 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:05:17.105 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:05:17.105 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:05:17.105 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:05:17.105 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:05:17.105 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:05:17.106 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:05:17.106 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:05:17.106 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:05:17.106 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:05:17.106 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:05:17.106 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:05:17.106 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:05:17.106 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:05:17.106 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:05:17.110 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-01-29 03:05:17.577 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-01-29 03:05:17.621 [DEBUG] fake_trx.py:278 (BTS@172.18.28.20:5700) Recv FAKE_TOA cmd
2026-01-29 03:05:17.622 [DEBUG] fake_trx.py:297 (BTS@172.18.28.20:5700) Recv FAKE_RSSI cmd
2026-01-29 03:05:17.622 [DEBUG] fake_trx.py:322 (BTS@172.18.28.20:5700) Recv FAKE_CI cmd
2026-01-29 03:05:17.622 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:05:17.624 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:05:17.626 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 03:05:17.626 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:05:17.626 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:05:17.628 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:05:17.628 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 03:05:17.629 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 03:05:17.629 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 03:05:17.629 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 03:05:17.629 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.28.20:5700) Recv POWEROFF cmd
2026-01-29 03:05:17.629 [INFO] ctrl_if_trx.py:117 (BTS@172.18.28.20:5700) Stopping transceiver...
2026-01-29 03:05:17.629 [INFO] transceiver.py:246 Stopping clock generator
2026-01-29 03:05:17.629 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=115 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:05:17.629 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=115 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:05:17.629 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=115 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:05:17.629 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=115 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:05:17.629 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=115 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:05:17.630 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=115 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:05:22.627 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.28.20:5700) Recv POWEROFF cmd
2026-01-29 03:05:22.627 [INFO] ctrl_if_trx.py:117 (BTS@172.18.28.20:5700) Stopping transceiver...
2026-01-29 03:05:22.627 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 03:05:22.628 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 03:05:22.628 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 03:05:22.629 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 03:05:22.632 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 03:05:22.632 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.28.20:5700) Recv SETFORMAT cmd
2026-01-29 03:05:22.632 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.28.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:05:22.632 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.28.20:5700) Recv SETFORMAT cmd
2026-01-29 03:05:22.632 [INFO] ctrl_if_trx.py:201 (BTS@172.18.28.20:5700) TRXD header version 1 -> 1
2026-01-29 03:05:22.633 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.28.20:5700/1) Recv RXTUNE cmd
2026-01-29 03:05:22.633 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.28.20:5700/1) Recv TXTUNE cmd
2026-01-29 03:05:22.633 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.28.20:5700/1) Recv SETFORMAT cmd
2026-01-29 03:05:22.633 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.28.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:05:22.633 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 03:05:22.633 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.28.20:5700/1) Recv NOMTXPOWER cmd
2026-01-29 03:05:22.633 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.28.20:5700/1) Recv SETFORMAT cmd
2026-01-29 03:05:22.633 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.28.20:5700/1) TRXD header version 1 -> 1
2026-01-29 03:05:22.634 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.28.20:5700/2) Recv RXTUNE cmd
2026-01-29 03:05:22.634 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.28.20:5700/2) Recv TXTUNE cmd
2026-01-29 03:05:22.634 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.28.20:5700/2) Recv SETFORMAT cmd
2026-01-29 03:05:22.634 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.28.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:05:22.634 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 03:05:22.634 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.28.20:5700/2) Recv NOMTXPOWER cmd
2026-01-29 03:05:22.634 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.28.20:5700/2) Recv SETFORMAT cmd
2026-01-29 03:05:22.634 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.28.20:5700/2) TRXD header version 1 -> 1
2026-01-29 03:05:22.635 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.28.20:5700/3) Recv RXTUNE cmd
2026-01-29 03:05:22.635 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.28.20:5700/3) Recv TXTUNE cmd
2026-01-29 03:05:22.635 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.28.20:5700/3) Recv SETFORMAT cmd
2026-01-29 03:05:22.635 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.28.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:05:22.635 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 03:05:22.635 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.28.20:5700/3) Recv NOMTXPOWER cmd
2026-01-29 03:05:22.635 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.28.20:5700/3) Recv SETFORMAT cmd
2026-01-29 03:05:22.635 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.28.20:5700/3) TRXD header version 1 -> 1
2026-01-29 03:05:22.636 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.28.20:5700) Recv RXTUNE cmd
2026-01-29 03:05:22.636 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETTSC
2026-01-29 03:05:22.636 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETTSC
2026-01-29 03:05:22.636 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETTSC
2026-01-29 03:05:22.636 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.28.20:5700) Recv TXTUNE cmd
2026-01-29 03:05:22.636 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETRXGAIN
2026-01-29 03:05:22.636 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETRXGAIN
2026-01-29 03:05:22.636 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETRXGAIN
2026-01-29 03:05:22.636 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETTSC
2026-01-29 03:05:22.636 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:05:22.636 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:05:22.636 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:05:22.636 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.28.20:5700) Recv NOMTXPOWER cmd
2026-01-29 03:05:22.636 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:05:22.636 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:05:22.636 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:05:22.636 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.28.20:5700) Recv POWERON CMD
2026-01-29 03:05:22.636 [INFO] ctrl_if_trx.py:109 (BTS@172.18.28.20:5700) Starting transceiver...
2026-01-29 03:05:22.636 [INFO] transceiver.py:243 Starting clock generator
2026-01-29 03:05:22.636 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-01-29 03:05:22.636 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:05:22.637 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:05:22.637 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:05:22.637 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETRXGAIN
2026-01-29 03:05:22.637 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:05:22.637 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:05:22.637 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:05:22.637 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:05:22.637 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:05:22.637 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:05:22.637 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:05:22.637 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:05:22.637 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:05:22.637 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:05:22.637 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:05:22.637 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:05:22.637 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:05:22.637 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:05:22.637 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:05:22.637 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:05:22.637 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:05:22.637 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:05:22.637 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:05:22.637 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:05:22.637 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:05:22.637 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:05:22.637 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:05:22.641 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-01-29 03:05:23.109 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-01-29 03:05:23.153 [DEBUG] fake_trx.py:278 (BTS@172.18.28.20:5700) Recv FAKE_TOA cmd
2026-01-29 03:05:23.153 [DEBUG] fake_trx.py:297 (BTS@172.18.28.20:5700) Recv FAKE_RSSI cmd
2026-01-29 03:05:23.154 [DEBUG] fake_trx.py:322 (BTS@172.18.28.20:5700) Recv FAKE_CI cmd
2026-01-29 03:05:23.154 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:05:23.159 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 03:05:23.159 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:05:23.159 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:05:23.159 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:05:23.162 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 03:05:23.162 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 03:05:23.162 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 03:05:23.162 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.28.20:5700) Recv POWEROFF cmd
2026-01-29 03:05:23.162 [INFO] ctrl_if_trx.py:117 (BTS@172.18.28.20:5700) Stopping transceiver...
2026-01-29 03:05:23.162 [INFO] transceiver.py:246 Stopping clock generator
2026-01-29 03:05:23.163 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 03:05:23.163 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=115 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:05:23.163 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=115 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:05:23.163 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=115 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:05:23.163 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=115 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:05:23.163 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=115 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:05:23.163 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=115 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:05:23.163 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=115 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:05:23.164 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=115 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:05:28.162 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.28.20:5700) Recv POWEROFF cmd
2026-01-29 03:05:28.162 [INFO] ctrl_if_trx.py:117 (BTS@172.18.28.20:5700) Stopping transceiver...
2026-01-29 03:05:28.166 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 03:05:28.166 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 03:05:28.166 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 03:05:28.166 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 03:05:28.175 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 03:05:28.177 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.28.20:5700) Recv SETFORMAT cmd
2026-01-29 03:05:28.177 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.28.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:05:28.177 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.28.20:5700) Recv SETFORMAT cmd
2026-01-29 03:05:28.178 [INFO] ctrl_if_trx.py:201 (BTS@172.18.28.20:5700) TRXD header version 1 -> 1
2026-01-29 03:05:28.181 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.28.20:5700/1) Recv RXTUNE cmd
2026-01-29 03:05:28.181 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.28.20:5700/1) Recv TXTUNE cmd
2026-01-29 03:05:28.182 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.28.20:5700/1) Recv SETFORMAT cmd
2026-01-29 03:05:28.182 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.28.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:05:28.183 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 03:05:28.183 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.28.20:5700/1) Recv NOMTXPOWER cmd
2026-01-29 03:05:28.183 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.28.20:5700/1) Recv SETFORMAT cmd
2026-01-29 03:05:28.184 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.28.20:5700/1) TRXD header version 1 -> 1
2026-01-29 03:05:28.184 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.28.20:5700/2) Recv RXTUNE cmd
2026-01-29 03:05:28.185 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.28.20:5700/2) Recv TXTUNE cmd
2026-01-29 03:05:28.185 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.28.20:5700/2) Recv SETFORMAT cmd
2026-01-29 03:05:28.185 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.28.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:05:28.185 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 03:05:28.185 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.28.20:5700/2) Recv NOMTXPOWER cmd
2026-01-29 03:05:28.185 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.28.20:5700/2) Recv SETFORMAT cmd
2026-01-29 03:05:28.186 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.28.20:5700/2) TRXD header version 1 -> 1
2026-01-29 03:05:28.187 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.28.20:5700/3) Recv RXTUNE cmd
2026-01-29 03:05:28.187 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.28.20:5700/3) Recv TXTUNE cmd
2026-01-29 03:05:28.187 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.28.20:5700/3) Recv SETFORMAT cmd
2026-01-29 03:05:28.187 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.28.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:05:28.187 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 03:05:28.187 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.28.20:5700/3) Recv NOMTXPOWER cmd
2026-01-29 03:05:28.187 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.28.20:5700/3) Recv SETFORMAT cmd
2026-01-29 03:05:28.187 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.28.20:5700/3) TRXD header version 1 -> 1
2026-01-29 03:05:28.189 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.28.20:5700) Recv RXTUNE cmd
2026-01-29 03:05:28.189 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETTSC
2026-01-29 03:05:28.189 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETTSC
2026-01-29 03:05:28.189 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETTSC
2026-01-29 03:05:28.190 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.28.20:5700) Recv TXTUNE cmd
2026-01-29 03:05:28.190 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETRXGAIN
2026-01-29 03:05:28.190 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETRXGAIN
2026-01-29 03:05:28.190 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETRXGAIN
2026-01-29 03:05:28.190 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETTSC
2026-01-29 03:05:28.190 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:05:28.190 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:05:28.190 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.28.20:5700) Recv NOMTXPOWER cmd
2026-01-29 03:05:28.190 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:05:28.190 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:05:28.190 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:05:28.190 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.28.20:5700) Recv POWERON CMD
2026-01-29 03:05:28.190 [INFO] ctrl_if_trx.py:109 (BTS@172.18.28.20:5700) Starting transceiver...
2026-01-29 03:05:28.190 [INFO] transceiver.py:243 Starting clock generator
2026-01-29 03:05:28.190 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-01-29 03:05:28.190 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:05:28.190 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:05:28.190 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:05:28.190 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETRXGAIN
2026-01-29 03:05:28.190 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:05:28.190 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:05:28.190 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:05:28.190 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:05:28.190 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:05:28.190 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:05:28.190 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:05:28.190 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:05:28.190 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:05:28.190 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:05:28.190 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:05:28.191 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:05:28.191 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:05:28.191 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:05:28.191 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:05:28.191 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:05:28.191 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:05:28.191 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:05:28.191 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:05:28.191 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:05:28.191 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:05:28.191 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:05:28.191 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:05:28.191 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:05:28.195 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-01-29 03:05:28.678 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-01-29 03:05:28.712 [DEBUG] fake_trx.py:278 (BTS@172.18.28.20:5700) Recv FAKE_TOA cmd
2026-01-29 03:05:28.713 [DEBUG] fake_trx.py:297 (BTS@172.18.28.20:5700) Recv FAKE_RSSI cmd
2026-01-29 03:05:28.714 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:05:28.715 [DEBUG] fake_trx.py:322 (BTS@172.18.28.20:5700) Recv FAKE_CI cmd
2026-01-29 03:05:28.718 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 03:05:28.718 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 03:05:28.718 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 03:05:28.719 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 03:05:28.719 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 03:05:28.719 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 03:05:28.719 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.28.22:6700) Recv POWERON CMD
2026-01-29 03:05:28.719 [INFO] ctrl_if_trx.py:109 (MS@172.18.28.22:6700) Starting transceiver...
2026-01-29 03:05:29.155 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-01-29 03:05:29.192 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:05:29.193 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 03:05:29.193 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:05:29.193 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:05:29.633 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-01-29 03:05:30.111 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-01-29 03:05:30.193 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:05:30.193 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 03:05:30.194 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:05:30.194 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:05:30.589 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-01-29 03:05:31.068 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-01-29 03:05:31.194 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:05:31.194 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:05:31.194 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 03:05:31.194 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:05:31.545 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-01-29 03:05:31.728 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.28.22:6700) Recv SETFH cmd
2026-01-29 03:05:31.728 [INFO] transceiver.py:201 (MS@172.18.28.22:6700) Frequency hopping configured: hsn=0, maio=1, ma_len=2
2026-01-29 03:05:31.729 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 03:05:31.730 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 03:05:31.774 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 03:05:31.775 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 03:05:31.775 [INFO] transceiver.py:205 (MS@172.18.28.22:6700) Frequency hopping disabled
2026-01-29 03:05:31.775 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:05:31.780 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 03:05:31.780 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:05:31.781 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:05:31.781 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:05:31.784 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 03:05:31.784 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 03:05:31.784 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 03:05:31.784 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 03:05:31.785 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.28.20:5700) Recv POWEROFF cmd
2026-01-29 03:05:31.785 [INFO] ctrl_if_trx.py:117 (BTS@172.18.28.20:5700) Stopping transceiver...
2026-01-29 03:05:31.785 [INFO] transceiver.py:246 Stopping clock generator
2026-01-29 03:05:31.785 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=767 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:05:31.785 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=767 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:05:31.785 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=767 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:05:31.786 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=767 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:05:31.786 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=767 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:05:31.786 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=767 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:05:31.786 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=767 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:05:36.783 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.28.20:5700) Recv POWEROFF cmd
2026-01-29 03:05:36.783 [INFO] ctrl_if_trx.py:117 (BTS@172.18.28.20:5700) Stopping transceiver...
2026-01-29 03:05:36.784 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 03:05:36.785 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 03:05:36.785 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 03:05:36.786 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 03:05:36.789 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 03:05:36.789 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.28.20:5700) Recv SETFORMAT cmd
2026-01-29 03:05:36.789 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.28.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:05:36.789 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.28.20:5700) Recv SETFORMAT cmd
2026-01-29 03:05:36.789 [INFO] ctrl_if_trx.py:201 (BTS@172.18.28.20:5700) TRXD header version 1 -> 1
2026-01-29 03:05:36.790 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.28.20:5700/1) Recv RXTUNE cmd
2026-01-29 03:05:36.790 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.28.20:5700/1) Recv TXTUNE cmd
2026-01-29 03:05:36.791 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.28.20:5700/1) Recv SETFORMAT cmd
2026-01-29 03:05:36.791 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.28.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:05:36.791 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 03:05:36.791 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.28.20:5700/1) Recv NOMTXPOWER cmd
2026-01-29 03:05:36.792 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.28.20:5700/1) Recv SETFORMAT cmd
2026-01-29 03:05:36.792 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.28.20:5700/1) TRXD header version 1 -> 1
2026-01-29 03:05:36.792 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.28.20:5700/2) Recv RXTUNE cmd
2026-01-29 03:05:36.793 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.28.20:5700/2) Recv TXTUNE cmd
2026-01-29 03:05:36.793 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.28.20:5700/2) Recv SETFORMAT cmd
2026-01-29 03:05:36.793 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.28.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:05:36.793 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 03:05:36.793 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.28.20:5700/2) Recv NOMTXPOWER cmd
2026-01-29 03:05:36.793 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.28.20:5700/2) Recv SETFORMAT cmd
2026-01-29 03:05:36.793 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.28.20:5700/2) TRXD header version 1 -> 1
2026-01-29 03:05:36.795 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.28.20:5700/3) Recv RXTUNE cmd
2026-01-29 03:05:36.795 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.28.20:5700/3) Recv TXTUNE cmd
2026-01-29 03:05:36.796 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.28.20:5700/3) Recv SETFORMAT cmd
2026-01-29 03:05:36.796 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.28.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:05:36.796 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 03:05:36.796 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.28.20:5700/3) Recv NOMTXPOWER cmd
2026-01-29 03:05:36.796 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.28.20:5700/3) Recv SETFORMAT cmd
2026-01-29 03:05:36.796 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.28.20:5700/3) TRXD header version 1 -> 1
2026-01-29 03:05:36.798 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.28.20:5700) Recv RXTUNE cmd
2026-01-29 03:05:36.798 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETTSC
2026-01-29 03:05:36.798 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETTSC
2026-01-29 03:05:36.798 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETTSC
2026-01-29 03:05:36.798 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.28.20:5700) Recv TXTUNE cmd
2026-01-29 03:05:36.799 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETRXGAIN
2026-01-29 03:05:36.799 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETRXGAIN
2026-01-29 03:05:36.799 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETRXGAIN
2026-01-29 03:05:36.799 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETTSC
2026-01-29 03:05:36.799 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:05:36.799 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:05:36.799 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:05:36.799 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.28.20:5700) Recv NOMTXPOWER cmd
2026-01-29 03:05:36.799 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:05:36.799 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:05:36.799 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:05:36.799 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.28.20:5700) Recv POWERON CMD
2026-01-29 03:05:36.799 [INFO] ctrl_if_trx.py:109 (BTS@172.18.28.20:5700) Starting transceiver...
2026-01-29 03:05:36.799 [INFO] transceiver.py:243 Starting clock generator
2026-01-29 03:05:36.799 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-01-29 03:05:36.799 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:05:36.799 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:05:36.799 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:05:36.800 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETRXGAIN
2026-01-29 03:05:36.800 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:05:36.800 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:05:36.800 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:05:36.800 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:05:36.800 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:05:36.800 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:05:36.800 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:05:36.800 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:05:36.800 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:05:36.800 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:05:36.800 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:05:36.800 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:05:36.800 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:05:36.800 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:05:36.800 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:05:36.800 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:05:36.800 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:05:36.800 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:05:36.800 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:05:36.800 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:05:36.800 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:05:36.800 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:05:36.800 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:05:36.804 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-01-29 03:05:37.287 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-01-29 03:05:37.326 [DEBUG] fake_trx.py:278 (BTS@172.18.28.20:5700) Recv FAKE_TOA cmd
2026-01-29 03:05:37.328 [DEBUG] fake_trx.py:297 (BTS@172.18.28.20:5700) Recv FAKE_RSSI cmd
2026-01-29 03:05:37.329 [DEBUG] fake_trx.py:322 (BTS@172.18.28.20:5700) Recv FAKE_CI cmd
2026-01-29 03:05:37.329 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:05:37.334 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 03:05:37.334 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 03:05:37.334 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 03:05:37.335 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 03:05:37.336 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 03:05:37.336 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 03:05:37.336 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.28.22:6700) Recv POWERON CMD
2026-01-29 03:05:37.336 [INFO] ctrl_if_trx.py:109 (MS@172.18.28.22:6700) Starting transceiver...
2026-01-29 03:05:37.764 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-01-29 03:05:37.802 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 03:05:37.802 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:05:37.803 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:05:37.807 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:05:38.242 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-01-29 03:05:38.719 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-01-29 03:05:38.803 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 03:05:38.803 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:05:38.804 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:05:38.808 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:05:39.197 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-01-29 03:05:39.675 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-01-29 03:05:39.803 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 03:05:39.804 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:05:39.804 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:05:39.809 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:05:40.153 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-01-29 03:05:40.395 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.28.22:6700) Recv SETFH cmd
2026-01-29 03:05:40.396 [INFO] transceiver.py:201 (MS@172.18.28.22:6700) Frequency hopping configured: hsn=0, maio=1, ma_len=2
2026-01-29 03:05:40.396 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 03:05:40.396 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 03:05:40.631 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-01-29 03:05:40.804 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 03:05:40.805 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:05:40.805 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:05:40.810 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:05:41.109 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-01-29 03:05:41.120 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 03:05:41.121 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 03:05:41.121 [INFO] transceiver.py:205 (MS@172.18.28.22:6700) Frequency hopping disabled
2026-01-29 03:05:41.121 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:05:41.127 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 03:05:41.127 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:05:41.127 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:05:41.128 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:05:41.128 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 03:05:41.128 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 03:05:41.128 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 03:05:41.128 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.28.20:5700) Recv POWEROFF cmd
2026-01-29 03:05:41.128 [INFO] ctrl_if_trx.py:117 (BTS@172.18.28.20:5700) Stopping transceiver...
2026-01-29 03:05:41.128 [INFO] transceiver.py:246 Stopping clock generator
2026-01-29 03:05:41.128 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 03:05:41.129 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=924 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:05:41.129 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=924 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:05:41.129 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=924 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:05:41.129 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=924 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:05:41.129 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=924 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:05:41.129 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=924 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:05:41.129 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=924 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:05:41.129 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=924 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:05:46.130 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.28.20:5700) Recv POWEROFF cmd
2026-01-29 03:05:46.130 [INFO] ctrl_if_trx.py:117 (BTS@172.18.28.20:5700) Stopping transceiver...
2026-01-29 03:05:46.135 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 03:05:46.135 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 03:05:46.135 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 03:05:46.136 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 03:05:46.142 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 03:05:46.142 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.28.20:5700) Recv SETFORMAT cmd
2026-01-29 03:05:46.142 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.28.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:05:46.142 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.28.20:5700) Recv SETFORMAT cmd
2026-01-29 03:05:46.142 [INFO] ctrl_if_trx.py:201 (BTS@172.18.28.20:5700) TRXD header version 1 -> 1
2026-01-29 03:05:46.144 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.28.20:5700/1) Recv RXTUNE cmd
2026-01-29 03:05:46.144 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.28.20:5700/1) Recv TXTUNE cmd
2026-01-29 03:05:46.144 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.28.20:5700/1) Recv SETFORMAT cmd
2026-01-29 03:05:46.144 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.28.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:05:46.145 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 03:05:46.145 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.28.20:5700/1) Recv NOMTXPOWER cmd
2026-01-29 03:05:46.145 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.28.20:5700/1) Recv SETFORMAT cmd
2026-01-29 03:05:46.145 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.28.20:5700/1) TRXD header version 1 -> 1
2026-01-29 03:05:46.146 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.28.20:5700/2) Recv RXTUNE cmd
2026-01-29 03:05:46.146 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.28.20:5700/2) Recv TXTUNE cmd
2026-01-29 03:05:46.146 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.28.20:5700/2) Recv SETFORMAT cmd
2026-01-29 03:05:46.146 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.28.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:05:46.146 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 03:05:46.146 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.28.20:5700/2) Recv NOMTXPOWER cmd
2026-01-29 03:05:46.146 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.28.20:5700/2) Recv SETFORMAT cmd
2026-01-29 03:05:46.146 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.28.20:5700/2) TRXD header version 1 -> 1
2026-01-29 03:05:46.147 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.28.20:5700/3) Recv RXTUNE cmd
2026-01-29 03:05:46.148 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.28.20:5700/3) Recv TXTUNE cmd
2026-01-29 03:05:46.148 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.28.20:5700/3) Recv SETFORMAT cmd
2026-01-29 03:05:46.148 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.28.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:05:46.148 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.28.20:5700/3) Recv NOMTXPOWER cmd
2026-01-29 03:05:46.148 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 03:05:46.148 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.28.20:5700/3) Recv SETFORMAT cmd
2026-01-29 03:05:46.148 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.28.20:5700/3) TRXD header version 1 -> 1
2026-01-29 03:05:46.149 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.28.20:5700) Recv RXTUNE cmd
2026-01-29 03:05:46.149 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETTSC
2026-01-29 03:05:46.149 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETTSC
2026-01-29 03:05:46.149 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETTSC
2026-01-29 03:05:46.149 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.28.20:5700) Recv TXTUNE cmd
2026-01-29 03:05:46.149 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETRXGAIN
2026-01-29 03:05:46.149 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETRXGAIN
2026-01-29 03:05:46.149 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETRXGAIN
2026-01-29 03:05:46.149 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETTSC
2026-01-29 03:05:46.149 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:05:46.150 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:05:46.150 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:05:46.150 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.28.20:5700) Recv NOMTXPOWER cmd
2026-01-29 03:05:46.150 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:05:46.150 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:05:46.150 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.28.20:5700) Recv POWERON CMD
2026-01-29 03:05:46.150 [INFO] ctrl_if_trx.py:109 (BTS@172.18.28.20:5700) Starting transceiver...
2026-01-29 03:05:46.150 [INFO] transceiver.py:243 Starting clock generator
2026-01-29 03:05:46.150 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-01-29 03:05:46.150 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:05:46.150 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:05:46.150 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:05:46.150 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETRXGAIN
2026-01-29 03:05:46.150 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:05:46.150 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:05:46.150 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:05:46.150 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:05:46.150 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:05:46.150 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:05:46.150 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:05:46.150 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:05:46.150 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:05:46.150 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:05:46.150 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:05:46.150 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:05:46.150 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:05:46.150 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:05:46.150 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:05:46.150 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:05:46.150 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:05:46.150 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:05:46.150 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:05:46.150 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:05:46.150 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:05:46.150 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:05:46.150 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:05:46.150 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:05:46.154 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-01-29 03:05:46.634 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-01-29 03:05:46.669 [DEBUG] fake_trx.py:278 (BTS@172.18.28.20:5700) Recv FAKE_TOA cmd
2026-01-29 03:05:46.670 [DEBUG] fake_trx.py:297 (BTS@172.18.28.20:5700) Recv FAKE_RSSI cmd
2026-01-29 03:05:46.672 [DEBUG] fake_trx.py:322 (BTS@172.18.28.20:5700) Recv FAKE_CI cmd
2026-01-29 03:05:46.674 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:05:46.678 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 03:05:46.678 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 03:05:46.678 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 03:05:46.679 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 03:05:46.679 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 03:05:46.680 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 03:05:46.680 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.28.22:6700) Recv POWERON CMD
2026-01-29 03:05:46.680 [INFO] ctrl_if_trx.py:109 (MS@172.18.28.22:6700) Starting transceiver...
2026-01-29 03:05:47.103 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-01-29 03:05:47.152 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 03:05:47.152 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:05:47.152 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:05:47.153 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:05:47.581 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-01-29 03:05:48.058 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-01-29 03:05:48.152 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 03:05:48.153 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:05:48.153 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:05:48.153 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:05:48.536 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-01-29 03:05:49.014 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-01-29 03:05:49.153 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 03:05:49.154 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:05:49.154 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:05:49.154 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:05:49.492 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-01-29 03:05:49.734 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.28.22:6700) Recv SETFH cmd
2026-01-29 03:05:49.735 [INFO] transceiver.py:201 (MS@172.18.28.22:6700) Frequency hopping configured: hsn=0, maio=1, ma_len=2
2026-01-29 03:05:49.735 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 03:05:49.735 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 03:05:49.970 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-01-29 03:05:50.155 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 03:05:50.155 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:05:50.155 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:05:50.156 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:05:50.448 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-01-29 03:05:50.926 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-01-29 03:05:51.156 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:05:51.157 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:05:51.157 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 03:05:51.157 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:05:51.405 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-01-29 03:05:51.883 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-01-29 03:05:52.362 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-01-29 03:05:52.839 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-01-29 03:05:53.317 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-01-29 03:05:53.791 [DEBUG] clck_gen.py:113 IND CLOCK 1632
2026-01-29 03:05:54.269 [DEBUG] clck_gen.py:113 IND CLOCK 1734
2026-01-29 03:05:54.737 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 03:05:54.738 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 03:05:54.738 [INFO] transceiver.py:205 (MS@172.18.28.22:6700) Frequency hopping disabled
2026-01-29 03:05:54.738 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:05:54.747 [DEBUG] clck_gen.py:113 IND CLOCK 1836
2026-01-29 03:05:54.754 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 03:05:54.755 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:05:54.755 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:05:54.755 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:05:54.758 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 03:05:54.758 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 03:05:54.758 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 03:05:54.758 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 03:05:54.758 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.28.20:5700) Recv POWEROFF cmd
2026-01-29 03:05:54.758 [INFO] ctrl_if_trx.py:117 (BTS@172.18.28.20:5700) Stopping transceiver...
2026-01-29 03:05:54.758 [INFO] transceiver.py:246 Stopping clock generator
2026-01-29 03:05:54.758 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=1840 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:05:54.758 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=1840 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:05:54.758 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=1840 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:05:54.758 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=1840 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:05:54.758 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=1840 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:05:54.758 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=1840 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:05:54.758 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=1840 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:05:59.758 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.28.20:5700) Recv POWEROFF cmd
2026-01-29 03:05:59.759 [INFO] ctrl_if_trx.py:117 (BTS@172.18.28.20:5700) Stopping transceiver...
2026-01-29 03:05:59.760 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 03:05:59.761 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 03:05:59.763 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 03:05:59.766 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 03:05:59.781 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 03:05:59.783 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.28.20:5700) Recv SETFORMAT cmd
2026-01-29 03:05:59.783 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.28.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:05:59.784 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.28.20:5700) Recv SETFORMAT cmd
2026-01-29 03:05:59.784 [INFO] ctrl_if_trx.py:201 (BTS@172.18.28.20:5700) TRXD header version 1 -> 1
2026-01-29 03:05:59.787 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.28.20:5700/1) Recv RXTUNE cmd
2026-01-29 03:05:59.788 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.28.20:5700/1) Recv TXTUNE cmd
2026-01-29 03:05:59.788 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.28.20:5700/1) Recv SETFORMAT cmd
2026-01-29 03:05:59.788 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.28.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:05:59.789 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 03:05:59.789 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.28.20:5700/1) Recv NOMTXPOWER cmd
2026-01-29 03:05:59.790 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.28.20:5700/1) Recv SETFORMAT cmd
2026-01-29 03:05:59.790 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.28.20:5700/1) TRXD header version 1 -> 1
2026-01-29 03:05:59.790 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.28.20:5700/2) Recv RXTUNE cmd
2026-01-29 03:05:59.791 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.28.20:5700/2) Recv TXTUNE cmd
2026-01-29 03:05:59.791 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.28.20:5700/2) Recv SETFORMAT cmd
2026-01-29 03:05:59.791 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.28.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:05:59.791 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 03:05:59.791 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.28.20:5700/2) Recv NOMTXPOWER cmd
2026-01-29 03:05:59.791 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.28.20:5700/2) Recv SETFORMAT cmd
2026-01-29 03:05:59.791 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.28.20:5700/2) TRXD header version 1 -> 1
2026-01-29 03:05:59.793 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.28.20:5700/3) Recv RXTUNE cmd
2026-01-29 03:05:59.793 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.28.20:5700/3) Recv TXTUNE cmd
2026-01-29 03:05:59.793 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.28.20:5700/3) Recv SETFORMAT cmd
2026-01-29 03:05:59.793 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.28.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:05:59.793 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 03:05:59.793 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.28.20:5700/3) Recv NOMTXPOWER cmd
2026-01-29 03:05:59.793 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.28.20:5700/3) Recv SETFORMAT cmd
2026-01-29 03:05:59.793 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.28.20:5700/3) TRXD header version 1 -> 1
2026-01-29 03:05:59.796 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.28.20:5700) Recv RXTUNE cmd
2026-01-29 03:05:59.796 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETTSC
2026-01-29 03:05:59.796 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETTSC
2026-01-29 03:05:59.796 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETTSC
2026-01-29 03:05:59.796 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.28.20:5700) Recv TXTUNE cmd
2026-01-29 03:05:59.796 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETRXGAIN
2026-01-29 03:05:59.796 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETRXGAIN
2026-01-29 03:05:59.796 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETRXGAIN
2026-01-29 03:05:59.796 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETTSC
2026-01-29 03:05:59.796 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:05:59.796 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:05:59.796 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:05:59.796 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.28.20:5700) Recv NOMTXPOWER cmd
2026-01-29 03:05:59.796 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:05:59.796 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:05:59.796 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:05:59.796 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.28.20:5700) Recv POWERON CMD
2026-01-29 03:05:59.796 [INFO] ctrl_if_trx.py:109 (BTS@172.18.28.20:5700) Starting transceiver...
2026-01-29 03:05:59.796 [INFO] transceiver.py:243 Starting clock generator
2026-01-29 03:05:59.796 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-01-29 03:05:59.796 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:05:59.796 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:05:59.796 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:05:59.797 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETRXGAIN
2026-01-29 03:05:59.797 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:05:59.797 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:05:59.797 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:05:59.797 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:05:59.797 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:05:59.797 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:05:59.797 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:05:59.797 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:05:59.797 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:05:59.797 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:05:59.797 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:05:59.797 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:05:59.797 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:05:59.797 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:05:59.797 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:05:59.797 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:05:59.797 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:05:59.797 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:05:59.797 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:05:59.797 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:05:59.797 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:05:59.797 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:05:59.797 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:05:59.801 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-01-29 03:06:00.280 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-01-29 03:06:00.325 [DEBUG] fake_trx.py:278 (BTS@172.18.28.20:5700) Recv FAKE_TOA cmd
2026-01-29 03:06:00.327 [DEBUG] fake_trx.py:297 (BTS@172.18.28.20:5700) Recv FAKE_RSSI cmd
2026-01-29 03:06:00.328 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:06:00.328 [DEBUG] fake_trx.py:322 (BTS@172.18.28.20:5700) Recv FAKE_CI cmd
2026-01-29 03:06:00.336 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 03:06:00.336 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 03:06:00.336 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 03:06:00.338 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 03:06:00.338 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 03:06:00.338 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 03:06:00.338 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.28.22:6700) Recv POWERON CMD
2026-01-29 03:06:00.338 [INFO] ctrl_if_trx.py:109 (MS@172.18.28.22:6700) Starting transceiver...
2026-01-29 03:06:00.757 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-01-29 03:06:00.799 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 03:06:00.799 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:06:00.800 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:06:00.803 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:06:01.235 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-01-29 03:06:01.713 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-01-29 03:06:01.799 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 03:06:01.800 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:06:01.800 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:06:01.804 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:06:02.190 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-01-29 03:06:02.668 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-01-29 03:06:02.801 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 03:06:02.801 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:06:02.801 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:06:02.805 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:06:03.146 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-01-29 03:06:03.388 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.28.22:6700) Recv SETFH cmd
2026-01-29 03:06:03.388 [INFO] transceiver.py:201 (MS@172.18.28.22:6700) Frequency hopping configured: hsn=0, maio=1, ma_len=2
2026-01-29 03:06:03.389 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 03:06:03.389 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 03:06:03.624 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-01-29 03:06:03.802 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:06:03.802 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:06:03.802 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 03:06:03.806 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:06:04.102 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-01-29 03:06:04.580 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-01-29 03:06:04.802 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:06:04.803 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:06:04.803 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 03:06:04.807 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:06:05.058 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-01-29 03:06:05.537 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-01-29 03:06:06.011 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-01-29 03:06:06.490 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-01-29 03:06:06.968 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-01-29 03:06:07.446 [DEBUG] clck_gen.py:113 IND CLOCK 1632
2026-01-29 03:06:07.924 [DEBUG] clck_gen.py:113 IND CLOCK 1734
2026-01-29 03:06:08.391 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 03:06:08.391 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 03:06:08.391 [INFO] transceiver.py:205 (MS@172.18.28.22:6700) Frequency hopping disabled
2026-01-29 03:06:08.391 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:06:08.400 [DEBUG] clck_gen.py:113 IND CLOCK 1836
2026-01-29 03:06:08.402 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 03:06:08.402 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:06:08.402 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:06:08.402 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:06:08.406 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 03:06:08.406 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 03:06:08.406 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 03:06:08.406 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.28.20:5700) Recv POWEROFF cmd
2026-01-29 03:06:08.406 [INFO] ctrl_if_trx.py:117 (BTS@172.18.28.20:5700) Stopping transceiver...
2026-01-29 03:06:08.406 [INFO] transceiver.py:246 Stopping clock generator
2026-01-29 03:06:08.407 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 03:06:08.407 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=1839 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:06:08.407 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=1839 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:06:08.407 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=1839 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:06:08.407 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=1839 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:06:08.407 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=1839 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:06:08.407 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=1839 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:06:08.407 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=1839 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:06:08.407 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=1839 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:06:08.407 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=1840 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:06:08.408 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=1840 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:06:08.408 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=1840 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:06:08.408 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=1840 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:06:08.408 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=1840 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:06:08.408 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=1840 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:06:08.408 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=1840 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:06:08.408 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=1840 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:06:13.406 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.28.20:5700) Recv POWEROFF cmd
2026-01-29 03:06:13.406 [INFO] ctrl_if_trx.py:117 (BTS@172.18.28.20:5700) Stopping transceiver...
2026-01-29 03:06:13.408 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 03:06:13.409 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 03:06:13.409 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 03:06:13.409 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 03:06:13.413 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 03:06:13.413 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.28.20:5700) Recv SETFORMAT cmd
2026-01-29 03:06:13.413 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.28.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:06:13.413 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.28.20:5700) Recv SETFORMAT cmd
2026-01-29 03:06:13.413 [INFO] ctrl_if_trx.py:201 (BTS@172.18.28.20:5700) TRXD header version 1 -> 1
2026-01-29 03:06:13.414 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.28.20:5700/1) Recv RXTUNE cmd
2026-01-29 03:06:13.414 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.28.20:5700/1) Recv TXTUNE cmd
2026-01-29 03:06:13.414 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.28.20:5700/1) Recv SETFORMAT cmd
2026-01-29 03:06:13.414 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.28.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:06:13.414 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 03:06:13.414 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.28.20:5700/1) Recv NOMTXPOWER cmd
2026-01-29 03:06:13.414 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.28.20:5700/1) Recv SETFORMAT cmd
2026-01-29 03:06:13.414 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.28.20:5700/1) TRXD header version 1 -> 1
2026-01-29 03:06:13.415 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.28.20:5700/2) Recv RXTUNE cmd
2026-01-29 03:06:13.415 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.28.20:5700/2) Recv TXTUNE cmd
2026-01-29 03:06:13.415 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.28.20:5700/2) Recv SETFORMAT cmd
2026-01-29 03:06:13.415 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.28.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:06:13.415 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 03:06:13.415 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.28.20:5700/2) Recv NOMTXPOWER cmd
2026-01-29 03:06:13.415 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.28.20:5700/2) Recv SETFORMAT cmd
2026-01-29 03:06:13.415 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.28.20:5700/2) TRXD header version 1 -> 1
2026-01-29 03:06:13.417 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.28.20:5700/3) Recv RXTUNE cmd
2026-01-29 03:06:13.417 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.28.20:5700/3) Recv TXTUNE cmd
2026-01-29 03:06:13.417 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.28.20:5700/3) Recv SETFORMAT cmd
2026-01-29 03:06:13.417 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.28.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:06:13.417 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 03:06:13.417 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.28.20:5700/3) Recv NOMTXPOWER cmd
2026-01-29 03:06:13.417 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.28.20:5700/3) Recv SETFORMAT cmd
2026-01-29 03:06:13.417 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.28.20:5700/3) TRXD header version 1 -> 1
2026-01-29 03:06:13.420 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.28.20:5700) Recv RXTUNE cmd
2026-01-29 03:06:13.420 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETTSC
2026-01-29 03:06:13.420 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETTSC
2026-01-29 03:06:13.420 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETTSC
2026-01-29 03:06:13.420 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.28.20:5700) Recv TXTUNE cmd
2026-01-29 03:06:13.420 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETRXGAIN
2026-01-29 03:06:13.420 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETRXGAIN
2026-01-29 03:06:13.420 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETRXGAIN
2026-01-29 03:06:13.420 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETTSC
2026-01-29 03:06:13.420 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:06:13.420 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:06:13.420 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.28.20:5700) Recv NOMTXPOWER cmd
2026-01-29 03:06:13.421 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:06:13.421 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:06:13.421 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:06:13.421 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.28.20:5700) Recv POWERON CMD
2026-01-29 03:06:13.421 [INFO] ctrl_if_trx.py:109 (BTS@172.18.28.20:5700) Starting transceiver...
2026-01-29 03:06:13.421 [INFO] transceiver.py:243 Starting clock generator
2026-01-29 03:06:13.421 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-01-29 03:06:13.421 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:06:13.421 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:06:13.421 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:06:13.421 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETRXGAIN
2026-01-29 03:06:13.421 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:06:13.421 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:06:13.421 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:06:13.421 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:06:13.421 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:06:13.421 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:06:13.421 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:06:13.421 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:06:13.421 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:06:13.422 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:06:13.422 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:06:13.422 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:06:13.422 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:06:13.422 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:06:13.422 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:06:13.422 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:06:13.422 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:06:13.422 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:06:13.422 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:06:13.422 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:06:13.422 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:06:13.422 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:06:13.422 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:06:13.422 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:06:13.426 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-01-29 03:06:13.907 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-01-29 03:06:13.953 [DEBUG] fake_trx.py:278 (BTS@172.18.28.20:5700) Recv FAKE_TOA cmd
2026-01-29 03:06:13.955 [DEBUG] fake_trx.py:297 (BTS@172.18.28.20:5700) Recv FAKE_RSSI cmd
2026-01-29 03:06:13.956 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:06:13.957 [DEBUG] fake_trx.py:322 (BTS@172.18.28.20:5700) Recv FAKE_CI cmd
2026-01-29 03:06:13.966 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 03:06:13.966 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 03:06:13.966 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 03:06:13.967 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 03:06:13.967 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 03:06:13.967 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 03:06:13.968 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.28.22:6700) Recv POWERON CMD
2026-01-29 03:06:13.968 [INFO] ctrl_if_trx.py:109 (MS@172.18.28.22:6700) Starting transceiver...
2026-01-29 03:06:14.384 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-01-29 03:06:14.423 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 03:06:14.423 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:06:14.425 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:06:14.430 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:06:14.862 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-01-29 03:06:15.340 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-01-29 03:06:15.424 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 03:06:15.424 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:06:15.426 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:06:15.431 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:06:15.818 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-01-29 03:06:16.296 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-01-29 03:06:16.425 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 03:06:16.425 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:06:16.428 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:06:16.432 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:06:16.773 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-01-29 03:06:17.014 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.28.22:6700) Recv SETFH cmd
2026-01-29 03:06:17.014 [INFO] transceiver.py:201 (MS@172.18.28.22:6700) Frequency hopping configured: hsn=0, maio=1, ma_len=2
2026-01-29 03:06:17.015 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 03:06:17.015 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 03:06:17.251 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-01-29 03:06:17.425 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 03:06:17.426 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:06:17.429 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:06:17.434 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:06:17.729 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-01-29 03:06:18.207 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-01-29 03:06:18.426 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 03:06:18.427 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:06:18.430 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:06:18.434 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:06:18.685 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-01-29 03:06:19.163 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-01-29 03:06:19.641 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-01-29 03:06:20.118 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-01-29 03:06:20.597 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-01-29 03:06:21.075 [DEBUG] clck_gen.py:113 IND CLOCK 1632
2026-01-29 03:06:21.553 [DEBUG] clck_gen.py:113 IND CLOCK 1734
2026-01-29 03:06:22.016 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 03:06:22.016 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 03:06:22.016 [INFO] transceiver.py:205 (MS@172.18.28.22:6700) Frequency hopping disabled
2026-01-29 03:06:22.017 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:06:22.031 [DEBUG] clck_gen.py:113 IND CLOCK 1836
2026-01-29 03:06:22.032 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 03:06:22.032 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:06:22.033 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:06:22.033 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:06:22.036 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 03:06:22.036 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 03:06:22.036 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 03:06:22.036 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 03:06:22.036 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.28.20:5700) Recv POWEROFF cmd
2026-01-29 03:06:22.036 [INFO] ctrl_if_trx.py:117 (BTS@172.18.28.20:5700) Stopping transceiver...
2026-01-29 03:06:22.036 [INFO] transceiver.py:246 Stopping clock generator
2026-01-29 03:06:27.036 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.28.20:5700) Recv POWEROFF cmd
2026-01-29 03:06:27.036 [INFO] ctrl_if_trx.py:117 (BTS@172.18.28.20:5700) Stopping transceiver...
2026-01-29 03:06:27.038 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 03:06:27.040 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 03:06:27.040 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 03:06:27.040 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 03:06:27.054 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 03:06:27.056 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.28.20:5700) Recv SETFORMAT cmd
2026-01-29 03:06:27.056 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.28.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:06:27.056 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.28.20:5700) Recv SETFORMAT cmd
2026-01-29 03:06:27.057 [INFO] ctrl_if_trx.py:201 (BTS@172.18.28.20:5700) TRXD header version 1 -> 1
2026-01-29 03:06:27.061 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.28.20:5700/1) Recv RXTUNE cmd
2026-01-29 03:06:27.061 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.28.20:5700/1) Recv TXTUNE cmd
2026-01-29 03:06:27.062 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.28.20:5700/1) Recv SETFORMAT cmd
2026-01-29 03:06:27.062 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.28.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:06:27.062 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 03:06:27.063 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.28.20:5700/1) Recv NOMTXPOWER cmd
2026-01-29 03:06:27.063 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.28.20:5700/1) Recv SETFORMAT cmd
2026-01-29 03:06:27.063 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.28.20:5700/1) TRXD header version 1 -> 1
2026-01-29 03:06:27.064 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.28.20:5700/2) Recv RXTUNE cmd
2026-01-29 03:06:27.064 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.28.20:5700/2) Recv TXTUNE cmd
2026-01-29 03:06:27.065 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.28.20:5700/2) Recv SETFORMAT cmd
2026-01-29 03:06:27.065 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.28.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:06:27.065 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 03:06:27.065 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.28.20:5700/2) Recv NOMTXPOWER cmd
2026-01-29 03:06:27.065 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.28.20:5700/2) Recv SETFORMAT cmd
2026-01-29 03:06:27.065 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.28.20:5700/2) TRXD header version 1 -> 1
2026-01-29 03:06:27.067 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.28.20:5700/3) Recv RXTUNE cmd
2026-01-29 03:06:27.067 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.28.20:5700/3) Recv TXTUNE cmd
2026-01-29 03:06:27.067 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.28.20:5700/3) Recv SETFORMAT cmd
2026-01-29 03:06:27.067 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.28.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:06:27.067 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 03:06:27.068 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.28.20:5700/3) Recv NOMTXPOWER cmd
2026-01-29 03:06:27.068 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.28.20:5700/3) Recv SETFORMAT cmd
2026-01-29 03:06:27.068 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.28.20:5700/3) TRXD header version 1 -> 1
2026-01-29 03:06:27.070 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.28.20:5700) Recv RXTUNE cmd
2026-01-29 03:06:27.070 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETTSC
2026-01-29 03:06:27.070 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETTSC
2026-01-29 03:06:27.070 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.28.20:5700) Recv TXTUNE cmd
2026-01-29 03:06:27.070 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETTSC
2026-01-29 03:06:27.070 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETRXGAIN
2026-01-29 03:06:27.070 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETRXGAIN
2026-01-29 03:06:27.071 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETTSC
2026-01-29 03:06:27.071 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETRXGAIN
2026-01-29 03:06:27.071 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:06:27.071 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:06:27.071 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.28.20:5700) Recv NOMTXPOWER cmd
2026-01-29 03:06:27.071 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:06:27.071 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:06:27.071 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:06:27.071 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.28.20:5700) Recv POWERON CMD
2026-01-29 03:06:27.071 [INFO] ctrl_if_trx.py:109 (BTS@172.18.28.20:5700) Starting transceiver...
2026-01-29 03:06:27.071 [INFO] transceiver.py:243 Starting clock generator
2026-01-29 03:06:27.071 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-01-29 03:06:27.071 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:06:27.071 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:06:27.071 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:06:27.071 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETRXGAIN
2026-01-29 03:06:27.071 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:06:27.072 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:06:27.072 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:06:27.072 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:06:27.072 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:06:27.072 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:06:27.072 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:06:27.072 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:06:27.072 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:06:27.072 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:06:27.072 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:06:27.072 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:06:27.072 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:06:27.072 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:06:27.072 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:06:27.072 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:06:27.072 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:06:27.072 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:06:27.072 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:06:27.072 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:06:27.072 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:06:27.072 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:06:27.072 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:06:27.072 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:06:27.076 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-01-29 03:06:27.559 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-01-29 03:06:27.601 [DEBUG] fake_trx.py:278 (BTS@172.18.28.20:5700) Recv FAKE_TOA cmd
2026-01-29 03:06:27.603 [DEBUG] fake_trx.py:297 (BTS@172.18.28.20:5700) Recv FAKE_RSSI cmd
2026-01-29 03:06:27.605 [DEBUG] fake_trx.py:322 (BTS@172.18.28.20:5700) Recv FAKE_CI cmd
2026-01-29 03:06:27.605 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:06:27.609 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 03:06:27.609 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 03:06:27.609 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 03:06:27.609 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 03:06:27.609 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 03:06:27.609 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 03:06:27.610 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.28.22:6700) Recv POWERON CMD
2026-01-29 03:06:27.610 [INFO] ctrl_if_trx.py:109 (MS@172.18.28.22:6700) Starting transceiver...
2026-01-29 03:06:27.649 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.28.22:6700) Recv SETFH cmd
2026-01-29 03:06:27.650 [INFO] transceiver.py:201 (MS@172.18.28.22:6700) Frequency hopping configured: hsn=0, maio=1, ma_len=2
2026-01-29 03:06:27.650 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 03:06:27.650 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 03:06:28.037 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-01-29 03:06:28.074 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 03:06:28.074 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:06:28.076 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:06:28.079 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:06:28.515 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-01-29 03:06:28.993 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-01-29 03:06:29.075 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 03:06:29.076 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:06:29.077 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:06:29.080 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:06:29.472 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-01-29 03:06:29.950 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-01-29 03:06:30.076 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:06:30.076 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 03:06:30.078 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:06:30.081 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:06:30.428 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-01-29 03:06:30.906 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-01-29 03:06:31.077 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 03:06:31.077 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:06:31.078 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:06:31.082 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:06:31.385 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-01-29 03:06:31.863 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-01-29 03:06:32.078 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 03:06:32.078 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:06:32.080 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:06:32.083 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:06:32.341 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-01-29 03:06:32.651 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 03:06:32.652 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 03:06:32.652 [INFO] transceiver.py:205 (MS@172.18.28.22:6700) Frequency hopping disabled
2026-01-29 03:06:32.663 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 03:06:32.663 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:06:32.664 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:06:32.664 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:06:32.664 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 03:06:32.664 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 03:06:32.664 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.28.20:5700) Recv POWEROFF cmd
2026-01-29 03:06:32.665 [INFO] ctrl_if_trx.py:117 (BTS@172.18.28.20:5700) Stopping transceiver...
2026-01-29 03:06:32.665 [INFO] transceiver.py:246 Stopping clock generator
2026-01-29 03:06:32.665 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 03:06:32.665 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 03:06:32.665 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=1194 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:06:32.665 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=1194 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:06:32.665 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=1194 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:06:32.665 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=1194 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:06:32.665 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=1194 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:06:32.665 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=1194 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:06:32.665 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=1194 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:06:32.665 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=1194 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:06:37.667 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.28.20:5700) Recv POWEROFF cmd
2026-01-29 03:06:37.667 [INFO] ctrl_if_trx.py:117 (BTS@172.18.28.20:5700) Stopping transceiver...
2026-01-29 03:06:37.668 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 03:06:37.669 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 03:06:37.669 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 03:06:37.670 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 03:06:37.678 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 03:06:37.679 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.28.20:5700) Recv SETFORMAT cmd
2026-01-29 03:06:37.679 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.28.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:06:37.680 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.28.20:5700) Recv SETFORMAT cmd
2026-01-29 03:06:37.680 [INFO] ctrl_if_trx.py:201 (BTS@172.18.28.20:5700) TRXD header version 1 -> 1
2026-01-29 03:06:37.683 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.28.20:5700/1) Recv RXTUNE cmd
2026-01-29 03:06:37.683 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.28.20:5700/1) Recv TXTUNE cmd
2026-01-29 03:06:37.684 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.28.20:5700/1) Recv SETFORMAT cmd
2026-01-29 03:06:37.684 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.28.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:06:37.684 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 03:06:37.684 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.28.20:5700/1) Recv NOMTXPOWER cmd
2026-01-29 03:06:37.685 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.28.20:5700/1) Recv SETFORMAT cmd
2026-01-29 03:06:37.685 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.28.20:5700/1) TRXD header version 1 -> 1
2026-01-29 03:06:37.686 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.28.20:5700/2) Recv RXTUNE cmd
2026-01-29 03:06:37.686 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.28.20:5700/2) Recv TXTUNE cmd
2026-01-29 03:06:37.686 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.28.20:5700/2) Recv SETFORMAT cmd
2026-01-29 03:06:37.686 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.28.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:06:37.686 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 03:06:37.686 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.28.20:5700/2) Recv NOMTXPOWER cmd
2026-01-29 03:06:37.687 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.28.20:5700/2) Recv SETFORMAT cmd
2026-01-29 03:06:37.687 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.28.20:5700/2) TRXD header version 1 -> 1
2026-01-29 03:06:37.688 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.28.20:5700/3) Recv RXTUNE cmd
2026-01-29 03:06:37.688 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.28.20:5700/3) Recv TXTUNE cmd
2026-01-29 03:06:37.688 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.28.20:5700/3) Recv SETFORMAT cmd
2026-01-29 03:06:37.688 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.28.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:06:37.688 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 03:06:37.688 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.28.20:5700/3) Recv NOMTXPOWER cmd
2026-01-29 03:06:37.688 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.28.20:5700/3) Recv SETFORMAT cmd
2026-01-29 03:06:37.688 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.28.20:5700/3) TRXD header version 1 -> 1
2026-01-29 03:06:37.690 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.28.20:5700) Recv RXTUNE cmd
2026-01-29 03:06:37.690 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETTSC
2026-01-29 03:06:37.690 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETTSC
2026-01-29 03:06:37.690 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETTSC
2026-01-29 03:06:37.690 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.28.20:5700) Recv TXTUNE cmd
2026-01-29 03:06:37.690 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETRXGAIN
2026-01-29 03:06:37.690 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETRXGAIN
2026-01-29 03:06:37.690 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETRXGAIN
2026-01-29 03:06:37.690 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETTSC
2026-01-29 03:06:37.690 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:06:37.691 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:06:37.691 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:06:37.691 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.28.20:5700) Recv NOMTXPOWER cmd
2026-01-29 03:06:37.691 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:06:37.691 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:06:37.691 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:06:37.691 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.28.20:5700) Recv POWERON CMD
2026-01-29 03:06:37.691 [INFO] ctrl_if_trx.py:109 (BTS@172.18.28.20:5700) Starting transceiver...
2026-01-29 03:06:37.691 [INFO] transceiver.py:243 Starting clock generator
2026-01-29 03:06:37.691 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-01-29 03:06:37.691 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:06:37.691 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:06:37.691 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:06:37.691 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETRXGAIN
2026-01-29 03:06:37.691 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:06:37.691 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:06:37.691 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:06:37.691 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:06:37.691 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:06:37.691 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:06:37.691 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:06:37.691 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:06:37.691 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:06:37.691 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:06:37.691 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:06:37.691 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:06:37.691 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:06:37.691 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:06:37.691 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:06:37.691 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:06:37.691 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:06:37.691 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:06:37.691 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:06:37.691 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:06:37.691 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:06:37.692 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:06:37.692 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:06:37.695 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-01-29 03:06:38.179 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-01-29 03:06:38.218 [DEBUG] fake_trx.py:278 (BTS@172.18.28.20:5700) Recv FAKE_TOA cmd
2026-01-29 03:06:38.219 [DEBUG] fake_trx.py:297 (BTS@172.18.28.20:5700) Recv FAKE_RSSI cmd
2026-01-29 03:06:38.221 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:06:38.222 [DEBUG] fake_trx.py:322 (BTS@172.18.28.20:5700) Recv FAKE_CI cmd
2026-01-29 03:06:38.231 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 03:06:38.231 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 03:06:38.232 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 03:06:38.232 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 03:06:38.232 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 03:06:38.232 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 03:06:38.233 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.28.22:6700) Recv POWERON CMD
2026-01-29 03:06:38.233 [INFO] ctrl_if_trx.py:109 (MS@172.18.28.22:6700) Starting transceiver...
2026-01-29 03:06:38.654 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-01-29 03:06:38.693 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 03:06:38.693 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:06:38.694 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:06:38.697 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:06:39.132 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-01-29 03:06:39.609 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-01-29 03:06:39.693 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 03:06:39.694 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:06:39.696 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:06:39.698 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:06:40.088 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-01-29 03:06:40.565 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-01-29 03:06:40.695 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 03:06:40.695 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:06:40.696 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:06:40.699 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:06:41.043 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-01-29 03:06:41.286 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.28.22:6700) Recv SETFH cmd
2026-01-29 03:06:41.286 [INFO] transceiver.py:201 (MS@172.18.28.22:6700) Frequency hopping configured: hsn=0, maio=1, ma_len=2
2026-01-29 03:06:41.286 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 03:06:41.286 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 03:06:41.521 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-01-29 03:06:41.696 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 03:06:41.696 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:06:41.697 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:06:41.700 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:06:42.000 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-01-29 03:06:42.478 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-01-29 03:06:42.696 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 03:06:42.697 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:06:42.698 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:06:42.701 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:06:42.957 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-01-29 03:06:43.288 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 03:06:43.288 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 03:06:43.288 [INFO] transceiver.py:205 (MS@172.18.28.22:6700) Frequency hopping disabled
2026-01-29 03:06:43.288 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:06:43.298 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 03:06:43.301 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:06:43.301 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:06:43.301 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:06:43.302 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 03:06:43.302 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 03:06:43.302 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 03:06:43.302 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 03:06:43.302 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.28.20:5700) Recv POWEROFF cmd
2026-01-29 03:06:43.302 [INFO] ctrl_if_trx.py:117 (BTS@172.18.28.20:5700) Stopping transceiver...
2026-01-29 03:06:43.302 [INFO] transceiver.py:246 Stopping clock generator
2026-01-29 03:06:43.302 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=1198 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:06:43.302 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=1198 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:06:43.302 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=1198 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:06:48.302 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.28.20:5700) Recv POWEROFF cmd
2026-01-29 03:06:48.302 [INFO] ctrl_if_trx.py:117 (BTS@172.18.28.20:5700) Stopping transceiver...
2026-01-29 03:06:48.303 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 03:06:48.305 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 03:06:48.306 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 03:06:48.306 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 03:06:48.316 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 03:06:48.318 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.28.20:5700) Recv SETFORMAT cmd
2026-01-29 03:06:48.318 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.28.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:06:48.319 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.28.20:5700) Recv SETFORMAT cmd
2026-01-29 03:06:48.319 [INFO] ctrl_if_trx.py:201 (BTS@172.18.28.20:5700) TRXD header version 1 -> 1
2026-01-29 03:06:48.324 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.28.20:5700/1) Recv RXTUNE cmd
2026-01-29 03:06:48.324 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.28.20:5700/1) Recv TXTUNE cmd
2026-01-29 03:06:48.325 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.28.20:5700/1) Recv SETFORMAT cmd
2026-01-29 03:06:48.325 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.28.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:06:48.325 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 03:06:48.325 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.28.20:5700/1) Recv NOMTXPOWER cmd
2026-01-29 03:06:48.325 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.28.20:5700/1) Recv SETFORMAT cmd
2026-01-29 03:06:48.326 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.28.20:5700/1) TRXD header version 1 -> 1
2026-01-29 03:06:48.328 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.28.20:5700/2) Recv RXTUNE cmd
2026-01-29 03:06:48.328 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.28.20:5700/2) Recv TXTUNE cmd
2026-01-29 03:06:48.328 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.28.20:5700/2) Recv SETFORMAT cmd
2026-01-29 03:06:48.328 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.28.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:06:48.328 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 03:06:48.328 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.28.20:5700/2) Recv NOMTXPOWER cmd
2026-01-29 03:06:48.329 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.28.20:5700/2) Recv SETFORMAT cmd
2026-01-29 03:06:48.329 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.28.20:5700/2) TRXD header version 1 -> 1
2026-01-29 03:06:48.331 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.28.20:5700/3) Recv RXTUNE cmd
2026-01-29 03:06:48.331 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.28.20:5700/3) Recv TXTUNE cmd
2026-01-29 03:06:48.331 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.28.20:5700/3) Recv SETFORMAT cmd
2026-01-29 03:06:48.331 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.28.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:06:48.331 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 03:06:48.331 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.28.20:5700/3) Recv NOMTXPOWER cmd
2026-01-29 03:06:48.331 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.28.20:5700/3) Recv SETFORMAT cmd
2026-01-29 03:06:48.331 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.28.20:5700/3) TRXD header version 1 -> 1
2026-01-29 03:06:48.334 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.28.20:5700) Recv RXTUNE cmd
2026-01-29 03:06:48.334 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETTSC
2026-01-29 03:06:48.334 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETTSC
2026-01-29 03:06:48.334 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETTSC
2026-01-29 03:06:48.334 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.28.20:5700) Recv TXTUNE cmd
2026-01-29 03:06:48.334 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETRXGAIN
2026-01-29 03:06:48.334 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETRXGAIN
2026-01-29 03:06:48.334 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETRXGAIN
2026-01-29 03:06:48.334 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETTSC
2026-01-29 03:06:48.334 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:06:48.335 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:06:48.335 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:06:48.335 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.28.20:5700) Recv NOMTXPOWER cmd
2026-01-29 03:06:48.335 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:06:48.335 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:06:48.335 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:06:48.335 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.28.20:5700) Recv POWERON CMD
2026-01-29 03:06:48.335 [INFO] ctrl_if_trx.py:109 (BTS@172.18.28.20:5700) Starting transceiver...
2026-01-29 03:06:48.335 [INFO] transceiver.py:243 Starting clock generator
2026-01-29 03:06:48.335 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-01-29 03:06:48.335 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:06:48.335 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:06:48.335 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:06:48.335 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETRXGAIN
2026-01-29 03:06:48.335 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:06:48.335 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:06:48.335 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:06:48.335 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:06:48.335 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:06:48.335 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:06:48.335 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:06:48.335 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:06:48.336 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:06:48.336 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:06:48.336 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:06:48.336 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:06:48.336 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:06:48.336 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:06:48.336 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:06:48.336 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:06:48.336 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:06:48.336 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:06:48.336 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:06:48.336 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:06:48.336 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:06:48.336 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:06:48.336 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:06:48.340 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-01-29 03:06:48.825 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-01-29 03:06:48.866 [DEBUG] fake_trx.py:278 (BTS@172.18.28.20:5700) Recv FAKE_TOA cmd
2026-01-29 03:06:48.868 [DEBUG] fake_trx.py:297 (BTS@172.18.28.20:5700) Recv FAKE_RSSI cmd
2026-01-29 03:06:48.869 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:06:48.870 [DEBUG] fake_trx.py:322 (BTS@172.18.28.20:5700) Recv FAKE_CI cmd
2026-01-29 03:06:48.878 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 03:06:48.879 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 03:06:48.879 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 03:06:48.880 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 03:06:48.880 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 03:06:48.881 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 03:06:48.881 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.28.22:6700) Recv POWERON CMD
2026-01-29 03:06:48.881 [INFO] ctrl_if_trx.py:109 (MS@172.18.28.22:6700) Starting transceiver...
2026-01-29 03:06:49.302 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-01-29 03:06:49.338 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 03:06:49.338 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:06:49.339 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:06:49.343 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:06:49.780 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-01-29 03:06:50.258 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-01-29 03:06:50.339 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 03:06:50.339 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:06:50.341 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:06:50.344 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:06:50.736 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-01-29 03:06:51.213 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-01-29 03:06:51.340 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 03:06:51.340 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:06:51.342 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:06:51.345 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:06:51.691 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-01-29 03:06:51.989 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 03:06:51.989 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 03:06:51.989 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:06:51.994 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 03:06:51.994 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:06:51.994 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:06:51.995 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:06:51.998 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 03:06:51.998 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 03:06:51.998 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 03:06:51.998 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.28.20:5700) Recv POWEROFF cmd
2026-01-29 03:06:51.998 [INFO] ctrl_if_trx.py:117 (BTS@172.18.28.20:5700) Stopping transceiver...
2026-01-29 03:06:51.998 [INFO] transceiver.py:246 Stopping clock generator
2026-01-29 03:06:51.999 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 03:06:51.999 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=781 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:06:51.999 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=781 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:06:51.999 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=781 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:06:51.999 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=781 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:06:51.999 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=781 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:06:52.000 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=781 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:06:52.000 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=781 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:06:52.000 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=781 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:06:52.000 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=782 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:06:52.000 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=782 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:06:52.000 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=782 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:06:52.000 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=782 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:06:52.000 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=782 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:06:52.000 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=782 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:06:52.000 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=782 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:06:52.000 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=782 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:06:56.998 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.28.20:5700) Recv POWEROFF cmd
2026-01-29 03:06:56.998 [INFO] ctrl_if_trx.py:117 (BTS@172.18.28.20:5700) Stopping transceiver...
2026-01-29 03:06:57.000 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 03:06:57.001 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 03:06:57.002 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 03:06:57.002 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 03:06:57.010 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 03:06:57.011 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.28.20:5700) Recv SETFORMAT cmd
2026-01-29 03:06:57.011 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.28.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:06:57.012 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.28.20:5700) Recv SETFORMAT cmd
2026-01-29 03:06:57.012 [INFO] ctrl_if_trx.py:201 (BTS@172.18.28.20:5700) TRXD header version 1 -> 1
2026-01-29 03:06:57.016 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.28.20:5700/1) Recv RXTUNE cmd
2026-01-29 03:06:57.016 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.28.20:5700/1) Recv TXTUNE cmd
2026-01-29 03:06:57.016 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.28.20:5700/1) Recv SETFORMAT cmd
2026-01-29 03:06:57.016 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.28.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:06:57.016 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 03:06:57.016 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.28.20:5700/1) Recv NOMTXPOWER cmd
2026-01-29 03:06:57.016 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.28.20:5700/1) Recv SETFORMAT cmd
2026-01-29 03:06:57.016 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.28.20:5700/1) TRXD header version 1 -> 1
2026-01-29 03:06:57.019 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.28.20:5700/2) Recv RXTUNE cmd
2026-01-29 03:06:57.019 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.28.20:5700/2) Recv TXTUNE cmd
2026-01-29 03:06:57.019 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.28.20:5700/2) Recv SETFORMAT cmd
2026-01-29 03:06:57.019 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.28.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:06:57.019 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 03:06:57.019 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.28.20:5700/2) Recv NOMTXPOWER cmd
2026-01-29 03:06:57.019 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.28.20:5700/2) Recv SETFORMAT cmd
2026-01-29 03:06:57.019 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.28.20:5700/2) TRXD header version 1 -> 1
2026-01-29 03:06:57.021 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.28.20:5700/3) Recv RXTUNE cmd
2026-01-29 03:06:57.021 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.28.20:5700/3) Recv TXTUNE cmd
2026-01-29 03:06:57.022 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.28.20:5700/3) Recv SETFORMAT cmd
2026-01-29 03:06:57.022 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.28.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:06:57.022 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 03:06:57.022 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.28.20:5700/3) Recv NOMTXPOWER cmd
2026-01-29 03:06:57.022 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.28.20:5700/3) Recv SETFORMAT cmd
2026-01-29 03:06:57.022 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.28.20:5700/3) TRXD header version 1 -> 1
2026-01-29 03:06:57.024 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.28.20:5700) Recv RXTUNE cmd
2026-01-29 03:06:57.024 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETTSC
2026-01-29 03:06:57.024 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETTSC
2026-01-29 03:06:57.024 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETTSC
2026-01-29 03:06:57.024 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.28.20:5700) Recv TXTUNE cmd
2026-01-29 03:06:57.024 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETRXGAIN
2026-01-29 03:06:57.025 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETRXGAIN
2026-01-29 03:06:57.025 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETRXGAIN
2026-01-29 03:06:57.025 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETTSC
2026-01-29 03:06:57.025 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:06:57.025 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:06:57.025 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:06:57.025 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.28.20:5700) Recv NOMTXPOWER cmd
2026-01-29 03:06:57.025 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:06:57.025 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:06:57.025 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:06:57.025 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.28.20:5700) Recv POWERON CMD
2026-01-29 03:06:57.025 [INFO] ctrl_if_trx.py:109 (BTS@172.18.28.20:5700) Starting transceiver...
2026-01-29 03:06:57.025 [INFO] transceiver.py:243 Starting clock generator
2026-01-29 03:06:57.025 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-01-29 03:06:57.025 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:06:57.025 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:06:57.025 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:06:57.025 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETRXGAIN
2026-01-29 03:06:57.025 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:06:57.025 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:06:57.026 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:06:57.026 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:06:57.026 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:06:57.026 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:06:57.026 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:06:57.026 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:06:57.026 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:06:57.026 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:06:57.026 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:06:57.026 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:06:57.026 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:06:57.026 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:06:57.026 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:06:57.026 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:06:57.026 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:06:57.026 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:06:57.026 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:06:57.026 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:06:57.026 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:06:57.026 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:06:57.026 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:06:57.030 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-01-29 03:06:57.514 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-01-29 03:06:57.546 [DEBUG] fake_trx.py:278 (BTS@172.18.28.20:5700) Recv FAKE_TOA cmd
2026-01-29 03:06:57.547 [DEBUG] fake_trx.py:297 (BTS@172.18.28.20:5700) Recv FAKE_RSSI cmd
2026-01-29 03:06:57.549 [DEBUG] fake_trx.py:322 (BTS@172.18.28.20:5700) Recv FAKE_CI cmd
2026-01-29 03:06:57.550 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:06:57.554 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 03:06:57.554 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 03:06:57.554 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 03:06:57.555 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 03:06:57.555 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 03:06:57.556 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 03:06:57.556 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.28.22:6700) Recv POWERON CMD
2026-01-29 03:06:57.556 [INFO] ctrl_if_trx.py:109 (MS@172.18.28.22:6700) Starting transceiver...
2026-01-29 03:06:57.991 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-01-29 03:06:58.027 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 03:06:58.028 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:06:58.028 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:06:58.031 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:06:58.469 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-01-29 03:06:58.947 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-01-29 03:06:59.028 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 03:06:59.029 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:06:59.029 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:06:59.032 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:06:59.425 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-01-29 03:06:59.903 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-01-29 03:07:00.029 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 03:07:00.029 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:07:00.030 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:07:00.032 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:07:00.381 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-01-29 03:07:00.697 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 03:07:00.697 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 03:07:00.697 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:07:00.702 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 03:07:00.703 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:07:00.703 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:07:00.703 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:07:00.705 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 03:07:00.705 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 03:07:00.705 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 03:07:00.705 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 03:07:00.705 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.28.20:5700) Recv POWEROFF cmd
2026-01-29 03:07:00.705 [INFO] ctrl_if_trx.py:117 (BTS@172.18.28.20:5700) Stopping transceiver...
2026-01-29 03:07:00.705 [INFO] transceiver.py:246 Stopping clock generator
2026-01-29 03:07:00.705 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=785 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:07:00.705 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=785 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:07:00.705 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=785 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:07:00.706 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=785 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:07:00.706 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=785 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:07:00.706 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=785 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:07:00.706 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=786 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:07:00.706 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=786 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:07:00.706 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=786 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:07:00.706 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=786 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:07:00.706 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=786 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:07:00.706 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=786 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:07:00.706 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=786 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:07:00.706 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=786 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:07:05.710 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.28.20:5700) Recv POWEROFF cmd
2026-01-29 03:07:05.710 [INFO] ctrl_if_trx.py:117 (BTS@172.18.28.20:5700) Stopping transceiver...
2026-01-29 03:07:05.710 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 03:07:05.710 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 03:07:05.710 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 03:07:05.710 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 03:07:05.719 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 03:07:05.721 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.28.20:5700) Recv SETFORMAT cmd
2026-01-29 03:07:05.721 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.28.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:07:05.722 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.28.20:5700) Recv SETFORMAT cmd
2026-01-29 03:07:05.722 [INFO] ctrl_if_trx.py:201 (BTS@172.18.28.20:5700) TRXD header version 1 -> 1
2026-01-29 03:07:05.726 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.28.20:5700/1) Recv RXTUNE cmd
2026-01-29 03:07:05.726 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.28.20:5700/1) Recv TXTUNE cmd
2026-01-29 03:07:05.727 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.28.20:5700/1) Recv SETFORMAT cmd
2026-01-29 03:07:05.727 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.28.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:07:05.728 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 03:07:05.728 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.28.20:5700/1) Recv NOMTXPOWER cmd
2026-01-29 03:07:05.729 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.28.20:5700/1) Recv SETFORMAT cmd
2026-01-29 03:07:05.729 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.28.20:5700/1) TRXD header version 1 -> 1
2026-01-29 03:07:05.730 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.28.20:5700/2) Recv RXTUNE cmd
2026-01-29 03:07:05.730 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.28.20:5700/2) Recv TXTUNE cmd
2026-01-29 03:07:05.730 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.28.20:5700/2) Recv SETFORMAT cmd
2026-01-29 03:07:05.730 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.28.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:07:05.731 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 03:07:05.731 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.28.20:5700/2) Recv NOMTXPOWER cmd
2026-01-29 03:07:05.732 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.28.20:5700/2) Recv SETFORMAT cmd
2026-01-29 03:07:05.732 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.28.20:5700/2) TRXD header version 1 -> 1
2026-01-29 03:07:05.733 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.28.20:5700/3) Recv RXTUNE cmd
2026-01-29 03:07:05.733 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.28.20:5700/3) Recv TXTUNE cmd
2026-01-29 03:07:05.733 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.28.20:5700/3) Recv SETFORMAT cmd
2026-01-29 03:07:05.733 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.28.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:07:05.733 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 03:07:05.733 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.28.20:5700/3) Recv NOMTXPOWER cmd
2026-01-29 03:07:05.733 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.28.20:5700/3) Recv SETFORMAT cmd
2026-01-29 03:07:05.733 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.28.20:5700/3) TRXD header version 1 -> 1
2026-01-29 03:07:05.736 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.28.20:5700) Recv RXTUNE cmd
2026-01-29 03:07:05.736 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETTSC
2026-01-29 03:07:05.736 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETTSC
2026-01-29 03:07:05.736 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETTSC
2026-01-29 03:07:05.736 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.28.20:5700) Recv TXTUNE cmd
2026-01-29 03:07:05.736 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETRXGAIN
2026-01-29 03:07:05.736 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETRXGAIN
2026-01-29 03:07:05.736 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETRXGAIN
2026-01-29 03:07:05.736 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETTSC
2026-01-29 03:07:05.736 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:07:05.736 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:07:05.736 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:07:05.736 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.28.20:5700) Recv NOMTXPOWER cmd
2026-01-29 03:07:05.737 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:07:05.737 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:07:05.737 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:07:05.737 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.28.20:5700) Recv POWERON CMD
2026-01-29 03:07:05.737 [INFO] ctrl_if_trx.py:109 (BTS@172.18.28.20:5700) Starting transceiver...
2026-01-29 03:07:05.737 [INFO] transceiver.py:243 Starting clock generator
2026-01-29 03:07:05.737 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-01-29 03:07:05.737 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:07:05.737 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:07:05.737 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:07:05.737 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETRXGAIN
2026-01-29 03:07:05.737 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:07:05.737 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:07:05.737 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:07:05.737 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:07:05.737 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:07:05.737 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:07:05.737 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:07:05.737 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:07:05.737 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:07:05.738 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:07:05.738 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:07:05.738 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:07:05.738 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:07:05.738 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:07:05.738 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:07:05.738 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:07:05.738 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:07:05.738 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:07:05.738 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:07:05.738 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:07:05.738 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:07:05.738 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:07:05.738 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:07:05.742 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-01-29 03:07:06.226 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-01-29 03:07:06.266 [DEBUG] fake_trx.py:278 (BTS@172.18.28.20:5700) Recv FAKE_TOA cmd
2026-01-29 03:07:06.268 [DEBUG] fake_trx.py:297 (BTS@172.18.28.20:5700) Recv FAKE_RSSI cmd
2026-01-29 03:07:06.271 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:07:06.271 [DEBUG] fake_trx.py:322 (BTS@172.18.28.20:5700) Recv FAKE_CI cmd
2026-01-29 03:07:06.278 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 03:07:06.278 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 03:07:06.279 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 03:07:06.280 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 03:07:06.280 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 03:07:06.281 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 03:07:06.281 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.28.22:6700) Recv POWERON CMD
2026-01-29 03:07:06.281 [INFO] ctrl_if_trx.py:109 (MS@172.18.28.22:6700) Starting transceiver...
2026-01-29 03:07:06.542 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 03:07:06.542 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 03:07:06.548 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 03:07:06.548 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:07:06.548 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:07:06.548 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:07:06.550 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 03:07:06.550 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 03:07:06.550 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 03:07:06.550 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.28.20:5700) Recv POWEROFF cmd
2026-01-29 03:07:06.550 [INFO] ctrl_if_trx.py:117 (BTS@172.18.28.20:5700) Stopping transceiver...
2026-01-29 03:07:06.550 [INFO] transceiver.py:246 Stopping clock generator
2026-01-29 03:07:06.550 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 03:07:06.550 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=173 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:07:06.550 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=173 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:07:06.550 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=173 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:07:06.550 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=173 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:07:06.550 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=173 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:07:06.550 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=173 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:07:06.550 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=173 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:07:06.550 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=174 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:07:06.550 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=174 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:07:06.550 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=174 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:07:06.550 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=174 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:07:06.550 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=174 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:07:06.550 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=174 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:07:06.550 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=174 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:07:06.550 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=174 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:07:11.552 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.28.20:5700) Recv POWEROFF cmd
2026-01-29 03:07:11.552 [INFO] ctrl_if_trx.py:117 (BTS@172.18.28.20:5700) Stopping transceiver...
2026-01-29 03:07:11.553 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 03:07:11.555 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 03:07:11.555 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 03:07:11.555 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 03:07:11.563 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 03:07:11.563 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.28.20:5700) Recv SETFORMAT cmd
2026-01-29 03:07:11.563 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.28.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:07:11.564 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.28.20:5700) Recv SETFORMAT cmd
2026-01-29 03:07:11.564 [INFO] ctrl_if_trx.py:201 (BTS@172.18.28.20:5700) TRXD header version 1 -> 1
2026-01-29 03:07:11.566 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.28.20:5700/1) Recv RXTUNE cmd
2026-01-29 03:07:11.566 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.28.20:5700/1) Recv TXTUNE cmd
2026-01-29 03:07:11.567 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.28.20:5700/1) Recv SETFORMAT cmd
2026-01-29 03:07:11.567 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.28.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:07:11.567 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 03:07:11.568 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.28.20:5700/1) Recv NOMTXPOWER cmd
2026-01-29 03:07:11.568 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.28.20:5700/1) Recv SETFORMAT cmd
2026-01-29 03:07:11.568 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.28.20:5700/1) TRXD header version 1 -> 1
2026-01-29 03:07:11.569 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.28.20:5700/2) Recv RXTUNE cmd
2026-01-29 03:07:11.569 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.28.20:5700/2) Recv TXTUNE cmd
2026-01-29 03:07:11.569 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.28.20:5700/2) Recv SETFORMAT cmd
2026-01-29 03:07:11.569 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.28.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:07:11.569 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 03:07:11.570 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.28.20:5700/2) Recv NOMTXPOWER cmd
2026-01-29 03:07:11.570 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.28.20:5700/2) Recv SETFORMAT cmd
2026-01-29 03:07:11.570 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.28.20:5700/2) TRXD header version 1 -> 1
2026-01-29 03:07:11.571 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.28.20:5700/3) Recv RXTUNE cmd
2026-01-29 03:07:11.571 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.28.20:5700/3) Recv TXTUNE cmd
2026-01-29 03:07:11.571 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.28.20:5700/3) Recv SETFORMAT cmd
2026-01-29 03:07:11.571 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.28.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:07:11.571 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 03:07:11.572 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.28.20:5700/3) Recv NOMTXPOWER cmd
2026-01-29 03:07:11.572 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.28.20:5700/3) Recv SETFORMAT cmd
2026-01-29 03:07:11.572 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.28.20:5700/3) TRXD header version 1 -> 1
2026-01-29 03:07:11.574 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.28.20:5700) Recv RXTUNE cmd
2026-01-29 03:07:11.574 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETTSC
2026-01-29 03:07:11.574 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETTSC
2026-01-29 03:07:11.574 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETTSC
2026-01-29 03:07:11.574 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.28.20:5700) Recv TXTUNE cmd
2026-01-29 03:07:11.574 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETRXGAIN
2026-01-29 03:07:11.574 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETRXGAIN
2026-01-29 03:07:11.574 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETRXGAIN
2026-01-29 03:07:11.574 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETTSC
2026-01-29 03:07:11.574 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:07:11.574 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:07:11.574 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:07:11.574 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.28.20:5700) Recv NOMTXPOWER cmd
2026-01-29 03:07:11.575 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:07:11.575 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:07:11.575 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:07:11.575 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.28.20:5700) Recv POWERON CMD
2026-01-29 03:07:11.575 [INFO] ctrl_if_trx.py:109 (BTS@172.18.28.20:5700) Starting transceiver...
2026-01-29 03:07:11.575 [INFO] transceiver.py:243 Starting clock generator
2026-01-29 03:07:11.575 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-01-29 03:07:11.575 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:07:11.575 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:07:11.575 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:07:11.575 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETRXGAIN
2026-01-29 03:07:11.575 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:07:11.575 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:07:11.575 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:07:11.575 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:07:11.575 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:07:11.575 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:07:11.575 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:07:11.575 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:07:11.575 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:07:11.575 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:07:11.575 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:07:11.576 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:07:11.576 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:07:11.576 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:07:11.576 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:07:11.576 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:07:11.576 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:07:11.576 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:07:11.576 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:07:11.576 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:07:11.576 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:07:11.576 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:07:11.576 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:07:11.580 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-01-29 03:07:12.064 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-01-29 03:07:12.114 [DEBUG] fake_trx.py:278 (BTS@172.18.28.20:5700) Recv FAKE_TOA cmd
2026-01-29 03:07:12.116 [DEBUG] fake_trx.py:297 (BTS@172.18.28.20:5700) Recv FAKE_RSSI cmd
2026-01-29 03:07:12.117 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:07:12.118 [DEBUG] fake_trx.py:322 (BTS@172.18.28.20:5700) Recv FAKE_CI cmd
2026-01-29 03:07:12.125 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 03:07:12.126 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 03:07:12.126 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 03:07:12.127 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 03:07:12.128 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 03:07:12.128 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 03:07:12.129 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.28.22:6700) Recv POWERON CMD
2026-01-29 03:07:12.129 [INFO] ctrl_if_trx.py:109 (MS@172.18.28.22:6700) Starting transceiver...
2026-01-29 03:07:12.334 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 03:07:12.334 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 03:07:12.340 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 03:07:12.340 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:07:12.340 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:07:12.340 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:07:12.342 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 03:07:12.342 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 03:07:12.342 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 03:07:12.342 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 03:07:12.343 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.28.20:5700) Recv POWEROFF cmd
2026-01-29 03:07:12.343 [INFO] ctrl_if_trx.py:117 (BTS@172.18.28.20:5700) Stopping transceiver...
2026-01-29 03:07:12.343 [INFO] transceiver.py:246 Stopping clock generator
2026-01-29 03:07:12.343 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=164 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:07:12.343 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=164 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:07:12.343 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=164 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:07:12.343 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=164 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:07:12.343 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=164 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:07:12.343 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=164 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:07:12.343 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=164 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:07:17.345 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.28.20:5700) Recv POWEROFF cmd
2026-01-29 03:07:17.345 [INFO] ctrl_if_trx.py:117 (BTS@172.18.28.20:5700) Stopping transceiver...
2026-01-29 03:07:17.345 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 03:07:17.345 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 03:07:17.345 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 03:07:17.345 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 03:07:17.355 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 03:07:17.357 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.28.20:5700) Recv SETFORMAT cmd
2026-01-29 03:07:17.357 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.28.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:07:17.358 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.28.20:5700) Recv SETFORMAT cmd
2026-01-29 03:07:17.358 [INFO] ctrl_if_trx.py:201 (BTS@172.18.28.20:5700) TRXD header version 1 -> 1
2026-01-29 03:07:17.363 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.28.20:5700/1) Recv RXTUNE cmd
2026-01-29 03:07:17.363 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.28.20:5700/1) Recv TXTUNE cmd
2026-01-29 03:07:17.363 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.28.20:5700/1) Recv SETFORMAT cmd
2026-01-29 03:07:17.364 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.28.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:07:17.364 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 03:07:17.364 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.28.20:5700/1) Recv NOMTXPOWER cmd
2026-01-29 03:07:17.365 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.28.20:5700/1) Recv SETFORMAT cmd
2026-01-29 03:07:17.365 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.28.20:5700/1) TRXD header version 1 -> 1
2026-01-29 03:07:17.366 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.28.20:5700/2) Recv RXTUNE cmd
2026-01-29 03:07:17.366 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.28.20:5700/2) Recv TXTUNE cmd
2026-01-29 03:07:17.367 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.28.20:5700/2) Recv SETFORMAT cmd
2026-01-29 03:07:17.367 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.28.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:07:17.367 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 03:07:17.367 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.28.20:5700/2) Recv NOMTXPOWER cmd
2026-01-29 03:07:17.367 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.28.20:5700/2) Recv SETFORMAT cmd
2026-01-29 03:07:17.367 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.28.20:5700/2) TRXD header version 1 -> 1
2026-01-29 03:07:17.369 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.28.20:5700/3) Recv RXTUNE cmd
2026-01-29 03:07:17.369 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.28.20:5700/3) Recv TXTUNE cmd
2026-01-29 03:07:17.369 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.28.20:5700/3) Recv SETFORMAT cmd
2026-01-29 03:07:17.369 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.28.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:07:17.369 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 03:07:17.369 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.28.20:5700/3) Recv NOMTXPOWER cmd
2026-01-29 03:07:17.370 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.28.20:5700/3) Recv SETFORMAT cmd
2026-01-29 03:07:17.370 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.28.20:5700/3) TRXD header version 1 -> 1
2026-01-29 03:07:17.372 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.28.20:5700) Recv RXTUNE cmd
2026-01-29 03:07:17.372 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETTSC
2026-01-29 03:07:17.372 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETTSC
2026-01-29 03:07:17.372 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETTSC
2026-01-29 03:07:17.372 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.28.20:5700) Recv TXTUNE cmd
2026-01-29 03:07:17.373 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETRXGAIN
2026-01-29 03:07:17.373 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETRXGAIN
2026-01-29 03:07:17.373 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETRXGAIN
2026-01-29 03:07:17.373 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETTSC
2026-01-29 03:07:17.373 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:07:17.373 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:07:17.373 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.28.20:5700) Recv NOMTXPOWER cmd
2026-01-29 03:07:17.373 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:07:17.373 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:07:17.373 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:07:17.373 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.28.20:5700) Recv POWERON CMD
2026-01-29 03:07:17.373 [INFO] ctrl_if_trx.py:109 (BTS@172.18.28.20:5700) Starting transceiver...
2026-01-29 03:07:17.373 [INFO] transceiver.py:243 Starting clock generator
2026-01-29 03:07:17.373 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-01-29 03:07:17.373 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:07:17.373 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:07:17.373 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:07:17.374 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETRXGAIN
2026-01-29 03:07:17.374 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:07:17.374 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:07:17.374 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:07:17.374 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:07:17.374 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:07:17.374 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:07:17.374 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:07:17.374 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:07:17.374 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:07:17.374 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:07:17.374 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:07:17.374 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:07:17.374 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:07:17.374 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:07:17.374 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:07:17.374 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:07:17.374 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:07:17.374 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:07:17.374 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:07:17.374 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:07:17.374 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:07:17.374 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:07:17.375 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:07:17.375 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:07:17.378 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-01-29 03:07:17.861 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-01-29 03:07:17.899 [DEBUG] fake_trx.py:278 (BTS@172.18.28.20:5700) Recv FAKE_TOA cmd
2026-01-29 03:07:17.901 [DEBUG] fake_trx.py:297 (BTS@172.18.28.20:5700) Recv FAKE_RSSI cmd
2026-01-29 03:07:17.901 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:07:17.902 [DEBUG] fake_trx.py:322 (BTS@172.18.28.20:5700) Recv FAKE_CI cmd
2026-01-29 03:07:17.906 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 03:07:17.906 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 03:07:17.907 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 03:07:17.907 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 03:07:17.907 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 03:07:17.908 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 03:07:17.908 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.28.22:6700) Recv POWERON CMD
2026-01-29 03:07:17.908 [INFO] ctrl_if_trx.py:109 (MS@172.18.28.22:6700) Starting transceiver...
2026-01-29 03:07:18.339 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-01-29 03:07:18.376 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 03:07:18.376 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:07:18.377 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:07:18.380 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:07:18.817 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-01-29 03:07:19.294 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-01-29 03:07:19.377 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 03:07:19.377 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:07:19.378 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:07:19.382 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:07:19.773 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-01-29 03:07:20.251 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-01-29 03:07:20.378 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:07:20.379 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 03:07:20.379 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:07:20.383 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:07:20.729 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-01-29 03:07:21.207 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-01-29 03:07:21.379 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:07:21.379 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 03:07:21.380 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:07:21.384 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:07:21.685 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-01-29 03:07:22.163 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-01-29 03:07:22.380 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 03:07:22.380 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:07:22.381 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:07:22.384 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:07:22.641 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-01-29 03:07:23.118 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-01-29 03:07:23.595 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-01-29 03:07:24.073 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-01-29 03:07:24.551 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-01-29 03:07:25.029 [DEBUG] clck_gen.py:113 IND CLOCK 1632
2026-01-29 03:07:25.506 [DEBUG] clck_gen.py:113 IND CLOCK 1734
2026-01-29 03:07:25.985 [DEBUG] clck_gen.py:113 IND CLOCK 1836
2026-01-29 03:07:26.463 [DEBUG] clck_gen.py:113 IND CLOCK 1938
2026-01-29 03:07:26.826 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 03:07:26.826 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 03:07:26.832 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 03:07:26.832 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:07:26.832 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:07:26.832 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:07:26.836 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 03:07:26.836 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 03:07:26.836 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 03:07:26.836 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.28.20:5700) Recv POWEROFF cmd
2026-01-29 03:07:26.836 [INFO] ctrl_if_trx.py:117 (BTS@172.18.28.20:5700) Stopping transceiver...
2026-01-29 03:07:26.836 [INFO] transceiver.py:246 Stopping clock generator
2026-01-29 03:07:26.837 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 03:07:26.837 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=2020 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:07:26.837 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=2020 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:07:26.837 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=2020 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:07:26.837 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=2020 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:07:26.837 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=2020 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:07:26.837 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=2020 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:07:26.837 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=2020 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:07:26.837 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=2020 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:07:31.835 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.28.20:5700) Recv POWEROFF cmd
2026-01-29 03:07:31.836 [INFO] ctrl_if_trx.py:117 (BTS@172.18.28.20:5700) Stopping transceiver...
2026-01-29 03:07:31.837 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 03:07:31.839 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 03:07:31.839 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 03:07:31.840 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 03:07:31.848 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 03:07:31.850 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.28.20:5700) Recv SETFORMAT cmd
2026-01-29 03:07:31.850 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.28.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:07:31.851 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.28.20:5700) Recv SETFORMAT cmd
2026-01-29 03:07:31.851 [INFO] ctrl_if_trx.py:201 (BTS@172.18.28.20:5700) TRXD header version 1 -> 1
2026-01-29 03:07:31.855 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.28.20:5700/1) Recv RXTUNE cmd
2026-01-29 03:07:31.855 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.28.20:5700/1) Recv TXTUNE cmd
2026-01-29 03:07:31.856 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.28.20:5700/1) Recv SETFORMAT cmd
2026-01-29 03:07:31.856 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.28.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:07:31.856 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 03:07:31.857 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.28.20:5700/1) Recv NOMTXPOWER cmd
2026-01-29 03:07:31.857 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.28.20:5700/1) Recv SETFORMAT cmd
2026-01-29 03:07:31.857 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.28.20:5700/1) TRXD header version 1 -> 1
2026-01-29 03:07:31.858 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.28.20:5700/2) Recv RXTUNE cmd
2026-01-29 03:07:31.859 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.28.20:5700/2) Recv TXTUNE cmd
2026-01-29 03:07:31.859 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.28.20:5700/2) Recv SETFORMAT cmd
2026-01-29 03:07:31.859 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.28.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:07:31.859 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 03:07:31.859 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.28.20:5700/2) Recv NOMTXPOWER cmd
2026-01-29 03:07:31.859 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.28.20:5700/2) Recv SETFORMAT cmd
2026-01-29 03:07:31.860 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.28.20:5700/2) TRXD header version 1 -> 1
2026-01-29 03:07:31.861 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.28.20:5700/3) Recv RXTUNE cmd
2026-01-29 03:07:31.861 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.28.20:5700/3) Recv TXTUNE cmd
2026-01-29 03:07:31.861 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.28.20:5700/3) Recv SETFORMAT cmd
2026-01-29 03:07:31.861 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.28.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:07:31.861 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 03:07:31.861 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.28.20:5700/3) Recv NOMTXPOWER cmd
2026-01-29 03:07:31.862 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.28.20:5700/3) Recv SETFORMAT cmd
2026-01-29 03:07:31.862 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.28.20:5700/3) TRXD header version 1 -> 1
2026-01-29 03:07:31.864 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.28.20:5700) Recv RXTUNE cmd
2026-01-29 03:07:31.864 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETTSC
2026-01-29 03:07:31.864 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETTSC
2026-01-29 03:07:31.864 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETTSC
2026-01-29 03:07:31.864 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.28.20:5700) Recv TXTUNE cmd
2026-01-29 03:07:31.864 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETRXGAIN
2026-01-29 03:07:31.864 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETRXGAIN
2026-01-29 03:07:31.865 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETRXGAIN
2026-01-29 03:07:31.865 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETTSC
2026-01-29 03:07:31.865 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:07:31.865 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:07:31.865 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.28.20:5700) Recv NOMTXPOWER cmd
2026-01-29 03:07:31.865 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:07:31.865 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:07:31.865 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:07:31.865 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.28.20:5700) Recv POWERON CMD
2026-01-29 03:07:31.865 [INFO] ctrl_if_trx.py:109 (BTS@172.18.28.20:5700) Starting transceiver...
2026-01-29 03:07:31.865 [INFO] transceiver.py:243 Starting clock generator
2026-01-29 03:07:31.865 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-01-29 03:07:31.865 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:07:31.865 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:07:31.865 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:07:31.865 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETRXGAIN
2026-01-29 03:07:31.865 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:07:31.865 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:07:31.865 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:07:31.866 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:07:31.866 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:07:31.866 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:07:31.866 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:07:31.866 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:07:31.866 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:07:31.866 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:07:31.866 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:07:31.866 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:07:31.866 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:07:31.866 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:07:31.866 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:07:31.866 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:07:31.866 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:07:31.866 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:07:31.866 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:07:31.866 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:07:31.866 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:07:31.866 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:07:31.866 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:07:31.866 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:07:31.870 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-01-29 03:07:32.354 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-01-29 03:07:32.385 [DEBUG] fake_trx.py:278 (BTS@172.18.28.20:5700) Recv FAKE_TOA cmd
2026-01-29 03:07:32.386 [DEBUG] fake_trx.py:297 (BTS@172.18.28.20:5700) Recv FAKE_RSSI cmd
2026-01-29 03:07:32.387 [DEBUG] fake_trx.py:322 (BTS@172.18.28.20:5700) Recv FAKE_CI cmd
2026-01-29 03:07:32.387 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:07:32.391 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 03:07:32.391 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 03:07:32.391 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 03:07:32.391 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 03:07:32.392 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 03:07:32.392 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 03:07:32.392 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.28.22:6700) Recv POWERON CMD
2026-01-29 03:07:32.392 [INFO] ctrl_if_trx.py:109 (MS@172.18.28.22:6700) Starting transceiver...
2026-01-29 03:07:32.831 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-01-29 03:07:32.867 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 03:07:32.868 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:07:32.868 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:07:32.871 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:07:33.310 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-01-29 03:07:33.788 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-01-29 03:07:33.868 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 03:07:33.868 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:07:33.869 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:07:33.872 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:07:34.267 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-01-29 03:07:34.745 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-01-29 03:07:34.869 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:07:34.869 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:07:34.870 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 03:07:34.873 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:07:35.224 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-01-29 03:07:35.701 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-01-29 03:07:35.870 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 03:07:35.871 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:07:35.871 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:07:35.873 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:07:36.179 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-01-29 03:07:36.657 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-01-29 03:07:36.871 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 03:07:36.871 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:07:36.871 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:07:36.874 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:07:37.135 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-01-29 03:07:37.626 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-01-29 03:07:38.105 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-01-29 03:07:38.582 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-01-29 03:07:39.060 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-01-29 03:07:39.538 [DEBUG] clck_gen.py:113 IND CLOCK 1632
2026-01-29 03:07:40.015 [DEBUG] clck_gen.py:113 IND CLOCK 1734
2026-01-29 03:07:40.494 [DEBUG] clck_gen.py:113 IND CLOCK 1836
2026-01-29 03:07:40.971 [DEBUG] clck_gen.py:113 IND CLOCK 1938
2026-01-29 03:07:41.274 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 03:07:41.275 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 03:07:41.280 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 03:07:41.280 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:07:41.280 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:07:41.281 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:07:41.283 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 03:07:41.284 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 03:07:41.284 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 03:07:41.284 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 03:07:41.284 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.28.20:5700) Recv POWEROFF cmd
2026-01-29 03:07:41.284 [INFO] ctrl_if_trx.py:117 (BTS@172.18.28.20:5700) Stopping transceiver...
2026-01-29 03:07:41.284 [INFO] transceiver.py:246 Stopping clock generator
2026-01-29 03:07:41.284 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=2007 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:07:41.285 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=2007 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:07:41.285 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=2007 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:07:41.285 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=2007 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:07:41.285 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=2007 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:07:41.285 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=2007 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:07:41.285 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=2007 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:07:46.283 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.28.20:5700) Recv POWEROFF cmd
2026-01-29 03:07:46.283 [INFO] ctrl_if_trx.py:117 (BTS@172.18.28.20:5700) Stopping transceiver...
2026-01-29 03:07:46.284 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 03:07:46.285 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 03:07:46.285 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 03:07:46.286 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 03:07:46.290 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 03:07:46.292 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.28.20:5700) Recv SETFORMAT cmd
2026-01-29 03:07:46.292 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.28.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:07:46.293 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.28.20:5700) Recv SETFORMAT cmd
2026-01-29 03:07:46.293 [INFO] ctrl_if_trx.py:201 (BTS@172.18.28.20:5700) TRXD header version 1 -> 1
2026-01-29 03:07:46.296 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.28.20:5700/1) Recv RXTUNE cmd
2026-01-29 03:07:46.296 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.28.20:5700/1) Recv TXTUNE cmd
2026-01-29 03:07:46.297 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.28.20:5700/1) Recv SETFORMAT cmd
2026-01-29 03:07:46.297 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.28.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:07:46.297 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 03:07:46.298 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.28.20:5700/1) Recv NOMTXPOWER cmd
2026-01-29 03:07:46.298 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.28.20:5700/1) Recv SETFORMAT cmd
2026-01-29 03:07:46.298 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.28.20:5700/1) TRXD header version 1 -> 1
2026-01-29 03:07:46.299 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.28.20:5700/2) Recv RXTUNE cmd
2026-01-29 03:07:46.300 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.28.20:5700/2) Recv TXTUNE cmd
2026-01-29 03:07:46.300 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.28.20:5700/2) Recv SETFORMAT cmd
2026-01-29 03:07:46.300 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.28.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:07:46.300 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 03:07:46.300 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.28.20:5700/2) Recv NOMTXPOWER cmd
2026-01-29 03:07:46.300 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.28.20:5700/2) Recv SETFORMAT cmd
2026-01-29 03:07:46.300 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.28.20:5700/2) TRXD header version 1 -> 1
2026-01-29 03:07:46.302 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.28.20:5700/3) Recv RXTUNE cmd
2026-01-29 03:07:46.302 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.28.20:5700/3) Recv TXTUNE cmd
2026-01-29 03:07:46.302 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.28.20:5700/3) Recv SETFORMAT cmd
2026-01-29 03:07:46.302 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.28.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:07:46.302 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 03:07:46.302 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.28.20:5700/3) Recv NOMTXPOWER cmd
2026-01-29 03:07:46.302 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.28.20:5700/3) Recv SETFORMAT cmd
2026-01-29 03:07:46.302 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.28.20:5700/3) TRXD header version 1 -> 1
2026-01-29 03:07:46.305 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.28.20:5700) Recv RXTUNE cmd
2026-01-29 03:07:46.305 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETTSC
2026-01-29 03:07:46.305 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETTSC
2026-01-29 03:07:46.305 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.28.20:5700) Recv TXTUNE cmd
2026-01-29 03:07:46.305 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETTSC
2026-01-29 03:07:46.305 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETRXGAIN
2026-01-29 03:07:46.305 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETRXGAIN
2026-01-29 03:07:46.305 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETTSC
2026-01-29 03:07:46.305 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETRXGAIN
2026-01-29 03:07:46.305 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:07:46.305 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:07:46.305 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.28.20:5700) Recv NOMTXPOWER cmd
2026-01-29 03:07:46.306 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:07:46.306 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:07:46.306 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:07:46.306 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.28.20:5700) Recv POWERON CMD
2026-01-29 03:07:46.306 [INFO] ctrl_if_trx.py:109 (BTS@172.18.28.20:5700) Starting transceiver...
2026-01-29 03:07:46.306 [INFO] transceiver.py:243 Starting clock generator
2026-01-29 03:07:46.306 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-01-29 03:07:46.306 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:07:46.306 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:07:46.306 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:07:46.306 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETRXGAIN
2026-01-29 03:07:46.306 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:07:46.306 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:07:46.306 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:07:46.306 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:07:46.306 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:07:46.306 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:07:46.306 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:07:46.306 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:07:46.306 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:07:46.306 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:07:46.306 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:07:46.306 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:07:46.306 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:07:46.306 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:07:46.306 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:07:46.306 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:07:46.307 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:07:46.307 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:07:46.307 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:07:46.307 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:07:46.307 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:07:46.307 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:07:46.307 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:07:46.307 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:07:46.311 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-01-29 03:07:46.794 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-01-29 03:07:46.836 [DEBUG] fake_trx.py:278 (BTS@172.18.28.20:5700) Recv FAKE_TOA cmd
2026-01-29 03:07:46.839 [DEBUG] fake_trx.py:297 (BTS@172.18.28.20:5700) Recv FAKE_RSSI cmd
2026-01-29 03:07:46.839 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:07:46.841 [DEBUG] fake_trx.py:322 (BTS@172.18.28.20:5700) Recv FAKE_CI cmd
2026-01-29 03:07:46.849 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 03:07:46.849 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 03:07:46.849 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 03:07:46.849 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 03:07:46.850 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 03:07:46.850 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 03:07:46.850 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.28.22:6700) Recv POWERON CMD
2026-01-29 03:07:46.850 [INFO] ctrl_if_trx.py:109 (MS@172.18.28.22:6700) Starting transceiver...
2026-01-29 03:07:47.272 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-01-29 03:07:47.309 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:07:47.309 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 03:07:47.310 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:07:47.314 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:07:47.749 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-01-29 03:07:48.227 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-01-29 03:07:48.310 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 03:07:48.310 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:07:48.311 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:07:48.315 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:07:48.705 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-01-29 03:07:49.183 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-01-29 03:07:49.311 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:07:49.311 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:07:49.312 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 03:07:49.316 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:07:49.661 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-01-29 03:07:49.903 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.28.22:6700) Recv SETFH cmd
2026-01-29 03:07:49.904 [INFO] transceiver.py:201 (MS@172.18.28.22:6700) Frequency hopping configured: hsn=0, maio=1, ma_len=2
2026-01-29 03:07:49.904 [DEBUG] fake_trx.py:322 (BTS@172.18.28.20:5700) Recv FAKE_CI cmd
2026-01-29 03:07:49.904 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 03:07:49.904 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 03:07:50.139 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-01-29 03:07:50.313 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 03:07:50.313 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:07:50.313 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:07:50.317 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:07:50.617 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-01-29 03:07:50.940 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 03:07:50.940 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 03:07:50.941 [INFO] transceiver.py:205 (MS@172.18.28.22:6700) Frequency hopping disabled
2026-01-29 03:07:50.943 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:07:50.943 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 03:07:50.943 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:07:50.943 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:07:50.943 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:07:50.944 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 03:07:50.944 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 03:07:50.944 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 03:07:50.944 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 03:07:50.944 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.28.20:5700) Recv POWEROFF cmd
2026-01-29 03:07:50.944 [INFO] ctrl_if_trx.py:117 (BTS@172.18.28.20:5700) Stopping transceiver...
2026-01-29 03:07:50.944 [INFO] transceiver.py:246 Stopping clock generator
2026-01-29 03:07:55.947 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.28.20:5700) Recv POWEROFF cmd
2026-01-29 03:07:55.947 [INFO] ctrl_if_trx.py:117 (BTS@172.18.28.20:5700) Stopping transceiver...
2026-01-29 03:07:55.948 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 03:07:55.950 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 03:07:55.951 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 03:07:55.951 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 03:07:55.959 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 03:07:55.959 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.28.20:5700) Recv SETFORMAT cmd
2026-01-29 03:07:55.959 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.28.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:07:55.959 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.28.20:5700) Recv SETFORMAT cmd
2026-01-29 03:07:55.959 [INFO] ctrl_if_trx.py:201 (BTS@172.18.28.20:5700) TRXD header version 1 -> 1
2026-01-29 03:07:55.961 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.28.20:5700/1) Recv RXTUNE cmd
2026-01-29 03:07:55.961 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.28.20:5700/1) Recv TXTUNE cmd
2026-01-29 03:07:55.962 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.28.20:5700/1) Recv SETFORMAT cmd
2026-01-29 03:07:55.962 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.28.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:07:55.962 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 03:07:55.963 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.28.20:5700/1) Recv NOMTXPOWER cmd
2026-01-29 03:07:55.963 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.28.20:5700/1) Recv SETFORMAT cmd
2026-01-29 03:07:55.963 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.28.20:5700/1) TRXD header version 1 -> 1
2026-01-29 03:07:55.964 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.28.20:5700/2) Recv RXTUNE cmd
2026-01-29 03:07:55.964 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.28.20:5700/2) Recv TXTUNE cmd
2026-01-29 03:07:55.964 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.28.20:5700/2) Recv SETFORMAT cmd
2026-01-29 03:07:55.964 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.28.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:07:55.964 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 03:07:55.965 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.28.20:5700/2) Recv NOMTXPOWER cmd
2026-01-29 03:07:55.965 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.28.20:5700/2) Recv SETFORMAT cmd
2026-01-29 03:07:55.965 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.28.20:5700/2) TRXD header version 1 -> 1
2026-01-29 03:07:55.966 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.28.20:5700/3) Recv RXTUNE cmd
2026-01-29 03:07:55.966 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.28.20:5700/3) Recv TXTUNE cmd
2026-01-29 03:07:55.966 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.28.20:5700/3) Recv SETFORMAT cmd
2026-01-29 03:07:55.966 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.28.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:07:55.966 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 03:07:55.966 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.28.20:5700/3) Recv NOMTXPOWER cmd
2026-01-29 03:07:55.966 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.28.20:5700/3) Recv SETFORMAT cmd
2026-01-29 03:07:55.966 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.28.20:5700/3) TRXD header version 1 -> 1
2026-01-29 03:07:55.969 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.28.20:5700) Recv RXTUNE cmd
2026-01-29 03:07:55.969 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETTSC
2026-01-29 03:07:55.969 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETTSC
2026-01-29 03:07:55.969 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETTSC
2026-01-29 03:07:55.969 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.28.20:5700) Recv TXTUNE cmd
2026-01-29 03:07:55.969 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETRXGAIN
2026-01-29 03:07:55.969 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETRXGAIN
2026-01-29 03:07:55.969 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETRXGAIN
2026-01-29 03:07:55.969 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETTSC
2026-01-29 03:07:55.969 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:07:55.969 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:07:55.969 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.28.20:5700) Recv NOMTXPOWER cmd
2026-01-29 03:07:55.969 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:07:55.969 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:07:55.969 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:07:55.969 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.28.20:5700) Recv POWERON CMD
2026-01-29 03:07:55.969 [INFO] ctrl_if_trx.py:109 (BTS@172.18.28.20:5700) Starting transceiver...
2026-01-29 03:07:55.969 [INFO] transceiver.py:243 Starting clock generator
2026-01-29 03:07:55.969 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-01-29 03:07:55.970 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:07:55.970 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:07:55.970 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:07:55.970 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETRXGAIN
2026-01-29 03:07:55.970 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:07:55.970 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:07:55.970 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:07:55.970 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:07:55.970 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:07:55.970 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:07:55.970 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:07:55.970 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:07:55.970 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:07:55.970 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:07:55.970 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:07:55.970 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:07:55.970 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:07:55.970 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:07:55.970 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:07:55.970 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:07:55.970 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:07:55.970 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:07:55.970 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:07:55.970 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:07:55.970 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:07:55.970 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:07:55.970 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:07:55.971 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:07:55.974 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-01-29 03:07:56.459 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-01-29 03:07:56.500 [DEBUG] fake_trx.py:278 (BTS@172.18.28.20:5700) Recv FAKE_TOA cmd
2026-01-29 03:07:56.502 [DEBUG] fake_trx.py:297 (BTS@172.18.28.20:5700) Recv FAKE_RSSI cmd
2026-01-29 03:07:56.503 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:07:56.504 [DEBUG] fake_trx.py:322 (BTS@172.18.28.20:5700) Recv FAKE_CI cmd
2026-01-29 03:07:56.731 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 03:07:56.731 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:07:56.731 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:07:56.731 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:07:56.732 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 03:07:56.732 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 03:07:56.732 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 03:07:56.732 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.28.20:5700) Recv POWEROFF cmd
2026-01-29 03:07:56.732 [INFO] ctrl_if_trx.py:117 (BTS@172.18.28.20:5700) Stopping transceiver...
2026-01-29 03:07:56.732 [INFO] transceiver.py:246 Stopping clock generator
2026-01-29 03:07:56.732 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 03:07:56.732 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=163 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:07:56.732 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=163 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:07:56.732 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=163 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:07:56.732 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=163 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:07:56.732 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=163 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:07:56.732 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=163 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:07:56.732 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=163 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:07:56.732 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=163 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:08:01.737 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.28.20:5700) Recv POWEROFF cmd
2026-01-29 03:08:01.737 [INFO] ctrl_if_trx.py:117 (BTS@172.18.28.20:5700) Stopping transceiver...
2026-01-29 03:08:01.737 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 03:08:01.737 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 03:08:01.737 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 03:08:01.737 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 03:08:01.745 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 03:08:01.745 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.28.20:5700) Recv SETFORMAT cmd
2026-01-29 03:08:01.745 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.28.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:08:01.746 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.28.20:5700) Recv SETFORMAT cmd
2026-01-29 03:08:01.746 [INFO] ctrl_if_trx.py:201 (BTS@172.18.28.20:5700) TRXD header version 1 -> 1
2026-01-29 03:08:01.748 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.28.20:5700/1) Recv RXTUNE cmd
2026-01-29 03:08:01.749 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.28.20:5700/1) Recv TXTUNE cmd
2026-01-29 03:08:01.749 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.28.20:5700/1) Recv SETFORMAT cmd
2026-01-29 03:08:01.750 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.28.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:08:01.750 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 03:08:01.750 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.28.20:5700/1) Recv NOMTXPOWER cmd
2026-01-29 03:08:01.751 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.28.20:5700/1) Recv SETFORMAT cmd
2026-01-29 03:08:01.751 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.28.20:5700/1) TRXD header version 1 -> 1
2026-01-29 03:08:01.752 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.28.20:5700/2) Recv RXTUNE cmd
2026-01-29 03:08:01.752 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.28.20:5700/2) Recv TXTUNE cmd
2026-01-29 03:08:01.753 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.28.20:5700/2) Recv SETFORMAT cmd
2026-01-29 03:08:01.753 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.28.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:08:01.753 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 03:08:01.753 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.28.20:5700/2) Recv NOMTXPOWER cmd
2026-01-29 03:08:01.754 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.28.20:5700/2) Recv SETFORMAT cmd
2026-01-29 03:08:01.754 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.28.20:5700/2) TRXD header version 1 -> 1
2026-01-29 03:08:01.755 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.28.20:5700/3) Recv RXTUNE cmd
2026-01-29 03:08:01.755 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.28.20:5700/3) Recv TXTUNE cmd
2026-01-29 03:08:01.755 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.28.20:5700/3) Recv SETFORMAT cmd
2026-01-29 03:08:01.755 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.28.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:08:01.755 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 03:08:01.755 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.28.20:5700/3) Recv NOMTXPOWER cmd
2026-01-29 03:08:01.755 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.28.20:5700/3) Recv SETFORMAT cmd
2026-01-29 03:08:01.755 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.28.20:5700/3) TRXD header version 1 -> 1
2026-01-29 03:08:01.758 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.28.20:5700) Recv RXTUNE cmd
2026-01-29 03:08:01.758 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETTSC
2026-01-29 03:08:01.758 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETTSC
2026-01-29 03:08:01.758 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETTSC
2026-01-29 03:08:01.758 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.28.20:5700) Recv TXTUNE cmd
2026-01-29 03:08:01.758 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETRXGAIN
2026-01-29 03:08:01.758 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETRXGAIN
2026-01-29 03:08:01.758 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETRXGAIN
2026-01-29 03:08:01.759 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETTSC
2026-01-29 03:08:01.759 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:08:01.759 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:08:01.759 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.28.20:5700) Recv NOMTXPOWER cmd
2026-01-29 03:08:01.759 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:08:01.759 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:08:01.759 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:08:01.759 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.28.20:5700) Recv POWERON CMD
2026-01-29 03:08:01.759 [INFO] ctrl_if_trx.py:109 (BTS@172.18.28.20:5700) Starting transceiver...
2026-01-29 03:08:01.759 [INFO] transceiver.py:243 Starting clock generator
2026-01-29 03:08:01.759 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-01-29 03:08:01.759 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:08:01.759 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:08:01.759 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:08:01.759 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETRXGAIN
2026-01-29 03:08:01.759 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:08:01.759 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:08:01.759 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:08:01.759 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:08:01.759 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:08:01.759 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:08:01.760 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:08:01.760 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:08:01.760 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:08:01.760 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:08:01.760 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:08:01.760 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:08:01.760 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:08:01.760 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:08:01.760 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:08:01.760 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:08:01.760 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:08:01.760 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:08:01.760 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:08:01.760 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:08:01.760 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:08:01.760 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:08:01.760 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:08:01.760 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:08:01.764 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-01-29 03:08:02.248 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-01-29 03:08:02.282 [DEBUG] fake_trx.py:278 (BTS@172.18.28.20:5700) Recv FAKE_TOA cmd
2026-01-29 03:08:02.283 [DEBUG] fake_trx.py:297 (BTS@172.18.28.20:5700) Recv FAKE_RSSI cmd
2026-01-29 03:08:02.285 [DEBUG] fake_trx.py:322 (BTS@172.18.28.20:5700) Recv FAKE_CI cmd
2026-01-29 03:08:02.286 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:08:02.724 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-01-29 03:08:02.762 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 03:08:02.762 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:08:02.762 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:08:02.766 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:08:03.193 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-01-29 03:08:03.663 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-01-29 03:08:03.763 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:08:03.763 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 03:08:03.764 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:08:03.767 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:08:04.141 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-01-29 03:08:04.619 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-01-29 03:08:04.765 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:08:04.765 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 03:08:04.765 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:08:04.769 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:08:05.099 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-01-29 03:08:05.580 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-01-29 03:08:05.767 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 03:08:05.767 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:08:05.767 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:08:05.770 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:08:06.058 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-01-29 03:08:06.537 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-01-29 03:08:06.768 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:08:06.768 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 03:08:06.768 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:08:06.771 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:08:07.016 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-01-29 03:08:07.494 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-01-29 03:08:07.972 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-01-29 03:08:08.449 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-01-29 03:08:08.928 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-01-29 03:08:09.406 [DEBUG] clck_gen.py:113 IND CLOCK 1632
2026-01-29 03:08:09.885 [DEBUG] clck_gen.py:113 IND CLOCK 1734
2026-01-29 03:08:10.363 [DEBUG] clck_gen.py:113 IND CLOCK 1836
2026-01-29 03:08:10.841 [DEBUG] clck_gen.py:113 IND CLOCK 1938
2026-01-29 03:08:11.303 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:08:11.307 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 03:08:11.307 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:08:11.308 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:08:11.308 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:08:11.308 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 03:08:11.309 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 03:08:11.309 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 03:08:11.309 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 03:08:11.309 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.28.20:5700) Recv POWEROFF cmd
2026-01-29 03:08:11.309 [INFO] ctrl_if_trx.py:117 (BTS@172.18.28.20:5700) Stopping transceiver...
2026-01-29 03:08:11.309 [INFO] transceiver.py:246 Stopping clock generator
2026-01-29 03:08:11.309 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=2041 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:08:11.309 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=2041 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:08:11.309 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=2041 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:08:11.309 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=2041 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:08:11.309 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=2041 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:08:11.309 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=2041 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:08:11.309 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=2041 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:08:16.313 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.28.20:5700) Recv POWEROFF cmd
2026-01-29 03:08:16.313 [INFO] ctrl_if_trx.py:117 (BTS@172.18.28.20:5700) Stopping transceiver...
2026-01-29 03:08:16.313 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 03:08:16.313 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 03:08:16.313 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 03:08:16.313 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 03:08:16.321 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 03:08:16.321 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.28.20:5700) Recv SETFORMAT cmd
2026-01-29 03:08:16.321 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.28.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:08:16.321 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.28.20:5700) Recv SETFORMAT cmd
2026-01-29 03:08:16.321 [INFO] ctrl_if_trx.py:201 (BTS@172.18.28.20:5700) TRXD header version 1 -> 1
2026-01-29 03:08:16.323 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.28.20:5700/1) Recv RXTUNE cmd
2026-01-29 03:08:16.323 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.28.20:5700/1) Recv TXTUNE cmd
2026-01-29 03:08:16.323 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.28.20:5700/1) Recv SETFORMAT cmd
2026-01-29 03:08:16.323 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.28.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:08:16.323 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 03:08:16.323 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.28.20:5700/1) Recv NOMTXPOWER cmd
2026-01-29 03:08:16.324 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.28.20:5700/1) Recv SETFORMAT cmd
2026-01-29 03:08:16.324 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.28.20:5700/1) TRXD header version 1 -> 1
2026-01-29 03:08:16.325 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.28.20:5700/2) Recv RXTUNE cmd
2026-01-29 03:08:16.325 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.28.20:5700/2) Recv TXTUNE cmd
2026-01-29 03:08:16.325 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.28.20:5700/2) Recv SETFORMAT cmd
2026-01-29 03:08:16.325 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.28.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:08:16.325 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 03:08:16.325 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.28.20:5700/2) Recv NOMTXPOWER cmd
2026-01-29 03:08:16.325 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.28.20:5700/2) Recv SETFORMAT cmd
2026-01-29 03:08:16.325 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.28.20:5700/2) TRXD header version 1 -> 1
2026-01-29 03:08:16.327 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.28.20:5700/3) Recv RXTUNE cmd
2026-01-29 03:08:16.327 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.28.20:5700/3) Recv TXTUNE cmd
2026-01-29 03:08:16.327 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.28.20:5700/3) Recv SETFORMAT cmd
2026-01-29 03:08:16.327 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.28.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:08:16.327 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 03:08:16.327 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.28.20:5700/3) Recv NOMTXPOWER cmd
2026-01-29 03:08:16.327 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.28.20:5700/3) Recv SETFORMAT cmd
2026-01-29 03:08:16.327 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.28.20:5700/3) TRXD header version 1 -> 1
2026-01-29 03:08:16.329 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.28.20:5700) Recv RXTUNE cmd
2026-01-29 03:08:16.329 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETTSC
2026-01-29 03:08:16.329 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETTSC
2026-01-29 03:08:16.329 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETTSC
2026-01-29 03:08:16.329 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.28.20:5700) Recv TXTUNE cmd
2026-01-29 03:08:16.329 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETRXGAIN
2026-01-29 03:08:16.329 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETRXGAIN
2026-01-29 03:08:16.329 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETRXGAIN
2026-01-29 03:08:16.329 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETTSC
2026-01-29 03:08:16.329 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:08:16.329 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:08:16.329 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.28.20:5700) Recv NOMTXPOWER cmd
2026-01-29 03:08:16.329 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:08:16.329 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:08:16.329 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.28.20:5700) Recv POWERON CMD
2026-01-29 03:08:16.329 [INFO] ctrl_if_trx.py:109 (BTS@172.18.28.20:5700) Starting transceiver...
2026-01-29 03:08:16.329 [INFO] transceiver.py:243 Starting clock generator
2026-01-29 03:08:16.330 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-01-29 03:08:16.330 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:08:16.330 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:08:16.330 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:08:16.330 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETRXGAIN
2026-01-29 03:08:16.330 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:08:16.330 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:08:16.330 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:08:16.330 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:08:16.330 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:08:16.330 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:08:16.330 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:08:16.330 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:08:16.330 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:08:16.330 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:08:16.330 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:08:16.330 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:08:16.330 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:08:16.330 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:08:16.330 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:08:16.330 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:08:16.330 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:08:16.330 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:08:16.330 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:08:16.330 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:08:16.330 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:08:16.330 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:08:16.330 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:08:16.330 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:08:16.330 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:08:16.334 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-01-29 03:08:16.818 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-01-29 03:08:16.858 [DEBUG] fake_trx.py:278 (BTS@172.18.28.20:5700) Recv FAKE_TOA cmd
2026-01-29 03:08:16.860 [DEBUG] fake_trx.py:297 (BTS@172.18.28.20:5700) Recv FAKE_RSSI cmd
2026-01-29 03:08:16.861 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:08:16.862 [DEBUG] fake_trx.py:322 (BTS@172.18.28.20:5700) Recv FAKE_CI cmd
2026-01-29 03:08:17.295 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-01-29 03:08:17.333 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:08:17.333 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:08:17.333 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 03:08:17.335 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:08:17.776 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-01-29 03:08:18.254 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-01-29 03:08:18.334 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 03:08:18.335 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:08:18.335 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:08:18.336 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:08:18.734 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-01-29 03:08:19.215 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-01-29 03:08:19.335 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 03:08:19.335 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:08:19.336 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:08:19.337 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:08:19.695 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-01-29 03:08:20.176 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-01-29 03:08:20.336 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 03:08:20.336 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:08:20.336 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:08:20.338 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:08:20.656 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-01-29 03:08:21.135 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-01-29 03:08:21.337 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:08:21.337 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 03:08:21.338 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:08:21.339 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:08:21.614 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-01-29 03:08:22.094 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-01-29 03:08:22.573 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-01-29 03:08:23.051 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-01-29 03:08:23.531 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-01-29 03:08:24.013 [DEBUG] clck_gen.py:113 IND CLOCK 1632
2026-01-29 03:08:24.491 [DEBUG] clck_gen.py:113 IND CLOCK 1734
2026-01-29 03:08:24.968 [DEBUG] clck_gen.py:113 IND CLOCK 1836
2026-01-29 03:08:25.445 [DEBUG] clck_gen.py:113 IND CLOCK 1938
2026-01-29 03:08:25.879 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:08:25.884 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 03:08:25.884 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:08:25.884 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:08:25.885 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:08:25.888 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 03:08:25.888 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 03:08:25.888 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 03:08:25.888 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 03:08:25.888 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.28.20:5700) Recv POWEROFF cmd
2026-01-29 03:08:25.888 [INFO] ctrl_if_trx.py:117 (BTS@172.18.28.20:5700) Stopping transceiver...
2026-01-29 03:08:25.889 [INFO] transceiver.py:246 Stopping clock generator
2026-01-29 03:08:25.889 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=2036 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:08:25.889 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=2036 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:08:25.889 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=2036 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:08:25.889 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=2036 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:08:25.889 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=2036 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:08:25.890 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=2036 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:08:25.890 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=2036 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:08:30.890 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.28.20:5700) Recv POWEROFF cmd
2026-01-29 03:08:30.890 [INFO] ctrl_if_trx.py:117 (BTS@172.18.28.20:5700) Stopping transceiver...
2026-01-29 03:08:30.890 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 03:08:30.890 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 03:08:30.890 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 03:08:30.890 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 03:08:30.900 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 03:08:30.902 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.28.20:5700) Recv SETFORMAT cmd
2026-01-29 03:08:30.902 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.28.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:08:30.903 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.28.20:5700) Recv SETFORMAT cmd
2026-01-29 03:08:30.903 [INFO] ctrl_if_trx.py:201 (BTS@172.18.28.20:5700) TRXD header version 1 -> 1
2026-01-29 03:08:30.908 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.28.20:5700/1) Recv RXTUNE cmd
2026-01-29 03:08:30.909 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.28.20:5700/1) Recv TXTUNE cmd
2026-01-29 03:08:30.909 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.28.20:5700/1) Recv SETFORMAT cmd
2026-01-29 03:08:30.909 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.28.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:08:30.909 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 03:08:30.910 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.28.20:5700/1) Recv NOMTXPOWER cmd
2026-01-29 03:08:30.910 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.28.20:5700/1) Recv SETFORMAT cmd
2026-01-29 03:08:30.910 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.28.20:5700/1) TRXD header version 1 -> 1
2026-01-29 03:08:30.913 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.28.20:5700/2) Recv RXTUNE cmd
2026-01-29 03:08:30.914 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.28.20:5700/2) Recv TXTUNE cmd
2026-01-29 03:08:30.914 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.28.20:5700/2) Recv SETFORMAT cmd
2026-01-29 03:08:30.915 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.28.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:08:30.915 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 03:08:30.916 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.28.20:5700/2) Recv NOMTXPOWER cmd
2026-01-29 03:08:30.916 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.28.20:5700/2) Recv SETFORMAT cmd
2026-01-29 03:08:30.916 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.28.20:5700/2) TRXD header version 1 -> 1
2026-01-29 03:08:30.918 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.28.20:5700/3) Recv RXTUNE cmd
2026-01-29 03:08:30.918 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.28.20:5700/3) Recv TXTUNE cmd
2026-01-29 03:08:30.919 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.28.20:5700/3) Recv SETFORMAT cmd
2026-01-29 03:08:30.919 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.28.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:08:30.919 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 03:08:30.920 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.28.20:5700/3) Recv NOMTXPOWER cmd
2026-01-29 03:08:30.920 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.28.20:5700/3) Recv SETFORMAT cmd
2026-01-29 03:08:30.920 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.28.20:5700/3) TRXD header version 1 -> 1
2026-01-29 03:08:30.923 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.28.20:5700) Recv RXTUNE cmd
2026-01-29 03:08:30.923 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETTSC
2026-01-29 03:08:30.923 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETTSC
2026-01-29 03:08:30.923 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETTSC
2026-01-29 03:08:30.923 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.28.20:5700) Recv TXTUNE cmd
2026-01-29 03:08:30.924 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETRXGAIN
2026-01-29 03:08:30.924 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETRXGAIN
2026-01-29 03:08:30.924 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETRXGAIN
2026-01-29 03:08:30.924 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETTSC
2026-01-29 03:08:30.924 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:08:30.924 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:08:30.924 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.28.20:5700) Recv NOMTXPOWER cmd
2026-01-29 03:08:30.924 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:08:30.924 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:08:30.925 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.28.20:5700) Recv POWERON CMD
2026-01-29 03:08:30.925 [INFO] ctrl_if_trx.py:109 (BTS@172.18.28.20:5700) Starting transceiver...
2026-01-29 03:08:30.925 [INFO] transceiver.py:243 Starting clock generator
2026-01-29 03:08:30.925 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-01-29 03:08:30.925 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:08:30.925 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:08:30.925 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:08:30.925 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETRXGAIN
2026-01-29 03:08:30.925 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:08:30.925 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:08:30.925 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:08:30.925 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:08:30.925 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:08:30.926 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:08:30.926 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:08:30.926 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:08:30.926 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:08:30.926 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:08:30.926 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:08:30.926 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:08:30.926 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:08:30.926 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:08:30.926 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:08:30.926 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:08:30.926 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:08:30.926 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:08:30.926 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:08:30.926 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:08:30.926 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:08:30.926 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:08:30.926 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:08:30.926 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:08:30.926 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:08:30.930 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-01-29 03:08:31.414 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-01-29 03:08:31.458 [DEBUG] fake_trx.py:278 (BTS@172.18.28.20:5700) Recv FAKE_TOA cmd
2026-01-29 03:08:31.460 [DEBUG] fake_trx.py:297 (BTS@172.18.28.20:5700) Recv FAKE_RSSI cmd
2026-01-29 03:08:31.462 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:08:31.463 [DEBUG] fake_trx.py:322 (BTS@172.18.28.20:5700) Recv FAKE_CI cmd
2026-01-29 03:08:31.894 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-01-29 03:08:31.929 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:08:31.929 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 03:08:31.931 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:08:31.934 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:08:32.370 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-01-29 03:08:32.839 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-01-29 03:08:32.930 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 03:08:32.931 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:08:32.932 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:08:32.935 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:08:33.308 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-01-29 03:08:33.788 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-01-29 03:08:33.931 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:08:33.932 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 03:08:33.934 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:08:33.936 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:08:34.266 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-01-29 03:08:34.499 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:08:34.500 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 03:08:34.500 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:08:34.500 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:08:34.500 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:08:34.500 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 03:08:34.500 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 03:08:34.500 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 03:08:34.500 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 03:08:34.500 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.28.20:5700) Recv POWEROFF cmd
2026-01-29 03:08:34.500 [INFO] ctrl_if_trx.py:117 (BTS@172.18.28.20:5700) Stopping transceiver...
2026-01-29 03:08:34.500 [INFO] transceiver.py:246 Stopping clock generator
2026-01-29 03:08:39.504 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.28.20:5700) Recv POWEROFF cmd
2026-01-29 03:08:39.504 [INFO] ctrl_if_trx.py:117 (BTS@172.18.28.20:5700) Stopping transceiver...
2026-01-29 03:08:39.506 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 03:08:39.507 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 03:08:39.508 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 03:08:39.508 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 03:08:39.517 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 03:08:39.519 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.28.20:5700) Recv SETFORMAT cmd
2026-01-29 03:08:39.519 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.28.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:08:39.519 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.28.20:5700) Recv SETFORMAT cmd
2026-01-29 03:08:39.520 [INFO] ctrl_if_trx.py:201 (BTS@172.18.28.20:5700) TRXD header version 1 -> 1
2026-01-29 03:08:39.525 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.28.20:5700/1) Recv RXTUNE cmd
2026-01-29 03:08:39.525 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.28.20:5700/1) Recv TXTUNE cmd
2026-01-29 03:08:39.526 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.28.20:5700/1) Recv SETFORMAT cmd
2026-01-29 03:08:39.526 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.28.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:08:39.527 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 03:08:39.527 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.28.20:5700/1) Recv NOMTXPOWER cmd
2026-01-29 03:08:39.528 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.28.20:5700/1) Recv SETFORMAT cmd
2026-01-29 03:08:39.528 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.28.20:5700/1) TRXD header version 1 -> 1
2026-01-29 03:08:39.532 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.28.20:5700/2) Recv RXTUNE cmd
2026-01-29 03:08:39.532 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.28.20:5700/2) Recv TXTUNE cmd
2026-01-29 03:08:39.532 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.28.20:5700/2) Recv SETFORMAT cmd
2026-01-29 03:08:39.532 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.28.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:08:39.533 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 03:08:39.533 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.28.20:5700/2) Recv NOMTXPOWER cmd
2026-01-29 03:08:39.533 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.28.20:5700/2) Recv SETFORMAT cmd
2026-01-29 03:08:39.533 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.28.20:5700/2) TRXD header version 1 -> 1
2026-01-29 03:08:39.538 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.28.20:5700/3) Recv RXTUNE cmd
2026-01-29 03:08:39.538 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.28.20:5700/3) Recv TXTUNE cmd
2026-01-29 03:08:39.538 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.28.20:5700/3) Recv SETFORMAT cmd
2026-01-29 03:08:39.538 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.28.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:08:39.538 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 03:08:39.539 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.28.20:5700/3) Recv NOMTXPOWER cmd
2026-01-29 03:08:39.539 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.28.20:5700/3) Recv SETFORMAT cmd
2026-01-29 03:08:39.539 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.28.20:5700/3) TRXD header version 1 -> 1
2026-01-29 03:08:39.542 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.28.20:5700) Recv RXTUNE cmd
2026-01-29 03:08:39.542 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETTSC
2026-01-29 03:08:39.543 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETTSC
2026-01-29 03:08:39.543 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETTSC
2026-01-29 03:08:39.543 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.28.20:5700) Recv TXTUNE cmd
2026-01-29 03:08:39.543 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETRXGAIN
2026-01-29 03:08:39.543 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETRXGAIN
2026-01-29 03:08:39.543 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETRXGAIN
2026-01-29 03:08:39.543 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETTSC
2026-01-29 03:08:39.543 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:08:39.543 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:08:39.543 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.28.20:5700) Recv NOMTXPOWER cmd
2026-01-29 03:08:39.543 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:08:39.543 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:08:39.543 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.28.20:5700) Recv POWERON CMD
2026-01-29 03:08:39.543 [INFO] ctrl_if_trx.py:109 (BTS@172.18.28.20:5700) Starting transceiver...
2026-01-29 03:08:39.543 [INFO] transceiver.py:243 Starting clock generator
2026-01-29 03:08:39.543 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-01-29 03:08:39.543 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:08:39.543 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:08:39.543 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:08:39.543 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETRXGAIN
2026-01-29 03:08:39.543 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:08:39.543 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:08:39.543 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:08:39.543 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:08:39.543 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:08:39.543 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:08:39.544 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:08:39.544 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:08:39.544 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:08:39.544 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:08:39.544 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:08:39.544 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:08:39.544 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:08:39.544 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:08:39.544 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:08:39.544 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:08:39.544 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:08:39.544 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:08:39.544 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:08:39.544 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:08:39.544 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:08:39.544 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:08:39.544 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:08:39.544 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:08:39.544 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:08:39.548 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-01-29 03:08:40.033 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-01-29 03:08:40.074 [DEBUG] fake_trx.py:278 (BTS@172.18.28.20:5700) Recv FAKE_TOA cmd
2026-01-29 03:08:40.077 [DEBUG] fake_trx.py:297 (BTS@172.18.28.20:5700) Recv FAKE_RSSI cmd
2026-01-29 03:08:40.077 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:08:40.079 [DEBUG] fake_trx.py:322 (BTS@172.18.28.20:5700) Recv FAKE_CI cmd
2026-01-29 03:08:40.113 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 03:08:40.113 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 03:08:40.114 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 03:08:40.123 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 03:08:40.123 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 03:08:40.123 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 03:08:40.124 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.28.22:6700) Recv POWERON CMD
2026-01-29 03:08:40.124 [INFO] ctrl_if_trx.py:109 (MS@172.18.28.22:6700) Starting transceiver...
2026-01-29 03:08:40.176 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:08:40.182 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 03:08:40.182 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 03:08:40.183 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 03:08:40.183 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 03:08:40.510 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-01-29 03:08:40.514 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:08:40.517 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 03:08:40.519 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 03:08:40.519 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 03:08:40.526 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 03:08:40.526 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:08:40.526 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:08:40.526 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:08:40.528 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 03:08:40.528 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 03:08:40.528 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.28.20:5700) Recv POWEROFF cmd
2026-01-29 03:08:40.528 [INFO] ctrl_if_trx.py:117 (BTS@172.18.28.20:5700) Stopping transceiver...
2026-01-29 03:08:40.528 [INFO] transceiver.py:246 Stopping clock generator
2026-01-29 03:08:40.528 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 03:08:40.528 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 03:08:40.528 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=209 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:08:40.528 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=209 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:08:40.528 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=209 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:08:40.528 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=209 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:08:40.528 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=209 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:08:40.528 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=209 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:08:40.528 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=209 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:08:45.529 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.28.20:5700) Recv POWEROFF cmd
2026-01-29 03:08:45.529 [INFO] ctrl_if_trx.py:117 (BTS@172.18.28.20:5700) Stopping transceiver...
2026-01-29 03:08:45.531 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 03:08:45.532 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 03:08:45.533 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 03:08:45.533 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 03:08:45.538 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 03:08:45.539 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.28.20:5700) Recv SETFORMAT cmd
2026-01-29 03:08:45.540 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.28.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:08:45.540 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.28.20:5700) Recv SETFORMAT cmd
2026-01-29 03:08:45.540 [INFO] ctrl_if_trx.py:201 (BTS@172.18.28.20:5700) TRXD header version 1 -> 1
2026-01-29 03:08:45.543 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.28.20:5700/1) Recv RXTUNE cmd
2026-01-29 03:08:45.543 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.28.20:5700/1) Recv TXTUNE cmd
2026-01-29 03:08:45.543 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.28.20:5700/1) Recv SETFORMAT cmd
2026-01-29 03:08:45.543 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.28.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:08:45.543 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 03:08:45.543 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.28.20:5700/1) Recv NOMTXPOWER cmd
2026-01-29 03:08:45.544 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.28.20:5700/1) Recv SETFORMAT cmd
2026-01-29 03:08:45.544 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.28.20:5700/1) TRXD header version 1 -> 1
2026-01-29 03:08:45.546 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.28.20:5700/2) Recv RXTUNE cmd
2026-01-29 03:08:45.546 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.28.20:5700/2) Recv TXTUNE cmd
2026-01-29 03:08:45.547 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.28.20:5700/2) Recv SETFORMAT cmd
2026-01-29 03:08:45.547 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.28.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:08:45.547 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 03:08:45.547 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.28.20:5700/2) Recv NOMTXPOWER cmd
2026-01-29 03:08:45.547 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.28.20:5700/2) Recv SETFORMAT cmd
2026-01-29 03:08:45.547 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.28.20:5700/2) TRXD header version 1 -> 1
2026-01-29 03:08:45.549 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.28.20:5700/3) Recv RXTUNE cmd
2026-01-29 03:08:45.549 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.28.20:5700/3) Recv TXTUNE cmd
2026-01-29 03:08:45.549 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.28.20:5700/3) Recv SETFORMAT cmd
2026-01-29 03:08:45.550 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.28.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:08:45.550 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 03:08:45.550 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.28.20:5700/3) Recv NOMTXPOWER cmd
2026-01-29 03:08:45.550 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.28.20:5700/3) Recv SETFORMAT cmd
2026-01-29 03:08:45.550 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.28.20:5700/3) TRXD header version 1 -> 1
2026-01-29 03:08:45.554 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.28.20:5700) Recv RXTUNE cmd
2026-01-29 03:08:45.554 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETTSC
2026-01-29 03:08:45.554 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETTSC
2026-01-29 03:08:45.554 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETTSC
2026-01-29 03:08:45.554 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.28.20:5700) Recv TXTUNE cmd
2026-01-29 03:08:45.554 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETRXGAIN
2026-01-29 03:08:45.554 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETRXGAIN
2026-01-29 03:08:45.554 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETRXGAIN
2026-01-29 03:08:45.554 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETTSC
2026-01-29 03:08:45.554 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:08:45.554 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:08:45.554 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.28.20:5700) Recv NOMTXPOWER cmd
2026-01-29 03:08:45.555 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:08:45.555 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:08:45.555 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:08:45.555 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.28.20:5700) Recv POWERON CMD
2026-01-29 03:08:45.555 [INFO] ctrl_if_trx.py:109 (BTS@172.18.28.20:5700) Starting transceiver...
2026-01-29 03:08:45.555 [INFO] transceiver.py:243 Starting clock generator
2026-01-29 03:08:45.555 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-01-29 03:08:45.555 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:08:45.555 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:08:45.555 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:08:45.555 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETRXGAIN
2026-01-29 03:08:45.555 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:08:45.555 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:08:45.555 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:08:45.556 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:08:45.556 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:08:45.556 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:08:45.556 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:08:45.556 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:08:45.556 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:08:45.556 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:08:45.556 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:08:45.556 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:08:45.556 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:08:45.556 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:08:45.556 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:08:45.556 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:08:45.556 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:08:45.556 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:08:45.556 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:08:45.556 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:08:45.556 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:08:45.556 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:08:45.556 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:08:45.556 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:08:45.560 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-01-29 03:08:46.043 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-01-29 03:08:46.080 [DEBUG] fake_trx.py:278 (BTS@172.18.28.20:5700) Recv FAKE_TOA cmd
2026-01-29 03:08:46.081 [DEBUG] fake_trx.py:297 (BTS@172.18.28.20:5700) Recv FAKE_RSSI cmd
2026-01-29 03:08:46.082 [DEBUG] fake_trx.py:322 (BTS@172.18.28.20:5700) Recv FAKE_CI cmd
2026-01-29 03:08:46.083 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:08:46.094 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 03:08:46.094 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:08:46.094 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:08:46.094 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:08:46.097 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 03:08:46.098 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 03:08:46.098 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 03:08:46.098 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.28.20:5700) Recv POWEROFF cmd
2026-01-29 03:08:46.098 [INFO] ctrl_if_trx.py:117 (BTS@172.18.28.20:5700) Stopping transceiver...
2026-01-29 03:08:46.098 [INFO] transceiver.py:246 Stopping clock generator
2026-01-29 03:08:46.098 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 03:08:46.098 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=115 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:08:46.099 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=115 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:08:46.099 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=115 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:08:46.099 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=115 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:08:46.099 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=115 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:08:46.099 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=115 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:08:46.099 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=115 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:08:46.099 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=115 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:08:51.098 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.28.20:5700) Recv POWEROFF cmd
2026-01-29 03:08:51.098 [INFO] ctrl_if_trx.py:117 (BTS@172.18.28.20:5700) Stopping transceiver...
2026-01-29 03:08:51.102 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 03:08:51.102 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 03:08:51.102 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 03:08:51.102 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 03:08:51.110 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 03:08:51.112 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.28.20:5700) Recv SETFORMAT cmd
2026-01-29 03:08:51.112 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.28.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:08:51.112 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.28.20:5700) Recv SETFORMAT cmd
2026-01-29 03:08:51.112 [INFO] ctrl_if_trx.py:201 (BTS@172.18.28.20:5700) TRXD header version 1 -> 1
2026-01-29 03:08:51.117 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.28.20:5700/1) Recv RXTUNE cmd
2026-01-29 03:08:51.117 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.28.20:5700/1) Recv TXTUNE cmd
2026-01-29 03:08:51.117 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.28.20:5700/1) Recv SETFORMAT cmd
2026-01-29 03:08:51.117 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.28.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:08:51.117 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 03:08:51.117 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.28.20:5700/1) Recv NOMTXPOWER cmd
2026-01-29 03:08:51.118 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.28.20:5700/1) Recv SETFORMAT cmd
2026-01-29 03:08:51.118 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.28.20:5700/1) TRXD header version 1 -> 1
2026-01-29 03:08:51.121 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.28.20:5700/2) Recv RXTUNE cmd
2026-01-29 03:08:51.121 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.28.20:5700/2) Recv TXTUNE cmd
2026-01-29 03:08:51.121 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.28.20:5700/2) Recv SETFORMAT cmd
2026-01-29 03:08:51.121 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.28.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:08:51.121 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 03:08:51.121 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.28.20:5700/2) Recv NOMTXPOWER cmd
2026-01-29 03:08:51.121 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.28.20:5700/2) Recv SETFORMAT cmd
2026-01-29 03:08:51.121 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.28.20:5700/2) TRXD header version 1 -> 1
2026-01-29 03:08:51.124 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.28.20:5700/3) Recv RXTUNE cmd
2026-01-29 03:08:51.124 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.28.20:5700/3) Recv TXTUNE cmd
2026-01-29 03:08:51.124 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.28.20:5700/3) Recv SETFORMAT cmd
2026-01-29 03:08:51.124 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.28.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:08:51.124 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 03:08:51.124 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.28.20:5700/3) Recv NOMTXPOWER cmd
2026-01-29 03:08:51.125 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.28.20:5700/3) Recv SETFORMAT cmd
2026-01-29 03:08:51.125 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.28.20:5700/3) TRXD header version 1 -> 1
2026-01-29 03:08:51.128 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.28.20:5700) Recv RXTUNE cmd
2026-01-29 03:08:51.128 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETTSC
2026-01-29 03:08:51.128 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETTSC
2026-01-29 03:08:51.128 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETTSC
2026-01-29 03:08:51.128 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.28.20:5700) Recv TXTUNE cmd
2026-01-29 03:08:51.128 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETRXGAIN
2026-01-29 03:08:51.128 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETRXGAIN
2026-01-29 03:08:51.128 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETRXGAIN
2026-01-29 03:08:51.128 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETTSC
2026-01-29 03:08:51.128 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:08:51.128 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:08:51.128 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:08:51.128 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.28.20:5700) Recv NOMTXPOWER cmd
2026-01-29 03:08:51.128 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:08:51.128 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:08:51.128 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:08:51.128 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.28.20:5700) Recv POWERON CMD
2026-01-29 03:08:51.128 [INFO] ctrl_if_trx.py:109 (BTS@172.18.28.20:5700) Starting transceiver...
2026-01-29 03:08:51.129 [INFO] transceiver.py:243 Starting clock generator
2026-01-29 03:08:51.129 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-01-29 03:08:51.129 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:08:51.129 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:08:51.129 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:08:51.129 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETRXGAIN
2026-01-29 03:08:51.129 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:08:51.129 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:08:51.129 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:08:51.129 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:08:51.129 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:08:51.129 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:08:51.129 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:08:51.129 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:08:51.129 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:08:51.130 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:08:51.130 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:08:51.130 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:08:51.130 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:08:51.130 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:08:51.130 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:08:51.130 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:08:51.130 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:08:51.130 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:08:51.130 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:08:51.130 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:08:51.130 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:08:51.130 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:08:51.130 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:08:51.133 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-01-29 03:08:51.617 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-01-29 03:08:51.654 [DEBUG] fake_trx.py:278 (BTS@172.18.28.20:5700) Recv FAKE_TOA cmd
2026-01-29 03:08:51.656 [DEBUG] fake_trx.py:297 (BTS@172.18.28.20:5700) Recv FAKE_RSSI cmd
2026-01-29 03:08:51.657 [DEBUG] fake_trx.py:322 (BTS@172.18.28.20:5700) Recv FAKE_CI cmd
2026-01-29 03:08:51.658 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:08:52.095 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-01-29 03:08:52.132 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:08:52.133 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 03:08:52.133 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:08:52.136 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:08:52.574 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-01-29 03:08:53.055 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-01-29 03:08:53.134 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:08:53.134 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 03:08:53.134 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:08:53.137 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:08:53.535 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-01-29 03:08:53.674 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 03:08:53.674 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:08:53.675 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:08:53.675 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:08:53.676 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 03:08:53.676 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 03:08:53.676 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 03:08:53.676 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 03:08:53.676 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.28.20:5700) Recv POWEROFF cmd
2026-01-29 03:08:53.676 [INFO] ctrl_if_trx.py:117 (BTS@172.18.28.20:5700) Stopping transceiver...
2026-01-29 03:08:53.676 [INFO] transceiver.py:246 Stopping clock generator
2026-01-29 03:08:53.676 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=542 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:08:53.676 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=542 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:08:53.676 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=542 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:08:53.676 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=542 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:08:53.676 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=542 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:08:53.676 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=542 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:08:53.676 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=542 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:08:58.678 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.28.20:5700) Recv POWEROFF cmd
2026-01-29 03:08:58.678 [INFO] ctrl_if_trx.py:117 (BTS@172.18.28.20:5700) Stopping transceiver...
2026-01-29 03:08:58.680 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 03:08:58.681 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 03:08:58.682 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 03:08:58.683 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 03:08:58.690 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 03:08:58.691 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.28.20:5700) Recv SETFORMAT cmd
2026-01-29 03:08:58.691 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.28.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:08:58.691 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.28.20:5700) Recv SETFORMAT cmd
2026-01-29 03:08:58.691 [INFO] ctrl_if_trx.py:201 (BTS@172.18.28.20:5700) TRXD header version 1 -> 1
2026-01-29 03:08:58.693 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.28.20:5700/1) Recv RXTUNE cmd
2026-01-29 03:08:58.693 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.28.20:5700/1) Recv TXTUNE cmd
2026-01-29 03:08:58.693 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.28.20:5700/1) Recv SETFORMAT cmd
2026-01-29 03:08:58.693 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.28.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:08:58.694 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 03:08:58.694 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.28.20:5700/1) Recv NOMTXPOWER cmd
2026-01-29 03:08:58.694 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.28.20:5700/1) Recv SETFORMAT cmd
2026-01-29 03:08:58.695 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.28.20:5700/1) TRXD header version 1 -> 1
2026-01-29 03:08:58.695 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.28.20:5700/2) Recv RXTUNE cmd
2026-01-29 03:08:58.695 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.28.20:5700/2) Recv TXTUNE cmd
2026-01-29 03:08:58.696 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.28.20:5700/2) Recv SETFORMAT cmd
2026-01-29 03:08:58.696 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.28.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:08:58.696 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 03:08:58.696 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.28.20:5700/2) Recv NOMTXPOWER cmd
2026-01-29 03:08:58.696 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.28.20:5700/2) Recv SETFORMAT cmd
2026-01-29 03:08:58.696 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.28.20:5700/2) TRXD header version 1 -> 1
2026-01-29 03:08:58.698 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.28.20:5700/3) Recv RXTUNE cmd
2026-01-29 03:08:58.698 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.28.20:5700/3) Recv TXTUNE cmd
2026-01-29 03:08:58.698 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.28.20:5700/3) Recv SETFORMAT cmd
2026-01-29 03:08:58.698 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.28.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:08:58.698 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 03:08:58.698 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.28.20:5700/3) Recv NOMTXPOWER cmd
2026-01-29 03:08:58.698 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.28.20:5700/3) Recv SETFORMAT cmd
2026-01-29 03:08:58.698 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.28.20:5700/3) TRXD header version 1 -> 1
2026-01-29 03:08:58.700 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.28.20:5700) Recv RXTUNE cmd
2026-01-29 03:08:58.700 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETTSC
2026-01-29 03:08:58.700 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETTSC
2026-01-29 03:08:58.700 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETTSC
2026-01-29 03:08:58.700 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.28.20:5700) Recv TXTUNE cmd
2026-01-29 03:08:58.700 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETRXGAIN
2026-01-29 03:08:58.700 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETRXGAIN
2026-01-29 03:08:58.700 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETRXGAIN
2026-01-29 03:08:58.700 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETTSC
2026-01-29 03:08:58.700 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:08:58.700 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:08:58.700 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:08:58.701 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.28.20:5700) Recv NOMTXPOWER cmd
2026-01-29 03:08:58.701 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:08:58.701 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:08:58.701 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:08:58.701 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.28.20:5700) Recv POWERON CMD
2026-01-29 03:08:58.701 [INFO] ctrl_if_trx.py:109 (BTS@172.18.28.20:5700) Starting transceiver...
2026-01-29 03:08:58.701 [INFO] transceiver.py:243 Starting clock generator
2026-01-29 03:08:58.701 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-01-29 03:08:58.701 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:08:58.701 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:08:58.701 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:08:58.701 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETRXGAIN
2026-01-29 03:08:58.701 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:08:58.701 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:08:58.701 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:08:58.701 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:08:58.701 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:08:58.701 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:08:58.701 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:08:58.701 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:08:58.701 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:08:58.701 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:08:58.701 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:08:58.701 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:08:58.701 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:08:58.702 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:08:58.702 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:08:58.702 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:08:58.702 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:08:58.702 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:08:58.702 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:08:58.702 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:08:58.702 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:08:58.702 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:08:58.702 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:08:58.705 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-01-29 03:08:59.190 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-01-29 03:08:59.222 [DEBUG] fake_trx.py:278 (BTS@172.18.28.20:5700) Recv FAKE_TOA cmd
2026-01-29 03:08:59.223 [DEBUG] fake_trx.py:297 (BTS@172.18.28.20:5700) Recv FAKE_RSSI cmd
2026-01-29 03:08:59.224 [DEBUG] fake_trx.py:322 (BTS@172.18.28.20:5700) Recv FAKE_CI cmd
2026-01-29 03:08:59.224 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:08:59.225 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 03:08:59.225 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 03:08:59.225 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 03:08:59.226 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 03:08:59.226 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 03:08:59.226 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 03:08:59.226 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.28.22:6700) Recv POWERON CMD
2026-01-29 03:08:59.226 [INFO] ctrl_if_trx.py:109 (MS@172.18.28.22:6700) Starting transceiver...
2026-01-29 03:08:59.668 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-01-29 03:08:59.704 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 03:08:59.704 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:08:59.704 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:08:59.705 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:09:00.143 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-01-29 03:09:00.621 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-01-29 03:09:00.705 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 03:09:00.705 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:09:00.705 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:09:00.706 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:09:01.099 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-01-29 03:09:01.577 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-01-29 03:09:01.705 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 03:09:01.706 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:09:01.706 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:09:01.706 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:09:02.055 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-01-29 03:09:02.075 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 03:09:02.075 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 03:09:02.079 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 03:09:02.079 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:09:02.080 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:09:02.080 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:09:02.080 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 03:09:02.081 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 03:09:02.081 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 03:09:02.081 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.28.20:5700) Recv POWEROFF cmd
2026-01-29 03:09:02.081 [INFO] ctrl_if_trx.py:117 (BTS@172.18.28.20:5700) Stopping transceiver...
2026-01-29 03:09:02.081 [INFO] transceiver.py:246 Stopping clock generator
2026-01-29 03:09:02.081 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 03:09:02.081 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=721 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:09:02.081 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=721 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:09:02.081 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=721 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:09:02.081 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=721 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:09:02.081 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=721 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:09:02.081 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=721 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:09:02.081 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=721 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:09:07.083 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.28.20:5700) Recv POWEROFF cmd
2026-01-29 03:09:07.083 [INFO] ctrl_if_trx.py:117 (BTS@172.18.28.20:5700) Stopping transceiver...
2026-01-29 03:09:07.085 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 03:09:07.087 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 03:09:07.087 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 03:09:07.087 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 03:09:07.097 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 03:09:07.099 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.28.20:5700) Recv SETFORMAT cmd
2026-01-29 03:09:07.099 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.28.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:09:07.100 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.28.20:5700) Recv SETFORMAT cmd
2026-01-29 03:09:07.100 [INFO] ctrl_if_trx.py:201 (BTS@172.18.28.20:5700) TRXD header version 1 -> 1
2026-01-29 03:09:07.103 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.28.20:5700/1) Recv RXTUNE cmd
2026-01-29 03:09:07.104 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.28.20:5700/1) Recv TXTUNE cmd
2026-01-29 03:09:07.104 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.28.20:5700/1) Recv SETFORMAT cmd
2026-01-29 03:09:07.104 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.28.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:09:07.105 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 03:09:07.105 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.28.20:5700/1) Recv NOMTXPOWER cmd
2026-01-29 03:09:07.106 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.28.20:5700/1) Recv SETFORMAT cmd
2026-01-29 03:09:07.106 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.28.20:5700/1) TRXD header version 1 -> 1
2026-01-29 03:09:07.107 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.28.20:5700/2) Recv RXTUNE cmd
2026-01-29 03:09:07.107 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.28.20:5700/2) Recv TXTUNE cmd
2026-01-29 03:09:07.108 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.28.20:5700/2) Recv SETFORMAT cmd
2026-01-29 03:09:07.108 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.28.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:09:07.108 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 03:09:07.109 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.28.20:5700/2) Recv NOMTXPOWER cmd
2026-01-29 03:09:07.109 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.28.20:5700/2) Recv SETFORMAT cmd
2026-01-29 03:09:07.109 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.28.20:5700/2) TRXD header version 1 -> 1
2026-01-29 03:09:07.110 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.28.20:5700/3) Recv RXTUNE cmd
2026-01-29 03:09:07.110 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.28.20:5700/3) Recv TXTUNE cmd
2026-01-29 03:09:07.110 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.28.20:5700/3) Recv SETFORMAT cmd
2026-01-29 03:09:07.111 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.28.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:09:07.111 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 03:09:07.111 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.28.20:5700/3) Recv NOMTXPOWER cmd
2026-01-29 03:09:07.111 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.28.20:5700/3) Recv SETFORMAT cmd
2026-01-29 03:09:07.111 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.28.20:5700/3) TRXD header version 1 -> 1
2026-01-29 03:09:07.114 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.28.20:5700) Recv RXTUNE cmd
2026-01-29 03:09:07.114 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETTSC
2026-01-29 03:09:07.114 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETTSC
2026-01-29 03:09:07.114 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETTSC
2026-01-29 03:09:07.114 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.28.20:5700) Recv TXTUNE cmd
2026-01-29 03:09:07.114 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETRXGAIN
2026-01-29 03:09:07.114 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETRXGAIN
2026-01-29 03:09:07.114 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETRXGAIN
2026-01-29 03:09:07.114 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETTSC
2026-01-29 03:09:07.114 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:09:07.114 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:09:07.114 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.28.20:5700) Recv NOMTXPOWER cmd
2026-01-29 03:09:07.114 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:09:07.114 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:09:07.114 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:09:07.114 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.28.20:5700) Recv POWERON CMD
2026-01-29 03:09:07.114 [INFO] ctrl_if_trx.py:109 (BTS@172.18.28.20:5700) Starting transceiver...
2026-01-29 03:09:07.114 [INFO] transceiver.py:243 Starting clock generator
2026-01-29 03:09:07.115 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-01-29 03:09:07.115 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:09:07.115 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:09:07.115 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:09:07.115 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETRXGAIN
2026-01-29 03:09:07.115 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:09:07.115 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:09:07.115 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:09:07.115 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:09:07.115 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:09:07.115 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:09:07.115 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:09:07.115 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:09:07.115 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:09:07.115 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:09:07.116 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:09:07.116 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:09:07.116 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:09:07.116 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:09:07.116 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:09:07.116 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:09:07.116 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:09:07.116 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:09:07.116 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:09:07.116 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:09:07.116 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:09:07.116 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:09:07.116 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:09:07.116 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:09:07.120 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-01-29 03:09:07.603 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-01-29 03:09:07.647 [DEBUG] fake_trx.py:278 (BTS@172.18.28.20:5700) Recv FAKE_TOA cmd
2026-01-29 03:09:07.650 [DEBUG] fake_trx.py:297 (BTS@172.18.28.20:5700) Recv FAKE_RSSI cmd
2026-01-29 03:09:07.651 [DEBUG] fake_trx.py:322 (BTS@172.18.28.20:5700) Recv FAKE_CI cmd
2026-01-29 03:09:07.652 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:09:07.655 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 03:09:07.655 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 03:09:07.655 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 03:09:07.656 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 03:09:07.656 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 03:09:07.656 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 03:09:07.656 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.28.22:6700) Recv POWERON CMD
2026-01-29 03:09:07.656 [INFO] ctrl_if_trx.py:109 (MS@172.18.28.22:6700) Starting transceiver...
2026-01-29 03:09:08.081 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-01-29 03:09:08.117 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 03:09:08.118 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:09:08.119 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:09:08.123 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:09:08.559 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-01-29 03:09:09.036 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-01-29 03:09:09.119 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 03:09:09.119 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:09:09.120 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:09:09.125 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:09:09.514 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-01-29 03:09:09.769 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 03:09:09.769 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 03:09:09.772 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 03:09:09.772 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:09:09.772 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:09:09.772 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:09:09.773 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 03:09:09.773 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 03:09:09.773 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 03:09:09.773 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 03:09:09.773 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.28.20:5700) Recv POWEROFF cmd
2026-01-29 03:09:09.773 [INFO] ctrl_if_trx.py:117 (BTS@172.18.28.20:5700) Stopping transceiver...
2026-01-29 03:09:09.773 [INFO] transceiver.py:246 Stopping clock generator
2026-01-29 03:09:09.773 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=568 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:09:09.773 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=568 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:09:09.773 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=568 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:09:09.773 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=568 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:09:09.773 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=568 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:09:09.773 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=568 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:09:09.773 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=568 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:09:14.775 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.28.20:5700) Recv POWEROFF cmd
2026-01-29 03:09:14.776 [INFO] ctrl_if_trx.py:117 (BTS@172.18.28.20:5700) Stopping transceiver...
2026-01-29 03:09:14.777 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 03:09:14.779 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 03:09:14.780 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 03:09:14.780 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 03:09:14.784 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 03:09:14.786 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.28.20:5700) Recv SETFORMAT cmd
2026-01-29 03:09:14.786 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.28.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:09:14.786 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.28.20:5700) Recv SETFORMAT cmd
2026-01-29 03:09:14.787 [INFO] ctrl_if_trx.py:201 (BTS@172.18.28.20:5700) TRXD header version 1 -> 1
2026-01-29 03:09:14.788 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.28.20:5700/1) Recv RXTUNE cmd
2026-01-29 03:09:14.789 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.28.20:5700/1) Recv TXTUNE cmd
2026-01-29 03:09:14.789 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.28.20:5700/1) Recv SETFORMAT cmd
2026-01-29 03:09:14.790 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.28.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:09:14.790 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 03:09:14.790 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.28.20:5700/1) Recv NOMTXPOWER cmd
2026-01-29 03:09:14.791 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.28.20:5700/1) Recv SETFORMAT cmd
2026-01-29 03:09:14.791 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.28.20:5700/1) TRXD header version 1 -> 1
2026-01-29 03:09:14.792 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.28.20:5700/2) Recv RXTUNE cmd
2026-01-29 03:09:14.792 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.28.20:5700/2) Recv TXTUNE cmd
2026-01-29 03:09:14.792 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.28.20:5700/2) Recv SETFORMAT cmd
2026-01-29 03:09:14.792 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.28.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:09:14.793 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 03:09:14.793 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.28.20:5700/2) Recv NOMTXPOWER cmd
2026-01-29 03:09:14.793 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.28.20:5700/2) Recv SETFORMAT cmd
2026-01-29 03:09:14.793 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.28.20:5700/2) TRXD header version 1 -> 1
2026-01-29 03:09:14.795 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.28.20:5700/3) Recv RXTUNE cmd
2026-01-29 03:09:14.795 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.28.20:5700/3) Recv TXTUNE cmd
2026-01-29 03:09:14.795 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.28.20:5700/3) Recv SETFORMAT cmd
2026-01-29 03:09:14.795 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.28.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:09:14.795 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 03:09:14.795 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.28.20:5700/3) Recv NOMTXPOWER cmd
2026-01-29 03:09:14.796 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.28.20:5700/3) Recv SETFORMAT cmd
2026-01-29 03:09:14.796 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.28.20:5700/3) TRXD header version 1 -> 1
2026-01-29 03:09:14.799 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.28.20:5700) Recv RXTUNE cmd
2026-01-29 03:09:14.799 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETTSC
2026-01-29 03:09:14.799 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETTSC
2026-01-29 03:09:14.799 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETTSC
2026-01-29 03:09:14.799 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.28.20:5700) Recv TXTUNE cmd
2026-01-29 03:09:14.799 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETRXGAIN
2026-01-29 03:09:14.799 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETRXGAIN
2026-01-29 03:09:14.799 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETRXGAIN
2026-01-29 03:09:14.799 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETTSC
2026-01-29 03:09:14.799 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:09:14.799 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:09:14.799 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.28.20:5700) Recv NOMTXPOWER cmd
2026-01-29 03:09:14.799 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:09:14.799 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:09:14.799 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:09:14.799 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.28.20:5700) Recv POWERON CMD
2026-01-29 03:09:14.799 [INFO] ctrl_if_trx.py:109 (BTS@172.18.28.20:5700) Starting transceiver...
2026-01-29 03:09:14.799 [INFO] transceiver.py:243 Starting clock generator
2026-01-29 03:09:14.800 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-01-29 03:09:14.800 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:09:14.800 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:09:14.800 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:09:14.800 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETRXGAIN
2026-01-29 03:09:14.800 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:09:14.800 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:09:14.800 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:09:14.800 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:09:14.800 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:09:14.800 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:09:14.800 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:09:14.800 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:09:14.801 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:09:14.801 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:09:14.801 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:09:14.801 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:09:14.801 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:09:14.801 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:09:14.801 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:09:14.801 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:09:14.801 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:09:14.801 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:09:14.801 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:09:14.801 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:09:14.801 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:09:14.801 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:09:14.801 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:09:14.801 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:09:14.804 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-01-29 03:09:15.289 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-01-29 03:09:15.328 [DEBUG] fake_trx.py:278 (BTS@172.18.28.20:5700) Recv FAKE_TOA cmd
2026-01-29 03:09:15.331 [DEBUG] fake_trx.py:297 (BTS@172.18.28.20:5700) Recv FAKE_RSSI cmd
2026-01-29 03:09:15.333 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:09:15.333 [DEBUG] fake_trx.py:322 (BTS@172.18.28.20:5700) Recv FAKE_CI cmd
2026-01-29 03:09:15.342 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 03:09:15.342 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 03:09:15.343 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 03:09:15.344 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 03:09:15.344 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 03:09:15.345 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 03:09:15.345 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.28.22:6700) Recv POWERON CMD
2026-01-29 03:09:15.345 [INFO] ctrl_if_trx.py:109 (MS@172.18.28.22:6700) Starting transceiver...
2026-01-29 03:09:15.766 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-01-29 03:09:15.803 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:09:15.804 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 03:09:15.804 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:09:15.807 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:09:16.243 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-01-29 03:09:16.722 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-01-29 03:09:16.804 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 03:09:16.804 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:09:16.805 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:09:16.808 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:09:17.200 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-01-29 03:09:17.678 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-01-29 03:09:17.805 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 03:09:17.805 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:09:17.805 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:09:17.808 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:09:18.155 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-01-29 03:09:18.175 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 03:09:18.175 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 03:09:18.182 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 03:09:18.182 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:09:18.182 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:09:18.182 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:09:18.185 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 03:09:18.186 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 03:09:18.186 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 03:09:18.186 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 03:09:18.186 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.28.20:5700) Recv POWEROFF cmd
2026-01-29 03:09:18.186 [INFO] ctrl_if_trx.py:117 (BTS@172.18.28.20:5700) Stopping transceiver...
2026-01-29 03:09:18.186 [INFO] transceiver.py:246 Stopping clock generator
2026-01-29 03:09:18.186 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=721 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:09:18.186 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=721 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:09:18.186 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=722 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:09:18.186 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=722 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:09:18.186 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=722 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:09:18.186 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=722 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:09:18.186 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=722 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:09:18.186 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=722 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:09:18.186 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=722 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:09:18.186 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=722 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:09:23.186 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.28.20:5700) Recv POWEROFF cmd
2026-01-29 03:09:23.186 [INFO] ctrl_if_trx.py:117 (BTS@172.18.28.20:5700) Stopping transceiver...
2026-01-29 03:09:23.188 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 03:09:23.189 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 03:09:23.190 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 03:09:23.190 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 03:09:23.198 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 03:09:23.200 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.28.20:5700) Recv SETFORMAT cmd
2026-01-29 03:09:23.200 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.28.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:09:23.201 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.28.20:5700) Recv SETFORMAT cmd
2026-01-29 03:09:23.201 [INFO] ctrl_if_trx.py:201 (BTS@172.18.28.20:5700) TRXD header version 1 -> 1
2026-01-29 03:09:23.205 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.28.20:5700/1) Recv RXTUNE cmd
2026-01-29 03:09:23.205 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.28.20:5700/1) Recv TXTUNE cmd
2026-01-29 03:09:23.206 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.28.20:5700/1) Recv SETFORMAT cmd
2026-01-29 03:09:23.206 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.28.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:09:23.206 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 03:09:23.207 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.28.20:5700/1) Recv NOMTXPOWER cmd
2026-01-29 03:09:23.207 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.28.20:5700/1) Recv SETFORMAT cmd
2026-01-29 03:09:23.207 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.28.20:5700/1) TRXD header version 1 -> 1
2026-01-29 03:09:23.208 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.28.20:5700/2) Recv RXTUNE cmd
2026-01-29 03:09:23.208 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.28.20:5700/2) Recv TXTUNE cmd
2026-01-29 03:09:23.208 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.28.20:5700/2) Recv SETFORMAT cmd
2026-01-29 03:09:23.208 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.28.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:09:23.208 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 03:09:23.209 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.28.20:5700/2) Recv NOMTXPOWER cmd
2026-01-29 03:09:23.209 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.28.20:5700/2) Recv SETFORMAT cmd
2026-01-29 03:09:23.209 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.28.20:5700/2) TRXD header version 1 -> 1
2026-01-29 03:09:23.211 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.28.20:5700/3) Recv RXTUNE cmd
2026-01-29 03:09:23.211 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.28.20:5700/3) Recv TXTUNE cmd
2026-01-29 03:09:23.211 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.28.20:5700/3) Recv SETFORMAT cmd
2026-01-29 03:09:23.211 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.28.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:09:23.211 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 03:09:23.211 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.28.20:5700/3) Recv NOMTXPOWER cmd
2026-01-29 03:09:23.211 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.28.20:5700/3) Recv SETFORMAT cmd
2026-01-29 03:09:23.211 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.28.20:5700/3) TRXD header version 1 -> 1
2026-01-29 03:09:23.214 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.28.20:5700) Recv RXTUNE cmd
2026-01-29 03:09:23.214 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETTSC
2026-01-29 03:09:23.214 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETTSC
2026-01-29 03:09:23.214 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETTSC
2026-01-29 03:09:23.214 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.28.20:5700) Recv TXTUNE cmd
2026-01-29 03:09:23.214 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETRXGAIN
2026-01-29 03:09:23.214 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETRXGAIN
2026-01-29 03:09:23.214 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETRXGAIN
2026-01-29 03:09:23.214 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETTSC
2026-01-29 03:09:23.214 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:09:23.214 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:09:23.214 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:09:23.214 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.28.20:5700) Recv NOMTXPOWER cmd
2026-01-29 03:09:23.214 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:09:23.214 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:09:23.214 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:09:23.214 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.28.20:5700) Recv POWERON CMD
2026-01-29 03:09:23.214 [INFO] ctrl_if_trx.py:109 (BTS@172.18.28.20:5700) Starting transceiver...
2026-01-29 03:09:23.214 [INFO] transceiver.py:243 Starting clock generator
2026-01-29 03:09:23.214 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-01-29 03:09:23.215 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:09:23.215 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:09:23.215 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:09:23.215 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETRXGAIN
2026-01-29 03:09:23.215 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:09:23.215 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:09:23.215 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:09:23.215 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:09:23.215 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:09:23.215 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:09:23.215 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:09:23.215 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:09:23.215 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:09:23.215 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:09:23.215 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:09:23.215 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:09:23.215 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:09:23.215 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:09:23.215 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:09:23.215 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:09:23.215 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:09:23.215 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:09:23.215 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:09:23.215 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:09:23.216 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:09:23.216 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:09:23.216 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:09:23.219 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-01-29 03:09:23.701 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-01-29 03:09:23.744 [DEBUG] fake_trx.py:278 (BTS@172.18.28.20:5700) Recv FAKE_TOA cmd
2026-01-29 03:09:23.746 [DEBUG] fake_trx.py:297 (BTS@172.18.28.20:5700) Recv FAKE_RSSI cmd
2026-01-29 03:09:23.748 [DEBUG] fake_trx.py:322 (BTS@172.18.28.20:5700) Recv FAKE_CI cmd
2026-01-29 03:09:23.748 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:09:23.755 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 03:09:23.755 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 03:09:23.755 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 03:09:23.757 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 03:09:23.757 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 03:09:23.757 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 03:09:23.757 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.28.22:6700) Recv POWERON CMD
2026-01-29 03:09:23.757 [INFO] ctrl_if_trx.py:109 (MS@172.18.28.22:6700) Starting transceiver...
2026-01-29 03:09:24.178 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-01-29 03:09:24.217 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 03:09:24.217 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:09:24.219 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:09:24.220 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:09:24.656 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-01-29 03:09:25.134 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-01-29 03:09:25.217 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 03:09:25.218 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:09:25.220 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:09:25.222 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:09:25.612 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-01-29 03:09:25.868 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 03:09:25.868 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 03:09:25.875 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 03:09:25.876 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:09:25.876 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:09:25.876 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:09:25.879 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 03:09:25.879 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 03:09:25.879 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 03:09:25.880 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.28.20:5700) Recv POWEROFF cmd
2026-01-29 03:09:25.880 [INFO] ctrl_if_trx.py:117 (BTS@172.18.28.20:5700) Stopping transceiver...
2026-01-29 03:09:25.880 [INFO] transceiver.py:246 Stopping clock generator
2026-01-29 03:09:25.880 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 03:09:25.880 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=569 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:09:25.880 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=569 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:09:25.881 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=569 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:09:25.881 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=569 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:09:25.881 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=569 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:09:25.881 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=569 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:09:25.881 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=569 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:09:25.881 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=570 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:09:25.881 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=570 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:09:25.881 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=570 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:09:25.881 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=570 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:09:25.881 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=570 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:09:25.881 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=570 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:09:25.882 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=570 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:09:25.882 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=570 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:09:30.879 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.28.20:5700) Recv POWEROFF cmd
2026-01-29 03:09:30.879 [INFO] ctrl_if_trx.py:117 (BTS@172.18.28.20:5700) Stopping transceiver...
2026-01-29 03:09:30.880 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 03:09:30.882 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 03:09:30.883 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 03:09:30.883 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 03:09:30.892 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 03:09:30.893 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.28.20:5700) Recv SETFORMAT cmd
2026-01-29 03:09:30.893 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.28.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:09:30.893 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.28.20:5700) Recv SETFORMAT cmd
2026-01-29 03:09:30.894 [INFO] ctrl_if_trx.py:201 (BTS@172.18.28.20:5700) TRXD header version 1 -> 1
2026-01-29 03:09:30.897 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.28.20:5700/1) Recv RXTUNE cmd
2026-01-29 03:09:30.897 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.28.20:5700/1) Recv TXTUNE cmd
2026-01-29 03:09:30.898 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.28.20:5700/1) Recv SETFORMAT cmd
2026-01-29 03:09:30.898 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.28.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:09:30.898 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 03:09:30.899 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.28.20:5700/1) Recv NOMTXPOWER cmd
2026-01-29 03:09:30.899 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.28.20:5700/1) Recv SETFORMAT cmd
2026-01-29 03:09:30.899 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.28.20:5700/1) TRXD header version 1 -> 1
2026-01-29 03:09:30.900 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.28.20:5700/2) Recv RXTUNE cmd
2026-01-29 03:09:30.901 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.28.20:5700/2) Recv TXTUNE cmd
2026-01-29 03:09:30.901 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.28.20:5700/2) Recv SETFORMAT cmd
2026-01-29 03:09:30.901 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.28.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:09:30.901 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 03:09:30.902 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.28.20:5700/2) Recv NOMTXPOWER cmd
2026-01-29 03:09:30.902 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.28.20:5700/2) Recv SETFORMAT cmd
2026-01-29 03:09:30.902 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.28.20:5700/2) TRXD header version 1 -> 1
2026-01-29 03:09:30.904 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.28.20:5700/3) Recv RXTUNE cmd
2026-01-29 03:09:30.904 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.28.20:5700/3) Recv TXTUNE cmd
2026-01-29 03:09:30.904 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.28.20:5700/3) Recv SETFORMAT cmd
2026-01-29 03:09:30.904 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.28.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:09:30.904 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 03:09:30.904 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.28.20:5700/3) Recv NOMTXPOWER cmd
2026-01-29 03:09:30.904 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.28.20:5700/3) Recv SETFORMAT cmd
2026-01-29 03:09:30.905 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.28.20:5700/3) TRXD header version 1 -> 1
2026-01-29 03:09:30.907 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.28.20:5700) Recv RXTUNE cmd
2026-01-29 03:09:30.907 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETTSC
2026-01-29 03:09:30.907 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETTSC
2026-01-29 03:09:30.908 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETTSC
2026-01-29 03:09:30.908 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.28.20:5700) Recv TXTUNE cmd
2026-01-29 03:09:30.908 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETRXGAIN
2026-01-29 03:09:30.908 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETRXGAIN
2026-01-29 03:09:30.908 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETRXGAIN
2026-01-29 03:09:30.908 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETTSC
2026-01-29 03:09:30.908 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:09:30.908 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:09:30.908 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.28.20:5700) Recv NOMTXPOWER cmd
2026-01-29 03:09:30.908 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:09:30.908 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:09:30.908 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:09:30.908 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.28.20:5700) Recv POWERON CMD
2026-01-29 03:09:30.908 [INFO] ctrl_if_trx.py:109 (BTS@172.18.28.20:5700) Starting transceiver...
2026-01-29 03:09:30.908 [INFO] transceiver.py:243 Starting clock generator
2026-01-29 03:09:30.908 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-01-29 03:09:30.908 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:09:30.909 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:09:30.909 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:09:30.909 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETRXGAIN
2026-01-29 03:09:30.909 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:09:30.909 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:09:30.909 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:09:30.909 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:09:30.909 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:09:30.909 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:09:30.909 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:09:30.909 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:09:30.909 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:09:30.909 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:09:30.909 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:09:30.909 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:09:30.909 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:09:30.909 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:09:30.910 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:09:30.910 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:09:30.910 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:09:30.910 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:09:30.910 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:09:30.910 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:09:30.910 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:09:30.910 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:09:30.910 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:09:30.910 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:09:30.913 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-01-29 03:09:31.396 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-01-29 03:09:31.436 [DEBUG] fake_trx.py:278 (BTS@172.18.28.20:5700) Recv FAKE_TOA cmd
2026-01-29 03:09:31.438 [DEBUG] fake_trx.py:297 (BTS@172.18.28.20:5700) Recv FAKE_RSSI cmd
2026-01-29 03:09:31.440 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:09:31.441 [DEBUG] fake_trx.py:322 (BTS@172.18.28.20:5700) Recv FAKE_CI cmd
2026-01-29 03:09:31.450 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 03:09:31.450 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 03:09:31.451 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 03:09:31.451 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 03:09:31.451 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 03:09:31.452 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 03:09:31.452 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.28.22:6700) Recv POWERON CMD
2026-01-29 03:09:31.452 [INFO] ctrl_if_trx.py:109 (MS@172.18.28.22:6700) Starting transceiver...
2026-01-29 03:09:31.874 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-01-29 03:09:31.911 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 03:09:31.912 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:09:31.914 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:09:31.917 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:09:32.352 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-01-29 03:09:32.830 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-01-29 03:09:32.912 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 03:09:32.912 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:09:32.915 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:09:32.918 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:09:33.307 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-01-29 03:09:33.785 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-01-29 03:09:33.913 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 03:09:33.914 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:09:33.917 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:09:33.919 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:09:34.262 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-01-29 03:09:34.740 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-01-29 03:09:34.915 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 03:09:34.915 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:09:34.918 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:09:34.920 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:09:35.218 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-01-29 03:09:35.237 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 03:09:35.237 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 03:09:35.241 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 03:09:35.241 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:09:35.241 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:09:35.241 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:09:35.242 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 03:09:35.242 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 03:09:35.242 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 03:09:35.242 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 03:09:35.242 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.28.20:5700) Recv POWEROFF cmd
2026-01-29 03:09:35.242 [INFO] ctrl_if_trx.py:117 (BTS@172.18.28.20:5700) Stopping transceiver...
2026-01-29 03:09:35.242 [INFO] transceiver.py:246 Stopping clock generator
2026-01-29 03:09:35.242 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=925 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:09:35.242 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=925 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:09:35.242 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=925 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:09:35.242 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=925 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:09:40.245 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.28.20:5700) Recv POWEROFF cmd
2026-01-29 03:09:40.245 [INFO] ctrl_if_trx.py:117 (BTS@172.18.28.20:5700) Stopping transceiver...
2026-01-29 03:09:40.247 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 03:09:40.248 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 03:09:40.249 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 03:09:40.249 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 03:09:40.254 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 03:09:40.255 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.28.20:5700) Recv SETFORMAT cmd
2026-01-29 03:09:40.256 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.28.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:09:40.256 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.28.20:5700) Recv SETFORMAT cmd
2026-01-29 03:09:40.256 [INFO] ctrl_if_trx.py:201 (BTS@172.18.28.20:5700) TRXD header version 1 -> 1
2026-01-29 03:09:40.259 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.28.20:5700/1) Recv RXTUNE cmd
2026-01-29 03:09:40.260 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.28.20:5700/1) Recv TXTUNE cmd
2026-01-29 03:09:40.260 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.28.20:5700/1) Recv SETFORMAT cmd
2026-01-29 03:09:40.260 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.28.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:09:40.261 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 03:09:40.261 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.28.20:5700/1) Recv NOMTXPOWER cmd
2026-01-29 03:09:40.261 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.28.20:5700/1) Recv SETFORMAT cmd
2026-01-29 03:09:40.261 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.28.20:5700/1) TRXD header version 1 -> 1
2026-01-29 03:09:40.262 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.28.20:5700/2) Recv RXTUNE cmd
2026-01-29 03:09:40.262 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.28.20:5700/2) Recv TXTUNE cmd
2026-01-29 03:09:40.263 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.28.20:5700/2) Recv SETFORMAT cmd
2026-01-29 03:09:40.263 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.28.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:09:40.263 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 03:09:40.263 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.28.20:5700/2) Recv NOMTXPOWER cmd
2026-01-29 03:09:40.264 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.28.20:5700/2) Recv SETFORMAT cmd
2026-01-29 03:09:40.264 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.28.20:5700/2) TRXD header version 1 -> 1
2026-01-29 03:09:40.265 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.28.20:5700/3) Recv RXTUNE cmd
2026-01-29 03:09:40.265 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.28.20:5700/3) Recv TXTUNE cmd
2026-01-29 03:09:40.265 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.28.20:5700/3) Recv SETFORMAT cmd
2026-01-29 03:09:40.265 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.28.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:09:40.265 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 03:09:40.265 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.28.20:5700/3) Recv NOMTXPOWER cmd
2026-01-29 03:09:40.265 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.28.20:5700/3) Recv SETFORMAT cmd
2026-01-29 03:09:40.265 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.28.20:5700/3) TRXD header version 1 -> 1
2026-01-29 03:09:40.268 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.28.20:5700) Recv RXTUNE cmd
2026-01-29 03:09:40.268 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETTSC
2026-01-29 03:09:40.268 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETTSC
2026-01-29 03:09:40.268 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETTSC
2026-01-29 03:09:40.268 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.28.20:5700) Recv TXTUNE cmd
2026-01-29 03:09:40.268 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETRXGAIN
2026-01-29 03:09:40.268 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETRXGAIN
2026-01-29 03:09:40.268 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETRXGAIN
2026-01-29 03:09:40.268 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETTSC
2026-01-29 03:09:40.268 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:09:40.268 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:09:40.268 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:09:40.268 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.28.20:5700) Recv NOMTXPOWER cmd
2026-01-29 03:09:40.268 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:09:40.268 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:09:40.268 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:09:40.268 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.28.20:5700) Recv POWERON CMD
2026-01-29 03:09:40.268 [INFO] ctrl_if_trx.py:109 (BTS@172.18.28.20:5700) Starting transceiver...
2026-01-29 03:09:40.268 [INFO] transceiver.py:243 Starting clock generator
2026-01-29 03:09:40.268 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-01-29 03:09:40.269 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:09:40.269 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:09:40.269 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:09:40.269 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETRXGAIN
2026-01-29 03:09:40.269 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:09:40.269 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:09:40.269 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:09:40.269 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:09:40.269 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:09:40.269 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:09:40.269 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:09:40.269 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:09:40.269 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:09:40.269 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:09:40.269 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:09:40.269 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:09:40.269 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:09:40.269 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:09:40.269 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:09:40.269 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:09:40.269 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:09:40.269 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:09:40.269 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:09:40.269 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:09:40.269 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:09:40.270 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:09:40.270 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:09:40.273 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-01-29 03:09:40.758 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-01-29 03:09:40.798 [DEBUG] fake_trx.py:278 (BTS@172.18.28.20:5700) Recv FAKE_TOA cmd
2026-01-29 03:09:40.801 [DEBUG] fake_trx.py:297 (BTS@172.18.28.20:5700) Recv FAKE_RSSI cmd
2026-01-29 03:09:40.803 [DEBUG] fake_trx.py:322 (BTS@172.18.28.20:5700) Recv FAKE_CI cmd
2026-01-29 03:09:40.803 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:09:40.810 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 03:09:40.810 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 03:09:40.810 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 03:09:40.811 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 03:09:40.812 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 03:09:40.812 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 03:09:40.812 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.28.22:6700) Recv POWERON CMD
2026-01-29 03:09:40.812 [INFO] ctrl_if_trx.py:109 (MS@172.18.28.22:6700) Starting transceiver...
2026-01-29 03:09:41.236 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-01-29 03:09:41.271 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 03:09:41.271 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:09:41.273 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:09:41.276 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:09:41.714 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-01-29 03:09:42.191 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-01-29 03:09:42.272 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 03:09:42.272 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:09:42.274 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:09:42.278 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:09:42.668 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-01-29 03:09:43.146 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-01-29 03:09:43.273 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 03:09:43.273 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:09:43.275 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:09:43.279 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:09:43.624 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-01-29 03:09:43.879 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 03:09:43.879 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 03:09:43.885 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 03:09:43.885 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:09:43.886 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:09:43.886 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:09:43.889 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 03:09:43.890 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 03:09:43.890 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 03:09:43.890 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 03:09:43.890 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.28.20:5700) Recv POWEROFF cmd
2026-01-29 03:09:43.890 [INFO] ctrl_if_trx.py:117 (BTS@172.18.28.20:5700) Stopping transceiver...
2026-01-29 03:09:43.890 [INFO] transceiver.py:246 Stopping clock generator
2026-01-29 03:09:43.890 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=772 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:09:43.891 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=772 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:09:43.891 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=772 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:09:43.891 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=772 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:09:43.891 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=772 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:09:43.891 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=772 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:09:43.891 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=773 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:09:43.891 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=773 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:09:43.891 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=773 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:09:43.891 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=773 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:09:43.891 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=773 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:09:43.891 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=773 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:09:43.892 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=773 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:09:43.892 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=773 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:09:48.889 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.28.20:5700) Recv POWEROFF cmd
2026-01-29 03:09:48.889 [INFO] ctrl_if_trx.py:117 (BTS@172.18.28.20:5700) Stopping transceiver...
2026-01-29 03:09:48.891 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 03:09:48.892 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 03:09:48.893 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 03:09:48.893 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 03:09:48.902 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 03:09:48.903 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.28.20:5700) Recv SETFORMAT cmd
2026-01-29 03:09:48.903 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.28.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:09:48.903 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.28.20:5700) Recv SETFORMAT cmd
2026-01-29 03:09:48.903 [INFO] ctrl_if_trx.py:201 (BTS@172.18.28.20:5700) TRXD header version 1 -> 1
2026-01-29 03:09:48.907 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.28.20:5700/1) Recv RXTUNE cmd
2026-01-29 03:09:48.907 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.28.20:5700/1) Recv TXTUNE cmd
2026-01-29 03:09:48.907 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.28.20:5700/1) Recv SETFORMAT cmd
2026-01-29 03:09:48.908 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.28.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:09:48.908 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 03:09:48.908 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.28.20:5700/1) Recv NOMTXPOWER cmd
2026-01-29 03:09:48.909 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.28.20:5700/1) Recv SETFORMAT cmd
2026-01-29 03:09:48.909 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.28.20:5700/1) TRXD header version 1 -> 1
2026-01-29 03:09:48.910 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.28.20:5700/2) Recv RXTUNE cmd
2026-01-29 03:09:48.910 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.28.20:5700/2) Recv TXTUNE cmd
2026-01-29 03:09:48.910 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.28.20:5700/2) Recv SETFORMAT cmd
2026-01-29 03:09:48.910 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.28.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:09:48.910 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 03:09:48.910 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.28.20:5700/2) Recv NOMTXPOWER cmd
2026-01-29 03:09:48.910 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.28.20:5700/2) Recv SETFORMAT cmd
2026-01-29 03:09:48.910 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.28.20:5700/2) TRXD header version 1 -> 1
2026-01-29 03:09:48.912 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.28.20:5700/3) Recv RXTUNE cmd
2026-01-29 03:09:48.912 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.28.20:5700/3) Recv TXTUNE cmd
2026-01-29 03:09:48.912 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.28.20:5700/3) Recv SETFORMAT cmd
2026-01-29 03:09:48.912 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.28.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:09:48.912 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 03:09:48.913 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.28.20:5700/3) Recv NOMTXPOWER cmd
2026-01-29 03:09:48.913 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.28.20:5700/3) Recv SETFORMAT cmd
2026-01-29 03:09:48.913 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.28.20:5700/3) TRXD header version 1 -> 1
2026-01-29 03:09:48.915 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.28.20:5700) Recv RXTUNE cmd
2026-01-29 03:09:48.915 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETTSC
2026-01-29 03:09:48.915 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETTSC
2026-01-29 03:09:48.915 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETTSC
2026-01-29 03:09:48.915 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.28.20:5700) Recv TXTUNE cmd
2026-01-29 03:09:48.915 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETRXGAIN
2026-01-29 03:09:48.915 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETRXGAIN
2026-01-29 03:09:48.916 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETRXGAIN
2026-01-29 03:09:48.916 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETTSC
2026-01-29 03:09:48.916 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:09:48.916 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:09:48.916 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.28.20:5700) Recv NOMTXPOWER cmd
2026-01-29 03:09:48.916 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:09:48.916 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:09:48.916 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:09:48.916 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.28.20:5700) Recv POWERON CMD
2026-01-29 03:09:48.916 [INFO] ctrl_if_trx.py:109 (BTS@172.18.28.20:5700) Starting transceiver...
2026-01-29 03:09:48.916 [INFO] transceiver.py:243 Starting clock generator
2026-01-29 03:09:48.916 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-01-29 03:09:48.916 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:09:48.916 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:09:48.916 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:09:48.916 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETRXGAIN
2026-01-29 03:09:48.916 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:09:48.916 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:09:48.916 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:09:48.916 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:09:48.916 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:09:48.917 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:09:48.917 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:09:48.917 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:09:48.917 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:09:48.917 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:09:48.917 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:09:48.917 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:09:48.917 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:09:48.917 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:09:48.917 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:09:48.917 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:09:48.917 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:09:48.917 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:09:48.917 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:09:48.917 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:09:48.917 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:09:48.917 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:09:48.917 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:09:48.917 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:09:48.921 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-01-29 03:09:49.404 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-01-29 03:09:49.440 [DEBUG] fake_trx.py:278 (BTS@172.18.28.20:5700) Recv FAKE_TOA cmd
2026-01-29 03:09:49.441 [DEBUG] fake_trx.py:297 (BTS@172.18.28.20:5700) Recv FAKE_RSSI cmd
2026-01-29 03:09:49.442 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:09:49.443 [DEBUG] fake_trx.py:322 (BTS@172.18.28.20:5700) Recv FAKE_CI cmd
2026-01-29 03:09:49.886 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-01-29 03:09:49.919 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 03:09:49.919 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:09:49.921 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:09:49.923 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:09:50.367 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-01-29 03:09:50.848 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-01-29 03:09:50.920 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 03:09:50.920 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:09:50.921 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:09:50.925 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:09:51.319 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-01-29 03:09:51.457 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 03:09:51.457 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:09:51.458 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:09:51.458 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:09:51.461 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 03:09:51.461 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 03:09:51.461 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.28.20:5700) Recv POWEROFF cmd
2026-01-29 03:09:51.461 [INFO] ctrl_if_trx.py:117 (BTS@172.18.28.20:5700) Stopping transceiver...
2026-01-29 03:09:51.461 [INFO] transceiver.py:246 Stopping clock generator
2026-01-29 03:09:51.462 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 03:09:51.462 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 03:09:51.462 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=543 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:09:51.462 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=543 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:09:51.462 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=543 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:09:51.462 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=543 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:09:51.462 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=543 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:09:51.462 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=543 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:09:51.462 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=543 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:09:56.462 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.28.20:5700) Recv POWEROFF cmd
2026-01-29 03:09:56.462 [INFO] ctrl_if_trx.py:117 (BTS@172.18.28.20:5700) Stopping transceiver...
2026-01-29 03:09:56.462 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 03:09:56.462 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 03:09:56.462 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 03:09:56.462 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 03:09:56.470 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 03:09:56.471 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.28.20:5700) Recv SETFORMAT cmd
2026-01-29 03:09:56.471 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.28.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:09:56.472 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.28.20:5700) Recv SETFORMAT cmd
2026-01-29 03:09:56.472 [INFO] ctrl_if_trx.py:201 (BTS@172.18.28.20:5700) TRXD header version 1 -> 1
2026-01-29 03:09:56.475 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.28.20:5700/1) Recv RXTUNE cmd
2026-01-29 03:09:56.475 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.28.20:5700/1) Recv TXTUNE cmd
2026-01-29 03:09:56.476 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.28.20:5700/1) Recv SETFORMAT cmd
2026-01-29 03:09:56.476 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.28.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:09:56.476 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 03:09:56.477 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.28.20:5700/1) Recv NOMTXPOWER cmd
2026-01-29 03:09:56.477 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.28.20:5700/1) Recv SETFORMAT cmd
2026-01-29 03:09:56.477 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.28.20:5700/1) TRXD header version 1 -> 1
2026-01-29 03:09:56.479 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.28.20:5700/2) Recv RXTUNE cmd
2026-01-29 03:09:56.479 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.28.20:5700/2) Recv TXTUNE cmd
2026-01-29 03:09:56.480 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.28.20:5700/2) Recv SETFORMAT cmd
2026-01-29 03:09:56.480 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.28.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:09:56.480 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 03:09:56.480 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.28.20:5700/2) Recv NOMTXPOWER cmd
2026-01-29 03:09:56.480 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.28.20:5700/2) Recv SETFORMAT cmd
2026-01-29 03:09:56.480 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.28.20:5700/2) TRXD header version 1 -> 1
2026-01-29 03:09:56.482 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.28.20:5700/3) Recv RXTUNE cmd
2026-01-29 03:09:56.483 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.28.20:5700/3) Recv TXTUNE cmd
2026-01-29 03:09:56.483 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.28.20:5700/3) Recv SETFORMAT cmd
2026-01-29 03:09:56.483 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.28.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:09:56.483 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 03:09:56.483 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.28.20:5700/3) Recv NOMTXPOWER cmd
2026-01-29 03:09:56.483 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.28.20:5700/3) Recv SETFORMAT cmd
2026-01-29 03:09:56.483 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.28.20:5700/3) TRXD header version 1 -> 1
2026-01-29 03:09:56.486 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.28.20:5700) Recv RXTUNE cmd
2026-01-29 03:09:56.486 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETTSC
2026-01-29 03:09:56.487 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETTSC
2026-01-29 03:09:56.487 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETTSC
2026-01-29 03:09:56.487 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.28.20:5700) Recv TXTUNE cmd
2026-01-29 03:09:56.487 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETRXGAIN
2026-01-29 03:09:56.487 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETRXGAIN
2026-01-29 03:09:56.487 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETRXGAIN
2026-01-29 03:09:56.487 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETTSC
2026-01-29 03:09:56.487 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:09:56.487 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:09:56.487 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.28.20:5700) Recv NOMTXPOWER cmd
2026-01-29 03:09:56.487 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:09:56.487 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:09:56.487 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:09:56.487 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.28.20:5700) Recv POWERON CMD
2026-01-29 03:09:56.487 [INFO] ctrl_if_trx.py:109 (BTS@172.18.28.20:5700) Starting transceiver...
2026-01-29 03:09:56.487 [INFO] transceiver.py:243 Starting clock generator
2026-01-29 03:09:56.487 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-01-29 03:09:56.488 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:09:56.488 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:09:56.488 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:09:56.488 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETRXGAIN
2026-01-29 03:09:56.488 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:09:56.488 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:09:56.488 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:09:56.488 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:09:56.488 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:09:56.488 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:09:56.488 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:09:56.488 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:09:56.488 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:09:56.488 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:09:56.489 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:09:56.489 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:09:56.489 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:09:56.489 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:09:56.489 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:09:56.489 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:09:56.489 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:09:56.489 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:09:56.489 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:09:56.489 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:09:56.489 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:09:56.489 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:09:56.489 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:09:56.489 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:09:56.492 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-01-29 03:09:56.970 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-01-29 03:09:57.003 [DEBUG] fake_trx.py:278 (BTS@172.18.28.20:5700) Recv FAKE_TOA cmd
2026-01-29 03:09:57.004 [DEBUG] fake_trx.py:297 (BTS@172.18.28.20:5700) Recv FAKE_RSSI cmd
2026-01-29 03:09:57.004 [DEBUG] fake_trx.py:322 (BTS@172.18.28.20:5700) Recv FAKE_CI cmd
2026-01-29 03:09:57.005 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:09:57.011 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 03:09:57.011 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 03:09:57.011 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 03:09:57.014 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:09:57.016 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:09:57.439 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-01-29 03:09:57.491 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 03:09:57.491 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:09:57.493 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:09:57.496 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:09:57.915 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-01-29 03:09:58.392 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-01-29 03:09:58.492 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 03:09:58.492 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:09:58.493 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:09:58.497 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:09:58.867 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-01-29 03:09:59.345 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-01-29 03:09:59.493 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 03:09:59.493 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:09:59.494 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:09:59.497 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:09:59.820 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-01-29 03:10:00.022 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:10:00.028 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 03:10:00.028 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:10:00.028 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:10:00.028 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:10:00.029 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 03:10:00.029 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 03:10:00.029 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 03:10:00.029 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.28.20:5700) Recv POWEROFF cmd
2026-01-29 03:10:00.029 [INFO] ctrl_if_trx.py:117 (BTS@172.18.28.20:5700) Stopping transceiver...
2026-01-29 03:10:00.029 [INFO] transceiver.py:246 Stopping clock generator
2026-01-29 03:10:00.029 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 03:10:00.029 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=762 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:10:00.029 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=762 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:10:00.029 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=762 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:10:00.029 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=762 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:10:00.029 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=762 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:10:00.029 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=762 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:10:00.029 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=762 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:10:00.029 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=762 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:10:05.032 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.28.20:5700) Recv POWEROFF cmd
2026-01-29 03:10:05.032 [INFO] ctrl_if_trx.py:117 (BTS@172.18.28.20:5700) Stopping transceiver...
2026-01-29 03:10:05.034 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 03:10:05.035 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 03:10:05.036 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 03:10:05.036 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 03:10:05.044 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 03:10:05.045 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.28.20:5700) Recv SETFORMAT cmd
2026-01-29 03:10:05.045 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.28.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:10:05.045 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.28.20:5700) Recv SETFORMAT cmd
2026-01-29 03:10:05.045 [INFO] ctrl_if_trx.py:201 (BTS@172.18.28.20:5700) TRXD header version 1 -> 1
2026-01-29 03:10:05.048 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.28.20:5700/1) Recv RXTUNE cmd
2026-01-29 03:10:05.048 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.28.20:5700/1) Recv TXTUNE cmd
2026-01-29 03:10:05.048 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.28.20:5700/1) Recv SETFORMAT cmd
2026-01-29 03:10:05.048 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.28.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:10:05.049 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 03:10:05.049 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.28.20:5700/1) Recv NOMTXPOWER cmd
2026-01-29 03:10:05.049 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.28.20:5700/1) Recv SETFORMAT cmd
2026-01-29 03:10:05.049 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.28.20:5700/1) TRXD header version 1 -> 1
2026-01-29 03:10:05.050 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.28.20:5700/2) Recv RXTUNE cmd
2026-01-29 03:10:05.050 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.28.20:5700/2) Recv TXTUNE cmd
2026-01-29 03:10:05.050 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.28.20:5700/2) Recv SETFORMAT cmd
2026-01-29 03:10:05.050 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.28.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:10:05.051 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 03:10:05.051 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.28.20:5700/2) Recv NOMTXPOWER cmd
2026-01-29 03:10:05.051 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.28.20:5700/2) Recv SETFORMAT cmd
2026-01-29 03:10:05.051 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.28.20:5700/2) TRXD header version 1 -> 1
2026-01-29 03:10:05.053 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.28.20:5700/3) Recv RXTUNE cmd
2026-01-29 03:10:05.053 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.28.20:5700/3) Recv TXTUNE cmd
2026-01-29 03:10:05.053 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.28.20:5700/3) Recv SETFORMAT cmd
2026-01-29 03:10:05.053 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.28.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:10:05.053 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 03:10:05.053 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.28.20:5700/3) Recv NOMTXPOWER cmd
2026-01-29 03:10:05.053 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.28.20:5700/3) Recv SETFORMAT cmd
2026-01-29 03:10:05.053 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.28.20:5700/3) TRXD header version 1 -> 1
2026-01-29 03:10:05.055 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.28.20:5700) Recv RXTUNE cmd
2026-01-29 03:10:05.055 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETTSC
2026-01-29 03:10:05.055 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETTSC
2026-01-29 03:10:05.055 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETTSC
2026-01-29 03:10:05.055 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.28.20:5700) Recv TXTUNE cmd
2026-01-29 03:10:05.055 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETRXGAIN
2026-01-29 03:10:05.056 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETRXGAIN
2026-01-29 03:10:05.056 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETRXGAIN
2026-01-29 03:10:05.056 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETTSC
2026-01-29 03:10:05.056 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:10:05.056 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:10:05.056 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.28.20:5700) Recv NOMTXPOWER cmd
2026-01-29 03:10:05.056 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:10:05.056 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:10:05.056 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.28.20:5700) Recv POWERON CMD
2026-01-29 03:10:05.056 [INFO] ctrl_if_trx.py:109 (BTS@172.18.28.20:5700) Starting transceiver...
2026-01-29 03:10:05.056 [INFO] transceiver.py:243 Starting clock generator
2026-01-29 03:10:05.056 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-01-29 03:10:05.056 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:10:05.056 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:10:05.056 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:10:05.056 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETRXGAIN
2026-01-29 03:10:05.056 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:10:05.056 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:10:05.056 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:10:05.056 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:10:05.056 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:10:05.056 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:10:05.056 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:10:05.057 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:10:05.057 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:10:05.057 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:10:05.057 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:10:05.057 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:10:05.057 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:10:05.057 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:10:05.057 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:10:05.057 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:10:05.057 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:10:05.057 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:10:05.057 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:10:05.057 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:10:05.057 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:10:05.057 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:10:05.057 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:10:05.057 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:10:05.057 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:10:05.061 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-01-29 03:10:05.537 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-01-29 03:10:05.571 [DEBUG] fake_trx.py:278 (BTS@172.18.28.20:5700) Recv FAKE_TOA cmd
2026-01-29 03:10:05.571 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:10:05.571 [DEBUG] fake_trx.py:297 (BTS@172.18.28.20:5700) Recv FAKE_RSSI cmd
2026-01-29 03:10:05.572 [DEBUG] fake_trx.py:322 (BTS@172.18.28.20:5700) Recv FAKE_CI cmd
2026-01-29 03:10:05.578 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 03:10:05.578 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 03:10:05.578 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 03:10:05.582 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:10:05.583 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:10:05.584 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:10:05.586 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 03:10:05.586 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:10:05.586 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:10:05.586 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:10:05.586 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 03:10:05.586 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 03:10:05.587 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 03:10:05.587 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 03:10:05.587 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.28.20:5700) Recv POWEROFF cmd
2026-01-29 03:10:05.587 [INFO] ctrl_if_trx.py:117 (BTS@172.18.28.20:5700) Stopping transceiver...
2026-01-29 03:10:05.587 [INFO] transceiver.py:246 Stopping clock generator
2026-01-29 03:10:10.590 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.28.20:5700) Recv POWEROFF cmd
2026-01-29 03:10:10.590 [INFO] ctrl_if_trx.py:117 (BTS@172.18.28.20:5700) Stopping transceiver...
2026-01-29 03:10:10.591 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 03:10:10.592 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 03:10:10.593 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 03:10:10.593 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 03:10:10.607 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 03:10:10.609 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.28.20:5700) Recv SETFORMAT cmd
2026-01-29 03:10:10.609 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.28.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:10:10.609 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.28.20:5700) Recv SETFORMAT cmd
2026-01-29 03:10:10.609 [INFO] ctrl_if_trx.py:201 (BTS@172.18.28.20:5700) TRXD header version 1 -> 1
2026-01-29 03:10:10.611 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.28.20:5700/1) Recv RXTUNE cmd
2026-01-29 03:10:10.612 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.28.20:5700/1) Recv TXTUNE cmd
2026-01-29 03:10:10.612 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.28.20:5700/1) Recv SETFORMAT cmd
2026-01-29 03:10:10.612 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.28.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:10:10.612 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 03:10:10.612 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.28.20:5700/1) Recv NOMTXPOWER cmd
2026-01-29 03:10:10.613 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.28.20:5700/1) Recv SETFORMAT cmd
2026-01-29 03:10:10.613 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.28.20:5700/1) TRXD header version 1 -> 1
2026-01-29 03:10:10.613 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.28.20:5700/2) Recv RXTUNE cmd
2026-01-29 03:10:10.613 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.28.20:5700/2) Recv TXTUNE cmd
2026-01-29 03:10:10.613 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.28.20:5700/2) Recv SETFORMAT cmd
2026-01-29 03:10:10.613 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.28.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:10:10.614 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 03:10:10.614 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.28.20:5700/2) Recv NOMTXPOWER cmd
2026-01-29 03:10:10.614 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.28.20:5700/2) Recv SETFORMAT cmd
2026-01-29 03:10:10.614 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.28.20:5700/2) TRXD header version 1 -> 1
2026-01-29 03:10:10.615 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.28.20:5700/3) Recv RXTUNE cmd
2026-01-29 03:10:10.615 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.28.20:5700/3) Recv TXTUNE cmd
2026-01-29 03:10:10.615 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.28.20:5700/3) Recv SETFORMAT cmd
2026-01-29 03:10:10.615 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.28.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:10:10.615 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 03:10:10.615 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.28.20:5700/3) Recv NOMTXPOWER cmd
2026-01-29 03:10:10.616 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.28.20:5700/3) Recv SETFORMAT cmd
2026-01-29 03:10:10.616 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.28.20:5700/3) TRXD header version 1 -> 1
2026-01-29 03:10:10.617 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.28.20:5700) Recv RXTUNE cmd
2026-01-29 03:10:10.617 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETTSC
2026-01-29 03:10:10.618 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETTSC
2026-01-29 03:10:10.618 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETTSC
2026-01-29 03:10:10.618 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.28.20:5700) Recv TXTUNE cmd
2026-01-29 03:10:10.618 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETRXGAIN
2026-01-29 03:10:10.618 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETRXGAIN
2026-01-29 03:10:10.618 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETRXGAIN
2026-01-29 03:10:10.618 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETTSC
2026-01-29 03:10:10.618 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:10:10.618 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:10:10.618 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:10:10.618 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.28.20:5700) Recv NOMTXPOWER cmd
2026-01-29 03:10:10.618 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:10:10.618 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:10:10.618 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:10:10.618 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.28.20:5700) Recv POWERON CMD
2026-01-29 03:10:10.618 [INFO] ctrl_if_trx.py:109 (BTS@172.18.28.20:5700) Starting transceiver...
2026-01-29 03:10:10.618 [INFO] transceiver.py:243 Starting clock generator
2026-01-29 03:10:10.618 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-01-29 03:10:10.618 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:10:10.618 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:10:10.618 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:10:10.618 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETRXGAIN
2026-01-29 03:10:10.618 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:10:10.618 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:10:10.619 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:10:10.619 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:10:10.619 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:10:10.619 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:10:10.619 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:10:10.619 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:10:10.619 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:10:10.619 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:10:10.619 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:10:10.619 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:10:10.619 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:10:10.619 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:10:10.619 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:10:10.619 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:10:10.619 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:10:10.619 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:10:10.619 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:10:10.619 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:10:10.619 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:10:10.619 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:10:10.619 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:10:10.623 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-01-29 03:10:11.098 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-01-29 03:10:11.144 [DEBUG] fake_trx.py:278 (BTS@172.18.28.20:5700) Recv FAKE_TOA cmd
2026-01-29 03:10:11.146 [DEBUG] fake_trx.py:297 (BTS@172.18.28.20:5700) Recv FAKE_RSSI cmd
2026-01-29 03:10:11.146 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:10:11.148 [DEBUG] fake_trx.py:322 (BTS@172.18.28.20:5700) Recv FAKE_CI cmd
2026-01-29 03:10:11.174 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 03:10:11.175 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 03:10:11.175 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 03:10:11.187 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:10:11.190 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:10:11.571 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-01-29 03:10:11.621 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 03:10:11.621 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:10:11.622 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:10:11.625 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:10:12.039 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-01-29 03:10:12.507 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-01-29 03:10:12.621 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 03:10:12.621 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:10:12.623 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:10:12.626 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:10:12.976 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-01-29 03:10:13.453 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-01-29 03:10:13.622 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 03:10:13.622 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:10:13.623 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:10:13.627 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:10:13.930 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-01-29 03:10:14.198 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:10:14.198 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:10:14.207 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 03:10:14.207 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:10:14.207 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:10:14.207 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:10:14.207 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 03:10:14.208 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 03:10:14.208 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 03:10:14.208 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 03:10:14.208 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.28.20:5700) Recv POWEROFF cmd
2026-01-29 03:10:14.208 [INFO] ctrl_if_trx.py:117 (BTS@172.18.28.20:5700) Stopping transceiver...
2026-01-29 03:10:14.208 [INFO] transceiver.py:246 Stopping clock generator
2026-01-29 03:10:14.208 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=776 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:10:14.208 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=776 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:10:14.208 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=776 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:10:14.208 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=776 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:10:14.208 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=776 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:10:14.208 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=776 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:10:19.211 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.28.20:5700) Recv POWEROFF cmd
2026-01-29 03:10:19.211 [INFO] ctrl_if_trx.py:117 (BTS@172.18.28.20:5700) Stopping transceiver...
2026-01-29 03:10:19.213 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 03:10:19.214 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 03:10:19.215 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 03:10:19.215 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 03:10:19.224 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 03:10:19.226 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.28.20:5700) Recv SETFORMAT cmd
2026-01-29 03:10:19.226 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.28.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:10:19.226 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.28.20:5700) Recv SETFORMAT cmd
2026-01-29 03:10:19.226 [INFO] ctrl_if_trx.py:201 (BTS@172.18.28.20:5700) TRXD header version 1 -> 1
2026-01-29 03:10:19.231 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.28.20:5700/1) Recv RXTUNE cmd
2026-01-29 03:10:19.231 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.28.20:5700/1) Recv TXTUNE cmd
2026-01-29 03:10:19.231 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.28.20:5700/1) Recv SETFORMAT cmd
2026-01-29 03:10:19.231 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.28.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:10:19.231 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 03:10:19.231 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.28.20:5700/1) Recv NOMTXPOWER cmd
2026-01-29 03:10:19.232 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.28.20:5700/1) Recv SETFORMAT cmd
2026-01-29 03:10:19.232 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.28.20:5700/1) TRXD header version 1 -> 1
2026-01-29 03:10:19.234 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.28.20:5700/2) Recv RXTUNE cmd
2026-01-29 03:10:19.234 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.28.20:5700/2) Recv TXTUNE cmd
2026-01-29 03:10:19.235 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.28.20:5700/2) Recv SETFORMAT cmd
2026-01-29 03:10:19.235 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.28.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:10:19.235 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 03:10:19.235 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.28.20:5700/2) Recv NOMTXPOWER cmd
2026-01-29 03:10:19.235 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.28.20:5700/2) Recv SETFORMAT cmd
2026-01-29 03:10:19.235 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.28.20:5700/2) TRXD header version 1 -> 1
2026-01-29 03:10:19.237 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.28.20:5700/3) Recv RXTUNE cmd
2026-01-29 03:10:19.237 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.28.20:5700/3) Recv TXTUNE cmd
2026-01-29 03:10:19.237 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.28.20:5700/3) Recv SETFORMAT cmd
2026-01-29 03:10:19.238 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.28.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:10:19.238 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 03:10:19.238 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.28.20:5700/3) Recv NOMTXPOWER cmd
2026-01-29 03:10:19.238 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.28.20:5700/3) Recv SETFORMAT cmd
2026-01-29 03:10:19.238 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.28.20:5700/3) TRXD header version 1 -> 1
2026-01-29 03:10:19.241 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.28.20:5700) Recv RXTUNE cmd
2026-01-29 03:10:19.241 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETTSC
2026-01-29 03:10:19.241 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETTSC
2026-01-29 03:10:19.241 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETTSC
2026-01-29 03:10:19.241 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.28.20:5700) Recv TXTUNE cmd
2026-01-29 03:10:19.241 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETRXGAIN
2026-01-29 03:10:19.241 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETRXGAIN
2026-01-29 03:10:19.241 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETRXGAIN
2026-01-29 03:10:19.241 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETTSC
2026-01-29 03:10:19.241 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:10:19.241 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:10:19.241 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.28.20:5700) Recv NOMTXPOWER cmd
2026-01-29 03:10:19.241 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:10:19.241 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:10:19.241 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:10:19.241 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.28.20:5700) Recv POWERON CMD
2026-01-29 03:10:19.241 [INFO] ctrl_if_trx.py:109 (BTS@172.18.28.20:5700) Starting transceiver...
2026-01-29 03:10:19.241 [INFO] transceiver.py:243 Starting clock generator
2026-01-29 03:10:19.242 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-01-29 03:10:19.242 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:10:19.242 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:10:19.242 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:10:19.242 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETRXGAIN
2026-01-29 03:10:19.242 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:10:19.242 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:10:19.242 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:10:19.242 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:10:19.242 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:10:19.242 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:10:19.242 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:10:19.242 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:10:19.242 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:10:19.242 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:10:19.242 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:10:19.242 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:10:19.243 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:10:19.243 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:10:19.243 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:10:19.243 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:10:19.243 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:10:19.243 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:10:19.243 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:10:19.243 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:10:19.243 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:10:19.243 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:10:19.243 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:10:19.243 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:10:19.246 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-01-29 03:10:19.730 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-01-29 03:10:19.765 [DEBUG] fake_trx.py:278 (BTS@172.18.28.20:5700) Recv FAKE_TOA cmd
2026-01-29 03:10:19.766 [DEBUG] fake_trx.py:297 (BTS@172.18.28.20:5700) Recv FAKE_RSSI cmd
2026-01-29 03:10:19.768 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:10:19.768 [DEBUG] fake_trx.py:322 (BTS@172.18.28.20:5700) Recv FAKE_CI cmd
2026-01-29 03:10:19.790 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 03:10:19.790 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 03:10:19.791 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 03:10:19.802 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:10:19.804 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:10:19.810 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:10:19.810 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:10:19.813 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 03:10:19.813 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:10:19.813 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:10:19.814 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:10:19.816 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 03:10:19.817 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 03:10:19.817 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 03:10:19.817 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.28.20:5700) Recv POWEROFF cmd
2026-01-29 03:10:19.817 [INFO] ctrl_if_trx.py:117 (BTS@172.18.28.20:5700) Stopping transceiver...
2026-01-29 03:10:19.817 [INFO] transceiver.py:246 Stopping clock generator
2026-01-29 03:10:19.817 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 03:10:19.817 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=122 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:10:19.817 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=122 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:10:19.818 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=122 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:10:19.818 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=122 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:10:19.818 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=122 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:10:19.818 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=122 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:10:19.818 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=122 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:10:19.818 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=122 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:10:24.817 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.28.20:5700) Recv POWEROFF cmd
2026-01-29 03:10:24.817 [INFO] ctrl_if_trx.py:117 (BTS@172.18.28.20:5700) Stopping transceiver...
2026-01-29 03:10:24.818 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 03:10:24.820 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 03:10:24.820 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 03:10:24.821 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 03:10:24.830 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 03:10:24.831 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.28.20:5700) Recv SETFORMAT cmd
2026-01-29 03:10:24.831 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.28.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:10:24.832 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.28.20:5700) Recv SETFORMAT cmd
2026-01-29 03:10:24.832 [INFO] ctrl_if_trx.py:201 (BTS@172.18.28.20:5700) TRXD header version 1 -> 1
2026-01-29 03:10:24.836 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.28.20:5700/1) Recv RXTUNE cmd
2026-01-29 03:10:24.836 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.28.20:5700/1) Recv TXTUNE cmd
2026-01-29 03:10:24.837 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.28.20:5700/1) Recv SETFORMAT cmd
2026-01-29 03:10:24.837 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.28.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:10:24.838 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 03:10:24.838 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.28.20:5700/1) Recv NOMTXPOWER cmd
2026-01-29 03:10:24.838 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.28.20:5700/1) Recv SETFORMAT cmd
2026-01-29 03:10:24.838 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.28.20:5700/1) TRXD header version 1 -> 1
2026-01-29 03:10:24.839 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.28.20:5700/2) Recv RXTUNE cmd
2026-01-29 03:10:24.840 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.28.20:5700/2) Recv TXTUNE cmd
2026-01-29 03:10:24.840 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.28.20:5700/2) Recv SETFORMAT cmd
2026-01-29 03:10:24.840 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.28.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:10:24.840 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 03:10:24.841 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.28.20:5700/2) Recv NOMTXPOWER cmd
2026-01-29 03:10:24.841 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.28.20:5700/2) Recv SETFORMAT cmd
2026-01-29 03:10:24.841 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.28.20:5700/2) TRXD header version 1 -> 1
2026-01-29 03:10:24.842 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.28.20:5700/3) Recv RXTUNE cmd
2026-01-29 03:10:24.842 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.28.20:5700/3) Recv TXTUNE cmd
2026-01-29 03:10:24.842 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.28.20:5700/3) Recv SETFORMAT cmd
2026-01-29 03:10:24.842 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.28.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:10:24.842 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 03:10:24.842 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.28.20:5700/3) Recv NOMTXPOWER cmd
2026-01-29 03:10:24.843 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.28.20:5700/3) Recv SETFORMAT cmd
2026-01-29 03:10:24.843 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.28.20:5700/3) TRXD header version 1 -> 1
2026-01-29 03:10:24.845 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.28.20:5700) Recv RXTUNE cmd
2026-01-29 03:10:24.845 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETTSC
2026-01-29 03:10:24.845 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETTSC
2026-01-29 03:10:24.845 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETTSC
2026-01-29 03:10:24.845 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.28.20:5700) Recv TXTUNE cmd
2026-01-29 03:10:24.845 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETRXGAIN
2026-01-29 03:10:24.846 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETRXGAIN
2026-01-29 03:10:24.846 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETRXGAIN
2026-01-29 03:10:24.846 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETTSC
2026-01-29 03:10:24.846 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:10:24.846 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:10:24.846 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:10:24.846 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.28.20:5700) Recv NOMTXPOWER cmd
2026-01-29 03:10:24.846 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:10:24.846 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:10:24.846 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:10:24.846 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.28.20:5700) Recv POWERON CMD
2026-01-29 03:10:24.846 [INFO] ctrl_if_trx.py:109 (BTS@172.18.28.20:5700) Starting transceiver...
2026-01-29 03:10:24.846 [INFO] transceiver.py:243 Starting clock generator
2026-01-29 03:10:24.846 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-01-29 03:10:24.846 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:10:24.846 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:10:24.846 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:10:24.846 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETRXGAIN
2026-01-29 03:10:24.846 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:10:24.846 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:10:24.847 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:10:24.847 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:10:24.847 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:10:24.847 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:10:24.847 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:10:24.847 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:10:24.847 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:10:24.847 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:10:24.847 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:10:24.847 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:10:24.847 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:10:24.847 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:10:24.847 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:10:24.847 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:10:24.847 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:10:24.847 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:10:24.847 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:10:24.847 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:10:24.847 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:10:24.847 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:10:24.847 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:10:24.851 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-01-29 03:10:25.335 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-01-29 03:10:25.374 [DEBUG] fake_trx.py:278 (BTS@172.18.28.20:5700) Recv FAKE_TOA cmd
2026-01-29 03:10:25.376 [DEBUG] fake_trx.py:297 (BTS@172.18.28.20:5700) Recv FAKE_RSSI cmd
2026-01-29 03:10:25.377 [DEBUG] fake_trx.py:322 (BTS@172.18.28.20:5700) Recv FAKE_CI cmd
2026-01-29 03:10:25.379 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:10:25.389 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 03:10:25.389 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:10:25.389 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:10:25.389 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:10:25.392 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 03:10:25.393 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 03:10:25.393 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 03:10:25.393 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 03:10:25.393 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.28.20:5700) Recv POWEROFF cmd
2026-01-29 03:10:25.393 [INFO] ctrl_if_trx.py:117 (BTS@172.18.28.20:5700) Stopping transceiver...
2026-01-29 03:10:25.393 [INFO] transceiver.py:246 Stopping clock generator
2026-01-29 03:10:25.394 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=116 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:10:25.394 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=116 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:10:25.394 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=116 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:10:25.394 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=116 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:10:25.394 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=116 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:10:25.394 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=116 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:10:30.392 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.28.20:5700) Recv POWEROFF cmd
2026-01-29 03:10:30.392 [INFO] ctrl_if_trx.py:117 (BTS@172.18.28.20:5700) Stopping transceiver...
2026-01-29 03:10:30.394 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 03:10:30.395 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 03:10:30.396 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 03:10:30.396 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 03:10:30.405 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 03:10:30.406 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.28.20:5700) Recv SETFORMAT cmd
2026-01-29 03:10:30.406 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.28.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:10:30.407 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.28.20:5700) Recv SETFORMAT cmd
2026-01-29 03:10:30.407 [INFO] ctrl_if_trx.py:201 (BTS@172.18.28.20:5700) TRXD header version 1 -> 1
2026-01-29 03:10:30.410 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.28.20:5700/1) Recv RXTUNE cmd
2026-01-29 03:10:30.411 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.28.20:5700/1) Recv TXTUNE cmd
2026-01-29 03:10:30.411 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.28.20:5700/1) Recv SETFORMAT cmd
2026-01-29 03:10:30.411 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.28.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:10:30.412 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 03:10:30.412 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.28.20:5700/1) Recv NOMTXPOWER cmd
2026-01-29 03:10:30.413 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.28.20:5700/1) Recv SETFORMAT cmd
2026-01-29 03:10:30.413 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.28.20:5700/1) TRXD header version 1 -> 1
2026-01-29 03:10:30.414 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.28.20:5700/2) Recv RXTUNE cmd
2026-01-29 03:10:30.414 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.28.20:5700/2) Recv TXTUNE cmd
2026-01-29 03:10:30.414 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.28.20:5700/2) Recv SETFORMAT cmd
2026-01-29 03:10:30.414 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.28.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:10:30.415 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 03:10:30.415 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.28.20:5700/2) Recv NOMTXPOWER cmd
2026-01-29 03:10:30.415 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.28.20:5700/2) Recv SETFORMAT cmd
2026-01-29 03:10:30.415 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.28.20:5700/2) TRXD header version 1 -> 1
2026-01-29 03:10:30.416 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.28.20:5700/3) Recv RXTUNE cmd
2026-01-29 03:10:30.416 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.28.20:5700/3) Recv TXTUNE cmd
2026-01-29 03:10:30.416 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.28.20:5700/3) Recv SETFORMAT cmd
2026-01-29 03:10:30.417 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.28.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:10:30.417 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 03:10:30.417 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.28.20:5700/3) Recv NOMTXPOWER cmd
2026-01-29 03:10:30.417 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.28.20:5700/3) Recv SETFORMAT cmd
2026-01-29 03:10:30.417 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.28.20:5700/3) TRXD header version 1 -> 1
2026-01-29 03:10:30.419 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.28.20:5700) Recv RXTUNE cmd
2026-01-29 03:10:30.419 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETTSC
2026-01-29 03:10:30.419 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETTSC
2026-01-29 03:10:30.419 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETTSC
2026-01-29 03:10:30.419 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.28.20:5700) Recv TXTUNE cmd
2026-01-29 03:10:30.419 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETRXGAIN
2026-01-29 03:10:30.419 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETRXGAIN
2026-01-29 03:10:30.420 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETRXGAIN
2026-01-29 03:10:30.420 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETTSC
2026-01-29 03:10:30.420 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:10:30.420 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:10:30.420 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:10:30.420 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.28.20:5700) Recv NOMTXPOWER cmd
2026-01-29 03:10:30.420 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:10:30.420 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:10:30.420 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:10:30.420 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.28.20:5700) Recv POWERON CMD
2026-01-29 03:10:30.420 [INFO] ctrl_if_trx.py:109 (BTS@172.18.28.20:5700) Starting transceiver...
2026-01-29 03:10:30.420 [INFO] transceiver.py:243 Starting clock generator
2026-01-29 03:10:30.420 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-01-29 03:10:30.420 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:10:30.420 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:10:30.420 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:10:30.420 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETRXGAIN
2026-01-29 03:10:30.420 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:10:30.420 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:10:30.420 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:10:30.420 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:10:30.420 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:10:30.421 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:10:30.421 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:10:30.421 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:10:30.421 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:10:30.421 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:10:30.421 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:10:30.421 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:10:30.421 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:10:30.421 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:10:30.421 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:10:30.421 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:10:30.421 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:10:30.421 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:10:30.421 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:10:30.421 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:10:30.421 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:10:30.421 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:10:30.421 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:10:30.425 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-01-29 03:10:30.909 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-01-29 03:10:30.952 [DEBUG] fake_trx.py:278 (BTS@172.18.28.20:5700) Recv FAKE_TOA cmd
2026-01-29 03:10:30.955 [DEBUG] fake_trx.py:297 (BTS@172.18.28.20:5700) Recv FAKE_RSSI cmd
2026-01-29 03:10:30.957 [DEBUG] fake_trx.py:322 (BTS@172.18.28.20:5700) Recv FAKE_CI cmd
2026-01-29 03:10:30.957 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:10:30.970 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 03:10:30.970 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:10:30.971 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:10:30.971 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:10:30.975 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 03:10:30.975 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 03:10:30.975 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 03:10:30.975 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.28.20:5700) Recv POWEROFF cmd
2026-01-29 03:10:30.975 [INFO] ctrl_if_trx.py:117 (BTS@172.18.28.20:5700) Stopping transceiver...
2026-01-29 03:10:30.975 [INFO] transceiver.py:246 Stopping clock generator
2026-01-29 03:10:30.976 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 03:10:30.976 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=117 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:10:30.976 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=117 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:10:30.976 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=117 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:10:30.976 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=117 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:10:30.976 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=117 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:10:30.976 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=117 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:10:30.976 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=117 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:10:30.976 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=118 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:10:30.977 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=118 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:10:30.977 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=118 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:10:30.977 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=118 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:10:30.977 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=118 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:10:30.977 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=118 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:10:30.977 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=118 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:10:30.977 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=118 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:10:35.974 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.28.20:5700) Recv POWEROFF cmd
2026-01-29 03:10:35.974 [INFO] ctrl_if_trx.py:117 (BTS@172.18.28.20:5700) Stopping transceiver...
2026-01-29 03:10:35.977 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 03:10:35.977 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 03:10:35.977 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 03:10:35.977 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 03:10:35.987 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 03:10:35.989 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.28.20:5700) Recv SETFORMAT cmd
2026-01-29 03:10:35.989 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.28.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:10:35.989 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.28.20:5700) Recv SETFORMAT cmd
2026-01-29 03:10:35.989 [INFO] ctrl_if_trx.py:201 (BTS@172.18.28.20:5700) TRXD header version 1 -> 1
2026-01-29 03:10:35.995 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.28.20:5700/1) Recv RXTUNE cmd
2026-01-29 03:10:35.996 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.28.20:5700/1) Recv TXTUNE cmd
2026-01-29 03:10:35.996 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.28.20:5700/1) Recv SETFORMAT cmd
2026-01-29 03:10:35.996 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.28.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:10:35.996 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 03:10:35.996 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.28.20:5700/1) Recv NOMTXPOWER cmd
2026-01-29 03:10:35.997 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.28.20:5700/1) Recv SETFORMAT cmd
2026-01-29 03:10:35.997 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.28.20:5700/1) TRXD header version 1 -> 1
2026-01-29 03:10:35.999 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.28.20:5700/2) Recv RXTUNE cmd
2026-01-29 03:10:35.999 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.28.20:5700/2) Recv TXTUNE cmd
2026-01-29 03:10:35.999 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.28.20:5700/2) Recv SETFORMAT cmd
2026-01-29 03:10:35.999 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.28.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:10:36.000 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 03:10:36.000 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.28.20:5700/2) Recv NOMTXPOWER cmd
2026-01-29 03:10:36.000 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.28.20:5700/2) Recv SETFORMAT cmd
2026-01-29 03:10:36.000 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.28.20:5700/2) TRXD header version 1 -> 1
2026-01-29 03:10:36.002 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.28.20:5700/3) Recv RXTUNE cmd
2026-01-29 03:10:36.002 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.28.20:5700/3) Recv TXTUNE cmd
2026-01-29 03:10:36.003 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.28.20:5700/3) Recv SETFORMAT cmd
2026-01-29 03:10:36.003 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.28.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:10:36.003 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 03:10:36.003 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.28.20:5700/3) Recv NOMTXPOWER cmd
2026-01-29 03:10:36.003 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.28.20:5700/3) Recv SETFORMAT cmd
2026-01-29 03:10:36.003 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.28.20:5700/3) TRXD header version 1 -> 1
2026-01-29 03:10:36.006 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.28.20:5700) Recv RXTUNE cmd
2026-01-29 03:10:36.006 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETTSC
2026-01-29 03:10:36.006 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETTSC
2026-01-29 03:10:36.006 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETTSC
2026-01-29 03:10:36.006 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.28.20:5700) Recv TXTUNE cmd
2026-01-29 03:10:36.006 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETRXGAIN
2026-01-29 03:10:36.007 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETRXGAIN
2026-01-29 03:10:36.007 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETRXGAIN
2026-01-29 03:10:36.007 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETTSC
2026-01-29 03:10:36.007 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:10:36.007 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:10:36.007 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.28.20:5700) Recv NOMTXPOWER cmd
2026-01-29 03:10:36.007 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:10:36.007 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:10:36.007 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:10:36.007 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.28.20:5700) Recv POWERON CMD
2026-01-29 03:10:36.007 [INFO] ctrl_if_trx.py:109 (BTS@172.18.28.20:5700) Starting transceiver...
2026-01-29 03:10:36.007 [INFO] transceiver.py:243 Starting clock generator
2026-01-29 03:10:36.007 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-01-29 03:10:36.007 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:10:36.007 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:10:36.007 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:10:36.008 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETRXGAIN
2026-01-29 03:10:36.008 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:10:36.008 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:10:36.008 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:10:36.008 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:10:36.008 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:10:36.008 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:10:36.008 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:10:36.008 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:10:36.008 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:10:36.008 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:10:36.008 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:10:36.008 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:10:36.008 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:10:36.008 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:10:36.008 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:10:36.008 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:10:36.008 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:10:36.008 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:10:36.008 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:10:36.008 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:10:36.008 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:10:36.008 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:10:36.008 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:10:36.008 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:10:36.012 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-01-29 03:10:36.494 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-01-29 03:10:36.539 [DEBUG] fake_trx.py:278 (BTS@172.18.28.20:5700) Recv FAKE_TOA cmd
2026-01-29 03:10:36.541 [DEBUG] fake_trx.py:297 (BTS@172.18.28.20:5700) Recv FAKE_RSSI cmd
2026-01-29 03:10:36.542 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:10:36.543 [DEBUG] fake_trx.py:322 (BTS@172.18.28.20:5700) Recv FAKE_CI cmd
2026-01-29 03:10:36.550 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 03:10:36.550 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:10:36.550 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:10:36.550 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:10:36.554 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 03:10:36.554 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 03:10:36.554 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 03:10:36.554 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.28.20:5700) Recv POWEROFF cmd
2026-01-29 03:10:36.554 [INFO] ctrl_if_trx.py:117 (BTS@172.18.28.20:5700) Stopping transceiver...
2026-01-29 03:10:36.554 [INFO] transceiver.py:246 Stopping clock generator
2026-01-29 03:10:36.554 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 03:10:36.554 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=116 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:10:36.554 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=116 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:10:36.554 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=116 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:10:36.554 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=116 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:10:36.554 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=116 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:10:36.554 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=116 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:10:36.554 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=116 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:10:41.554 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.28.20:5700) Recv POWEROFF cmd
2026-01-29 03:10:41.554 [INFO] ctrl_if_trx.py:117 (BTS@172.18.28.20:5700) Stopping transceiver...
2026-01-29 03:10:41.556 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 03:10:41.556 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 03:10:41.556 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 03:10:41.557 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 03:10:41.566 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 03:10:41.568 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.28.20:5700) Recv SETFORMAT cmd
2026-01-29 03:10:41.568 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.28.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:10:41.569 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.28.20:5700) Recv SETFORMAT cmd
2026-01-29 03:10:41.569 [INFO] ctrl_if_trx.py:201 (BTS@172.18.28.20:5700) TRXD header version 1 -> 1
2026-01-29 03:10:41.573 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.28.20:5700/1) Recv RXTUNE cmd
2026-01-29 03:10:41.573 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.28.20:5700/1) Recv TXTUNE cmd
2026-01-29 03:10:41.574 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.28.20:5700/1) Recv SETFORMAT cmd
2026-01-29 03:10:41.574 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.28.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:10:41.574 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 03:10:41.575 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.28.20:5700/1) Recv NOMTXPOWER cmd
2026-01-29 03:10:41.575 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.28.20:5700/1) Recv SETFORMAT cmd
2026-01-29 03:10:41.575 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.28.20:5700/1) TRXD header version 1 -> 1
2026-01-29 03:10:41.576 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.28.20:5700/2) Recv RXTUNE cmd
2026-01-29 03:10:41.577 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.28.20:5700/2) Recv TXTUNE cmd
2026-01-29 03:10:41.577 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.28.20:5700/2) Recv SETFORMAT cmd
2026-01-29 03:10:41.577 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.28.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:10:41.577 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 03:10:41.577 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.28.20:5700/2) Recv NOMTXPOWER cmd
2026-01-29 03:10:41.578 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.28.20:5700/2) Recv SETFORMAT cmd
2026-01-29 03:10:41.578 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.28.20:5700/2) TRXD header version 1 -> 1
2026-01-29 03:10:41.579 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.28.20:5700/3) Recv RXTUNE cmd
2026-01-29 03:10:41.579 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.28.20:5700/3) Recv TXTUNE cmd
2026-01-29 03:10:41.579 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.28.20:5700/3) Recv SETFORMAT cmd
2026-01-29 03:10:41.579 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.28.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:10:41.580 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 03:10:41.580 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.28.20:5700/3) Recv NOMTXPOWER cmd
2026-01-29 03:10:41.580 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.28.20:5700/3) Recv SETFORMAT cmd
2026-01-29 03:10:41.580 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.28.20:5700/3) TRXD header version 1 -> 1
2026-01-29 03:10:41.583 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.28.20:5700) Recv RXTUNE cmd
2026-01-29 03:10:41.583 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETTSC
2026-01-29 03:10:41.583 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETTSC
2026-01-29 03:10:41.583 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETTSC
2026-01-29 03:10:41.583 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.28.20:5700) Recv TXTUNE cmd
2026-01-29 03:10:41.583 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETRXGAIN
2026-01-29 03:10:41.583 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETRXGAIN
2026-01-29 03:10:41.583 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETRXGAIN
2026-01-29 03:10:41.583 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETTSC
2026-01-29 03:10:41.583 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:10:41.583 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:10:41.583 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:10:41.583 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.28.20:5700) Recv NOMTXPOWER cmd
2026-01-29 03:10:41.583 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:10:41.583 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:10:41.583 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:10:41.584 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.28.20:5700) Recv POWERON CMD
2026-01-29 03:10:41.584 [INFO] ctrl_if_trx.py:109 (BTS@172.18.28.20:5700) Starting transceiver...
2026-01-29 03:10:41.584 [INFO] transceiver.py:243 Starting clock generator
2026-01-29 03:10:41.584 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-01-29 03:10:41.584 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:10:41.584 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:10:41.584 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:10:41.584 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETRXGAIN
2026-01-29 03:10:41.584 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:10:41.584 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:10:41.584 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:10:41.584 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:10:41.584 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:10:41.584 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:10:41.584 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:10:41.584 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:10:41.584 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:10:41.584 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:10:41.584 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:10:41.584 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:10:41.584 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:10:41.584 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:10:41.584 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:10:41.584 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:10:41.585 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:10:41.585 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:10:41.585 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:10:41.585 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:10:41.585 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:10:41.585 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:10:41.585 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:10:41.589 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-01-29 03:10:42.072 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-01-29 03:10:42.113 [DEBUG] fake_trx.py:278 (BTS@172.18.28.20:5700) Recv FAKE_TOA cmd
2026-01-29 03:10:42.116 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:10:42.117 [DEBUG] fake_trx.py:297 (BTS@172.18.28.20:5700) Recv FAKE_RSSI cmd
2026-01-29 03:10:42.120 [DEBUG] fake_trx.py:322 (BTS@172.18.28.20:5700) Recv FAKE_CI cmd
2026-01-29 03:10:42.133 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 03:10:42.133 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:10:42.133 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:10:42.133 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:10:42.136 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 03:10:42.137 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 03:10:42.137 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 03:10:42.137 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.28.20:5700) Recv POWEROFF cmd
2026-01-29 03:10:42.137 [INFO] ctrl_if_trx.py:117 (BTS@172.18.28.20:5700) Stopping transceiver...
2026-01-29 03:10:42.137 [INFO] transceiver.py:246 Stopping clock generator
2026-01-29 03:10:42.137 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 03:10:42.137 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=117 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:10:42.138 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=117 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:10:42.138 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=117 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:10:42.138 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=117 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:10:42.138 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=117 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:10:42.138 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=117 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:10:42.138 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=117 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:10:42.138 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=117 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:10:42.138 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=118 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:10:42.138 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=118 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:10:42.138 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=118 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:10:42.139 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=118 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:10:42.139 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=118 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:10:42.139 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=118 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:10:42.139 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=118 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:10:42.139 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=118 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:10:47.136 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.28.20:5700) Recv POWEROFF cmd
2026-01-29 03:10:47.136 [INFO] ctrl_if_trx.py:117 (BTS@172.18.28.20:5700) Stopping transceiver...
2026-01-29 03:10:47.138 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 03:10:47.139 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 03:10:47.140 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 03:10:47.140 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 03:10:47.147 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 03:10:47.148 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.28.20:5700) Recv SETFORMAT cmd
2026-01-29 03:10:47.148 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.28.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:10:47.148 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.28.20:5700) Recv SETFORMAT cmd
2026-01-29 03:10:47.148 [INFO] ctrl_if_trx.py:201 (BTS@172.18.28.20:5700) TRXD header version 1 -> 1
2026-01-29 03:10:47.151 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.28.20:5700/1) Recv RXTUNE cmd
2026-01-29 03:10:47.151 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.28.20:5700/1) Recv TXTUNE cmd
2026-01-29 03:10:47.151 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.28.20:5700/1) Recv SETFORMAT cmd
2026-01-29 03:10:47.151 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.28.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:10:47.151 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 03:10:47.151 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.28.20:5700/1) Recv NOMTXPOWER cmd
2026-01-29 03:10:47.151 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.28.20:5700/1) Recv SETFORMAT cmd
2026-01-29 03:10:47.151 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.28.20:5700/1) TRXD header version 1 -> 1
2026-01-29 03:10:47.154 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.28.20:5700/2) Recv RXTUNE cmd
2026-01-29 03:10:47.154 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.28.20:5700/2) Recv TXTUNE cmd
2026-01-29 03:10:47.154 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.28.20:5700/2) Recv SETFORMAT cmd
2026-01-29 03:10:47.154 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.28.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:10:47.154 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 03:10:47.154 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.28.20:5700/2) Recv NOMTXPOWER cmd
2026-01-29 03:10:47.154 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.28.20:5700/2) Recv SETFORMAT cmd
2026-01-29 03:10:47.154 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.28.20:5700/2) TRXD header version 1 -> 1
2026-01-29 03:10:47.156 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.28.20:5700/3) Recv RXTUNE cmd
2026-01-29 03:10:47.156 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.28.20:5700/3) Recv TXTUNE cmd
2026-01-29 03:10:47.157 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.28.20:5700/3) Recv SETFORMAT cmd
2026-01-29 03:10:47.157 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.28.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:10:47.157 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 03:10:47.157 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.28.20:5700/3) Recv NOMTXPOWER cmd
2026-01-29 03:10:47.157 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.28.20:5700/3) Recv SETFORMAT cmd
2026-01-29 03:10:47.157 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.28.20:5700/3) TRXD header version 1 -> 1
2026-01-29 03:10:47.160 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.28.20:5700) Recv RXTUNE cmd
2026-01-29 03:10:47.160 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETTSC
2026-01-29 03:10:47.160 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETTSC
2026-01-29 03:10:47.160 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETTSC
2026-01-29 03:10:47.160 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.28.20:5700) Recv TXTUNE cmd
2026-01-29 03:10:47.160 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETRXGAIN
2026-01-29 03:10:47.160 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETRXGAIN
2026-01-29 03:10:47.161 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETRXGAIN
2026-01-29 03:10:47.161 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETTSC
2026-01-29 03:10:47.161 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:10:47.161 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:10:47.161 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:10:47.161 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.28.20:5700) Recv NOMTXPOWER cmd
2026-01-29 03:10:47.161 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:10:47.161 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:10:47.161 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:10:47.161 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.28.20:5700) Recv POWERON CMD
2026-01-29 03:10:47.161 [INFO] ctrl_if_trx.py:109 (BTS@172.18.28.20:5700) Starting transceiver...
2026-01-29 03:10:47.161 [INFO] transceiver.py:243 Starting clock generator
2026-01-29 03:10:47.161 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-01-29 03:10:47.161 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:10:47.161 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:10:47.161 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:10:47.161 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETRXGAIN
2026-01-29 03:10:47.161 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:10:47.161 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:10:47.161 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:10:47.161 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:10:47.162 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:10:47.162 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:10:47.162 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:10:47.162 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:10:47.162 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:10:47.162 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:10:47.162 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:10:47.162 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:10:47.162 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:10:47.162 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:10:47.162 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:10:47.162 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:10:47.162 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:10:47.162 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:10:47.162 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:10:47.162 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:10:47.162 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:10:47.163 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:10:47.163 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:10:47.166 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-01-29 03:10:47.648 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-01-29 03:10:47.688 [DEBUG] fake_trx.py:278 (BTS@172.18.28.20:5700) Recv FAKE_TOA cmd
2026-01-29 03:10:47.689 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:10:47.690 [DEBUG] fake_trx.py:297 (BTS@172.18.28.20:5700) Recv FAKE_RSSI cmd
2026-01-29 03:10:47.691 [DEBUG] fake_trx.py:322 (BTS@172.18.28.20:5700) Recv FAKE_CI cmd
2026-01-29 03:10:48.118 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-01-29 03:10:48.165 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:10:48.165 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 03:10:48.166 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:10:48.171 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:10:48.587 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-01-29 03:10:49.060 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-01-29 03:10:49.167 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 03:10:49.167 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:10:49.167 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:10:49.172 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:10:49.538 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-01-29 03:10:50.017 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-01-29 03:10:50.168 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:10:50.168 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:10:50.168 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 03:10:50.173 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:10:50.495 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-01-29 03:10:50.720 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 03:10:50.720 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 03:10:50.721 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 03:10:50.721 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 03:10:50.722 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 03:10:50.723 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 03:10:50.723 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.28.22:6700) Recv POWERON CMD
2026-01-29 03:10:50.723 [INFO] ctrl_if_trx.py:109 (MS@172.18.28.22:6700) Starting transceiver...
2026-01-29 03:10:50.973 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-01-29 03:10:51.169 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 03:10:51.169 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:10:51.170 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:10:51.175 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:10:51.451 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-01-29 03:10:51.930 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-01-29 03:10:52.170 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 03:10:52.170 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:10:52.170 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:10:52.175 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:10:52.408 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-01-29 03:10:52.886 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-01-29 03:10:53.011 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 03:10:53.011 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 03:10:53.013 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:10:53.016 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 03:10:53.017 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:10:53.017 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:10:53.017 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:10:53.020 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 03:10:53.020 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 03:10:53.020 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 03:10:53.020 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 03:10:53.020 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.28.20:5700) Recv POWEROFF cmd
2026-01-29 03:10:53.020 [INFO] ctrl_if_trx.py:117 (BTS@172.18.28.20:5700) Stopping transceiver...
2026-01-29 03:10:53.020 [INFO] transceiver.py:246 Stopping clock generator
2026-01-29 03:10:53.020 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=1255 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:10:58.019 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.28.20:5700) Recv POWEROFF cmd
2026-01-29 03:10:58.019 [INFO] ctrl_if_trx.py:117 (BTS@172.18.28.20:5700) Stopping transceiver...
2026-01-29 03:10:58.020 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 03:10:58.022 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 03:10:58.023 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 03:10:58.023 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 03:10:58.032 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 03:10:58.034 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.28.20:5700) Recv SETFORMAT cmd
2026-01-29 03:10:58.034 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.28.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:10:58.035 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.28.20:5700) Recv SETFORMAT cmd
2026-01-29 03:10:58.035 [INFO] ctrl_if_trx.py:201 (BTS@172.18.28.20:5700) TRXD header version 1 -> 1
2026-01-29 03:10:58.040 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.28.20:5700/1) Recv RXTUNE cmd
2026-01-29 03:10:58.041 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.28.20:5700/1) Recv TXTUNE cmd
2026-01-29 03:10:58.041 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.28.20:5700/1) Recv SETFORMAT cmd
2026-01-29 03:10:58.041 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.28.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:10:58.041 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 03:10:58.041 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.28.20:5700/1) Recv NOMTXPOWER cmd
2026-01-29 03:10:58.041 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.28.20:5700/1) Recv SETFORMAT cmd
2026-01-29 03:10:58.041 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.28.20:5700/1) TRXD header version 1 -> 1
2026-01-29 03:10:58.044 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.28.20:5700/2) Recv RXTUNE cmd
2026-01-29 03:10:58.044 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.28.20:5700/2) Recv TXTUNE cmd
2026-01-29 03:10:58.045 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.28.20:5700/2) Recv SETFORMAT cmd
2026-01-29 03:10:58.045 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.28.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:10:58.045 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.28.20:5700/2) Recv NOMTXPOWER cmd
2026-01-29 03:10:58.045 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 03:10:58.045 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.28.20:5700/2) Recv SETFORMAT cmd
2026-01-29 03:10:58.045 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.28.20:5700/2) TRXD header version 1 -> 1
2026-01-29 03:10:58.048 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.28.20:5700/3) Recv RXTUNE cmd
2026-01-29 03:10:58.048 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.28.20:5700/3) Recv TXTUNE cmd
2026-01-29 03:10:58.048 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.28.20:5700/3) Recv SETFORMAT cmd
2026-01-29 03:10:58.048 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.28.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:10:58.048 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 03:10:58.048 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.28.20:5700/3) Recv NOMTXPOWER cmd
2026-01-29 03:10:58.048 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.28.20:5700/3) Recv SETFORMAT cmd
2026-01-29 03:10:58.048 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.28.20:5700/3) TRXD header version 1 -> 1
2026-01-29 03:10:58.051 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.28.20:5700) Recv RXTUNE cmd
2026-01-29 03:10:58.051 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETTSC
2026-01-29 03:10:58.051 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETTSC
2026-01-29 03:10:58.052 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETTSC
2026-01-29 03:10:58.052 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.28.20:5700) Recv TXTUNE cmd
2026-01-29 03:10:58.052 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETRXGAIN
2026-01-29 03:10:58.052 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETRXGAIN
2026-01-29 03:10:58.052 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETRXGAIN
2026-01-29 03:10:58.052 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETTSC
2026-01-29 03:10:58.052 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:10:58.052 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:10:58.052 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:10:58.052 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.28.20:5700) Recv NOMTXPOWER cmd
2026-01-29 03:10:58.052 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:10:58.052 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:10:58.052 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:10:58.052 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.28.20:5700) Recv POWERON CMD
2026-01-29 03:10:58.052 [INFO] ctrl_if_trx.py:109 (BTS@172.18.28.20:5700) Starting transceiver...
2026-01-29 03:10:58.052 [INFO] transceiver.py:243 Starting clock generator
2026-01-29 03:10:58.052 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-01-29 03:10:58.052 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:10:58.052 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:10:58.053 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:10:58.053 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETRXGAIN
2026-01-29 03:10:58.053 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:10:58.053 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:10:58.053 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:10:58.053 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:10:58.053 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:10:58.053 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:10:58.053 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:10:58.053 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:10:58.053 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:10:58.053 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:10:58.053 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:10:58.053 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:10:58.053 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:10:58.053 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:10:58.053 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:10:58.053 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:10:58.053 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:10:58.053 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:10:58.053 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:10:58.053 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:10:58.054 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:10:58.054 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:10:58.054 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:10:58.057 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-01-29 03:10:58.540 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-01-29 03:10:58.586 [DEBUG] fake_trx.py:278 (BTS@172.18.28.20:5700) Recv FAKE_TOA cmd
2026-01-29 03:10:58.588 [DEBUG] fake_trx.py:297 (BTS@172.18.28.20:5700) Recv FAKE_RSSI cmd
2026-01-29 03:10:58.590 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:10:58.590 [DEBUG] fake_trx.py:322 (BTS@172.18.28.20:5700) Recv FAKE_CI cmd
2026-01-29 03:10:58.609 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 03:10:58.609 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 03:10:58.609 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 03:10:58.620 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 03:10:58.621 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:10:58.621 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:10:58.621 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:10:58.624 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 03:10:58.624 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 03:10:58.624 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 03:10:58.624 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 03:10:58.624 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.28.20:5700) Recv POWEROFF cmd
2026-01-29 03:10:58.624 [INFO] ctrl_if_trx.py:117 (BTS@172.18.28.20:5700) Stopping transceiver...
2026-01-29 03:10:58.624 [INFO] transceiver.py:246 Stopping clock generator
2026-01-29 03:10:58.624 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=122 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:10:58.624 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=122 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:10:58.624 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=122 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:10:58.624 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=122 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:10:58.624 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=122 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:10:58.624 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=122 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:10:58.624 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=122 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:11:03.624 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.28.20:5700) Recv POWEROFF cmd
2026-01-29 03:11:03.624 [INFO] ctrl_if_trx.py:117 (BTS@172.18.28.20:5700) Stopping transceiver...
2026-01-29 03:11:03.626 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 03:11:03.628 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 03:11:03.628 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 03:11:03.628 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 03:11:03.635 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 03:11:03.635 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.28.20:5700) Recv SETFORMAT cmd
2026-01-29 03:11:03.635 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.28.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:11:03.635 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.28.20:5700) Recv SETFORMAT cmd
2026-01-29 03:11:03.635 [INFO] ctrl_if_trx.py:201 (BTS@172.18.28.20:5700) TRXD header version 1 -> 1
2026-01-29 03:11:03.638 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.28.20:5700/1) Recv RXTUNE cmd
2026-01-29 03:11:03.638 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.28.20:5700/1) Recv TXTUNE cmd
2026-01-29 03:11:03.639 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.28.20:5700/1) Recv SETFORMAT cmd
2026-01-29 03:11:03.639 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.28.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:11:03.639 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 03:11:03.640 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.28.20:5700/1) Recv NOMTXPOWER cmd
2026-01-29 03:11:03.640 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.28.20:5700/1) Recv SETFORMAT cmd
2026-01-29 03:11:03.640 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.28.20:5700/1) TRXD header version 1 -> 1
2026-01-29 03:11:03.641 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.28.20:5700/2) Recv RXTUNE cmd
2026-01-29 03:11:03.641 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.28.20:5700/2) Recv TXTUNE cmd
2026-01-29 03:11:03.641 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.28.20:5700/2) Recv SETFORMAT cmd
2026-01-29 03:11:03.641 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.28.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:11:03.641 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 03:11:03.642 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.28.20:5700/2) Recv NOMTXPOWER cmd
2026-01-29 03:11:03.642 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.28.20:5700/2) Recv SETFORMAT cmd
2026-01-29 03:11:03.642 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.28.20:5700/2) TRXD header version 1 -> 1
2026-01-29 03:11:03.644 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.28.20:5700/3) Recv RXTUNE cmd
2026-01-29 03:11:03.644 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.28.20:5700/3) Recv TXTUNE cmd
2026-01-29 03:11:03.644 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.28.20:5700/3) Recv SETFORMAT cmd
2026-01-29 03:11:03.644 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.28.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:11:03.644 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 03:11:03.644 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.28.20:5700/3) Recv NOMTXPOWER cmd
2026-01-29 03:11:03.644 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.28.20:5700/3) Recv SETFORMAT cmd
2026-01-29 03:11:03.644 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.28.20:5700/3) TRXD header version 1 -> 1
2026-01-29 03:11:03.647 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.28.20:5700) Recv RXTUNE cmd
2026-01-29 03:11:03.647 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETTSC
2026-01-29 03:11:03.647 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETTSC
2026-01-29 03:11:03.647 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETTSC
2026-01-29 03:11:03.647 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.28.20:5700) Recv TXTUNE cmd
2026-01-29 03:11:03.647 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETRXGAIN
2026-01-29 03:11:03.647 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETRXGAIN
2026-01-29 03:11:03.647 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETRXGAIN
2026-01-29 03:11:03.647 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETTSC
2026-01-29 03:11:03.647 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:11:03.647 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:11:03.647 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:11:03.647 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.28.20:5700) Recv NOMTXPOWER cmd
2026-01-29 03:11:03.647 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:11:03.647 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:11:03.647 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:11:03.647 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.28.20:5700) Recv POWERON CMD
2026-01-29 03:11:03.648 [INFO] ctrl_if_trx.py:109 (BTS@172.18.28.20:5700) Starting transceiver...
2026-01-29 03:11:03.648 [INFO] transceiver.py:243 Starting clock generator
2026-01-29 03:11:03.648 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-01-29 03:11:03.648 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:11:03.648 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:11:03.648 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:11:03.648 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETRXGAIN
2026-01-29 03:11:03.648 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:11:03.648 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:11:03.648 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:11:03.648 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:11:03.648 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:11:03.648 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:11:03.648 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:11:03.648 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:11:03.648 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:11:03.648 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:11:03.648 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:11:03.648 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:11:03.648 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:11:03.649 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:11:03.649 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:11:03.649 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:11:03.649 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:11:03.649 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:11:03.649 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:11:03.649 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:11:03.649 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:11:03.649 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:11:03.649 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:11:03.652 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-01-29 03:11:04.136 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-01-29 03:11:04.173 [DEBUG] fake_trx.py:278 (BTS@172.18.28.20:5700) Recv FAKE_TOA cmd
2026-01-29 03:11:04.174 [DEBUG] fake_trx.py:297 (BTS@172.18.28.20:5700) Recv FAKE_RSSI cmd
2026-01-29 03:11:04.175 [DEBUG] fake_trx.py:322 (BTS@172.18.28.20:5700) Recv FAKE_CI cmd
2026-01-29 03:11:04.175 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:11:04.199 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 03:11:04.200 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 03:11:04.200 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 03:11:04.208 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:11:04.208 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:11:04.212 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 03:11:04.212 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:11:04.212 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:11:04.212 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:11:04.213 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 03:11:04.213 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 03:11:04.213 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 03:11:04.213 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.28.20:5700) Recv POWEROFF cmd
2026-01-29 03:11:04.213 [INFO] ctrl_if_trx.py:117 (BTS@172.18.28.20:5700) Stopping transceiver...
2026-01-29 03:11:04.213 [INFO] transceiver.py:246 Stopping clock generator
2026-01-29 03:11:04.214 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 03:11:09.215 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.28.20:5700) Recv POWEROFF cmd
2026-01-29 03:11:09.215 [INFO] ctrl_if_trx.py:117 (BTS@172.18.28.20:5700) Stopping transceiver...
2026-01-29 03:11:09.217 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 03:11:09.218 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 03:11:09.218 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 03:11:09.219 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 03:11:09.224 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 03:11:09.226 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.28.20:5700) Recv SETFORMAT cmd
2026-01-29 03:11:09.226 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.28.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:11:09.226 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.28.20:5700) Recv SETFORMAT cmd
2026-01-29 03:11:09.226 [INFO] ctrl_if_trx.py:201 (BTS@172.18.28.20:5700) TRXD header version 1 -> 1
2026-01-29 03:11:09.230 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.28.20:5700/1) Recv RXTUNE cmd
2026-01-29 03:11:09.230 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.28.20:5700/1) Recv TXTUNE cmd
2026-01-29 03:11:09.231 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.28.20:5700/1) Recv SETFORMAT cmd
2026-01-29 03:11:09.231 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.28.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:11:09.231 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 03:11:09.231 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.28.20:5700/1) Recv NOMTXPOWER cmd
2026-01-29 03:11:09.232 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.28.20:5700/1) Recv SETFORMAT cmd
2026-01-29 03:11:09.232 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.28.20:5700/1) TRXD header version 1 -> 1
2026-01-29 03:11:09.233 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.28.20:5700/2) Recv RXTUNE cmd
2026-01-29 03:11:09.234 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.28.20:5700/2) Recv TXTUNE cmd
2026-01-29 03:11:09.234 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.28.20:5700/2) Recv SETFORMAT cmd
2026-01-29 03:11:09.234 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.28.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:11:09.234 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 03:11:09.234 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.28.20:5700/2) Recv NOMTXPOWER cmd
2026-01-29 03:11:09.234 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.28.20:5700/2) Recv SETFORMAT cmd
2026-01-29 03:11:09.234 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.28.20:5700/2) TRXD header version 1 -> 1
2026-01-29 03:11:09.236 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.28.20:5700/3) Recv RXTUNE cmd
2026-01-29 03:11:09.236 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.28.20:5700/3) Recv TXTUNE cmd
2026-01-29 03:11:09.236 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.28.20:5700/3) Recv SETFORMAT cmd
2026-01-29 03:11:09.236 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.28.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:11:09.237 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 03:11:09.237 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.28.20:5700/3) Recv NOMTXPOWER cmd
2026-01-29 03:11:09.237 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.28.20:5700/3) Recv SETFORMAT cmd
2026-01-29 03:11:09.237 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.28.20:5700/3) TRXD header version 1 -> 1
2026-01-29 03:11:09.240 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.28.20:5700) Recv RXTUNE cmd
2026-01-29 03:11:09.240 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETTSC
2026-01-29 03:11:09.240 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETTSC
2026-01-29 03:11:09.240 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETTSC
2026-01-29 03:11:09.240 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.28.20:5700) Recv TXTUNE cmd
2026-01-29 03:11:09.240 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETRXGAIN
2026-01-29 03:11:09.240 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETRXGAIN
2026-01-29 03:11:09.240 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETRXGAIN
2026-01-29 03:11:09.240 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETTSC
2026-01-29 03:11:09.240 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:11:09.240 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:11:09.240 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:11:09.240 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.28.20:5700) Recv NOMTXPOWER cmd
2026-01-29 03:11:09.240 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:11:09.240 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:11:09.240 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:11:09.240 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.28.20:5700) Recv POWERON CMD
2026-01-29 03:11:09.240 [INFO] ctrl_if_trx.py:109 (BTS@172.18.28.20:5700) Starting transceiver...
2026-01-29 03:11:09.240 [INFO] transceiver.py:243 Starting clock generator
2026-01-29 03:11:09.241 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-01-29 03:11:09.241 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:11:09.241 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:11:09.241 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:11:09.241 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETRXGAIN
2026-01-29 03:11:09.241 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:11:09.241 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:11:09.241 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:11:09.241 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:11:09.241 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:11:09.241 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:11:09.241 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:11:09.241 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:11:09.241 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:11:09.241 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:11:09.241 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:11:09.241 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:11:09.241 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:11:09.242 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:11:09.242 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:11:09.242 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:11:09.242 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:11:09.242 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:11:09.242 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:11:09.242 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:11:09.242 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:11:09.242 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:11:09.242 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:11:09.245 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-01-29 03:11:09.729 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-01-29 03:11:09.766 [DEBUG] fake_trx.py:278 (BTS@172.18.28.20:5700) Recv FAKE_TOA cmd
2026-01-29 03:11:09.767 [DEBUG] fake_trx.py:297 (BTS@172.18.28.20:5700) Recv FAKE_RSSI cmd
2026-01-29 03:11:09.768 [DEBUG] fake_trx.py:322 (BTS@172.18.28.20:5700) Recv FAKE_CI cmd
2026-01-29 03:11:09.768 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:11:09.783 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 03:11:09.783 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 03:11:09.783 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 03:11:09.796 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:11:09.797 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:11:09.799 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:11:09.803 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 03:11:09.803 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:11:09.803 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:11:09.803 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:11:09.806 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 03:11:09.806 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 03:11:09.806 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 03:11:09.806 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 03:11:09.806 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.28.20:5700) Recv POWEROFF cmd
2026-01-29 03:11:09.806 [INFO] ctrl_if_trx.py:117 (BTS@172.18.28.20:5700) Stopping transceiver...
2026-01-29 03:11:09.806 [INFO] transceiver.py:246 Stopping clock generator
2026-01-29 03:11:09.806 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=120 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:11:09.807 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=120 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:11:09.807 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=120 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:11:09.807 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=120 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:11:09.807 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=120 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:11:09.807 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=120 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:11:14.810 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.28.20:5700) Recv POWEROFF cmd
2026-01-29 03:11:14.811 [INFO] ctrl_if_trx.py:117 (BTS@172.18.28.20:5700) Stopping transceiver...
2026-01-29 03:11:14.811 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 03:11:14.811 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 03:11:14.811 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 03:11:14.811 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 03:11:14.819 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 03:11:14.820 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.28.20:5700) Recv SETFORMAT cmd
2026-01-29 03:11:14.821 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.28.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:11:14.821 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.28.20:5700) Recv SETFORMAT cmd
2026-01-29 03:11:14.821 [INFO] ctrl_if_trx.py:201 (BTS@172.18.28.20:5700) TRXD header version 1 -> 1
2026-01-29 03:11:14.826 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.28.20:5700/1) Recv RXTUNE cmd
2026-01-29 03:11:14.826 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.28.20:5700/1) Recv TXTUNE cmd
2026-01-29 03:11:14.827 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.28.20:5700/1) Recv SETFORMAT cmd
2026-01-29 03:11:14.827 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.28.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:11:14.827 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 03:11:14.828 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.28.20:5700/1) Recv NOMTXPOWER cmd
2026-01-29 03:11:14.828 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.28.20:5700/1) Recv SETFORMAT cmd
2026-01-29 03:11:14.829 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.28.20:5700/1) TRXD header version 1 -> 1
2026-01-29 03:11:14.830 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.28.20:5700/2) Recv RXTUNE cmd
2026-01-29 03:11:14.830 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.28.20:5700/2) Recv TXTUNE cmd
2026-01-29 03:11:14.831 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.28.20:5700/2) Recv SETFORMAT cmd
2026-01-29 03:11:14.831 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.28.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:11:14.831 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 03:11:14.831 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.28.20:5700/2) Recv NOMTXPOWER cmd
2026-01-29 03:11:14.832 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.28.20:5700/2) Recv SETFORMAT cmd
2026-01-29 03:11:14.832 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.28.20:5700/2) TRXD header version 1 -> 1
2026-01-29 03:11:14.833 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.28.20:5700/3) Recv RXTUNE cmd
2026-01-29 03:11:14.833 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.28.20:5700/3) Recv TXTUNE cmd
2026-01-29 03:11:14.834 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.28.20:5700/3) Recv SETFORMAT cmd
2026-01-29 03:11:14.834 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.28.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:11:14.834 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 03:11:14.834 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.28.20:5700/3) Recv NOMTXPOWER cmd
2026-01-29 03:11:14.834 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.28.20:5700/3) Recv SETFORMAT cmd
2026-01-29 03:11:14.834 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.28.20:5700/3) TRXD header version 1 -> 1
2026-01-29 03:11:14.837 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.28.20:5700) Recv RXTUNE cmd
2026-01-29 03:11:14.837 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETTSC
2026-01-29 03:11:14.837 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETTSC
2026-01-29 03:11:14.837 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETTSC
2026-01-29 03:11:14.837 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.28.20:5700) Recv TXTUNE cmd
2026-01-29 03:11:14.837 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETRXGAIN
2026-01-29 03:11:14.837 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETRXGAIN
2026-01-29 03:11:14.837 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETRXGAIN
2026-01-29 03:11:14.837 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETTSC
2026-01-29 03:11:14.837 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:11:14.837 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:11:14.837 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.28.20:5700) Recv NOMTXPOWER cmd
2026-01-29 03:11:14.837 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:11:14.838 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:11:14.838 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:11:14.838 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.28.20:5700) Recv POWERON CMD
2026-01-29 03:11:14.838 [INFO] ctrl_if_trx.py:109 (BTS@172.18.28.20:5700) Starting transceiver...
2026-01-29 03:11:14.838 [INFO] transceiver.py:243 Starting clock generator
2026-01-29 03:11:14.838 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-01-29 03:11:14.838 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:11:14.838 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:11:14.838 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:11:14.838 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETRXGAIN
2026-01-29 03:11:14.838 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:11:14.838 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:11:14.838 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:11:14.838 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:11:14.838 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:11:14.838 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:11:14.838 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:11:14.838 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:11:14.838 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:11:14.838 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:11:14.839 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:11:14.839 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:11:14.839 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:11:14.839 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:11:14.839 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:11:14.839 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:11:14.839 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:11:14.839 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:11:14.839 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:11:14.839 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:11:14.839 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:11:14.839 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:11:14.839 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:11:14.839 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:11:14.843 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-01-29 03:11:15.325 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-01-29 03:11:15.360 [DEBUG] fake_trx.py:278 (BTS@172.18.28.20:5700) Recv FAKE_TOA cmd
2026-01-29 03:11:15.361 [DEBUG] fake_trx.py:297 (BTS@172.18.28.20:5700) Recv FAKE_RSSI cmd
2026-01-29 03:11:15.362 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:11:15.362 [DEBUG] fake_trx.py:322 (BTS@172.18.28.20:5700) Recv FAKE_CI cmd
2026-01-29 03:11:15.382 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 03:11:15.382 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 03:11:15.383 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 03:11:15.396 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:11:15.396 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:11:15.398 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:11:15.399 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:11:15.401 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:11:15.402 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:11:15.403 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:11:15.405 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:11:15.406 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:11:15.409 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 03:11:15.409 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:11:15.409 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:11:15.409 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:11:15.413 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 03:11:15.413 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 03:11:15.413 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 03:11:15.413 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 03:11:15.413 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.28.20:5700) Recv POWEROFF cmd
2026-01-29 03:11:15.413 [INFO] ctrl_if_trx.py:117 (BTS@172.18.28.20:5700) Stopping transceiver...
2026-01-29 03:11:15.413 [INFO] transceiver.py:246 Stopping clock generator
2026-01-29 03:11:15.414 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=122 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:11:15.414 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=122 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:11:15.414 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=122 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:11:15.414 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=122 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:11:15.414 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=122 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:11:15.414 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=122 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:11:15.414 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=123 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:11:15.414 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=123 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:11:15.414 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=123 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:11:15.414 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=123 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:11:15.414 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=123 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:11:15.414 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=123 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:11:15.414 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=123 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:11:15.414 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=123 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:11:20.413 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.28.20:5700) Recv POWEROFF cmd
2026-01-29 03:11:20.413 [INFO] ctrl_if_trx.py:117 (BTS@172.18.28.20:5700) Stopping transceiver...
2026-01-29 03:11:20.415 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 03:11:20.416 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 03:11:20.417 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 03:11:20.417 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 03:11:20.420 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 03:11:20.421 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.28.20:5700) Recv SETFORMAT cmd
2026-01-29 03:11:20.421 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.28.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:11:20.421 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.28.20:5700) Recv SETFORMAT cmd
2026-01-29 03:11:20.421 [INFO] ctrl_if_trx.py:201 (BTS@172.18.28.20:5700) TRXD header version 1 -> 1
2026-01-29 03:11:20.423 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.28.20:5700/1) Recv RXTUNE cmd
2026-01-29 03:11:20.423 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.28.20:5700/1) Recv TXTUNE cmd
2026-01-29 03:11:20.423 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.28.20:5700/1) Recv SETFORMAT cmd
2026-01-29 03:11:20.423 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.28.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:11:20.423 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 03:11:20.423 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.28.20:5700/1) Recv NOMTXPOWER cmd
2026-01-29 03:11:20.423 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.28.20:5700/1) Recv SETFORMAT cmd
2026-01-29 03:11:20.423 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.28.20:5700/1) TRXD header version 1 -> 1
2026-01-29 03:11:20.425 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.28.20:5700/2) Recv RXTUNE cmd
2026-01-29 03:11:20.425 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.28.20:5700/2) Recv TXTUNE cmd
2026-01-29 03:11:20.425 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.28.20:5700/2) Recv SETFORMAT cmd
2026-01-29 03:11:20.425 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.28.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:11:20.425 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 03:11:20.426 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.28.20:5700/2) Recv NOMTXPOWER cmd
2026-01-29 03:11:20.426 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.28.20:5700/2) Recv SETFORMAT cmd
2026-01-29 03:11:20.426 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.28.20:5700/2) TRXD header version 1 -> 1
2026-01-29 03:11:20.427 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.28.20:5700/3) Recv RXTUNE cmd
2026-01-29 03:11:20.428 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.28.20:5700/3) Recv TXTUNE cmd
2026-01-29 03:11:20.428 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.28.20:5700/3) Recv SETFORMAT cmd
2026-01-29 03:11:20.428 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.28.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:11:20.428 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 03:11:20.428 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.28.20:5700/3) Recv NOMTXPOWER cmd
2026-01-29 03:11:20.428 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.28.20:5700/3) Recv SETFORMAT cmd
2026-01-29 03:11:20.428 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.28.20:5700/3) TRXD header version 1 -> 1
2026-01-29 03:11:20.430 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.28.20:5700) Recv RXTUNE cmd
2026-01-29 03:11:20.430 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETTSC
2026-01-29 03:11:20.430 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETTSC
2026-01-29 03:11:20.430 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETTSC
2026-01-29 03:11:20.430 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.28.20:5700) Recv TXTUNE cmd
2026-01-29 03:11:20.430 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETRXGAIN
2026-01-29 03:11:20.431 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETRXGAIN
2026-01-29 03:11:20.431 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETRXGAIN
2026-01-29 03:11:20.431 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETTSC
2026-01-29 03:11:20.431 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:11:20.431 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:11:20.431 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:11:20.431 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.28.20:5700) Recv NOMTXPOWER cmd
2026-01-29 03:11:20.431 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:11:20.431 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:11:20.431 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:11:20.431 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.28.20:5700) Recv POWERON CMD
2026-01-29 03:11:20.431 [INFO] ctrl_if_trx.py:109 (BTS@172.18.28.20:5700) Starting transceiver...
2026-01-29 03:11:20.431 [INFO] transceiver.py:243 Starting clock generator
2026-01-29 03:11:20.431 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-01-29 03:11:20.431 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:11:20.431 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:11:20.431 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:11:20.431 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETRXGAIN
2026-01-29 03:11:20.431 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:11:20.431 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:11:20.431 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:11:20.431 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:11:20.431 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:11:20.431 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:11:20.431 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:11:20.431 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:11:20.431 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:11:20.431 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:11:20.432 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:11:20.432 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:11:20.432 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:11:20.432 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:11:20.432 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:11:20.432 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:11:20.432 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:11:20.432 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:11:20.432 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:11:20.432 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:11:20.432 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:11:20.432 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:11:20.432 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:11:20.436 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-01-29 03:11:20.919 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-01-29 03:11:20.964 [DEBUG] fake_trx.py:278 (BTS@172.18.28.20:5700) Recv FAKE_TOA cmd
2026-01-29 03:11:20.966 [DEBUG] fake_trx.py:297 (BTS@172.18.28.20:5700) Recv FAKE_RSSI cmd
2026-01-29 03:11:20.967 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:11:20.968 [DEBUG] fake_trx.py:322 (BTS@172.18.28.20:5700) Recv FAKE_CI cmd
2026-01-29 03:11:20.970 [DEBUG] fake_trx.py:382 (BTS@172.18.28.20:5700) Recv FAKE_TRXC_DELAY cmd
2026-01-29 03:11:20.971 [INFO] fake_trx.py:385 (BTS@172.18.28.20:5700) Artificial TRXC delay set to 200
2026-01-29 03:11:20.971 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD FAKE_TRXC_DELAY
2026-01-29 03:11:21.204 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:11:21.398 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-01-29 03:11:21.405 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:11:21.606 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:11:21.606 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:11:21.606 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:11:21.607 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:11:21.807 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 03:11:21.876 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-01-29 03:11:22.355 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-01-29 03:11:22.412 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:11:22.613 [DEBUG] fake_trx.py:382 (BTS@172.18.28.20:5700) Recv FAKE_TRXC_DELAY cmd
2026-01-29 03:11:22.620 [INFO] fake_trx.py:385 (BTS@172.18.28.20:5700) Artificial TRXC delay set to 0
2026-01-29 03:11:22.620 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD FAKE_TRXC_DELAY
2026-01-29 03:11:22.620 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:11:22.620 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:11:22.620 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:11:22.620 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:11:22.628 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 03:11:22.628 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:11:22.628 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:11:22.629 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:11:22.629 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 03:11:22.629 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 03:11:22.629 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 03:11:22.629 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.28.20:5700) Recv POWEROFF cmd
2026-01-29 03:11:22.629 [INFO] ctrl_if_trx.py:117 (BTS@172.18.28.20:5700) Stopping transceiver...
2026-01-29 03:11:22.629 [INFO] transceiver.py:246 Stopping clock generator
2026-01-29 03:11:22.629 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 03:11:27.631 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.28.20:5700) Recv POWEROFF cmd
2026-01-29 03:11:27.631 [INFO] ctrl_if_trx.py:117 (BTS@172.18.28.20:5700) Stopping transceiver...
2026-01-29 03:11:27.632 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 03:11:27.634 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 03:11:27.635 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 03:11:27.638 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 03:11:27.645 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 03:11:27.646 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.28.20:5700) Recv SETFORMAT cmd
2026-01-29 03:11:27.646 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.28.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:11:27.646 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.28.20:5700) Recv SETFORMAT cmd
2026-01-29 03:11:27.646 [INFO] ctrl_if_trx.py:201 (BTS@172.18.28.20:5700) TRXD header version 1 -> 1
2026-01-29 03:11:27.648 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.28.20:5700/1) Recv RXTUNE cmd
2026-01-29 03:11:27.648 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.28.20:5700/1) Recv TXTUNE cmd
2026-01-29 03:11:27.648 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.28.20:5700/1) Recv SETFORMAT cmd
2026-01-29 03:11:27.648 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.28.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:11:27.649 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 03:11:27.649 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.28.20:5700/1) Recv NOMTXPOWER cmd
2026-01-29 03:11:27.649 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.28.20:5700/1) Recv SETFORMAT cmd
2026-01-29 03:11:27.649 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.28.20:5700/1) TRXD header version 1 -> 1
2026-01-29 03:11:27.650 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.28.20:5700/2) Recv RXTUNE cmd
2026-01-29 03:11:27.650 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.28.20:5700/2) Recv TXTUNE cmd
2026-01-29 03:11:27.650 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.28.20:5700/2) Recv SETFORMAT cmd
2026-01-29 03:11:27.650 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.28.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:11:27.650 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 03:11:27.650 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.28.20:5700/2) Recv NOMTXPOWER cmd
2026-01-29 03:11:27.650 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.28.20:5700/2) Recv SETFORMAT cmd
2026-01-29 03:11:27.650 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.28.20:5700/2) TRXD header version 1 -> 1
2026-01-29 03:11:27.651 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.28.20:5700/3) Recv RXTUNE cmd
2026-01-29 03:11:27.652 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.28.20:5700/3) Recv TXTUNE cmd
2026-01-29 03:11:27.652 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.28.20:5700/3) Recv SETFORMAT cmd
2026-01-29 03:11:27.652 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.28.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:11:27.652 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 03:11:27.652 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.28.20:5700/3) Recv NOMTXPOWER cmd
2026-01-29 03:11:27.652 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.28.20:5700/3) Recv SETFORMAT cmd
2026-01-29 03:11:27.652 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.28.20:5700/3) TRXD header version 1 -> 1
2026-01-29 03:11:27.654 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.28.20:5700) Recv RXTUNE cmd
2026-01-29 03:11:27.654 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETTSC
2026-01-29 03:11:27.654 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETTSC
2026-01-29 03:11:27.654 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETTSC
2026-01-29 03:11:27.654 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.28.20:5700) Recv TXTUNE cmd
2026-01-29 03:11:27.654 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETRXGAIN
2026-01-29 03:11:27.654 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETRXGAIN
2026-01-29 03:11:27.654 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETTSC
2026-01-29 03:11:27.654 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETRXGAIN
2026-01-29 03:11:27.654 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.28.20:5700) Recv NOMTXPOWER cmd
2026-01-29 03:11:27.654 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:11:27.654 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:11:27.654 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.28.20:5700) Recv POWERON CMD
2026-01-29 03:11:27.654 [INFO] ctrl_if_trx.py:109 (BTS@172.18.28.20:5700) Starting transceiver...
2026-01-29 03:11:27.654 [INFO] transceiver.py:243 Starting clock generator
2026-01-29 03:11:27.654 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-01-29 03:11:27.654 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:11:27.654 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:11:27.654 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:11:27.654 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETRXGAIN
2026-01-29 03:11:27.654 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:11:27.654 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:11:27.654 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:11:27.654 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:11:27.654 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:11:27.654 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:11:27.654 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:11:27.654 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:11:27.655 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:11:27.655 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:11:27.655 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:11:27.655 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:11:27.655 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:11:27.655 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:11:27.655 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:11:27.655 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:11:27.655 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:11:27.655 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:11:27.655 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:11:27.655 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:11:27.655 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:11:27.655 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:11:27.655 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:11:27.655 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:11:27.655 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:11:27.655 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:11:27.655 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:11:27.659 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-01-29 03:11:28.142 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-01-29 03:11:28.182 [DEBUG] fake_trx.py:278 (BTS@172.18.28.20:5700) Recv FAKE_TOA cmd
2026-01-29 03:11:28.184 [DEBUG] fake_trx.py:297 (BTS@172.18.28.20:5700) Recv FAKE_RSSI cmd
2026-01-29 03:11:28.186 [DEBUG] fake_trx.py:322 (BTS@172.18.28.20:5700) Recv FAKE_CI cmd
2026-01-29 03:11:28.187 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:11:28.188 [DEBUG] fake_trx.py:382 (BTS@172.18.28.20:5700) Recv FAKE_TRXC_DELAY cmd
2026-01-29 03:11:28.189 [INFO] fake_trx.py:385 (BTS@172.18.28.20:5700) Artificial TRXC delay set to 200
2026-01-29 03:11:28.189 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD FAKE_TRXC_DELAY
2026-01-29 03:11:28.422 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:11:28.622 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-01-29 03:11:28.626 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:11:28.826 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:11:28.826 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:11:28.826 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:11:28.827 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:11:29.027 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:11:29.100 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-01-29 03:11:29.228 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:11:29.429 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:11:29.579 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-01-29 03:11:29.629 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:11:29.830 [DEBUG] fake_trx.py:382 (BTS@172.18.28.20:5700) Recv FAKE_TRXC_DELAY cmd
2026-01-29 03:11:29.830 [INFO] fake_trx.py:385 (BTS@172.18.28.20:5700) Artificial TRXC delay set to 0
2026-01-29 03:11:29.830 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD FAKE_TRXC_DELAY
2026-01-29 03:11:29.830 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:11:29.831 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:11:29.831 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:11:29.831 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:11:29.831 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:11:29.831 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 03:11:29.832 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:11:29.832 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:11:29.832 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:11:29.833 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:11:29.833 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:11:29.833 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:11:29.833 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:11:29.834 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:11:29.840 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 03:11:29.840 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:11:29.840 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:11:29.840 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:11:29.841 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 03:11:29.841 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 03:11:29.842 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 03:11:29.842 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 03:11:29.842 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.28.20:5700) Recv POWEROFF cmd
2026-01-29 03:11:29.842 [INFO] ctrl_if_trx.py:117 (BTS@172.18.28.20:5700) Stopping transceiver...
2026-01-29 03:11:29.842 [INFO] transceiver.py:246 Stopping clock generator
2026-01-29 03:11:34.842 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.28.20:5700) Recv POWEROFF cmd
2026-01-29 03:11:34.846 [INFO] ctrl_if_trx.py:117 (BTS@172.18.28.20:5700) Stopping transceiver...
2026-01-29 03:11:34.846 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 03:11:34.846 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 03:11:34.846 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 03:11:34.846 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 03:11:34.855 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 03:11:34.856 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.28.20:5700) Recv SETFORMAT cmd
2026-01-29 03:11:34.856 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.28.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:11:34.857 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.28.20:5700) Recv SETFORMAT cmd
2026-01-29 03:11:34.857 [INFO] ctrl_if_trx.py:201 (BTS@172.18.28.20:5700) TRXD header version 1 -> 1
2026-01-29 03:11:34.860 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.28.20:5700/1) Recv RXTUNE cmd
2026-01-29 03:11:34.860 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.28.20:5700/1) Recv TXTUNE cmd
2026-01-29 03:11:34.861 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.28.20:5700/1) Recv SETFORMAT cmd
2026-01-29 03:11:34.861 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.28.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:11:34.861 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 03:11:34.861 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.28.20:5700/1) Recv NOMTXPOWER cmd
2026-01-29 03:11:34.862 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.28.20:5700/1) Recv SETFORMAT cmd
2026-01-29 03:11:34.862 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.28.20:5700/1) TRXD header version 1 -> 1
2026-01-29 03:11:34.863 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.28.20:5700/2) Recv RXTUNE cmd
2026-01-29 03:11:34.863 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.28.20:5700/2) Recv TXTUNE cmd
2026-01-29 03:11:34.863 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.28.20:5700/2) Recv SETFORMAT cmd
2026-01-29 03:11:34.863 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.28.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:11:34.863 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 03:11:34.863 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.28.20:5700/2) Recv NOMTXPOWER cmd
2026-01-29 03:11:34.864 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.28.20:5700/2) Recv SETFORMAT cmd
2026-01-29 03:11:34.864 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.28.20:5700/2) TRXD header version 1 -> 1
2026-01-29 03:11:34.865 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.28.20:5700/3) Recv RXTUNE cmd
2026-01-29 03:11:34.866 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.28.20:5700/3) Recv TXTUNE cmd
2026-01-29 03:11:34.866 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.28.20:5700/3) Recv SETFORMAT cmd
2026-01-29 03:11:34.866 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.28.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:11:34.866 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 03:11:34.866 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.28.20:5700/3) Recv NOMTXPOWER cmd
2026-01-29 03:11:34.866 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.28.20:5700/3) Recv SETFORMAT cmd
2026-01-29 03:11:34.866 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.28.20:5700/3) TRXD header version 1 -> 1
2026-01-29 03:11:34.869 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.28.20:5700) Recv RXTUNE cmd
2026-01-29 03:11:34.869 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETTSC
2026-01-29 03:11:34.869 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETTSC
2026-01-29 03:11:34.869 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETTSC
2026-01-29 03:11:34.869 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.28.20:5700) Recv TXTUNE cmd
2026-01-29 03:11:34.869 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETRXGAIN
2026-01-29 03:11:34.869 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETRXGAIN
2026-01-29 03:11:34.869 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETRXGAIN
2026-01-29 03:11:34.869 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETTSC
2026-01-29 03:11:34.869 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:11:34.869 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:11:34.869 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:11:34.869 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.28.20:5700) Recv NOMTXPOWER cmd
2026-01-29 03:11:34.869 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:11:34.869 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:11:34.869 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:11:34.869 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.28.20:5700) Recv POWERON CMD
2026-01-29 03:11:34.869 [INFO] ctrl_if_trx.py:109 (BTS@172.18.28.20:5700) Starting transceiver...
2026-01-29 03:11:34.869 [INFO] transceiver.py:243 Starting clock generator
2026-01-29 03:11:34.869 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-01-29 03:11:34.869 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:11:34.870 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:11:34.870 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:11:34.870 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETRXGAIN
2026-01-29 03:11:34.870 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:11:34.870 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:11:34.870 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:11:34.870 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:11:34.870 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:11:34.870 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:11:34.870 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:11:34.870 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:11:34.870 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:11:34.870 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:11:34.870 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:11:34.870 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:11:34.870 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:11:34.870 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:11:34.870 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:11:34.870 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:11:34.870 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:11:34.870 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:11:34.870 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:11:34.870 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:11:34.870 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:11:34.870 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:11:34.870 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:11:34.874 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-01-29 03:11:35.352 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-01-29 03:11:35.395 [DEBUG] fake_trx.py:278 (BTS@172.18.28.20:5700) Recv FAKE_TOA cmd
2026-01-29 03:11:35.396 [DEBUG] fake_trx.py:297 (BTS@172.18.28.20:5700) Recv FAKE_RSSI cmd
2026-01-29 03:11:35.398 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:11:35.399 [DEBUG] fake_trx.py:322 (BTS@172.18.28.20:5700) Recv FAKE_CI cmd
2026-01-29 03:11:35.421 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 03:11:35.421 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 03:11:35.421 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 03:11:35.435 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:11:35.440 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:11:35.448 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 03:11:35.449 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:11:35.449 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:11:35.449 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:11:35.452 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 03:11:35.452 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 03:11:35.452 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 03:11:35.452 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.28.20:5700) Recv POWEROFF cmd
2026-01-29 03:11:35.452 [INFO] ctrl_if_trx.py:117 (BTS@172.18.28.20:5700) Stopping transceiver...
2026-01-29 03:11:35.452 [INFO] transceiver.py:246 Stopping clock generator
2026-01-29 03:11:35.453 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 03:11:35.453 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=125 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:11:35.453 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=125 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:11:35.453 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=125 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:11:35.453 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=125 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:11:35.453 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=125 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:11:35.453 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=125 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:11:35.453 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=125 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:11:40.453 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.28.20:5700) Recv POWEROFF cmd
2026-01-29 03:11:40.453 [INFO] ctrl_if_trx.py:117 (BTS@172.18.28.20:5700) Stopping transceiver...
2026-01-29 03:11:40.453 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 03:11:40.453 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 03:11:40.453 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 03:11:40.453 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 03:11:40.466 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 03:11:40.467 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.28.20:5700) Recv SETFORMAT cmd
2026-01-29 03:11:40.467 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.28.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:11:40.468 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.28.20:5700) Recv SETFORMAT cmd
2026-01-29 03:11:40.468 [INFO] ctrl_if_trx.py:201 (BTS@172.18.28.20:5700) TRXD header version 1 -> 1
2026-01-29 03:11:40.470 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.28.20:5700/1) Recv RXTUNE cmd
2026-01-29 03:11:40.470 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.28.20:5700/1) Recv TXTUNE cmd
2026-01-29 03:11:40.471 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.28.20:5700/1) Recv SETFORMAT cmd
2026-01-29 03:11:40.471 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.28.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:11:40.471 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 03:11:40.471 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.28.20:5700/1) Recv NOMTXPOWER cmd
2026-01-29 03:11:40.471 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.28.20:5700/1) Recv SETFORMAT cmd
2026-01-29 03:11:40.471 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.28.20:5700/1) TRXD header version 1 -> 1
2026-01-29 03:11:40.473 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.28.20:5700/2) Recv RXTUNE cmd
2026-01-29 03:11:40.473 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.28.20:5700/2) Recv TXTUNE cmd
2026-01-29 03:11:40.473 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.28.20:5700/2) Recv SETFORMAT cmd
2026-01-29 03:11:40.473 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.28.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:11:40.473 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 03:11:40.473 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.28.20:5700/2) Recv NOMTXPOWER cmd
2026-01-29 03:11:40.474 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.28.20:5700/2) Recv SETFORMAT cmd
2026-01-29 03:11:40.474 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.28.20:5700/2) TRXD header version 1 -> 1
2026-01-29 03:11:40.475 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.28.20:5700/3) Recv RXTUNE cmd
2026-01-29 03:11:40.475 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.28.20:5700/3) Recv TXTUNE cmd
2026-01-29 03:11:40.476 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.28.20:5700/3) Recv SETFORMAT cmd
2026-01-29 03:11:40.476 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.28.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:11:40.476 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 03:11:40.476 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.28.20:5700/3) Recv NOMTXPOWER cmd
2026-01-29 03:11:40.476 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.28.20:5700/3) Recv SETFORMAT cmd
2026-01-29 03:11:40.476 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.28.20:5700/3) TRXD header version 1 -> 1
2026-01-29 03:11:40.478 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.28.20:5700) Recv RXTUNE cmd
2026-01-29 03:11:40.478 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETTSC
2026-01-29 03:11:40.478 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETTSC
2026-01-29 03:11:40.478 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETTSC
2026-01-29 03:11:40.479 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.28.20:5700) Recv TXTUNE cmd
2026-01-29 03:11:40.479 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETRXGAIN
2026-01-29 03:11:40.479 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETRXGAIN
2026-01-29 03:11:40.479 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETRXGAIN
2026-01-29 03:11:40.479 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETTSC
2026-01-29 03:11:40.479 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:11:40.479 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:11:40.479 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:11:40.479 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.28.20:5700) Recv NOMTXPOWER cmd
2026-01-29 03:11:40.479 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:11:40.479 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:11:40.479 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:11:40.479 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.28.20:5700) Recv POWERON CMD
2026-01-29 03:11:40.479 [INFO] ctrl_if_trx.py:109 (BTS@172.18.28.20:5700) Starting transceiver...
2026-01-29 03:11:40.479 [INFO] transceiver.py:243 Starting clock generator
2026-01-29 03:11:40.479 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-01-29 03:11:40.479 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:11:40.479 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:11:40.479 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:11:40.479 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETRXGAIN
2026-01-29 03:11:40.480 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:11:40.480 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:11:40.480 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:11:40.480 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:11:40.480 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:11:40.480 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:11:40.480 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:11:40.480 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:11:40.480 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:11:40.480 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:11:40.480 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:11:40.480 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:11:40.480 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:11:40.480 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:11:40.480 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:11:40.480 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:11:40.480 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:11:40.480 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:11:40.480 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:11:40.480 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:11:40.480 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:11:40.480 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:11:40.480 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:11:40.484 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-01-29 03:11:40.965 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-01-29 03:11:40.995 [DEBUG] fake_trx.py:278 (BTS@172.18.28.20:5700) Recv FAKE_TOA cmd
2026-01-29 03:11:40.995 [DEBUG] fake_trx.py:297 (BTS@172.18.28.20:5700) Recv FAKE_RSSI cmd
2026-01-29 03:11:40.996 [DEBUG] fake_trx.py:322 (BTS@172.18.28.20:5700) Recv FAKE_CI cmd
2026-01-29 03:11:40.996 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:11:41.007 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 03:11:41.008 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 03:11:41.008 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 03:11:41.021 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:11:41.027 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:11:41.032 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 03:11:41.032 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:11:41.033 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:11:41.033 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:11:41.036 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 03:11:41.036 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 03:11:41.036 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 03:11:41.036 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.28.20:5700) Recv POWEROFF cmd
2026-01-29 03:11:41.036 [INFO] ctrl_if_trx.py:117 (BTS@172.18.28.20:5700) Stopping transceiver...
2026-01-29 03:11:41.037 [INFO] transceiver.py:246 Stopping clock generator
2026-01-29 03:11:41.037 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 03:11:41.037 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=118 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:11:41.037 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=118 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:11:41.037 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=118 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:11:41.037 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=118 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:11:41.038 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=118 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:11:41.038 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=118 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:11:41.038 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=118 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:11:46.036 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.28.20:5700) Recv POWEROFF cmd
2026-01-29 03:11:46.036 [INFO] ctrl_if_trx.py:117 (BTS@172.18.28.20:5700) Stopping transceiver...
2026-01-29 03:11:46.037 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 03:11:46.042 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 03:11:46.042 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 03:11:46.043 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 03:11:46.058 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 03:11:46.059 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.28.20:5700) Recv SETFORMAT cmd
2026-01-29 03:11:46.059 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.28.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:11:46.060 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.28.20:5700) Recv SETFORMAT cmd
2026-01-29 03:11:46.060 [INFO] ctrl_if_trx.py:201 (BTS@172.18.28.20:5700) TRXD header version 1 -> 1
2026-01-29 03:11:46.063 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.28.20:5700/1) Recv RXTUNE cmd
2026-01-29 03:11:46.063 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.28.20:5700/1) Recv TXTUNE cmd
2026-01-29 03:11:46.063 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.28.20:5700/1) Recv SETFORMAT cmd
2026-01-29 03:11:46.064 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.28.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:11:46.064 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 03:11:46.064 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.28.20:5700/1) Recv NOMTXPOWER cmd
2026-01-29 03:11:46.064 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.28.20:5700/1) Recv SETFORMAT cmd
2026-01-29 03:11:46.064 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.28.20:5700/1) TRXD header version 1 -> 1
2026-01-29 03:11:46.066 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.28.20:5700/2) Recv RXTUNE cmd
2026-01-29 03:11:46.066 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.28.20:5700/2) Recv TXTUNE cmd
2026-01-29 03:11:46.066 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.28.20:5700/2) Recv SETFORMAT cmd
2026-01-29 03:11:46.066 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.28.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:11:46.066 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 03:11:46.066 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.28.20:5700/2) Recv NOMTXPOWER cmd
2026-01-29 03:11:46.066 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.28.20:5700/2) Recv SETFORMAT cmd
2026-01-29 03:11:46.066 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.28.20:5700/2) TRXD header version 1 -> 1
2026-01-29 03:11:46.068 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.28.20:5700/3) Recv RXTUNE cmd
2026-01-29 03:11:46.068 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.28.20:5700/3) Recv TXTUNE cmd
2026-01-29 03:11:46.069 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.28.20:5700/3) Recv SETFORMAT cmd
2026-01-29 03:11:46.069 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.28.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:11:46.069 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 03:11:46.069 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.28.20:5700/3) Recv NOMTXPOWER cmd
2026-01-29 03:11:46.069 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.28.20:5700/3) Recv SETFORMAT cmd
2026-01-29 03:11:46.069 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.28.20:5700/3) TRXD header version 1 -> 1
2026-01-29 03:11:46.072 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.28.20:5700) Recv RXTUNE cmd
2026-01-29 03:11:46.072 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETTSC
2026-01-29 03:11:46.072 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETTSC
2026-01-29 03:11:46.072 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETTSC
2026-01-29 03:11:46.072 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.28.20:5700) Recv TXTUNE cmd
2026-01-29 03:11:46.072 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETRXGAIN
2026-01-29 03:11:46.072 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETRXGAIN
2026-01-29 03:11:46.072 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETRXGAIN
2026-01-29 03:11:46.072 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETTSC
2026-01-29 03:11:46.072 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:11:46.072 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:11:46.072 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.28.20:5700) Recv NOMTXPOWER cmd
2026-01-29 03:11:46.072 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:11:46.072 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:11:46.072 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:11:46.072 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.28.20:5700) Recv POWERON CMD
2026-01-29 03:11:46.072 [INFO] ctrl_if_trx.py:109 (BTS@172.18.28.20:5700) Starting transceiver...
2026-01-29 03:11:46.072 [INFO] transceiver.py:243 Starting clock generator
2026-01-29 03:11:46.073 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-01-29 03:11:46.073 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:11:46.073 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:11:46.073 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:11:46.073 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETRXGAIN
2026-01-29 03:11:46.073 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:11:46.073 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:11:46.073 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:11:46.073 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:11:46.073 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:11:46.073 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:11:46.073 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:11:46.073 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:11:46.073 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:11:46.073 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:11:46.074 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:11:46.074 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:11:46.074 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:11:46.074 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:11:46.074 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:11:46.074 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:11:46.074 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:11:46.074 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:11:46.074 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:11:46.074 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:11:46.074 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:11:46.074 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:11:46.074 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:11:46.074 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:11:46.077 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-01-29 03:11:46.555 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-01-29 03:11:46.602 [DEBUG] fake_trx.py:278 (BTS@172.18.28.20:5700) Recv FAKE_TOA cmd
2026-01-29 03:11:46.605 [DEBUG] fake_trx.py:297 (BTS@172.18.28.20:5700) Recv FAKE_RSSI cmd
2026-01-29 03:11:46.606 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:11:46.606 [DEBUG] fake_trx.py:322 (BTS@172.18.28.20:5700) Recv FAKE_CI cmd
2026-01-29 03:11:46.633 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 03:11:46.633 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 03:11:46.633 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 03:11:46.638 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 03:11:46.638 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 03:11:46.638 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 03:11:46.638 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.28.22:6700) Recv POWERON CMD
2026-01-29 03:11:46.638 [INFO] ctrl_if_trx.py:109 (MS@172.18.28.22:6700) Starting transceiver...
2026-01-29 03:11:46.651 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:11:46.656 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 03:11:46.656 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 03:11:46.656 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 03:11:46.656 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 03:11:46.714 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:11:46.717 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 03:11:46.719 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 03:11:46.719 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 03:11:46.738 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 03:11:46.738 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 03:11:46.738 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 03:11:46.739 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 03:11:46.739 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 03:11:46.739 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 03:11:46.739 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.28.22:6700) Recv POWERON CMD
2026-01-29 03:11:46.739 [INFO] ctrl_if_trx.py:109 (MS@172.18.28.22:6700) Starting transceiver...
2026-01-29 03:11:46.794 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:11:46.799 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 03:11:46.800 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 03:11:46.800 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 03:11:46.800 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 03:11:47.031 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-01-29 03:11:47.076 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 03:11:47.076 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:11:47.079 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:11:47.080 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:11:47.509 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-01-29 03:11:47.987 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-01-29 03:11:48.076 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 03:11:48.077 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:11:48.080 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:11:48.081 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:11:48.465 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-01-29 03:11:48.943 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-01-29 03:11:49.078 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 03:11:49.078 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:11:49.081 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:11:49.082 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:11:49.421 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-01-29 03:11:49.804 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:11:49.807 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 03:11:49.808 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 03:11:49.808 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 03:11:49.829 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 03:11:49.829 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 03:11:49.829 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 03:11:49.830 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 03:11:49.830 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 03:11:49.830 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 03:11:49.830 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.28.22:6700) Recv POWERON CMD
2026-01-29 03:11:49.830 [INFO] ctrl_if_trx.py:109 (MS@172.18.28.22:6700) Starting transceiver...
2026-01-29 03:11:49.839 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:11:49.840 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 03:11:49.840 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 03:11:49.840 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 03:11:49.840 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 03:11:49.891 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:11:49.894 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 03:11:49.895 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 03:11:49.895 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 03:11:49.897 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-01-29 03:11:49.914 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 03:11:49.914 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 03:11:49.914 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 03:11:49.915 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 03:11:49.915 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 03:11:49.915 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 03:11:49.915 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.28.22:6700) Recv POWERON CMD
2026-01-29 03:11:49.915 [INFO] ctrl_if_trx.py:109 (MS@172.18.28.22:6700) Starting transceiver...
2026-01-29 03:11:49.945 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:11:49.950 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 03:11:49.950 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 03:11:49.951 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 03:11:49.951 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 03:11:50.079 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:11:50.079 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 03:11:50.082 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:11:50.083 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:11:50.373 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-01-29 03:11:50.850 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-01-29 03:11:51.079 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 03:11:51.080 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:11:51.083 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:11:51.083 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:11:51.329 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-01-29 03:11:51.807 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-01-29 03:11:52.285 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-01-29 03:11:52.763 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-01-29 03:11:52.954 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:11:52.956 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 03:11:52.959 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 03:11:52.959 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 03:11:52.976 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 03:11:52.976 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 03:11:52.976 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 03:11:52.977 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 03:11:52.977 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 03:11:52.977 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 03:11:52.977 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.28.22:6700) Recv POWERON CMD
2026-01-29 03:11:52.977 [INFO] ctrl_if_trx.py:109 (MS@172.18.28.22:6700) Starting transceiver...
2026-01-29 03:11:52.996 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:11:52.998 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 03:11:52.998 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 03:11:52.998 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 03:11:52.998 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 03:11:53.240 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-01-29 03:11:53.714 [DEBUG] clck_gen.py:113 IND CLOCK 1632
2026-01-29 03:11:54.193 [DEBUG] clck_gen.py:113 IND CLOCK 1734
2026-01-29 03:11:54.670 [DEBUG] clck_gen.py:113 IND CLOCK 1836
2026-01-29 03:11:55.148 [DEBUG] clck_gen.py:113 IND CLOCK 1938
2026-01-29 03:11:55.626 [DEBUG] clck_gen.py:113 IND CLOCK 2040
2026-01-29 03:11:56.001 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:11:56.004 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 03:11:56.006 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 03:11:56.006 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 03:11:56.027 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 03:11:56.027 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 03:11:56.027 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 03:11:56.028 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 03:11:56.028 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 03:11:56.028 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 03:11:56.028 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.28.22:6700) Recv POWERON CMD
2026-01-29 03:11:56.028 [INFO] ctrl_if_trx.py:109 (MS@172.18.28.22:6700) Starting transceiver...
2026-01-29 03:11:56.044 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:11:56.047 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 03:11:56.047 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 03:11:56.047 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 03:11:56.047 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 03:11:56.097 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:11:56.099 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 03:11:56.100 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 03:11:56.100 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 03:11:56.103 [DEBUG] clck_gen.py:113 IND CLOCK 2142
2026-01-29 03:11:56.118 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 03:11:56.118 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 03:11:56.118 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 03:11:56.119 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 03:11:56.119 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 03:11:56.119 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 03:11:56.119 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.28.22:6700) Recv POWERON CMD
2026-01-29 03:11:56.119 [INFO] ctrl_if_trx.py:109 (MS@172.18.28.22:6700) Starting transceiver...
2026-01-29 03:11:56.152 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:11:56.158 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 03:11:56.158 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 03:11:56.159 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 03:11:56.159 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 03:11:56.581 [DEBUG] clck_gen.py:113 IND CLOCK 2244
2026-01-29 03:11:57.059 [DEBUG] clck_gen.py:113 IND CLOCK 2346
2026-01-29 03:11:57.263 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:11:57.266 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 03:11:57.267 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 03:11:57.267 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 03:11:57.286 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 03:11:57.286 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 03:11:57.286 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 03:11:57.287 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 03:11:57.288 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 03:11:57.288 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 03:11:57.288 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.28.22:6700) Recv POWERON CMD
2026-01-29 03:11:57.288 [INFO] ctrl_if_trx.py:109 (MS@172.18.28.22:6700) Starting transceiver...
2026-01-29 03:11:57.291 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:11:57.292 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.28.22:6700) Recv SETFH cmd
2026-01-29 03:11:57.292 [INFO] transceiver.py:201 (MS@172.18.28.22:6700) Frequency hopping configured: hsn=5, maio=0, ma_len=4
2026-01-29 03:11:57.292 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 03:11:57.292 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 03:11:57.359 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:11:57.362 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 03:11:57.363 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 03:11:57.363 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 03:11:57.363 [INFO] transceiver.py:205 (MS@172.18.28.22:6700) Frequency hopping disabled
2026-01-29 03:11:57.385 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 03:11:57.385 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 03:11:57.385 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 03:11:57.387 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 03:11:57.387 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 03:11:57.387 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 03:11:57.387 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.28.22:6700) Recv POWERON CMD
2026-01-29 03:11:57.387 [INFO] ctrl_if_trx.py:109 (MS@172.18.28.22:6700) Starting transceiver...
2026-01-29 03:11:57.434 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:11:57.439 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.28.22:6700) Recv SETFH cmd
2026-01-29 03:11:57.439 [INFO] transceiver.py:201 (MS@172.18.28.22:6700) Frequency hopping configured: hsn=5, maio=0, ma_len=4
2026-01-29 03:11:57.440 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 03:11:57.440 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 03:11:57.532 [DEBUG] clck_gen.py:113 IND CLOCK 2448
2026-01-29 03:11:58.002 [DEBUG] clck_gen.py:113 IND CLOCK 2550
2026-01-29 03:11:58.477 [DEBUG] clck_gen.py:113 IND CLOCK 2652
2026-01-29 03:11:58.957 [DEBUG] clck_gen.py:113 IND CLOCK 2754
2026-01-29 03:11:59.435 [DEBUG] clck_gen.py:113 IND CLOCK 2856
2026-01-29 03:11:59.914 [DEBUG] clck_gen.py:113 IND CLOCK 2958
2026-01-29 03:12:00.393 [DEBUG] clck_gen.py:113 IND CLOCK 3060
2026-01-29 03:12:00.443 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:12:00.446 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 03:12:00.447 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 03:12:00.447 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 03:12:00.448 [INFO] transceiver.py:205 (MS@172.18.28.22:6700) Frequency hopping disabled
2026-01-29 03:12:00.467 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 03:12:00.467 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 03:12:00.467 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 03:12:00.468 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 03:12:00.468 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 03:12:00.468 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 03:12:00.468 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.28.22:6700) Recv POWERON CMD
2026-01-29 03:12:00.468 [INFO] ctrl_if_trx.py:109 (MS@172.18.28.22:6700) Starting transceiver...
2026-01-29 03:12:00.484 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:12:00.487 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.28.22:6700) Recv SETFH cmd
2026-01-29 03:12:00.487 [INFO] transceiver.py:201 (MS@172.18.28.22:6700) Frequency hopping configured: hsn=5, maio=0, ma_len=4
2026-01-29 03:12:00.487 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 03:12:00.487 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 03:12:00.560 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:12:00.562 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 03:12:00.564 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 03:12:00.564 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 03:12:00.564 [INFO] transceiver.py:205 (MS@172.18.28.22:6700) Frequency hopping disabled
2026-01-29 03:12:00.580 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 03:12:00.580 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 03:12:00.580 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 03:12:00.581 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 03:12:00.581 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 03:12:00.581 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 03:12:00.581 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.28.22:6700) Recv POWERON CMD
2026-01-29 03:12:00.581 [INFO] ctrl_if_trx.py:109 (MS@172.18.28.22:6700) Starting transceiver...
2026-01-29 03:12:00.631 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:12:00.636 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.28.22:6700) Recv SETFH cmd
2026-01-29 03:12:00.636 [INFO] transceiver.py:201 (MS@172.18.28.22:6700) Frequency hopping configured: hsn=5, maio=0, ma_len=4
2026-01-29 03:12:00.637 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 03:12:00.637 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 03:12:00.869 [DEBUG] clck_gen.py:113 IND CLOCK 3162
2026-01-29 03:12:01.347 [DEBUG] clck_gen.py:113 IND CLOCK 3264
2026-01-29 03:12:01.826 [DEBUG] clck_gen.py:113 IND CLOCK 3366
2026-01-29 03:12:02.305 [DEBUG] clck_gen.py:113 IND CLOCK 3468
2026-01-29 03:12:02.783 [DEBUG] clck_gen.py:113 IND CLOCK 3570
2026-01-29 03:12:03.262 [DEBUG] clck_gen.py:113 IND CLOCK 3672
2026-01-29 03:12:03.641 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:12:03.644 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 03:12:03.646 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 03:12:03.646 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 03:12:03.646 [INFO] transceiver.py:205 (MS@172.18.28.22:6700) Frequency hopping disabled
2026-01-29 03:12:03.666 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 03:12:03.666 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 03:12:03.666 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 03:12:03.667 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 03:12:03.667 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 03:12:03.667 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 03:12:03.667 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.28.22:6700) Recv POWERON CMD
2026-01-29 03:12:03.667 [INFO] ctrl_if_trx.py:109 (MS@172.18.28.22:6700) Starting transceiver...
2026-01-29 03:12:03.679 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:12:03.681 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.28.22:6700) Recv SETFH cmd
2026-01-29 03:12:03.681 [INFO] transceiver.py:201 (MS@172.18.28.22:6700) Frequency hopping configured: hsn=5, maio=0, ma_len=4
2026-01-29 03:12:03.681 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 03:12:03.681 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 03:12:03.739 [DEBUG] clck_gen.py:113 IND CLOCK 3774
2026-01-29 03:12:04.208 [DEBUG] clck_gen.py:113 IND CLOCK 3876
2026-01-29 03:12:04.677 [DEBUG] clck_gen.py:113 IND CLOCK 3978
2026-01-29 03:12:05.148 [DEBUG] clck_gen.py:113 IND CLOCK 4080
2026-01-29 03:12:05.625 [DEBUG] clck_gen.py:113 IND CLOCK 4182
2026-01-29 03:12:06.104 [DEBUG] clck_gen.py:113 IND CLOCK 4284
2026-01-29 03:12:06.582 [DEBUG] clck_gen.py:113 IND CLOCK 4386
2026-01-29 03:12:06.685 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:12:06.688 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 03:12:06.689 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 03:12:06.689 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 03:12:06.689 [INFO] transceiver.py:205 (MS@172.18.28.22:6700) Frequency hopping disabled
2026-01-29 03:12:06.710 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 03:12:06.710 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 03:12:06.711 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 03:12:06.712 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 03:12:06.712 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 03:12:06.712 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 03:12:06.712 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.28.22:6700) Recv POWERON CMD
2026-01-29 03:12:06.712 [INFO] ctrl_if_trx.py:109 (MS@172.18.28.22:6700) Starting transceiver...
2026-01-29 03:12:06.718 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:12:06.719 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.28.22:6700) Recv SETFH cmd
2026-01-29 03:12:06.719 [INFO] transceiver.py:201 (MS@172.18.28.22:6700) Frequency hopping configured: hsn=5, maio=0, ma_len=4
2026-01-29 03:12:06.719 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 03:12:06.719 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 03:12:06.783 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:12:06.784 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 03:12:06.785 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 03:12:06.785 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 03:12:06.785 [INFO] transceiver.py:205 (MS@172.18.28.22:6700) Frequency hopping disabled
2026-01-29 03:12:06.801 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 03:12:06.801 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 03:12:06.801 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 03:12:06.803 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 03:12:06.803 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 03:12:06.803 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 03:12:06.803 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.28.22:6700) Recv POWERON CMD
2026-01-29 03:12:06.803 [INFO] ctrl_if_trx.py:109 (MS@172.18.28.22:6700) Starting transceiver...
2026-01-29 03:12:06.815 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:12:06.818 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.28.22:6700) Recv SETFH cmd
2026-01-29 03:12:06.818 [INFO] transceiver.py:201 (MS@172.18.28.22:6700) Frequency hopping configured: hsn=5, maio=0, ma_len=4
2026-01-29 03:12:06.818 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 03:12:06.818 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 03:12:07.059 [DEBUG] clck_gen.py:113 IND CLOCK 4488
2026-01-29 03:12:07.538 [DEBUG] clck_gen.py:113 IND CLOCK 4590
2026-01-29 03:12:07.707 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:12:07.710 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 03:12:07.711 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 03:12:07.712 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 03:12:07.712 [INFO] transceiver.py:205 (MS@172.18.28.22:6700) Frequency hopping disabled
2026-01-29 03:12:07.731 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 03:12:07.731 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 03:12:07.731 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 03:12:07.732 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 03:12:07.732 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 03:12:07.732 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 03:12:07.732 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.28.22:6700) Recv POWERON CMD
2026-01-29 03:12:07.732 [INFO] ctrl_if_trx.py:109 (MS@172.18.28.22:6700) Starting transceiver...
2026-01-29 03:12:07.777 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:12:07.782 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 03:12:07.782 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 03:12:07.783 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 03:12:07.783 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 03:12:08.001 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:12:08.004 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 03:12:08.005 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 03:12:08.006 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 03:12:08.016 [DEBUG] clck_gen.py:113 IND CLOCK 4692
2026-01-29 03:12:08.022 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 03:12:08.022 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 03:12:08.022 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 03:12:08.024 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 03:12:08.024 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 03:12:08.024 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 03:12:08.024 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.28.22:6700) Recv POWERON CMD
2026-01-29 03:12:08.024 [INFO] ctrl_if_trx.py:109 (MS@172.18.28.22:6700) Starting transceiver...
2026-01-29 03:12:08.066 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:12:08.071 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 03:12:08.071 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 03:12:08.071 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 03:12:08.071 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 03:12:08.493 [DEBUG] clck_gen.py:113 IND CLOCK 4794
2026-01-29 03:12:08.971 [DEBUG] clck_gen.py:113 IND CLOCK 4896
2026-01-29 03:12:09.448 [DEBUG] clck_gen.py:113 IND CLOCK 4998
2026-01-29 03:12:09.927 [DEBUG] clck_gen.py:113 IND CLOCK 5100
2026-01-29 03:12:10.405 [DEBUG] clck_gen.py:113 IND CLOCK 5202
2026-01-29 03:12:10.883 [DEBUG] clck_gen.py:113 IND CLOCK 5304
2026-01-29 03:12:11.076 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:12:11.078 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 03:12:11.080 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 03:12:11.080 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 03:12:11.097 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 03:12:11.097 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 03:12:11.097 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 03:12:11.098 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 03:12:11.098 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 03:12:11.098 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 03:12:11.098 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.28.22:6700) Recv POWERON CMD
2026-01-29 03:12:11.098 [INFO] ctrl_if_trx.py:109 (MS@172.18.28.22:6700) Starting transceiver...
2026-01-29 03:12:11.117 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:12:11.121 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 03:12:11.121 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 03:12:11.122 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 03:12:11.122 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 03:12:11.344 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:12:11.346 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 03:12:11.347 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 03:12:11.347 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 03:12:11.360 [DEBUG] clck_gen.py:113 IND CLOCK 5406
2026-01-29 03:12:11.361 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 03:12:11.361 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 03:12:11.361 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 03:12:11.363 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 03:12:11.363 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 03:12:11.363 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 03:12:11.363 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.28.22:6700) Recv POWERON CMD
2026-01-29 03:12:11.363 [INFO] ctrl_if_trx.py:109 (MS@172.18.28.22:6700) Starting transceiver...
2026-01-29 03:12:11.408 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:12:11.413 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 03:12:11.413 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 03:12:11.413 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 03:12:11.414 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 03:12:11.835 [DEBUG] clck_gen.py:113 IND CLOCK 5508
2026-01-29 03:12:12.312 [DEBUG] clck_gen.py:113 IND CLOCK 5610
2026-01-29 03:12:12.791 [DEBUG] clck_gen.py:113 IND CLOCK 5712
2026-01-29 03:12:13.269 [DEBUG] clck_gen.py:113 IND CLOCK 5814
2026-01-29 03:12:13.747 [DEBUG] clck_gen.py:113 IND CLOCK 5916
2026-01-29 03:12:14.225 [DEBUG] clck_gen.py:113 IND CLOCK 6018
2026-01-29 03:12:14.418 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:12:14.420 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 03:12:14.421 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 03:12:14.421 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 03:12:14.440 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 03:12:14.440 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 03:12:14.440 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 03:12:14.442 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 03:12:14.442 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 03:12:14.442 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 03:12:14.442 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.28.22:6700) Recv POWERON CMD
2026-01-29 03:12:14.442 [INFO] ctrl_if_trx.py:109 (MS@172.18.28.22:6700) Starting transceiver...
2026-01-29 03:12:14.459 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:12:14.463 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 03:12:14.463 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 03:12:14.464 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 03:12:14.464 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 03:12:14.702 [DEBUG] clck_gen.py:113 IND CLOCK 6120
2026-01-29 03:12:15.180 [DEBUG] clck_gen.py:113 IND CLOCK 6222
2026-01-29 03:12:15.659 [DEBUG] clck_gen.py:113 IND CLOCK 6324
2026-01-29 03:12:16.136 [DEBUG] clck_gen.py:113 IND CLOCK 6426
2026-01-29 03:12:16.614 [DEBUG] clck_gen.py:113 IND CLOCK 6528
2026-01-29 03:12:17.092 [DEBUG] clck_gen.py:113 IND CLOCK 6630
2026-01-29 03:12:17.468 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:12:17.471 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 03:12:17.473 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 03:12:17.473 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 03:12:17.490 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 03:12:17.490 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 03:12:17.490 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 03:12:17.491 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 03:12:17.491 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 03:12:17.491 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 03:12:17.491 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.28.22:6700) Recv POWERON CMD
2026-01-29 03:12:17.491 [INFO] ctrl_if_trx.py:109 (MS@172.18.28.22:6700) Starting transceiver...
2026-01-29 03:12:17.510 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:12:17.513 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 03:12:17.513 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 03:12:17.513 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 03:12:17.513 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 03:12:17.553 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:12:17.556 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 03:12:17.557 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 03:12:17.557 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 03:12:17.566 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 03:12:17.566 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 03:12:17.566 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 03:12:17.567 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 03:12:17.567 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 03:12:17.567 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 03:12:17.567 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.28.22:6700) Recv POWERON CMD
2026-01-29 03:12:17.567 [INFO] ctrl_if_trx.py:109 (MS@172.18.28.22:6700) Starting transceiver...
2026-01-29 03:12:17.568 [DEBUG] clck_gen.py:113 IND CLOCK 6732
2026-01-29 03:12:17.617 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:12:17.622 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 03:12:17.622 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 03:12:17.622 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 03:12:17.622 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 03:12:18.045 [DEBUG] clck_gen.py:113 IND CLOCK 6834
2026-01-29 03:12:18.523 [DEBUG] clck_gen.py:113 IND CLOCK 6936
2026-01-29 03:12:18.561 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:12:18.563 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 03:12:18.565 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 03:12:18.566 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 03:12:18.584 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 03:12:18.584 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 03:12:18.584 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 03:12:18.585 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 03:12:18.585 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 03:12:18.585 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 03:12:18.585 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.28.22:6700) Recv POWERON CMD
2026-01-29 03:12:18.585 [INFO] ctrl_if_trx.py:109 (MS@172.18.28.22:6700) Starting transceiver...
2026-01-29 03:12:18.617 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:12:18.622 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.28.22:6700) Recv SETFH cmd
2026-01-29 03:12:18.622 [INFO] transceiver.py:201 (MS@172.18.28.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2026-01-29 03:12:18.623 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 03:12:18.623 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 03:12:18.912 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:12:18.915 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 03:12:18.916 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 03:12:18.916 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 03:12:18.916 [INFO] transceiver.py:205 (MS@172.18.28.22:6700) Frequency hopping disabled
2026-01-29 03:12:18.931 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 03:12:18.931 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 03:12:18.931 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 03:12:18.933 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 03:12:18.933 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 03:12:18.933 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 03:12:18.933 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.28.22:6700) Recv POWERON CMD
2026-01-29 03:12:18.933 [INFO] ctrl_if_trx.py:109 (MS@172.18.28.22:6700) Starting transceiver...
2026-01-29 03:12:18.940 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:12:18.941 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.28.22:6700) Recv SETFH cmd
2026-01-29 03:12:18.941 [INFO] transceiver.py:201 (MS@172.18.28.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2026-01-29 03:12:18.941 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 03:12:18.941 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 03:12:19.000 [DEBUG] clck_gen.py:113 IND CLOCK 7038
2026-01-29 03:12:19.478 [DEBUG] clck_gen.py:113 IND CLOCK 7140
2026-01-29 03:12:19.957 [DEBUG] clck_gen.py:113 IND CLOCK 7242
2026-01-29 03:12:20.433 [DEBUG] clck_gen.py:113 IND CLOCK 7344
2026-01-29 03:12:20.912 [DEBUG] clck_gen.py:113 IND CLOCK 7446
2026-01-29 03:12:21.391 [DEBUG] clck_gen.py:113 IND CLOCK 7548
2026-01-29 03:12:21.869 [DEBUG] clck_gen.py:113 IND CLOCK 7650
2026-01-29 03:12:21.944 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:12:21.947 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 03:12:21.948 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 03:12:21.948 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 03:12:21.948 [INFO] transceiver.py:205 (MS@172.18.28.22:6700) Frequency hopping disabled
2026-01-29 03:12:21.962 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 03:12:21.962 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 03:12:21.962 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 03:12:21.963 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 03:12:21.963 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 03:12:21.964 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 03:12:21.964 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.28.22:6700) Recv POWERON CMD
2026-01-29 03:12:21.964 [INFO] ctrl_if_trx.py:109 (MS@172.18.28.22:6700) Starting transceiver...
2026-01-29 03:12:22.010 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:12:22.016 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.28.22:6700) Recv SETFH cmd
2026-01-29 03:12:22.016 [INFO] transceiver.py:201 (MS@172.18.28.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2026-01-29 03:12:22.016 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 03:12:22.016 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 03:12:22.348 [DEBUG] clck_gen.py:113 IND CLOCK 7752
2026-01-29 03:12:22.736 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:12:22.738 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 03:12:22.740 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 03:12:22.740 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 03:12:22.740 [INFO] transceiver.py:205 (MS@172.18.28.22:6700) Frequency hopping disabled
2026-01-29 03:12:22.758 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 03:12:22.759 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 03:12:22.759 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 03:12:22.760 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 03:12:22.760 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 03:12:22.760 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 03:12:22.760 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.28.22:6700) Recv POWERON CMD
2026-01-29 03:12:22.760 [INFO] ctrl_if_trx.py:109 (MS@172.18.28.22:6700) Starting transceiver...
2026-01-29 03:12:22.765 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:12:22.766 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.28.22:6700) Recv SETFH cmd
2026-01-29 03:12:22.766 [INFO] transceiver.py:201 (MS@172.18.28.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2026-01-29 03:12:22.766 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 03:12:22.766 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 03:12:22.825 [DEBUG] clck_gen.py:113 IND CLOCK 7854
2026-01-29 03:12:23.302 [DEBUG] clck_gen.py:113 IND CLOCK 7956
2026-01-29 03:12:23.780 [DEBUG] clck_gen.py:113 IND CLOCK 8058
2026-01-29 03:12:24.259 [DEBUG] clck_gen.py:113 IND CLOCK 8160
2026-01-29 03:12:24.738 [DEBUG] clck_gen.py:113 IND CLOCK 8262
2026-01-29 03:12:25.216 [DEBUG] clck_gen.py:113 IND CLOCK 8364
2026-01-29 03:12:25.694 [DEBUG] clck_gen.py:113 IND CLOCK 8466
2026-01-29 03:12:25.769 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:12:25.772 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 03:12:25.774 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 03:12:25.774 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 03:12:25.774 [INFO] transceiver.py:205 (MS@172.18.28.22:6700) Frequency hopping disabled
2026-01-29 03:12:25.792 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 03:12:25.792 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 03:12:25.792 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 03:12:25.793 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 03:12:25.793 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 03:12:25.793 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 03:12:25.793 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.28.22:6700) Recv POWERON CMD
2026-01-29 03:12:25.793 [INFO] ctrl_if_trx.py:109 (MS@172.18.28.22:6700) Starting transceiver...
2026-01-29 03:12:25.835 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:12:25.841 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.28.22:6700) Recv SETFH cmd
2026-01-29 03:12:25.841 [INFO] transceiver.py:201 (MS@172.18.28.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2026-01-29 03:12:25.842 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 03:12:25.842 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 03:12:26.172 [DEBUG] clck_gen.py:113 IND CLOCK 8568
2026-01-29 03:12:26.651 [DEBUG] clck_gen.py:113 IND CLOCK 8670
2026-01-29 03:12:27.129 [DEBUG] clck_gen.py:113 IND CLOCK 8772
2026-01-29 03:12:27.608 [DEBUG] clck_gen.py:113 IND CLOCK 8874
2026-01-29 03:12:28.086 [DEBUG] clck_gen.py:113 IND CLOCK 8976
2026-01-29 03:12:28.565 [DEBUG] clck_gen.py:113 IND CLOCK 9078
2026-01-29 03:12:28.846 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:12:28.849 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 03:12:28.851 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 03:12:28.851 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 03:12:28.851 [INFO] transceiver.py:205 (MS@172.18.28.22:6700) Frequency hopping disabled
2026-01-29 03:12:28.870 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 03:12:28.870 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 03:12:28.870 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 03:12:28.871 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 03:12:28.871 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 03:12:28.871 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 03:12:28.871 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.28.22:6700) Recv POWERON CMD
2026-01-29 03:12:28.871 [INFO] ctrl_if_trx.py:109 (MS@172.18.28.22:6700) Starting transceiver...
2026-01-29 03:12:28.892 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:12:28.896 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.28.22:6700) Recv SETFH cmd
2026-01-29 03:12:28.896 [INFO] transceiver.py:201 (MS@172.18.28.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2026-01-29 03:12:28.896 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 03:12:28.897 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 03:12:28.954 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:12:28.957 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 03:12:28.959 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 03:12:28.959 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 03:12:28.959 [INFO] transceiver.py:205 (MS@172.18.28.22:6700) Frequency hopping disabled
2026-01-29 03:12:28.979 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 03:12:28.979 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 03:12:28.979 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 03:12:28.980 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 03:12:28.981 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 03:12:28.981 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 03:12:28.981 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.28.22:6700) Recv POWERON CMD
2026-01-29 03:12:28.981 [INFO] ctrl_if_trx.py:109 (MS@172.18.28.22:6700) Starting transceiver...
2026-01-29 03:12:28.982 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:12:28.983 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.28.22:6700) Recv SETFH cmd
2026-01-29 03:12:28.983 [INFO] transceiver.py:201 (MS@172.18.28.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2026-01-29 03:12:28.984 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 03:12:28.984 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 03:12:29.042 [DEBUG] clck_gen.py:113 IND CLOCK 9180
2026-01-29 03:12:29.520 [DEBUG] clck_gen.py:113 IND CLOCK 9282
2026-01-29 03:12:29.999 [DEBUG] clck_gen.py:113 IND CLOCK 9384
2026-01-29 03:12:30.477 [DEBUG] clck_gen.py:113 IND CLOCK 9486
2026-01-29 03:12:30.931 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:12:30.934 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 03:12:30.935 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 03:12:30.935 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 03:12:30.935 [INFO] transceiver.py:205 (MS@172.18.28.22:6700) Frequency hopping disabled
2026-01-29 03:12:30.943 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 03:12:30.943 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:12:30.943 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:12:30.943 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:12:30.943 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 03:12:30.943 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 03:12:30.943 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 03:12:30.943 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 03:12:30.943 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.28.20:5700) Recv POWEROFF cmd
2026-01-29 03:12:30.944 [INFO] ctrl_if_trx.py:117 (BTS@172.18.28.20:5700) Stopping transceiver...
2026-01-29 03:12:30.944 [INFO] transceiver.py:246 Stopping clock generator
2026-01-29 03:12:30.944 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=9589 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:12:30.944 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=9589 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:12:30.944 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=9589 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:12:30.944 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=9589 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:12:30.944 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=9589 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:12:30.944 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=9589 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:12:30.944 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=9589 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:12:35.947 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.28.20:5700) Recv POWEROFF cmd
2026-01-29 03:12:35.947 [INFO] ctrl_if_trx.py:117 (BTS@172.18.28.20:5700) Stopping transceiver...
2026-01-29 03:12:35.949 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 03:12:35.949 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 03:12:35.949 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 03:12:35.950 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 03:12:35.954 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 03:12:35.954 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.28.20:5700) Recv SETFORMAT cmd
2026-01-29 03:12:35.954 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.28.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:12:35.954 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.28.20:5700) Recv SETFORMAT cmd
2026-01-29 03:12:35.954 [INFO] ctrl_if_trx.py:201 (BTS@172.18.28.20:5700) TRXD header version 1 -> 1
2026-01-29 03:12:35.955 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.28.20:5700/1) Recv RXTUNE cmd
2026-01-29 03:12:35.955 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.28.20:5700/1) Recv TXTUNE cmd
2026-01-29 03:12:35.955 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.28.20:5700/1) Recv SETFORMAT cmd
2026-01-29 03:12:35.955 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.28.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:12:35.955 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 03:12:35.955 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.28.20:5700/1) Recv NOMTXPOWER cmd
2026-01-29 03:12:35.955 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.28.20:5700/1) Recv SETFORMAT cmd
2026-01-29 03:12:35.955 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.28.20:5700/1) TRXD header version 1 -> 1
2026-01-29 03:12:35.955 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.28.20:5700/2) Recv RXTUNE cmd
2026-01-29 03:12:35.955 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.28.20:5700/2) Recv TXTUNE cmd
2026-01-29 03:12:35.955 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.28.20:5700/2) Recv SETFORMAT cmd
2026-01-29 03:12:35.955 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.28.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:12:35.956 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 03:12:35.956 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.28.20:5700/2) Recv NOMTXPOWER cmd
2026-01-29 03:12:35.956 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.28.20:5700/2) Recv SETFORMAT cmd
2026-01-29 03:12:35.956 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.28.20:5700/2) TRXD header version 1 -> 1
2026-01-29 03:12:35.956 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.28.20:5700/3) Recv RXTUNE cmd
2026-01-29 03:12:35.956 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.28.20:5700/3) Recv TXTUNE cmd
2026-01-29 03:12:35.956 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.28.20:5700/3) Recv SETFORMAT cmd
2026-01-29 03:12:35.956 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.28.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:12:35.956 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 03:12:35.956 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.28.20:5700/3) Recv NOMTXPOWER cmd
2026-01-29 03:12:35.956 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.28.20:5700/3) Recv SETFORMAT cmd
2026-01-29 03:12:35.956 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.28.20:5700/3) TRXD header version 1 -> 1
2026-01-29 03:12:35.958 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.28.20:5700) Recv RXTUNE cmd
2026-01-29 03:12:35.958 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETTSC
2026-01-29 03:12:35.958 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETTSC
2026-01-29 03:12:35.958 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETTSC
2026-01-29 03:12:35.958 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.28.20:5700) Recv TXTUNE cmd
2026-01-29 03:12:35.958 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETRXGAIN
2026-01-29 03:12:35.958 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETRXGAIN
2026-01-29 03:12:35.958 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETRXGAIN
2026-01-29 03:12:35.958 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETTSC
2026-01-29 03:12:35.958 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:12:35.958 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:12:35.958 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.28.20:5700) Recv NOMTXPOWER cmd
2026-01-29 03:12:35.958 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:12:35.958 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:12:35.958 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:12:35.958 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.28.20:5700) Recv POWERON CMD
2026-01-29 03:12:35.958 [INFO] ctrl_if_trx.py:109 (BTS@172.18.28.20:5700) Starting transceiver...
2026-01-29 03:12:35.958 [INFO] transceiver.py:243 Starting clock generator
2026-01-29 03:12:35.958 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-01-29 03:12:35.958 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:12:35.958 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:12:35.958 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:12:35.958 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETRXGAIN
2026-01-29 03:12:35.958 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:12:35.958 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:12:35.958 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:12:35.958 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:12:35.958 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:12:35.958 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:12:35.958 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:12:35.958 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:12:35.958 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:12:35.958 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:12:35.959 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:12:35.959 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:12:35.959 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:12:35.959 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:12:35.959 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:12:35.959 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:12:35.959 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:12:35.959 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:12:35.959 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:12:35.959 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:12:35.959 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:12:35.959 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:12:35.959 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:12:35.959 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:12:35.963 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-01-29 03:12:36.446 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-01-29 03:12:36.487 [DEBUG] fake_trx.py:278 (BTS@172.18.28.20:5700) Recv FAKE_TOA cmd
2026-01-29 03:12:36.489 [DEBUG] fake_trx.py:297 (BTS@172.18.28.20:5700) Recv FAKE_RSSI cmd
2026-01-29 03:12:36.491 [DEBUG] fake_trx.py:322 (BTS@172.18.28.20:5700) Recv FAKE_CI cmd
2026-01-29 03:12:36.492 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:12:36.515 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 03:12:36.516 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 03:12:36.516 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 03:12:36.519 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 03:12:36.519 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 03:12:36.519 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 03:12:36.519 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.28.22:6700) Recv POWERON CMD
2026-01-29 03:12:36.519 [INFO] ctrl_if_trx.py:109 (MS@172.18.28.22:6700) Starting transceiver...
2026-01-29 03:12:36.543 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:12:36.549 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 03:12:36.549 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 03:12:36.549 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 03:12:36.550 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 03:12:36.604 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:12:36.607 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 03:12:36.608 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 03:12:36.608 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 03:12:36.624 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 03:12:36.624 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 03:12:36.625 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 03:12:36.626 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 03:12:36.626 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 03:12:36.626 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 03:12:36.626 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.28.22:6700) Recv POWERON CMD
2026-01-29 03:12:36.626 [INFO] ctrl_if_trx.py:109 (MS@172.18.28.22:6700) Starting transceiver...
2026-01-29 03:12:36.628 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:12:36.629 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.28.22:6700) Recv SETFH cmd
2026-01-29 03:12:36.629 [INFO] transceiver.py:201 (MS@172.18.28.22:6700) Frequency hopping configured: hsn=5, maio=0, ma_len=4
2026-01-29 03:12:36.629 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 03:12:36.629 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 03:12:36.722 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:12:36.725 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 03:12:36.727 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 03:12:36.727 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 03:12:36.727 [INFO] transceiver.py:205 (MS@172.18.28.22:6700) Frequency hopping disabled
2026-01-29 03:12:36.746 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 03:12:36.746 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 03:12:36.746 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 03:12:36.747 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 03:12:36.747 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 03:12:36.747 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 03:12:36.748 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.28.22:6700) Recv POWERON CMD
2026-01-29 03:12:36.748 [INFO] ctrl_if_trx.py:109 (MS@172.18.28.22:6700) Starting transceiver...
2026-01-29 03:12:36.776 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:12:36.781 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 03:12:36.781 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 03:12:36.781 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 03:12:36.781 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 03:12:36.838 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:12:36.841 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 03:12:36.842 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 03:12:36.842 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 03:12:36.860 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 03:12:36.860 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 03:12:36.860 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 03:12:36.862 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 03:12:36.862 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 03:12:36.862 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 03:12:36.862 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.28.22:6700) Recv POWERON CMD
2026-01-29 03:12:36.862 [INFO] ctrl_if_trx.py:109 (MS@172.18.28.22:6700) Starting transceiver...
2026-01-29 03:12:36.919 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-01-29 03:12:36.921 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:12:36.926 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.28.22:6700) Recv SETFH cmd
2026-01-29 03:12:36.926 [INFO] transceiver.py:201 (MS@172.18.28.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2026-01-29 03:12:36.926 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 03:12:36.926 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 03:12:36.960 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 03:12:36.960 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:12:36.962 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:12:36.965 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:12:37.000 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:12:37.003 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 03:12:37.005 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 03:12:37.005 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 03:12:37.005 [INFO] transceiver.py:205 (MS@172.18.28.22:6700) Frequency hopping disabled
2026-01-29 03:12:37.012 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 03:12:37.012 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:12:37.012 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:12:37.012 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:12:37.013 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 03:12:37.013 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 03:12:37.013 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 03:12:37.013 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 03:12:37.013 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.28.20:5700) Recv POWEROFF cmd
2026-01-29 03:12:37.013 [INFO] ctrl_if_trx.py:117 (BTS@172.18.28.20:5700) Stopping transceiver...
2026-01-29 03:12:37.013 [INFO] transceiver.py:246 Stopping clock generator
2026-01-29 03:12:42.017 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.28.20:5700) Recv POWEROFF cmd
2026-01-29 03:12:42.018 [INFO] ctrl_if_trx.py:117 (BTS@172.18.28.20:5700) Stopping transceiver...
2026-01-29 03:12:42.018 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 03:12:42.018 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 03:12:42.018 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 03:12:42.018 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 03:12:42.025 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 03:12:42.025 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.28.20:5700) Recv SETFORMAT cmd
2026-01-29 03:12:42.026 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.28.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:12:42.026 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.28.20:5700) Recv SETFORMAT cmd
2026-01-29 03:12:42.026 [INFO] ctrl_if_trx.py:201 (BTS@172.18.28.20:5700) TRXD header version 1 -> 1
2026-01-29 03:12:42.029 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.28.20:5700/1) Recv RXTUNE cmd
2026-01-29 03:12:42.029 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.28.20:5700/1) Recv TXTUNE cmd
2026-01-29 03:12:42.029 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.28.20:5700/1) Recv SETFORMAT cmd
2026-01-29 03:12:42.030 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.28.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:12:42.030 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 03:12:42.030 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.28.20:5700/1) Recv NOMTXPOWER cmd
2026-01-29 03:12:42.031 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.28.20:5700/1) Recv SETFORMAT cmd
2026-01-29 03:12:42.031 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.28.20:5700/1) TRXD header version 1 -> 1
2026-01-29 03:12:42.032 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.28.20:5700/2) Recv RXTUNE cmd
2026-01-29 03:12:42.032 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.28.20:5700/2) Recv TXTUNE cmd
2026-01-29 03:12:42.033 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.28.20:5700/2) Recv SETFORMAT cmd
2026-01-29 03:12:42.033 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.28.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:12:42.033 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 03:12:42.034 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.28.20:5700/2) Recv NOMTXPOWER cmd
2026-01-29 03:12:42.034 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.28.20:5700/2) Recv SETFORMAT cmd
2026-01-29 03:12:42.034 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.28.20:5700/2) TRXD header version 1 -> 1
2026-01-29 03:12:42.035 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.28.20:5700/3) Recv RXTUNE cmd
2026-01-29 03:12:42.035 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.28.20:5700/3) Recv TXTUNE cmd
2026-01-29 03:12:42.035 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.28.20:5700/3) Recv SETFORMAT cmd
2026-01-29 03:12:42.035 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.28.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:12:42.035 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 03:12:42.035 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.28.20:5700/3) Recv NOMTXPOWER cmd
2026-01-29 03:12:42.035 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.28.20:5700/3) Recv SETFORMAT cmd
2026-01-29 03:12:42.035 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.28.20:5700/3) TRXD header version 1 -> 1
2026-01-29 03:12:42.038 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.28.20:5700) Recv RXTUNE cmd
2026-01-29 03:12:42.038 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETTSC
2026-01-29 03:12:42.038 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETTSC
2026-01-29 03:12:42.038 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETTSC
2026-01-29 03:12:42.038 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.28.20:5700) Recv TXTUNE cmd
2026-01-29 03:12:42.039 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETRXGAIN
2026-01-29 03:12:42.039 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETRXGAIN
2026-01-29 03:12:42.039 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETRXGAIN
2026-01-29 03:12:42.039 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETTSC
2026-01-29 03:12:42.039 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:12:42.039 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:12:42.039 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:12:42.039 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.28.20:5700) Recv NOMTXPOWER cmd
2026-01-29 03:12:42.039 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:12:42.039 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:12:42.039 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:12:42.039 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.28.20:5700) Recv POWERON CMD
2026-01-29 03:12:42.039 [INFO] ctrl_if_trx.py:109 (BTS@172.18.28.20:5700) Starting transceiver...
2026-01-29 03:12:42.039 [INFO] transceiver.py:243 Starting clock generator
2026-01-29 03:12:42.039 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-01-29 03:12:42.039 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:12:42.039 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:12:42.039 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:12:42.039 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETRXGAIN
2026-01-29 03:12:42.040 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:12:42.040 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:12:42.040 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:12:42.040 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:12:42.040 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:12:42.040 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:12:42.040 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:12:42.040 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:12:42.040 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:12:42.040 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:12:42.040 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:12:42.040 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:12:42.040 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:12:42.040 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:12:42.040 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:12:42.040 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:12:42.040 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:12:42.040 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:12:42.040 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:12:42.040 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:12:42.040 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:12:42.040 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:12:42.040 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:12:42.044 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-01-29 03:12:42.527 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-01-29 03:12:42.563 [DEBUG] fake_trx.py:278 (BTS@172.18.28.20:5700) Recv FAKE_TOA cmd
2026-01-29 03:12:42.564 [DEBUG] fake_trx.py:297 (BTS@172.18.28.20:5700) Recv FAKE_RSSI cmd
2026-01-29 03:12:42.564 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:12:42.565 [DEBUG] fake_trx.py:322 (BTS@172.18.28.20:5700) Recv FAKE_CI cmd
2026-01-29 03:12:42.580 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 03:12:42.580 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 03:12:42.580 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 03:12:42.585 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 03:12:42.585 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 03:12:42.585 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 03:12:42.585 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.28.22:6700) Recv POWERON CMD
2026-01-29 03:12:42.585 [INFO] ctrl_if_trx.py:109 (MS@172.18.28.22:6700) Starting transceiver...
2026-01-29 03:12:42.623 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:12:42.628 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 03:12:42.628 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 03:12:42.629 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 03:12:42.629 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 03:12:42.997 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-01-29 03:12:43.042 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 03:12:43.042 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:12:43.044 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:12:43.047 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:12:43.467 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-01-29 03:12:43.481 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:12:43.483 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 03:12:43.485 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 03:12:43.485 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 03:12:43.502 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 03:12:43.502 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 03:12:43.502 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 03:12:43.503 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 03:12:43.503 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 03:12:43.503 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 03:12:43.503 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.28.22:6700) Recv POWERON CMD
2026-01-29 03:12:43.503 [INFO] ctrl_if_trx.py:109 (MS@172.18.28.22:6700) Starting transceiver...
2026-01-29 03:12:43.507 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:12:43.508 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.28.22:6700) Recv SETFH cmd
2026-01-29 03:12:43.508 [INFO] transceiver.py:201 (MS@172.18.28.22:6700) Frequency hopping configured: hsn=5, maio=0, ma_len=4
2026-01-29 03:12:43.508 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 03:12:43.508 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 03:12:43.943 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-01-29 03:12:44.043 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 03:12:44.043 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:12:44.045 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:12:44.048 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:12:44.210 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:12:44.213 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 03:12:44.214 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 03:12:44.214 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 03:12:44.215 [INFO] transceiver.py:205 (MS@172.18.28.22:6700) Frequency hopping disabled
2026-01-29 03:12:44.232 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 03:12:44.232 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 03:12:44.232 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 03:12:44.234 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 03:12:44.234 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 03:12:44.234 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 03:12:44.234 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.28.22:6700) Recv POWERON CMD
2026-01-29 03:12:44.234 [INFO] ctrl_if_trx.py:109 (MS@172.18.28.22:6700) Starting transceiver...
2026-01-29 03:12:44.272 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:12:44.274 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 03:12:44.274 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 03:12:44.274 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 03:12:44.274 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 03:12:44.381 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:12:44.384 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 03:12:44.385 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 03:12:44.385 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 03:12:44.402 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 03:12:44.402 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 03:12:44.403 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 03:12:44.404 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 03:12:44.404 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 03:12:44.404 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 03:12:44.404 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.28.22:6700) Recv POWERON CMD
2026-01-29 03:12:44.404 [INFO] ctrl_if_trx.py:109 (MS@172.18.28.22:6700) Starting transceiver...
2026-01-29 03:12:44.410 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:12:44.411 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.28.22:6700) Recv SETFH cmd
2026-01-29 03:12:44.411 [INFO] transceiver.py:201 (MS@172.18.28.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2026-01-29 03:12:44.411 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 03:12:44.412 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 03:12:44.418 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-01-29 03:12:44.805 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:12:44.808 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 03:12:44.810 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 03:12:44.810 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 03:12:44.810 [INFO] transceiver.py:205 (MS@172.18.28.22:6700) Frequency hopping disabled
2026-01-29 03:12:44.815 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 03:12:44.815 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:12:44.815 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:12:44.815 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:12:44.815 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 03:12:44.815 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 03:12:44.815 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 03:12:44.815 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 03:12:44.815 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.28.20:5700) Recv POWEROFF cmd
2026-01-29 03:12:44.815 [INFO] ctrl_if_trx.py:117 (BTS@172.18.28.20:5700) Stopping transceiver...
2026-01-29 03:12:44.815 [INFO] transceiver.py:246 Stopping clock generator
2026-01-29 03:12:44.815 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=599 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:12:44.815 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=599 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:12:44.815 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=599 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:12:44.815 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=599 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:12:44.816 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=599 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:12:44.816 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=599 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:12:44.816 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=599 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:12:44.816 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=599 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:12:49.818 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.28.20:5700) Recv POWEROFF cmd
2026-01-29 03:12:49.819 [INFO] ctrl_if_trx.py:117 (BTS@172.18.28.20:5700) Stopping transceiver...
2026-01-29 03:12:49.820 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 03:12:49.821 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 03:12:49.821 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 03:12:49.822 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 03:12:49.827 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 03:12:49.828 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.28.20:5700) Recv SETFORMAT cmd
2026-01-29 03:12:49.828 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.28.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:12:49.829 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.28.20:5700) Recv SETFORMAT cmd
2026-01-29 03:12:49.829 [INFO] ctrl_if_trx.py:201 (BTS@172.18.28.20:5700) TRXD header version 1 -> 1
2026-01-29 03:12:49.832 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.28.20:5700/1) Recv RXTUNE cmd
2026-01-29 03:12:49.832 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.28.20:5700/1) Recv TXTUNE cmd
2026-01-29 03:12:49.833 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.28.20:5700/1) Recv SETFORMAT cmd
2026-01-29 03:12:49.833 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.28.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:12:49.833 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 03:12:49.834 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.28.20:5700/1) Recv NOMTXPOWER cmd
2026-01-29 03:12:49.834 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.28.20:5700/1) Recv SETFORMAT cmd
2026-01-29 03:12:49.834 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.28.20:5700/1) TRXD header version 1 -> 1
2026-01-29 03:12:49.836 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.28.20:5700/2) Recv RXTUNE cmd
2026-01-29 03:12:49.836 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.28.20:5700/2) Recv TXTUNE cmd
2026-01-29 03:12:49.836 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.28.20:5700/2) Recv SETFORMAT cmd
2026-01-29 03:12:49.836 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.28.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:12:49.836 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 03:12:49.836 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.28.20:5700/2) Recv NOMTXPOWER cmd
2026-01-29 03:12:49.836 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.28.20:5700/2) Recv SETFORMAT cmd
2026-01-29 03:12:49.836 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.28.20:5700/2) TRXD header version 1 -> 1
2026-01-29 03:12:49.838 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.28.20:5700/3) Recv RXTUNE cmd
2026-01-29 03:12:49.838 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.28.20:5700/3) Recv TXTUNE cmd
2026-01-29 03:12:49.838 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.28.20:5700/3) Recv SETFORMAT cmd
2026-01-29 03:12:49.838 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.28.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:12:49.838 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 03:12:49.839 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.28.20:5700/3) Recv NOMTXPOWER cmd
2026-01-29 03:12:49.839 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.28.20:5700/3) Recv SETFORMAT cmd
2026-01-29 03:12:49.839 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.28.20:5700/3) TRXD header version 1 -> 1
2026-01-29 03:12:49.841 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.28.20:5700) Recv RXTUNE cmd
2026-01-29 03:12:49.841 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETTSC
2026-01-29 03:12:49.841 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETTSC
2026-01-29 03:12:49.841 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETTSC
2026-01-29 03:12:49.841 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.28.20:5700) Recv TXTUNE cmd
2026-01-29 03:12:49.841 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETRXGAIN
2026-01-29 03:12:49.841 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETRXGAIN
2026-01-29 03:12:49.841 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETRXGAIN
2026-01-29 03:12:49.841 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETTSC
2026-01-29 03:12:49.841 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:12:49.841 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:12:49.841 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.28.20:5700) Recv NOMTXPOWER cmd
2026-01-29 03:12:49.841 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:12:49.841 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:12:49.841 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.28.20:5700) Recv POWERON CMD
2026-01-29 03:12:49.841 [INFO] ctrl_if_trx.py:109 (BTS@172.18.28.20:5700) Starting transceiver...
2026-01-29 03:12:49.841 [INFO] transceiver.py:243 Starting clock generator
2026-01-29 03:12:49.841 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-01-29 03:12:49.842 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:12:49.842 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:12:49.842 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:12:49.842 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETRXGAIN
2026-01-29 03:12:49.842 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:12:49.842 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:12:49.842 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:12:49.842 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:12:49.842 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:12:49.842 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:12:49.842 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:12:49.842 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:12:49.842 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:12:49.842 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:12:49.842 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:12:49.842 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:12:49.842 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:12:49.842 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:12:49.842 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:12:49.842 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:12:49.842 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:12:49.842 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:12:49.842 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:12:49.842 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:12:49.842 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:12:49.842 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:12:49.842 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:12:49.842 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:12:49.842 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:12:49.846 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-01-29 03:12:50.330 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-01-29 03:12:50.362 [DEBUG] fake_trx.py:278 (BTS@172.18.28.20:5700) Recv FAKE_TOA cmd
2026-01-29 03:12:50.364 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:12:50.365 [DEBUG] fake_trx.py:297 (BTS@172.18.28.20:5700) Recv FAKE_RSSI cmd
2026-01-29 03:12:50.367 [DEBUG] fake_trx.py:322 (BTS@172.18.28.20:5700) Recv FAKE_CI cmd
2026-01-29 03:12:50.389 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 03:12:50.389 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 03:12:50.390 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 03:12:50.394 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 03:12:50.395 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 03:12:50.395 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 03:12:50.395 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.28.22:6700) Recv POWERON CMD
2026-01-29 03:12:50.395 [INFO] ctrl_if_trx.py:109 (MS@172.18.28.22:6700) Starting transceiver...
2026-01-29 03:12:50.425 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:12:50.431 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 03:12:50.431 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 03:12:50.431 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 03:12:50.431 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 03:12:50.597 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:12:50.600 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 03:12:50.601 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 03:12:50.602 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 03:12:50.619 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 03:12:50.619 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 03:12:50.619 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 03:12:50.620 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 03:12:50.621 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 03:12:50.621 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 03:12:50.621 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.28.22:6700) Recv POWERON CMD
2026-01-29 03:12:50.621 [INFO] ctrl_if_trx.py:109 (MS@172.18.28.22:6700) Starting transceiver...
2026-01-29 03:12:50.661 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:12:50.667 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.28.22:6700) Recv SETFH cmd
2026-01-29 03:12:50.667 [INFO] transceiver.py:201 (MS@172.18.28.22:6700) Frequency hopping configured: hsn=5, maio=0, ma_len=4
2026-01-29 03:12:50.667 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 03:12:50.667 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 03:12:50.807 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-01-29 03:12:50.845 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:12:50.846 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:12:50.846 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 03:12:50.847 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:12:50.950 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:12:50.953 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 03:12:50.955 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 03:12:50.955 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 03:12:50.955 [INFO] transceiver.py:205 (MS@172.18.28.22:6700) Frequency hopping disabled
2026-01-29 03:12:50.975 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 03:12:50.975 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 03:12:50.975 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 03:12:50.976 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 03:12:50.976 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 03:12:50.976 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 03:12:50.976 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.28.22:6700) Recv POWERON CMD
2026-01-29 03:12:50.976 [INFO] ctrl_if_trx.py:109 (MS@172.18.28.22:6700) Starting transceiver...
2026-01-29 03:12:50.990 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:12:50.993 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 03:12:50.993 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 03:12:50.993 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 03:12:50.993 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 03:12:51.269 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:12:51.271 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 03:12:51.272 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 03:12:51.273 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 03:12:51.284 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-01-29 03:12:51.284 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 03:12:51.285 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 03:12:51.285 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 03:12:51.286 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 03:12:51.286 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 03:12:51.286 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 03:12:51.286 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.28.22:6700) Recv POWERON CMD
2026-01-29 03:12:51.286 [INFO] ctrl_if_trx.py:109 (MS@172.18.28.22:6700) Starting transceiver...
2026-01-29 03:12:51.332 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:12:51.337 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.28.22:6700) Recv SETFH cmd
2026-01-29 03:12:51.337 [INFO] transceiver.py:201 (MS@172.18.28.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2026-01-29 03:12:51.337 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 03:12:51.338 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 03:12:51.759 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-01-29 03:12:51.846 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:12:51.846 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 03:12:51.846 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:12:51.848 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:12:52.147 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:12:52.150 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 03:12:52.151 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 03:12:52.151 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 03:12:52.152 [INFO] transceiver.py:205 (MS@172.18.28.22:6700) Frequency hopping disabled
2026-01-29 03:12:52.161 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 03:12:52.161 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:12:52.161 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:12:52.161 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:12:52.165 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 03:12:52.165 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 03:12:52.165 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 03:12:52.165 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 03:12:52.165 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.28.20:5700) Recv POWEROFF cmd
2026-01-29 03:12:52.165 [INFO] ctrl_if_trx.py:117 (BTS@172.18.28.20:5700) Stopping transceiver...
2026-01-29 03:12:52.166 [INFO] transceiver.py:246 Stopping clock generator
2026-01-29 03:12:52.166 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=497 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:12:52.166 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=497 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:12:52.166 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=497 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:12:52.166 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=497 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:12:52.166 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=497 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:12:52.167 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=497 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:12:52.167 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=497 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:12:52.167 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=498 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:12:52.167 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=498 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:12:52.167 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=498 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:12:52.167 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=498 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:12:52.167 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=498 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:12:52.167 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=498 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:12:52.167 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=498 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:12:52.167 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=498 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:12:57.165 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.28.20:5700) Recv POWEROFF cmd
2026-01-29 03:12:57.165 [INFO] ctrl_if_trx.py:117 (BTS@172.18.28.20:5700) Stopping transceiver...
2026-01-29 03:12:57.167 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 03:12:57.168 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 03:12:57.168 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 03:12:57.168 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 03:12:57.178 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 03:12:57.179 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.28.20:5700) Recv SETFORMAT cmd
2026-01-29 03:12:57.179 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.28.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:12:57.180 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.28.20:5700) Recv SETFORMAT cmd
2026-01-29 03:12:57.180 [INFO] ctrl_if_trx.py:201 (BTS@172.18.28.20:5700) TRXD header version 1 -> 1
2026-01-29 03:12:57.185 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.28.20:5700/1) Recv RXTUNE cmd
2026-01-29 03:12:57.185 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.28.20:5700/1) Recv TXTUNE cmd
2026-01-29 03:12:57.186 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.28.20:5700/1) Recv SETFORMAT cmd
2026-01-29 03:12:57.186 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.28.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:12:57.186 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 03:12:57.187 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.28.20:5700/1) Recv NOMTXPOWER cmd
2026-01-29 03:12:57.187 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.28.20:5700/1) Recv SETFORMAT cmd
2026-01-29 03:12:57.187 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.28.20:5700/1) TRXD header version 1 -> 1
2026-01-29 03:12:57.188 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.28.20:5700/2) Recv RXTUNE cmd
2026-01-29 03:12:57.189 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.28.20:5700/2) Recv TXTUNE cmd
2026-01-29 03:12:57.189 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.28.20:5700/2) Recv SETFORMAT cmd
2026-01-29 03:12:57.189 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.28.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:12:57.189 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 03:12:57.190 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.28.20:5700/2) Recv NOMTXPOWER cmd
2026-01-29 03:12:57.190 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.28.20:5700/2) Recv SETFORMAT cmd
2026-01-29 03:12:57.190 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.28.20:5700/2) TRXD header version 1 -> 1
2026-01-29 03:12:57.192 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.28.20:5700/3) Recv RXTUNE cmd
2026-01-29 03:12:57.192 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.28.20:5700/3) Recv TXTUNE cmd
2026-01-29 03:12:57.192 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.28.20:5700/3) Recv SETFORMAT cmd
2026-01-29 03:12:57.192 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.28.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:12:57.192 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 03:12:57.192 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.28.20:5700/3) Recv NOMTXPOWER cmd
2026-01-29 03:12:57.192 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.28.20:5700/3) Recv SETFORMAT cmd
2026-01-29 03:12:57.192 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.28.20:5700/3) TRXD header version 1 -> 1
2026-01-29 03:12:57.197 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.28.20:5700) Recv RXTUNE cmd
2026-01-29 03:12:57.197 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETTSC
2026-01-29 03:12:57.197 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETTSC
2026-01-29 03:12:57.197 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETTSC
2026-01-29 03:12:57.197 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.28.20:5700) Recv TXTUNE cmd
2026-01-29 03:12:57.197 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETRXGAIN
2026-01-29 03:12:57.197 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETRXGAIN
2026-01-29 03:12:57.197 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETRXGAIN
2026-01-29 03:12:57.197 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETTSC
2026-01-29 03:12:57.197 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:12:57.197 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:12:57.197 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:12:57.197 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.28.20:5700) Recv NOMTXPOWER cmd
2026-01-29 03:12:57.197 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:12:57.197 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:12:57.198 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:12:57.198 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.28.20:5700) Recv POWERON CMD
2026-01-29 03:12:57.198 [INFO] ctrl_if_trx.py:109 (BTS@172.18.28.20:5700) Starting transceiver...
2026-01-29 03:12:57.198 [INFO] transceiver.py:243 Starting clock generator
2026-01-29 03:12:57.198 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-01-29 03:12:57.198 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:12:57.198 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:12:57.198 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:12:57.198 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETRXGAIN
2026-01-29 03:12:57.198 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:12:57.198 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:12:57.198 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:12:57.198 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:12:57.199 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:12:57.199 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:12:57.199 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:12:57.199 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:12:57.199 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:12:57.199 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:12:57.199 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:12:57.199 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:12:57.199 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:12:57.199 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:12:57.199 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:12:57.199 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:12:57.199 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:12:57.199 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:12:57.199 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:12:57.199 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:12:57.199 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:12:57.200 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:12:57.200 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:12:57.203 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-01-29 03:12:57.684 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-01-29 03:12:57.729 [DEBUG] fake_trx.py:278 (BTS@172.18.28.20:5700) Recv FAKE_TOA cmd
2026-01-29 03:12:57.731 [DEBUG] fake_trx.py:297 (BTS@172.18.28.20:5700) Recv FAKE_RSSI cmd
2026-01-29 03:12:57.732 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:12:57.732 [DEBUG] fake_trx.py:322 (BTS@172.18.28.20:5700) Recv FAKE_CI cmd
2026-01-29 03:12:57.745 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 03:12:57.746 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 03:12:57.746 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 03:12:57.749 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 03:12:57.749 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 03:12:57.749 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 03:12:57.749 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.28.22:6700) Recv POWERON CMD
2026-01-29 03:12:57.750 [INFO] ctrl_if_trx.py:109 (MS@172.18.28.22:6700) Starting transceiver...
2026-01-29 03:12:57.780 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:12:57.786 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 03:12:57.786 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 03:12:57.787 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 03:12:57.787 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 03:12:57.951 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:12:57.954 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 03:12:57.955 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 03:12:57.955 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 03:12:57.974 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 03:12:57.974 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 03:12:57.974 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 03:12:57.975 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 03:12:57.975 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 03:12:57.976 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 03:12:57.976 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.28.22:6700) Recv POWERON CMD
2026-01-29 03:12:57.976 [INFO] ctrl_if_trx.py:109 (MS@172.18.28.22:6700) Starting transceiver...
2026-01-29 03:12:58.015 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:12:58.021 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.28.22:6700) Recv SETFH cmd
2026-01-29 03:12:58.021 [INFO] transceiver.py:201 (MS@172.18.28.22:6700) Frequency hopping configured: hsn=5, maio=0, ma_len=4
2026-01-29 03:12:58.021 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 03:12:58.021 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 03:12:58.161 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-01-29 03:12:58.202 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 03:12:58.202 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:12:58.203 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:12:58.208 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:12:58.304 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:12:58.307 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 03:12:58.310 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 03:12:58.310 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 03:12:58.310 [INFO] transceiver.py:205 (MS@172.18.28.22:6700) Frequency hopping disabled
2026-01-29 03:12:58.327 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 03:12:58.327 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 03:12:58.327 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 03:12:58.328 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 03:12:58.328 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 03:12:58.328 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 03:12:58.328 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.28.22:6700) Recv POWERON CMD
2026-01-29 03:12:58.328 [INFO] ctrl_if_trx.py:109 (MS@172.18.28.22:6700) Starting transceiver...
2026-01-29 03:12:58.343 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:12:58.345 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 03:12:58.345 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 03:12:58.345 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 03:12:58.345 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 03:12:58.623 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:12:58.626 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 03:12:58.628 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 03:12:58.628 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 03:12:58.634 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-01-29 03:12:58.648 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 03:12:58.648 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 03:12:58.648 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 03:12:58.650 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 03:12:58.650 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 03:12:58.650 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 03:12:58.650 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.28.22:6700) Recv POWERON CMD
2026-01-29 03:12:58.650 [INFO] ctrl_if_trx.py:109 (MS@172.18.28.22:6700) Starting transceiver...
2026-01-29 03:12:58.679 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:12:58.684 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.28.22:6700) Recv SETFH cmd
2026-01-29 03:12:58.684 [INFO] transceiver.py:201 (MS@172.18.28.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2026-01-29 03:12:58.684 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 03:12:58.685 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 03:12:59.112 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-01-29 03:12:59.203 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 03:12:59.203 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:12:59.204 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:12:59.209 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:12:59.500 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:12:59.503 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 03:12:59.505 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 03:12:59.505 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 03:12:59.506 [INFO] transceiver.py:205 (MS@172.18.28.22:6700) Frequency hopping disabled
2026-01-29 03:12:59.513 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 03:12:59.513 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:12:59.513 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:12:59.513 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:12:59.517 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 03:12:59.517 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 03:12:59.517 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.28.20:5700) Recv POWEROFF cmd
2026-01-29 03:12:59.517 [INFO] ctrl_if_trx.py:117 (BTS@172.18.28.20:5700) Stopping transceiver...
2026-01-29 03:12:59.517 [INFO] transceiver.py:246 Stopping clock generator
2026-01-29 03:12:59.517 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 03:12:59.517 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 03:12:59.517 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=497 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:12:59.517 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=497 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:12:59.517 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=497 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:12:59.517 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=497 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:12:59.517 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=497 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:12:59.517 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=497 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:12:59.517 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=497 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:13:04.519 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.28.20:5700) Recv POWEROFF cmd
2026-01-29 03:13:04.520 [INFO] ctrl_if_trx.py:117 (BTS@172.18.28.20:5700) Stopping transceiver...
2026-01-29 03:13:04.520 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 03:13:04.520 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 03:13:04.520 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 03:13:04.520 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 03:13:04.528 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 03:13:04.529 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.28.20:5700) Recv SETFORMAT cmd
2026-01-29 03:13:04.529 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.28.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:13:04.530 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.28.20:5700) Recv SETFORMAT cmd
2026-01-29 03:13:04.530 [INFO] ctrl_if_trx.py:201 (BTS@172.18.28.20:5700) TRXD header version 1 -> 1
2026-01-29 03:13:04.532 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.28.20:5700/1) Recv RXTUNE cmd
2026-01-29 03:13:04.533 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.28.20:5700/1) Recv TXTUNE cmd
2026-01-29 03:13:04.533 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.28.20:5700/1) Recv SETFORMAT cmd
2026-01-29 03:13:04.533 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.28.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:13:04.534 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 03:13:04.534 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.28.20:5700/1) Recv NOMTXPOWER cmd
2026-01-29 03:13:04.534 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.28.20:5700/1) Recv SETFORMAT cmd
2026-01-29 03:13:04.534 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.28.20:5700/1) TRXD header version 1 -> 1
2026-01-29 03:13:04.536 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.28.20:5700/2) Recv RXTUNE cmd
2026-01-29 03:13:04.536 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.28.20:5700/2) Recv TXTUNE cmd
2026-01-29 03:13:04.536 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.28.20:5700/2) Recv SETFORMAT cmd
2026-01-29 03:13:04.536 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.28.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:13:04.537 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 03:13:04.537 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.28.20:5700/2) Recv NOMTXPOWER cmd
2026-01-29 03:13:04.537 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.28.20:5700/2) Recv SETFORMAT cmd
2026-01-29 03:13:04.537 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.28.20:5700/2) TRXD header version 1 -> 1
2026-01-29 03:13:04.538 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.28.20:5700/3) Recv RXTUNE cmd
2026-01-29 03:13:04.538 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.28.20:5700/3) Recv TXTUNE cmd
2026-01-29 03:13:04.538 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.28.20:5700/3) Recv SETFORMAT cmd
2026-01-29 03:13:04.538 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.28.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:13:04.538 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 03:13:04.539 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.28.20:5700/3) Recv NOMTXPOWER cmd
2026-01-29 03:13:04.539 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.28.20:5700/3) Recv SETFORMAT cmd
2026-01-29 03:13:04.539 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.28.20:5700/3) TRXD header version 1 -> 1
2026-01-29 03:13:04.541 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.28.20:5700) Recv RXTUNE cmd
2026-01-29 03:13:04.541 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETTSC
2026-01-29 03:13:04.541 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETTSC
2026-01-29 03:13:04.541 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETTSC
2026-01-29 03:13:04.541 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.28.20:5700) Recv TXTUNE cmd
2026-01-29 03:13:04.542 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETRXGAIN
2026-01-29 03:13:04.542 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETRXGAIN
2026-01-29 03:13:04.542 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETRXGAIN
2026-01-29 03:13:04.542 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETTSC
2026-01-29 03:13:04.542 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:13:04.542 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:13:04.542 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:13:04.542 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.28.20:5700) Recv NOMTXPOWER cmd
2026-01-29 03:13:04.542 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:13:04.542 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:13:04.542 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.28.20:5700) Recv POWERON CMD
2026-01-29 03:13:04.542 [INFO] ctrl_if_trx.py:109 (BTS@172.18.28.20:5700) Starting transceiver...
2026-01-29 03:13:04.542 [INFO] transceiver.py:243 Starting clock generator
2026-01-29 03:13:04.542 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-01-29 03:13:04.542 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:13:04.542 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:13:04.542 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:13:04.542 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETRXGAIN
2026-01-29 03:13:04.542 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:13:04.542 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:13:04.543 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:13:04.543 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:13:04.543 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:13:04.543 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:13:04.543 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:13:04.543 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:13:04.543 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:13:04.543 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:13:04.543 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:13:04.543 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:13:04.543 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:13:04.543 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:13:04.543 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:13:04.543 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:13:04.543 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:13:04.543 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:13:04.543 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:13:04.543 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:13:04.543 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:13:04.543 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:13:04.543 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:13:04.543 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:13:04.547 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-01-29 03:13:05.027 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-01-29 03:13:05.072 [DEBUG] fake_trx.py:278 (BTS@172.18.28.20:5700) Recv FAKE_TOA cmd
2026-01-29 03:13:05.075 [DEBUG] fake_trx.py:297 (BTS@172.18.28.20:5700) Recv FAKE_RSSI cmd
2026-01-29 03:13:05.076 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:13:05.077 [DEBUG] fake_trx.py:322 (BTS@172.18.28.20:5700) Recv FAKE_CI cmd
2026-01-29 03:13:05.094 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 03:13:05.094 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 03:13:05.094 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 03:13:05.097 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 03:13:05.097 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 03:13:05.097 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 03:13:05.098 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.28.22:6700) Recv POWERON CMD
2026-01-29 03:13:05.098 [INFO] ctrl_if_trx.py:109 (MS@172.18.28.22:6700) Starting transceiver...
2026-01-29 03:13:05.123 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:13:05.127 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 03:13:05.127 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 03:13:05.127 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 03:13:05.127 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 03:13:05.503 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-01-29 03:13:05.545 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 03:13:05.545 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:13:05.546 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:13:05.548 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:13:05.981 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-01-29 03:13:06.459 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-01-29 03:13:06.546 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 03:13:06.546 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:13:06.547 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:13:06.549 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:13:06.937 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-01-29 03:13:06.983 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:13:06.985 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 03:13:06.987 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 03:13:06.987 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 03:13:07.005 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 03:13:07.005 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 03:13:07.005 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 03:13:07.006 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 03:13:07.006 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 03:13:07.006 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 03:13:07.006 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.28.22:6700) Recv POWERON CMD
2026-01-29 03:13:07.006 [INFO] ctrl_if_trx.py:109 (MS@172.18.28.22:6700) Starting transceiver...
2026-01-29 03:13:07.030 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:13:07.034 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.28.22:6700) Recv SETFH cmd
2026-01-29 03:13:07.034 [INFO] transceiver.py:201 (MS@172.18.28.22:6700) Frequency hopping configured: hsn=5, maio=0, ma_len=4
2026-01-29 03:13:07.034 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 03:13:07.034 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 03:13:07.411 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-01-29 03:13:07.547 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 03:13:07.547 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:13:07.547 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:13:07.550 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:13:07.890 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-01-29 03:13:08.367 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-01-29 03:13:08.547 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 03:13:08.548 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:13:08.548 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:13:08.552 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:13:08.845 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-01-29 03:13:09.172 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:13:09.174 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 03:13:09.176 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 03:13:09.176 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 03:13:09.176 [INFO] transceiver.py:205 (MS@172.18.28.22:6700) Frequency hopping disabled
2026-01-29 03:13:09.194 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 03:13:09.194 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 03:13:09.194 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 03:13:09.195 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 03:13:09.195 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 03:13:09.195 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 03:13:09.195 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.28.22:6700) Recv POWERON CMD
2026-01-29 03:13:09.195 [INFO] ctrl_if_trx.py:109 (MS@172.18.28.22:6700) Starting transceiver...
2026-01-29 03:13:09.219 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:13:09.223 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 03:13:09.223 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 03:13:09.223 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 03:13:09.224 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 03:13:09.322 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-01-29 03:13:09.548 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 03:13:09.549 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:13:09.549 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:13:09.552 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:13:09.800 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-01-29 03:13:10.277 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-01-29 03:13:10.756 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-01-29 03:13:10.794 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:13:10.796 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 03:13:10.798 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 03:13:10.798 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 03:13:10.815 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 03:13:10.816 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 03:13:10.816 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 03:13:10.817 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 03:13:10.817 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 03:13:10.817 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 03:13:10.817 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.28.22:6700) Recv POWERON CMD
2026-01-29 03:13:10.817 [INFO] ctrl_if_trx.py:109 (MS@172.18.28.22:6700) Starting transceiver...
2026-01-29 03:13:10.850 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:13:10.855 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.28.22:6700) Recv SETFH cmd
2026-01-29 03:13:10.855 [INFO] transceiver.py:201 (MS@172.18.28.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2026-01-29 03:13:10.856 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 03:13:10.856 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 03:13:11.233 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-01-29 03:13:11.711 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-01-29 03:13:12.190 [DEBUG] clck_gen.py:113 IND CLOCK 1632
2026-01-29 03:13:12.668 [DEBUG] clck_gen.py:113 IND CLOCK 1734
2026-01-29 03:13:13.147 [DEBUG] clck_gen.py:113 IND CLOCK 1836
2026-01-29 03:13:13.625 [DEBUG] clck_gen.py:113 IND CLOCK 1938
2026-01-29 03:13:14.104 [DEBUG] clck_gen.py:113 IND CLOCK 2040
2026-01-29 03:13:14.582 [DEBUG] clck_gen.py:113 IND CLOCK 2142
2026-01-29 03:13:15.061 [DEBUG] clck_gen.py:113 IND CLOCK 2244
2026-01-29 03:13:15.540 [DEBUG] clck_gen.py:113 IND CLOCK 2346
2026-01-29 03:13:16.019 [DEBUG] clck_gen.py:113 IND CLOCK 2448
2026-01-29 03:13:16.497 [DEBUG] clck_gen.py:113 IND CLOCK 2550
2026-01-29 03:13:16.975 [DEBUG] clck_gen.py:113 IND CLOCK 2652
2026-01-29 03:13:17.453 [DEBUG] clck_gen.py:113 IND CLOCK 2754
2026-01-29 03:13:17.931 [DEBUG] clck_gen.py:113 IND CLOCK 2856
2026-01-29 03:13:18.409 [DEBUG] clck_gen.py:113 IND CLOCK 2958
2026-01-29 03:13:18.888 [DEBUG] clck_gen.py:113 IND CLOCK 3060
2026-01-29 03:13:19.367 [DEBUG] clck_gen.py:113 IND CLOCK 3162
2026-01-29 03:13:19.843 [DEBUG] clck_gen.py:113 IND CLOCK 3264
2026-01-29 03:13:20.322 [DEBUG] clck_gen.py:113 IND CLOCK 3366
2026-01-29 03:13:20.800 [DEBUG] clck_gen.py:113 IND CLOCK 3468
2026-01-29 03:13:21.279 [DEBUG] clck_gen.py:113 IND CLOCK 3570
2026-01-29 03:13:21.757 [DEBUG] clck_gen.py:113 IND CLOCK 3672
2026-01-29 03:13:22.235 [DEBUG] clck_gen.py:113 IND CLOCK 3774
2026-01-29 03:13:22.713 [DEBUG] clck_gen.py:113 IND CLOCK 3876
2026-01-29 03:13:23.191 [DEBUG] clck_gen.py:113 IND CLOCK 3978
2026-01-29 03:13:23.669 [DEBUG] clck_gen.py:113 IND CLOCK 4080
2026-01-29 03:13:24.148 [DEBUG] clck_gen.py:113 IND CLOCK 4182
2026-01-29 03:13:24.626 [DEBUG] clck_gen.py:113 IND CLOCK 4284
2026-01-29 03:13:25.105 [DEBUG] clck_gen.py:113 IND CLOCK 4386
2026-01-29 03:13:25.583 [DEBUG] clck_gen.py:113 IND CLOCK 4488
2026-01-29 03:13:26.062 [DEBUG] clck_gen.py:113 IND CLOCK 4590
2026-01-29 03:13:26.541 [DEBUG] clck_gen.py:113 IND CLOCK 4692
2026-01-29 03:13:27.019 [DEBUG] clck_gen.py:113 IND CLOCK 4794
2026-01-29 03:13:27.498 [DEBUG] clck_gen.py:113 IND CLOCK 4896
2026-01-29 03:13:27.976 [DEBUG] clck_gen.py:113 IND CLOCK 4998
2026-01-29 03:13:28.454 [DEBUG] clck_gen.py:113 IND CLOCK 5100
2026-01-29 03:13:28.933 [DEBUG] clck_gen.py:113 IND CLOCK 5202
2026-01-29 03:13:29.412 [DEBUG] clck_gen.py:113 IND CLOCK 5304
2026-01-29 03:13:29.891 [DEBUG] clck_gen.py:113 IND CLOCK 5406
2026-01-29 03:13:30.370 [DEBUG] clck_gen.py:113 IND CLOCK 5508
2026-01-29 03:13:30.820 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 03:13:30.820 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 03:13:30.820 [INFO] transceiver.py:205 (MS@172.18.28.22:6700) Frequency hopping disabled
2026-01-29 03:13:30.822 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 03:13:30.822 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:13:30.822 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:13:30.822 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:13:30.822 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 03:13:30.823 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 03:13:30.823 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 03:13:30.823 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.28.20:5700) Recv POWEROFF cmd
2026-01-29 03:13:30.823 [INFO] ctrl_if_trx.py:117 (BTS@172.18.28.20:5700) Stopping transceiver...
2026-01-29 03:13:30.823 [INFO] transceiver.py:246 Stopping clock generator
2026-01-29 03:13:30.823 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 03:13:30.823 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=5608 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:13:30.823 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=5608 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:13:30.823 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=5608 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:13:30.823 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=5608 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:13:30.823 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=5608 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:13:30.823 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=5608 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:13:30.823 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=5608 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:13:30.823 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=5608 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:13:35.825 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.28.20:5700) Recv POWEROFF cmd
2026-01-29 03:13:35.825 [INFO] ctrl_if_trx.py:117 (BTS@172.18.28.20:5700) Stopping transceiver...
2026-01-29 03:13:35.827 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 03:13:35.828 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 03:13:35.828 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 03:13:35.829 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 03:13:35.832 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 03:13:35.832 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.28.20:5700) Recv SETFORMAT cmd
2026-01-29 03:13:35.832 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.28.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:13:35.832 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.28.20:5700) Recv SETFORMAT cmd
2026-01-29 03:13:35.832 [INFO] ctrl_if_trx.py:201 (BTS@172.18.28.20:5700) TRXD header version 1 -> 1
2026-01-29 03:13:35.834 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.28.20:5700/1) Recv RXTUNE cmd
2026-01-29 03:13:35.834 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.28.20:5700/1) Recv TXTUNE cmd
2026-01-29 03:13:35.834 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.28.20:5700/1) Recv SETFORMAT cmd
2026-01-29 03:13:35.834 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.28.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:13:35.834 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 03:13:35.834 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.28.20:5700/1) Recv NOMTXPOWER cmd
2026-01-29 03:13:35.834 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.28.20:5700/1) Recv SETFORMAT cmd
2026-01-29 03:13:35.834 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.28.20:5700/1) TRXD header version 1 -> 1
2026-01-29 03:13:35.836 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.28.20:5700/2) Recv RXTUNE cmd
2026-01-29 03:13:35.837 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.28.20:5700/2) Recv TXTUNE cmd
2026-01-29 03:13:35.837 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.28.20:5700/2) Recv SETFORMAT cmd
2026-01-29 03:13:35.837 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.28.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:13:35.837 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 03:13:35.837 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.28.20:5700/2) Recv NOMTXPOWER cmd
2026-01-29 03:13:35.837 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.28.20:5700/2) Recv SETFORMAT cmd
2026-01-29 03:13:35.837 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.28.20:5700/2) TRXD header version 1 -> 1
2026-01-29 03:13:35.839 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.28.20:5700/3) Recv RXTUNE cmd
2026-01-29 03:13:35.839 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.28.20:5700/3) Recv TXTUNE cmd
2026-01-29 03:13:35.839 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.28.20:5700/3) Recv SETFORMAT cmd
2026-01-29 03:13:35.839 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.28.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:13:35.839 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 03:13:35.839 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.28.20:5700/3) Recv NOMTXPOWER cmd
2026-01-29 03:13:35.839 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.28.20:5700/3) Recv SETFORMAT cmd
2026-01-29 03:13:35.839 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.28.20:5700/3) TRXD header version 1 -> 1
2026-01-29 03:13:35.842 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.28.20:5700) Recv RXTUNE cmd
2026-01-29 03:13:35.842 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETTSC
2026-01-29 03:13:35.842 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETTSC
2026-01-29 03:13:35.842 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETTSC
2026-01-29 03:13:35.842 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.28.20:5700) Recv TXTUNE cmd
2026-01-29 03:13:35.842 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETRXGAIN
2026-01-29 03:13:35.842 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETRXGAIN
2026-01-29 03:13:35.842 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETRXGAIN
2026-01-29 03:13:35.842 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETTSC
2026-01-29 03:13:35.843 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:13:35.843 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:13:35.843 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:13:35.843 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.28.20:5700) Recv NOMTXPOWER cmd
2026-01-29 03:13:35.843 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:13:35.843 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:13:35.843 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:13:35.843 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.28.20:5700) Recv POWERON CMD
2026-01-29 03:13:35.843 [INFO] ctrl_if_trx.py:109 (BTS@172.18.28.20:5700) Starting transceiver...
2026-01-29 03:13:35.843 [INFO] transceiver.py:243 Starting clock generator
2026-01-29 03:13:35.843 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-01-29 03:13:35.843 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:13:35.843 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:13:35.843 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:13:35.843 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETRXGAIN
2026-01-29 03:13:35.843 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:13:35.843 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:13:35.843 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:13:35.843 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:13:35.844 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:13:35.844 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:13:35.844 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:13:35.844 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:13:35.844 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:13:35.844 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:13:35.844 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:13:35.844 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:13:35.844 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:13:35.844 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:13:35.844 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:13:35.844 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:13:35.844 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:13:35.844 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:13:35.844 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:13:35.844 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:13:35.844 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:13:35.844 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:13:35.844 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:13:35.848 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-01-29 03:13:36.328 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-01-29 03:13:36.371 [DEBUG] fake_trx.py:278 (BTS@172.18.28.20:5700) Recv FAKE_TOA cmd
2026-01-29 03:13:36.373 [DEBUG] fake_trx.py:297 (BTS@172.18.28.20:5700) Recv FAKE_RSSI cmd
2026-01-29 03:13:36.374 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:13:36.375 [DEBUG] fake_trx.py:322 (BTS@172.18.28.20:5700) Recv FAKE_CI cmd
2026-01-29 03:13:36.393 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 03:13:36.393 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 03:13:36.393 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 03:13:36.397 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 03:13:36.398 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 03:13:36.398 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 03:13:36.398 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.28.22:6700) Recv POWERON CMD
2026-01-29 03:13:36.398 [INFO] ctrl_if_trx.py:109 (MS@172.18.28.22:6700) Starting transceiver...
2026-01-29 03:13:36.425 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:13:36.429 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 03:13:36.430 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 03:13:36.430 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 03:13:36.430 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 03:13:36.806 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-01-29 03:13:36.847 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:13:36.847 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 03:13:36.848 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:13:36.851 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:13:37.284 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-01-29 03:13:37.761 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-01-29 03:13:37.848 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 03:13:37.848 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:13:37.849 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:13:37.852 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:13:38.239 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-01-29 03:13:38.284 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:13:38.286 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 03:13:38.288 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 03:13:38.288 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 03:13:38.304 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 03:13:38.304 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 03:13:38.304 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 03:13:38.305 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 03:13:38.305 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 03:13:38.305 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 03:13:38.305 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.28.22:6700) Recv POWERON CMD
2026-01-29 03:13:38.305 [INFO] ctrl_if_trx.py:109 (MS@172.18.28.22:6700) Starting transceiver...
2026-01-29 03:13:38.332 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:13:38.335 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.28.22:6700) Recv SETFH cmd
2026-01-29 03:13:38.335 [INFO] transceiver.py:201 (MS@172.18.28.22:6700) Frequency hopping configured: hsn=5, maio=0, ma_len=4
2026-01-29 03:13:38.336 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 03:13:38.336 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 03:13:38.716 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-01-29 03:13:38.849 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 03:13:38.849 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:13:38.849 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:13:38.853 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:13:39.195 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-01-29 03:13:39.671 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-01-29 03:13:39.850 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:13:39.850 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 03:13:39.850 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:13:39.854 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:13:40.141 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-01-29 03:13:40.465 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:13:40.467 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 03:13:40.469 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 03:13:40.469 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 03:13:40.469 [INFO] transceiver.py:205 (MS@172.18.28.22:6700) Frequency hopping disabled
2026-01-29 03:13:40.488 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 03:13:40.488 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 03:13:40.488 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 03:13:40.489 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 03:13:40.489 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 03:13:40.489 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 03:13:40.489 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.28.22:6700) Recv POWERON CMD
2026-01-29 03:13:40.489 [INFO] ctrl_if_trx.py:109 (MS@172.18.28.22:6700) Starting transceiver...
2026-01-29 03:13:40.512 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:13:40.517 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 03:13:40.517 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 03:13:40.517 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 03:13:40.518 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 03:13:40.610 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-01-29 03:13:40.851 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 03:13:40.851 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:13:40.852 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:13:40.856 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:13:41.089 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-01-29 03:13:41.566 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-01-29 03:13:42.043 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-01-29 03:13:42.082 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:13:42.085 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 03:13:42.087 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 03:13:42.087 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 03:13:42.106 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 03:13:42.106 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 03:13:42.106 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 03:13:42.107 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 03:13:42.107 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 03:13:42.107 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 03:13:42.107 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.28.22:6700) Recv POWERON CMD
2026-01-29 03:13:42.107 [INFO] ctrl_if_trx.py:109 (MS@172.18.28.22:6700) Starting transceiver...
2026-01-29 03:13:42.139 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:13:42.144 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.28.22:6700) Recv SETFH cmd
2026-01-29 03:13:42.144 [INFO] transceiver.py:201 (MS@172.18.28.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2026-01-29 03:13:42.144 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 03:13:42.145 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 03:13:42.520 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-01-29 03:13:42.998 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-01-29 03:13:43.477 [DEBUG] clck_gen.py:113 IND CLOCK 1632
2026-01-29 03:13:43.956 [DEBUG] clck_gen.py:113 IND CLOCK 1734
2026-01-29 03:13:44.435 [DEBUG] clck_gen.py:113 IND CLOCK 1836
2026-01-29 03:13:44.913 [DEBUG] clck_gen.py:113 IND CLOCK 1938
2026-01-29 03:13:45.392 [DEBUG] clck_gen.py:113 IND CLOCK 2040
2026-01-29 03:13:45.871 [DEBUG] clck_gen.py:113 IND CLOCK 2142
2026-01-29 03:13:46.350 [DEBUG] clck_gen.py:113 IND CLOCK 2244
2026-01-29 03:13:46.828 [DEBUG] clck_gen.py:113 IND CLOCK 2346
2026-01-29 03:13:47.301 [DEBUG] clck_gen.py:113 IND CLOCK 2448
2026-01-29 03:13:47.778 [DEBUG] clck_gen.py:113 IND CLOCK 2550
2026-01-29 03:13:48.257 [DEBUG] clck_gen.py:113 IND CLOCK 2652
2026-01-29 03:13:48.735 [DEBUG] clck_gen.py:113 IND CLOCK 2754
2026-01-29 03:13:49.214 [DEBUG] clck_gen.py:113 IND CLOCK 2856
2026-01-29 03:13:49.692 [DEBUG] clck_gen.py:113 IND CLOCK 2958
2026-01-29 03:13:50.170 [DEBUG] clck_gen.py:113 IND CLOCK 3060
2026-01-29 03:13:50.649 [DEBUG] clck_gen.py:113 IND CLOCK 3162
2026-01-29 03:13:51.127 [DEBUG] clck_gen.py:113 IND CLOCK 3264
2026-01-29 03:13:51.596 [DEBUG] clck_gen.py:113 IND CLOCK 3366
2026-01-29 03:13:52.074 [DEBUG] clck_gen.py:113 IND CLOCK 3468
2026-01-29 03:13:52.552 [DEBUG] clck_gen.py:113 IND CLOCK 3570
2026-01-29 03:13:53.030 [DEBUG] clck_gen.py:113 IND CLOCK 3672
2026-01-29 03:13:53.508 [DEBUG] clck_gen.py:113 IND CLOCK 3774
2026-01-29 03:13:53.987 [DEBUG] clck_gen.py:113 IND CLOCK 3876
2026-01-29 03:13:54.465 [DEBUG] clck_gen.py:113 IND CLOCK 3978
2026-01-29 03:13:54.944 [DEBUG] clck_gen.py:113 IND CLOCK 4080
2026-01-29 03:13:55.423 [DEBUG] clck_gen.py:113 IND CLOCK 4182
2026-01-29 03:13:55.902 [DEBUG] clck_gen.py:113 IND CLOCK 4284
2026-01-29 03:13:56.381 [DEBUG] clck_gen.py:113 IND CLOCK 4386
2026-01-29 03:13:56.860 [DEBUG] clck_gen.py:113 IND CLOCK 4488
2026-01-29 03:13:57.335 [DEBUG] clck_gen.py:113 IND CLOCK 4590
2026-01-29 03:13:57.814 [DEBUG] clck_gen.py:113 IND CLOCK 4692
2026-01-29 03:13:58.293 [DEBUG] clck_gen.py:113 IND CLOCK 4794
2026-01-29 03:13:58.771 [DEBUG] clck_gen.py:113 IND CLOCK 4896
2026-01-29 03:13:59.250 [DEBUG] clck_gen.py:113 IND CLOCK 4998
2026-01-29 03:13:59.728 [DEBUG] clck_gen.py:113 IND CLOCK 5100
2026-01-29 03:14:00.206 [DEBUG] clck_gen.py:113 IND CLOCK 5202
2026-01-29 03:14:00.685 [DEBUG] clck_gen.py:113 IND CLOCK 5304
2026-01-29 03:14:01.164 [DEBUG] clck_gen.py:113 IND CLOCK 5406
2026-01-29 03:14:01.642 [DEBUG] clck_gen.py:113 IND CLOCK 5508
2026-01-29 03:14:02.113 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 03:14:02.113 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:14:02.113 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:14:02.113 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:14:02.114 [DEBUG] clck_gen.py:113 IND CLOCK 5610
2026-01-29 03:14:02.115 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 03:14:02.115 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 03:14:02.116 [INFO] transceiver.py:205 (MS@172.18.28.22:6700) Frequency hopping disabled
2026-01-29 03:14:02.116 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 03:14:02.117 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 03:14:02.117 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 03:14:02.117 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 03:14:02.117 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.28.20:5700) Recv POWEROFF cmd
2026-01-29 03:14:02.117 [INFO] ctrl_if_trx.py:117 (BTS@172.18.28.20:5700) Stopping transceiver...
2026-01-29 03:14:02.117 [INFO] transceiver.py:246 Stopping clock generator
2026-01-29 03:14:02.118 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=5612 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:14:02.118 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=5612 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:14:02.118 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=5612 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:14:02.118 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=5612 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:14:02.118 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=5612 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:14:02.118 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=5612 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:14:02.118 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=5612 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:14:02.118 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=5613 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:14:02.118 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=5613 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:14:02.118 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=5613 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:14:02.119 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=5613 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:14:02.119 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=5613 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:14:02.119 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=5613 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:14:07.115 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.28.20:5700) Recv POWEROFF cmd
2026-01-29 03:14:07.115 [INFO] ctrl_if_trx.py:117 (BTS@172.18.28.20:5700) Stopping transceiver...
2026-01-29 03:14:07.115 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 03:14:07.115 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 03:14:07.116 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 03:14:07.116 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 03:14:07.119 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 03:14:07.120 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.28.20:5700) Recv SETFORMAT cmd
2026-01-29 03:14:07.120 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.28.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:14:07.120 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.28.20:5700) Recv SETFORMAT cmd
2026-01-29 03:14:07.120 [INFO] ctrl_if_trx.py:201 (BTS@172.18.28.20:5700) TRXD header version 1 -> 1
2026-01-29 03:14:07.120 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.28.20:5700/1) Recv RXTUNE cmd
2026-01-29 03:14:07.120 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.28.20:5700/1) Recv TXTUNE cmd
2026-01-29 03:14:07.120 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.28.20:5700/1) Recv SETFORMAT cmd
2026-01-29 03:14:07.120 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.28.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:14:07.120 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 03:14:07.120 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.28.20:5700/1) Recv NOMTXPOWER cmd
2026-01-29 03:14:07.121 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.28.20:5700/1) Recv SETFORMAT cmd
2026-01-29 03:14:07.121 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.28.20:5700/1) TRXD header version 1 -> 1
2026-01-29 03:14:07.121 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.28.20:5700/2) Recv RXTUNE cmd
2026-01-29 03:14:07.121 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.28.20:5700/2) Recv TXTUNE cmd
2026-01-29 03:14:07.121 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.28.20:5700/2) Recv SETFORMAT cmd
2026-01-29 03:14:07.121 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.28.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:14:07.121 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 03:14:07.121 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.28.20:5700/2) Recv NOMTXPOWER cmd
2026-01-29 03:14:07.121 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.28.20:5700/2) Recv SETFORMAT cmd
2026-01-29 03:14:07.121 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.28.20:5700/2) TRXD header version 1 -> 1
2026-01-29 03:14:07.122 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.28.20:5700/3) Recv RXTUNE cmd
2026-01-29 03:14:07.122 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.28.20:5700/3) Recv TXTUNE cmd
2026-01-29 03:14:07.122 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.28.20:5700/3) Recv SETFORMAT cmd
2026-01-29 03:14:07.122 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.28.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:14:07.122 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 03:14:07.122 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.28.20:5700/3) Recv NOMTXPOWER cmd
2026-01-29 03:14:07.122 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.28.20:5700/3) Recv SETFORMAT cmd
2026-01-29 03:14:07.122 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.28.20:5700/3) TRXD header version 1 -> 1
2026-01-29 03:14:07.124 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.28.20:5700) Recv RXTUNE cmd
2026-01-29 03:14:07.124 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETTSC
2026-01-29 03:14:07.124 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETTSC
2026-01-29 03:14:07.124 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETTSC
2026-01-29 03:14:07.124 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.28.20:5700) Recv TXTUNE cmd
2026-01-29 03:14:07.124 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETRXGAIN
2026-01-29 03:14:07.124 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETRXGAIN
2026-01-29 03:14:07.124 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETRXGAIN
2026-01-29 03:14:07.124 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETTSC
2026-01-29 03:14:07.124 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:14:07.124 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:14:07.124 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.28.20:5700) Recv NOMTXPOWER cmd
2026-01-29 03:14:07.124 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:14:07.124 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:14:07.124 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:14:07.124 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.28.20:5700) Recv POWERON CMD
2026-01-29 03:14:07.124 [INFO] ctrl_if_trx.py:109 (BTS@172.18.28.20:5700) Starting transceiver...
2026-01-29 03:14:07.124 [INFO] transceiver.py:243 Starting clock generator
2026-01-29 03:14:07.124 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-01-29 03:14:07.124 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:14:07.124 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:14:07.124 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:14:07.124 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETRXGAIN
2026-01-29 03:14:07.124 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:14:07.124 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:14:07.124 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:14:07.124 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:14:07.124 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:14:07.124 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:14:07.124 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:14:07.124 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:14:07.125 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:14:07.125 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:14:07.125 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:14:07.125 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:14:07.125 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:14:07.125 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:14:07.125 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:14:07.125 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:14:07.125 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:14:07.125 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:14:07.125 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:14:07.125 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:14:07.125 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:14:07.125 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:14:07.125 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:14:07.125 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:14:07.129 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-01-29 03:14:07.599 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-01-29 03:14:07.643 [DEBUG] fake_trx.py:278 (BTS@172.18.28.20:5700) Recv FAKE_TOA cmd
2026-01-29 03:14:07.644 [DEBUG] fake_trx.py:297 (BTS@172.18.28.20:5700) Recv FAKE_RSSI cmd
2026-01-29 03:14:07.644 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:14:07.644 [DEBUG] fake_trx.py:322 (BTS@172.18.28.20:5700) Recv FAKE_CI cmd
2026-01-29 03:14:07.650 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 03:14:07.650 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 03:14:07.650 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 03:14:07.651 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 03:14:07.651 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 03:14:07.652 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 03:14:07.652 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.28.22:6700) Recv POWERON CMD
2026-01-29 03:14:07.652 [INFO] ctrl_if_trx.py:109 (MS@172.18.28.22:6700) Starting transceiver...
2026-01-29 03:14:07.691 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:14:07.693 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 03:14:07.693 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 03:14:07.693 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 03:14:07.693 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 03:14:07.855 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:14:07.856 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 03:14:07.857 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 03:14:07.857 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 03:14:07.866 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 03:14:07.867 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 03:14:07.867 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 03:14:07.869 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 03:14:07.869 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 03:14:07.869 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 03:14:07.869 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.28.22:6700) Recv POWERON CMD
2026-01-29 03:14:07.869 [INFO] ctrl_if_trx.py:109 (MS@172.18.28.22:6700) Starting transceiver...
2026-01-29 03:14:07.879 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:14:07.881 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 03:14:07.881 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 03:14:07.881 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 03:14:07.881 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 03:14:08.069 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-01-29 03:14:08.126 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 03:14:08.126 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:14:08.127 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:14:08.132 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:14:08.538 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-01-29 03:14:09.009 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-01-29 03:14:09.127 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:14:09.127 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 03:14:09.127 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:14:09.132 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:14:09.478 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-01-29 03:14:09.949 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-01-29 03:14:09.991 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:14:09.992 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 03:14:09.992 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 03:14:09.992 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 03:14:09.998 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 03:14:09.998 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 03:14:09.999 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 03:14:09.999 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 03:14:10.000 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 03:14:10.000 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 03:14:10.000 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.28.22:6700) Recv POWERON CMD
2026-01-29 03:14:10.000 [INFO] ctrl_if_trx.py:109 (MS@172.18.28.22:6700) Starting transceiver...
2026-01-29 03:14:10.038 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:14:10.039 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 03:14:10.039 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 03:14:10.039 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 03:14:10.040 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 03:14:10.128 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 03:14:10.128 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:14:10.128 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:14:10.132 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:14:10.208 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:14:10.209 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 03:14:10.209 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 03:14:10.209 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 03:14:10.215 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 03:14:10.215 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 03:14:10.216 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 03:14:10.216 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 03:14:10.217 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 03:14:10.217 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 03:14:10.217 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.28.22:6700) Recv POWERON CMD
2026-01-29 03:14:10.217 [INFO] ctrl_if_trx.py:109 (MS@172.18.28.22:6700) Starting transceiver...
2026-01-29 03:14:10.228 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:14:10.229 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 03:14:10.229 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 03:14:10.229 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 03:14:10.229 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 03:14:10.416 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-01-29 03:14:10.888 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-01-29 03:14:11.128 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 03:14:11.128 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:14:11.128 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:14:11.133 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:14:11.360 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-01-29 03:14:11.827 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-01-29 03:14:12.129 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:14:12.129 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 03:14:12.129 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:14:12.133 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:14:12.295 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-01-29 03:14:12.382 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:14:12.383 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 03:14:12.383 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 03:14:12.383 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 03:14:12.390 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 03:14:12.390 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 03:14:12.390 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 03:14:12.391 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 03:14:12.391 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 03:14:12.391 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 03:14:12.391 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.28.22:6700) Recv POWERON CMD
2026-01-29 03:14:12.391 [INFO] ctrl_if_trx.py:109 (MS@172.18.28.22:6700) Starting transceiver...
2026-01-29 03:14:12.430 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:14:12.431 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.28.22:6700) Recv SETFH cmd
2026-01-29 03:14:12.431 [INFO] transceiver.py:201 (MS@172.18.28.22:6700) Frequency hopping configured: hsn=5, maio=0, ma_len=4
2026-01-29 03:14:12.431 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 03:14:12.431 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 03:14:12.701 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:14:12.701 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 03:14:12.702 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 03:14:12.702 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 03:14:12.702 [INFO] transceiver.py:205 (MS@172.18.28.22:6700) Frequency hopping disabled
2026-01-29 03:14:12.709 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 03:14:12.709 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 03:14:12.709 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 03:14:12.710 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 03:14:12.710 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 03:14:12.710 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 03:14:12.710 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.28.22:6700) Recv POWERON CMD
2026-01-29 03:14:12.710 [INFO] ctrl_if_trx.py:109 (MS@172.18.28.22:6700) Starting transceiver...
2026-01-29 03:14:12.762 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:14:12.762 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-01-29 03:14:12.763 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.28.22:6700) Recv SETFH cmd
2026-01-29 03:14:12.763 [INFO] transceiver.py:201 (MS@172.18.28.22:6700) Frequency hopping configured: hsn=5, maio=0, ma_len=4
2026-01-29 03:14:12.763 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 03:14:12.763 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 03:14:13.231 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-01-29 03:14:13.699 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-01-29 03:14:14.168 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-01-29 03:14:14.638 [DEBUG] clck_gen.py:113 IND CLOCK 1632
2026-01-29 03:14:15.009 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:14:15.010 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 03:14:15.010 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 03:14:15.010 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 03:14:15.010 [INFO] transceiver.py:205 (MS@172.18.28.22:6700) Frequency hopping disabled
2026-01-29 03:14:15.017 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 03:14:15.017 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 03:14:15.017 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 03:14:15.018 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 03:14:15.019 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 03:14:15.019 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 03:14:15.019 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.28.22:6700) Recv POWERON CMD
2026-01-29 03:14:15.019 [INFO] ctrl_if_trx.py:109 (MS@172.18.28.22:6700) Starting transceiver...
2026-01-29 03:14:15.051 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:14:15.052 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.28.22:6700) Recv SETFH cmd
2026-01-29 03:14:15.052 [INFO] transceiver.py:201 (MS@172.18.28.22:6700) Frequency hopping configured: hsn=5, maio=0, ma_len=4
2026-01-29 03:14:15.052 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 03:14:15.052 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 03:14:15.107 [DEBUG] clck_gen.py:113 IND CLOCK 1734
2026-01-29 03:14:15.285 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:14:15.286 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 03:14:15.287 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 03:14:15.287 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 03:14:15.287 [INFO] transceiver.py:205 (MS@172.18.28.22:6700) Frequency hopping disabled
2026-01-29 03:14:15.293 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 03:14:15.293 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 03:14:15.293 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 03:14:15.294 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 03:14:15.294 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 03:14:15.294 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 03:14:15.294 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.28.22:6700) Recv POWERON CMD
2026-01-29 03:14:15.294 [INFO] ctrl_if_trx.py:109 (MS@172.18.28.22:6700) Starting transceiver...
2026-01-29 03:14:15.337 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:14:15.338 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.28.22:6700) Recv SETFH cmd
2026-01-29 03:14:15.338 [INFO] transceiver.py:201 (MS@172.18.28.22:6700) Frequency hopping configured: hsn=5, maio=0, ma_len=4
2026-01-29 03:14:15.338 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 03:14:15.339 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 03:14:15.575 [DEBUG] clck_gen.py:113 IND CLOCK 1836
2026-01-29 03:14:16.043 [DEBUG] clck_gen.py:113 IND CLOCK 1938
2026-01-29 03:14:16.514 [DEBUG] clck_gen.py:113 IND CLOCK 2040
2026-01-29 03:14:16.983 [DEBUG] clck_gen.py:113 IND CLOCK 2142
2026-01-29 03:14:17.404 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:14:17.405 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 03:14:17.405 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 03:14:17.405 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 03:14:17.405 [INFO] transceiver.py:205 (MS@172.18.28.22:6700) Frequency hopping disabled
2026-01-29 03:14:17.412 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 03:14:17.412 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 03:14:17.412 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 03:14:17.413 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 03:14:17.413 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 03:14:17.413 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 03:14:17.413 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.28.22:6700) Recv POWERON CMD
2026-01-29 03:14:17.413 [INFO] ctrl_if_trx.py:109 (MS@172.18.28.22:6700) Starting transceiver...
2026-01-29 03:14:17.451 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:14:17.452 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 03:14:17.452 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 03:14:17.452 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 03:14:17.452 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 03:14:17.453 [DEBUG] clck_gen.py:113 IND CLOCK 2244
2026-01-29 03:14:17.923 [DEBUG] clck_gen.py:113 IND CLOCK 2346
2026-01-29 03:14:18.076 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:14:18.079 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 03:14:18.081 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 03:14:18.081 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 03:14:18.095 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 03:14:18.095 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 03:14:18.095 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 03:14:18.096 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 03:14:18.096 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 03:14:18.096 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 03:14:18.096 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.28.22:6700) Recv POWERON CMD
2026-01-29 03:14:18.096 [INFO] ctrl_if_trx.py:109 (MS@172.18.28.22:6700) Starting transceiver...
2026-01-29 03:14:18.101 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:14:18.102 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 03:14:18.102 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 03:14:18.102 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 03:14:18.102 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 03:14:18.393 [DEBUG] clck_gen.py:113 IND CLOCK 2448
2026-01-29 03:14:18.868 [DEBUG] clck_gen.py:113 IND CLOCK 2550
2026-01-29 03:14:19.345 [DEBUG] clck_gen.py:113 IND CLOCK 2652
2026-01-29 03:14:19.784 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:14:19.786 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 03:14:19.788 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 03:14:19.788 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 03:14:19.806 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 03:14:19.806 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 03:14:19.806 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 03:14:19.808 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 03:14:19.808 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 03:14:19.808 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 03:14:19.808 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.28.22:6700) Recv POWERON CMD
2026-01-29 03:14:19.808 [INFO] ctrl_if_trx.py:109 (MS@172.18.28.22:6700) Starting transceiver...
2026-01-29 03:14:19.813 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:14:19.814 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 03:14:19.814 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 03:14:19.814 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 03:14:19.814 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 03:14:19.822 [DEBUG] clck_gen.py:113 IND CLOCK 2754
2026-01-29 03:14:20.299 [DEBUG] clck_gen.py:113 IND CLOCK 2856
2026-01-29 03:14:20.455 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:14:20.457 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 03:14:20.459 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 03:14:20.459 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 03:14:20.479 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 03:14:20.479 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 03:14:20.479 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 03:14:20.480 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 03:14:20.480 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 03:14:20.480 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 03:14:20.480 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.28.22:6700) Recv POWERON CMD
2026-01-29 03:14:20.481 [INFO] ctrl_if_trx.py:109 (MS@172.18.28.22:6700) Starting transceiver...
2026-01-29 03:14:20.538 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:14:20.543 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 03:14:20.543 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 03:14:20.543 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 03:14:20.543 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 03:14:20.777 [DEBUG] clck_gen.py:113 IND CLOCK 2958
2026-01-29 03:14:21.254 [DEBUG] clck_gen.py:113 IND CLOCK 3060
2026-01-29 03:14:21.732 [DEBUG] clck_gen.py:113 IND CLOCK 3162
2026-01-29 03:14:22.170 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:14:22.173 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 03:14:22.174 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 03:14:22.174 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 03:14:22.192 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 03:14:22.192 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 03:14:22.192 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 03:14:22.193 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 03:14:22.193 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 03:14:22.193 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 03:14:22.193 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.28.22:6700) Recv POWERON CMD
2026-01-29 03:14:22.193 [INFO] ctrl_if_trx.py:109 (MS@172.18.28.22:6700) Starting transceiver...
2026-01-29 03:14:22.200 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:14:22.201 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.28.22:6700) Recv SETFH cmd
2026-01-29 03:14:22.201 [INFO] transceiver.py:201 (MS@172.18.28.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2026-01-29 03:14:22.201 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 03:14:22.201 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 03:14:22.210 [DEBUG] clck_gen.py:113 IND CLOCK 3264
2026-01-29 03:14:22.679 [DEBUG] clck_gen.py:113 IND CLOCK 3366
2026-01-29 03:14:23.150 [DEBUG] clck_gen.py:113 IND CLOCK 3468
2026-01-29 03:14:23.465 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:14:23.468 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 03:14:23.469 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 03:14:23.469 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 03:14:23.470 [INFO] transceiver.py:205 (MS@172.18.28.22:6700) Frequency hopping disabled
2026-01-29 03:14:23.487 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 03:14:23.487 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 03:14:23.487 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 03:14:23.489 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 03:14:23.489 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 03:14:23.489 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 03:14:23.489 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.28.22:6700) Recv POWERON CMD
2026-01-29 03:14:23.489 [INFO] ctrl_if_trx.py:109 (MS@172.18.28.22:6700) Starting transceiver...
2026-01-29 03:14:23.523 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:14:23.528 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.28.22:6700) Recv SETFH cmd
2026-01-29 03:14:23.528 [INFO] transceiver.py:201 (MS@172.18.28.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2026-01-29 03:14:23.528 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 03:14:23.528 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 03:14:23.624 [DEBUG] clck_gen.py:113 IND CLOCK 3570
2026-01-29 03:14:24.100 [DEBUG] clck_gen.py:113 IND CLOCK 3672
2026-01-29 03:14:24.578 [DEBUG] clck_gen.py:113 IND CLOCK 3774
2026-01-29 03:14:25.056 [DEBUG] clck_gen.py:113 IND CLOCK 3876
2026-01-29 03:14:25.535 [DEBUG] clck_gen.py:113 IND CLOCK 3978
2026-01-29 03:14:26.011 [DEBUG] clck_gen.py:113 IND CLOCK 4080
2026-01-29 03:14:26.480 [DEBUG] clck_gen.py:113 IND CLOCK 4182
2026-01-29 03:14:26.949 [DEBUG] clck_gen.py:113 IND CLOCK 4284
2026-01-29 03:14:27.420 [DEBUG] clck_gen.py:113 IND CLOCK 4386
2026-01-29 03:14:27.896 [DEBUG] clck_gen.py:113 IND CLOCK 4488
2026-01-29 03:14:28.367 [DEBUG] clck_gen.py:113 IND CLOCK 4590
2026-01-29 03:14:28.840 [DEBUG] clck_gen.py:113 IND CLOCK 4692
2026-01-29 03:14:29.309 [DEBUG] clck_gen.py:113 IND CLOCK 4794
2026-01-29 03:14:29.783 [DEBUG] clck_gen.py:113 IND CLOCK 4896
2026-01-29 03:14:30.253 [DEBUG] clck_gen.py:113 IND CLOCK 4998
2026-01-29 03:14:30.721 [DEBUG] clck_gen.py:113 IND CLOCK 5100
2026-01-29 03:14:31.190 [DEBUG] clck_gen.py:113 IND CLOCK 5202
2026-01-29 03:14:31.658 [DEBUG] clck_gen.py:113 IND CLOCK 5304
2026-01-29 03:14:32.127 [DEBUG] clck_gen.py:113 IND CLOCK 5406
2026-01-29 03:14:32.595 [DEBUG] clck_gen.py:113 IND CLOCK 5508
2026-01-29 03:14:33.064 [DEBUG] clck_gen.py:113 IND CLOCK 5610
2026-01-29 03:14:33.534 [DEBUG] clck_gen.py:113 IND CLOCK 5712
2026-01-29 03:14:34.004 [DEBUG] clck_gen.py:113 IND CLOCK 5814
2026-01-29 03:14:34.476 [DEBUG] clck_gen.py:113 IND CLOCK 5916
2026-01-29 03:14:34.944 [DEBUG] clck_gen.py:113 IND CLOCK 6018
2026-01-29 03:14:35.413 [DEBUG] clck_gen.py:113 IND CLOCK 6120
2026-01-29 03:14:35.881 [DEBUG] clck_gen.py:113 IND CLOCK 6222
2026-01-29 03:14:36.349 [DEBUG] clck_gen.py:113 IND CLOCK 6324
2026-01-29 03:14:36.818 [DEBUG] clck_gen.py:113 IND CLOCK 6426
2026-01-29 03:14:37.286 [DEBUG] clck_gen.py:113 IND CLOCK 6528
2026-01-29 03:14:37.755 [DEBUG] clck_gen.py:113 IND CLOCK 6630
2026-01-29 03:14:38.228 [DEBUG] clck_gen.py:113 IND CLOCK 6732
2026-01-29 03:14:38.699 [DEBUG] clck_gen.py:113 IND CLOCK 6834
2026-01-29 03:14:39.167 [DEBUG] clck_gen.py:113 IND CLOCK 6936
2026-01-29 03:14:39.643 [DEBUG] clck_gen.py:113 IND CLOCK 7038
2026-01-29 03:14:40.143 [DEBUG] clck_gen.py:113 IND CLOCK 7140
2026-01-29 03:14:40.611 [DEBUG] clck_gen.py:113 IND CLOCK 7242
2026-01-29 03:14:41.086 [DEBUG] clck_gen.py:113 IND CLOCK 7344
2026-01-29 03:14:41.562 [DEBUG] clck_gen.py:113 IND CLOCK 7446
2026-01-29 03:14:42.036 [DEBUG] clck_gen.py:113 IND CLOCK 7548
2026-01-29 03:14:42.511 [DEBUG] clck_gen.py:113 IND CLOCK 7650
2026-01-29 03:14:42.984 [DEBUG] clck_gen.py:113 IND CLOCK 7752
2026-01-29 03:14:43.459 [DEBUG] clck_gen.py:113 IND CLOCK 7854
2026-01-29 03:14:43.489 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 03:14:43.489 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 03:14:43.489 [INFO] transceiver.py:205 (MS@172.18.28.22:6700) Frequency hopping disabled
2026-01-29 03:14:43.490 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 03:14:43.490 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:14:43.490 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:14:43.490 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:14:43.491 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 03:14:43.491 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 03:14:43.491 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 03:14:43.491 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 03:14:43.491 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.28.20:5700) Recv POWEROFF cmd
2026-01-29 03:14:43.491 [INFO] ctrl_if_trx.py:117 (BTS@172.18.28.20:5700) Stopping transceiver...
2026-01-29 03:14:43.491 [INFO] transceiver.py:246 Stopping clock generator
2026-01-29 03:14:48.492 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.28.20:5700) Recv POWEROFF cmd
2026-01-29 03:14:48.492 [INFO] ctrl_if_trx.py:117 (BTS@172.18.28.20:5700) Stopping transceiver...
2026-01-29 03:14:48.492 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 03:14:48.492 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 03:14:48.493 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 03:14:48.493 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 03:14:48.496 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 03:14:48.497 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.28.20:5700) Recv SETFORMAT cmd
2026-01-29 03:14:48.497 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.28.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:14:48.497 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.28.20:5700) Recv SETFORMAT cmd
2026-01-29 03:14:48.497 [INFO] ctrl_if_trx.py:201 (BTS@172.18.28.20:5700) TRXD header version 1 -> 1
2026-01-29 03:14:48.498 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.28.20:5700/1) Recv RXTUNE cmd
2026-01-29 03:14:48.498 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.28.20:5700/1) Recv TXTUNE cmd
2026-01-29 03:14:48.498 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.28.20:5700/1) Recv SETFORMAT cmd
2026-01-29 03:14:48.498 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.28.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:14:48.498 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 03:14:48.498 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.28.20:5700/1) Recv NOMTXPOWER cmd
2026-01-29 03:14:48.498 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.28.20:5700/1) Recv SETFORMAT cmd
2026-01-29 03:14:48.498 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.28.20:5700/1) TRXD header version 1 -> 1
2026-01-29 03:14:48.499 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.28.20:5700/2) Recv RXTUNE cmd
2026-01-29 03:14:48.499 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.28.20:5700/2) Recv TXTUNE cmd
2026-01-29 03:14:48.499 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.28.20:5700/2) Recv SETFORMAT cmd
2026-01-29 03:14:48.499 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.28.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:14:48.499 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 03:14:48.499 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.28.20:5700/2) Recv NOMTXPOWER cmd
2026-01-29 03:14:48.499 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.28.20:5700/2) Recv SETFORMAT cmd
2026-01-29 03:14:48.499 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.28.20:5700/2) TRXD header version 1 -> 1
2026-01-29 03:14:48.500 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.28.20:5700/3) Recv RXTUNE cmd
2026-01-29 03:14:48.500 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.28.20:5700/3) Recv TXTUNE cmd
2026-01-29 03:14:48.500 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.28.20:5700/3) Recv SETFORMAT cmd
2026-01-29 03:14:48.500 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.28.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:14:48.500 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.28.20:5700/3) Recv NOMTXPOWER cmd
2026-01-29 03:14:48.500 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 03:14:48.500 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.28.20:5700/3) Recv SETFORMAT cmd
2026-01-29 03:14:48.500 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.28.20:5700/3) TRXD header version 1 -> 1
2026-01-29 03:14:48.502 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.28.20:5700) Recv RXTUNE cmd
2026-01-29 03:14:48.502 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETTSC
2026-01-29 03:14:48.502 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETTSC
2026-01-29 03:14:48.502 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETTSC
2026-01-29 03:14:48.502 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.28.20:5700) Recv TXTUNE cmd
2026-01-29 03:14:48.502 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETRXGAIN
2026-01-29 03:14:48.502 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETRXGAIN
2026-01-29 03:14:48.502 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETRXGAIN
2026-01-29 03:14:48.502 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETTSC
2026-01-29 03:14:48.502 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:14:48.502 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:14:48.502 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.28.20:5700) Recv NOMTXPOWER cmd
2026-01-29 03:14:48.502 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:14:48.502 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:14:48.502 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.28.20:5700) Recv POWERON CMD
2026-01-29 03:14:48.502 [INFO] ctrl_if_trx.py:109 (BTS@172.18.28.20:5700) Starting transceiver...
2026-01-29 03:14:48.502 [INFO] transceiver.py:243 Starting clock generator
2026-01-29 03:14:48.502 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-01-29 03:14:48.502 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:14:48.503 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:14:48.503 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:14:48.503 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETRXGAIN
2026-01-29 03:14:48.503 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:14:48.503 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:14:48.503 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:14:48.503 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:14:48.503 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:14:48.503 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:14:48.503 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:14:48.503 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:14:48.503 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:14:48.503 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:14:48.503 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:14:48.503 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:14:48.503 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:14:48.503 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:14:48.503 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:14:48.503 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:14:48.503 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:14:48.503 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:14:48.503 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:14:48.503 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:14:48.503 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:14:48.503 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:14:48.503 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:14:48.503 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:14:48.503 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:14:48.507 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-01-29 03:14:48.983 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-01-29 03:14:49.033 [DEBUG] fake_trx.py:278 (BTS@172.18.28.20:5700) Recv FAKE_TOA cmd
2026-01-29 03:14:49.034 [DEBUG] fake_trx.py:297 (BTS@172.18.28.20:5700) Recv FAKE_RSSI cmd
2026-01-29 03:14:49.036 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:14:49.037 [DEBUG] fake_trx.py:322 (BTS@172.18.28.20:5700) Recv FAKE_CI cmd
2026-01-29 03:14:49.055 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 03:14:49.055 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 03:14:49.055 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 03:14:49.056 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 03:14:49.056 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 03:14:49.056 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 03:14:49.056 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.28.22:6700) Recv POWERON CMD
2026-01-29 03:14:49.056 [INFO] ctrl_if_trx.py:109 (MS@172.18.28.22:6700) Starting transceiver...
2026-01-29 03:14:49.079 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:14:49.086 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 03:14:49.086 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 03:14:49.087 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 03:14:49.087 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 03:14:49.141 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:14:49.144 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 03:14:49.145 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 03:14:49.145 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 03:14:49.163 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 03:14:49.163 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 03:14:49.163 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 03:14:49.164 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 03:14:49.164 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 03:14:49.164 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 03:14:49.164 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.28.22:6700) Recv POWERON CMD
2026-01-29 03:14:49.164 [INFO] ctrl_if_trx.py:109 (MS@172.18.28.22:6700) Starting transceiver...
2026-01-29 03:14:49.221 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:14:49.222 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 03:14:49.223 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 03:14:49.223 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 03:14:49.223 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 03:14:49.276 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:14:49.277 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 03:14:49.277 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 03:14:49.277 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 03:14:49.285 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 03:14:49.285 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 03:14:49.285 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 03:14:49.286 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 03:14:49.286 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 03:14:49.286 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 03:14:49.286 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.28.22:6700) Recv POWERON CMD
2026-01-29 03:14:49.286 [INFO] ctrl_if_trx.py:109 (MS@172.18.28.22:6700) Starting transceiver...
2026-01-29 03:14:49.309 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:14:49.310 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.28.22:6700) Recv SETFH cmd
2026-01-29 03:14:49.310 [INFO] transceiver.py:201 (MS@172.18.28.22:6700) Frequency hopping configured: hsn=5, maio=0, ma_len=4
2026-01-29 03:14:49.310 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 03:14:49.310 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 03:14:49.377 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:14:49.378 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 03:14:49.378 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 03:14:49.378 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 03:14:49.378 [INFO] transceiver.py:205 (MS@172.18.28.22:6700) Frequency hopping disabled
2026-01-29 03:14:49.387 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 03:14:49.387 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 03:14:49.387 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 03:14:49.389 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 03:14:49.389 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 03:14:49.389 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 03:14:49.389 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.28.22:6700) Recv POWERON CMD
2026-01-29 03:14:49.389 [INFO] ctrl_if_trx.py:109 (MS@172.18.28.22:6700) Starting transceiver...
2026-01-29 03:14:49.401 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:14:49.403 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.28.22:6700) Recv SETFH cmd
2026-01-29 03:14:49.403 [INFO] transceiver.py:201 (MS@172.18.28.22:6700) Frequency hopping configured: hsn=5, maio=0, ma_len=4
2026-01-29 03:14:49.403 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 03:14:49.403 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 03:14:49.456 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-01-29 03:14:49.500 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:14:49.504 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 03:14:49.505 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 03:14:49.505 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:14:49.506 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 03:14:49.506 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 03:14:49.506 [INFO] transceiver.py:205 (MS@172.18.28.22:6700) Frequency hopping disabled
2026-01-29 03:14:49.507 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:14:49.508 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:14:49.525 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 03:14:49.525 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 03:14:49.525 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 03:14:49.526 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 03:14:49.526 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 03:14:49.526 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 03:14:49.527 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.28.22:6700) Recv POWERON CMD
2026-01-29 03:14:49.527 [INFO] ctrl_if_trx.py:109 (MS@172.18.28.22:6700) Starting transceiver...
2026-01-29 03:14:49.546 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:14:49.549 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 03:14:49.549 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 03:14:49.549 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 03:14:49.549 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 03:14:49.611 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:14:49.615 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 03:14:49.616 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 03:14:49.616 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 03:14:49.636 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 03:14:49.636 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 03:14:49.636 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 03:14:49.637 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 03:14:49.637 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 03:14:49.637 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 03:14:49.637 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.28.22:6700) Recv POWERON CMD
2026-01-29 03:14:49.637 [INFO] ctrl_if_trx.py:109 (MS@172.18.28.22:6700) Starting transceiver...
2026-01-29 03:14:49.691 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:14:49.693 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 03:14:49.694 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 03:14:49.694 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 03:14:49.694 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 03:14:49.844 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:14:49.844 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 03:14:49.845 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 03:14:49.845 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 03:14:49.853 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 03:14:49.853 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 03:14:49.853 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 03:14:49.854 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 03:14:49.854 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 03:14:49.854 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 03:14:49.854 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.28.22:6700) Recv POWERON CMD
2026-01-29 03:14:49.854 [INFO] ctrl_if_trx.py:109 (MS@172.18.28.22:6700) Starting transceiver...
2026-01-29 03:14:49.872 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:14:49.874 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.28.22:6700) Recv SETFH cmd
2026-01-29 03:14:49.874 [INFO] transceiver.py:201 (MS@172.18.28.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2026-01-29 03:14:49.874 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 03:14:49.874 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 03:14:49.924 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-01-29 03:14:50.005 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:14:50.009 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 03:14:50.010 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 03:14:50.010 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 03:14:50.010 [INFO] transceiver.py:205 (MS@172.18.28.22:6700) Frequency hopping disabled
2026-01-29 03:14:50.020 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 03:14:50.021 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 03:14:50.021 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 03:14:50.022 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 03:14:50.022 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 03:14:50.022 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 03:14:50.022 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.28.22:6700) Recv POWERON CMD
2026-01-29 03:14:50.022 [INFO] ctrl_if_trx.py:109 (MS@172.18.28.22:6700) Starting transceiver...
2026-01-29 03:14:50.062 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:14:50.067 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.28.22:6700) Recv SETFH cmd
2026-01-29 03:14:50.068 [INFO] transceiver.py:201 (MS@172.18.28.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2026-01-29 03:14:50.068 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 03:14:50.068 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 03:14:50.240 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:14:50.243 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 03:14:50.245 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 03:14:50.245 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 03:14:50.245 [INFO] transceiver.py:205 (MS@172.18.28.22:6700) Frequency hopping disabled
2026-01-29 03:14:50.253 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 03:14:50.253 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:14:50.253 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:14:50.253 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:14:50.257 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 03:14:50.257 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 03:14:50.257 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 03:14:50.257 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 03:14:50.258 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.28.20:5700) Recv POWEROFF cmd
2026-01-29 03:14:50.258 [INFO] ctrl_if_trx.py:117 (BTS@172.18.28.20:5700) Stopping transceiver...
2026-01-29 03:14:50.258 [INFO] transceiver.py:246 Stopping clock generator
2026-01-29 03:14:50.258 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=380 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:14:50.258 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=380 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:14:50.258 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=380 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:14:50.259 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=380 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:14:50.259 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=380 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:14:50.259 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=380 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:14:50.259 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=380 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:14:50.259 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=381 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:14:50.259 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=381 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:14:50.259 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=381 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:14:50.259 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=381 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:14:50.259 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=381 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:14:50.259 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=381 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:14:50.259 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=381 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:14:50.260 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=381 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:14:55.257 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.28.20:5700) Recv POWEROFF cmd
2026-01-29 03:14:55.257 [INFO] ctrl_if_trx.py:117 (BTS@172.18.28.20:5700) Stopping transceiver...
2026-01-29 03:14:55.261 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 03:14:55.261 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 03:14:55.261 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 03:14:55.261 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 03:14:55.268 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 03:14:55.268 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.28.20:5700) Recv SETFORMAT cmd
2026-01-29 03:14:55.268 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.28.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:14:55.268 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.28.20:5700) Recv SETFORMAT cmd
2026-01-29 03:14:55.268 [INFO] ctrl_if_trx.py:201 (BTS@172.18.28.20:5700) TRXD header version 1 -> 1
2026-01-29 03:14:55.269 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.28.20:5700/1) Recv RXTUNE cmd
2026-01-29 03:14:55.270 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.28.20:5700/1) Recv TXTUNE cmd
2026-01-29 03:14:55.270 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.28.20:5700/1) Recv SETFORMAT cmd
2026-01-29 03:14:55.270 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.28.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:14:55.270 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 03:14:55.271 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.28.20:5700/1) Recv NOMTXPOWER cmd
2026-01-29 03:14:55.271 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.28.20:5700/1) Recv SETFORMAT cmd
2026-01-29 03:14:55.271 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.28.20:5700/1) TRXD header version 1 -> 1
2026-01-29 03:14:55.272 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.28.20:5700/2) Recv RXTUNE cmd
2026-01-29 03:14:55.272 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.28.20:5700/2) Recv TXTUNE cmd
2026-01-29 03:14:55.272 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.28.20:5700/2) Recv SETFORMAT cmd
2026-01-29 03:14:55.272 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.28.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:14:55.272 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 03:14:55.272 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.28.20:5700/2) Recv NOMTXPOWER cmd
2026-01-29 03:14:55.272 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.28.20:5700/2) Recv SETFORMAT cmd
2026-01-29 03:14:55.272 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.28.20:5700/2) TRXD header version 1 -> 1
2026-01-29 03:14:55.274 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.28.20:5700/3) Recv RXTUNE cmd
2026-01-29 03:14:55.274 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.28.20:5700/3) Recv TXTUNE cmd
2026-01-29 03:14:55.274 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.28.20:5700/3) Recv SETFORMAT cmd
2026-01-29 03:14:55.274 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.28.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:14:55.274 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 03:14:55.274 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.28.20:5700/3) Recv NOMTXPOWER cmd
2026-01-29 03:14:55.274 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.28.20:5700/3) Recv SETFORMAT cmd
2026-01-29 03:14:55.274 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.28.20:5700/3) TRXD header version 1 -> 1
2026-01-29 03:14:55.277 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.28.20:5700) Recv RXTUNE cmd
2026-01-29 03:14:55.277 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETTSC
2026-01-29 03:14:55.277 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETTSC
2026-01-29 03:14:55.277 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETTSC
2026-01-29 03:14:55.277 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.28.20:5700) Recv TXTUNE cmd
2026-01-29 03:14:55.277 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETRXGAIN
2026-01-29 03:14:55.277 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETRXGAIN
2026-01-29 03:14:55.277 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETRXGAIN
2026-01-29 03:14:55.277 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETTSC
2026-01-29 03:14:55.277 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:14:55.277 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:14:55.278 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.28.20:5700) Recv NOMTXPOWER cmd
2026-01-29 03:14:55.278 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:14:55.278 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:14:55.278 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:14:55.278 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.28.20:5700) Recv POWERON CMD
2026-01-29 03:14:55.278 [INFO] ctrl_if_trx.py:109 (BTS@172.18.28.20:5700) Starting transceiver...
2026-01-29 03:14:55.278 [INFO] transceiver.py:243 Starting clock generator
2026-01-29 03:14:55.278 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-01-29 03:14:55.278 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:14:55.278 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:14:55.278 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:14:55.278 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETRXGAIN
2026-01-29 03:14:55.278 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:14:55.278 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:14:55.278 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:14:55.278 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:14:55.278 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:14:55.278 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:14:55.278 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:14:55.278 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:14:55.278 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:14:55.279 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:14:55.279 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:14:55.279 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:14:55.279 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:14:55.279 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:14:55.279 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:14:55.279 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:14:55.279 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:14:55.279 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:14:55.279 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:14:55.279 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:14:55.279 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:14:55.279 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:14:55.279 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:14:55.279 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:14:55.283 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-01-29 03:14:55.763 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-01-29 03:14:55.806 [DEBUG] fake_trx.py:278 (BTS@172.18.28.20:5700) Recv FAKE_TOA cmd
2026-01-29 03:14:55.808 [DEBUG] fake_trx.py:297 (BTS@172.18.28.20:5700) Recv FAKE_RSSI cmd
2026-01-29 03:14:55.809 [DEBUG] fake_trx.py:322 (BTS@172.18.28.20:5700) Recv FAKE_CI cmd
2026-01-29 03:14:55.810 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:14:55.825 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 03:14:55.825 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 03:14:55.825 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 03:14:55.829 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 03:14:55.829 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 03:14:55.829 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 03:14:55.829 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.28.22:6700) Recv POWERON CMD
2026-01-29 03:14:55.829 [INFO] ctrl_if_trx.py:109 (MS@172.18.28.22:6700) Starting transceiver...
2026-01-29 03:14:55.860 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:14:55.866 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 03:14:55.866 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 03:14:55.867 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 03:14:55.867 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 03:14:56.241 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-01-29 03:14:56.280 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 03:14:56.281 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:14:56.282 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:14:56.285 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:14:56.719 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-01-29 03:14:56.737 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:14:56.739 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 03:14:56.741 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 03:14:56.741 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 03:14:56.759 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 03:14:56.759 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 03:14:56.759 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 03:14:56.760 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 03:14:56.760 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 03:14:56.760 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 03:14:56.760 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.28.22:6700) Recv POWERON CMD
2026-01-29 03:14:56.760 [INFO] ctrl_if_trx.py:109 (MS@172.18.28.22:6700) Starting transceiver...
2026-01-29 03:14:56.762 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:14:56.763 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 03:14:56.763 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 03:14:56.763 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 03:14:56.763 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 03:14:57.196 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-01-29 03:14:57.223 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:14:57.225 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 03:14:57.226 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 03:14:57.226 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 03:14:57.244 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 03:14:57.245 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 03:14:57.245 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 03:14:57.246 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 03:14:57.246 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 03:14:57.246 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 03:14:57.246 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.28.22:6700) Recv POWERON CMD
2026-01-29 03:14:57.246 [INFO] ctrl_if_trx.py:109 (MS@172.18.28.22:6700) Starting transceiver...
2026-01-29 03:14:57.281 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 03:14:57.282 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:14:57.283 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:14:57.286 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:14:57.291 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:14:57.292 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.28.22:6700) Recv SETFH cmd
2026-01-29 03:14:57.292 [INFO] transceiver.py:201 (MS@172.18.28.22:6700) Frequency hopping configured: hsn=5, maio=0, ma_len=4
2026-01-29 03:14:57.292 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 03:14:57.293 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 03:14:57.672 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-01-29 03:14:57.949 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:14:57.952 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 03:14:57.953 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 03:14:57.953 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 03:14:57.953 [INFO] transceiver.py:205 (MS@172.18.28.22:6700) Frequency hopping disabled
2026-01-29 03:14:57.972 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 03:14:57.972 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 03:14:57.972 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 03:14:57.973 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 03:14:57.973 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 03:14:57.973 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 03:14:57.973 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.28.22:6700) Recv POWERON CMD
2026-01-29 03:14:57.973 [INFO] ctrl_if_trx.py:109 (MS@172.18.28.22:6700) Starting transceiver...
2026-01-29 03:14:58.001 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:14:58.005 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.28.22:6700) Recv SETFH cmd
2026-01-29 03:14:58.005 [INFO] transceiver.py:201 (MS@172.18.28.22:6700) Frequency hopping configured: hsn=5, maio=0, ma_len=4
2026-01-29 03:14:58.005 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 03:14:58.005 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 03:14:58.142 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-01-29 03:14:58.282 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 03:14:58.282 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:14:58.285 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:14:58.287 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:14:58.425 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:14:58.428 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 03:14:58.429 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 03:14:58.429 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 03:14:58.429 [INFO] transceiver.py:205 (MS@172.18.28.22:6700) Frequency hopping disabled
2026-01-29 03:14:58.448 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 03:14:58.448 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 03:14:58.448 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 03:14:58.449 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 03:14:58.449 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 03:14:58.449 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 03:14:58.449 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.28.22:6700) Recv POWERON CMD
2026-01-29 03:14:58.449 [INFO] ctrl_if_trx.py:109 (MS@172.18.28.22:6700) Starting transceiver...
2026-01-29 03:14:58.465 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:14:58.469 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 03:14:58.469 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 03:14:58.469 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 03:14:58.469 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 03:14:58.576 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:14:58.579 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 03:14:58.580 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 03:14:58.580 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 03:14:58.600 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 03:14:58.600 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 03:14:58.600 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 03:14:58.601 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 03:14:58.601 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 03:14:58.601 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 03:14:58.601 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.28.22:6700) Recv POWERON CMD
2026-01-29 03:14:58.601 [INFO] ctrl_if_trx.py:109 (MS@172.18.28.22:6700) Starting transceiver...
2026-01-29 03:14:58.606 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:14:58.607 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 03:14:58.607 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 03:14:58.607 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 03:14:58.607 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 03:14:58.611 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-01-29 03:14:59.047 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:14:59.050 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 03:14:59.051 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 03:14:59.051 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 03:14:59.060 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 03:14:59.060 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 03:14:59.060 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 03:14:59.061 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 03:14:59.061 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 03:14:59.061 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 03:14:59.061 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.28.22:6700) Recv POWERON CMD
2026-01-29 03:14:59.061 [INFO] ctrl_if_trx.py:109 (MS@172.18.28.22:6700) Starting transceiver...
2026-01-29 03:14:59.079 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:14:59.081 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.28.22:6700) Recv SETFH cmd
2026-01-29 03:14:59.081 [INFO] transceiver.py:201 (MS@172.18.28.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2026-01-29 03:14:59.081 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 03:14:59.081 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 03:14:59.087 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-01-29 03:14:59.282 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 03:14:59.283 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:14:59.286 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:14:59.287 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:14:59.480 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:14:59.482 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 03:14:59.484 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 03:14:59.484 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 03:14:59.484 [INFO] transceiver.py:205 (MS@172.18.28.22:6700) Frequency hopping disabled
2026-01-29 03:14:59.497 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 03:14:59.497 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 03:14:59.497 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 03:14:59.499 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 03:14:59.499 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 03:14:59.499 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 03:14:59.499 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.28.22:6700) Recv POWERON CMD
2026-01-29 03:14:59.499 [INFO] ctrl_if_trx.py:109 (MS@172.18.28.22:6700) Starting transceiver...
2026-01-29 03:14:59.504 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:14:59.505 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.28.22:6700) Recv SETFH cmd
2026-01-29 03:14:59.505 [INFO] transceiver.py:201 (MS@172.18.28.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2026-01-29 03:14:59.505 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 03:14:59.505 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 03:14:59.559 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-01-29 03:14:59.950 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:14:59.952 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 03:14:59.953 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 03:14:59.953 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 03:14:59.954 [INFO] transceiver.py:205 (MS@172.18.28.22:6700) Frequency hopping disabled
2026-01-29 03:14:59.960 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 03:14:59.960 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:14:59.960 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:14:59.960 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:14:59.960 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 03:14:59.960 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 03:14:59.960 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 03:14:59.960 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.28.20:5700) Recv POWEROFF cmd
2026-01-29 03:14:59.960 [INFO] ctrl_if_trx.py:117 (BTS@172.18.28.20:5700) Stopping transceiver...
2026-01-29 03:14:59.960 [INFO] transceiver.py:246 Stopping clock generator
2026-01-29 03:14:59.960 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 03:14:59.961 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=1007 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:14:59.961 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=1007 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:14:59.961 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=1007 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:14:59.961 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=1007 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:14:59.961 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=1007 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:14:59.961 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=1007 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:14:59.961 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=1007 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:14:59.961 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=1007 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:15:04.962 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.28.20:5700) Recv POWEROFF cmd
2026-01-29 03:15:04.962 [INFO] ctrl_if_trx.py:117 (BTS@172.18.28.20:5700) Stopping transceiver...
2026-01-29 03:15:04.963 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 03:15:04.964 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 03:15:04.965 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 03:15:04.966 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 03:15:04.972 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 03:15:04.973 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.28.20:5700) Recv SETFORMAT cmd
2026-01-29 03:15:04.973 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.28.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:15:04.973 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.28.20:5700) Recv SETFORMAT cmd
2026-01-29 03:15:04.973 [INFO] ctrl_if_trx.py:201 (BTS@172.18.28.20:5700) TRXD header version 1 -> 1
2026-01-29 03:15:04.976 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.28.20:5700/1) Recv RXTUNE cmd
2026-01-29 03:15:04.976 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.28.20:5700/1) Recv TXTUNE cmd
2026-01-29 03:15:04.977 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.28.20:5700/1) Recv SETFORMAT cmd
2026-01-29 03:15:04.977 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.28.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:15:04.977 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 03:15:04.977 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.28.20:5700/1) Recv NOMTXPOWER cmd
2026-01-29 03:15:04.977 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.28.20:5700/1) Recv SETFORMAT cmd
2026-01-29 03:15:04.977 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.28.20:5700/1) TRXD header version 1 -> 1
2026-01-29 03:15:04.979 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.28.20:5700/2) Recv RXTUNE cmd
2026-01-29 03:15:04.979 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.28.20:5700/2) Recv TXTUNE cmd
2026-01-29 03:15:04.979 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.28.20:5700/2) Recv SETFORMAT cmd
2026-01-29 03:15:04.979 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.28.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:15:04.980 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 03:15:04.980 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.28.20:5700/2) Recv NOMTXPOWER cmd
2026-01-29 03:15:04.980 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.28.20:5700/2) Recv SETFORMAT cmd
2026-01-29 03:15:04.980 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.28.20:5700/2) TRXD header version 1 -> 1
2026-01-29 03:15:04.981 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.28.20:5700/3) Recv RXTUNE cmd
2026-01-29 03:15:04.981 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.28.20:5700/3) Recv TXTUNE cmd
2026-01-29 03:15:04.981 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.28.20:5700/3) Recv SETFORMAT cmd
2026-01-29 03:15:04.981 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.28.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:15:04.982 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 03:15:04.982 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.28.20:5700/3) Recv NOMTXPOWER cmd
2026-01-29 03:15:04.982 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.28.20:5700/3) Recv SETFORMAT cmd
2026-01-29 03:15:04.982 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.28.20:5700/3) TRXD header version 1 -> 1
2026-01-29 03:15:04.983 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.28.20:5700) Recv RXTUNE cmd
2026-01-29 03:15:04.983 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETTSC
2026-01-29 03:15:04.983 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETTSC
2026-01-29 03:15:04.983 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETTSC
2026-01-29 03:15:04.983 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.28.20:5700) Recv TXTUNE cmd
2026-01-29 03:15:04.984 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETRXGAIN
2026-01-29 03:15:04.984 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETRXGAIN
2026-01-29 03:15:04.984 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETRXGAIN
2026-01-29 03:15:04.984 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETTSC
2026-01-29 03:15:04.984 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:15:04.984 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:15:04.984 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:15:04.984 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.28.20:5700) Recv NOMTXPOWER cmd
2026-01-29 03:15:04.984 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:15:04.984 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:15:04.984 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:15:04.984 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.28.20:5700) Recv POWERON CMD
2026-01-29 03:15:04.984 [INFO] ctrl_if_trx.py:109 (BTS@172.18.28.20:5700) Starting transceiver...
2026-01-29 03:15:04.984 [INFO] transceiver.py:243 Starting clock generator
2026-01-29 03:15:04.984 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-01-29 03:15:04.984 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:15:04.984 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:15:04.984 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:15:04.984 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETRXGAIN
2026-01-29 03:15:04.984 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:15:04.984 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:15:04.984 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:15:04.984 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:15:04.984 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:15:04.984 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:15:04.984 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:15:04.984 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:15:04.984 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:15:04.984 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:15:04.984 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:15:04.984 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:15:04.984 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:15:04.984 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:15:04.984 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:15:04.984 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:15:04.984 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:15:04.985 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:15:04.985 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:15:04.985 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:15:04.985 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:15:04.985 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:15:04.985 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:15:04.989 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-01-29 03:15:05.470 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-01-29 03:15:05.512 [DEBUG] fake_trx.py:278 (BTS@172.18.28.20:5700) Recv FAKE_TOA cmd
2026-01-29 03:15:05.513 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:15:05.514 [DEBUG] fake_trx.py:297 (BTS@172.18.28.20:5700) Recv FAKE_RSSI cmd
2026-01-29 03:15:05.516 [DEBUG] fake_trx.py:322 (BTS@172.18.28.20:5700) Recv FAKE_CI cmd
2026-01-29 03:15:05.541 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 03:15:05.541 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 03:15:05.541 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 03:15:05.542 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 03:15:05.542 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 03:15:05.542 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 03:15:05.542 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.28.22:6700) Recv POWERON CMD
2026-01-29 03:15:05.542 [INFO] ctrl_if_trx.py:109 (MS@172.18.28.22:6700) Starting transceiver...
2026-01-29 03:15:05.565 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:15:05.571 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 03:15:05.571 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 03:15:05.571 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 03:15:05.572 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 03:15:05.628 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:15:05.631 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 03:15:05.632 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 03:15:05.632 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 03:15:05.652 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 03:15:05.652 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 03:15:05.652 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 03:15:05.653 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 03:15:05.653 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 03:15:05.653 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 03:15:05.653 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.28.22:6700) Recv POWERON CMD
2026-01-29 03:15:05.653 [INFO] ctrl_if_trx.py:109 (MS@172.18.28.22:6700) Starting transceiver...
2026-01-29 03:15:05.707 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:15:05.712 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 03:15:05.712 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 03:15:05.712 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 03:15:05.713 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 03:15:05.766 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:15:05.768 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 03:15:05.770 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 03:15:05.770 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 03:15:05.788 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 03:15:05.788 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 03:15:05.788 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 03:15:05.790 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 03:15:05.790 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 03:15:05.790 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 03:15:05.790 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.28.22:6700) Recv POWERON CMD
2026-01-29 03:15:05.790 [INFO] ctrl_if_trx.py:109 (MS@172.18.28.22:6700) Starting transceiver...
2026-01-29 03:15:05.794 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:15:05.795 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.28.22:6700) Recv SETFH cmd
2026-01-29 03:15:05.795 [INFO] transceiver.py:201 (MS@172.18.28.22:6700) Frequency hopping configured: hsn=5, maio=0, ma_len=4
2026-01-29 03:15:05.796 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 03:15:05.796 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 03:15:05.886 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:15:05.888 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 03:15:05.889 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 03:15:05.890 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 03:15:05.890 [INFO] transceiver.py:205 (MS@172.18.28.22:6700) Frequency hopping disabled
2026-01-29 03:15:05.910 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 03:15:05.910 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 03:15:05.910 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 03:15:05.911 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 03:15:05.911 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 03:15:05.911 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 03:15:05.912 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.28.22:6700) Recv POWERON CMD
2026-01-29 03:15:05.912 [INFO] ctrl_if_trx.py:109 (MS@172.18.28.22:6700) Starting transceiver...
2026-01-29 03:15:05.944 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:15:05.946 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-01-29 03:15:05.950 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.28.22:6700) Recv SETFH cmd
2026-01-29 03:15:05.950 [INFO] transceiver.py:201 (MS@172.18.28.22:6700) Frequency hopping configured: hsn=5, maio=0, ma_len=4
2026-01-29 03:15:05.950 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 03:15:05.951 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 03:15:05.987 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:15:05.987 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 03:15:05.987 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:15:05.990 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:15:06.014 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:15:06.017 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 03:15:06.018 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 03:15:06.019 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 03:15:06.019 [INFO] transceiver.py:205 (MS@172.18.28.22:6700) Frequency hopping disabled
2026-01-29 03:15:06.037 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 03:15:06.037 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 03:15:06.037 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 03:15:06.039 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 03:15:06.039 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 03:15:06.039 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 03:15:06.039 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.28.22:6700) Recv POWERON CMD
2026-01-29 03:15:06.039 [INFO] ctrl_if_trx.py:109 (MS@172.18.28.22:6700) Starting transceiver...
2026-01-29 03:15:06.088 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:15:06.094 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 03:15:06.094 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 03:15:06.095 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 03:15:06.095 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 03:15:06.173 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:15:06.176 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 03:15:06.178 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 03:15:06.178 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 03:15:06.196 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 03:15:06.196 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 03:15:06.196 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 03:15:06.197 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 03:15:06.197 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 03:15:06.197 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 03:15:06.197 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.28.22:6700) Recv POWERON CMD
2026-01-29 03:15:06.197 [INFO] ctrl_if_trx.py:109 (MS@172.18.28.22:6700) Starting transceiver...
2026-01-29 03:15:06.231 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:15:06.236 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 03:15:06.237 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 03:15:06.237 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 03:15:06.237 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 03:15:06.408 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:15:06.411 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 03:15:06.412 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 03:15:06.412 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 03:15:06.423 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-01-29 03:15:06.431 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 03:15:06.431 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 03:15:06.432 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 03:15:06.433 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 03:15:06.433 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 03:15:06.433 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 03:15:06.433 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.28.22:6700) Recv POWERON CMD
2026-01-29 03:15:06.433 [INFO] ctrl_if_trx.py:109 (MS@172.18.28.22:6700) Starting transceiver...
2026-01-29 03:15:06.473 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:15:06.479 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.28.22:6700) Recv SETFH cmd
2026-01-29 03:15:06.479 [INFO] transceiver.py:201 (MS@172.18.28.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2026-01-29 03:15:06.480 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 03:15:06.480 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 03:15:06.902 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-01-29 03:15:06.988 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 03:15:06.989 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:15:06.989 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:15:06.991 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:15:07.063 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:15:07.067 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 03:15:07.069 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 03:15:07.069 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 03:15:07.069 [INFO] transceiver.py:205 (MS@172.18.28.22:6700) Frequency hopping disabled
2026-01-29 03:15:07.087 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 03:15:07.087 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 03:15:07.087 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 03:15:07.089 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 03:15:07.089 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 03:15:07.089 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 03:15:07.089 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.28.22:6700) Recv POWERON CMD
2026-01-29 03:15:07.089 [INFO] ctrl_if_trx.py:109 (MS@172.18.28.22:6700) Starting transceiver...
2026-01-29 03:15:07.140 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:15:07.146 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.28.22:6700) Recv SETFH cmd
2026-01-29 03:15:07.146 [INFO] transceiver.py:201 (MS@172.18.28.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2026-01-29 03:15:07.146 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 03:15:07.147 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 03:15:07.291 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:15:07.294 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 03:15:07.296 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 03:15:07.296 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 03:15:07.296 [INFO] transceiver.py:205 (MS@172.18.28.22:6700) Frequency hopping disabled
2026-01-29 03:15:07.305 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 03:15:07.305 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:15:07.306 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:15:07.306 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:15:07.309 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 03:15:07.309 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 03:15:07.309 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 03:15:07.310 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 03:15:07.310 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.28.20:5700) Recv POWEROFF cmd
2026-01-29 03:15:07.310 [INFO] ctrl_if_trx.py:117 (BTS@172.18.28.20:5700) Stopping transceiver...
2026-01-29 03:15:07.310 [INFO] transceiver.py:246 Stopping clock generator
2026-01-29 03:15:07.310 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=498 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:15:07.310 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=498 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:15:07.311 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=498 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:15:07.311 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=498 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:15:07.311 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=498 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:15:07.311 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=498 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:15:12.328 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.28.20:5700) Recv POWEROFF cmd
2026-01-29 03:15:12.328 [INFO] ctrl_if_trx.py:117 (BTS@172.18.28.20:5700) Stopping transceiver...
2026-01-29 03:15:12.329 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 03:15:12.331 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 03:15:12.332 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 03:15:12.332 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 03:15:12.343 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 03:15:12.343 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.28.20:5700) Recv SETFORMAT cmd
2026-01-29 03:15:12.343 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.28.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:15:12.343 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.28.20:5700) Recv SETFORMAT cmd
2026-01-29 03:15:12.344 [INFO] ctrl_if_trx.py:201 (BTS@172.18.28.20:5700) TRXD header version 1 -> 1
2026-01-29 03:15:12.345 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.28.20:5700/1) Recv RXTUNE cmd
2026-01-29 03:15:12.345 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.28.20:5700/1) Recv TXTUNE cmd
2026-01-29 03:15:12.345 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.28.20:5700/1) Recv SETFORMAT cmd
2026-01-29 03:15:12.345 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.28.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:15:12.346 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 03:15:12.346 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.28.20:5700/1) Recv NOMTXPOWER cmd
2026-01-29 03:15:12.346 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.28.20:5700/1) Recv SETFORMAT cmd
2026-01-29 03:15:12.346 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.28.20:5700/1) TRXD header version 1 -> 1
2026-01-29 03:15:12.347 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.28.20:5700/2) Recv RXTUNE cmd
2026-01-29 03:15:12.347 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.28.20:5700/2) Recv TXTUNE cmd
2026-01-29 03:15:12.347 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.28.20:5700/2) Recv SETFORMAT cmd
2026-01-29 03:15:12.347 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.28.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:15:12.347 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 03:15:12.348 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.28.20:5700/2) Recv NOMTXPOWER cmd
2026-01-29 03:15:12.348 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.28.20:5700/2) Recv SETFORMAT cmd
2026-01-29 03:15:12.348 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.28.20:5700/2) TRXD header version 1 -> 1
2026-01-29 03:15:12.349 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.28.20:5700/3) Recv RXTUNE cmd
2026-01-29 03:15:12.349 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.28.20:5700/3) Recv TXTUNE cmd
2026-01-29 03:15:12.349 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.28.20:5700/3) Recv SETFORMAT cmd
2026-01-29 03:15:12.349 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.28.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:15:12.349 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 03:15:12.350 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.28.20:5700/3) Recv NOMTXPOWER cmd
2026-01-29 03:15:12.350 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.28.20:5700/3) Recv SETFORMAT cmd
2026-01-29 03:15:12.350 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.28.20:5700/3) TRXD header version 1 -> 1
2026-01-29 03:15:12.352 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.28.20:5700) Recv RXTUNE cmd
2026-01-29 03:15:12.352 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETTSC
2026-01-29 03:15:12.352 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETTSC
2026-01-29 03:15:12.352 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.28.20:5700) Recv TXTUNE cmd
2026-01-29 03:15:12.352 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETTSC
2026-01-29 03:15:12.352 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETRXGAIN
2026-01-29 03:15:12.352 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETRXGAIN
2026-01-29 03:15:12.352 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETTSC
2026-01-29 03:15:12.352 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETRXGAIN
2026-01-29 03:15:12.352 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:15:12.352 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:15:12.352 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.28.20:5700) Recv NOMTXPOWER cmd
2026-01-29 03:15:12.352 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:15:12.352 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:15:12.352 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:15:12.352 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.28.20:5700) Recv POWERON CMD
2026-01-29 03:15:12.352 [INFO] ctrl_if_trx.py:109 (BTS@172.18.28.20:5700) Starting transceiver...
2026-01-29 03:15:12.352 [INFO] transceiver.py:243 Starting clock generator
2026-01-29 03:15:12.353 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-01-29 03:15:12.353 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:15:12.353 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:15:12.353 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:15:12.353 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETRXGAIN
2026-01-29 03:15:12.353 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:15:12.353 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:15:12.353 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:15:12.353 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:15:12.353 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:15:12.353 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:15:12.353 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:15:12.353 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:15:12.353 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:15:12.353 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:15:12.353 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:15:12.353 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:15:12.353 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:15:12.353 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:15:12.353 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:15:12.353 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:15:12.353 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:15:12.353 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:15:12.353 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:15:12.354 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:15:12.354 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:15:12.354 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:15:12.354 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:15:12.354 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:15:12.357 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-01-29 03:15:12.838 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-01-29 03:15:12.879 [DEBUG] fake_trx.py:278 (BTS@172.18.28.20:5700) Recv FAKE_TOA cmd
2026-01-29 03:15:12.881 [DEBUG] fake_trx.py:297 (BTS@172.18.28.20:5700) Recv FAKE_RSSI cmd
2026-01-29 03:15:12.881 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:15:12.882 [DEBUG] fake_trx.py:322 (BTS@172.18.28.20:5700) Recv FAKE_CI cmd
2026-01-29 03:15:12.893 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 03:15:12.893 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 03:15:12.894 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 03:15:12.896 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 03:15:12.896 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 03:15:12.896 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 03:15:12.896 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.28.22:6700) Recv POWERON CMD
2026-01-29 03:15:12.897 [INFO] ctrl_if_trx.py:109 (MS@172.18.28.22:6700) Starting transceiver...
2026-01-29 03:15:12.933 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:15:12.939 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 03:15:12.939 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 03:15:12.939 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 03:15:12.940 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 03:15:13.315 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-01-29 03:15:13.356 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:15:13.356 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 03:15:13.356 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:15:13.360 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:15:13.793 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-01-29 03:15:13.814 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:15:13.816 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 03:15:13.819 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 03:15:13.819 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 03:15:13.839 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 03:15:13.839 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 03:15:13.839 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 03:15:13.840 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 03:15:13.840 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 03:15:13.840 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 03:15:13.840 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.28.22:6700) Recv POWERON CMD
2026-01-29 03:15:13.840 [INFO] ctrl_if_trx.py:109 (MS@172.18.28.22:6700) Starting transceiver...
2026-01-29 03:15:13.888 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:15:13.893 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 03:15:13.894 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 03:15:13.894 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 03:15:13.894 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 03:15:14.270 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-01-29 03:15:14.357 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 03:15:14.357 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:15:14.357 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:15:14.362 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:15:14.748 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-01-29 03:15:14.786 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:15:14.789 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 03:15:14.791 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 03:15:14.791 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 03:15:14.809 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 03:15:14.809 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 03:15:14.809 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 03:15:14.810 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 03:15:14.810 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 03:15:14.810 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 03:15:14.810 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.28.22:6700) Recv POWERON CMD
2026-01-29 03:15:14.810 [INFO] ctrl_if_trx.py:109 (MS@172.18.28.22:6700) Starting transceiver...
2026-01-29 03:15:14.841 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:15:14.846 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.28.22:6700) Recv SETFH cmd
2026-01-29 03:15:14.846 [INFO] transceiver.py:201 (MS@172.18.28.22:6700) Frequency hopping configured: hsn=5, maio=0, ma_len=4
2026-01-29 03:15:14.846 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 03:15:14.846 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 03:15:15.221 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-01-29 03:15:15.358 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:15:15.358 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 03:15:15.358 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:15:15.362 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:15:15.690 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-01-29 03:15:15.987 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:15:15.990 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 03:15:15.992 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 03:15:15.992 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 03:15:15.992 [INFO] transceiver.py:205 (MS@172.18.28.22:6700) Frequency hopping disabled
2026-01-29 03:15:16.010 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 03:15:16.010 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 03:15:16.011 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 03:15:16.012 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 03:15:16.012 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 03:15:16.012 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 03:15:16.012 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.28.22:6700) Recv POWERON CMD
2026-01-29 03:15:16.012 [INFO] ctrl_if_trx.py:109 (MS@172.18.28.22:6700) Starting transceiver...
2026-01-29 03:15:16.014 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:15:16.015 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.28.22:6700) Recv SETFH cmd
2026-01-29 03:15:16.015 [INFO] transceiver.py:201 (MS@172.18.28.22:6700) Frequency hopping configured: hsn=5, maio=0, ma_len=4
2026-01-29 03:15:16.015 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 03:15:16.015 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 03:15:16.162 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-01-29 03:15:16.359 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 03:15:16.359 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:15:16.359 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:15:16.363 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:15:16.641 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-01-29 03:15:16.957 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:15:16.959 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 03:15:16.961 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 03:15:16.961 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 03:15:16.961 [INFO] transceiver.py:205 (MS@172.18.28.22:6700) Frequency hopping disabled
2026-01-29 03:15:16.981 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 03:15:16.981 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 03:15:16.981 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 03:15:16.983 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 03:15:16.983 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 03:15:16.983 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 03:15:16.983 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.28.22:6700) Recv POWERON CMD
2026-01-29 03:15:16.983 [INFO] ctrl_if_trx.py:109 (MS@172.18.28.22:6700) Starting transceiver...
2026-01-29 03:15:17.016 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:15:17.021 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 03:15:17.021 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 03:15:17.021 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 03:15:17.021 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 03:15:17.112 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-01-29 03:15:17.359 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:15:17.360 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 03:15:17.360 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:15:17.364 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:15:17.586 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-01-29 03:15:17.620 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:15:17.622 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 03:15:17.623 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 03:15:17.623 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 03:15:17.642 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 03:15:17.642 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 03:15:17.642 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 03:15:17.643 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 03:15:17.643 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 03:15:17.643 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 03:15:17.643 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.28.22:6700) Recv POWERON CMD
2026-01-29 03:15:17.643 [INFO] ctrl_if_trx.py:109 (MS@172.18.28.22:6700) Starting transceiver...
2026-01-29 03:15:17.675 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:15:17.681 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 03:15:17.681 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 03:15:17.681 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 03:15:17.681 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 03:15:18.063 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-01-29 03:15:18.541 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-01-29 03:15:18.579 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:15:18.582 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 03:15:18.583 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 03:15:18.583 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 03:15:18.596 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 03:15:18.596 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 03:15:18.596 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 03:15:18.597 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 03:15:18.597 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 03:15:18.597 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 03:15:18.597 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.28.22:6700) Recv POWERON CMD
2026-01-29 03:15:18.597 [INFO] ctrl_if_trx.py:109 (MS@172.18.28.22:6700) Starting transceiver...
2026-01-29 03:15:18.635 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:15:18.640 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.28.22:6700) Recv SETFH cmd
2026-01-29 03:15:18.641 [INFO] transceiver.py:201 (MS@172.18.28.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2026-01-29 03:15:18.641 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 03:15:18.641 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 03:15:19.015 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-01-29 03:15:19.493 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-01-29 03:15:19.971 [DEBUG] clck_gen.py:113 IND CLOCK 1632
2026-01-29 03:15:20.426 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:15:20.428 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 03:15:20.430 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 03:15:20.430 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 03:15:20.430 [INFO] transceiver.py:205 (MS@172.18.28.22:6700) Frequency hopping disabled
2026-01-29 03:15:20.448 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 03:15:20.448 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 03:15:20.448 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 03:15:20.449 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 03:15:20.449 [DEBUG] clck_gen.py:113 IND CLOCK 1734
2026-01-29 03:15:20.449 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 03:15:20.449 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 03:15:20.449 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.28.22:6700) Recv POWERON CMD
2026-01-29 03:15:20.449 [INFO] ctrl_if_trx.py:109 (MS@172.18.28.22:6700) Starting transceiver...
2026-01-29 03:15:20.499 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:15:20.504 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.28.22:6700) Recv SETFH cmd
2026-01-29 03:15:20.504 [INFO] transceiver.py:201 (MS@172.18.28.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2026-01-29 03:15:20.505 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 03:15:20.505 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 03:15:20.927 [DEBUG] clck_gen.py:113 IND CLOCK 1836
2026-01-29 03:15:21.405 [DEBUG] clck_gen.py:113 IND CLOCK 1938
2026-01-29 03:15:21.884 [DEBUG] clck_gen.py:113 IND CLOCK 2040
2026-01-29 03:15:22.347 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:15:22.350 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 03:15:22.351 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 03:15:22.352 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 03:15:22.352 [INFO] transceiver.py:205 (MS@172.18.28.22:6700) Frequency hopping disabled
2026-01-29 03:15:22.361 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 03:15:22.361 [DEBUG] clck_gen.py:113 IND CLOCK 2142
2026-01-29 03:15:22.361 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:15:22.362 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:15:22.362 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:15:22.362 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 03:15:22.362 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 03:15:22.362 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 03:15:22.362 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 03:15:22.362 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.28.20:5700) Recv POWEROFF cmd
2026-01-29 03:15:22.362 [INFO] ctrl_if_trx.py:117 (BTS@172.18.28.20:5700) Stopping transceiver...
2026-01-29 03:15:22.362 [INFO] transceiver.py:246 Stopping clock generator
2026-01-29 03:15:27.363 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.28.20:5700) Recv POWEROFF cmd
2026-01-29 03:15:27.363 [INFO] ctrl_if_trx.py:117 (BTS@172.18.28.20:5700) Stopping transceiver...
2026-01-29 03:15:27.365 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 03:15:27.366 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 03:15:27.366 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 03:15:27.366 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 03:15:27.373 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 03:15:27.375 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.28.20:5700) Recv SETFORMAT cmd
2026-01-29 03:15:27.375 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.28.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:15:27.375 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.28.20:5700) Recv SETFORMAT cmd
2026-01-29 03:15:27.375 [INFO] ctrl_if_trx.py:201 (BTS@172.18.28.20:5700) TRXD header version 1 -> 1
2026-01-29 03:15:27.379 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.28.20:5700/1) Recv RXTUNE cmd
2026-01-29 03:15:27.379 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.28.20:5700/1) Recv TXTUNE cmd
2026-01-29 03:15:27.379 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.28.20:5700/1) Recv SETFORMAT cmd
2026-01-29 03:15:27.379 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.28.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:15:27.380 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 03:15:27.380 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.28.20:5700/1) Recv NOMTXPOWER cmd
2026-01-29 03:15:27.380 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.28.20:5700/1) Recv SETFORMAT cmd
2026-01-29 03:15:27.380 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.28.20:5700/1) TRXD header version 1 -> 1
2026-01-29 03:15:27.383 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.28.20:5700/2) Recv RXTUNE cmd
2026-01-29 03:15:27.383 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.28.20:5700/2) Recv TXTUNE cmd
2026-01-29 03:15:27.383 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.28.20:5700/2) Recv SETFORMAT cmd
2026-01-29 03:15:27.383 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.28.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:15:27.383 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 03:15:27.383 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.28.20:5700/2) Recv NOMTXPOWER cmd
2026-01-29 03:15:27.383 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.28.20:5700/2) Recv SETFORMAT cmd
2026-01-29 03:15:27.384 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.28.20:5700/2) TRXD header version 1 -> 1
2026-01-29 03:15:27.386 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.28.20:5700/3) Recv RXTUNE cmd
2026-01-29 03:15:27.386 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.28.20:5700/3) Recv TXTUNE cmd
2026-01-29 03:15:27.386 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.28.20:5700/3) Recv SETFORMAT cmd
2026-01-29 03:15:27.386 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.28.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:15:27.386 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 03:15:27.386 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.28.20:5700/3) Recv NOMTXPOWER cmd
2026-01-29 03:15:27.386 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.28.20:5700/3) Recv SETFORMAT cmd
2026-01-29 03:15:27.386 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.28.20:5700/3) TRXD header version 1 -> 1
2026-01-29 03:15:27.389 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.28.20:5700) Recv RXTUNE cmd
2026-01-29 03:15:27.389 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETTSC
2026-01-29 03:15:27.389 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETTSC
2026-01-29 03:15:27.389 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETTSC
2026-01-29 03:15:27.389 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.28.20:5700) Recv TXTUNE cmd
2026-01-29 03:15:27.389 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETRXGAIN
2026-01-29 03:15:27.389 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETRXGAIN
2026-01-29 03:15:27.389 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETRXGAIN
2026-01-29 03:15:27.389 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETTSC
2026-01-29 03:15:27.389 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:15:27.389 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:15:27.389 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:15:27.389 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.28.20:5700) Recv NOMTXPOWER cmd
2026-01-29 03:15:27.389 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:15:27.389 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:15:27.389 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:15:27.389 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.28.20:5700) Recv POWERON CMD
2026-01-29 03:15:27.389 [INFO] ctrl_if_trx.py:109 (BTS@172.18.28.20:5700) Starting transceiver...
2026-01-29 03:15:27.389 [INFO] transceiver.py:243 Starting clock generator
2026-01-29 03:15:27.389 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-01-29 03:15:27.389 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:15:27.389 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:15:27.389 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:15:27.390 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETRXGAIN
2026-01-29 03:15:27.390 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:15:27.390 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:15:27.390 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:15:27.390 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:15:27.390 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:15:27.390 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:15:27.390 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:15:27.390 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:15:27.390 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:15:27.390 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:15:27.390 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:15:27.390 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:15:27.390 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:15:27.390 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:15:27.390 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:15:27.390 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:15:27.390 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:15:27.390 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:15:27.390 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:15:27.390 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:15:27.390 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:15:27.390 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:15:27.390 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:15:27.394 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-01-29 03:15:27.876 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-01-29 03:15:27.922 [DEBUG] fake_trx.py:278 (BTS@172.18.28.20:5700) Recv FAKE_TOA cmd
2026-01-29 03:15:27.924 [DEBUG] fake_trx.py:297 (BTS@172.18.28.20:5700) Recv FAKE_RSSI cmd
2026-01-29 03:15:27.926 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:15:27.926 [DEBUG] fake_trx.py:322 (BTS@172.18.28.20:5700) Recv FAKE_CI cmd
2026-01-29 03:15:27.952 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 03:15:27.952 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 03:15:27.952 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 03:15:27.955 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 03:15:27.955 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 03:15:27.955 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 03:15:27.955 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.28.22:6700) Recv POWERON CMD
2026-01-29 03:15:27.955 [INFO] ctrl_if_trx.py:109 (MS@172.18.28.22:6700) Starting transceiver...
2026-01-29 03:15:27.971 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:15:27.974 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 03:15:27.974 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 03:15:27.974 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 03:15:27.974 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 03:15:28.077 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:15:28.079 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 03:15:28.081 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 03:15:28.081 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 03:15:28.099 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 03:15:28.099 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 03:15:28.099 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 03:15:28.100 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 03:15:28.100 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 03:15:28.100 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 03:15:28.100 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.28.22:6700) Recv POWERON CMD
2026-01-29 03:15:28.100 [INFO] ctrl_if_trx.py:109 (MS@172.18.28.22:6700) Starting transceiver...
2026-01-29 03:15:28.110 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:15:28.111 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.28.22:6700) Recv SETFH cmd
2026-01-29 03:15:28.111 [INFO] transceiver.py:201 (MS@172.18.28.22:6700) Frequency hopping configured: hsn=5, maio=0, ma_len=4
2026-01-29 03:15:28.111 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 03:15:28.111 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 03:15:28.256 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:15:28.258 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 03:15:28.260 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 03:15:28.260 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 03:15:28.260 [INFO] transceiver.py:205 (MS@172.18.28.22:6700) Frequency hopping disabled
2026-01-29 03:15:28.279 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 03:15:28.279 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 03:15:28.279 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 03:15:28.280 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 03:15:28.280 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 03:15:28.280 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 03:15:28.280 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.28.22:6700) Recv POWERON CMD
2026-01-29 03:15:28.280 [INFO] ctrl_if_trx.py:109 (MS@172.18.28.22:6700) Starting transceiver...
2026-01-29 03:15:28.296 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:15:28.299 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 03:15:28.299 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 03:15:28.299 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 03:15:28.299 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 03:15:28.349 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-01-29 03:15:28.393 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:15:28.393 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 03:15:28.393 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:15:28.397 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:15:28.576 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:15:28.579 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 03:15:28.580 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 03:15:28.580 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 03:15:28.598 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 03:15:28.598 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 03:15:28.598 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 03:15:28.599 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 03:15:28.599 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 03:15:28.599 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 03:15:28.599 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.28.22:6700) Recv POWERON CMD
2026-01-29 03:15:28.599 [INFO] ctrl_if_trx.py:109 (MS@172.18.28.22:6700) Starting transceiver...
2026-01-29 03:15:28.634 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:15:28.638 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.28.22:6700) Recv SETFH cmd
2026-01-29 03:15:28.638 [INFO] transceiver.py:201 (MS@172.18.28.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2026-01-29 03:15:28.638 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 03:15:28.639 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 03:15:28.826 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-01-29 03:15:29.304 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-01-29 03:15:29.394 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 03:15:29.394 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:15:29.394 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:15:29.398 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:15:29.459 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:15:29.463 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 03:15:29.465 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 03:15:29.465 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 03:15:29.465 [INFO] transceiver.py:205 (MS@172.18.28.22:6700) Frequency hopping disabled
2026-01-29 03:15:29.473 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 03:15:29.473 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:15:29.474 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:15:29.474 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:15:29.477 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 03:15:29.477 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 03:15:29.477 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 03:15:29.477 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 03:15:29.478 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.28.20:5700) Recv POWEROFF cmd
2026-01-29 03:15:29.478 [INFO] ctrl_if_trx.py:117 (BTS@172.18.28.20:5700) Stopping transceiver...
2026-01-29 03:15:29.478 [INFO] transceiver.py:246 Stopping clock generator
2026-01-29 03:15:29.478 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=446 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:15:29.479 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=446 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:15:29.479 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=446 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:15:29.479 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=446 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:15:29.479 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=446 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:15:29.479 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=446 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:15:29.479 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=446 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:15:29.479 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=447 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:15:29.479 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=447 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:15:29.479 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=447 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:15:29.479 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=447 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:15:29.479 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=447 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:15:29.480 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=447 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:15:29.480 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=447 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:15:29.480 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=447 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:15:34.477 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.28.20:5700) Recv POWEROFF cmd
2026-01-29 03:15:34.477 [INFO] ctrl_if_trx.py:117 (BTS@172.18.28.20:5700) Stopping transceiver...
2026-01-29 03:15:34.479 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 03:15:34.480 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 03:15:34.480 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 03:15:34.481 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 03:15:34.485 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 03:15:34.486 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.28.20:5700) Recv SETFORMAT cmd
2026-01-29 03:15:34.486 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.28.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:15:34.486 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.28.20:5700) Recv SETFORMAT cmd
2026-01-29 03:15:34.486 [INFO] ctrl_if_trx.py:201 (BTS@172.18.28.20:5700) TRXD header version 1 -> 1
2026-01-29 03:15:34.488 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.28.20:5700/1) Recv RXTUNE cmd
2026-01-29 03:15:34.488 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.28.20:5700/1) Recv TXTUNE cmd
2026-01-29 03:15:34.489 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.28.20:5700/1) Recv SETFORMAT cmd
2026-01-29 03:15:34.489 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.28.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:15:34.489 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 03:15:34.489 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.28.20:5700/1) Recv NOMTXPOWER cmd
2026-01-29 03:15:34.489 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.28.20:5700/1) Recv SETFORMAT cmd
2026-01-29 03:15:34.489 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.28.20:5700/1) TRXD header version 1 -> 1
2026-01-29 03:15:34.491 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.28.20:5700/2) Recv RXTUNE cmd
2026-01-29 03:15:34.491 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.28.20:5700/2) Recv TXTUNE cmd
2026-01-29 03:15:34.492 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.28.20:5700/2) Recv SETFORMAT cmd
2026-01-29 03:15:34.492 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.28.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:15:34.492 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 03:15:34.492 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.28.20:5700/2) Recv NOMTXPOWER cmd
2026-01-29 03:15:34.492 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.28.20:5700/2) Recv SETFORMAT cmd
2026-01-29 03:15:34.492 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.28.20:5700/2) TRXD header version 1 -> 1
2026-01-29 03:15:34.494 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.28.20:5700/3) Recv RXTUNE cmd
2026-01-29 03:15:34.494 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.28.20:5700/3) Recv TXTUNE cmd
2026-01-29 03:15:34.494 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.28.20:5700/3) Recv SETFORMAT cmd
2026-01-29 03:15:34.494 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.28.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:15:34.494 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 03:15:34.494 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.28.20:5700/3) Recv NOMTXPOWER cmd
2026-01-29 03:15:34.494 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.28.20:5700/3) Recv SETFORMAT cmd
2026-01-29 03:15:34.495 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.28.20:5700/3) TRXD header version 1 -> 1
2026-01-29 03:15:34.497 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.28.20:5700) Recv RXTUNE cmd
2026-01-29 03:15:34.498 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETTSC
2026-01-29 03:15:34.498 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETTSC
2026-01-29 03:15:34.498 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETTSC
2026-01-29 03:15:34.498 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.28.20:5700) Recv TXTUNE cmd
2026-01-29 03:15:34.498 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETRXGAIN
2026-01-29 03:15:34.498 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETRXGAIN
2026-01-29 03:15:34.498 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETRXGAIN
2026-01-29 03:15:34.498 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETTSC
2026-01-29 03:15:34.498 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:15:34.498 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:15:34.498 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.28.20:5700) Recv NOMTXPOWER cmd
2026-01-29 03:15:34.498 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:15:34.498 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:15:34.498 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.28.20:5700) Recv POWERON CMD
2026-01-29 03:15:34.498 [INFO] ctrl_if_trx.py:109 (BTS@172.18.28.20:5700) Starting transceiver...
2026-01-29 03:15:34.498 [INFO] transceiver.py:243 Starting clock generator
2026-01-29 03:15:34.498 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-01-29 03:15:34.499 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:15:34.499 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:15:34.499 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:15:34.499 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETRXGAIN
2026-01-29 03:15:34.499 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:15:34.499 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:15:34.499 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:15:34.499 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:15:34.499 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:15:34.499 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:15:34.499 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:15:34.499 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:15:34.499 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:15:34.499 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:15:34.499 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:15:34.499 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:15:34.499 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:15:34.499 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:15:34.499 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:15:34.499 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:15:34.499 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:15:34.499 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:15:34.499 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:15:34.499 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:15:34.500 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:15:34.500 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:15:34.500 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:15:34.500 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:15:34.500 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:15:34.503 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-01-29 03:15:34.984 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-01-29 03:15:35.031 [DEBUG] fake_trx.py:278 (BTS@172.18.28.20:5700) Recv FAKE_TOA cmd
2026-01-29 03:15:35.034 [DEBUG] fake_trx.py:297 (BTS@172.18.28.20:5700) Recv FAKE_RSSI cmd
2026-01-29 03:15:35.034 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:15:35.036 [DEBUG] fake_trx.py:322 (BTS@172.18.28.20:5700) Recv FAKE_CI cmd
2026-01-29 03:15:35.060 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 03:15:35.060 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 03:15:35.060 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 03:15:35.065 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 03:15:35.066 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 03:15:35.066 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 03:15:35.067 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.28.22:6700) Recv POWERON CMD
2026-01-29 03:15:35.067 [INFO] ctrl_if_trx.py:109 (MS@172.18.28.22:6700) Starting transceiver...
2026-01-29 03:15:35.082 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:15:35.088 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 03:15:35.089 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 03:15:35.089 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 03:15:35.089 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 03:15:35.204 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:15:35.206 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 03:15:35.208 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 03:15:35.208 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 03:15:35.225 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 03:15:35.225 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 03:15:35.225 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 03:15:35.226 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 03:15:35.226 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 03:15:35.226 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 03:15:35.226 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.28.22:6700) Recv POWERON CMD
2026-01-29 03:15:35.226 [INFO] ctrl_if_trx.py:109 (MS@172.18.28.22:6700) Starting transceiver...
2026-01-29 03:15:35.269 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:15:35.274 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.28.22:6700) Recv SETFH cmd
2026-01-29 03:15:35.275 [INFO] transceiver.py:201 (MS@172.18.28.22:6700) Frequency hopping configured: hsn=5, maio=0, ma_len=4
2026-01-29 03:15:35.275 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 03:15:35.275 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 03:15:35.442 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:15:35.443 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 03:15:35.443 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 03:15:35.443 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 03:15:35.443 [INFO] transceiver.py:205 (MS@172.18.28.22:6700) Frequency hopping disabled
2026-01-29 03:15:35.461 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-01-29 03:15:35.462 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 03:15:35.462 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 03:15:35.463 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 03:15:35.464 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 03:15:35.464 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 03:15:35.464 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 03:15:35.464 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.28.22:6700) Recv POWERON CMD
2026-01-29 03:15:35.464 [INFO] ctrl_if_trx.py:109 (MS@172.18.28.22:6700) Starting transceiver...
2026-01-29 03:15:35.502 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:15:35.502 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 03:15:35.503 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:15:35.507 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:15:35.508 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:15:35.510 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 03:15:35.510 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 03:15:35.510 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 03:15:35.511 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 03:15:35.687 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:15:35.690 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 03:15:35.691 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 03:15:35.691 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 03:15:35.709 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 03:15:35.709 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 03:15:35.709 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 03:15:35.710 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 03:15:35.710 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 03:15:35.710 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 03:15:35.710 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.28.22:6700) Recv POWERON CMD
2026-01-29 03:15:35.710 [INFO] ctrl_if_trx.py:109 (MS@172.18.28.22:6700) Starting transceiver...
2026-01-29 03:15:35.745 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:15:35.750 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.28.22:6700) Recv SETFH cmd
2026-01-29 03:15:35.750 [INFO] transceiver.py:201 (MS@172.18.28.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2026-01-29 03:15:35.750 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 03:15:35.750 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 03:15:35.933 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-01-29 03:15:36.412 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-01-29 03:15:36.503 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 03:15:36.503 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:15:36.504 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:15:36.508 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:15:36.565 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:15:36.568 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 03:15:36.569 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 03:15:36.569 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 03:15:36.569 [INFO] transceiver.py:205 (MS@172.18.28.22:6700) Frequency hopping disabled
2026-01-29 03:15:36.577 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 03:15:36.577 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:15:36.577 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:15:36.577 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:15:36.578 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 03:15:36.578 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 03:15:36.578 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 03:15:36.578 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 03:15:36.578 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.28.20:5700) Recv POWEROFF cmd
2026-01-29 03:15:36.578 [INFO] ctrl_if_trx.py:117 (BTS@172.18.28.20:5700) Stopping transceiver...
2026-01-29 03:15:36.578 [INFO] transceiver.py:246 Stopping clock generator
2026-01-29 03:15:36.578 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=446 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:15:41.581 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.28.20:5700) Recv POWEROFF cmd
2026-01-29 03:15:41.581 [INFO] ctrl_if_trx.py:117 (BTS@172.18.28.20:5700) Stopping transceiver...
2026-01-29 03:15:41.583 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 03:15:41.583 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 03:15:41.584 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 03:15:41.584 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 03:15:41.587 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 03:15:41.587 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.28.20:5700) Recv SETFORMAT cmd
2026-01-29 03:15:41.587 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.28.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:15:41.587 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.28.20:5700) Recv SETFORMAT cmd
2026-01-29 03:15:41.587 [INFO] ctrl_if_trx.py:201 (BTS@172.18.28.20:5700) TRXD header version 1 -> 1
2026-01-29 03:15:41.589 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.28.20:5700/1) Recv RXTUNE cmd
2026-01-29 03:15:41.589 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.28.20:5700/1) Recv TXTUNE cmd
2026-01-29 03:15:41.589 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.28.20:5700/1) Recv SETFORMAT cmd
2026-01-29 03:15:41.590 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.28.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:15:41.590 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 03:15:41.590 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.28.20:5700/1) Recv NOMTXPOWER cmd
2026-01-29 03:15:41.591 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.28.20:5700/1) Recv SETFORMAT cmd
2026-01-29 03:15:41.591 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.28.20:5700/1) TRXD header version 1 -> 1
2026-01-29 03:15:41.591 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.28.20:5700/2) Recv RXTUNE cmd
2026-01-29 03:15:41.591 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.28.20:5700/2) Recv TXTUNE cmd
2026-01-29 03:15:41.591 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.28.20:5700/2) Recv SETFORMAT cmd
2026-01-29 03:15:41.591 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.28.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:15:41.592 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 03:15:41.592 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.28.20:5700/2) Recv NOMTXPOWER cmd
2026-01-29 03:15:41.592 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.28.20:5700/2) Recv SETFORMAT cmd
2026-01-29 03:15:41.592 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.28.20:5700/2) TRXD header version 1 -> 1
2026-01-29 03:15:41.593 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.28.20:5700/3) Recv RXTUNE cmd
2026-01-29 03:15:41.594 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.28.20:5700/3) Recv TXTUNE cmd
2026-01-29 03:15:41.594 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.28.20:5700/3) Recv SETFORMAT cmd
2026-01-29 03:15:41.594 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.28.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:15:41.594 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 03:15:41.594 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.28.20:5700/3) Recv NOMTXPOWER cmd
2026-01-29 03:15:41.594 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.28.20:5700/3) Recv SETFORMAT cmd
2026-01-29 03:15:41.594 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.28.20:5700/3) TRXD header version 1 -> 1
2026-01-29 03:15:41.597 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.28.20:5700) Recv RXTUNE cmd
2026-01-29 03:15:41.597 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETTSC
2026-01-29 03:15:41.597 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETTSC
2026-01-29 03:15:41.597 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETTSC
2026-01-29 03:15:41.597 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.28.20:5700) Recv TXTUNE cmd
2026-01-29 03:15:41.597 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETRXGAIN
2026-01-29 03:15:41.597 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETRXGAIN
2026-01-29 03:15:41.597 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETRXGAIN
2026-01-29 03:15:41.597 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETTSC
2026-01-29 03:15:41.597 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:15:41.597 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:15:41.597 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:15:41.597 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.28.20:5700) Recv NOMTXPOWER cmd
2026-01-29 03:15:41.597 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:15:41.597 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:15:41.597 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:15:41.597 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.28.20:5700) Recv POWERON CMD
2026-01-29 03:15:41.597 [INFO] ctrl_if_trx.py:109 (BTS@172.18.28.20:5700) Starting transceiver...
2026-01-29 03:15:41.597 [INFO] transceiver.py:243 Starting clock generator
2026-01-29 03:15:41.597 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-01-29 03:15:41.597 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:15:41.598 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:15:41.598 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:15:41.598 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETRXGAIN
2026-01-29 03:15:41.598 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:15:41.598 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:15:41.598 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:15:41.598 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:15:41.598 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:15:41.598 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:15:41.598 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:15:41.598 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:15:41.598 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:15:41.598 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:15:41.598 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:15:41.598 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:15:41.598 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:15:41.598 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:15:41.598 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:15:41.598 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:15:41.598 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:15:41.598 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:15:41.598 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:15:41.599 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:15:41.599 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:15:41.599 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:15:41.599 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:15:41.602 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-01-29 03:15:42.084 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-01-29 03:15:42.134 [DEBUG] fake_trx.py:278 (BTS@172.18.28.20:5700) Recv FAKE_TOA cmd
2026-01-29 03:15:42.137 [DEBUG] fake_trx.py:297 (BTS@172.18.28.20:5700) Recv FAKE_RSSI cmd
2026-01-29 03:15:42.139 [DEBUG] fake_trx.py:322 (BTS@172.18.28.20:5700) Recv FAKE_CI cmd
2026-01-29 03:15:42.139 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:15:42.157 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 03:15:42.158 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 03:15:42.158 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 03:15:42.162 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 03:15:42.162 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 03:15:42.162 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 03:15:42.162 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.28.22:6700) Recv POWERON CMD
2026-01-29 03:15:42.162 [INFO] ctrl_if_trx.py:109 (MS@172.18.28.22:6700) Starting transceiver...
2026-01-29 03:15:42.181 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:15:42.186 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 03:15:42.186 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 03:15:42.187 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 03:15:42.187 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 03:15:42.284 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:15:42.287 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 03:15:42.288 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 03:15:42.288 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 03:15:42.304 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 03:15:42.305 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 03:15:42.305 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 03:15:42.306 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 03:15:42.306 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 03:15:42.306 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 03:15:42.306 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.28.22:6700) Recv POWERON CMD
2026-01-29 03:15:42.306 [INFO] ctrl_if_trx.py:109 (MS@172.18.28.22:6700) Starting transceiver...
2026-01-29 03:15:42.318 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:15:42.320 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.28.22:6700) Recv SETFH cmd
2026-01-29 03:15:42.320 [INFO] transceiver.py:201 (MS@172.18.28.22:6700) Frequency hopping configured: hsn=5, maio=0, ma_len=4
2026-01-29 03:15:42.320 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 03:15:42.320 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 03:15:42.464 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:15:42.467 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 03:15:42.469 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 03:15:42.469 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 03:15:42.469 [INFO] transceiver.py:205 (MS@172.18.28.22:6700) Frequency hopping disabled
2026-01-29 03:15:42.489 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 03:15:42.489 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 03:15:42.489 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 03:15:42.490 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 03:15:42.490 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 03:15:42.490 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 03:15:42.490 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.28.22:6700) Recv POWERON CMD
2026-01-29 03:15:42.490 [INFO] ctrl_if_trx.py:109 (MS@172.18.28.22:6700) Starting transceiver...
2026-01-29 03:15:42.502 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:15:42.504 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 03:15:42.505 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 03:15:42.505 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 03:15:42.505 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 03:15:42.557 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-01-29 03:15:42.601 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 03:15:42.627 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:15:42.627 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:15:42.627 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:15:42.782 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:15:42.785 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 03:15:42.786 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 03:15:42.786 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 03:15:42.804 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 03:15:42.804 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 03:15:42.804 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 03:15:42.806 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 03:15:42.806 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 03:15:42.806 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 03:15:42.806 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.28.22:6700) Recv POWERON CMD
2026-01-29 03:15:42.806 [INFO] ctrl_if_trx.py:109 (MS@172.18.28.22:6700) Starting transceiver...
2026-01-29 03:15:42.841 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:15:42.846 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.28.22:6700) Recv SETFH cmd
2026-01-29 03:15:42.846 [INFO] transceiver.py:201 (MS@172.18.28.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2026-01-29 03:15:42.847 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 03:15:42.847 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 03:15:43.033 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-01-29 03:15:43.510 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-01-29 03:15:43.627 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 03:15:43.628 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:15:43.628 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:15:43.628 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:15:43.665 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:15:43.669 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 03:15:43.671 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 03:15:43.671 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 03:15:43.671 [INFO] transceiver.py:205 (MS@172.18.28.22:6700) Frequency hopping disabled
2026-01-29 03:15:43.679 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 03:15:43.679 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:15:43.680 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:15:43.680 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:15:43.682 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 03:15:43.682 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 03:15:43.682 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.28.20:5700) Recv POWEROFF cmd
2026-01-29 03:15:43.682 [INFO] ctrl_if_trx.py:117 (BTS@172.18.28.20:5700) Stopping transceiver...
2026-01-29 03:15:43.682 [INFO] transceiver.py:246 Stopping clock generator
2026-01-29 03:15:43.682 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 03:15:43.682 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 03:15:43.682 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=447 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:15:43.682 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=447 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:15:43.682 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=447 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:15:43.682 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=447 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:15:43.682 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=447 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:15:43.682 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=447 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:15:43.682 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=447 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:15:48.685 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.28.20:5700) Recv POWEROFF cmd
2026-01-29 03:15:48.685 [INFO] ctrl_if_trx.py:117 (BTS@172.18.28.20:5700) Stopping transceiver...
2026-01-29 03:15:48.685 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 03:15:48.685 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 03:15:48.685 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 03:15:48.685 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 03:15:48.692 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 03:15:48.694 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.28.20:5700) Recv SETFORMAT cmd
2026-01-29 03:15:48.694 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.28.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:15:48.694 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.28.20:5700) Recv SETFORMAT cmd
2026-01-29 03:15:48.695 [INFO] ctrl_if_trx.py:201 (BTS@172.18.28.20:5700) TRXD header version 1 -> 1
2026-01-29 03:15:48.698 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.28.20:5700/1) Recv RXTUNE cmd
2026-01-29 03:15:48.699 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.28.20:5700/1) Recv TXTUNE cmd
2026-01-29 03:15:48.699 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.28.20:5700/1) Recv SETFORMAT cmd
2026-01-29 03:15:48.699 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.28.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:15:48.700 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 03:15:48.700 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.28.20:5700/1) Recv NOMTXPOWER cmd
2026-01-29 03:15:48.701 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.28.20:5700/1) Recv SETFORMAT cmd
2026-01-29 03:15:48.701 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.28.20:5700/1) TRXD header version 1 -> 1
2026-01-29 03:15:48.702 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.28.20:5700/2) Recv RXTUNE cmd
2026-01-29 03:15:48.703 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.28.20:5700/2) Recv TXTUNE cmd
2026-01-29 03:15:48.703 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.28.20:5700/2) Recv SETFORMAT cmd
2026-01-29 03:15:48.703 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.28.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:15:48.703 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 03:15:48.704 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.28.20:5700/2) Recv NOMTXPOWER cmd
2026-01-29 03:15:48.704 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.28.20:5700/2) Recv SETFORMAT cmd
2026-01-29 03:15:48.704 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.28.20:5700/2) TRXD header version 1 -> 1
2026-01-29 03:15:48.706 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.28.20:5700/3) Recv RXTUNE cmd
2026-01-29 03:15:48.706 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.28.20:5700/3) Recv TXTUNE cmd
2026-01-29 03:15:48.706 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.28.20:5700/3) Recv SETFORMAT cmd
2026-01-29 03:15:48.706 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.28.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:15:48.706 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 03:15:48.707 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.28.20:5700/3) Recv NOMTXPOWER cmd
2026-01-29 03:15:48.707 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.28.20:5700/3) Recv SETFORMAT cmd
2026-01-29 03:15:48.707 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.28.20:5700/3) TRXD header version 1 -> 1
2026-01-29 03:15:48.710 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.28.20:5700) Recv RXTUNE cmd
2026-01-29 03:15:48.710 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETTSC
2026-01-29 03:15:48.710 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETTSC
2026-01-29 03:15:48.710 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETTSC
2026-01-29 03:15:48.710 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.28.20:5700) Recv TXTUNE cmd
2026-01-29 03:15:48.710 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETRXGAIN
2026-01-29 03:15:48.711 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETRXGAIN
2026-01-29 03:15:48.711 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETRXGAIN
2026-01-29 03:15:48.711 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETTSC
2026-01-29 03:15:48.711 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:15:48.711 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:15:48.711 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:15:48.711 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.28.20:5700) Recv NOMTXPOWER cmd
2026-01-29 03:15:48.711 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:15:48.711 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:15:48.711 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:15:48.711 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.28.20:5700) Recv POWERON CMD
2026-01-29 03:15:48.711 [INFO] ctrl_if_trx.py:109 (BTS@172.18.28.20:5700) Starting transceiver...
2026-01-29 03:15:48.711 [INFO] transceiver.py:243 Starting clock generator
2026-01-29 03:15:48.711 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-01-29 03:15:48.711 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:15:48.711 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:15:48.712 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:15:48.712 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETRXGAIN
2026-01-29 03:15:48.712 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:15:48.712 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:15:48.712 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:15:48.712 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:15:48.712 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:15:48.712 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:15:48.712 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:15:48.712 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:15:48.712 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:15:48.712 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:15:48.712 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:15:48.712 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:15:48.712 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:15:48.712 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:15:48.712 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:15:48.713 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:15:48.713 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:15:48.713 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:15:48.713 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:15:48.713 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:15:48.713 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:15:48.713 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:15:48.713 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:15:48.716 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-01-29 03:15:49.199 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-01-29 03:15:49.250 [DEBUG] fake_trx.py:278 (BTS@172.18.28.20:5700) Recv FAKE_TOA cmd
2026-01-29 03:15:49.252 [DEBUG] fake_trx.py:297 (BTS@172.18.28.20:5700) Recv FAKE_RSSI cmd
2026-01-29 03:15:49.254 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:15:49.254 [DEBUG] fake_trx.py:322 (BTS@172.18.28.20:5700) Recv FAKE_CI cmd
2026-01-29 03:15:49.279 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 03:15:49.279 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 03:15:49.280 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 03:15:49.283 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 03:15:49.283 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 03:15:49.284 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 03:15:49.284 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.28.22:6700) Recv POWERON CMD
2026-01-29 03:15:49.284 [INFO] ctrl_if_trx.py:109 (MS@172.18.28.22:6700) Starting transceiver...
2026-01-29 03:15:49.294 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:15:49.297 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 03:15:49.297 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 03:15:49.297 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 03:15:49.297 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 03:15:49.400 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:15:49.403 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 03:15:49.404 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 03:15:49.404 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 03:15:49.421 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 03:15:49.421 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 03:15:49.421 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 03:15:49.422 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 03:15:49.423 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 03:15:49.423 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 03:15:49.423 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.28.22:6700) Recv POWERON CMD
2026-01-29 03:15:49.423 [INFO] ctrl_if_trx.py:109 (MS@172.18.28.22:6700) Starting transceiver...
2026-01-29 03:15:49.432 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:15:49.434 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.28.22:6700) Recv SETFH cmd
2026-01-29 03:15:49.434 [INFO] transceiver.py:201 (MS@172.18.28.22:6700) Frequency hopping configured: hsn=5, maio=0, ma_len=4
2026-01-29 03:15:49.434 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 03:15:49.434 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 03:15:49.578 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:15:49.581 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 03:15:49.583 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 03:15:49.583 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 03:15:49.583 [INFO] transceiver.py:205 (MS@172.18.28.22:6700) Frequency hopping disabled
2026-01-29 03:15:49.600 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 03:15:49.600 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 03:15:49.600 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 03:15:49.601 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 03:15:49.601 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 03:15:49.601 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 03:15:49.601 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.28.22:6700) Recv POWERON CMD
2026-01-29 03:15:49.601 [INFO] ctrl_if_trx.py:109 (MS@172.18.28.22:6700) Starting transceiver...
2026-01-29 03:15:49.618 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:15:49.620 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 03:15:49.621 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 03:15:49.621 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 03:15:49.621 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 03:15:49.671 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-01-29 03:15:49.716 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 03:15:49.717 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:15:49.719 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:15:49.725 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:15:49.897 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:15:49.899 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 03:15:49.900 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 03:15:49.900 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 03:15:49.914 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 03:15:49.914 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 03:15:49.914 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 03:15:49.915 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 03:15:49.915 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 03:15:49.915 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 03:15:49.915 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.28.22:6700) Recv POWERON CMD
2026-01-29 03:15:49.915 [INFO] ctrl_if_trx.py:109 (MS@172.18.28.22:6700) Starting transceiver...
2026-01-29 03:15:49.951 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:15:49.953 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.28.22:6700) Recv SETFH cmd
2026-01-29 03:15:49.953 [INFO] transceiver.py:201 (MS@172.18.28.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2026-01-29 03:15:49.953 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 03:15:49.953 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 03:15:50.145 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-01-29 03:15:50.618 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-01-29 03:15:50.718 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:15:50.718 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 03:15:50.719 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:15:50.727 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:15:50.772 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:15:50.774 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 03:15:50.776 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 03:15:50.776 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 03:15:50.776 [INFO] transceiver.py:205 (MS@172.18.28.22:6700) Frequency hopping disabled
2026-01-29 03:15:50.781 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 03:15:50.781 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:15:50.781 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:15:50.781 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:15:50.782 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 03:15:50.782 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 03:15:50.782 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 03:15:50.782 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 03:15:50.782 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.28.20:5700) Recv POWEROFF cmd
2026-01-29 03:15:50.782 [INFO] ctrl_if_trx.py:117 (BTS@172.18.28.20:5700) Stopping transceiver...
2026-01-29 03:15:50.782 [INFO] transceiver.py:246 Stopping clock generator
2026-01-29 03:15:55.785 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.28.20:5700) Recv POWEROFF cmd
2026-01-29 03:15:55.785 [INFO] ctrl_if_trx.py:117 (BTS@172.18.28.20:5700) Stopping transceiver...
2026-01-29 03:15:55.786 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 03:15:55.788 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 03:15:55.789 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 03:15:55.789 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 03:15:55.794 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 03:15:55.794 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.28.20:5700) Recv SETFORMAT cmd
2026-01-29 03:15:55.795 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.28.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:15:55.795 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.28.20:5700) Recv SETFORMAT cmd
2026-01-29 03:15:55.795 [INFO] ctrl_if_trx.py:201 (BTS@172.18.28.20:5700) TRXD header version 1 -> 1
2026-01-29 03:15:55.798 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.28.20:5700/1) Recv RXTUNE cmd
2026-01-29 03:15:55.798 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.28.20:5700/1) Recv TXTUNE cmd
2026-01-29 03:15:55.799 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.28.20:5700/1) Recv SETFORMAT cmd
2026-01-29 03:15:55.799 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.28.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:15:55.799 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 03:15:55.800 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.28.20:5700/1) Recv NOMTXPOWER cmd
2026-01-29 03:15:55.800 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.28.20:5700/1) Recv SETFORMAT cmd
2026-01-29 03:15:55.800 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.28.20:5700/1) TRXD header version 1 -> 1
2026-01-29 03:15:55.801 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.28.20:5700/2) Recv RXTUNE cmd
2026-01-29 03:15:55.801 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.28.20:5700/2) Recv TXTUNE cmd
2026-01-29 03:15:55.801 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.28.20:5700/2) Recv SETFORMAT cmd
2026-01-29 03:15:55.801 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.28.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:15:55.801 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 03:15:55.801 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.28.20:5700/2) Recv NOMTXPOWER cmd
2026-01-29 03:15:55.801 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.28.20:5700/2) Recv SETFORMAT cmd
2026-01-29 03:15:55.801 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.28.20:5700/2) TRXD header version 1 -> 1
2026-01-29 03:15:55.804 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.28.20:5700/3) Recv RXTUNE cmd
2026-01-29 03:15:55.804 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.28.20:5700/3) Recv TXTUNE cmd
2026-01-29 03:15:55.805 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.28.20:5700/3) Recv SETFORMAT cmd
2026-01-29 03:15:55.805 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.28.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:15:55.805 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.28.20:5700/3) Recv NOMTXPOWER cmd
2026-01-29 03:15:55.805 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.28.20:5700/3) Recv SETFORMAT cmd
2026-01-29 03:15:55.805 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.28.20:5700/3) TRXD header version 1 -> 1
2026-01-29 03:15:55.805 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 03:15:55.809 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.28.20:5700) Recv RXTUNE cmd
2026-01-29 03:15:55.809 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETTSC
2026-01-29 03:15:55.809 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETTSC
2026-01-29 03:15:55.809 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETTSC
2026-01-29 03:15:55.809 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.28.20:5700) Recv TXTUNE cmd
2026-01-29 03:15:55.809 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETRXGAIN
2026-01-29 03:15:55.809 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETRXGAIN
2026-01-29 03:15:55.810 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETRXGAIN
2026-01-29 03:15:55.810 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETTSC
2026-01-29 03:15:55.810 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:15:55.810 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:15:55.810 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.28.20:5700) Recv NOMTXPOWER cmd
2026-01-29 03:15:55.810 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:15:55.810 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:15:55.810 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.28.20:5700) Recv POWERON CMD
2026-01-29 03:15:55.810 [INFO] ctrl_if_trx.py:109 (BTS@172.18.28.20:5700) Starting transceiver...
2026-01-29 03:15:55.810 [INFO] transceiver.py:243 Starting clock generator
2026-01-29 03:15:55.810 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-01-29 03:15:55.810 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:15:55.810 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:15:55.810 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:15:55.810 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETRXGAIN
2026-01-29 03:15:55.810 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:15:55.810 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:15:55.810 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:15:55.810 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:15:55.810 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:15:55.810 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:15:55.810 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:15:55.810 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:15:55.810 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:15:55.810 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:15:55.810 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:15:55.810 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:15:55.810 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:15:55.810 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:15:55.810 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:15:55.810 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:15:55.810 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:15:55.810 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:15:55.810 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:15:55.810 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:15:55.811 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:15:55.811 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:15:55.811 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:15:55.811 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:15:55.811 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:15:55.815 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-01-29 03:15:56.292 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-01-29 03:15:56.341 [DEBUG] fake_trx.py:278 (BTS@172.18.28.20:5700) Recv FAKE_TOA cmd
2026-01-29 03:15:56.342 [DEBUG] fake_trx.py:297 (BTS@172.18.28.20:5700) Recv FAKE_RSSI cmd
2026-01-29 03:15:56.343 [DEBUG] fake_trx.py:322 (BTS@172.18.28.20:5700) Recv FAKE_CI cmd
2026-01-29 03:15:56.344 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:15:56.359 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 03:15:56.359 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 03:15:56.359 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 03:15:56.365 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 03:15:56.365 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 03:15:56.365 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 03:15:56.365 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.28.22:6700) Recv POWERON CMD
2026-01-29 03:15:56.365 [INFO] ctrl_if_trx.py:109 (MS@172.18.28.22:6700) Starting transceiver...
2026-01-29 03:15:56.389 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:15:56.395 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 03:15:56.395 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 03:15:56.396 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 03:15:56.396 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 03:15:56.707 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:15:56.709 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 03:15:56.711 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 03:15:56.711 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 03:15:56.728 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 03:15:56.728 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 03:15:56.728 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 03:15:56.730 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 03:15:56.730 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 03:15:56.730 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 03:15:56.730 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.28.22:6700) Recv POWERON CMD
2026-01-29 03:15:56.730 [INFO] ctrl_if_trx.py:109 (MS@172.18.28.22:6700) Starting transceiver...
2026-01-29 03:15:56.762 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-01-29 03:15:56.765 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:15:56.770 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.28.22:6700) Recv SETFH cmd
2026-01-29 03:15:56.771 [INFO] transceiver.py:201 (MS@172.18.28.22:6700) Frequency hopping configured: hsn=5, maio=0, ma_len=4
2026-01-29 03:15:56.771 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 03:15:56.771 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 03:15:56.813 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:15:56.813 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 03:15:56.814 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:15:56.816 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:15:57.232 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-01-29 03:15:57.243 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:15:57.246 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 03:15:57.247 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 03:15:57.248 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 03:15:57.248 [INFO] transceiver.py:205 (MS@172.18.28.22:6700) Frequency hopping disabled
2026-01-29 03:15:57.267 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 03:15:57.267 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 03:15:57.267 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 03:15:57.269 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 03:15:57.269 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 03:15:57.269 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 03:15:57.269 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.28.22:6700) Recv POWERON CMD
2026-01-29 03:15:57.269 [INFO] ctrl_if_trx.py:109 (MS@172.18.28.22:6700) Starting transceiver...
2026-01-29 03:15:57.273 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:15:57.274 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 03:15:57.274 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 03:15:57.274 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 03:15:57.274 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 03:15:57.708 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-01-29 03:15:57.814 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:15:57.814 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 03:15:57.814 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:15:57.818 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:15:58.186 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-01-29 03:15:58.342 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:15:58.345 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 03:15:58.346 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 03:15:58.346 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 03:15:58.363 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 03:15:58.363 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 03:15:58.363 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 03:15:58.365 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 03:15:58.365 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 03:15:58.365 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 03:15:58.365 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.28.22:6700) Recv POWERON CMD
2026-01-29 03:15:58.365 [INFO] ctrl_if_trx.py:109 (MS@172.18.28.22:6700) Starting transceiver...
2026-01-29 03:15:58.368 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:15:58.369 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.28.22:6700) Recv SETFH cmd
2026-01-29 03:15:58.369 [INFO] transceiver.py:201 (MS@172.18.28.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2026-01-29 03:15:58.369 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 03:15:58.369 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 03:15:58.658 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-01-29 03:15:58.815 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 03:15:58.815 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:15:58.815 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:15:58.819 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:15:59.137 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-01-29 03:15:59.612 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-01-29 03:15:59.816 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 03:15:59.816 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:15:59.816 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:15:59.819 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:16:00.088 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-01-29 03:16:00.406 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:16:00.410 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 03:16:00.412 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 03:16:00.412 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 03:16:00.412 [INFO] transceiver.py:205 (MS@172.18.28.22:6700) Frequency hopping disabled
2026-01-29 03:16:00.420 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 03:16:00.421 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:16:00.421 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:16:00.421 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:16:00.423 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 03:16:00.423 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 03:16:00.423 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 03:16:00.423 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.28.20:5700) Recv POWEROFF cmd
2026-01-29 03:16:00.423 [INFO] ctrl_if_trx.py:117 (BTS@172.18.28.20:5700) Stopping transceiver...
2026-01-29 03:16:00.423 [INFO] transceiver.py:246 Stopping clock generator
2026-01-29 03:16:00.424 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 03:16:00.424 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=992 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:16:00.424 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=992 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:16:00.424 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=992 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:16:00.424 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=992 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:16:00.424 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=992 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:16:00.424 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=992 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:16:00.424 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=992 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:16:00.424 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=992 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:16:05.424 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.28.20:5700) Recv POWEROFF cmd
2026-01-29 03:16:05.424 [INFO] ctrl_if_trx.py:117 (BTS@172.18.28.20:5700) Stopping transceiver...
2026-01-29 03:16:05.425 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 03:16:05.430 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 03:16:05.430 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 03:16:05.431 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 03:16:05.444 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 03:16:05.445 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.28.20:5700) Recv SETFORMAT cmd
2026-01-29 03:16:05.445 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.28.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:16:05.446 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.28.20:5700) Recv SETFORMAT cmd
2026-01-29 03:16:05.446 [INFO] ctrl_if_trx.py:201 (BTS@172.18.28.20:5700) TRXD header version 1 -> 1
2026-01-29 03:16:05.449 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.28.20:5700/1) Recv RXTUNE cmd
2026-01-29 03:16:05.449 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.28.20:5700/1) Recv TXTUNE cmd
2026-01-29 03:16:05.449 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.28.20:5700/1) Recv SETFORMAT cmd
2026-01-29 03:16:05.449 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.28.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:16:05.449 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 03:16:05.450 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.28.20:5700/1) Recv NOMTXPOWER cmd
2026-01-29 03:16:05.450 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.28.20:5700/1) Recv SETFORMAT cmd
2026-01-29 03:16:05.450 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.28.20:5700/1) TRXD header version 1 -> 1
2026-01-29 03:16:05.452 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.28.20:5700/2) Recv RXTUNE cmd
2026-01-29 03:16:05.452 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.28.20:5700/2) Recv TXTUNE cmd
2026-01-29 03:16:05.452 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.28.20:5700/2) Recv SETFORMAT cmd
2026-01-29 03:16:05.452 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.28.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:16:05.453 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 03:16:05.453 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.28.20:5700/2) Recv NOMTXPOWER cmd
2026-01-29 03:16:05.453 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.28.20:5700/2) Recv SETFORMAT cmd
2026-01-29 03:16:05.453 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.28.20:5700/2) TRXD header version 1 -> 1
2026-01-29 03:16:05.456 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.28.20:5700/3) Recv RXTUNE cmd
2026-01-29 03:16:05.456 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.28.20:5700/3) Recv TXTUNE cmd
2026-01-29 03:16:05.456 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.28.20:5700/3) Recv SETFORMAT cmd
2026-01-29 03:16:05.456 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.28.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:16:05.456 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 03:16:05.456 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.28.20:5700/3) Recv NOMTXPOWER cmd
2026-01-29 03:16:05.456 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.28.20:5700/3) Recv SETFORMAT cmd
2026-01-29 03:16:05.456 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.28.20:5700/3) TRXD header version 1 -> 1
2026-01-29 03:16:05.459 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.28.20:5700) Recv RXTUNE cmd
2026-01-29 03:16:05.459 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETTSC
2026-01-29 03:16:05.459 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETTSC
2026-01-29 03:16:05.459 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETTSC
2026-01-29 03:16:05.459 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.28.20:5700) Recv TXTUNE cmd
2026-01-29 03:16:05.460 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETRXGAIN
2026-01-29 03:16:05.460 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETRXGAIN
2026-01-29 03:16:05.460 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETRXGAIN
2026-01-29 03:16:05.460 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETTSC
2026-01-29 03:16:05.460 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:16:05.460 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:16:05.460 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.28.20:5700) Recv NOMTXPOWER cmd
2026-01-29 03:16:05.460 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:16:05.460 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:16:05.460 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:16:05.460 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.28.20:5700) Recv POWERON CMD
2026-01-29 03:16:05.460 [INFO] ctrl_if_trx.py:109 (BTS@172.18.28.20:5700) Starting transceiver...
2026-01-29 03:16:05.460 [INFO] transceiver.py:243 Starting clock generator
2026-01-29 03:16:05.460 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-01-29 03:16:05.460 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:16:05.460 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:16:05.460 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:16:05.460 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETRXGAIN
2026-01-29 03:16:05.461 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:16:05.461 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:16:05.461 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:16:05.461 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:16:05.461 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:16:05.461 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:16:05.461 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:16:05.461 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:16:05.461 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:16:05.461 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:16:05.461 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:16:05.461 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:16:05.461 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:16:05.461 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:16:05.461 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:16:05.461 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:16:05.461 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:16:05.461 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:16:05.461 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:16:05.461 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:16:05.461 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:16:05.461 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:16:05.461 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:16:05.461 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:16:05.465 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-01-29 03:16:05.939 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-01-29 03:16:05.992 [DEBUG] fake_trx.py:278 (BTS@172.18.28.20:5700) Recv FAKE_TOA cmd
2026-01-29 03:16:05.994 [DEBUG] fake_trx.py:297 (BTS@172.18.28.20:5700) Recv FAKE_RSSI cmd
2026-01-29 03:16:05.995 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:16:05.996 [DEBUG] fake_trx.py:322 (BTS@172.18.28.20:5700) Recv FAKE_CI cmd
2026-01-29 03:16:06.016 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 03:16:06.016 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 03:16:06.016 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 03:16:06.020 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 03:16:06.021 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 03:16:06.021 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 03:16:06.021 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.28.22:6700) Recv POWERON CMD
2026-01-29 03:16:06.021 [INFO] ctrl_if_trx.py:109 (MS@172.18.28.22:6700) Starting transceiver...
2026-01-29 03:16:06.033 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:16:06.038 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 03:16:06.038 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 03:16:06.038 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 03:16:06.038 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 03:16:06.354 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:16:06.356 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 03:16:06.358 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 03:16:06.358 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 03:16:06.378 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 03:16:06.378 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 03:16:06.378 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 03:16:06.380 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 03:16:06.380 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 03:16:06.380 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 03:16:06.380 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.28.22:6700) Recv POWERON CMD
2026-01-29 03:16:06.380 [INFO] ctrl_if_trx.py:109 (MS@172.18.28.22:6700) Starting transceiver...
2026-01-29 03:16:06.413 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:16:06.414 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-01-29 03:16:06.419 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.28.22:6700) Recv SETFH cmd
2026-01-29 03:16:06.419 [INFO] transceiver.py:201 (MS@172.18.28.22:6700) Frequency hopping configured: hsn=5, maio=0, ma_len=4
2026-01-29 03:16:06.419 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 03:16:06.419 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 03:16:06.464 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:16:06.464 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 03:16:06.465 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:16:06.469 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:16:06.885 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-01-29 03:16:06.895 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:16:06.898 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 03:16:06.899 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 03:16:06.899 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 03:16:06.899 [INFO] transceiver.py:205 (MS@172.18.28.22:6700) Frequency hopping disabled
2026-01-29 03:16:06.918 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 03:16:06.918 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 03:16:06.918 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 03:16:06.920 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 03:16:06.920 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 03:16:06.920 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 03:16:06.920 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.28.22:6700) Recv POWERON CMD
2026-01-29 03:16:06.920 [INFO] ctrl_if_trx.py:109 (MS@172.18.28.22:6700) Starting transceiver...
2026-01-29 03:16:06.924 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:16:06.925 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 03:16:06.925 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 03:16:06.925 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 03:16:06.925 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 03:16:07.363 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-01-29 03:16:07.464 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 03:16:07.465 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:16:07.466 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:16:07.470 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:16:07.840 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-01-29 03:16:07.997 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:16:08.000 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 03:16:08.001 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 03:16:08.001 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 03:16:08.019 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 03:16:08.019 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 03:16:08.019 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 03:16:08.021 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 03:16:08.021 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 03:16:08.021 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 03:16:08.021 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.28.22:6700) Recv POWERON CMD
2026-01-29 03:16:08.021 [INFO] ctrl_if_trx.py:109 (MS@172.18.28.22:6700) Starting transceiver...
2026-01-29 03:16:08.090 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:16:08.092 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.28.22:6700) Recv SETFH cmd
2026-01-29 03:16:08.092 [INFO] transceiver.py:201 (MS@172.18.28.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2026-01-29 03:16:08.093 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 03:16:08.093 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 03:16:08.317 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-01-29 03:16:08.465 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 03:16:08.466 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:16:08.466 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:16:08.470 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:16:08.795 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-01-29 03:16:09.274 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-01-29 03:16:09.467 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:16:09.467 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:16:09.467 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 03:16:09.471 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:16:09.752 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-01-29 03:16:10.070 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:16:10.073 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 03:16:10.075 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 03:16:10.075 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 03:16:10.075 [INFO] transceiver.py:205 (MS@172.18.28.22:6700) Frequency hopping disabled
2026-01-29 03:16:10.082 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 03:16:10.082 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:16:10.082 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:16:10.082 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:16:10.083 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 03:16:10.083 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 03:16:10.083 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 03:16:10.083 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 03:16:10.083 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.28.20:5700) Recv POWEROFF cmd
2026-01-29 03:16:10.083 [INFO] ctrl_if_trx.py:117 (BTS@172.18.28.20:5700) Stopping transceiver...
2026-01-29 03:16:10.083 [INFO] transceiver.py:246 Stopping clock generator
2026-01-29 03:16:15.086 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.28.20:5700) Recv POWEROFF cmd
2026-01-29 03:16:15.086 [INFO] ctrl_if_trx.py:117 (BTS@172.18.28.20:5700) Stopping transceiver...
2026-01-29 03:16:15.087 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 03:16:15.089 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 03:16:15.089 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 03:16:15.089 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 03:16:15.093 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 03:16:15.093 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.28.20:5700) Recv SETFORMAT cmd
2026-01-29 03:16:15.093 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.28.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:16:15.093 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.28.20:5700) Recv SETFORMAT cmd
2026-01-29 03:16:15.093 [INFO] ctrl_if_trx.py:201 (BTS@172.18.28.20:5700) TRXD header version 1 -> 1
2026-01-29 03:16:15.095 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.28.20:5700/1) Recv RXTUNE cmd
2026-01-29 03:16:15.095 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.28.20:5700/1) Recv TXTUNE cmd
2026-01-29 03:16:15.095 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.28.20:5700/1) Recv SETFORMAT cmd
2026-01-29 03:16:15.095 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.28.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:16:15.095 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 03:16:15.095 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.28.20:5700/1) Recv NOMTXPOWER cmd
2026-01-29 03:16:15.095 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.28.20:5700/1) Recv SETFORMAT cmd
2026-01-29 03:16:15.095 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.28.20:5700/1) TRXD header version 1 -> 1
2026-01-29 03:16:15.097 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.28.20:5700/2) Recv RXTUNE cmd
2026-01-29 03:16:15.097 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.28.20:5700/2) Recv TXTUNE cmd
2026-01-29 03:16:15.097 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.28.20:5700/2) Recv SETFORMAT cmd
2026-01-29 03:16:15.098 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.28.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:16:15.098 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 03:16:15.098 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.28.20:5700/2) Recv NOMTXPOWER cmd
2026-01-29 03:16:15.098 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.28.20:5700/2) Recv SETFORMAT cmd
2026-01-29 03:16:15.098 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.28.20:5700/2) TRXD header version 1 -> 1
2026-01-29 03:16:15.100 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.28.20:5700/3) Recv RXTUNE cmd
2026-01-29 03:16:15.100 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.28.20:5700/3) Recv TXTUNE cmd
2026-01-29 03:16:15.100 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.28.20:5700/3) Recv SETFORMAT cmd
2026-01-29 03:16:15.100 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.28.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:16:15.100 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 03:16:15.100 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.28.20:5700/3) Recv NOMTXPOWER cmd
2026-01-29 03:16:15.100 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.28.20:5700/3) Recv SETFORMAT cmd
2026-01-29 03:16:15.100 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.28.20:5700/3) TRXD header version 1 -> 1
2026-01-29 03:16:15.103 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.28.20:5700) Recv RXTUNE cmd
2026-01-29 03:16:15.103 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETTSC
2026-01-29 03:16:15.103 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETTSC
2026-01-29 03:16:15.103 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETTSC
2026-01-29 03:16:15.103 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.28.20:5700) Recv TXTUNE cmd
2026-01-29 03:16:15.103 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETRXGAIN
2026-01-29 03:16:15.103 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETRXGAIN
2026-01-29 03:16:15.103 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETRXGAIN
2026-01-29 03:16:15.103 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETTSC
2026-01-29 03:16:15.103 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:16:15.103 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:16:15.103 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:16:15.103 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.28.20:5700) Recv NOMTXPOWER cmd
2026-01-29 03:16:15.103 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:16:15.103 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:16:15.103 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:16:15.103 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.28.20:5700) Recv POWERON CMD
2026-01-29 03:16:15.104 [INFO] ctrl_if_trx.py:109 (BTS@172.18.28.20:5700) Starting transceiver...
2026-01-29 03:16:15.104 [INFO] transceiver.py:243 Starting clock generator
2026-01-29 03:16:15.104 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-01-29 03:16:15.104 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:16:15.104 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:16:15.104 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:16:15.104 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETRXGAIN
2026-01-29 03:16:15.104 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:16:15.104 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:16:15.104 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:16:15.104 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:16:15.104 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:16:15.104 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:16:15.104 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:16:15.104 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:16:15.104 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:16:15.104 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:16:15.105 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:16:15.105 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:16:15.105 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:16:15.105 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:16:15.105 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:16:15.105 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:16:15.105 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:16:15.105 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:16:15.105 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:16:15.105 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:16:15.105 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:16:15.105 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:16:15.105 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:16:15.108 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-01-29 03:16:15.589 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-01-29 03:16:15.638 [DEBUG] fake_trx.py:278 (BTS@172.18.28.20:5700) Recv FAKE_TOA cmd
2026-01-29 03:16:15.640 [DEBUG] fake_trx.py:297 (BTS@172.18.28.20:5700) Recv FAKE_RSSI cmd
2026-01-29 03:16:15.642 [DEBUG] fake_trx.py:322 (BTS@172.18.28.20:5700) Recv FAKE_CI cmd
2026-01-29 03:16:15.642 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:16:15.665 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 03:16:15.665 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 03:16:15.666 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 03:16:15.673 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 03:16:15.673 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 03:16:15.673 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 03:16:15.673 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.28.22:6700) Recv POWERON CMD
2026-01-29 03:16:15.673 [INFO] ctrl_if_trx.py:109 (MS@172.18.28.22:6700) Starting transceiver...
2026-01-29 03:16:15.684 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:16:15.689 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 03:16:15.689 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 03:16:15.689 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 03:16:15.689 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 03:16:16.003 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:16:16.006 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 03:16:16.008 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 03:16:16.008 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 03:16:16.026 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 03:16:16.026 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 03:16:16.026 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 03:16:16.028 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 03:16:16.028 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 03:16:16.028 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 03:16:16.028 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.28.22:6700) Recv POWERON CMD
2026-01-29 03:16:16.028 [INFO] ctrl_if_trx.py:109 (MS@172.18.28.22:6700) Starting transceiver...
2026-01-29 03:16:16.059 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-01-29 03:16:16.063 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:16:16.068 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.28.22:6700) Recv SETFH cmd
2026-01-29 03:16:16.068 [INFO] transceiver.py:201 (MS@172.18.28.22:6700) Frequency hopping configured: hsn=5, maio=0, ma_len=4
2026-01-29 03:16:16.068 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 03:16:16.068 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 03:16:16.108 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:16:16.109 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 03:16:16.110 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:16:16.114 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:16:16.528 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-01-29 03:16:16.539 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:16:16.541 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 03:16:16.543 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 03:16:16.543 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 03:16:16.543 [INFO] transceiver.py:205 (MS@172.18.28.22:6700) Frequency hopping disabled
2026-01-29 03:16:16.563 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 03:16:16.563 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 03:16:16.563 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 03:16:16.565 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 03:16:16.565 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 03:16:16.565 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 03:16:16.565 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.28.22:6700) Recv POWERON CMD
2026-01-29 03:16:16.565 [INFO] ctrl_if_trx.py:109 (MS@172.18.28.22:6700) Starting transceiver...
2026-01-29 03:16:16.569 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:16:16.570 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 03:16:16.570 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 03:16:16.570 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 03:16:16.571 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 03:16:17.002 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-01-29 03:16:17.109 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 03:16:17.109 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:16:17.111 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:16:17.115 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:16:17.479 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-01-29 03:16:17.635 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:16:17.638 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 03:16:17.639 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 03:16:17.639 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 03:16:17.654 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 03:16:17.654 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 03:16:17.654 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 03:16:17.656 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 03:16:17.656 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 03:16:17.657 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 03:16:17.657 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.28.22:6700) Recv POWERON CMD
2026-01-29 03:16:17.657 [INFO] ctrl_if_trx.py:109 (MS@172.18.28.22:6700) Starting transceiver...
2026-01-29 03:16:17.660 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:16:17.661 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.28.22:6700) Recv SETFH cmd
2026-01-29 03:16:17.661 [INFO] transceiver.py:201 (MS@172.18.28.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2026-01-29 03:16:17.661 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 03:16:17.661 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 03:16:17.956 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-01-29 03:16:18.122 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:16:18.122 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:16:18.123 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 03:16:18.123 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:16:18.435 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-01-29 03:16:18.913 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-01-29 03:16:19.124 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:16:19.124 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 03:16:19.124 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:16:19.124 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:16:19.392 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-01-29 03:16:19.709 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:16:19.712 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 03:16:19.714 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 03:16:19.714 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 03:16:19.714 [INFO] transceiver.py:205 (MS@172.18.28.22:6700) Frequency hopping disabled
2026-01-29 03:16:19.721 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 03:16:19.721 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:16:19.721 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:16:19.721 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:16:19.721 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 03:16:19.721 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 03:16:19.721 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 03:16:19.721 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 03:16:19.721 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.28.20:5700) Recv POWEROFF cmd
2026-01-29 03:16:19.721 [INFO] ctrl_if_trx.py:117 (BTS@172.18.28.20:5700) Stopping transceiver...
2026-01-29 03:16:19.721 [INFO] transceiver.py:246 Stopping clock generator
2026-01-29 03:16:19.722 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=991 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:16:19.722 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=991 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:16:19.722 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=991 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:16:19.722 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=991 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:16:19.722 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=991 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:16:19.722 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=991 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:16:19.722 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=991 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:16:24.725 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.28.20:5700) Recv POWEROFF cmd
2026-01-29 03:16:24.725 [INFO] ctrl_if_trx.py:117 (BTS@172.18.28.20:5700) Stopping transceiver...
2026-01-29 03:16:24.727 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 03:16:24.728 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 03:16:24.728 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 03:16:24.728 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 03:16:24.738 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 03:16:24.739 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.28.20:5700) Recv SETFORMAT cmd
2026-01-29 03:16:24.739 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.28.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:16:24.740 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.28.20:5700) Recv SETFORMAT cmd
2026-01-29 03:16:24.740 [INFO] ctrl_if_trx.py:201 (BTS@172.18.28.20:5700) TRXD header version 1 -> 1
2026-01-29 03:16:24.743 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.28.20:5700/1) Recv RXTUNE cmd
2026-01-29 03:16:24.744 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.28.20:5700/1) Recv TXTUNE cmd
2026-01-29 03:16:24.744 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.28.20:5700/1) Recv SETFORMAT cmd
2026-01-29 03:16:24.744 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.28.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:16:24.745 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 03:16:24.745 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.28.20:5700/1) Recv NOMTXPOWER cmd
2026-01-29 03:16:24.745 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.28.20:5700/1) Recv SETFORMAT cmd
2026-01-29 03:16:24.745 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.28.20:5700/1) TRXD header version 1 -> 1
2026-01-29 03:16:24.747 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.28.20:5700/2) Recv RXTUNE cmd
2026-01-29 03:16:24.747 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.28.20:5700/2) Recv TXTUNE cmd
2026-01-29 03:16:24.747 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.28.20:5700/2) Recv SETFORMAT cmd
2026-01-29 03:16:24.747 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.28.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:16:24.747 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 03:16:24.748 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.28.20:5700/2) Recv NOMTXPOWER cmd
2026-01-29 03:16:24.748 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.28.20:5700/2) Recv SETFORMAT cmd
2026-01-29 03:16:24.748 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.28.20:5700/2) TRXD header version 1 -> 1
2026-01-29 03:16:24.751 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.28.20:5700/3) Recv RXTUNE cmd
2026-01-29 03:16:24.751 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.28.20:5700/3) Recv TXTUNE cmd
2026-01-29 03:16:24.751 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.28.20:5700/3) Recv SETFORMAT cmd
2026-01-29 03:16:24.751 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.28.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:16:24.751 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 03:16:24.751 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.28.20:5700/3) Recv NOMTXPOWER cmd
2026-01-29 03:16:24.751 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.28.20:5700/3) Recv SETFORMAT cmd
2026-01-29 03:16:24.752 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.28.20:5700/3) TRXD header version 1 -> 1
2026-01-29 03:16:24.756 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.28.20:5700) Recv RXTUNE cmd
2026-01-29 03:16:24.756 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETTSC
2026-01-29 03:16:24.756 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETTSC
2026-01-29 03:16:24.756 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETTSC
2026-01-29 03:16:24.756 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.28.20:5700) Recv TXTUNE cmd
2026-01-29 03:16:24.756 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETRXGAIN
2026-01-29 03:16:24.756 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETRXGAIN
2026-01-29 03:16:24.757 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETRXGAIN
2026-01-29 03:16:24.757 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETTSC
2026-01-29 03:16:24.757 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:16:24.757 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:16:24.757 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:16:24.757 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.28.20:5700) Recv NOMTXPOWER cmd
2026-01-29 03:16:24.757 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:16:24.757 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:16:24.757 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:16:24.757 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.28.20:5700) Recv POWERON CMD
2026-01-29 03:16:24.757 [INFO] ctrl_if_trx.py:109 (BTS@172.18.28.20:5700) Starting transceiver...
2026-01-29 03:16:24.757 [INFO] transceiver.py:243 Starting clock generator
2026-01-29 03:16:24.757 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-01-29 03:16:24.757 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:16:24.758 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:16:24.758 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:16:24.758 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETRXGAIN
2026-01-29 03:16:24.758 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:16:24.758 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:16:24.758 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:16:24.758 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:16:24.758 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:16:24.758 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:16:24.758 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:16:24.758 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:16:24.758 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:16:24.758 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:16:24.758 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:16:24.758 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:16:24.758 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:16:24.758 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:16:24.758 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:16:24.758 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:16:24.758 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:16:24.758 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:16:24.758 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:16:24.758 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:16:24.759 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:16:24.759 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:16:24.759 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:16:24.762 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-01-29 03:16:25.238 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-01-29 03:16:25.294 [DEBUG] fake_trx.py:278 (BTS@172.18.28.20:5700) Recv FAKE_TOA cmd
2026-01-29 03:16:25.296 [DEBUG] fake_trx.py:297 (BTS@172.18.28.20:5700) Recv FAKE_RSSI cmd
2026-01-29 03:16:25.298 [DEBUG] fake_trx.py:322 (BTS@172.18.28.20:5700) Recv FAKE_CI cmd
2026-01-29 03:16:25.299 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:16:25.320 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 03:16:25.320 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 03:16:25.321 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 03:16:25.326 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 03:16:25.326 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 03:16:25.326 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 03:16:25.326 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.28.22:6700) Recv POWERON CMD
2026-01-29 03:16:25.326 [INFO] ctrl_if_trx.py:109 (MS@172.18.28.22:6700) Starting transceiver...
2026-01-29 03:16:25.381 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:16:25.386 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 03:16:25.386 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 03:16:25.387 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 03:16:25.387 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 03:16:25.694 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:16:25.696 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 03:16:25.698 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 03:16:25.698 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 03:16:25.711 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-01-29 03:16:25.717 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 03:16:25.717 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 03:16:25.717 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 03:16:25.719 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 03:16:25.719 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 03:16:25.719 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 03:16:25.719 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.28.22:6700) Recv POWERON CMD
2026-01-29 03:16:25.719 [INFO] ctrl_if_trx.py:109 (MS@172.18.28.22:6700) Starting transceiver...
2026-01-29 03:16:25.758 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:16:25.762 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 03:16:25.763 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:16:25.764 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:16:25.765 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.28.22:6700) Recv SETFH cmd
2026-01-29 03:16:25.765 [INFO] transceiver.py:201 (MS@172.18.28.22:6700) Frequency hopping configured: hsn=5, maio=0, ma_len=4
2026-01-29 03:16:25.765 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 03:16:25.765 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 03:16:25.769 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:16:26.190 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-01-29 03:16:26.288 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:16:26.291 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 03:16:26.294 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 03:16:26.295 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 03:16:26.295 [INFO] transceiver.py:205 (MS@172.18.28.22:6700) Frequency hopping disabled
2026-01-29 03:16:26.316 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 03:16:26.316 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 03:16:26.317 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 03:16:26.319 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 03:16:26.319 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 03:16:26.319 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 03:16:26.319 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.28.22:6700) Recv POWERON CMD
2026-01-29 03:16:26.319 [INFO] ctrl_if_trx.py:109 (MS@172.18.28.22:6700) Starting transceiver...
2026-01-29 03:16:26.326 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:16:26.328 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 03:16:26.328 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 03:16:26.328 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 03:16:26.328 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 03:16:26.668 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-01-29 03:16:26.763 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 03:16:26.763 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:16:26.765 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:16:26.770 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:16:27.146 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-01-29 03:16:27.302 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:16:27.305 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 03:16:27.306 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 03:16:27.307 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 03:16:27.319 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 03:16:27.319 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 03:16:27.319 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 03:16:27.322 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 03:16:27.322 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 03:16:27.322 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 03:16:27.322 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.28.22:6700) Recv POWERON CMD
2026-01-29 03:16:27.322 [INFO] ctrl_if_trx.py:109 (MS@172.18.28.22:6700) Starting transceiver...
2026-01-29 03:16:27.328 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:16:27.329 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.28.22:6700) Recv SETFH cmd
2026-01-29 03:16:27.329 [INFO] transceiver.py:201 (MS@172.18.28.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2026-01-29 03:16:27.329 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 03:16:27.329 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 03:16:27.624 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-01-29 03:16:27.764 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 03:16:27.764 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:16:27.766 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:16:27.770 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:16:28.102 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-01-29 03:16:28.580 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-01-29 03:16:28.765 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:16:28.766 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 03:16:28.766 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:16:28.771 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:16:29.058 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-01-29 03:16:29.376 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:16:29.379 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 03:16:29.380 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 03:16:29.380 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 03:16:29.380 [INFO] transceiver.py:205 (MS@172.18.28.22:6700) Frequency hopping disabled
2026-01-29 03:16:29.385 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 03:16:29.385 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:16:29.385 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:16:29.385 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:16:29.386 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 03:16:29.386 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 03:16:29.386 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 03:16:29.386 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 03:16:29.386 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.28.20:5700) Recv POWEROFF cmd
2026-01-29 03:16:29.386 [INFO] ctrl_if_trx.py:117 (BTS@172.18.28.20:5700) Stopping transceiver...
2026-01-29 03:16:29.386 [INFO] transceiver.py:246 Stopping clock generator
2026-01-29 03:16:34.389 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.28.20:5700) Recv POWEROFF cmd
2026-01-29 03:16:34.389 [INFO] ctrl_if_trx.py:117 (BTS@172.18.28.20:5700) Stopping transceiver...
2026-01-29 03:16:34.393 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 03:16:34.393 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 03:16:34.393 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 03:16:34.393 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 03:16:34.401 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 03:16:34.403 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.28.20:5700) Recv SETFORMAT cmd
2026-01-29 03:16:34.403 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.28.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:16:34.403 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.28.20:5700) Recv SETFORMAT cmd
2026-01-29 03:16:34.403 [INFO] ctrl_if_trx.py:201 (BTS@172.18.28.20:5700) TRXD header version 1 -> 1
2026-01-29 03:16:34.406 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.28.20:5700/1) Recv RXTUNE cmd
2026-01-29 03:16:34.407 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.28.20:5700/1) Recv TXTUNE cmd
2026-01-29 03:16:34.407 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.28.20:5700/1) Recv SETFORMAT cmd
2026-01-29 03:16:34.407 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.28.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:16:34.408 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 03:16:34.408 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.28.20:5700/1) Recv NOMTXPOWER cmd
2026-01-29 03:16:34.409 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.28.20:5700/1) Recv SETFORMAT cmd
2026-01-29 03:16:34.409 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.28.20:5700/1) TRXD header version 1 -> 1
2026-01-29 03:16:34.410 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.28.20:5700/2) Recv RXTUNE cmd
2026-01-29 03:16:34.410 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.28.20:5700/2) Recv TXTUNE cmd
2026-01-29 03:16:34.410 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.28.20:5700/2) Recv SETFORMAT cmd
2026-01-29 03:16:34.410 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.28.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:16:34.410 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 03:16:34.410 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.28.20:5700/2) Recv NOMTXPOWER cmd
2026-01-29 03:16:34.410 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.28.20:5700/2) Recv SETFORMAT cmd
2026-01-29 03:16:34.410 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.28.20:5700/2) TRXD header version 1 -> 1
2026-01-29 03:16:34.412 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.28.20:5700/3) Recv RXTUNE cmd
2026-01-29 03:16:34.413 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.28.20:5700/3) Recv TXTUNE cmd
2026-01-29 03:16:34.413 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.28.20:5700/3) Recv SETFORMAT cmd
2026-01-29 03:16:34.413 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.28.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:16:34.413 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 03:16:34.413 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.28.20:5700/3) Recv NOMTXPOWER cmd
2026-01-29 03:16:34.413 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.28.20:5700/3) Recv SETFORMAT cmd
2026-01-29 03:16:34.413 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.28.20:5700/3) TRXD header version 1 -> 1
2026-01-29 03:16:34.416 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.28.20:5700) Recv RXTUNE cmd
2026-01-29 03:16:34.416 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETTSC
2026-01-29 03:16:34.416 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETTSC
2026-01-29 03:16:34.416 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETTSC
2026-01-29 03:16:34.416 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.28.20:5700) Recv TXTUNE cmd
2026-01-29 03:16:34.416 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETRXGAIN
2026-01-29 03:16:34.416 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETRXGAIN
2026-01-29 03:16:34.416 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETRXGAIN
2026-01-29 03:16:34.416 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETTSC
2026-01-29 03:16:34.417 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:16:34.417 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:16:34.417 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:16:34.417 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.28.20:5700) Recv NOMTXPOWER cmd
2026-01-29 03:16:34.417 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:16:34.417 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:16:34.417 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:16:34.417 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.28.20:5700) Recv POWERON CMD
2026-01-29 03:16:34.417 [INFO] ctrl_if_trx.py:109 (BTS@172.18.28.20:5700) Starting transceiver...
2026-01-29 03:16:34.417 [INFO] transceiver.py:243 Starting clock generator
2026-01-29 03:16:34.417 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-01-29 03:16:34.417 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:16:34.417 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:16:34.417 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:16:34.417 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETRXGAIN
2026-01-29 03:16:34.417 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:16:34.417 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:16:34.417 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:16:34.417 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:16:34.417 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:16:34.418 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:16:34.418 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:16:34.418 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:16:34.418 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:16:34.418 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:16:34.418 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:16:34.418 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:16:34.418 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:16:34.418 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:16:34.418 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:16:34.418 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:16:34.418 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:16:34.418 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:16:34.418 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:16:34.418 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:16:34.418 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:16:34.418 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:16:34.418 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:16:34.422 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-01-29 03:16:34.905 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-01-29 03:16:34.944 [DEBUG] fake_trx.py:278 (BTS@172.18.28.20:5700) Recv FAKE_TOA cmd
2026-01-29 03:16:34.945 [DEBUG] fake_trx.py:297 (BTS@172.18.28.20:5700) Recv FAKE_RSSI cmd
2026-01-29 03:16:34.946 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:16:34.947 [DEBUG] fake_trx.py:322 (BTS@172.18.28.20:5700) Recv FAKE_CI cmd
2026-01-29 03:16:34.966 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 03:16:34.967 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 03:16:34.967 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 03:16:34.983 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 03:16:34.984 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:16:34.984 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:16:34.984 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:16:34.986 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 03:16:34.986 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 03:16:34.986 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.28.20:5700) Recv POWEROFF cmd
2026-01-29 03:16:34.986 [INFO] ctrl_if_trx.py:117 (BTS@172.18.28.20:5700) Stopping transceiver...
2026-01-29 03:16:34.986 [INFO] transceiver.py:246 Stopping clock generator
2026-01-29 03:16:34.986 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 03:16:34.986 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 03:16:34.986 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=121 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:16:34.986 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=121 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:16:34.986 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=121 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:16:34.986 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=121 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:16:34.986 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=121 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:16:34.987 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=121 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:16:34.987 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=121 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:16:39.986 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.28.20:5700) Recv POWEROFF cmd
2026-01-29 03:16:39.986 [INFO] ctrl_if_trx.py:117 (BTS@172.18.28.20:5700) Stopping transceiver...
2026-01-29 03:16:39.988 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 03:16:39.988 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 03:16:39.989 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 03:16:39.989 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 03:16:39.994 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 03:16:39.996 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.28.20:5700) Recv SETFORMAT cmd
2026-01-29 03:16:39.996 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.28.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:16:39.996 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.28.20:5700) Recv SETFORMAT cmd
2026-01-29 03:16:39.996 [INFO] ctrl_if_trx.py:201 (BTS@172.18.28.20:5700) TRXD header version 1 -> 1
2026-01-29 03:16:39.999 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.28.20:5700/1) Recv RXTUNE cmd
2026-01-29 03:16:39.999 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.28.20:5700/1) Recv TXTUNE cmd
2026-01-29 03:16:40.000 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.28.20:5700/1) Recv SETFORMAT cmd
2026-01-29 03:16:40.000 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.28.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:16:40.000 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 03:16:40.001 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.28.20:5700/1) Recv NOMTXPOWER cmd
2026-01-29 03:16:40.001 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.28.20:5700/1) Recv SETFORMAT cmd
2026-01-29 03:16:40.001 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.28.20:5700/1) TRXD header version 1 -> 1
2026-01-29 03:16:40.002 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.28.20:5700/2) Recv RXTUNE cmd
2026-01-29 03:16:40.002 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.28.20:5700/2) Recv TXTUNE cmd
2026-01-29 03:16:40.003 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.28.20:5700/2) Recv SETFORMAT cmd
2026-01-29 03:16:40.003 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.28.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:16:40.003 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 03:16:40.003 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.28.20:5700/2) Recv NOMTXPOWER cmd
2026-01-29 03:16:40.003 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.28.20:5700/2) Recv SETFORMAT cmd
2026-01-29 03:16:40.003 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.28.20:5700/2) TRXD header version 1 -> 1
2026-01-29 03:16:40.005 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.28.20:5700/3) Recv RXTUNE cmd
2026-01-29 03:16:40.005 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.28.20:5700/3) Recv TXTUNE cmd
2026-01-29 03:16:40.005 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.28.20:5700/3) Recv SETFORMAT cmd
2026-01-29 03:16:40.005 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.28.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:16:40.005 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 03:16:40.005 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.28.20:5700/3) Recv NOMTXPOWER cmd
2026-01-29 03:16:40.006 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.28.20:5700/3) Recv SETFORMAT cmd
2026-01-29 03:16:40.006 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.28.20:5700/3) TRXD header version 1 -> 1
2026-01-29 03:16:40.009 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.28.20:5700) Recv RXTUNE cmd
2026-01-29 03:16:40.009 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETTSC
2026-01-29 03:16:40.009 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETTSC
2026-01-29 03:16:40.009 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETTSC
2026-01-29 03:16:40.009 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.28.20:5700) Recv TXTUNE cmd
2026-01-29 03:16:40.009 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETRXGAIN
2026-01-29 03:16:40.009 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETRXGAIN
2026-01-29 03:16:40.009 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETRXGAIN
2026-01-29 03:16:40.009 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETTSC
2026-01-29 03:16:40.009 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:16:40.009 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:16:40.009 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:16:40.009 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.28.20:5700) Recv NOMTXPOWER cmd
2026-01-29 03:16:40.009 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:16:40.009 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:16:40.009 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:16:40.009 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.28.20:5700) Recv POWERON CMD
2026-01-29 03:16:40.009 [INFO] ctrl_if_trx.py:109 (BTS@172.18.28.20:5700) Starting transceiver...
2026-01-29 03:16:40.009 [INFO] transceiver.py:243 Starting clock generator
2026-01-29 03:16:40.010 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-01-29 03:16:40.010 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:16:40.010 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:16:40.010 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:16:40.010 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETRXGAIN
2026-01-29 03:16:40.010 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:16:40.010 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:16:40.010 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:16:40.010 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:16:40.010 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:16:40.010 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:16:40.010 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:16:40.010 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:16:40.010 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:16:40.010 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:16:40.010 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:16:40.010 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:16:40.011 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:16:40.011 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:16:40.011 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:16:40.011 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:16:40.011 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:16:40.011 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:16:40.011 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:16:40.011 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:16:40.011 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:16:40.011 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:16:40.011 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:16:40.014 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-01-29 03:16:40.498 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-01-29 03:16:40.532 [DEBUG] fake_trx.py:278 (BTS@172.18.28.20:5700) Recv FAKE_TOA cmd
2026-01-29 03:16:40.533 [DEBUG] fake_trx.py:297 (BTS@172.18.28.20:5700) Recv FAKE_RSSI cmd
2026-01-29 03:16:40.534 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:16:40.534 [DEBUG] fake_trx.py:322 (BTS@172.18.28.20:5700) Recv FAKE_CI cmd
2026-01-29 03:16:40.562 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 03:16:40.562 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 03:16:40.563 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 03:16:40.582 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 03:16:40.582 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 03:16:40.582 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 03:16:40.584 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:16:40.587 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 03:16:40.587 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:16:40.587 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:16:40.587 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:16:40.588 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 03:16:40.588 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 03:16:40.588 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 03:16:40.588 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 03:16:40.588 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.28.20:5700) Recv POWEROFF cmd
2026-01-29 03:16:40.588 [INFO] ctrl_if_trx.py:117 (BTS@172.18.28.20:5700) Stopping transceiver...
2026-01-29 03:16:40.588 [INFO] transceiver.py:246 Stopping clock generator
2026-01-29 03:16:45.595 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.28.20:5700) Recv POWEROFF cmd
2026-01-29 03:16:45.595 [INFO] ctrl_if_trx.py:117 (BTS@172.18.28.20:5700) Stopping transceiver...
2026-01-29 03:16:45.595 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 03:16:45.595 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 03:16:45.595 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 03:16:45.595 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 03:16:45.603 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 03:16:45.604 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.28.20:5700) Recv SETFORMAT cmd
2026-01-29 03:16:45.604 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.28.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:16:45.605 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.28.20:5700) Recv SETFORMAT cmd
2026-01-29 03:16:45.605 [INFO] ctrl_if_trx.py:201 (BTS@172.18.28.20:5700) TRXD header version 1 -> 1
2026-01-29 03:16:45.609 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.28.20:5700/1) Recv RXTUNE cmd
2026-01-29 03:16:45.609 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.28.20:5700/1) Recv TXTUNE cmd
2026-01-29 03:16:45.610 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.28.20:5700/1) Recv SETFORMAT cmd
2026-01-29 03:16:45.610 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.28.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:16:45.610 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 03:16:45.611 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.28.20:5700/1) Recv NOMTXPOWER cmd
2026-01-29 03:16:45.611 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.28.20:5700/1) Recv SETFORMAT cmd
2026-01-29 03:16:45.612 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.28.20:5700/1) TRXD header version 1 -> 1
2026-01-29 03:16:45.613 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.28.20:5700/2) Recv RXTUNE cmd
2026-01-29 03:16:45.613 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.28.20:5700/2) Recv TXTUNE cmd
2026-01-29 03:16:45.613 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.28.20:5700/2) Recv SETFORMAT cmd
2026-01-29 03:16:45.613 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.28.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:16:45.613 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 03:16:45.614 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.28.20:5700/2) Recv NOMTXPOWER cmd
2026-01-29 03:16:45.614 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.28.20:5700/2) Recv SETFORMAT cmd
2026-01-29 03:16:45.614 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.28.20:5700/2) TRXD header version 1 -> 1
2026-01-29 03:16:45.616 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.28.20:5700/3) Recv RXTUNE cmd
2026-01-29 03:16:45.616 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.28.20:5700/3) Recv TXTUNE cmd
2026-01-29 03:16:45.616 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.28.20:5700/3) Recv SETFORMAT cmd
2026-01-29 03:16:45.616 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.28.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:16:45.616 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 03:16:45.616 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.28.20:5700/3) Recv NOMTXPOWER cmd
2026-01-29 03:16:45.617 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.28.20:5700/3) Recv SETFORMAT cmd
2026-01-29 03:16:45.617 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.28.20:5700/3) TRXD header version 1 -> 1
2026-01-29 03:16:45.620 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.28.20:5700) Recv RXTUNE cmd
2026-01-29 03:16:45.620 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETTSC
2026-01-29 03:16:45.620 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETTSC
2026-01-29 03:16:45.620 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.28.20:5700) Recv TXTUNE cmd
2026-01-29 03:16:45.620 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETTSC
2026-01-29 03:16:45.620 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETRXGAIN
2026-01-29 03:16:45.620 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETRXGAIN
2026-01-29 03:16:45.620 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETTSC
2026-01-29 03:16:45.620 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETRXGAIN
2026-01-29 03:16:45.620 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:16:45.620 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:16:45.621 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.28.20:5700) Recv NOMTXPOWER cmd
2026-01-29 03:16:45.621 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:16:45.621 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:16:45.621 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.28.20:5700) Recv POWERON CMD
2026-01-29 03:16:45.621 [INFO] ctrl_if_trx.py:109 (BTS@172.18.28.20:5700) Starting transceiver...
2026-01-29 03:16:45.621 [INFO] transceiver.py:243 Starting clock generator
2026-01-29 03:16:45.621 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-01-29 03:16:45.621 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:16:45.621 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:16:45.621 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:16:45.621 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETRXGAIN
2026-01-29 03:16:45.621 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:16:45.621 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:16:45.621 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:16:45.621 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:16:45.621 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:16:45.621 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:16:45.621 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:16:45.621 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:16:45.622 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:16:45.622 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:16:45.622 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:16:45.622 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:16:45.622 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:16:45.622 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:16:45.622 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:16:45.622 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:16:45.622 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:16:45.622 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:16:45.622 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:16:45.622 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:16:45.622 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:16:45.622 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:16:45.622 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:16:45.622 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:16:45.622 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:16:45.626 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-01-29 03:16:46.107 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-01-29 03:16:46.153 [DEBUG] fake_trx.py:278 (BTS@172.18.28.20:5700) Recv FAKE_TOA cmd
2026-01-29 03:16:46.156 [DEBUG] fake_trx.py:297 (BTS@172.18.28.20:5700) Recv FAKE_RSSI cmd
2026-01-29 03:16:46.157 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:16:46.159 [DEBUG] fake_trx.py:322 (BTS@172.18.28.20:5700) Recv FAKE_CI cmd
2026-01-29 03:16:46.185 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 03:16:46.185 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 03:16:46.185 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 03:16:46.195 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 03:16:46.195 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:16:46.195 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:16:46.195 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:16:46.198 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 03:16:46.198 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 03:16:46.198 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 03:16:46.198 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.28.20:5700) Recv POWEROFF cmd
2026-01-29 03:16:46.198 [INFO] ctrl_if_trx.py:117 (BTS@172.18.28.20:5700) Stopping transceiver...
2026-01-29 03:16:46.198 [INFO] transceiver.py:246 Stopping clock generator
2026-01-29 03:16:46.198 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 03:16:46.198 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=123 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:16:46.199 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=123 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:16:46.199 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=123 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:16:46.199 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=123 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:16:46.199 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=123 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:16:46.199 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=123 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:16:46.199 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=123 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:16:46.199 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=123 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:16:51.201 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.28.20:5700) Recv POWEROFF cmd
2026-01-29 03:16:51.201 [INFO] ctrl_if_trx.py:117 (BTS@172.18.28.20:5700) Stopping transceiver...
2026-01-29 03:16:51.202 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 03:16:51.202 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 03:16:51.202 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 03:16:51.202 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 03:16:51.215 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 03:16:51.217 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.28.20:5700) Recv SETFORMAT cmd
2026-01-29 03:16:51.217 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.28.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:16:51.217 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.28.20:5700) Recv SETFORMAT cmd
2026-01-29 03:16:51.218 [INFO] ctrl_if_trx.py:201 (BTS@172.18.28.20:5700) TRXD header version 1 -> 1
2026-01-29 03:16:51.222 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.28.20:5700/1) Recv RXTUNE cmd
2026-01-29 03:16:51.222 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.28.20:5700/1) Recv TXTUNE cmd
2026-01-29 03:16:51.223 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.28.20:5700/1) Recv SETFORMAT cmd
2026-01-29 03:16:51.223 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.28.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:16:51.223 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 03:16:51.223 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.28.20:5700/1) Recv NOMTXPOWER cmd
2026-01-29 03:16:51.223 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.28.20:5700/1) Recv SETFORMAT cmd
2026-01-29 03:16:51.223 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.28.20:5700/1) TRXD header version 1 -> 1
2026-01-29 03:16:51.225 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.28.20:5700/2) Recv RXTUNE cmd
2026-01-29 03:16:51.225 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.28.20:5700/2) Recv TXTUNE cmd
2026-01-29 03:16:51.226 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.28.20:5700/2) Recv SETFORMAT cmd
2026-01-29 03:16:51.226 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.28.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:16:51.226 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 03:16:51.226 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.28.20:5700/2) Recv NOMTXPOWER cmd
2026-01-29 03:16:51.226 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.28.20:5700/2) Recv SETFORMAT cmd
2026-01-29 03:16:51.226 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.28.20:5700/2) TRXD header version 1 -> 1
2026-01-29 03:16:51.228 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.28.20:5700/3) Recv RXTUNE cmd
2026-01-29 03:16:51.228 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.28.20:5700/3) Recv TXTUNE cmd
2026-01-29 03:16:51.228 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.28.20:5700/3) Recv SETFORMAT cmd
2026-01-29 03:16:51.228 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.28.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:16:51.228 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 03:16:51.228 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.28.20:5700/3) Recv NOMTXPOWER cmd
2026-01-29 03:16:51.229 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.28.20:5700/3) Recv SETFORMAT cmd
2026-01-29 03:16:51.229 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.28.20:5700/3) TRXD header version 1 -> 1
2026-01-29 03:16:51.231 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.28.20:5700) Recv RXTUNE cmd
2026-01-29 03:16:51.231 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETTSC
2026-01-29 03:16:51.231 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETTSC
2026-01-29 03:16:51.232 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETTSC
2026-01-29 03:16:51.232 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.28.20:5700) Recv TXTUNE cmd
2026-01-29 03:16:51.232 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETRXGAIN
2026-01-29 03:16:51.232 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETRXGAIN
2026-01-29 03:16:51.232 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETRXGAIN
2026-01-29 03:16:51.232 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETTSC
2026-01-29 03:16:51.232 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:16:51.232 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:16:51.232 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:16:51.232 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.28.20:5700) Recv NOMTXPOWER cmd
2026-01-29 03:16:51.232 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:16:51.232 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:16:51.232 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.28.20:5700) Recv POWERON CMD
2026-01-29 03:16:51.232 [INFO] ctrl_if_trx.py:109 (BTS@172.18.28.20:5700) Starting transceiver...
2026-01-29 03:16:51.232 [INFO] transceiver.py:243 Starting clock generator
2026-01-29 03:16:51.232 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-01-29 03:16:51.232 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:16:51.232 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:16:51.232 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:16:51.232 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETRXGAIN
2026-01-29 03:16:51.232 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:16:51.232 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:16:51.233 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:16:51.233 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:16:51.233 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:16:51.233 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:16:51.233 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:16:51.233 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:16:51.234 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:16:51.234 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:16:51.234 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:16:51.234 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:16:51.234 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:16:51.234 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:16:51.234 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:16:51.234 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:16:51.234 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:16:51.234 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:16:51.234 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:16:51.234 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:16:51.234 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:16:51.234 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 03:16:51.234 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:16:51.234 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:16:51.234 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:16:51.234 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 03:16:51.234 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 03:16:51.234 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.28.20:5700) Recv POWEROFF cmd
2026-01-29 03:16:51.234 [INFO] ctrl_if_trx.py:117 (BTS@172.18.28.20:5700) Stopping transceiver...
2026-01-29 03:16:51.234 [INFO] transceiver.py:246 Stopping clock generator
2026-01-29 03:16:51.234 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 03:16:56.236 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.28.20:5700) Recv POWEROFF cmd
2026-01-29 03:16:56.237 [INFO] ctrl_if_trx.py:117 (BTS@172.18.28.20:5700) Stopping transceiver...
2026-01-29 03:16:56.238 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 03:16:56.241 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 03:16:56.241 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 03:16:56.241 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 03:16:56.252 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 03:16:56.253 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.28.20:5700) Recv SETFORMAT cmd
2026-01-29 03:16:56.253 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.28.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:16:56.253 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.28.20:5700) Recv SETFORMAT cmd
2026-01-29 03:16:56.253 [INFO] ctrl_if_trx.py:201 (BTS@172.18.28.20:5700) TRXD header version 1 -> 1
2026-01-29 03:16:56.256 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.28.20:5700/1) Recv RXTUNE cmd
2026-01-29 03:16:56.257 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.28.20:5700/1) Recv TXTUNE cmd
2026-01-29 03:16:56.257 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.28.20:5700/1) Recv SETFORMAT cmd
2026-01-29 03:16:56.257 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.28.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:16:56.257 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 03:16:56.257 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.28.20:5700/1) Recv NOMTXPOWER cmd
2026-01-29 03:16:56.257 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.28.20:5700/1) Recv SETFORMAT cmd
2026-01-29 03:16:56.257 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.28.20:5700/1) TRXD header version 1 -> 1
2026-01-29 03:16:56.260 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.28.20:5700/2) Recv RXTUNE cmd
2026-01-29 03:16:56.260 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.28.20:5700/2) Recv TXTUNE cmd
2026-01-29 03:16:56.260 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.28.20:5700/2) Recv SETFORMAT cmd
2026-01-29 03:16:56.260 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.28.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:16:56.260 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 03:16:56.260 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.28.20:5700/2) Recv NOMTXPOWER cmd
2026-01-29 03:16:56.260 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.28.20:5700/2) Recv SETFORMAT cmd
2026-01-29 03:16:56.260 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.28.20:5700/2) TRXD header version 1 -> 1
2026-01-29 03:16:56.262 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.28.20:5700/3) Recv RXTUNE cmd
2026-01-29 03:16:56.262 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.28.20:5700/3) Recv TXTUNE cmd
2026-01-29 03:16:56.262 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.28.20:5700/3) Recv SETFORMAT cmd
2026-01-29 03:16:56.262 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.28.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:16:56.262 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 03:16:56.262 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.28.20:5700/3) Recv NOMTXPOWER cmd
2026-01-29 03:16:56.263 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.28.20:5700/3) Recv SETFORMAT cmd
2026-01-29 03:16:56.263 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.28.20:5700/3) TRXD header version 1 -> 1
2026-01-29 03:16:56.265 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.28.20:5700) Recv RXTUNE cmd
2026-01-29 03:16:56.265 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETTSC
2026-01-29 03:16:56.265 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETTSC
2026-01-29 03:16:56.265 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETTSC
2026-01-29 03:16:56.265 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.28.20:5700) Recv TXTUNE cmd
2026-01-29 03:16:56.265 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETRXGAIN
2026-01-29 03:16:56.265 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETRXGAIN
2026-01-29 03:16:56.265 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETRXGAIN
2026-01-29 03:16:56.265 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETTSC
2026-01-29 03:16:56.265 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:16:56.265 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:16:56.265 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.28.20:5700) Recv NOMTXPOWER cmd
2026-01-29 03:16:56.265 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:16:56.265 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:16:56.265 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:16:56.265 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.28.20:5700) Recv POWERON CMD
2026-01-29 03:16:56.265 [INFO] ctrl_if_trx.py:109 (BTS@172.18.28.20:5700) Starting transceiver...
2026-01-29 03:16:56.265 [INFO] transceiver.py:243 Starting clock generator
2026-01-29 03:16:56.265 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-01-29 03:16:56.265 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:16:56.265 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:16:56.265 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:16:56.266 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETRXGAIN
2026-01-29 03:16:56.266 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:16:56.266 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:16:56.266 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:16:56.266 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:16:56.266 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:16:56.266 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:16:56.266 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:16:56.266 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:16:56.266 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:16:56.266 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:16:56.266 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:16:56.266 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:16:56.266 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:16:56.266 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:16:56.266 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:16:56.266 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:16:56.266 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:16:56.266 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:16:56.266 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:16:56.266 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:16:56.266 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:16:56.266 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:16:56.266 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:16:56.266 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:16:56.270 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-01-29 03:16:56.750 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-01-29 03:16:56.792 [DEBUG] fake_trx.py:278 (BTS@172.18.28.20:5700) Recv FAKE_TOA cmd
2026-01-29 03:16:56.793 [DEBUG] fake_trx.py:297 (BTS@172.18.28.20:5700) Recv FAKE_RSSI cmd
2026-01-29 03:16:56.794 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:16:56.795 [DEBUG] fake_trx.py:322 (BTS@172.18.28.20:5700) Recv FAKE_CI cmd
2026-01-29 03:16:56.812 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 03:16:56.813 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 03:16:56.813 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 03:16:56.818 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 03:16:56.818 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 03:16:56.819 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 03:16:56.819 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.28.22:6700) Recv POWERON CMD
2026-01-29 03:16:56.819 [INFO] ctrl_if_trx.py:109 (MS@172.18.28.22:6700) Starting transceiver...
2026-01-29 03:16:56.844 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:16:56.848 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 03:16:56.849 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 03:16:56.849 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 03:16:56.849 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 03:16:57.227 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-01-29 03:16:57.268 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:16:57.268 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 03:16:57.268 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:16:57.269 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:16:57.705 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-01-29 03:16:57.815 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:16:57.817 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 03:16:57.818 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 03:16:57.818 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 03:16:57.837 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 03:16:57.837 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 03:16:57.837 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 03:16:57.838 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 03:16:57.838 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 03:16:57.838 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 03:16:57.839 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.28.22:6700) Recv POWERON CMD
2026-01-29 03:16:57.839 [INFO] ctrl_if_trx.py:109 (MS@172.18.28.22:6700) Starting transceiver...
2026-01-29 03:16:57.841 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:16:57.842 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 03:16:57.842 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 03:16:57.842 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 03:16:57.842 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 03:16:58.181 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-01-29 03:16:58.269 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:16:58.271 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 03:16:58.272 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:16:58.272 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:16:58.658 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-01-29 03:16:58.787 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:16:58.790 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 03:16:58.791 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 03:16:58.791 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 03:16:58.811 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 03:16:58.811 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 03:16:58.811 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 03:16:58.812 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 03:16:58.812 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 03:16:58.813 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 03:16:58.813 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.28.22:6700) Recv POWERON CMD
2026-01-29 03:16:58.813 [INFO] ctrl_if_trx.py:109 (MS@172.18.28.22:6700) Starting transceiver...
2026-01-29 03:16:58.847 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:16:58.852 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 03:16:58.853 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 03:16:58.853 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 03:16:58.854 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 03:16:59.136 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-01-29 03:16:59.271 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:16:59.272 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 03:16:59.272 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:16:59.272 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:16:59.614 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-01-29 03:16:59.770 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:16:59.773 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 03:16:59.774 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 03:16:59.774 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 03:16:59.790 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 03:16:59.790 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 03:16:59.790 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 03:16:59.791 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 03:16:59.791 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 03:16:59.791 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 03:16:59.792 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.28.22:6700) Recv POWERON CMD
2026-01-29 03:16:59.792 [INFO] ctrl_if_trx.py:109 (MS@172.18.28.22:6700) Starting transceiver...
2026-01-29 03:16:59.795 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:16:59.796 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 03:16:59.796 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 03:16:59.796 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 03:16:59.797 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 03:17:00.091 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-01-29 03:17:00.272 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:17:00.273 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 03:17:00.273 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:17:00.273 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:17:00.569 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-01-29 03:17:00.743 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:17:00.745 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 03:17:00.746 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 03:17:00.746 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 03:17:00.766 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 03:17:00.766 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 03:17:00.766 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 03:17:00.767 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 03:17:00.767 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 03:17:00.767 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 03:17:00.767 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.28.22:6700) Recv POWERON CMD
2026-01-29 03:17:00.767 [INFO] ctrl_if_trx.py:109 (MS@172.18.28.22:6700) Starting transceiver...
2026-01-29 03:17:00.803 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:17:00.805 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 03:17:00.805 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 03:17:00.805 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 03:17:00.805 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 03:17:01.046 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-01-29 03:17:01.273 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:17:01.273 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 03:17:01.274 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:17:01.274 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:17:01.363 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:17:01.365 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 03:17:01.366 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 03:17:01.366 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 03:17:01.386 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 03:17:01.386 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 03:17:01.386 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 03:17:01.387 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 03:17:01.387 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 03:17:01.387 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 03:17:01.388 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.28.22:6700) Recv POWERON CMD
2026-01-29 03:17:01.388 [INFO] ctrl_if_trx.py:109 (MS@172.18.28.22:6700) Starting transceiver...
2026-01-29 03:17:01.424 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:17:01.429 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.28.22:6700) Recv SETFH cmd
2026-01-29 03:17:01.429 [INFO] transceiver.py:201 (MS@172.18.28.22:6700) Frequency hopping configured: hsn=2, maio=0, ma_len=2
2026-01-29 03:17:01.429 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 03:17:01.429 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 03:17:01.524 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-01-29 03:17:01.971 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:17:01.973 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 03:17:01.974 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 03:17:01.974 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 03:17:01.974 [INFO] transceiver.py:205 (MS@172.18.28.22:6700) Frequency hopping disabled
2026-01-29 03:17:01.993 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 03:17:01.993 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 03:17:01.993 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 03:17:01.995 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 03:17:01.995 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 03:17:01.995 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 03:17:01.995 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.28.22:6700) Recv POWERON CMD
2026-01-29 03:17:01.995 [INFO] ctrl_if_trx.py:109 (MS@172.18.28.22:6700) Starting transceiver...
2026-01-29 03:17:02.002 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-01-29 03:17:02.052 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:17:02.058 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.28.22:6700) Recv SETFH cmd
2026-01-29 03:17:02.058 [INFO] transceiver.py:201 (MS@172.18.28.22:6700) Frequency hopping configured: hsn=3, maio=3, ma_len=4
2026-01-29 03:17:02.058 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 03:17:02.059 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 03:17:02.480 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-01-29 03:17:02.609 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:17:02.612 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 03:17:02.613 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 03:17:02.613 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 03:17:02.613 [INFO] transceiver.py:205 (MS@172.18.28.22:6700) Frequency hopping disabled
2026-01-29 03:17:02.628 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 03:17:02.628 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 03:17:02.628 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 03:17:02.629 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 03:17:02.629 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 03:17:02.630 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 03:17:02.630 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.28.22:6700) Recv POWERON CMD
2026-01-29 03:17:02.630 [INFO] ctrl_if_trx.py:109 (MS@172.18.28.22:6700) Starting transceiver...
2026-01-29 03:17:02.667 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:17:02.667 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:17:02.668 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 03:17:02.668 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 03:17:02.668 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 03:17:02.668 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 03:17:02.958 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-01-29 03:17:03.271 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:17:03.273 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 03:17:03.274 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 03:17:03.274 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 03:17:03.293 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 03:17:03.294 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 03:17:03.294 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 03:17:03.295 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 03:17:03.295 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 03:17:03.295 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 03:17:03.295 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.28.22:6700) Recv POWERON CMD
2026-01-29 03:17:03.295 [INFO] ctrl_if_trx.py:109 (MS@172.18.28.22:6700) Starting transceiver...
2026-01-29 03:17:03.335 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:17:03.340 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 03:17:03.340 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 03:17:03.341 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 03:17:03.341 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 03:17:03.436 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-01-29 03:17:03.914 [DEBUG] clck_gen.py:113 IND CLOCK 1632
2026-01-29 03:17:03.927 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:17:03.930 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 03:17:03.930 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 03:17:03.930 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 03:17:03.941 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 03:17:03.941 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 03:17:03.941 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 03:17:03.942 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 03:17:03.942 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 03:17:03.942 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 03:17:03.942 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.28.22:6700) Recv POWERON CMD
2026-01-29 03:17:03.942 [INFO] ctrl_if_trx.py:109 (MS@172.18.28.22:6700) Starting transceiver...
2026-01-29 03:17:03.959 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:17:03.960 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:17:03.963 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 03:17:03.964 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 03:17:03.964 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 03:17:03.964 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 03:17:04.392 [DEBUG] clck_gen.py:113 IND CLOCK 1734
2026-01-29 03:17:04.516 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:17:04.519 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 03:17:04.520 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 03:17:04.520 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 03:17:04.538 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 03:17:04.538 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 03:17:04.538 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 03:17:04.540 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 03:17:04.540 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 03:17:04.540 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 03:17:04.540 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.28.22:6700) Recv POWERON CMD
2026-01-29 03:17:04.540 [INFO] ctrl_if_trx.py:109 (MS@172.18.28.22:6700) Starting transceiver...
2026-01-29 03:17:04.579 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:17:04.585 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.28.22:6700) Recv SETFH cmd
2026-01-29 03:17:04.585 [INFO] transceiver.py:201 (MS@172.18.28.22:6700) Frequency hopping configured: hsn=5, maio=0, ma_len=4
2026-01-29 03:17:04.586 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 03:17:04.586 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 03:17:04.870 [DEBUG] clck_gen.py:113 IND CLOCK 1836
2026-01-29 03:17:05.179 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:17:05.182 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 03:17:05.182 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 03:17:05.182 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 03:17:05.183 [INFO] transceiver.py:205 (MS@172.18.28.22:6700) Frequency hopping disabled
2026-01-29 03:17:05.203 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 03:17:05.203 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 03:17:05.204 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 03:17:05.205 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 03:17:05.205 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 03:17:05.205 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 03:17:05.205 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.28.22:6700) Recv POWERON CMD
2026-01-29 03:17:05.205 [INFO] ctrl_if_trx.py:109 (MS@172.18.28.22:6700) Starting transceiver...
2026-01-29 03:17:05.246 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:17:05.252 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.28.22:6700) Recv SETFH cmd
2026-01-29 03:17:05.252 [INFO] transceiver.py:201 (MS@172.18.28.22:6700) Frequency hopping configured: hsn=5, maio=0, ma_len=4
2026-01-29 03:17:05.252 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 03:17:05.252 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 03:17:05.348 [DEBUG] clck_gen.py:113 IND CLOCK 1938
2026-01-29 03:17:05.827 [DEBUG] clck_gen.py:113 IND CLOCK 2040
2026-01-29 03:17:05.878 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:17:05.881 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 03:17:05.881 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 03:17:05.881 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 03:17:05.882 [INFO] transceiver.py:205 (MS@172.18.28.22:6700) Frequency hopping disabled
2026-01-29 03:17:05.902 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 03:17:05.902 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 03:17:05.902 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 03:17:05.903 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 03:17:05.903 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 03:17:05.903 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 03:17:05.903 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.28.22:6700) Recv POWERON CMD
2026-01-29 03:17:05.903 [INFO] ctrl_if_trx.py:109 (MS@172.18.28.22:6700) Starting transceiver...
2026-01-29 03:17:05.919 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:17:05.923 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.28.22:6700) Recv SETFH cmd
2026-01-29 03:17:05.923 [INFO] transceiver.py:201 (MS@172.18.28.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2026-01-29 03:17:05.923 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 03:17:05.924 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 03:17:06.305 [DEBUG] clck_gen.py:113 IND CLOCK 2142
2026-01-29 03:17:06.784 [DEBUG] clck_gen.py:113 IND CLOCK 2244
2026-01-29 03:17:06.804 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:17:06.807 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 03:17:06.807 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 03:17:06.808 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 03:17:06.808 [INFO] transceiver.py:205 (MS@172.18.28.22:6700) Frequency hopping disabled
2026-01-29 03:17:06.828 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 03:17:06.828 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 03:17:06.828 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 03:17:06.829 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 03:17:06.829 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 03:17:06.829 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 03:17:06.829 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.28.22:6700) Recv POWERON CMD
2026-01-29 03:17:06.829 [INFO] ctrl_if_trx.py:109 (MS@172.18.28.22:6700) Starting transceiver...
2026-01-29 03:17:06.848 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:17:06.852 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.28.22:6700) Recv SETFH cmd
2026-01-29 03:17:06.852 [INFO] transceiver.py:201 (MS@172.18.28.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2026-01-29 03:17:06.852 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 03:17:06.852 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 03:17:07.280 [DEBUG] clck_gen.py:113 IND CLOCK 2346
2026-01-29 03:17:07.758 [DEBUG] clck_gen.py:113 IND CLOCK 2448
2026-01-29 03:17:07.786 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:17:07.789 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 03:17:07.790 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 03:17:07.790 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 03:17:07.790 [INFO] transceiver.py:205 (MS@172.18.28.22:6700) Frequency hopping disabled
2026-01-29 03:17:07.802 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 03:17:07.802 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 03:17:07.802 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 03:17:07.803 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 03:17:07.803 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 03:17:07.803 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 03:17:07.803 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.28.22:6700) Recv POWERON CMD
2026-01-29 03:17:07.803 [INFO] ctrl_if_trx.py:109 (MS@172.18.28.22:6700) Starting transceiver...
2026-01-29 03:17:07.855 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:17:07.861 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.28.22:6700) Recv SETFH cmd
2026-01-29 03:17:07.861 [INFO] transceiver.py:201 (MS@172.18.28.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2026-01-29 03:17:07.862 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 03:17:07.862 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 03:17:08.236 [DEBUG] clck_gen.py:113 IND CLOCK 2550
2026-01-29 03:17:08.714 [DEBUG] clck_gen.py:113 IND CLOCK 2652
2026-01-29 03:17:08.761 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:17:08.764 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 03:17:08.766 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 03:17:08.766 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 03:17:08.766 [INFO] transceiver.py:205 (MS@172.18.28.22:6700) Frequency hopping disabled
2026-01-29 03:17:08.786 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 03:17:08.786 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 03:17:08.786 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 03:17:08.787 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 03:17:08.787 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 03:17:08.787 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 03:17:08.787 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.28.22:6700) Recv POWERON CMD
2026-01-29 03:17:08.787 [INFO] ctrl_if_trx.py:109 (MS@172.18.28.22:6700) Starting transceiver...
2026-01-29 03:17:08.805 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:17:08.808 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.28.22:6700) Recv SETFH cmd
2026-01-29 03:17:08.808 [INFO] transceiver.py:201 (MS@172.18.28.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2026-01-29 03:17:08.808 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 03:17:08.808 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 03:17:09.193 [DEBUG] clck_gen.py:113 IND CLOCK 2754
2026-01-29 03:17:09.671 [DEBUG] clck_gen.py:113 IND CLOCK 2856
2026-01-29 03:17:09.735 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:17:09.739 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 03:17:09.739 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 03:17:09.739 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 03:17:09.739 [INFO] transceiver.py:205 (MS@172.18.28.22:6700) Frequency hopping disabled
2026-01-29 03:17:09.757 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 03:17:09.757 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 03:17:09.757 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 03:17:09.759 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 03:17:09.759 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 03:17:09.759 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 03:17:09.759 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.28.22:6700) Recv POWERON CMD
2026-01-29 03:17:09.759 [INFO] ctrl_if_trx.py:109 (MS@172.18.28.22:6700) Starting transceiver...
2026-01-29 03:17:09.761 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:17:09.762 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.28.22:6700) Recv SETFH cmd
2026-01-29 03:17:09.762 [INFO] transceiver.py:201 (MS@172.18.28.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2026-01-29 03:17:09.762 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 03:17:09.762 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 03:17:10.149 [DEBUG] clck_gen.py:113 IND CLOCK 2958
2026-01-29 03:17:10.628 [DEBUG] clck_gen.py:113 IND CLOCK 3060
2026-01-29 03:17:10.710 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:17:10.712 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 03:17:10.713 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 03:17:10.713 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 03:17:10.713 [INFO] transceiver.py:205 (MS@172.18.28.22:6700) Frequency hopping disabled
2026-01-29 03:17:10.732 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 03:17:10.732 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 03:17:10.732 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 03:17:10.733 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 03:17:10.733 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 03:17:10.733 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 03:17:10.733 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.28.22:6700) Recv POWERON CMD
2026-01-29 03:17:10.733 [INFO] ctrl_if_trx.py:109 (MS@172.18.28.22:6700) Starting transceiver...
2026-01-29 03:17:10.769 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:17:10.773 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.28.22:6700) Recv SETFH cmd
2026-01-29 03:17:10.773 [INFO] transceiver.py:201 (MS@172.18.28.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2026-01-29 03:17:10.773 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 03:17:10.773 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 03:17:11.106 [DEBUG] clck_gen.py:113 IND CLOCK 3162
2026-01-29 03:17:11.584 [DEBUG] clck_gen.py:113 IND CLOCK 3264
2026-01-29 03:17:11.685 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:17:11.688 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 03:17:11.689 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 03:17:11.689 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 03:17:11.689 [INFO] transceiver.py:205 (MS@172.18.28.22:6700) Frequency hopping disabled
2026-01-29 03:17:11.698 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 03:17:11.698 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 03:17:11.698 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 03:17:11.699 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 03:17:11.699 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 03:17:11.699 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 03:17:11.700 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.28.22:6700) Recv POWERON CMD
2026-01-29 03:17:11.700 [INFO] ctrl_if_trx.py:109 (MS@172.18.28.22:6700) Starting transceiver...
2026-01-29 03:17:11.723 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:17:11.728 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.28.22:6700) Recv SETFH cmd
2026-01-29 03:17:11.728 [INFO] transceiver.py:201 (MS@172.18.28.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2026-01-29 03:17:11.728 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 03:17:11.728 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 03:17:12.061 [DEBUG] clck_gen.py:113 IND CLOCK 3366
2026-01-29 03:17:12.539 [DEBUG] clck_gen.py:113 IND CLOCK 3468
2026-01-29 03:17:12.659 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:17:12.663 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 03:17:12.663 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 03:17:12.663 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 03:17:12.664 [INFO] transceiver.py:205 (MS@172.18.28.22:6700) Frequency hopping disabled
2026-01-29 03:17:12.683 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 03:17:12.683 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 03:17:12.683 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 03:17:12.684 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 03:17:12.685 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 03:17:12.685 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 03:17:12.685 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.28.22:6700) Recv POWERON CMD
2026-01-29 03:17:12.685 [INFO] ctrl_if_trx.py:109 (MS@172.18.28.22:6700) Starting transceiver...
2026-01-29 03:17:12.727 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:17:12.733 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.28.22:6700) Recv SETFH cmd
2026-01-29 03:17:12.733 [INFO] transceiver.py:201 (MS@172.18.28.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2026-01-29 03:17:12.733 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 03:17:12.734 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 03:17:13.011 [DEBUG] clck_gen.py:113 IND CLOCK 3570
2026-01-29 03:17:13.489 [DEBUG] clck_gen.py:113 IND CLOCK 3672
2026-01-29 03:17:13.627 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:17:13.630 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 03:17:13.631 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 03:17:13.632 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 03:17:13.632 [INFO] transceiver.py:205 (MS@172.18.28.22:6700) Frequency hopping disabled
2026-01-29 03:17:13.639 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 03:17:13.639 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:17:13.639 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:17:13.639 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:17:13.642 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 03:17:13.642 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 03:17:13.642 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 03:17:13.642 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 03:17:13.642 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.28.20:5700) Recv POWEROFF cmd
2026-01-29 03:17:13.642 [INFO] ctrl_if_trx.py:117 (BTS@172.18.28.20:5700) Stopping transceiver...
2026-01-29 03:17:13.642 [INFO] transceiver.py:246 Stopping clock generator
2026-01-29 03:17:13.643 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=3706 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:17:13.643 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=3706 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:17:13.643 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=3706 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:17:13.643 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=3706 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:17:13.643 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=3706 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:17:13.643 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=3706 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:17:13.643 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=3706 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:17:13.643 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=3707 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:17:13.643 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=3707 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:17:13.643 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=3707 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:17:13.643 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=3707 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:17:13.643 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=3707 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:17:13.643 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=3707 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:17:13.643 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=3707 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:17:13.643 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=3707 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:17:18.643 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.28.20:5700) Recv POWEROFF cmd
2026-01-29 03:17:18.643 [INFO] ctrl_if_trx.py:117 (BTS@172.18.28.20:5700) Stopping transceiver...
2026-01-29 03:17:18.644 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 03:17:18.646 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 03:17:18.647 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 03:17:18.647 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 03:17:18.656 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 03:17:18.657 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.28.20:5700) Recv SETFORMAT cmd
2026-01-29 03:17:18.657 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.28.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:17:18.658 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.28.20:5700) Recv SETFORMAT cmd
2026-01-29 03:17:18.658 [INFO] ctrl_if_trx.py:201 (BTS@172.18.28.20:5700) TRXD header version 1 -> 1
2026-01-29 03:17:18.662 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.28.20:5700/1) Recv RXTUNE cmd
2026-01-29 03:17:18.662 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.28.20:5700/1) Recv TXTUNE cmd
2026-01-29 03:17:18.663 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.28.20:5700/1) Recv SETFORMAT cmd
2026-01-29 03:17:18.663 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.28.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:17:18.664 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 03:17:18.664 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.28.20:5700/1) Recv NOMTXPOWER cmd
2026-01-29 03:17:18.664 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.28.20:5700/1) Recv SETFORMAT cmd
2026-01-29 03:17:18.665 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.28.20:5700/1) TRXD header version 1 -> 1
2026-01-29 03:17:18.666 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.28.20:5700/2) Recv RXTUNE cmd
2026-01-29 03:17:18.666 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.28.20:5700/2) Recv TXTUNE cmd
2026-01-29 03:17:18.666 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.28.20:5700/2) Recv SETFORMAT cmd
2026-01-29 03:17:18.667 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.28.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:17:18.667 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 03:17:18.667 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.28.20:5700/2) Recv NOMTXPOWER cmd
2026-01-29 03:17:18.667 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.28.20:5700/2) Recv SETFORMAT cmd
2026-01-29 03:17:18.667 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.28.20:5700/2) TRXD header version 1 -> 1
2026-01-29 03:17:18.668 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.28.20:5700/3) Recv RXTUNE cmd
2026-01-29 03:17:18.669 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.28.20:5700/3) Recv TXTUNE cmd
2026-01-29 03:17:18.669 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.28.20:5700/3) Recv SETFORMAT cmd
2026-01-29 03:17:18.669 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.28.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:17:18.669 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 03:17:18.669 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.28.20:5700/3) Recv NOMTXPOWER cmd
2026-01-29 03:17:18.669 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.28.20:5700/3) Recv SETFORMAT cmd
2026-01-29 03:17:18.669 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.28.20:5700/3) TRXD header version 1 -> 1
2026-01-29 03:17:18.672 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.28.20:5700) Recv RXTUNE cmd
2026-01-29 03:17:18.672 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETTSC
2026-01-29 03:17:18.672 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETTSC
2026-01-29 03:17:18.672 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.28.20:5700) Recv TXTUNE cmd
2026-01-29 03:17:18.672 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETTSC
2026-01-29 03:17:18.672 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETRXGAIN
2026-01-29 03:17:18.672 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETRXGAIN
2026-01-29 03:17:18.672 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETTSC
2026-01-29 03:17:18.672 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETRXGAIN
2026-01-29 03:17:18.672 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:17:18.672 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:17:18.672 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.28.20:5700) Recv NOMTXPOWER cmd
2026-01-29 03:17:18.672 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:17:18.672 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:17:18.672 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:17:18.672 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.28.20:5700) Recv POWERON CMD
2026-01-29 03:17:18.672 [INFO] ctrl_if_trx.py:109 (BTS@172.18.28.20:5700) Starting transceiver...
2026-01-29 03:17:18.672 [INFO] transceiver.py:243 Starting clock generator
2026-01-29 03:17:18.673 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-01-29 03:17:18.673 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:17:18.673 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:17:18.673 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:17:18.673 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETRXGAIN
2026-01-29 03:17:18.673 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:17:18.673 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:17:18.673 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:17:18.673 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:17:18.673 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:17:18.673 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:17:18.673 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:17:18.673 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:17:18.673 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:17:18.673 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:17:18.673 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:17:18.673 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:17:18.673 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:17:18.673 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:17:18.674 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:17:18.674 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:17:18.674 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:17:18.674 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:17:18.674 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:17:18.674 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:17:18.674 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:17:18.674 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:17:18.674 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:17:18.674 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:17:18.677 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-01-29 03:17:19.159 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-01-29 03:17:19.205 [DEBUG] fake_trx.py:278 (BTS@172.18.28.20:5700) Recv FAKE_TOA cmd
2026-01-29 03:17:19.206 [DEBUG] fake_trx.py:297 (BTS@172.18.28.20:5700) Recv FAKE_RSSI cmd
2026-01-29 03:17:19.208 [DEBUG] fake_trx.py:322 (BTS@172.18.28.20:5700) Recv FAKE_CI cmd
2026-01-29 03:17:19.209 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:17:19.223 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 03:17:19.223 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 03:17:19.223 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 03:17:19.227 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 03:17:19.228 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 03:17:19.228 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 03:17:19.228 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.28.22:6700) Recv POWERON CMD
2026-01-29 03:17:19.228 [INFO] ctrl_if_trx.py:109 (MS@172.18.28.22:6700) Starting transceiver...
2026-01-29 03:17:19.256 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:17:19.262 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 03:17:19.262 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 03:17:19.262 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 03:17:19.262 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 03:17:19.504 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:17:19.507 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 03:17:19.507 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 03:17:19.508 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 03:17:19.527 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 03:17:19.527 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 03:17:19.527 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 03:17:19.529 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 03:17:19.529 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 03:17:19.529 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 03:17:19.529 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.28.22:6700) Recv POWERON CMD
2026-01-29 03:17:19.529 [INFO] ctrl_if_trx.py:109 (MS@172.18.28.22:6700) Starting transceiver...
2026-01-29 03:17:19.581 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:17:19.587 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 03:17:19.587 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 03:17:19.587 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 03:17:19.588 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 03:17:19.635 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-01-29 03:17:19.677 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:17:19.677 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 03:17:19.678 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:17:19.681 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:17:19.764 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:17:19.767 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 03:17:19.767 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 03:17:19.767 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 03:17:19.777 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 03:17:19.777 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 03:17:19.777 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 03:17:19.778 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 03:17:19.778 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 03:17:19.778 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 03:17:19.778 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.28.22:6700) Recv POWERON CMD
2026-01-29 03:17:19.778 [INFO] ctrl_if_trx.py:109 (MS@172.18.28.22:6700) Starting transceiver...
2026-01-29 03:17:19.821 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:17:19.822 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 03:17:19.822 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 03:17:19.823 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 03:17:19.823 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 03:17:20.027 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:17:20.030 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 03:17:20.031 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 03:17:20.031 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 03:17:20.052 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 03:17:20.052 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 03:17:20.052 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 03:17:20.054 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 03:17:20.054 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 03:17:20.054 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 03:17:20.054 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.28.22:6700) Recv POWERON CMD
2026-01-29 03:17:20.054 [INFO] ctrl_if_trx.py:109 (MS@172.18.28.22:6700) Starting transceiver...
2026-01-29 03:17:20.108 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:17:20.109 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-01-29 03:17:20.110 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 03:17:20.110 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 03:17:20.111 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 03:17:20.111 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 03:17:20.281 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:17:20.284 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 03:17:20.285 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 03:17:20.285 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 03:17:20.291 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 03:17:20.291 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:17:20.291 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:17:20.291 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:17:20.292 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 03:17:20.292 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 03:17:20.292 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 03:17:20.292 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 03:17:20.292 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.28.20:5700) Recv POWEROFF cmd
2026-01-29 03:17:20.292 [INFO] ctrl_if_trx.py:117 (BTS@172.18.28.20:5700) Stopping transceiver...
2026-01-29 03:17:20.292 [INFO] transceiver.py:246 Stopping clock generator
2026-01-29 03:17:20.292 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=348 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:17:20.292 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=348 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:17:20.292 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=348 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:17:20.292 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=348 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:17:20.292 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=348 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:17:20.292 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=348 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:17:20.292 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=348 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:17:25.295 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.28.20:5700) Recv POWEROFF cmd
2026-01-29 03:17:25.295 [INFO] ctrl_if_trx.py:117 (BTS@172.18.28.20:5700) Stopping transceiver...
2026-01-29 03:17:25.297 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 03:17:25.298 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 03:17:25.298 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 03:17:25.299 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 03:17:25.302 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 03:17:25.303 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.28.20:5700) Recv SETFORMAT cmd
2026-01-29 03:17:25.303 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.28.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:17:25.303 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.28.20:5700) Recv SETFORMAT cmd
2026-01-29 03:17:25.303 [INFO] ctrl_if_trx.py:201 (BTS@172.18.28.20:5700) TRXD header version 1 -> 1
2026-01-29 03:17:25.304 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.28.20:5700/1) Recv RXTUNE cmd
2026-01-29 03:17:25.305 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.28.20:5700/1) Recv TXTUNE cmd
2026-01-29 03:17:25.305 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.28.20:5700/1) Recv SETFORMAT cmd
2026-01-29 03:17:25.305 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.28.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:17:25.306 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 03:17:25.306 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.28.20:5700/1) Recv NOMTXPOWER cmd
2026-01-29 03:17:25.306 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.28.20:5700/1) Recv SETFORMAT cmd
2026-01-29 03:17:25.306 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.28.20:5700/1) TRXD header version 1 -> 1
2026-01-29 03:17:25.307 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.28.20:5700/2) Recv RXTUNE cmd
2026-01-29 03:17:25.307 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.28.20:5700/2) Recv TXTUNE cmd
2026-01-29 03:17:25.307 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.28.20:5700/2) Recv SETFORMAT cmd
2026-01-29 03:17:25.307 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.28.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:17:25.307 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 03:17:25.307 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.28.20:5700/2) Recv NOMTXPOWER cmd
2026-01-29 03:17:25.307 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.28.20:5700/2) Recv SETFORMAT cmd
2026-01-29 03:17:25.307 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.28.20:5700/2) TRXD header version 1 -> 1
2026-01-29 03:17:25.309 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.28.20:5700/3) Recv RXTUNE cmd
2026-01-29 03:17:25.309 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.28.20:5700/3) Recv TXTUNE cmd
2026-01-29 03:17:25.309 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.28.20:5700/3) Recv SETFORMAT cmd
2026-01-29 03:17:25.309 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.28.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:17:25.309 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 03:17:25.309 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.28.20:5700/3) Recv NOMTXPOWER cmd
2026-01-29 03:17:25.309 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.28.20:5700/3) Recv SETFORMAT cmd
2026-01-29 03:17:25.309 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.28.20:5700/3) TRXD header version 1 -> 1
2026-01-29 03:17:25.312 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.28.20:5700) Recv RXTUNE cmd
2026-01-29 03:17:25.312 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETTSC
2026-01-29 03:17:25.312 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETTSC
2026-01-29 03:17:25.312 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.28.20:5700) Recv TXTUNE cmd
2026-01-29 03:17:25.312 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETTSC
2026-01-29 03:17:25.312 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETRXGAIN
2026-01-29 03:17:25.312 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETRXGAIN
2026-01-29 03:17:25.312 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETTSC
2026-01-29 03:17:25.312 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETRXGAIN
2026-01-29 03:17:25.312 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:17:25.312 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:17:25.312 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.28.20:5700) Recv NOMTXPOWER cmd
2026-01-29 03:17:25.312 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:17:25.312 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:17:25.312 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:17:25.312 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.28.20:5700) Recv POWERON CMD
2026-01-29 03:17:25.312 [INFO] ctrl_if_trx.py:109 (BTS@172.18.28.20:5700) Starting transceiver...
2026-01-29 03:17:25.312 [INFO] transceiver.py:243 Starting clock generator
2026-01-29 03:17:25.313 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-01-29 03:17:25.313 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:17:25.313 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:17:25.313 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:17:25.313 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETRXGAIN
2026-01-29 03:17:25.313 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:17:25.313 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:17:25.313 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:17:25.313 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:17:25.313 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:17:25.313 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:17:25.313 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:17:25.313 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:17:25.313 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:17:25.313 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:17:25.313 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:17:25.313 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:17:25.313 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:17:25.313 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:17:25.313 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:17:25.313 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:17:25.313 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:17:25.314 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:17:25.314 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:17:25.314 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:17:25.314 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:17:25.314 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:17:25.314 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:17:25.314 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:17:25.317 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-01-29 03:17:25.798 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-01-29 03:17:26.279 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-01-29 03:17:26.759 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-01-29 03:17:27.240 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-01-29 03:17:27.740 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-01-29 03:17:28.209 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-01-29 03:17:28.678 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-01-29 03:17:29.157 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-01-29 03:17:29.636 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-01-29 03:17:30.115 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-01-29 03:17:30.590 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-01-29 03:17:31.058 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-01-29 03:17:31.528 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-01-29 03:17:32.000 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-01-29 03:17:32.480 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-01-29 03:17:32.961 [DEBUG] clck_gen.py:113 IND CLOCK 1632
2026-01-29 03:17:33.440 [DEBUG] clck_gen.py:113 IND CLOCK 1734
2026-01-29 03:17:33.918 [DEBUG] clck_gen.py:113 IND CLOCK 1836
2026-01-29 03:17:34.396 [DEBUG] clck_gen.py:113 IND CLOCK 1938
2026-01-29 03:17:34.874 [DEBUG] clck_gen.py:113 IND CLOCK 2040
2026-01-29 03:17:35.354 [DEBUG] clck_gen.py:113 IND CLOCK 2142
2026-01-29 03:17:35.832 [DEBUG] clck_gen.py:113 IND CLOCK 2244
2026-01-29 03:17:36.312 [DEBUG] clck_gen.py:113 IND CLOCK 2346
2026-01-29 03:17:36.792 [DEBUG] clck_gen.py:113 IND CLOCK 2448
2026-01-29 03:17:37.272 [DEBUG] clck_gen.py:113 IND CLOCK 2550
2026-01-29 03:17:37.751 [DEBUG] clck_gen.py:113 IND CLOCK 2652
2026-01-29 03:17:38.232 [DEBUG] clck_gen.py:113 IND CLOCK 2754
2026-01-29 03:17:38.701 [DEBUG] clck_gen.py:113 IND CLOCK 2856
2026-01-29 03:17:39.170 [DEBUG] clck_gen.py:113 IND CLOCK 2958
2026-01-29 03:17:39.639 [DEBUG] clck_gen.py:113 IND CLOCK 3060
2026-01-29 03:17:40.107 [DEBUG] clck_gen.py:113 IND CLOCK 3162
2026-01-29 03:17:40.581 [DEBUG] clck_gen.py:113 IND CLOCK 3264
2026-01-29 03:17:41.060 [DEBUG] clck_gen.py:113 IND CLOCK 3366
2026-01-29 03:17:41.538 [DEBUG] clck_gen.py:113 IND CLOCK 3468
2026-01-29 03:17:42.016 [DEBUG] clck_gen.py:113 IND CLOCK 3570
2026-01-29 03:17:42.490 [DEBUG] clck_gen.py:113 IND CLOCK 3672
2026-01-29 03:17:42.959 [DEBUG] clck_gen.py:113 IND CLOCK 3774
2026-01-29 03:17:43.432 [DEBUG] clck_gen.py:113 IND CLOCK 3876
2026-01-29 03:17:43.908 [DEBUG] clck_gen.py:113 IND CLOCK 3978
2026-01-29 03:17:44.387 [DEBUG] clck_gen.py:113 IND CLOCK 4080
2026-01-29 03:17:44.867 [DEBUG] clck_gen.py:113 IND CLOCK 4182
2026-01-29 03:17:45.347 [DEBUG] clck_gen.py:113 IND CLOCK 4284
2026-01-29 03:17:45.826 [DEBUG] clck_gen.py:113 IND CLOCK 4386
2026-01-29 03:17:46.305 [DEBUG] clck_gen.py:113 IND CLOCK 4488
2026-01-29 03:17:46.784 [DEBUG] clck_gen.py:113 IND CLOCK 4590
2026-01-29 03:17:47.264 [DEBUG] clck_gen.py:113 IND CLOCK 4692
2026-01-29 03:17:47.734 [DEBUG] clck_gen.py:113 IND CLOCK 4794
2026-01-29 03:17:48.202 [DEBUG] clck_gen.py:113 IND CLOCK 4896
2026-01-29 03:17:48.676 [DEBUG] clck_gen.py:113 IND CLOCK 4998
2026-01-29 03:17:49.157 [DEBUG] clck_gen.py:113 IND CLOCK 5100
2026-01-29 03:17:49.340 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 03:17:49.340 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 03:17:49.340 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 03:17:49.340 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 03:17:49.341 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.28.20:5700) Recv POWEROFF cmd
2026-01-29 03:17:49.341 [INFO] ctrl_if_trx.py:117 (BTS@172.18.28.20:5700) Stopping transceiver...
2026-01-29 03:17:49.341 [INFO] transceiver.py:246 Stopping clock generator
2026-01-29 03:17:49.341 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=5141 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:17:49.341 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=5141 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:17:49.341 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=5141 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:17:49.342 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=5141 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:17:49.342 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=5141 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:17:49.342 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=5141 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:17:49.342 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=5141 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:17:54.344 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.28.20:5700) Recv POWEROFF cmd
2026-01-29 03:17:54.344 [INFO] ctrl_if_trx.py:117 (BTS@172.18.28.20:5700) Stopping transceiver...
2026-01-29 03:17:54.345 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 03:17:54.347 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 03:17:54.348 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 03:17:54.351 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 03:17:54.365 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 03:17:54.366 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.28.20:5700) Recv SETFORMAT cmd
2026-01-29 03:17:54.367 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.28.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:17:54.367 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.28.20:5700) Recv SETFORMAT cmd
2026-01-29 03:17:54.367 [INFO] ctrl_if_trx.py:201 (BTS@172.18.28.20:5700) TRXD header version 1 -> 1
2026-01-29 03:17:54.371 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.28.20:5700/1) Recv RXTUNE cmd
2026-01-29 03:17:54.371 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.28.20:5700/1) Recv TXTUNE cmd
2026-01-29 03:17:54.372 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.28.20:5700/1) Recv SETFORMAT cmd
2026-01-29 03:17:54.372 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.28.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:17:54.372 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 03:17:54.372 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.28.20:5700/1) Recv NOMTXPOWER cmd
2026-01-29 03:17:54.373 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.28.20:5700/1) Recv SETFORMAT cmd
2026-01-29 03:17:54.373 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.28.20:5700/1) TRXD header version 1 -> 1
2026-01-29 03:17:54.374 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.28.20:5700/2) Recv RXTUNE cmd
2026-01-29 03:17:54.374 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.28.20:5700/2) Recv TXTUNE cmd
2026-01-29 03:17:54.374 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.28.20:5700/2) Recv SETFORMAT cmd
2026-01-29 03:17:54.374 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.28.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:17:54.374 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 03:17:54.374 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.28.20:5700/2) Recv NOMTXPOWER cmd
2026-01-29 03:17:54.374 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.28.20:5700/2) Recv SETFORMAT cmd
2026-01-29 03:17:54.374 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.28.20:5700/2) TRXD header version 1 -> 1
2026-01-29 03:17:54.376 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.28.20:5700/3) Recv RXTUNE cmd
2026-01-29 03:17:54.376 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.28.20:5700/3) Recv TXTUNE cmd
2026-01-29 03:17:54.376 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.28.20:5700/3) Recv SETFORMAT cmd
2026-01-29 03:17:54.376 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.28.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:17:54.376 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 03:17:54.376 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.28.20:5700/3) Recv NOMTXPOWER cmd
2026-01-29 03:17:54.376 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.28.20:5700/3) Recv SETFORMAT cmd
2026-01-29 03:17:54.377 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.28.20:5700/3) TRXD header version 1 -> 1
2026-01-29 03:17:54.379 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.28.20:5700) Recv RXTUNE cmd
2026-01-29 03:17:54.379 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETTSC
2026-01-29 03:17:54.379 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETTSC
2026-01-29 03:17:54.379 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETTSC
2026-01-29 03:17:54.379 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.28.20:5700) Recv TXTUNE cmd
2026-01-29 03:17:54.379 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETRXGAIN
2026-01-29 03:17:54.379 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETRXGAIN
2026-01-29 03:17:54.379 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETRXGAIN
2026-01-29 03:17:54.379 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETTSC
2026-01-29 03:17:54.379 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:17:54.379 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:17:54.379 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:17:54.379 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.28.20:5700) Recv NOMTXPOWER cmd
2026-01-29 03:17:54.379 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:17:54.379 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:17:54.379 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:17:54.379 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.28.20:5700) Recv POWERON CMD
2026-01-29 03:17:54.379 [INFO] ctrl_if_trx.py:109 (BTS@172.18.28.20:5700) Starting transceiver...
2026-01-29 03:17:54.379 [INFO] transceiver.py:243 Starting clock generator
2026-01-29 03:17:54.380 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-01-29 03:17:54.380 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:17:54.380 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:17:54.380 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:17:54.380 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETRXGAIN
2026-01-29 03:17:54.380 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:17:54.380 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:17:54.380 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:17:54.380 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:17:54.380 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:17:54.380 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:17:54.380 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:17:54.380 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:17:54.380 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:17:54.380 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:17:54.380 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:17:54.380 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:17:54.380 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:17:54.380 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:17:54.380 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:17:54.380 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:17:54.380 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:17:54.380 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:17:54.380 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:17:54.380 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:17:54.381 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:17:54.381 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:17:54.381 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:17:54.384 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-01-29 03:17:54.861 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-01-29 03:17:55.330 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-01-29 03:17:55.799 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-01-29 03:17:56.276 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-01-29 03:17:56.754 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-01-29 03:17:57.232 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-01-29 03:17:57.710 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-01-29 03:17:58.190 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-01-29 03:17:58.662 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-01-29 03:17:59.135 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-01-29 03:17:59.614 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-01-29 03:18:00.096 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-01-29 03:18:00.575 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-01-29 03:18:01.054 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-01-29 03:18:01.532 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-01-29 03:18:02.010 [DEBUG] clck_gen.py:113 IND CLOCK 1632
2026-01-29 03:18:02.490 [DEBUG] clck_gen.py:113 IND CLOCK 1734
2026-01-29 03:18:02.969 [DEBUG] clck_gen.py:113 IND CLOCK 1836
2026-01-29 03:18:03.447 [DEBUG] clck_gen.py:113 IND CLOCK 1938
2026-01-29 03:18:03.925 [DEBUG] clck_gen.py:113 IND CLOCK 2040
2026-01-29 03:18:04.403 [DEBUG] clck_gen.py:113 IND CLOCK 2142
2026-01-29 03:18:04.876 [DEBUG] clck_gen.py:113 IND CLOCK 2244
2026-01-29 03:18:05.346 [DEBUG] clck_gen.py:113 IND CLOCK 2346
2026-01-29 03:18:05.826 [DEBUG] clck_gen.py:113 IND CLOCK 2448
2026-01-29 03:18:06.306 [DEBUG] clck_gen.py:113 IND CLOCK 2550
2026-01-29 03:18:06.784 [DEBUG] clck_gen.py:113 IND CLOCK 2652
2026-01-29 03:18:07.266 [DEBUG] clck_gen.py:113 IND CLOCK 2754
2026-01-29 03:18:07.744 [DEBUG] clck_gen.py:113 IND CLOCK 2856
2026-01-29 03:18:08.222 [DEBUG] clck_gen.py:113 IND CLOCK 2958
2026-01-29 03:18:08.700 [DEBUG] clck_gen.py:113 IND CLOCK 3060
2026-01-29 03:18:09.178 [DEBUG] clck_gen.py:113 IND CLOCK 3162
2026-01-29 03:18:09.656 [DEBUG] clck_gen.py:113 IND CLOCK 3264
2026-01-29 03:18:10.134 [DEBUG] clck_gen.py:113 IND CLOCK 3366
2026-01-29 03:18:10.614 [DEBUG] clck_gen.py:113 IND CLOCK 3468
2026-01-29 03:18:11.093 [DEBUG] clck_gen.py:113 IND CLOCK 3570
2026-01-29 03:18:11.572 [DEBUG] clck_gen.py:113 IND CLOCK 3672
2026-01-29 03:18:12.050 [DEBUG] clck_gen.py:113 IND CLOCK 3774
2026-01-29 03:18:12.528 [DEBUG] clck_gen.py:113 IND CLOCK 3876
2026-01-29 03:18:13.006 [DEBUG] clck_gen.py:113 IND CLOCK 3978
2026-01-29 03:18:13.484 [DEBUG] clck_gen.py:113 IND CLOCK 4080
2026-01-29 03:18:13.963 [DEBUG] clck_gen.py:113 IND CLOCK 4182
2026-01-29 03:18:14.441 [DEBUG] clck_gen.py:113 IND CLOCK 4284
2026-01-29 03:18:14.920 [DEBUG] clck_gen.py:113 IND CLOCK 4386
2026-01-29 03:18:15.398 [DEBUG] clck_gen.py:113 IND CLOCK 4488
2026-01-29 03:18:15.871 [DEBUG] clck_gen.py:113 IND CLOCK 4590
2026-01-29 03:18:16.351 [DEBUG] clck_gen.py:113 IND CLOCK 4692
2026-01-29 03:18:16.831 [DEBUG] clck_gen.py:113 IND CLOCK 4794
2026-01-29 03:18:17.311 [DEBUG] clck_gen.py:113 IND CLOCK 4896
2026-01-29 03:18:17.792 [DEBUG] clck_gen.py:113 IND CLOCK 4998
2026-01-29 03:18:18.274 [DEBUG] clck_gen.py:113 IND CLOCK 5100
2026-01-29 03:18:18.752 [DEBUG] clck_gen.py:113 IND CLOCK 5202
2026-01-29 03:18:19.230 [DEBUG] clck_gen.py:113 IND CLOCK 5304
2026-01-29 03:18:19.707 [DEBUG] clck_gen.py:113 IND CLOCK 5406
2026-01-29 03:18:20.185 [DEBUG] clck_gen.py:113 IND CLOCK 5508
2026-01-29 03:18:20.663 [DEBUG] clck_gen.py:113 IND CLOCK 5610
2026-01-29 03:18:21.144 [DEBUG] clck_gen.py:113 IND CLOCK 5712
2026-01-29 03:18:21.625 [DEBUG] clck_gen.py:113 IND CLOCK 5814
2026-01-29 03:18:22.103 [DEBUG] clck_gen.py:113 IND CLOCK 5916
2026-01-29 03:18:22.571 [DEBUG] clck_gen.py:113 IND CLOCK 6018
2026-01-29 03:18:23.041 [DEBUG] clck_gen.py:113 IND CLOCK 6120
2026-01-29 03:18:23.515 [DEBUG] clck_gen.py:113 IND CLOCK 6222
2026-01-29 03:18:23.993 [DEBUG] clck_gen.py:113 IND CLOCK 6324
2026-01-29 03:18:24.472 [DEBUG] clck_gen.py:113 IND CLOCK 6426
2026-01-29 03:18:24.950 [DEBUG] clck_gen.py:113 IND CLOCK 6528
2026-01-29 03:18:25.428 [DEBUG] clck_gen.py:113 IND CLOCK 6630
2026-01-29 03:18:25.906 [DEBUG] clck_gen.py:113 IND CLOCK 6732
2026-01-29 03:18:26.384 [DEBUG] clck_gen.py:113 IND CLOCK 6834
2026-01-29 03:18:26.862 [DEBUG] clck_gen.py:113 IND CLOCK 6936
2026-01-29 03:18:27.340 [DEBUG] clck_gen.py:113 IND CLOCK 7038
2026-01-29 03:18:27.818 [DEBUG] clck_gen.py:113 IND CLOCK 7140
2026-01-29 03:18:28.305 [DEBUG] clck_gen.py:113 IND CLOCK 7242
2026-01-29 03:18:28.786 [DEBUG] clck_gen.py:113 IND CLOCK 7344
2026-01-29 03:18:29.267 [DEBUG] clck_gen.py:113 IND CLOCK 7446
2026-01-29 03:18:29.748 [DEBUG] clck_gen.py:113 IND CLOCK 7548
2026-01-29 03:18:30.228 [DEBUG] clck_gen.py:113 IND CLOCK 7650
2026-01-29 03:18:30.703 [DEBUG] clck_gen.py:113 IND CLOCK 7752
2026-01-29 03:18:31.172 [DEBUG] clck_gen.py:113 IND CLOCK 7854
2026-01-29 03:18:31.412 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 03:18:31.642 [DEBUG] clck_gen.py:113 IND CLOCK 7956
2026-01-29 03:18:32.123 [DEBUG] clck_gen.py:113 IND CLOCK 8058
2026-01-29 03:18:32.413 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 03:18:32.605 [DEBUG] clck_gen.py:113 IND CLOCK 8160
2026-01-29 03:18:33.087 [DEBUG] clck_gen.py:113 IND CLOCK 8262
2026-01-29 03:18:33.414 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 03:18:33.565 [DEBUG] clck_gen.py:113 IND CLOCK 8364
2026-01-29 03:18:34.037 [DEBUG] clck_gen.py:113 IND CLOCK 8466
2026-01-29 03:18:34.415 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 03:18:34.508 [DEBUG] clck_gen.py:113 IND CLOCK 8568
2026-01-29 03:18:34.983 [DEBUG] clck_gen.py:113 IND CLOCK 8670
2026-01-29 03:18:35.416 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 03:18:35.465 [DEBUG] clck_gen.py:113 IND CLOCK 8772
2026-01-29 03:18:35.940 [DEBUG] clck_gen.py:113 IND CLOCK 8874
2026-01-29 03:18:36.408 [DEBUG] clck_gen.py:113 IND CLOCK 8976
2026-01-29 03:18:36.417 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 03:18:36.417 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 03:18:36.418 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 03:18:36.418 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 03:18:36.419 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 03:18:36.419 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.28.20:5700) Recv POWEROFF cmd
2026-01-29 03:18:36.419 [INFO] ctrl_if_trx.py:117 (BTS@172.18.28.20:5700) Stopping transceiver...
2026-01-29 03:18:36.419 [INFO] transceiver.py:246 Stopping clock generator
2026-01-29 03:18:41.423 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.28.20:5700) Recv POWEROFF cmd
2026-01-29 03:18:41.423 [INFO] ctrl_if_trx.py:117 (BTS@172.18.28.20:5700) Stopping transceiver...
2026-01-29 03:18:41.423 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 03:18:41.423 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 03:18:41.423 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 03:18:41.423 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 03:18:41.431 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 03:18:41.432 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.28.20:5700) Recv SETFORMAT cmd
2026-01-29 03:18:41.432 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.28.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:18:41.433 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.28.20:5700) Recv SETFORMAT cmd
2026-01-29 03:18:41.433 [INFO] ctrl_if_trx.py:201 (BTS@172.18.28.20:5700) TRXD header version 1 -> 1
2026-01-29 03:18:41.437 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.28.20:5700/1) Recv RXTUNE cmd
2026-01-29 03:18:41.437 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.28.20:5700/1) Recv TXTUNE cmd
2026-01-29 03:18:41.438 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.28.20:5700/1) Recv SETFORMAT cmd
2026-01-29 03:18:41.438 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.28.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:18:41.438 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 03:18:41.438 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.28.20:5700/1) Recv NOMTXPOWER cmd
2026-01-29 03:18:41.438 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.28.20:5700/1) Recv SETFORMAT cmd
2026-01-29 03:18:41.438 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.28.20:5700/1) TRXD header version 1 -> 1
2026-01-29 03:18:41.441 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.28.20:5700/2) Recv RXTUNE cmd
2026-01-29 03:18:41.441 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.28.20:5700/2) Recv TXTUNE cmd
2026-01-29 03:18:41.442 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.28.20:5700/2) Recv SETFORMAT cmd
2026-01-29 03:18:41.442 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.28.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:18:41.442 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 03:18:41.443 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.28.20:5700/2) Recv NOMTXPOWER cmd
2026-01-29 03:18:41.443 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.28.20:5700/2) Recv SETFORMAT cmd
2026-01-29 03:18:41.443 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.28.20:5700/2) TRXD header version 1 -> 1
2026-01-29 03:18:41.444 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.28.20:5700/3) Recv RXTUNE cmd
2026-01-29 03:18:41.444 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.28.20:5700/3) Recv TXTUNE cmd
2026-01-29 03:18:41.445 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.28.20:5700/3) Recv SETFORMAT cmd
2026-01-29 03:18:41.445 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.28.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:18:41.445 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 03:18:41.445 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.28.20:5700/3) Recv NOMTXPOWER cmd
2026-01-29 03:18:41.445 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.28.20:5700/3) Recv SETFORMAT cmd
2026-01-29 03:18:41.445 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.28.20:5700/3) TRXD header version 1 -> 1
2026-01-29 03:18:41.448 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.28.20:5700) Recv RXTUNE cmd
2026-01-29 03:18:41.448 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETTSC
2026-01-29 03:18:41.448 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETTSC
2026-01-29 03:18:41.448 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETTSC
2026-01-29 03:18:41.448 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.28.20:5700) Recv TXTUNE cmd
2026-01-29 03:18:41.448 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETRXGAIN
2026-01-29 03:18:41.448 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETRXGAIN
2026-01-29 03:18:41.448 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETRXGAIN
2026-01-29 03:18:41.448 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETTSC
2026-01-29 03:18:41.448 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:18:41.448 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:18:41.448 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:18:41.448 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.28.20:5700) Recv NOMTXPOWER cmd
2026-01-29 03:18:41.448 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:18:41.448 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:18:41.448 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:18:41.449 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.28.20:5700) Recv POWERON CMD
2026-01-29 03:18:41.449 [INFO] ctrl_if_trx.py:109 (BTS@172.18.28.20:5700) Starting transceiver...
2026-01-29 03:18:41.449 [INFO] transceiver.py:243 Starting clock generator
2026-01-29 03:18:41.449 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-01-29 03:18:41.449 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:18:41.449 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:18:41.449 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:18:41.449 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETRXGAIN
2026-01-29 03:18:41.449 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:18:41.449 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:18:41.449 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:18:41.449 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:18:41.449 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:18:41.449 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:18:41.449 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:18:41.450 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:18:41.450 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:18:41.450 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:18:41.450 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:18:41.450 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:18:41.450 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:18:41.450 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:18:41.450 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:18:41.450 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:18:41.450 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:18:41.450 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:18:41.450 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:18:41.450 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:18:41.450 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:18:41.450 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:18:41.450 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:18:41.454 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-01-29 03:18:41.935 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-01-29 03:18:41.988 [DEBUG] fake_trx.py:278 (BTS@172.18.28.20:5700) Recv FAKE_TOA cmd
2026-01-29 03:18:41.990 [DEBUG] fake_trx.py:297 (BTS@172.18.28.20:5700) Recv FAKE_RSSI cmd
2026-01-29 03:18:41.993 [DEBUG] fake_trx.py:322 (BTS@172.18.28.20:5700) Recv FAKE_CI cmd
2026-01-29 03:18:41.993 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:18:42.022 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 03:18:42.022 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 03:18:42.023 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 03:18:42.029 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 03:18:42.029 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 03:18:42.030 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 03:18:42.030 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.28.22:6700) Recv POWERON CMD
2026-01-29 03:18:42.030 [INFO] ctrl_if_trx.py:109 (MS@172.18.28.22:6700) Starting transceiver...
2026-01-29 03:18:42.074 [DEBUG] fake_trx.py:297 (BTS@172.18.28.20:5700) Recv FAKE_RSSI cmd
2026-01-29 03:18:42.089 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:18:42.093 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 03:18:42.093 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 03:18:42.094 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 03:18:42.094 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 03:18:42.412 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-01-29 03:18:42.453 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 03:18:42.454 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:18:42.456 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:18:42.460 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:18:42.890 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-01-29 03:18:43.368 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-01-29 03:18:43.393 [DEBUG] fake_trx.py:269 (MS@172.18.28.22:6700) Recv SETTA cmd
2026-01-29 03:18:43.455 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 03:18:43.455 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:18:43.456 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:18:43.461 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:18:43.846 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-01-29 03:18:44.324 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-01-29 03:18:44.455 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 03:18:44.455 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:18:44.457 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:18:44.462 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:18:44.802 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-01-29 03:18:45.280 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-01-29 03:18:45.456 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 03:18:45.456 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:18:45.457 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:18:45.463 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:18:45.758 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-01-29 03:18:46.235 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-01-29 03:18:46.319 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:18:46.321 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 03:18:46.322 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 03:18:46.322 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 03:18:46.339 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 03:18:46.339 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 03:18:46.339 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 03:18:46.341 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 03:18:46.341 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 03:18:46.341 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 03:18:46.341 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.28.22:6700) Recv POWERON CMD
2026-01-29 03:18:46.341 [INFO] ctrl_if_trx.py:109 (MS@172.18.28.22:6700) Starting transceiver...
2026-01-29 03:18:46.374 [DEBUG] fake_trx.py:297 (BTS@172.18.28.20:5700) Recv FAKE_RSSI cmd
2026-01-29 03:18:46.377 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:18:46.379 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.28.22:6700) Recv SETFH cmd
2026-01-29 03:18:46.379 [INFO] transceiver.py:201 (MS@172.18.28.22:6700) Frequency hopping configured: hsn=5, maio=0, ma_len=4
2026-01-29 03:18:46.379 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 03:18:46.379 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 03:18:46.457 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:18:46.458 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 03:18:46.458 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:18:46.464 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:18:46.712 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-01-29 03:18:47.191 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-01-29 03:18:47.669 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-01-29 03:18:48.148 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-01-29 03:18:48.627 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-01-29 03:18:49.107 [DEBUG] clck_gen.py:113 IND CLOCK 1632
2026-01-29 03:18:49.586 [DEBUG] clck_gen.py:113 IND CLOCK 1734
2026-01-29 03:18:50.065 [DEBUG] clck_gen.py:113 IND CLOCK 1836
2026-01-29 03:18:50.463 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:18:50.466 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 03:18:50.467 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 03:18:50.467 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 03:18:50.467 [INFO] transceiver.py:205 (MS@172.18.28.22:6700) Frequency hopping disabled
2026-01-29 03:18:50.487 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 03:18:50.487 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 03:18:50.487 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 03:18:50.489 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 03:18:50.489 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 03:18:50.489 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 03:18:50.489 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.28.22:6700) Recv POWERON CMD
2026-01-29 03:18:50.489 [INFO] ctrl_if_trx.py:109 (MS@172.18.28.22:6700) Starting transceiver...
2026-01-29 03:18:50.537 [DEBUG] fake_trx.py:297 (BTS@172.18.28.20:5700) Recv FAKE_RSSI cmd
2026-01-29 03:18:50.544 [DEBUG] clck_gen.py:113 IND CLOCK 1938
2026-01-29 03:18:50.548 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:18:50.550 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 03:18:50.550 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 03:18:50.550 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 03:18:50.551 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 03:18:50.980 [DEBUG] fake_trx.py:269 (MS@172.18.28.22:6700) Recv SETTA cmd
2026-01-29 03:18:51.021 [DEBUG] clck_gen.py:113 IND CLOCK 2040
2026-01-29 03:18:51.498 [DEBUG] clck_gen.py:113 IND CLOCK 2142
2026-01-29 03:18:51.976 [DEBUG] clck_gen.py:113 IND CLOCK 2244
2026-01-29 03:18:52.453 [DEBUG] clck_gen.py:113 IND CLOCK 2346
2026-01-29 03:18:52.931 [DEBUG] clck_gen.py:113 IND CLOCK 2448
2026-01-29 03:18:53.409 [DEBUG] clck_gen.py:113 IND CLOCK 2550
2026-01-29 03:18:53.887 [DEBUG] clck_gen.py:113 IND CLOCK 2652
2026-01-29 03:18:54.325 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:18:54.328 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 03:18:54.329 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 03:18:54.329 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 03:18:54.351 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 03:18:54.351 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 03:18:54.351 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 03:18:54.353 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 03:18:54.353 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 03:18:54.353 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 03:18:54.353 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.28.22:6700) Recv POWERON CMD
2026-01-29 03:18:54.353 [INFO] ctrl_if_trx.py:109 (MS@172.18.28.22:6700) Starting transceiver...
2026-01-29 03:18:54.354 [DEBUG] fake_trx.py:297 (BTS@172.18.28.20:5700) Recv FAKE_RSSI cmd
2026-01-29 03:18:54.357 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:18:54.358 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.28.22:6700) Recv SETFH cmd
2026-01-29 03:18:54.358 [INFO] transceiver.py:201 (MS@172.18.28.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2026-01-29 03:18:54.358 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 03:18:54.358 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 03:18:54.364 [DEBUG] clck_gen.py:113 IND CLOCK 2754
2026-01-29 03:18:54.837 [DEBUG] clck_gen.py:113 IND CLOCK 2856
2026-01-29 03:18:55.316 [DEBUG] clck_gen.py:113 IND CLOCK 2958
2026-01-29 03:18:55.706 [DEBUG] fake_trx.py:269 (MS@172.18.28.22:6700) Recv SETTA cmd
2026-01-29 03:18:55.794 [DEBUG] clck_gen.py:113 IND CLOCK 3060
2026-01-29 03:18:56.273 [DEBUG] clck_gen.py:113 IND CLOCK 3162
2026-01-29 03:18:56.663 [DEBUG] fake_trx.py:269 (MS@172.18.28.22:6700) Recv SETTA cmd
2026-01-29 03:18:56.752 [DEBUG] clck_gen.py:113 IND CLOCK 3264
2026-01-29 03:18:57.142 [DEBUG] fake_trx.py:269 (MS@172.18.28.22:6700) Recv SETTA cmd
2026-01-29 03:18:57.230 [DEBUG] clck_gen.py:113 IND CLOCK 3366
2026-01-29 03:18:57.708 [DEBUG] clck_gen.py:113 IND CLOCK 3468
2026-01-29 03:18:58.100 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:18:58.103 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 03:18:58.104 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 03:18:58.104 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 03:18:58.104 [INFO] transceiver.py:205 (MS@172.18.28.22:6700) Frequency hopping disabled
2026-01-29 03:18:58.115 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 03:18:58.115 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:18:58.116 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:18:58.116 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:18:58.118 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 03:18:58.119 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 03:18:58.119 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 03:18:58.119 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 03:18:58.119 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.28.20:5700) Recv POWEROFF cmd
2026-01-29 03:18:58.119 [INFO] ctrl_if_trx.py:117 (BTS@172.18.28.20:5700) Stopping transceiver...
2026-01-29 03:18:58.119 [INFO] transceiver.py:246 Stopping clock generator
2026-01-29 03:18:58.119 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=3559 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:18:58.120 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=3559 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:18:58.120 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=3559 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:19:03.118 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.28.20:5700) Recv POWEROFF cmd
2026-01-29 03:19:03.118 [INFO] ctrl_if_trx.py:117 (BTS@172.18.28.20:5700) Stopping transceiver...
2026-01-29 03:19:03.120 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 03:19:03.121 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 03:19:03.122 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 03:19:03.122 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 03:19:03.130 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 03:19:03.130 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.28.20:5700) Recv SETFORMAT cmd
2026-01-29 03:19:03.130 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.28.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:19:03.130 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.28.20:5700) Recv SETFORMAT cmd
2026-01-29 03:19:03.130 [INFO] ctrl_if_trx.py:201 (BTS@172.18.28.20:5700) TRXD header version 1 -> 1
2026-01-29 03:19:03.132 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.28.20:5700/1) Recv RXTUNE cmd
2026-01-29 03:19:03.132 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.28.20:5700/1) Recv TXTUNE cmd
2026-01-29 03:19:03.132 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.28.20:5700/1) Recv SETFORMAT cmd
2026-01-29 03:19:03.133 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.28.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:19:03.133 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 03:19:03.133 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.28.20:5700/1) Recv NOMTXPOWER cmd
2026-01-29 03:19:03.133 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.28.20:5700/1) Recv SETFORMAT cmd
2026-01-29 03:19:03.133 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.28.20:5700/1) TRXD header version 1 -> 1
2026-01-29 03:19:03.134 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.28.20:5700/2) Recv RXTUNE cmd
2026-01-29 03:19:03.134 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.28.20:5700/2) Recv TXTUNE cmd
2026-01-29 03:19:03.134 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.28.20:5700/2) Recv SETFORMAT cmd
2026-01-29 03:19:03.134 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.28.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:19:03.135 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 03:19:03.135 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.28.20:5700/2) Recv NOMTXPOWER cmd
2026-01-29 03:19:03.135 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.28.20:5700/2) Recv SETFORMAT cmd
2026-01-29 03:19:03.135 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.28.20:5700/2) TRXD header version 1 -> 1
2026-01-29 03:19:03.136 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.28.20:5700/3) Recv RXTUNE cmd
2026-01-29 03:19:03.136 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.28.20:5700/3) Recv TXTUNE cmd
2026-01-29 03:19:03.136 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.28.20:5700/3) Recv SETFORMAT cmd
2026-01-29 03:19:03.136 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.28.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:19:03.136 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 03:19:03.136 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.28.20:5700/3) Recv NOMTXPOWER cmd
2026-01-29 03:19:03.136 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.28.20:5700/3) Recv SETFORMAT cmd
2026-01-29 03:19:03.136 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.28.20:5700/3) TRXD header version 1 -> 1
2026-01-29 03:19:03.139 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.28.20:5700) Recv RXTUNE cmd
2026-01-29 03:19:03.139 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETTSC
2026-01-29 03:19:03.139 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETTSC
2026-01-29 03:19:03.139 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETTSC
2026-01-29 03:19:03.139 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.28.20:5700) Recv TXTUNE cmd
2026-01-29 03:19:03.139 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETRXGAIN
2026-01-29 03:19:03.139 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETRXGAIN
2026-01-29 03:19:03.139 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETRXGAIN
2026-01-29 03:19:03.139 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETTSC
2026-01-29 03:19:03.139 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:19:03.139 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:19:03.139 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:19:03.139 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.28.20:5700) Recv NOMTXPOWER cmd
2026-01-29 03:19:03.139 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:19:03.139 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:19:03.139 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:19:03.139 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.28.20:5700) Recv POWERON CMD
2026-01-29 03:19:03.139 [INFO] ctrl_if_trx.py:109 (BTS@172.18.28.20:5700) Starting transceiver...
2026-01-29 03:19:03.139 [INFO] transceiver.py:243 Starting clock generator
2026-01-29 03:19:03.139 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-01-29 03:19:03.139 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:19:03.139 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:19:03.139 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:19:03.139 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETRXGAIN
2026-01-29 03:19:03.140 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:19:03.140 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:19:03.140 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:19:03.140 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:19:03.140 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:19:03.140 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:19:03.140 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:19:03.140 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:19:03.140 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:19:03.140 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:19:03.140 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:19:03.140 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:19:03.140 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:19:03.140 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:19:03.140 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:19:03.140 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:19:03.140 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:19:03.140 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:19:03.140 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:19:03.140 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:19:03.140 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:19:03.140 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:19:03.140 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:19:03.144 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-01-29 03:19:03.625 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-01-29 03:19:03.665 [DEBUG] fake_trx.py:278 (BTS@172.18.28.20:5700) Recv FAKE_TOA cmd
2026-01-29 03:19:03.666 [DEBUG] fake_trx.py:297 (BTS@172.18.28.20:5700) Recv FAKE_RSSI cmd
2026-01-29 03:19:03.668 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:19:03.669 [DEBUG] fake_trx.py:322 (BTS@172.18.28.20:5700) Recv FAKE_CI cmd
2026-01-29 03:19:03.689 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 03:19:03.689 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 03:19:03.690 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 03:19:03.696 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 03:19:03.696 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 03:19:03.697 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 03:19:03.697 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.28.22:6700) Recv POWERON CMD
2026-01-29 03:19:03.697 [INFO] ctrl_if_trx.py:109 (MS@172.18.28.22:6700) Starting transceiver...
2026-01-29 03:19:03.719 [DEBUG] fake_trx.py:297 (BTS@172.18.28.20:5700) Recv FAKE_RSSI cmd
2026-01-29 03:19:03.730 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:19:03.733 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 03:19:03.733 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 03:19:03.733 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 03:19:03.734 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 03:19:04.103 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-01-29 03:19:04.142 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:19:04.143 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 03:19:04.143 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:19:04.144 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:19:04.581 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-01-29 03:19:04.597 [DEBUG] fake_trx.py:297 (BTS@172.18.28.20:5700) Recv FAKE_RSSI cmd
2026-01-29 03:19:04.600 [DEBUG] fake_trx.py:269 (MS@172.18.28.22:6700) Recv SETTA cmd
2026-01-29 03:19:05.059 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-01-29 03:19:05.084 [DEBUG] fake_trx.py:297 (BTS@172.18.28.20:5700) Recv FAKE_RSSI cmd
2026-01-29 03:19:05.143 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:19:05.143 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 03:19:05.144 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:19:05.145 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:19:05.537 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-01-29 03:19:05.571 [DEBUG] fake_trx.py:297 (BTS@172.18.28.20:5700) Recv FAKE_RSSI cmd
2026-01-29 03:19:06.015 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-01-29 03:19:06.058 [DEBUG] fake_trx.py:297 (BTS@172.18.28.20:5700) Recv FAKE_RSSI cmd
2026-01-29 03:19:06.144 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 03:19:06.145 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:19:06.145 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:19:06.146 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:19:06.493 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-01-29 03:19:06.546 [DEBUG] fake_trx.py:297 (BTS@172.18.28.20:5700) Recv FAKE_RSSI cmd
2026-01-29 03:19:06.971 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-01-29 03:19:07.033 [DEBUG] fake_trx.py:297 (BTS@172.18.28.20:5700) Recv FAKE_RSSI cmd
2026-01-29 03:19:07.146 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:19:07.146 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:19:07.146 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 03:19:07.146 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:19:07.449 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-01-29 03:19:07.520 [DEBUG] fake_trx.py:297 (BTS@172.18.28.20:5700) Recv FAKE_RSSI cmd
2026-01-29 03:19:07.926 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-01-29 03:19:08.007 [DEBUG] fake_trx.py:297 (BTS@172.18.28.20:5700) Recv FAKE_RSSI cmd
2026-01-29 03:19:08.147 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:19:08.147 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 03:19:08.148 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:19:08.148 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:19:08.404 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-01-29 03:19:08.494 [DEBUG] fake_trx.py:297 (BTS@172.18.28.20:5700) Recv FAKE_RSSI cmd
2026-01-29 03:19:08.882 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-01-29 03:19:08.980 [DEBUG] fake_trx.py:297 (BTS@172.18.28.20:5700) Recv FAKE_RSSI cmd
2026-01-29 03:19:09.359 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-01-29 03:19:09.467 [DEBUG] fake_trx.py:297 (BTS@172.18.28.20:5700) Recv FAKE_RSSI cmd
2026-01-29 03:19:09.837 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-01-29 03:19:09.954 [DEBUG] fake_trx.py:297 (BTS@172.18.28.20:5700) Recv FAKE_RSSI cmd
2026-01-29 03:19:10.314 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-01-29 03:19:10.441 [DEBUG] fake_trx.py:297 (BTS@172.18.28.20:5700) Recv FAKE_RSSI cmd
2026-01-29 03:19:10.792 [DEBUG] clck_gen.py:113 IND CLOCK 1632
2026-01-29 03:19:10.928 [DEBUG] fake_trx.py:297 (BTS@172.18.28.20:5700) Recv FAKE_RSSI cmd
2026-01-29 03:19:11.270 [DEBUG] clck_gen.py:113 IND CLOCK 1734
2026-01-29 03:19:11.415 [DEBUG] fake_trx.py:297 (BTS@172.18.28.20:5700) Recv FAKE_RSSI cmd
2026-01-29 03:19:11.748 [DEBUG] clck_gen.py:113 IND CLOCK 1836
2026-01-29 03:19:11.902 [DEBUG] fake_trx.py:297 (BTS@172.18.28.20:5700) Recv FAKE_RSSI cmd
2026-01-29 03:19:11.906 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:19:11.910 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 03:19:11.911 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 03:19:11.911 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 03:19:11.925 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 03:19:11.925 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 03:19:11.926 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 03:19:11.927 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 03:19:11.927 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 03:19:11.927 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 03:19:11.927 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.28.22:6700) Recv POWERON CMD
2026-01-29 03:19:11.927 [INFO] ctrl_if_trx.py:109 (MS@172.18.28.22:6700) Starting transceiver...
2026-01-29 03:19:11.929 [DEBUG] fake_trx.py:297 (BTS@172.18.28.20:5700) Recv FAKE_RSSI cmd
2026-01-29 03:19:11.932 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:19:11.933 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.28.22:6700) Recv SETFH cmd
2026-01-29 03:19:11.933 [INFO] transceiver.py:201 (MS@172.18.28.22:6700) Frequency hopping configured: hsn=5, maio=0, ma_len=4
2026-01-29 03:19:11.933 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 03:19:11.933 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 03:19:12.220 [DEBUG] clck_gen.py:113 IND CLOCK 1938
2026-01-29 03:19:12.623 [DEBUG] fake_trx.py:297 (BTS@172.18.28.20:5700) Recv FAKE_RSSI cmd
2026-01-29 03:19:12.692 [DEBUG] clck_gen.py:113 IND CLOCK 2040
2026-01-29 03:19:13.103 [DEBUG] fake_trx.py:297 (BTS@172.18.28.20:5700) Recv FAKE_RSSI cmd
2026-01-29 03:19:13.170 [DEBUG] clck_gen.py:113 IND CLOCK 2142
2026-01-29 03:19:13.593 [DEBUG] fake_trx.py:297 (BTS@172.18.28.20:5700) Recv FAKE_RSSI cmd
2026-01-29 03:19:13.649 [DEBUG] clck_gen.py:113 IND CLOCK 2244
2026-01-29 03:19:14.081 [DEBUG] fake_trx.py:297 (BTS@172.18.28.20:5700) Recv FAKE_RSSI cmd
2026-01-29 03:19:14.127 [DEBUG] clck_gen.py:113 IND CLOCK 2346
2026-01-29 03:19:14.569 [DEBUG] fake_trx.py:297 (BTS@172.18.28.20:5700) Recv FAKE_RSSI cmd
2026-01-29 03:19:14.606 [DEBUG] clck_gen.py:113 IND CLOCK 2448
2026-01-29 03:19:15.057 [DEBUG] fake_trx.py:297 (BTS@172.18.28.20:5700) Recv FAKE_RSSI cmd
2026-01-29 03:19:15.085 [DEBUG] clck_gen.py:113 IND CLOCK 2550
2026-01-29 03:19:15.545 [DEBUG] fake_trx.py:297 (BTS@172.18.28.20:5700) Recv FAKE_RSSI cmd
2026-01-29 03:19:15.563 [DEBUG] clck_gen.py:113 IND CLOCK 2652
2026-01-29 03:19:16.032 [DEBUG] fake_trx.py:297 (BTS@172.18.28.20:5700) Recv FAKE_RSSI cmd
2026-01-29 03:19:16.043 [DEBUG] clck_gen.py:113 IND CLOCK 2754
2026-01-29 03:19:16.520 [DEBUG] fake_trx.py:297 (BTS@172.18.28.20:5700) Recv FAKE_RSSI cmd
2026-01-29 03:19:16.521 [DEBUG] clck_gen.py:113 IND CLOCK 2856
2026-01-29 03:19:17.002 [DEBUG] clck_gen.py:113 IND CLOCK 2958
2026-01-29 03:19:17.018 [DEBUG] fake_trx.py:297 (BTS@172.18.28.20:5700) Recv FAKE_RSSI cmd
2026-01-29 03:19:17.480 [DEBUG] clck_gen.py:113 IND CLOCK 3060
2026-01-29 03:19:17.506 [DEBUG] fake_trx.py:297 (BTS@172.18.28.20:5700) Recv FAKE_RSSI cmd
2026-01-29 03:19:17.959 [DEBUG] clck_gen.py:113 IND CLOCK 3162
2026-01-29 03:19:17.994 [DEBUG] fake_trx.py:297 (BTS@172.18.28.20:5700) Recv FAKE_RSSI cmd
2026-01-29 03:19:18.438 [DEBUG] clck_gen.py:113 IND CLOCK 3264
2026-01-29 03:19:18.481 [DEBUG] fake_trx.py:297 (BTS@172.18.28.20:5700) Recv FAKE_RSSI cmd
2026-01-29 03:19:18.916 [DEBUG] clck_gen.py:113 IND CLOCK 3366
2026-01-29 03:19:18.970 [DEBUG] fake_trx.py:297 (BTS@172.18.28.20:5700) Recv FAKE_RSSI cmd
2026-01-29 03:19:19.395 [DEBUG] clck_gen.py:113 IND CLOCK 3468
2026-01-29 03:19:19.457 [DEBUG] fake_trx.py:297 (BTS@172.18.28.20:5700) Recv FAKE_RSSI cmd
2026-01-29 03:19:19.874 [DEBUG] clck_gen.py:113 IND CLOCK 3570
2026-01-29 03:19:19.945 [DEBUG] fake_trx.py:297 (BTS@172.18.28.20:5700) Recv FAKE_RSSI cmd
2026-01-29 03:19:19.950 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:19:19.953 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 03:19:19.953 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 03:19:19.953 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 03:19:19.954 [INFO] transceiver.py:205 (MS@172.18.28.22:6700) Frequency hopping disabled
2026-01-29 03:19:19.972 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 03:19:19.972 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 03:19:19.972 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 03:19:19.973 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 03:19:19.973 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 03:19:19.973 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 03:19:19.973 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.28.22:6700) Recv POWERON CMD
2026-01-29 03:19:19.973 [INFO] ctrl_if_trx.py:109 (MS@172.18.28.22:6700) Starting transceiver...
2026-01-29 03:19:20.014 [DEBUG] fake_trx.py:297 (BTS@172.18.28.20:5700) Recv FAKE_RSSI cmd
2026-01-29 03:19:20.025 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:19:20.028 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 03:19:20.028 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 03:19:20.028 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 03:19:20.028 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 03:19:20.310 [DEBUG] fake_trx.py:297 (BTS@172.18.28.20:5700) Recv FAKE_RSSI cmd
2026-01-29 03:19:20.351 [DEBUG] clck_gen.py:113 IND CLOCK 3672
2026-01-29 03:19:20.787 [DEBUG] fake_trx.py:297 (BTS@172.18.28.20:5700) Recv FAKE_RSSI cmd
2026-01-29 03:19:20.789 [DEBUG] fake_trx.py:269 (MS@172.18.28.22:6700) Recv SETTA cmd
2026-01-29 03:19:20.829 [DEBUG] clck_gen.py:113 IND CLOCK 3774
2026-01-29 03:19:21.265 [DEBUG] fake_trx.py:297 (BTS@172.18.28.20:5700) Recv FAKE_RSSI cmd
2026-01-29 03:19:21.307 [DEBUG] clck_gen.py:113 IND CLOCK 3876
2026-01-29 03:19:21.743 [DEBUG] fake_trx.py:297 (BTS@172.18.28.20:5700) Recv FAKE_RSSI cmd
2026-01-29 03:19:21.785 [DEBUG] clck_gen.py:113 IND CLOCK 3978
2026-01-29 03:19:22.221 [DEBUG] fake_trx.py:297 (BTS@172.18.28.20:5700) Recv FAKE_RSSI cmd
2026-01-29 03:19:22.263 [DEBUG] clck_gen.py:113 IND CLOCK 4080
2026-01-29 03:19:22.699 [DEBUG] fake_trx.py:297 (BTS@172.18.28.20:5700) Recv FAKE_RSSI cmd
2026-01-29 03:19:22.742 [DEBUG] clck_gen.py:113 IND CLOCK 4182
2026-01-29 03:19:23.177 [DEBUG] fake_trx.py:297 (BTS@172.18.28.20:5700) Recv FAKE_RSSI cmd
2026-01-29 03:19:23.219 [DEBUG] clck_gen.py:113 IND CLOCK 4284
2026-01-29 03:19:23.655 [DEBUG] fake_trx.py:297 (BTS@172.18.28.20:5700) Recv FAKE_RSSI cmd
2026-01-29 03:19:23.697 [DEBUG] clck_gen.py:113 IND CLOCK 4386
2026-01-29 03:19:24.133 [DEBUG] fake_trx.py:297 (BTS@172.18.28.20:5700) Recv FAKE_RSSI cmd
2026-01-29 03:19:24.175 [DEBUG] clck_gen.py:113 IND CLOCK 4488
2026-01-29 03:19:24.611 [DEBUG] fake_trx.py:297 (BTS@172.18.28.20:5700) Recv FAKE_RSSI cmd
2026-01-29 03:19:24.653 [DEBUG] clck_gen.py:113 IND CLOCK 4590
2026-01-29 03:19:25.089 [DEBUG] fake_trx.py:297 (BTS@172.18.28.20:5700) Recv FAKE_RSSI cmd
2026-01-29 03:19:25.131 [DEBUG] clck_gen.py:113 IND CLOCK 4692
2026-01-29 03:19:25.566 [DEBUG] fake_trx.py:297 (BTS@172.18.28.20:5700) Recv FAKE_RSSI cmd
2026-01-29 03:19:25.608 [DEBUG] clck_gen.py:113 IND CLOCK 4794
2026-01-29 03:19:26.044 [DEBUG] fake_trx.py:297 (BTS@172.18.28.20:5700) Recv FAKE_RSSI cmd
2026-01-29 03:19:26.086 [DEBUG] clck_gen.py:113 IND CLOCK 4896
2026-01-29 03:19:26.522 [DEBUG] fake_trx.py:297 (BTS@172.18.28.20:5700) Recv FAKE_RSSI cmd
2026-01-29 03:19:26.564 [DEBUG] clck_gen.py:113 IND CLOCK 4998
2026-01-29 03:19:27.000 [DEBUG] fake_trx.py:297 (BTS@172.18.28.20:5700) Recv FAKE_RSSI cmd
2026-01-29 03:19:27.042 [DEBUG] clck_gen.py:113 IND CLOCK 5100
2026-01-29 03:19:27.478 [DEBUG] fake_trx.py:297 (BTS@172.18.28.20:5700) Recv FAKE_RSSI cmd
2026-01-29 03:19:27.483 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:19:27.486 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 03:19:27.487 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 03:19:27.487 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 03:19:27.502 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 03:19:27.502 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 03:19:27.503 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 03:19:27.504 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 03:19:27.504 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 03:19:27.504 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 03:19:27.504 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.28.22:6700) Recv POWERON CMD
2026-01-29 03:19:27.504 [INFO] ctrl_if_trx.py:109 (MS@172.18.28.22:6700) Starting transceiver...
2026-01-29 03:19:27.510 [DEBUG] fake_trx.py:297 (BTS@172.18.28.20:5700) Recv FAKE_RSSI cmd
2026-01-29 03:19:27.513 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:19:27.514 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.28.22:6700) Recv SETFH cmd
2026-01-29 03:19:27.514 [INFO] transceiver.py:201 (MS@172.18.28.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2026-01-29 03:19:27.514 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 03:19:27.514 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 03:19:27.520 [DEBUG] clck_gen.py:113 IND CLOCK 5202
2026-01-29 03:19:27.911 [DEBUG] fake_trx.py:297 (BTS@172.18.28.20:5700) Recv FAKE_RSSI cmd
2026-01-29 03:19:27.998 [DEBUG] clck_gen.py:113 IND CLOCK 5304
2026-01-29 03:19:28.396 [DEBUG] fake_trx.py:297 (BTS@172.18.28.20:5700) Recv FAKE_RSSI cmd
2026-01-29 03:19:28.399 [DEBUG] fake_trx.py:269 (MS@172.18.28.22:6700) Recv SETTA cmd
2026-01-29 03:19:28.477 [DEBUG] clck_gen.py:113 IND CLOCK 5406
2026-01-29 03:19:28.867 [DEBUG] fake_trx.py:297 (BTS@172.18.28.20:5700) Recv FAKE_RSSI cmd
2026-01-29 03:19:28.955 [DEBUG] clck_gen.py:113 IND CLOCK 5508
2026-01-29 03:19:29.345 [DEBUG] fake_trx.py:297 (BTS@172.18.28.20:5700) Recv FAKE_RSSI cmd
2026-01-29 03:19:29.433 [DEBUG] clck_gen.py:113 IND CLOCK 5610
2026-01-29 03:19:29.824 [DEBUG] fake_trx.py:297 (BTS@172.18.28.20:5700) Recv FAKE_RSSI cmd
2026-01-29 03:19:29.912 [DEBUG] clck_gen.py:113 IND CLOCK 5712
2026-01-29 03:19:30.302 [DEBUG] fake_trx.py:297 (BTS@172.18.28.20:5700) Recv FAKE_RSSI cmd
2026-01-29 03:19:30.391 [DEBUG] clck_gen.py:113 IND CLOCK 5814
2026-01-29 03:19:30.781 [DEBUG] fake_trx.py:297 (BTS@172.18.28.20:5700) Recv FAKE_RSSI cmd
2026-01-29 03:19:30.870 [DEBUG] clck_gen.py:113 IND CLOCK 5916
2026-01-29 03:19:31.261 [DEBUG] fake_trx.py:297 (BTS@172.18.28.20:5700) Recv FAKE_RSSI cmd
2026-01-29 03:19:31.349 [DEBUG] clck_gen.py:113 IND CLOCK 6018
2026-01-29 03:19:31.739 [DEBUG] fake_trx.py:297 (BTS@172.18.28.20:5700) Recv FAKE_RSSI cmd
2026-01-29 03:19:31.828 [DEBUG] clck_gen.py:113 IND CLOCK 6120
2026-01-29 03:19:32.218 [DEBUG] fake_trx.py:297 (BTS@172.18.28.20:5700) Recv FAKE_RSSI cmd
2026-01-29 03:19:32.305 [DEBUG] clck_gen.py:113 IND CLOCK 6222
2026-01-29 03:19:32.694 [DEBUG] fake_trx.py:297 (BTS@172.18.28.20:5700) Recv FAKE_RSSI cmd
2026-01-29 03:19:32.783 [DEBUG] clck_gen.py:113 IND CLOCK 6324
2026-01-29 03:19:33.174 [DEBUG] fake_trx.py:297 (BTS@172.18.28.20:5700) Recv FAKE_RSSI cmd
2026-01-29 03:19:33.261 [DEBUG] clck_gen.py:113 IND CLOCK 6426
2026-01-29 03:19:33.651 [DEBUG] fake_trx.py:297 (BTS@172.18.28.20:5700) Recv FAKE_RSSI cmd
2026-01-29 03:19:33.739 [DEBUG] clck_gen.py:113 IND CLOCK 6528
2026-01-29 03:19:34.130 [DEBUG] fake_trx.py:297 (BTS@172.18.28.20:5700) Recv FAKE_RSSI cmd
2026-01-29 03:19:34.211 [DEBUG] clck_gen.py:113 IND CLOCK 6630
2026-01-29 03:19:34.599 [DEBUG] fake_trx.py:297 (BTS@172.18.28.20:5700) Recv FAKE_RSSI cmd
2026-01-29 03:19:34.689 [DEBUG] clck_gen.py:113 IND CLOCK 6732
2026-01-29 03:19:35.080 [DEBUG] fake_trx.py:297 (BTS@172.18.28.20:5700) Recv FAKE_RSSI cmd
2026-01-29 03:19:35.085 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:19:35.087 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 03:19:35.088 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 03:19:35.088 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 03:19:35.088 [INFO] transceiver.py:205 (MS@172.18.28.22:6700) Frequency hopping disabled
2026-01-29 03:19:35.097 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 03:19:35.098 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:19:35.098 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:19:35.098 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:19:35.102 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 03:19:35.102 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 03:19:35.102 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 03:19:35.102 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.28.20:5700) Recv POWEROFF cmd
2026-01-29 03:19:35.102 [INFO] ctrl_if_trx.py:117 (BTS@172.18.28.20:5700) Stopping transceiver...
2026-01-29 03:19:35.102 [INFO] transceiver.py:246 Stopping clock generator
2026-01-29 03:19:35.102 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 03:19:35.102 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=6822 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:19:35.102 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=6822 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:19:35.102 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=6822 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:19:35.102 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=6822 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:19:35.102 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=6822 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:19:35.102 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=6822 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:19:35.102 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=6822 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:19:35.102 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=6822 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:19:35.102 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=6823 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:19:35.102 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=6823 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:19:35.102 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=6823 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:19:35.102 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=6823 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:19:35.102 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=6823 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:19:35.102 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=6823 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:19:35.102 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=6823 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:19:40.101 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.28.20:5700) Recv POWEROFF cmd
2026-01-29 03:19:40.101 [INFO] ctrl_if_trx.py:117 (BTS@172.18.28.20:5700) Stopping transceiver...
2026-01-29 03:19:40.102 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 03:19:40.103 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 03:19:40.104 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 03:19:40.104 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 03:19:40.109 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 03:19:40.110 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.28.20:5700) Recv SETFORMAT cmd
2026-01-29 03:19:40.110 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.28.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:19:40.110 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.28.20:5700) Recv SETFORMAT cmd
2026-01-29 03:19:40.111 [INFO] ctrl_if_trx.py:201 (BTS@172.18.28.20:5700) TRXD header version 1 -> 1
2026-01-29 03:19:40.114 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.28.20:5700/1) Recv RXTUNE cmd
2026-01-29 03:19:40.114 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.28.20:5700/1) Recv TXTUNE cmd
2026-01-29 03:19:40.115 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.28.20:5700/1) Recv SETFORMAT cmd
2026-01-29 03:19:40.115 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.28.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:19:40.115 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 03:19:40.115 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.28.20:5700/1) Recv NOMTXPOWER cmd
2026-01-29 03:19:40.116 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.28.20:5700/1) Recv SETFORMAT cmd
2026-01-29 03:19:40.116 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.28.20:5700/1) TRXD header version 1 -> 1
2026-01-29 03:19:40.117 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.28.20:5700/2) Recv RXTUNE cmd
2026-01-29 03:19:40.117 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.28.20:5700/2) Recv TXTUNE cmd
2026-01-29 03:19:40.117 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.28.20:5700/2) Recv SETFORMAT cmd
2026-01-29 03:19:40.117 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.28.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:19:40.117 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 03:19:40.117 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.28.20:5700/2) Recv NOMTXPOWER cmd
2026-01-29 03:19:40.117 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.28.20:5700/2) Recv SETFORMAT cmd
2026-01-29 03:19:40.117 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.28.20:5700/2) TRXD header version 1 -> 1
2026-01-29 03:19:40.119 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.28.20:5700/3) Recv RXTUNE cmd
2026-01-29 03:19:40.120 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.28.20:5700/3) Recv TXTUNE cmd
2026-01-29 03:19:40.120 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.28.20:5700/3) Recv SETFORMAT cmd
2026-01-29 03:19:40.120 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.28.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:19:40.120 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 03:19:40.120 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.28.20:5700/3) Recv NOMTXPOWER cmd
2026-01-29 03:19:40.120 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.28.20:5700/3) Recv SETFORMAT cmd
2026-01-29 03:19:40.120 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.28.20:5700/3) TRXD header version 1 -> 1
2026-01-29 03:19:40.123 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.28.20:5700) Recv RXTUNE cmd
2026-01-29 03:19:40.123 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETTSC
2026-01-29 03:19:40.123 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETTSC
2026-01-29 03:19:40.123 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETTSC
2026-01-29 03:19:40.123 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.28.20:5700) Recv TXTUNE cmd
2026-01-29 03:19:40.123 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETRXGAIN
2026-01-29 03:19:40.123 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETRXGAIN
2026-01-29 03:19:40.123 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETRXGAIN
2026-01-29 03:19:40.123 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETTSC
2026-01-29 03:19:40.123 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:19:40.123 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:19:40.123 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:19:40.123 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.28.20:5700) Recv NOMTXPOWER cmd
2026-01-29 03:19:40.123 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:19:40.123 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:19:40.123 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:19:40.123 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.28.20:5700) Recv POWERON CMD
2026-01-29 03:19:40.123 [INFO] ctrl_if_trx.py:109 (BTS@172.18.28.20:5700) Starting transceiver...
2026-01-29 03:19:40.123 [INFO] transceiver.py:243 Starting clock generator
2026-01-29 03:19:40.123 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-01-29 03:19:40.124 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:19:40.124 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:19:40.124 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:19:40.124 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETRXGAIN
2026-01-29 03:19:40.124 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:19:40.124 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:19:40.124 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:19:40.124 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:19:40.124 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:19:40.124 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:19:40.124 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:19:40.124 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:19:40.124 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:19:40.124 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:19:40.124 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:19:40.124 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:19:40.124 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:19:40.125 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:19:40.125 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:19:40.125 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:19:40.125 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:19:40.125 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:19:40.125 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:19:40.125 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:19:40.125 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:19:40.125 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:19:40.125 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:19:40.128 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-01-29 03:19:40.608 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-01-29 03:19:40.648 [DEBUG] fake_trx.py:278 (BTS@172.18.28.20:5700) Recv FAKE_TOA cmd
2026-01-29 03:19:40.649 [DEBUG] fake_trx.py:297 (BTS@172.18.28.20:5700) Recv FAKE_RSSI cmd
2026-01-29 03:19:40.650 [DEBUG] fake_trx.py:322 (BTS@172.18.28.20:5700) Recv FAKE_CI cmd
2026-01-29 03:19:40.650 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:19:40.662 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 03:19:40.662 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 03:19:40.662 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 03:19:40.668 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 03:19:40.668 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 03:19:40.668 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 03:19:40.668 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.28.22:6700) Recv POWERON CMD
2026-01-29 03:19:40.668 [INFO] ctrl_if_trx.py:109 (MS@172.18.28.22:6700) Starting transceiver...
2026-01-29 03:19:40.705 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:19:40.711 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 03:19:40.712 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 03:19:40.712 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 03:19:40.712 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 03:19:41.086 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-01-29 03:19:41.127 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 03:19:41.128 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:19:41.130 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:19:41.132 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:19:41.564 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-01-29 03:19:42.042 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-01-29 03:19:42.128 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 03:19:42.130 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:19:42.131 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:19:42.133 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:19:42.520 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-01-29 03:19:42.814 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:19:42.818 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 03:19:42.823 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 03:19:42.823 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 03:19:42.842 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 03:19:42.842 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 03:19:42.842 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 03:19:42.844 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 03:19:42.844 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 03:19:42.844 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 03:19:42.844 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.28.22:6700) Recv POWERON CMD
2026-01-29 03:19:42.844 [INFO] ctrl_if_trx.py:109 (MS@172.18.28.22:6700) Starting transceiver...
2026-01-29 03:19:42.898 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:19:42.904 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 03:19:42.904 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 03:19:42.905 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 03:19:42.905 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 03:19:42.997 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-01-29 03:19:43.130 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 03:19:43.130 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:19:43.132 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:19:43.133 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:19:43.475 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-01-29 03:19:43.953 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-01-29 03:19:44.130 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 03:19:44.130 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:19:44.133 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:19:44.133 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:19:44.432 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-01-29 03:19:44.909 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-01-29 03:19:45.010 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:19:45.013 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 03:19:45.018 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 03:19:45.018 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 03:19:45.036 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 03:19:45.036 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 03:19:45.036 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 03:19:45.037 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 03:19:45.037 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 03:19:45.037 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 03:19:45.037 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.28.22:6700) Recv POWERON CMD
2026-01-29 03:19:45.037 [INFO] ctrl_if_trx.py:109 (MS@172.18.28.22:6700) Starting transceiver...
2026-01-29 03:19:45.046 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:19:45.047 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 03:19:45.047 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 03:19:45.047 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 03:19:45.047 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 03:19:45.131 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:19:45.132 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 03:19:45.134 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:19:45.135 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:19:45.387 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-01-29 03:19:45.866 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-01-29 03:19:46.344 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-01-29 03:19:46.822 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-01-29 03:19:47.140 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:19:47.143 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 03:19:47.149 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 03:19:47.149 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 03:19:47.157 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 03:19:47.158 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:19:47.158 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:19:47.158 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:19:47.161 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 03:19:47.162 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 03:19:47.162 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 03:19:47.162 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 03:19:47.162 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.28.20:5700) Recv POWEROFF cmd
2026-01-29 03:19:47.162 [INFO] ctrl_if_trx.py:117 (BTS@172.18.28.20:5700) Stopping transceiver...
2026-01-29 03:19:47.162 [INFO] transceiver.py:246 Stopping clock generator
2026-01-29 03:19:47.163 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=1502 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:19:47.163 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=1502 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:19:47.163 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=1502 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:19:47.163 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=1502 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:19:47.163 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=1502 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:19:47.163 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=1502 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:19:47.163 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=1503 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:19:47.164 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=1503 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:19:47.164 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=1503 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:19:47.164 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=1503 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:19:47.164 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=1503 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:19:47.164 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=1503 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:19:47.164 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=1503 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:19:47.164 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=1503 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:19:52.161 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.28.20:5700) Recv POWEROFF cmd
2026-01-29 03:19:52.161 [INFO] ctrl_if_trx.py:117 (BTS@172.18.28.20:5700) Stopping transceiver...
2026-01-29 03:19:52.163 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 03:19:52.164 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 03:19:52.164 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 03:19:52.164 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 03:19:52.169 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 03:19:52.170 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.28.20:5700) Recv SETFORMAT cmd
2026-01-29 03:19:52.170 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.28.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:19:52.170 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.28.20:5700) Recv SETFORMAT cmd
2026-01-29 03:19:52.170 [INFO] ctrl_if_trx.py:201 (BTS@172.18.28.20:5700) TRXD header version 1 -> 1
2026-01-29 03:19:52.172 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.28.20:5700/1) Recv RXTUNE cmd
2026-01-29 03:19:52.172 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.28.20:5700/1) Recv TXTUNE cmd
2026-01-29 03:19:52.172 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.28.20:5700/1) Recv SETFORMAT cmd
2026-01-29 03:19:52.172 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.28.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:19:52.173 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 03:19:52.173 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.28.20:5700/1) Recv NOMTXPOWER cmd
2026-01-29 03:19:52.173 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.28.20:5700/1) Recv SETFORMAT cmd
2026-01-29 03:19:52.173 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.28.20:5700/1) TRXD header version 1 -> 1
2026-01-29 03:19:52.174 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.28.20:5700/2) Recv RXTUNE cmd
2026-01-29 03:19:52.174 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.28.20:5700/2) Recv TXTUNE cmd
2026-01-29 03:19:52.174 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.28.20:5700/2) Recv SETFORMAT cmd
2026-01-29 03:19:52.174 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.28.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:19:52.174 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 03:19:52.174 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.28.20:5700/2) Recv NOMTXPOWER cmd
2026-01-29 03:19:52.174 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.28.20:5700/2) Recv SETFORMAT cmd
2026-01-29 03:19:52.174 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.28.20:5700/2) TRXD header version 1 -> 1
2026-01-29 03:19:52.176 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.28.20:5700/3) Recv RXTUNE cmd
2026-01-29 03:19:52.176 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.28.20:5700/3) Recv TXTUNE cmd
2026-01-29 03:19:52.177 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.28.20:5700/3) Recv SETFORMAT cmd
2026-01-29 03:19:52.177 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.28.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:19:52.177 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.28.20:5700/3) Recv NOMTXPOWER cmd
2026-01-29 03:19:52.177 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.28.20:5700/3) Recv SETFORMAT cmd
2026-01-29 03:19:52.177 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.28.20:5700/3) TRXD header version 1 -> 1
2026-01-29 03:19:52.177 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 03:19:52.182 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.28.20:5700) Recv RXTUNE cmd
2026-01-29 03:19:52.182 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETTSC
2026-01-29 03:19:52.182 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETTSC
2026-01-29 03:19:52.182 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETTSC
2026-01-29 03:19:52.182 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.28.20:5700) Recv TXTUNE cmd
2026-01-29 03:19:52.182 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETRXGAIN
2026-01-29 03:19:52.182 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETRXGAIN
2026-01-29 03:19:52.182 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETRXGAIN
2026-01-29 03:19:52.182 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETTSC
2026-01-29 03:19:52.182 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:19:52.182 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:19:52.182 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:19:52.182 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.28.20:5700) Recv NOMTXPOWER cmd
2026-01-29 03:19:52.182 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:19:52.182 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:19:52.182 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:19:52.183 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.28.20:5700) Recv POWERON CMD
2026-01-29 03:19:52.183 [INFO] ctrl_if_trx.py:109 (BTS@172.18.28.20:5700) Starting transceiver...
2026-01-29 03:19:52.183 [INFO] transceiver.py:243 Starting clock generator
2026-01-29 03:19:52.183 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-01-29 03:19:52.183 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:19:52.183 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:19:52.183 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:19:52.183 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETRXGAIN
2026-01-29 03:19:52.183 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:19:52.183 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:19:52.183 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:19:52.183 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:19:52.183 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:19:52.183 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:19:52.183 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:19:52.183 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:19:52.183 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:19:52.183 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:19:52.183 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:19:52.183 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:19:52.183 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:19:52.183 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:19:52.183 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:19:52.183 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:19:52.183 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:19:52.183 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:19:52.183 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:19:52.183 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:19:52.183 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:19:52.183 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:19:52.183 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:19:52.187 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-01-29 03:19:52.670 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-01-29 03:19:52.713 [DEBUG] fake_trx.py:278 (BTS@172.18.28.20:5700) Recv FAKE_TOA cmd
2026-01-29 03:19:52.715 [DEBUG] fake_trx.py:297 (BTS@172.18.28.20:5700) Recv FAKE_RSSI cmd
2026-01-29 03:19:52.718 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:19:52.718 [DEBUG] fake_trx.py:322 (BTS@172.18.28.20:5700) Recv FAKE_CI cmd
2026-01-29 03:19:52.741 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 03:19:52.741 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 03:19:52.741 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 03:19:52.744 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 03:19:52.744 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 03:19:52.745 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 03:19:52.745 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.28.22:6700) Recv POWERON CMD
2026-01-29 03:19:52.745 [INFO] ctrl_if_trx.py:109 (MS@172.18.28.22:6700) Starting transceiver...
2026-01-29 03:19:52.767 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:19:52.771 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.28.22:6700) Recv SETFH cmd
2026-01-29 03:19:52.771 [INFO] transceiver.py:201 (MS@172.18.28.22:6700) Frequency hopping configured: hsn=5, maio=0, ma_len=4
2026-01-29 03:19:52.771 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 03:19:52.771 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 03:19:53.148 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-01-29 03:19:53.186 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 03:19:53.187 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:19:53.189 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:19:53.192 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:19:53.627 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-01-29 03:19:54.106 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-01-29 03:19:54.187 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 03:19:54.187 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:19:54.190 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:19:54.193 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:19:54.585 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-01-29 03:19:54.875 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:19:54.878 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 03:19:54.884 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 03:19:54.884 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 03:19:54.885 [INFO] transceiver.py:205 (MS@172.18.28.22:6700) Frequency hopping disabled
2026-01-29 03:19:54.905 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 03:19:54.905 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 03:19:54.905 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 03:19:54.906 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 03:19:54.906 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 03:19:54.906 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 03:19:54.906 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.28.22:6700) Recv POWERON CMD
2026-01-29 03:19:54.906 [INFO] ctrl_if_trx.py:109 (MS@172.18.28.22:6700) Starting transceiver...
2026-01-29 03:19:54.911 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:19:54.912 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.28.22:6700) Recv SETFH cmd
2026-01-29 03:19:54.912 [INFO] transceiver.py:201 (MS@172.18.28.22:6700) Frequency hopping configured: hsn=5, maio=0, ma_len=4
2026-01-29 03:19:54.912 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 03:19:54.912 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 03:19:55.063 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-01-29 03:19:55.188 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:19:55.189 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 03:19:55.192 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:19:55.194 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:19:55.541 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-01-29 03:19:56.021 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-01-29 03:19:56.190 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 03:19:56.190 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:19:56.192 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:19:56.196 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:19:56.499 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-01-29 03:19:56.978 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-01-29 03:19:57.015 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:19:57.018 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 03:19:57.024 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 03:19:57.024 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 03:19:57.024 [INFO] transceiver.py:205 (MS@172.18.28.22:6700) Frequency hopping disabled
2026-01-29 03:19:57.033 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 03:19:57.033 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:19:57.033 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:19:57.033 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:19:57.036 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 03:19:57.036 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 03:19:57.036 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 03:19:57.037 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.28.20:5700) Recv POWEROFF cmd
2026-01-29 03:19:57.037 [INFO] ctrl_if_trx.py:117 (BTS@172.18.28.20:5700) Stopping transceiver...
2026-01-29 03:19:57.037 [INFO] transceiver.py:246 Stopping clock generator
2026-01-29 03:19:57.037 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 03:19:57.037 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=1034 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:19:57.037 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=1034 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:19:57.037 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=1034 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:19:57.038 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=1034 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:19:57.038 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=1034 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:19:57.038 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=1034 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:19:57.038 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=1034 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:20:02.035 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.28.20:5700) Recv POWEROFF cmd
2026-01-29 03:20:02.035 [INFO] ctrl_if_trx.py:117 (BTS@172.18.28.20:5700) Stopping transceiver...
2026-01-29 03:20:02.036 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 03:20:02.038 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 03:20:02.039 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 03:20:02.041 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 03:20:02.044 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 03:20:02.044 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.28.20:5700) Recv SETFORMAT cmd
2026-01-29 03:20:02.044 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.28.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:20:02.045 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.28.20:5700) Recv SETFORMAT cmd
2026-01-29 03:20:02.045 [INFO] ctrl_if_trx.py:201 (BTS@172.18.28.20:5700) TRXD header version 1 -> 1
2026-01-29 03:20:02.046 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.28.20:5700/1) Recv RXTUNE cmd
2026-01-29 03:20:02.046 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.28.20:5700/1) Recv TXTUNE cmd
2026-01-29 03:20:02.047 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.28.20:5700/1) Recv SETFORMAT cmd
2026-01-29 03:20:02.047 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.28.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:20:02.047 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 03:20:02.047 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.28.20:5700/1) Recv NOMTXPOWER cmd
2026-01-29 03:20:02.047 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.28.20:5700/1) Recv SETFORMAT cmd
2026-01-29 03:20:02.048 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.28.20:5700/1) TRXD header version 1 -> 1
2026-01-29 03:20:02.048 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.28.20:5700/2) Recv RXTUNE cmd
2026-01-29 03:20:02.048 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.28.20:5700/2) Recv TXTUNE cmd
2026-01-29 03:20:02.049 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.28.20:5700/2) Recv SETFORMAT cmd
2026-01-29 03:20:02.049 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.28.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:20:02.049 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 03:20:02.049 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.28.20:5700/2) Recv NOMTXPOWER cmd
2026-01-29 03:20:02.049 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.28.20:5700/2) Recv SETFORMAT cmd
2026-01-29 03:20:02.049 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.28.20:5700/2) TRXD header version 1 -> 1
2026-01-29 03:20:02.050 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.28.20:5700/3) Recv RXTUNE cmd
2026-01-29 03:20:02.050 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.28.20:5700/3) Recv TXTUNE cmd
2026-01-29 03:20:02.050 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.28.20:5700/3) Recv SETFORMAT cmd
2026-01-29 03:20:02.050 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.28.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:20:02.050 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 03:20:02.051 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.28.20:5700/3) Recv NOMTXPOWER cmd
2026-01-29 03:20:02.051 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.28.20:5700/3) Recv SETFORMAT cmd
2026-01-29 03:20:02.051 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.28.20:5700/3) TRXD header version 1 -> 1
2026-01-29 03:20:02.053 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.28.20:5700) Recv RXTUNE cmd
2026-01-29 03:20:02.053 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETTSC
2026-01-29 03:20:02.053 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETTSC
2026-01-29 03:20:02.053 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETTSC
2026-01-29 03:20:02.053 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.28.20:5700) Recv TXTUNE cmd
2026-01-29 03:20:02.053 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETRXGAIN
2026-01-29 03:20:02.053 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETRXGAIN
2026-01-29 03:20:02.053 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETRXGAIN
2026-01-29 03:20:02.053 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETTSC
2026-01-29 03:20:02.053 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:20:02.053 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:20:02.053 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:20:02.053 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.28.20:5700) Recv NOMTXPOWER cmd
2026-01-29 03:20:02.053 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:20:02.053 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:20:02.053 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.28.20:5700) Recv POWERON CMD
2026-01-29 03:20:02.053 [INFO] ctrl_if_trx.py:109 (BTS@172.18.28.20:5700) Starting transceiver...
2026-01-29 03:20:02.053 [INFO] transceiver.py:243 Starting clock generator
2026-01-29 03:20:02.053 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-01-29 03:20:02.053 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:20:02.053 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:20:02.053 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:20:02.053 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETRXGAIN
2026-01-29 03:20:02.053 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:20:02.053 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:20:02.053 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:20:02.053 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:20:02.054 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:20:02.054 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:20:02.054 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:20:02.054 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:20:02.054 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:20:02.054 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:20:02.054 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:20:02.054 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:20:02.054 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:20:02.054 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:20:02.054 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:20:02.054 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:20:02.054 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:20:02.054 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:20:02.054 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:20:02.054 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:20:02.054 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:20:02.054 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:20:02.054 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:20:02.054 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:20:02.058 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-01-29 03:20:02.540 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-01-29 03:20:02.577 [DEBUG] fake_trx.py:278 (BTS@172.18.28.20:5700) Recv FAKE_TOA cmd
2026-01-29 03:20:02.578 [DEBUG] fake_trx.py:297 (BTS@172.18.28.20:5700) Recv FAKE_RSSI cmd
2026-01-29 03:20:02.579 [DEBUG] fake_trx.py:322 (BTS@172.18.28.20:5700) Recv FAKE_CI cmd
2026-01-29 03:20:02.580 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:20:02.604 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 03:20:02.604 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 03:20:02.605 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 03:20:02.609 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 03:20:02.609 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 03:20:02.610 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 03:20:02.610 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.28.22:6700) Recv POWERON CMD
2026-01-29 03:20:02.610 [INFO] ctrl_if_trx.py:109 (MS@172.18.28.22:6700) Starting transceiver...
2026-01-29 03:20:02.637 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:20:02.643 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 03:20:02.644 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 03:20:02.644 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 03:20:02.644 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 03:20:03.017 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-01-29 03:20:03.056 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 03:20:03.056 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:20:03.057 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:20:03.058 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:20:03.485 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-01-29 03:20:03.963 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-01-29 03:20:04.056 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 03:20:04.057 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:20:04.057 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:20:04.059 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:20:04.441 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-01-29 03:20:04.713 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 03:20:04.715 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:20:04.722 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 03:20:04.722 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 03:20:04.739 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 03:20:04.739 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 03:20:04.739 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 03:20:04.740 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 03:20:04.740 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 03:20:04.740 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 03:20:04.740 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.28.22:6700) Recv POWERON CMD
2026-01-29 03:20:04.740 [INFO] ctrl_if_trx.py:109 (MS@172.18.28.22:6700) Starting transceiver...
2026-01-29 03:20:04.771 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:20:04.776 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 03:20:04.776 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 03:20:04.777 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 03:20:04.777 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 03:20:04.916 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-01-29 03:20:05.057 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 03:20:05.057 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:20:05.059 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:20:05.060 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:20:05.394 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-01-29 03:20:05.873 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-01-29 03:20:06.057 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 03:20:06.058 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:20:06.059 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:20:06.061 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:20:06.350 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-01-29 03:20:06.828 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-01-29 03:20:06.872 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 03:20:06.874 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:20:06.878 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 03:20:06.879 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 03:20:06.896 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 03:20:06.896 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 03:20:06.896 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 03:20:06.897 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 03:20:06.897 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 03:20:06.897 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 03:20:06.897 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.28.22:6700) Recv POWERON CMD
2026-01-29 03:20:06.897 [INFO] ctrl_if_trx.py:109 (MS@172.18.28.22:6700) Starting transceiver...
2026-01-29 03:20:06.925 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:20:06.929 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 03:20:06.930 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 03:20:06.930 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 03:20:06.930 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 03:20:07.059 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 03:20:07.059 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:20:07.060 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:20:07.062 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:20:07.306 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-01-29 03:20:07.783 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-01-29 03:20:08.262 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-01-29 03:20:08.739 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-01-29 03:20:09.018 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 03:20:09.020 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:20:09.026 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 03:20:09.026 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 03:20:09.036 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 03:20:09.036 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:20:09.036 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:20:09.037 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:20:09.039 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 03:20:09.040 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 03:20:09.040 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 03:20:09.040 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.28.20:5700) Recv POWEROFF cmd
2026-01-29 03:20:09.040 [INFO] ctrl_if_trx.py:117 (BTS@172.18.28.20:5700) Stopping transceiver...
2026-01-29 03:20:09.040 [INFO] transceiver.py:246 Stopping clock generator
2026-01-29 03:20:09.040 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 03:20:09.040 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=1495 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:20:09.041 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=1495 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:20:09.041 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=1495 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:20:09.041 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=1495 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:20:09.041 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=1495 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:20:09.041 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=1495 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:20:09.041 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=1495 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:20:14.043 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.28.20:5700) Recv POWEROFF cmd
2026-01-29 03:20:14.043 [INFO] ctrl_if_trx.py:117 (BTS@172.18.28.20:5700) Stopping transceiver...
2026-01-29 03:20:14.043 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 03:20:14.043 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 03:20:14.043 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 03:20:14.043 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 03:20:14.052 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 03:20:14.054 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.28.20:5700) Recv SETFORMAT cmd
2026-01-29 03:20:14.054 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.28.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:20:14.055 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.28.20:5700) Recv SETFORMAT cmd
2026-01-29 03:20:14.055 [INFO] ctrl_if_trx.py:201 (BTS@172.18.28.20:5700) TRXD header version 1 -> 1
2026-01-29 03:20:14.060 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.28.20:5700/1) Recv RXTUNE cmd
2026-01-29 03:20:14.060 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.28.20:5700/1) Recv TXTUNE cmd
2026-01-29 03:20:14.061 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.28.20:5700/1) Recv SETFORMAT cmd
2026-01-29 03:20:14.061 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.28.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:20:14.062 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 03:20:14.062 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.28.20:5700/1) Recv NOMTXPOWER cmd
2026-01-29 03:20:14.062 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.28.20:5700/1) Recv SETFORMAT cmd
2026-01-29 03:20:14.063 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.28.20:5700/1) TRXD header version 1 -> 1
2026-01-29 03:20:14.064 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.28.20:5700/2) Recv RXTUNE cmd
2026-01-29 03:20:14.064 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.28.20:5700/2) Recv TXTUNE cmd
2026-01-29 03:20:14.065 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.28.20:5700/2) Recv SETFORMAT cmd
2026-01-29 03:20:14.065 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.28.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:20:14.065 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 03:20:14.065 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.28.20:5700/2) Recv NOMTXPOWER cmd
2026-01-29 03:20:14.066 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.28.20:5700/2) Recv SETFORMAT cmd
2026-01-29 03:20:14.066 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.28.20:5700/2) TRXD header version 1 -> 1
2026-01-29 03:20:14.067 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.28.20:5700/3) Recv RXTUNE cmd
2026-01-29 03:20:14.068 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.28.20:5700/3) Recv TXTUNE cmd
2026-01-29 03:20:14.068 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.28.20:5700/3) Recv SETFORMAT cmd
2026-01-29 03:20:14.068 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.28.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:20:14.068 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 03:20:14.068 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.28.20:5700/3) Recv NOMTXPOWER cmd
2026-01-29 03:20:14.068 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.28.20:5700/3) Recv SETFORMAT cmd
2026-01-29 03:20:14.068 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.28.20:5700/3) TRXD header version 1 -> 1
2026-01-29 03:20:14.071 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.28.20:5700) Recv RXTUNE cmd
2026-01-29 03:20:14.071 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETTSC
2026-01-29 03:20:14.071 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETTSC
2026-01-29 03:20:14.071 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETTSC
2026-01-29 03:20:14.071 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.28.20:5700) Recv TXTUNE cmd
2026-01-29 03:20:14.071 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETRXGAIN
2026-01-29 03:20:14.071 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETRXGAIN
2026-01-29 03:20:14.071 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETRXGAIN
2026-01-29 03:20:14.072 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETTSC
2026-01-29 03:20:14.072 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:20:14.072 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:20:14.072 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:20:14.072 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.28.20:5700) Recv NOMTXPOWER cmd
2026-01-29 03:20:14.072 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:20:14.072 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:20:14.072 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:20:14.072 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.28.20:5700) Recv POWERON CMD
2026-01-29 03:20:14.072 [INFO] ctrl_if_trx.py:109 (BTS@172.18.28.20:5700) Starting transceiver...
2026-01-29 03:20:14.072 [INFO] transceiver.py:243 Starting clock generator
2026-01-29 03:20:14.072 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-01-29 03:20:14.072 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:20:14.072 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:20:14.072 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:20:14.072 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETRXGAIN
2026-01-29 03:20:14.072 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:20:14.072 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:20:14.072 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:20:14.072 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:20:14.073 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:20:14.073 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:20:14.073 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:20:14.073 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:20:14.073 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:20:14.073 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:20:14.073 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:20:14.073 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:20:14.073 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:20:14.073 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:20:14.073 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:20:14.073 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:20:14.073 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:20:14.073 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:20:14.073 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:20:14.073 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:20:14.073 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:20:14.073 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:20:14.073 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:20:14.077 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-01-29 03:20:14.559 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-01-29 03:20:14.606 [DEBUG] fake_trx.py:278 (BTS@172.18.28.20:5700) Recv FAKE_TOA cmd
2026-01-29 03:20:14.608 [DEBUG] fake_trx.py:297 (BTS@172.18.28.20:5700) Recv FAKE_RSSI cmd
2026-01-29 03:20:14.610 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:20:14.610 [DEBUG] fake_trx.py:322 (BTS@172.18.28.20:5700) Recv FAKE_CI cmd
2026-01-29 03:20:14.632 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 03:20:14.633 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 03:20:14.633 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 03:20:14.638 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 03:20:14.639 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 03:20:14.639 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 03:20:14.639 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.28.22:6700) Recv POWERON CMD
2026-01-29 03:20:14.639 [INFO] ctrl_if_trx.py:109 (MS@172.18.28.22:6700) Starting transceiver...
2026-01-29 03:20:14.656 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:20:14.662 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.28.22:6700) Recv SETFH cmd
2026-01-29 03:20:14.662 [INFO] transceiver.py:201 (MS@172.18.28.22:6700) Frequency hopping configured: hsn=5, maio=0, ma_len=4
2026-01-29 03:20:14.663 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 03:20:14.663 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 03:20:15.029 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-01-29 03:20:15.075 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 03:20:15.076 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:20:15.077 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:20:15.081 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:20:15.498 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-01-29 03:20:15.971 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-01-29 03:20:16.077 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 03:20:16.077 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:20:16.078 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:20:16.083 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:20:16.450 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-01-29 03:20:16.779 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 03:20:16.780 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:20:16.787 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 03:20:16.787 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 03:20:16.787 [INFO] transceiver.py:205 (MS@172.18.28.22:6700) Frequency hopping disabled
2026-01-29 03:20:16.804 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 03:20:16.804 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 03:20:16.804 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 03:20:16.805 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 03:20:16.805 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 03:20:16.805 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 03:20:16.805 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.28.22:6700) Recv POWERON CMD
2026-01-29 03:20:16.805 [INFO] ctrl_if_trx.py:109 (MS@172.18.28.22:6700) Starting transceiver...
2026-01-29 03:20:16.823 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:20:16.828 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.28.22:6700) Recv SETFH cmd
2026-01-29 03:20:16.828 [INFO] transceiver.py:201 (MS@172.18.28.22:6700) Frequency hopping configured: hsn=5, maio=0, ma_len=4
2026-01-29 03:20:16.829 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 03:20:16.829 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 03:20:16.928 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-01-29 03:20:17.078 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:20:17.078 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 03:20:17.080 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:20:17.084 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:20:17.404 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-01-29 03:20:17.873 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-01-29 03:20:18.079 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:20:18.079 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 03:20:18.081 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:20:18.085 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:20:18.343 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-01-29 03:20:18.813 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-01-29 03:20:18.947 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 03:20:18.949 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:20:18.954 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 03:20:18.954 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 03:20:18.954 [INFO] transceiver.py:205 (MS@172.18.28.22:6700) Frequency hopping disabled
2026-01-29 03:20:18.964 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 03:20:18.964 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:20:18.964 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:20:18.964 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:20:18.967 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 03:20:18.968 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 03:20:18.968 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 03:20:18.968 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.28.20:5700) Recv POWEROFF cmd
2026-01-29 03:20:18.968 [INFO] ctrl_if_trx.py:117 (BTS@172.18.28.20:5700) Stopping transceiver...
2026-01-29 03:20:18.968 [INFO] transceiver.py:246 Stopping clock generator
2026-01-29 03:20:18.968 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 03:20:18.969 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=1055 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:20:18.969 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=1055 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:20:18.969 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=1055 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:20:18.969 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=1055 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:20:18.969 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=1055 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:20:18.969 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=1055 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:20:18.969 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=1055 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:20:23.968 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.28.20:5700) Recv POWEROFF cmd
2026-01-29 03:20:23.968 [INFO] ctrl_if_trx.py:117 (BTS@172.18.28.20:5700) Stopping transceiver...
2026-01-29 03:20:23.970 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 03:20:23.971 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 03:20:23.971 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 03:20:23.971 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 03:20:23.978 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 03:20:23.978 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.28.20:5700) Recv SETFORMAT cmd
2026-01-29 03:20:23.978 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.28.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:20:23.978 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.28.20:5700) Recv SETFORMAT cmd
2026-01-29 03:20:23.978 [INFO] ctrl_if_trx.py:201 (BTS@172.18.28.20:5700) TRXD header version 1 -> 1
2026-01-29 03:20:23.980 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.28.20:5700/1) Recv RXTUNE cmd
2026-01-29 03:20:23.980 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.28.20:5700/1) Recv TXTUNE cmd
2026-01-29 03:20:23.981 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.28.20:5700/1) Recv SETFORMAT cmd
2026-01-29 03:20:23.981 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.28.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:20:23.981 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 03:20:23.981 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.28.20:5700/1) Recv NOMTXPOWER cmd
2026-01-29 03:20:23.981 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.28.20:5700/1) Recv SETFORMAT cmd
2026-01-29 03:20:23.981 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.28.20:5700/1) TRXD header version 1 -> 1
2026-01-29 03:20:23.983 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.28.20:5700/2) Recv RXTUNE cmd
2026-01-29 03:20:23.983 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.28.20:5700/2) Recv TXTUNE cmd
2026-01-29 03:20:23.983 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.28.20:5700/2) Recv SETFORMAT cmd
2026-01-29 03:20:23.983 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.28.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:20:23.983 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 03:20:23.983 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.28.20:5700/2) Recv NOMTXPOWER cmd
2026-01-29 03:20:23.983 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.28.20:5700/2) Recv SETFORMAT cmd
2026-01-29 03:20:23.983 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.28.20:5700/2) TRXD header version 1 -> 1
2026-01-29 03:20:23.985 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.28.20:5700/3) Recv RXTUNE cmd
2026-01-29 03:20:23.985 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.28.20:5700/3) Recv TXTUNE cmd
2026-01-29 03:20:23.985 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.28.20:5700/3) Recv SETFORMAT cmd
2026-01-29 03:20:23.985 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.28.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:20:23.985 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 03:20:23.985 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.28.20:5700/3) Recv NOMTXPOWER cmd
2026-01-29 03:20:23.985 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.28.20:5700/3) Recv SETFORMAT cmd
2026-01-29 03:20:23.985 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.28.20:5700/3) TRXD header version 1 -> 1
2026-01-29 03:20:23.988 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.28.20:5700) Recv RXTUNE cmd
2026-01-29 03:20:23.988 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETTSC
2026-01-29 03:20:23.988 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETTSC
2026-01-29 03:20:23.988 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETTSC
2026-01-29 03:20:23.988 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.28.20:5700) Recv TXTUNE cmd
2026-01-29 03:20:23.988 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETRXGAIN
2026-01-29 03:20:23.988 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETRXGAIN
2026-01-29 03:20:23.988 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETRXGAIN
2026-01-29 03:20:23.988 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETTSC
2026-01-29 03:20:23.988 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:20:23.988 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:20:23.988 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:20:23.988 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.28.20:5700) Recv NOMTXPOWER cmd
2026-01-29 03:20:23.988 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:20:23.988 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:20:23.988 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:20:23.988 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.28.20:5700) Recv POWERON CMD
2026-01-29 03:20:23.988 [INFO] ctrl_if_trx.py:109 (BTS@172.18.28.20:5700) Starting transceiver...
2026-01-29 03:20:23.989 [INFO] transceiver.py:243 Starting clock generator
2026-01-29 03:20:23.989 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-01-29 03:20:23.989 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:20:23.989 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:20:23.989 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:20:23.989 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETRXGAIN
2026-01-29 03:20:23.989 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:20:23.989 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:20:23.989 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:20:23.989 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:20:23.989 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:20:23.989 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:20:23.989 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:20:23.989 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:20:23.989 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:20:23.989 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:20:23.989 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:20:23.989 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:20:23.989 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:20:23.989 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:20:23.990 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:20:23.990 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:20:23.990 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:20:23.990 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:20:23.990 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:20:23.990 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:20:23.990 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:20:23.990 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:20:23.990 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:20:23.993 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-01-29 03:20:24.476 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-01-29 03:20:24.525 [DEBUG] fake_trx.py:278 (BTS@172.18.28.20:5700) Recv FAKE_TOA cmd
2026-01-29 03:20:24.527 [DEBUG] fake_trx.py:297 (BTS@172.18.28.20:5700) Recv FAKE_RSSI cmd
2026-01-29 03:20:24.528 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:20:24.529 [DEBUG] fake_trx.py:322 (BTS@172.18.28.20:5700) Recv FAKE_CI cmd
2026-01-29 03:20:24.554 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 03:20:24.554 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 03:20:24.555 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 03:20:24.559 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 03:20:24.560 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 03:20:24.560 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 03:20:24.560 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.28.22:6700) Recv POWERON CMD
2026-01-29 03:20:24.560 [INFO] ctrl_if_trx.py:109 (MS@172.18.28.22:6700) Starting transceiver...
2026-01-29 03:20:24.573 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:20:24.578 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 03:20:24.579 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 03:20:24.579 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 03:20:24.579 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 03:20:24.954 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-01-29 03:20:24.992 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 03:20:24.992 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:20:24.994 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:20:24.997 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:20:25.432 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-01-29 03:20:25.910 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-01-29 03:20:25.993 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:20:25.994 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 03:20:25.995 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:20:25.998 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:20:26.388 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-01-29 03:20:26.744 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 03:20:26.746 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:20:26.750 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 03:20:26.750 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 03:20:26.759 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 03:20:26.760 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:20:26.760 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:20:26.760 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:20:26.761 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 03:20:26.761 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 03:20:26.761 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 03:20:26.761 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 03:20:26.761 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.28.20:5700) Recv POWEROFF cmd
2026-01-29 03:20:26.761 [INFO] ctrl_if_trx.py:117 (BTS@172.18.28.20:5700) Stopping transceiver...
2026-01-29 03:20:26.761 [INFO] transceiver.py:246 Stopping clock generator
2026-01-29 03:20:31.763 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.28.20:5700) Recv POWEROFF cmd
2026-01-29 03:20:31.763 [INFO] ctrl_if_trx.py:117 (BTS@172.18.28.20:5700) Stopping transceiver...
2026-01-29 03:20:31.764 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 03:20:31.766 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 03:20:31.767 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 03:20:31.767 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 03:20:31.772 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 03:20:31.773 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.28.20:5700) Recv SETFORMAT cmd
2026-01-29 03:20:31.773 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.28.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:20:31.774 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.28.20:5700) Recv SETFORMAT cmd
2026-01-29 03:20:31.774 [INFO] ctrl_if_trx.py:201 (BTS@172.18.28.20:5700) TRXD header version 1 -> 1
2026-01-29 03:20:31.777 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.28.20:5700/1) Recv RXTUNE cmd
2026-01-29 03:20:31.777 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.28.20:5700/1) Recv TXTUNE cmd
2026-01-29 03:20:31.777 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.28.20:5700/1) Recv SETFORMAT cmd
2026-01-29 03:20:31.778 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.28.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:20:31.778 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 03:20:31.779 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.28.20:5700/1) Recv NOMTXPOWER cmd
2026-01-29 03:20:31.779 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.28.20:5700/1) Recv SETFORMAT cmd
2026-01-29 03:20:31.779 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.28.20:5700/1) TRXD header version 1 -> 1
2026-01-29 03:20:31.780 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.28.20:5700/2) Recv RXTUNE cmd
2026-01-29 03:20:31.780 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.28.20:5700/2) Recv TXTUNE cmd
2026-01-29 03:20:31.781 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.28.20:5700/2) Recv SETFORMAT cmd
2026-01-29 03:20:31.781 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.28.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:20:31.781 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 03:20:31.782 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.28.20:5700/2) Recv NOMTXPOWER cmd
2026-01-29 03:20:31.782 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.28.20:5700/2) Recv SETFORMAT cmd
2026-01-29 03:20:31.782 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.28.20:5700/2) TRXD header version 1 -> 1
2026-01-29 03:20:31.783 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.28.20:5700/3) Recv RXTUNE cmd
2026-01-29 03:20:31.783 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.28.20:5700/3) Recv TXTUNE cmd
2026-01-29 03:20:31.783 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.28.20:5700/3) Recv SETFORMAT cmd
2026-01-29 03:20:31.783 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.28.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:20:31.784 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 03:20:31.784 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.28.20:5700/3) Recv NOMTXPOWER cmd
2026-01-29 03:20:31.784 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.28.20:5700/3) Recv SETFORMAT cmd
2026-01-29 03:20:31.784 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.28.20:5700/3) TRXD header version 1 -> 1
2026-01-29 03:20:31.787 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.28.20:5700) Recv RXTUNE cmd
2026-01-29 03:20:31.787 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETTSC
2026-01-29 03:20:31.787 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETTSC
2026-01-29 03:20:31.787 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETTSC
2026-01-29 03:20:31.787 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.28.20:5700) Recv TXTUNE cmd
2026-01-29 03:20:31.787 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETRXGAIN
2026-01-29 03:20:31.787 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETRXGAIN
2026-01-29 03:20:31.787 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETRXGAIN
2026-01-29 03:20:31.787 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETTSC
2026-01-29 03:20:31.787 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:20:31.787 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:20:31.787 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:20:31.787 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.28.20:5700) Recv NOMTXPOWER cmd
2026-01-29 03:20:31.787 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:20:31.787 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:20:31.787 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:20:31.787 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.28.20:5700) Recv POWERON CMD
2026-01-29 03:20:31.787 [INFO] ctrl_if_trx.py:109 (BTS@172.18.28.20:5700) Starting transceiver...
2026-01-29 03:20:31.787 [INFO] transceiver.py:243 Starting clock generator
2026-01-29 03:20:31.788 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-01-29 03:20:31.788 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:20:31.788 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:20:31.788 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:20:31.788 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETRXGAIN
2026-01-29 03:20:31.788 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:20:31.788 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:20:31.788 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:20:31.788 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:20:31.788 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:20:31.788 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:20:31.788 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:20:31.788 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:20:31.788 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:20:31.788 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:20:31.788 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:20:31.788 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:20:31.788 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:20:31.789 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:20:31.789 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:20:31.789 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:20:31.789 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:20:31.789 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:20:31.789 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:20:31.789 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:20:31.789 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:20:31.789 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:20:31.789 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:20:31.792 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-01-29 03:20:32.276 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-01-29 03:20:32.315 [DEBUG] fake_trx.py:278 (BTS@172.18.28.20:5700) Recv FAKE_TOA cmd
2026-01-29 03:20:32.317 [DEBUG] fake_trx.py:297 (BTS@172.18.28.20:5700) Recv FAKE_RSSI cmd
2026-01-29 03:20:32.318 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:20:32.318 [DEBUG] fake_trx.py:322 (BTS@172.18.28.20:5700) Recv FAKE_CI cmd
2026-01-29 03:20:32.341 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 03:20:32.341 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 03:20:32.342 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 03:20:32.346 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 03:20:32.346 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 03:20:32.346 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 03:20:32.346 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.28.22:6700) Recv POWERON CMD
2026-01-29 03:20:32.346 [INFO] ctrl_if_trx.py:109 (MS@172.18.28.22:6700) Starting transceiver...
2026-01-29 03:20:32.374 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:20:32.380 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.28.22:6700) Recv SETFH cmd
2026-01-29 03:20:32.380 [INFO] transceiver.py:201 (MS@172.18.28.22:6700) Frequency hopping configured: hsn=5, maio=0, ma_len=4
2026-01-29 03:20:32.380 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 03:20:32.380 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 03:20:32.748 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-01-29 03:20:32.791 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:20:32.791 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 03:20:32.791 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:20:32.793 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:20:33.220 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-01-29 03:20:33.699 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-01-29 03:20:33.792 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:20:33.792 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 03:20:33.792 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:20:33.794 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:20:34.178 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-01-29 03:20:34.550 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 03:20:34.552 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:20:34.556 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 03:20:34.556 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 03:20:34.556 [INFO] transceiver.py:205 (MS@172.18.28.22:6700) Frequency hopping disabled
2026-01-29 03:20:34.565 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 03:20:34.565 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:20:34.565 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:20:34.566 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:20:34.569 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 03:20:34.569 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 03:20:34.569 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 03:20:34.569 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.28.20:5700) Recv POWEROFF cmd
2026-01-29 03:20:34.569 [INFO] ctrl_if_trx.py:117 (BTS@172.18.28.20:5700) Stopping transceiver...
2026-01-29 03:20:34.569 [INFO] transceiver.py:246 Stopping clock generator
2026-01-29 03:20:34.570 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 03:20:34.570 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=596 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:20:34.570 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=596 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:20:34.570 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=596 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:20:34.570 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=596 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:20:34.570 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=596 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:20:34.571 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=596 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:20:34.571 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=596 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:20:39.567 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.28.20:5700) Recv POWEROFF cmd
2026-01-29 03:20:39.567 [INFO] ctrl_if_trx.py:117 (BTS@172.18.28.20:5700) Stopping transceiver...
2026-01-29 03:20:39.568 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 03:20:39.569 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 03:20:39.569 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 03:20:39.570 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 03:20:39.577 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 03:20:39.579 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.28.20:5700) Recv SETFORMAT cmd
2026-01-29 03:20:39.579 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.28.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:20:39.579 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.28.20:5700) Recv SETFORMAT cmd
2026-01-29 03:20:39.579 [INFO] ctrl_if_trx.py:201 (BTS@172.18.28.20:5700) TRXD header version 1 -> 1
2026-01-29 03:20:39.582 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.28.20:5700/1) Recv RXTUNE cmd
2026-01-29 03:20:39.582 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.28.20:5700/1) Recv TXTUNE cmd
2026-01-29 03:20:39.582 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.28.20:5700/1) Recv SETFORMAT cmd
2026-01-29 03:20:39.583 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.28.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:20:39.583 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 03:20:39.583 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.28.20:5700/1) Recv NOMTXPOWER cmd
2026-01-29 03:20:39.584 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.28.20:5700/1) Recv SETFORMAT cmd
2026-01-29 03:20:39.584 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.28.20:5700/1) TRXD header version 1 -> 1
2026-01-29 03:20:39.584 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.28.20:5700/2) Recv RXTUNE cmd
2026-01-29 03:20:39.585 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.28.20:5700/2) Recv TXTUNE cmd
2026-01-29 03:20:39.585 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.28.20:5700/2) Recv SETFORMAT cmd
2026-01-29 03:20:39.585 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.28.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:20:39.585 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 03:20:39.586 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.28.20:5700/2) Recv NOMTXPOWER cmd
2026-01-29 03:20:39.586 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.28.20:5700/2) Recv SETFORMAT cmd
2026-01-29 03:20:39.586 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.28.20:5700/2) TRXD header version 1 -> 1
2026-01-29 03:20:39.587 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.28.20:5700/3) Recv RXTUNE cmd
2026-01-29 03:20:39.587 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.28.20:5700/3) Recv TXTUNE cmd
2026-01-29 03:20:39.587 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.28.20:5700/3) Recv SETFORMAT cmd
2026-01-29 03:20:39.587 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.28.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:20:39.587 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 03:20:39.587 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.28.20:5700/3) Recv NOMTXPOWER cmd
2026-01-29 03:20:39.587 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.28.20:5700/3) Recv SETFORMAT cmd
2026-01-29 03:20:39.587 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.28.20:5700/3) TRXD header version 1 -> 1
2026-01-29 03:20:39.590 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.28.20:5700) Recv RXTUNE cmd
2026-01-29 03:20:39.590 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETTSC
2026-01-29 03:20:39.590 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETTSC
2026-01-29 03:20:39.590 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETTSC
2026-01-29 03:20:39.590 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.28.20:5700) Recv TXTUNE cmd
2026-01-29 03:20:39.590 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETRXGAIN
2026-01-29 03:20:39.590 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETRXGAIN
2026-01-29 03:20:39.590 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETRXGAIN
2026-01-29 03:20:39.590 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETTSC
2026-01-29 03:20:39.590 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:20:39.590 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:20:39.590 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:20:39.590 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.28.20:5700) Recv NOMTXPOWER cmd
2026-01-29 03:20:39.590 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:20:39.590 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:20:39.590 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:20:39.590 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.28.20:5700) Recv POWERON CMD
2026-01-29 03:20:39.590 [INFO] ctrl_if_trx.py:109 (BTS@172.18.28.20:5700) Starting transceiver...
2026-01-29 03:20:39.590 [INFO] transceiver.py:243 Starting clock generator
2026-01-29 03:20:39.590 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-01-29 03:20:39.590 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:20:39.590 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:20:39.590 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:20:39.591 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETRXGAIN
2026-01-29 03:20:39.591 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:20:39.591 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:20:39.591 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:20:39.591 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:20:39.591 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:20:39.591 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:20:39.591 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:20:39.591 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:20:39.591 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:20:39.591 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:20:39.591 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:20:39.591 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:20:39.591 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:20:39.591 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:20:39.591 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:20:39.591 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:20:39.591 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:20:39.591 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:20:39.591 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:20:39.591 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:20:39.591 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:20:39.591 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:20:39.591 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:20:39.595 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-01-29 03:20:40.078 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-01-29 03:20:40.118 [DEBUG] fake_trx.py:278 (BTS@172.18.28.20:5700) Recv FAKE_TOA cmd
2026-01-29 03:20:40.120 [DEBUG] fake_trx.py:297 (BTS@172.18.28.20:5700) Recv FAKE_RSSI cmd
2026-01-29 03:20:40.122 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:20:40.123 [DEBUG] fake_trx.py:322 (BTS@172.18.28.20:5700) Recv FAKE_CI cmd
2026-01-29 03:20:40.139 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 03:20:40.139 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 03:20:40.140 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 03:20:40.187 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 03:20:40.187 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 03:20:40.188 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 03:20:40.188 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.28.22:6700) Recv POWERON CMD
2026-01-29 03:20:40.188 [INFO] ctrl_if_trx.py:109 (MS@172.18.28.22:6700) Starting transceiver...
2026-01-29 03:20:40.218 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:20:40.223 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 03:20:40.223 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 03:20:40.223 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 03:20:40.224 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 03:20:40.555 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-01-29 03:20:40.593 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 03:20:40.594 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:20:40.594 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:20:40.598 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:20:40.600 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 03:20:40.601 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:20:40.608 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 03:20:40.608 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 03:20:40.627 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 03:20:40.627 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 03:20:40.627 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 03:20:40.645 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 03:20:40.645 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 03:20:40.645 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 03:20:40.645 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.28.22:6700) Recv POWERON CMD
2026-01-29 03:20:40.645 [INFO] ctrl_if_trx.py:109 (MS@172.18.28.22:6700) Starting transceiver...
2026-01-29 03:20:40.694 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:20:40.698 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 03:20:40.699 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 03:20:40.699 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 03:20:40.700 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 03:20:41.033 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-01-29 03:20:41.069 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 03:20:41.071 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:20:41.075 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 03:20:41.076 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 03:20:41.084 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 03:20:41.084 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:20:41.085 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:20:41.085 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:20:41.087 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 03:20:41.087 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 03:20:41.087 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 03:20:41.087 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 03:20:41.087 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.28.20:5700) Recv POWEROFF cmd
2026-01-29 03:20:41.087 [INFO] ctrl_if_trx.py:117 (BTS@172.18.28.20:5700) Stopping transceiver...
2026-01-29 03:20:41.087 [INFO] transceiver.py:246 Stopping clock generator
2026-01-29 03:20:46.087 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.28.20:5700) Recv POWEROFF cmd
2026-01-29 03:20:46.087 [INFO] ctrl_if_trx.py:117 (BTS@172.18.28.20:5700) Stopping transceiver...
2026-01-29 03:20:46.089 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 03:20:46.090 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 03:20:46.091 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 03:20:46.091 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 03:20:46.095 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 03:20:46.095 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.28.20:5700) Recv SETFORMAT cmd
2026-01-29 03:20:46.096 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.28.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:20:46.096 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.28.20:5700) Recv SETFORMAT cmd
2026-01-29 03:20:46.096 [INFO] ctrl_if_trx.py:201 (BTS@172.18.28.20:5700) TRXD header version 1 -> 1
2026-01-29 03:20:46.099 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.28.20:5700/1) Recv RXTUNE cmd
2026-01-29 03:20:46.099 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.28.20:5700/1) Recv TXTUNE cmd
2026-01-29 03:20:46.099 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.28.20:5700/1) Recv SETFORMAT cmd
2026-01-29 03:20:46.099 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.28.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:20:46.099 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 03:20:46.099 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.28.20:5700/1) Recv NOMTXPOWER cmd
2026-01-29 03:20:46.099 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.28.20:5700/1) Recv SETFORMAT cmd
2026-01-29 03:20:46.099 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.28.20:5700/1) TRXD header version 1 -> 1
2026-01-29 03:20:46.101 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.28.20:5700/2) Recv RXTUNE cmd
2026-01-29 03:20:46.102 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.28.20:5700/2) Recv TXTUNE cmd
2026-01-29 03:20:46.102 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.28.20:5700/2) Recv SETFORMAT cmd
2026-01-29 03:20:46.102 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.28.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:20:46.102 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 03:20:46.102 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.28.20:5700/2) Recv NOMTXPOWER cmd
2026-01-29 03:20:46.102 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.28.20:5700/2) Recv SETFORMAT cmd
2026-01-29 03:20:46.102 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.28.20:5700/2) TRXD header version 1 -> 1
2026-01-29 03:20:46.104 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.28.20:5700/3) Recv RXTUNE cmd
2026-01-29 03:20:46.104 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.28.20:5700/3) Recv TXTUNE cmd
2026-01-29 03:20:46.104 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.28.20:5700/3) Recv SETFORMAT cmd
2026-01-29 03:20:46.104 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.28.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:20:46.104 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 03:20:46.104 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.28.20:5700/3) Recv NOMTXPOWER cmd
2026-01-29 03:20:46.104 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.28.20:5700/3) Recv SETFORMAT cmd
2026-01-29 03:20:46.104 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.28.20:5700/3) TRXD header version 1 -> 1
2026-01-29 03:20:46.106 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.28.20:5700) Recv RXTUNE cmd
2026-01-29 03:20:46.106 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETTSC
2026-01-29 03:20:46.106 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETTSC
2026-01-29 03:20:46.106 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETTSC
2026-01-29 03:20:46.107 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.28.20:5700) Recv TXTUNE cmd
2026-01-29 03:20:46.107 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETRXGAIN
2026-01-29 03:20:46.107 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETRXGAIN
2026-01-29 03:20:46.107 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETRXGAIN
2026-01-29 03:20:46.107 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETTSC
2026-01-29 03:20:46.107 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:20:46.107 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:20:46.107 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.28.20:5700) Recv NOMTXPOWER cmd
2026-01-29 03:20:46.107 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:20:46.107 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:20:46.107 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:20:46.107 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.28.20:5700) Recv POWERON CMD
2026-01-29 03:20:46.107 [INFO] ctrl_if_trx.py:109 (BTS@172.18.28.20:5700) Starting transceiver...
2026-01-29 03:20:46.107 [INFO] transceiver.py:243 Starting clock generator
2026-01-29 03:20:46.107 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-01-29 03:20:46.107 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:20:46.107 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:20:46.107 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:20:46.107 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETRXGAIN
2026-01-29 03:20:46.107 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:20:46.107 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:20:46.107 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:20:46.107 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:20:46.108 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:20:46.108 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:20:46.108 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:20:46.108 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:20:46.108 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:20:46.108 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:20:46.108 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:20:46.108 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:20:46.108 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:20:46.108 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:20:46.108 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:20:46.108 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:20:46.108 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:20:46.108 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:20:46.108 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:20:46.108 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:20:46.108 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:20:46.108 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:20:46.108 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:20:46.108 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:20:46.112 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-01-29 03:20:46.594 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-01-29 03:20:46.638 [DEBUG] fake_trx.py:278 (BTS@172.18.28.20:5700) Recv FAKE_TOA cmd
2026-01-29 03:20:46.640 [DEBUG] fake_trx.py:297 (BTS@172.18.28.20:5700) Recv FAKE_RSSI cmd
2026-01-29 03:20:46.641 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:20:46.643 [DEBUG] fake_trx.py:322 (BTS@172.18.28.20:5700) Recv FAKE_CI cmd
2026-01-29 03:20:46.668 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 03:20:46.668 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 03:20:46.669 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 03:20:46.705 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 03:20:46.706 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 03:20:46.706 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 03:20:46.706 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.28.22:6700) Recv POWERON CMD
2026-01-29 03:20:46.707 [INFO] ctrl_if_trx.py:109 (MS@172.18.28.22:6700) Starting transceiver...
2026-01-29 03:20:46.735 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:20:46.740 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 03:20:46.740 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 03:20:46.740 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 03:20:46.741 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 03:20:47.067 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-01-29 03:20:47.109 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 03:20:47.110 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:20:47.110 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 03:20:47.111 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:20:47.112 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:20:47.113 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:20:47.118 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 03:20:47.118 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 03:20:47.136 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 03:20:47.136 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 03:20:47.136 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 03:20:47.147 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 03:20:47.147 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 03:20:47.147 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 03:20:47.147 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.28.22:6700) Recv POWERON CMD
2026-01-29 03:20:47.147 [INFO] ctrl_if_trx.py:109 (MS@172.18.28.22:6700) Starting transceiver...
2026-01-29 03:20:47.155 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:20:47.157 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 03:20:47.157 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 03:20:47.157 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 03:20:47.157 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 03:20:47.530 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 03:20:47.532 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:20:47.536 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 03:20:47.536 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 03:20:47.539 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-01-29 03:20:47.544 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 03:20:47.545 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:20:47.545 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:20:47.545 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:20:47.547 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 03:20:47.547 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 03:20:47.547 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 03:20:47.547 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 03:20:47.547 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.28.20:5700) Recv POWEROFF cmd
2026-01-29 03:20:47.547 [INFO] ctrl_if_trx.py:117 (BTS@172.18.28.20:5700) Stopping transceiver...
2026-01-29 03:20:47.547 [INFO] transceiver.py:246 Stopping clock generator
2026-01-29 03:20:47.547 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=309 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:20:47.547 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=309 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:20:47.547 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=309 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:20:47.547 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=309 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:20:47.547 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=310 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:20:47.547 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=310 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:20:47.547 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=310 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:20:47.547 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=310 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:20:47.547 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=310 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:20:47.547 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=310 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:20:47.547 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=310 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:20:47.547 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=310 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:20:52.548 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.28.20:5700) Recv POWEROFF cmd
2026-01-29 03:20:52.548 [INFO] ctrl_if_trx.py:117 (BTS@172.18.28.20:5700) Stopping transceiver...
2026-01-29 03:20:52.549 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 03:20:52.550 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 03:20:52.550 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 03:20:52.551 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 03:20:52.555 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 03:20:52.555 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.28.20:5700) Recv SETFORMAT cmd
2026-01-29 03:20:52.556 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.28.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:20:52.556 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.28.20:5700) Recv SETFORMAT cmd
2026-01-29 03:20:52.556 [INFO] ctrl_if_trx.py:201 (BTS@172.18.28.20:5700) TRXD header version 1 -> 1
2026-01-29 03:20:52.558 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.28.20:5700/1) Recv RXTUNE cmd
2026-01-29 03:20:52.558 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.28.20:5700/1) Recv TXTUNE cmd
2026-01-29 03:20:52.559 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.28.20:5700/1) Recv SETFORMAT cmd
2026-01-29 03:20:52.559 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.28.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:20:52.559 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 03:20:52.559 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.28.20:5700/1) Recv NOMTXPOWER cmd
2026-01-29 03:20:52.560 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.28.20:5700/1) Recv SETFORMAT cmd
2026-01-29 03:20:52.560 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.28.20:5700/1) TRXD header version 1 -> 1
2026-01-29 03:20:52.561 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.28.20:5700/2) Recv RXTUNE cmd
2026-01-29 03:20:52.561 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.28.20:5700/2) Recv TXTUNE cmd
2026-01-29 03:20:52.561 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.28.20:5700/2) Recv SETFORMAT cmd
2026-01-29 03:20:52.561 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.28.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:20:52.561 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 03:20:52.561 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.28.20:5700/2) Recv NOMTXPOWER cmd
2026-01-29 03:20:52.561 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.28.20:5700/2) Recv SETFORMAT cmd
2026-01-29 03:20:52.561 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.28.20:5700/2) TRXD header version 1 -> 1
2026-01-29 03:20:52.563 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.28.20:5700/3) Recv RXTUNE cmd
2026-01-29 03:20:52.563 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.28.20:5700/3) Recv TXTUNE cmd
2026-01-29 03:20:52.563 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.28.20:5700/3) Recv SETFORMAT cmd
2026-01-29 03:20:52.563 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.28.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:20:52.563 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 03:20:52.563 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.28.20:5700/3) Recv NOMTXPOWER cmd
2026-01-29 03:20:52.563 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.28.20:5700/3) Recv SETFORMAT cmd
2026-01-29 03:20:52.563 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.28.20:5700/3) TRXD header version 1 -> 1
2026-01-29 03:20:52.566 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.28.20:5700) Recv RXTUNE cmd
2026-01-29 03:20:52.566 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETTSC
2026-01-29 03:20:52.566 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETTSC
2026-01-29 03:20:52.566 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETTSC
2026-01-29 03:20:52.566 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.28.20:5700) Recv TXTUNE cmd
2026-01-29 03:20:52.566 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETRXGAIN
2026-01-29 03:20:52.566 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETRXGAIN
2026-01-29 03:20:52.566 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETRXGAIN
2026-01-29 03:20:52.566 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETTSC
2026-01-29 03:20:52.566 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:20:52.566 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:20:52.566 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:20:52.566 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.28.20:5700) Recv NOMTXPOWER cmd
2026-01-29 03:20:52.566 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:20:52.566 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:20:52.566 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:20:52.566 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.28.20:5700) Recv POWERON CMD
2026-01-29 03:20:52.566 [INFO] ctrl_if_trx.py:109 (BTS@172.18.28.20:5700) Starting transceiver...
2026-01-29 03:20:52.566 [INFO] transceiver.py:243 Starting clock generator
2026-01-29 03:20:52.567 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-01-29 03:20:52.567 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:20:52.567 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:20:52.567 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:20:52.567 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETRXGAIN
2026-01-29 03:20:52.567 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:20:52.567 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:20:52.567 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:20:52.567 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:20:52.567 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:20:52.567 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:20:52.567 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:20:52.567 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:20:52.567 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:20:52.567 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:20:52.567 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:20:52.567 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:20:52.567 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:20:52.567 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:20:52.567 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:20:52.567 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:20:52.568 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:20:52.568 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:20:52.568 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:20:52.568 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:20:52.568 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:20:52.568 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:20:52.568 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:20:52.571 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-01-29 03:20:53.055 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-01-29 03:20:53.096 [DEBUG] fake_trx.py:278 (BTS@172.18.28.20:5700) Recv FAKE_TOA cmd
2026-01-29 03:20:53.096 [DEBUG] fake_trx.py:297 (BTS@172.18.28.20:5700) Recv FAKE_RSSI cmd
2026-01-29 03:20:53.097 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:20:53.098 [DEBUG] fake_trx.py:322 (BTS@172.18.28.20:5700) Recv FAKE_CI cmd
2026-01-29 03:20:53.123 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 03:20:53.123 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 03:20:53.123 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 03:20:53.167 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 03:20:53.167 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 03:20:53.168 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 03:20:53.168 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.28.22:6700) Recv POWERON CMD
2026-01-29 03:20:53.168 [INFO] ctrl_if_trx.py:109 (MS@172.18.28.22:6700) Starting transceiver...
2026-01-29 03:20:53.196 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:20:53.200 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 03:20:53.200 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 03:20:53.200 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 03:20:53.200 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 03:20:53.527 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-01-29 03:20:53.570 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 03:20:53.571 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 03:20:53.571 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:20:53.572 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:20:53.573 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:20:53.576 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:20:53.580 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 03:20:53.580 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 03:20:53.595 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 03:20:53.595 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 03:20:53.596 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 03:20:53.606 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 03:20:53.606 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 03:20:53.606 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 03:20:53.606 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.28.22:6700) Recv POWERON CMD
2026-01-29 03:20:53.606 [INFO] ctrl_if_trx.py:109 (MS@172.18.28.22:6700) Starting transceiver...
2026-01-29 03:20:53.615 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:20:53.616 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 03:20:53.616 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 03:20:53.616 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 03:20:53.616 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 03:20:54.016 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-01-29 03:20:54.052 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 03:20:54.054 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:20:54.059 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 03:20:54.059 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 03:20:54.067 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 03:20:54.067 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:20:54.067 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:20:54.067 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:20:54.069 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 03:20:54.069 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 03:20:54.069 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 03:20:54.069 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 03:20:54.069 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.28.20:5700) Recv POWEROFF cmd
2026-01-29 03:20:54.069 [INFO] ctrl_if_trx.py:117 (BTS@172.18.28.20:5700) Stopping transceiver...
2026-01-29 03:20:54.069 [INFO] transceiver.py:246 Stopping clock generator
2026-01-29 03:20:54.070 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=319 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:20:54.070 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=319 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:20:54.070 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=319 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:20:54.070 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=319 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:20:54.070 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=319 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:20:54.070 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=319 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:20:54.070 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=319 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:20:59.070 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.28.20:5700) Recv POWEROFF cmd
2026-01-29 03:20:59.070 [INFO] ctrl_if_trx.py:117 (BTS@172.18.28.20:5700) Stopping transceiver...
2026-01-29 03:20:59.072 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 03:20:59.073 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 03:20:59.074 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 03:20:59.075 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 03:20:59.084 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 03:20:59.085 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.28.20:5700) Recv SETFORMAT cmd
2026-01-29 03:20:59.085 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.28.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:20:59.086 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.28.20:5700) Recv SETFORMAT cmd
2026-01-29 03:20:59.086 [INFO] ctrl_if_trx.py:201 (BTS@172.18.28.20:5700) TRXD header version 1 -> 1
2026-01-29 03:20:59.089 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.28.20:5700/1) Recv RXTUNE cmd
2026-01-29 03:20:59.090 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.28.20:5700/1) Recv TXTUNE cmd
2026-01-29 03:20:59.090 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.28.20:5700/1) Recv SETFORMAT cmd
2026-01-29 03:20:59.090 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.28.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:20:59.091 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 03:20:59.091 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.28.20:5700/1) Recv NOMTXPOWER cmd
2026-01-29 03:20:59.091 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.28.20:5700/1) Recv SETFORMAT cmd
2026-01-29 03:20:59.091 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.28.20:5700/1) TRXD header version 1 -> 1
2026-01-29 03:20:59.093 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.28.20:5700/2) Recv RXTUNE cmd
2026-01-29 03:20:59.093 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.28.20:5700/2) Recv TXTUNE cmd
2026-01-29 03:20:59.093 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.28.20:5700/2) Recv SETFORMAT cmd
2026-01-29 03:20:59.093 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.28.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:20:59.094 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 03:20:59.094 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.28.20:5700/2) Recv NOMTXPOWER cmd
2026-01-29 03:20:59.094 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.28.20:5700/2) Recv SETFORMAT cmd
2026-01-29 03:20:59.094 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.28.20:5700/2) TRXD header version 1 -> 1
2026-01-29 03:20:59.095 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.28.20:5700/3) Recv RXTUNE cmd
2026-01-29 03:20:59.095 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.28.20:5700/3) Recv TXTUNE cmd
2026-01-29 03:20:59.095 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.28.20:5700/3) Recv SETFORMAT cmd
2026-01-29 03:20:59.095 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.28.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:20:59.096 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 03:20:59.096 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.28.20:5700/3) Recv NOMTXPOWER cmd
2026-01-29 03:20:59.096 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.28.20:5700/3) Recv SETFORMAT cmd
2026-01-29 03:20:59.096 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.28.20:5700/3) TRXD header version 1 -> 1
2026-01-29 03:20:59.098 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.28.20:5700) Recv RXTUNE cmd
2026-01-29 03:20:59.098 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETTSC
2026-01-29 03:20:59.098 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETTSC
2026-01-29 03:20:59.098 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETTSC
2026-01-29 03:20:59.098 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.28.20:5700) Recv TXTUNE cmd
2026-01-29 03:20:59.098 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETRXGAIN
2026-01-29 03:20:59.098 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETRXGAIN
2026-01-29 03:20:59.098 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETRXGAIN
2026-01-29 03:20:59.098 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:20:59.098 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETTSC
2026-01-29 03:20:59.098 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:20:59.098 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:20:59.098 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.28.20:5700) Recv NOMTXPOWER cmd
2026-01-29 03:20:59.098 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:20:59.098 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:20:59.098 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:20:59.098 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.28.20:5700) Recv POWERON CMD
2026-01-29 03:20:59.098 [INFO] ctrl_if_trx.py:109 (BTS@172.18.28.20:5700) Starting transceiver...
2026-01-29 03:20:59.098 [INFO] transceiver.py:243 Starting clock generator
2026-01-29 03:20:59.098 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-01-29 03:20:59.098 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:20:59.098 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:20:59.098 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:20:59.099 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETRXGAIN
2026-01-29 03:20:59.099 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:20:59.099 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:20:59.099 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:20:59.099 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:20:59.099 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:20:59.099 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:20:59.099 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:20:59.099 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:20:59.099 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:20:59.099 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:20:59.099 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:20:59.099 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:20:59.099 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:20:59.099 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:20:59.099 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:20:59.099 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:20:59.099 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:20:59.099 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:20:59.099 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:20:59.099 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:20:59.099 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:20:59.099 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:20:59.099 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:20:59.103 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-01-29 03:20:59.584 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-01-29 03:20:59.624 [DEBUG] fake_trx.py:278 (BTS@172.18.28.20:5700) Recv FAKE_TOA cmd
2026-01-29 03:20:59.625 [DEBUG] fake_trx.py:297 (BTS@172.18.28.20:5700) Recv FAKE_RSSI cmd
2026-01-29 03:20:59.627 [DEBUG] fake_trx.py:322 (BTS@172.18.28.20:5700) Recv FAKE_CI cmd
2026-01-29 03:20:59.628 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:20:59.651 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 03:20:59.651 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 03:20:59.651 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 03:20:59.699 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 03:20:59.700 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 03:20:59.700 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 03:20:59.700 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.28.22:6700) Recv POWERON CMD
2026-01-29 03:20:59.700 [INFO] ctrl_if_trx.py:109 (MS@172.18.28.22:6700) Starting transceiver...
2026-01-29 03:20:59.723 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:20:59.729 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.28.22:6700) Recv SETFH cmd
2026-01-29 03:20:59.729 [INFO] transceiver.py:201 (MS@172.18.28.22:6700) Frequency hopping configured: hsn=5, maio=0, ma_len=4
2026-01-29 03:20:59.729 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 03:20:59.729 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 03:21:00.060 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-01-29 03:21:00.101 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 03:21:00.101 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:21:00.101 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:21:00.104 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:21:00.538 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-01-29 03:21:01.016 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-01-29 03:21:01.101 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 03:21:01.102 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:21:01.102 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:21:01.105 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:21:01.495 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-01-29 03:21:01.973 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-01-29 03:21:02.102 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 03:21:02.102 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:21:02.103 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:21:02.106 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:21:02.453 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-01-29 03:21:02.931 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-01-29 03:21:03.103 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:21:03.103 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 03:21:03.103 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:21:03.107 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:21:03.405 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-01-29 03:21:03.734 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 03:21:03.734 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 03:21:03.734 [INFO] transceiver.py:205 (MS@172.18.28.22:6700) Frequency hopping disabled
2026-01-29 03:21:03.737 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 03:21:03.737 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:21:03.737 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:21:03.738 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:21:03.738 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 03:21:03.738 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 03:21:03.739 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.28.20:5700) Recv POWEROFF cmd
2026-01-29 03:21:03.739 [INFO] ctrl_if_trx.py:117 (BTS@172.18.28.20:5700) Stopping transceiver...
2026-01-29 03:21:03.739 [INFO] transceiver.py:246 Stopping clock generator
2026-01-29 03:21:03.739 [WARNING] transceiver.py:257 (TRX2@172.18.28.20:5700/2) RX TRXD message (ver=1 fn=992 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:21:03.739 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 03:21:03.739 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 03:21:03.739 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=992 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:21:03.739 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=992 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:21:03.739 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=992 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:21:03.739 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=992 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:21:03.739 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=992 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:21:03.739 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=992 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:21:03.739 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=992 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:21:08.741 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.28.20:5700) Recv POWEROFF cmd
2026-01-29 03:21:08.741 [INFO] ctrl_if_trx.py:117 (BTS@172.18.28.20:5700) Stopping transceiver...
2026-01-29 03:21:08.742 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 03:21:08.744 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 03:21:08.745 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 03:21:08.745 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 03:21:08.751 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 03:21:08.752 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.28.20:5700) Recv SETFORMAT cmd
2026-01-29 03:21:08.752 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.28.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:21:08.753 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.28.20:5700) Recv SETFORMAT cmd
2026-01-29 03:21:08.753 [INFO] ctrl_if_trx.py:201 (BTS@172.18.28.20:5700) TRXD header version 1 -> 1
2026-01-29 03:21:08.755 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.28.20:5700/1) Recv RXTUNE cmd
2026-01-29 03:21:08.755 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.28.20:5700/1) Recv TXTUNE cmd
2026-01-29 03:21:08.756 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.28.20:5700/1) Recv SETFORMAT cmd
2026-01-29 03:21:08.756 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.28.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:21:08.756 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 03:21:08.756 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.28.20:5700/1) Recv NOMTXPOWER cmd
2026-01-29 03:21:08.756 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.28.20:5700/1) Recv SETFORMAT cmd
2026-01-29 03:21:08.756 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.28.20:5700/1) TRXD header version 1 -> 1
2026-01-29 03:21:08.758 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.28.20:5700/2) Recv RXTUNE cmd
2026-01-29 03:21:08.759 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.28.20:5700/2) Recv TXTUNE cmd
2026-01-29 03:21:08.759 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.28.20:5700/2) Recv SETFORMAT cmd
2026-01-29 03:21:08.759 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.28.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:21:08.759 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 03:21:08.759 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.28.20:5700/2) Recv NOMTXPOWER cmd
2026-01-29 03:21:08.759 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.28.20:5700/2) Recv SETFORMAT cmd
2026-01-29 03:21:08.759 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.28.20:5700/2) TRXD header version 1 -> 1
2026-01-29 03:21:08.761 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.28.20:5700/3) Recv RXTUNE cmd
2026-01-29 03:21:08.761 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.28.20:5700/3) Recv TXTUNE cmd
2026-01-29 03:21:08.761 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.28.20:5700/3) Recv SETFORMAT cmd
2026-01-29 03:21:08.761 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.28.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:21:08.762 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 03:21:08.762 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.28.20:5700/3) Recv NOMTXPOWER cmd
2026-01-29 03:21:08.762 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.28.20:5700/3) Recv SETFORMAT cmd
2026-01-29 03:21:08.762 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.28.20:5700/3) TRXD header version 1 -> 1
2026-01-29 03:21:08.765 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.28.20:5700) Recv RXTUNE cmd
2026-01-29 03:21:08.765 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETTSC
2026-01-29 03:21:08.765 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETTSC
2026-01-29 03:21:08.765 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETTSC
2026-01-29 03:21:08.765 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.28.20:5700) Recv TXTUNE cmd
2026-01-29 03:21:08.765 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETRXGAIN
2026-01-29 03:21:08.765 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETRXGAIN
2026-01-29 03:21:08.765 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETRXGAIN
2026-01-29 03:21:08.765 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETTSC
2026-01-29 03:21:08.765 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:21:08.765 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:21:08.765 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:21:08.765 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.28.20:5700) Recv NOMTXPOWER cmd
2026-01-29 03:21:08.765 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:21:08.765 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:21:08.765 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:21:08.765 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.28.20:5700) Recv POWERON CMD
2026-01-29 03:21:08.765 [INFO] ctrl_if_trx.py:109 (BTS@172.18.28.20:5700) Starting transceiver...
2026-01-29 03:21:08.765 [INFO] transceiver.py:243 Starting clock generator
2026-01-29 03:21:08.766 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-01-29 03:21:08.766 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:21:08.766 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:21:08.766 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:21:08.766 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETRXGAIN
2026-01-29 03:21:08.766 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:21:08.766 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:21:08.766 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:21:08.766 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:21:08.766 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:21:08.766 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:21:08.766 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:21:08.766 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:21:08.766 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:21:08.767 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:21:08.767 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:21:08.767 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:21:08.767 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:21:08.767 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:21:08.767 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:21:08.767 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:21:08.767 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:21:08.767 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:21:08.767 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:21:08.767 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:21:08.767 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:21:08.767 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:21:08.767 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:21:08.771 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-01-29 03:21:09.255 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-01-29 03:21:09.293 [DEBUG] fake_trx.py:278 (BTS@172.18.28.20:5700) Recv FAKE_TOA cmd
2026-01-29 03:21:09.295 [DEBUG] fake_trx.py:297 (BTS@172.18.28.20:5700) Recv FAKE_RSSI cmd
2026-01-29 03:21:09.296 [DEBUG] fake_trx.py:322 (BTS@172.18.28.20:5700) Recv FAKE_CI cmd
2026-01-29 03:21:09.296 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:21:09.320 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 03:21:09.320 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 03:21:09.320 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 03:21:09.365 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 03:21:09.365 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 03:21:09.365 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 03:21:09.365 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.28.22:6700) Recv POWERON CMD
2026-01-29 03:21:09.365 [INFO] ctrl_if_trx.py:109 (MS@172.18.28.22:6700) Starting transceiver...
2026-01-29 03:21:09.395 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:21:09.400 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 03:21:09.400 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 03:21:09.400 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 03:21:09.401 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 03:21:09.609 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 03:21:09.611 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:21:09.618 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 03:21:09.618 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 03:21:09.635 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 03:21:09.635 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 03:21:09.635 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 03:21:09.644 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 03:21:09.644 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 03:21:09.644 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 03:21:09.644 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.28.22:6700) Recv POWERON CMD
2026-01-29 03:21:09.644 [INFO] ctrl_if_trx.py:109 (MS@172.18.28.22:6700) Starting transceiver...
2026-01-29 03:21:09.675 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:21:09.679 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 03:21:09.679 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 03:21:09.680 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 03:21:09.680 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 03:21:09.732 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-01-29 03:21:09.769 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 03:21:09.769 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:21:09.770 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:21:09.772 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:21:09.897 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 03:21:09.899 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:21:09.904 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 03:21:09.904 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 03:21:09.912 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 03:21:09.913 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:21:09.913 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:21:09.913 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:21:09.915 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 03:21:09.915 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 03:21:09.915 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 03:21:09.915 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.28.20:5700) Recv POWEROFF cmd
2026-01-29 03:21:09.915 [INFO] ctrl_if_trx.py:117 (BTS@172.18.28.20:5700) Stopping transceiver...
2026-01-29 03:21:09.915 [INFO] transceiver.py:246 Stopping clock generator
2026-01-29 03:21:09.915 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 03:21:09.915 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=245 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:21:09.915 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=245 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:21:09.915 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=245 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:21:09.916 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=245 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:21:09.916 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=245 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:21:09.916 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=245 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:21:09.916 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=245 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:21:09.916 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=245 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:21:14.916 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.28.20:5700) Recv POWEROFF cmd
2026-01-29 03:21:14.916 [INFO] ctrl_if_trx.py:117 (BTS@172.18.28.20:5700) Stopping transceiver...
2026-01-29 03:21:14.918 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 03:21:14.919 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 03:21:14.920 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 03:21:14.920 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 03:21:14.930 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 03:21:14.931 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.28.20:5700) Recv SETFORMAT cmd
2026-01-29 03:21:14.931 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.28.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:21:14.931 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.28.20:5700) Recv SETFORMAT cmd
2026-01-29 03:21:14.932 [INFO] ctrl_if_trx.py:201 (BTS@172.18.28.20:5700) TRXD header version 1 -> 1
2026-01-29 03:21:14.935 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.28.20:5700/1) Recv RXTUNE cmd
2026-01-29 03:21:14.936 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.28.20:5700/1) Recv TXTUNE cmd
2026-01-29 03:21:14.936 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.28.20:5700/1) Recv SETFORMAT cmd
2026-01-29 03:21:14.936 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.28.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:21:14.937 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 03:21:14.937 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.28.20:5700/1) Recv NOMTXPOWER cmd
2026-01-29 03:21:14.938 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.28.20:5700/1) Recv SETFORMAT cmd
2026-01-29 03:21:14.938 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.28.20:5700/1) TRXD header version 1 -> 1
2026-01-29 03:21:14.939 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.28.20:5700/2) Recv RXTUNE cmd
2026-01-29 03:21:14.939 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.28.20:5700/2) Recv TXTUNE cmd
2026-01-29 03:21:14.940 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.28.20:5700/2) Recv SETFORMAT cmd
2026-01-29 03:21:14.940 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.28.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:21:14.940 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 03:21:14.940 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.28.20:5700/2) Recv NOMTXPOWER cmd
2026-01-29 03:21:14.940 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.28.20:5700/2) Recv SETFORMAT cmd
2026-01-29 03:21:14.940 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.28.20:5700/2) TRXD header version 1 -> 1
2026-01-29 03:21:14.942 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.28.20:5700/3) Recv RXTUNE cmd
2026-01-29 03:21:14.942 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.28.20:5700/3) Recv TXTUNE cmd
2026-01-29 03:21:14.942 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.28.20:5700/3) Recv SETFORMAT cmd
2026-01-29 03:21:14.942 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.28.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:21:14.942 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.28.20:5700/3) Recv NOMTXPOWER cmd
2026-01-29 03:21:14.942 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.28.20:5700/3) Recv SETFORMAT cmd
2026-01-29 03:21:14.942 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.28.20:5700/3) TRXD header version 1 -> 1
2026-01-29 03:21:14.943 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 03:21:14.953 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.28.20:5700) Recv RXTUNE cmd
2026-01-29 03:21:14.953 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETTSC
2026-01-29 03:21:14.953 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETTSC
2026-01-29 03:21:14.953 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETTSC
2026-01-29 03:21:14.953 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.28.20:5700) Recv TXTUNE cmd
2026-01-29 03:21:14.953 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETRXGAIN
2026-01-29 03:21:14.953 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETRXGAIN
2026-01-29 03:21:14.953 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETRXGAIN
2026-01-29 03:21:14.954 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETTSC
2026-01-29 03:21:14.954 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:21:14.954 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:21:14.954 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:21:14.954 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.28.20:5700) Recv NOMTXPOWER cmd
2026-01-29 03:21:14.954 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:21:14.954 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:21:14.954 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:21:14.954 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.28.20:5700) Recv POWERON CMD
2026-01-29 03:21:14.954 [INFO] ctrl_if_trx.py:109 (BTS@172.18.28.20:5700) Starting transceiver...
2026-01-29 03:21:14.954 [INFO] transceiver.py:243 Starting clock generator
2026-01-29 03:21:14.954 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-01-29 03:21:14.955 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:21:14.955 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:21:14.955 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:21:14.955 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETRXGAIN
2026-01-29 03:21:14.955 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:21:14.955 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:21:14.955 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:21:14.955 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:21:14.955 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:21:14.955 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:21:14.955 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:21:14.955 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:21:14.955 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:21:14.955 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:21:14.955 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:21:14.955 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:21:14.955 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:21:14.955 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:21:14.955 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:21:14.955 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:21:14.956 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:21:14.956 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:21:14.956 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:21:14.956 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:21:14.956 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:21:14.956 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:21:14.956 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:21:14.959 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-01-29 03:21:15.442 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-01-29 03:21:15.482 [DEBUG] fake_trx.py:278 (BTS@172.18.28.20:5700) Recv FAKE_TOA cmd
2026-01-29 03:21:15.483 [DEBUG] fake_trx.py:297 (BTS@172.18.28.20:5700) Recv FAKE_RSSI cmd
2026-01-29 03:21:15.485 [DEBUG] fake_trx.py:322 (BTS@172.18.28.20:5700) Recv FAKE_CI cmd
2026-01-29 03:21:15.485 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:21:15.504 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 03:21:15.505 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 03:21:15.505 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 03:21:15.536 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 03:21:15.537 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 03:21:15.537 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 03:21:15.537 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.28.22:6700) Recv POWERON CMD
2026-01-29 03:21:15.537 [INFO] ctrl_if_trx.py:109 (MS@172.18.28.22:6700) Starting transceiver...
2026-01-29 03:21:15.581 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:21:15.586 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.28.22:6700) Recv SETFH cmd
2026-01-29 03:21:15.586 [INFO] transceiver.py:201 (MS@172.18.28.22:6700) Frequency hopping configured: hsn=5, maio=0, ma_len=4
2026-01-29 03:21:15.586 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 03:21:15.587 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 03:21:15.919 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-01-29 03:21:15.960 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 03:21:15.961 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:21:15.963 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:21:15.964 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:21:16.398 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-01-29 03:21:16.877 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-01-29 03:21:16.961 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 03:21:16.962 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:21:16.964 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:21:16.965 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:21:17.355 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-01-29 03:21:17.834 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-01-29 03:21:17.961 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 03:21:17.963 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:21:17.966 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:21:17.966 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:21:18.312 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-01-29 03:21:18.791 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-01-29 03:21:18.962 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 03:21:18.964 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:21:18.966 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:21:18.967 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:21:19.269 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-01-29 03:21:19.591 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 03:21:19.591 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 03:21:19.591 [INFO] transceiver.py:205 (MS@172.18.28.22:6700) Frequency hopping disabled
2026-01-29 03:21:19.596 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 03:21:19.596 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:21:19.596 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:21:19.596 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:21:19.596 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 03:21:19.596 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 03:21:19.596 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 03:21:19.596 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 03:21:19.596 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.28.20:5700) Recv POWEROFF cmd
2026-01-29 03:21:19.596 [INFO] ctrl_if_trx.py:117 (BTS@172.18.28.20:5700) Stopping transceiver...
2026-01-29 03:21:19.596 [INFO] transceiver.py:246 Stopping clock generator
2026-01-29 03:21:24.599 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.28.20:5700) Recv POWEROFF cmd
2026-01-29 03:21:24.599 [INFO] ctrl_if_trx.py:117 (BTS@172.18.28.20:5700) Stopping transceiver...
2026-01-29 03:21:24.600 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 03:21:24.602 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 03:21:24.602 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 03:21:24.602 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 03:21:24.610 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 03:21:24.611 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.28.20:5700) Recv SETFORMAT cmd
2026-01-29 03:21:24.611 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.28.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:21:24.611 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.28.20:5700) Recv SETFORMAT cmd
2026-01-29 03:21:24.611 [INFO] ctrl_if_trx.py:201 (BTS@172.18.28.20:5700) TRXD header version 1 -> 1
2026-01-29 03:21:24.614 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.28.20:5700/1) Recv RXTUNE cmd
2026-01-29 03:21:24.614 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.28.20:5700/1) Recv TXTUNE cmd
2026-01-29 03:21:24.615 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.28.20:5700/1) Recv SETFORMAT cmd
2026-01-29 03:21:24.615 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.28.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:21:24.615 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 03:21:24.616 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.28.20:5700/1) Recv NOMTXPOWER cmd
2026-01-29 03:21:24.616 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.28.20:5700/1) Recv SETFORMAT cmd
2026-01-29 03:21:24.616 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.28.20:5700/1) TRXD header version 1 -> 1
2026-01-29 03:21:24.617 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.28.20:5700/2) Recv RXTUNE cmd
2026-01-29 03:21:24.617 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.28.20:5700/2) Recv TXTUNE cmd
2026-01-29 03:21:24.617 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.28.20:5700/2) Recv SETFORMAT cmd
2026-01-29 03:21:24.617 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.28.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:21:24.617 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 03:21:24.617 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.28.20:5700/2) Recv NOMTXPOWER cmd
2026-01-29 03:21:24.618 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.28.20:5700/2) Recv SETFORMAT cmd
2026-01-29 03:21:24.618 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.28.20:5700/2) TRXD header version 1 -> 1
2026-01-29 03:21:24.619 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.28.20:5700/3) Recv RXTUNE cmd
2026-01-29 03:21:24.619 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.28.20:5700/3) Recv TXTUNE cmd
2026-01-29 03:21:24.619 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.28.20:5700/3) Recv SETFORMAT cmd
2026-01-29 03:21:24.620 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.28.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:21:24.620 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 03:21:24.620 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.28.20:5700/3) Recv NOMTXPOWER cmd
2026-01-29 03:21:24.620 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.28.20:5700/3) Recv SETFORMAT cmd
2026-01-29 03:21:24.620 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.28.20:5700/3) TRXD header version 1 -> 1
2026-01-29 03:21:24.622 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.28.20:5700) Recv RXTUNE cmd
2026-01-29 03:21:24.622 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETTSC
2026-01-29 03:21:24.622 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETTSC
2026-01-29 03:21:24.622 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETTSC
2026-01-29 03:21:24.622 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.28.20:5700) Recv TXTUNE cmd
2026-01-29 03:21:24.622 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETRXGAIN
2026-01-29 03:21:24.623 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETRXGAIN
2026-01-29 03:21:24.623 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETRXGAIN
2026-01-29 03:21:24.623 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETTSC
2026-01-29 03:21:24.623 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:21:24.623 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:21:24.623 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:21:24.623 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.28.20:5700) Recv NOMTXPOWER cmd
2026-01-29 03:21:24.623 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:21:24.623 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:21:24.623 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:21:24.623 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.28.20:5700) Recv POWERON CMD
2026-01-29 03:21:24.623 [INFO] ctrl_if_trx.py:109 (BTS@172.18.28.20:5700) Starting transceiver...
2026-01-29 03:21:24.623 [INFO] transceiver.py:243 Starting clock generator
2026-01-29 03:21:24.623 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-01-29 03:21:24.623 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:21:24.623 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:21:24.623 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:21:24.623 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETRXGAIN
2026-01-29 03:21:24.623 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:21:24.623 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:21:24.623 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:21:24.623 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:21:24.623 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:21:24.624 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:21:24.624 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:21:24.624 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:21:24.624 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:21:24.624 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:21:24.624 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:21:24.624 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:21:24.624 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:21:24.624 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:21:24.624 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:21:24.624 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:21:24.624 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:21:24.624 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:21:24.624 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:21:24.624 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:21:24.624 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:21:24.624 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:21:24.624 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:21:24.628 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-01-29 03:21:25.110 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-01-29 03:21:25.147 [DEBUG] fake_trx.py:278 (BTS@172.18.28.20:5700) Recv FAKE_TOA cmd
2026-01-29 03:21:25.148 [DEBUG] fake_trx.py:297 (BTS@172.18.28.20:5700) Recv FAKE_RSSI cmd
2026-01-29 03:21:25.149 [DEBUG] fake_trx.py:322 (BTS@172.18.28.20:5700) Recv FAKE_CI cmd
2026-01-29 03:21:25.149 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:21:25.157 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 03:21:25.157 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 03:21:25.157 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 03:21:25.171 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 03:21:25.171 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 03:21:25.171 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 03:21:25.172 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.28.22:6700) Recv POWERON CMD
2026-01-29 03:21:25.172 [INFO] ctrl_if_trx.py:109 (MS@172.18.28.22:6700) Starting transceiver...
2026-01-29 03:21:25.204 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:21:25.210 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 03:21:25.210 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 03:21:25.210 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 03:21:25.210 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 03:21:25.588 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-01-29 03:21:25.626 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 03:21:25.626 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:21:25.627 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:21:25.629 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:21:25.914 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 03:21:25.916 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:21:25.923 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 03:21:25.923 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 03:21:25.932 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 03:21:25.932 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:21:25.932 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:21:25.932 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:21:25.932 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 03:21:25.932 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 03:21:25.932 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 03:21:25.932 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 03:21:25.932 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.28.20:5700) Recv POWEROFF cmd
2026-01-29 03:21:25.932 [INFO] ctrl_if_trx.py:117 (BTS@172.18.28.20:5700) Stopping transceiver...
2026-01-29 03:21:25.932 [INFO] transceiver.py:246 Stopping clock generator
2026-01-29 03:21:30.935 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.28.20:5700) Recv POWEROFF cmd
2026-01-29 03:21:30.935 [INFO] ctrl_if_trx.py:117 (BTS@172.18.28.20:5700) Stopping transceiver...
2026-01-29 03:21:30.936 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 03:21:30.938 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 03:21:30.938 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 03:21:30.938 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 03:21:30.946 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 03:21:30.948 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.28.20:5700) Recv SETFORMAT cmd
2026-01-29 03:21:30.948 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.28.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:21:30.949 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.28.20:5700) Recv SETFORMAT cmd
2026-01-29 03:21:30.949 [INFO] ctrl_if_trx.py:201 (BTS@172.18.28.20:5700) TRXD header version 1 -> 1
2026-01-29 03:21:30.953 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.28.20:5700/1) Recv RXTUNE cmd
2026-01-29 03:21:30.953 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.28.20:5700/1) Recv TXTUNE cmd
2026-01-29 03:21:30.953 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.28.20:5700/1) Recv SETFORMAT cmd
2026-01-29 03:21:30.953 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.28.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:21:30.953 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 03:21:30.954 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.28.20:5700/1) Recv NOMTXPOWER cmd
2026-01-29 03:21:30.954 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.28.20:5700/1) Recv SETFORMAT cmd
2026-01-29 03:21:30.954 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.28.20:5700/1) TRXD header version 1 -> 1
2026-01-29 03:21:30.956 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.28.20:5700/2) Recv RXTUNE cmd
2026-01-29 03:21:30.957 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.28.20:5700/2) Recv TXTUNE cmd
2026-01-29 03:21:30.957 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.28.20:5700/2) Recv SETFORMAT cmd
2026-01-29 03:21:30.957 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.28.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:21:30.957 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 03:21:30.957 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.28.20:5700/2) Recv NOMTXPOWER cmd
2026-01-29 03:21:30.957 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.28.20:5700/2) Recv SETFORMAT cmd
2026-01-29 03:21:30.957 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.28.20:5700/2) TRXD header version 1 -> 1
2026-01-29 03:21:30.959 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.28.20:5700/3) Recv RXTUNE cmd
2026-01-29 03:21:30.959 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.28.20:5700/3) Recv TXTUNE cmd
2026-01-29 03:21:30.959 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.28.20:5700/3) Recv SETFORMAT cmd
2026-01-29 03:21:30.960 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.28.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:21:30.960 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 03:21:30.960 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.28.20:5700/3) Recv NOMTXPOWER cmd
2026-01-29 03:21:30.960 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.28.20:5700/3) Recv SETFORMAT cmd
2026-01-29 03:21:30.960 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.28.20:5700/3) TRXD header version 1 -> 1
2026-01-29 03:21:30.963 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.28.20:5700) Recv RXTUNE cmd
2026-01-29 03:21:30.963 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETTSC
2026-01-29 03:21:30.963 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETTSC
2026-01-29 03:21:30.963 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETTSC
2026-01-29 03:21:30.963 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.28.20:5700) Recv TXTUNE cmd
2026-01-29 03:21:30.963 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETRXGAIN
2026-01-29 03:21:30.963 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETRXGAIN
2026-01-29 03:21:30.963 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETRXGAIN
2026-01-29 03:21:30.963 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETTSC
2026-01-29 03:21:30.963 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:21:30.963 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:21:30.963 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:21:30.963 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.28.20:5700) Recv NOMTXPOWER cmd
2026-01-29 03:21:30.963 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:21:30.963 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:21:30.963 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:21:30.964 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.28.20:5700) Recv POWERON CMD
2026-01-29 03:21:30.964 [INFO] ctrl_if_trx.py:109 (BTS@172.18.28.20:5700) Starting transceiver...
2026-01-29 03:21:30.964 [INFO] transceiver.py:243 Starting clock generator
2026-01-29 03:21:30.964 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-01-29 03:21:30.964 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:21:30.964 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:21:30.964 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:21:30.964 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETRXGAIN
2026-01-29 03:21:30.964 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:21:30.964 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:21:30.964 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:21:30.964 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:21:30.964 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:21:30.964 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:21:30.964 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:21:30.964 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:21:30.964 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:21:30.964 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:21:30.964 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:21:30.965 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:21:30.965 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:21:30.965 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:21:30.965 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:21:30.965 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:21:30.965 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:21:30.965 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:21:30.965 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:21:30.965 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:21:30.965 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:21:30.965 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:21:30.965 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:21:30.968 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-01-29 03:21:31.452 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-01-29 03:21:31.495 [DEBUG] fake_trx.py:278 (BTS@172.18.28.20:5700) Recv FAKE_TOA cmd
2026-01-29 03:21:31.497 [DEBUG] fake_trx.py:297 (BTS@172.18.28.20:5700) Recv FAKE_RSSI cmd
2026-01-29 03:21:31.498 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:21:31.499 [DEBUG] fake_trx.py:322 (BTS@172.18.28.20:5700) Recv FAKE_CI cmd
2026-01-29 03:21:31.525 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 03:21:31.525 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 03:21:31.526 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 03:21:31.567 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 03:21:31.568 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 03:21:31.568 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 03:21:31.568 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.28.22:6700) Recv POWERON CMD
2026-01-29 03:21:31.568 [INFO] ctrl_if_trx.py:109 (MS@172.18.28.22:6700) Starting transceiver...
2026-01-29 03:21:31.592 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:21:31.597 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 03:21:31.597 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 03:21:31.597 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 03:21:31.597 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 03:21:31.929 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-01-29 03:21:31.968 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 03:21:31.968 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:21:31.970 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:21:31.974 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:21:32.315 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 03:21:32.317 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:21:32.323 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 03:21:32.323 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 03:21:32.330 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 03:21:32.330 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:21:32.330 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:21:32.330 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:21:32.330 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 03:21:32.330 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 03:21:32.331 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 03:21:32.331 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 03:21:32.331 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.28.20:5700) Recv POWEROFF cmd
2026-01-29 03:21:32.331 [INFO] ctrl_if_trx.py:117 (BTS@172.18.28.20:5700) Stopping transceiver...
2026-01-29 03:21:32.331 [INFO] transceiver.py:246 Stopping clock generator
2026-01-29 03:21:32.331 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=293 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:21:32.331 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=293 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:21:32.331 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=293 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:21:32.331 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=293 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:21:32.331 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=293 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:21:32.331 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=293 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:21:32.331 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=293 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:21:37.333 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.28.20:5700) Recv POWEROFF cmd
2026-01-29 03:21:37.333 [INFO] ctrl_if_trx.py:117 (BTS@172.18.28.20:5700) Stopping transceiver...
2026-01-29 03:21:37.335 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 03:21:37.336 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 03:21:37.337 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 03:21:37.337 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 03:21:37.346 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 03:21:37.346 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.28.20:5700) Recv SETFORMAT cmd
2026-01-29 03:21:37.347 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.28.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:21:37.347 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.28.20:5700) Recv SETFORMAT cmd
2026-01-29 03:21:37.347 [INFO] ctrl_if_trx.py:201 (BTS@172.18.28.20:5700) TRXD header version 1 -> 1
2026-01-29 03:21:37.350 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.28.20:5700/1) Recv RXTUNE cmd
2026-01-29 03:21:37.351 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.28.20:5700/1) Recv TXTUNE cmd
2026-01-29 03:21:37.351 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.28.20:5700/1) Recv SETFORMAT cmd
2026-01-29 03:21:37.351 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.28.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:21:37.351 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 03:21:37.352 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.28.20:5700/1) Recv NOMTXPOWER cmd
2026-01-29 03:21:37.352 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.28.20:5700/1) Recv SETFORMAT cmd
2026-01-29 03:21:37.352 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.28.20:5700/1) TRXD header version 1 -> 1
2026-01-29 03:21:37.353 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.28.20:5700/2) Recv RXTUNE cmd
2026-01-29 03:21:37.353 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.28.20:5700/2) Recv TXTUNE cmd
2026-01-29 03:21:37.354 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.28.20:5700/2) Recv SETFORMAT cmd
2026-01-29 03:21:37.354 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.28.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:21:37.354 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 03:21:37.354 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.28.20:5700/2) Recv NOMTXPOWER cmd
2026-01-29 03:21:37.354 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.28.20:5700/2) Recv SETFORMAT cmd
2026-01-29 03:21:37.354 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.28.20:5700/2) TRXD header version 1 -> 1
2026-01-29 03:21:37.355 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.28.20:5700/3) Recv RXTUNE cmd
2026-01-29 03:21:37.355 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.28.20:5700/3) Recv TXTUNE cmd
2026-01-29 03:21:37.355 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.28.20:5700/3) Recv SETFORMAT cmd
2026-01-29 03:21:37.356 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.28.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:21:37.356 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 03:21:37.356 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.28.20:5700/3) Recv NOMTXPOWER cmd
2026-01-29 03:21:37.356 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.28.20:5700/3) Recv SETFORMAT cmd
2026-01-29 03:21:37.356 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.28.20:5700/3) TRXD header version 1 -> 1
2026-01-29 03:21:37.358 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.28.20:5700) Recv RXTUNE cmd
2026-01-29 03:21:37.358 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETTSC
2026-01-29 03:21:37.358 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETTSC
2026-01-29 03:21:37.358 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETTSC
2026-01-29 03:21:37.358 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.28.20:5700) Recv TXTUNE cmd
2026-01-29 03:21:37.358 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETRXGAIN
2026-01-29 03:21:37.359 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETRXGAIN
2026-01-29 03:21:37.359 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETRXGAIN
2026-01-29 03:21:37.359 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETTSC
2026-01-29 03:21:37.359 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:21:37.359 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:21:37.359 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.28.20:5700) Recv NOMTXPOWER cmd
2026-01-29 03:21:37.359 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:21:37.359 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:21:37.359 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:21:37.359 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.28.20:5700) Recv POWERON CMD
2026-01-29 03:21:37.359 [INFO] ctrl_if_trx.py:109 (BTS@172.18.28.20:5700) Starting transceiver...
2026-01-29 03:21:37.359 [INFO] transceiver.py:243 Starting clock generator
2026-01-29 03:21:37.359 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-01-29 03:21:37.359 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:21:37.359 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:21:37.359 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:21:37.359 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETRXGAIN
2026-01-29 03:21:37.359 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:21:37.359 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:21:37.359 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:21:37.359 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:21:37.359 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:21:37.359 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:21:37.359 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:21:37.360 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:21:37.360 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:21:37.360 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:21:37.360 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:21:37.360 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:21:37.360 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:21:37.360 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:21:37.360 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:21:37.360 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:21:37.360 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:21:37.360 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:21:37.360 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:21:37.360 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:21:37.360 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:21:37.360 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:21:37.360 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:21:37.360 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:21:37.364 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-01-29 03:21:37.847 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-01-29 03:21:37.888 [DEBUG] fake_trx.py:278 (BTS@172.18.28.20:5700) Recv FAKE_TOA cmd
2026-01-29 03:21:37.890 [DEBUG] fake_trx.py:297 (BTS@172.18.28.20:5700) Recv FAKE_RSSI cmd
2026-01-29 03:21:37.891 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:21:37.892 [DEBUG] fake_trx.py:322 (BTS@172.18.28.20:5700) Recv FAKE_CI cmd
2026-01-29 03:21:37.916 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 03:21:37.917 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 03:21:37.917 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 03:21:37.963 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 03:21:37.963 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 03:21:37.964 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 03:21:37.964 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.28.22:6700) Recv POWERON CMD
2026-01-29 03:21:37.964 [INFO] ctrl_if_trx.py:109 (MS@172.18.28.22:6700) Starting transceiver...
2026-01-29 03:21:37.988 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:21:37.993 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 03:21:37.993 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 03:21:37.994 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 03:21:37.994 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 03:21:38.323 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-01-29 03:21:38.361 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 03:21:38.362 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:21:38.364 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:21:38.365 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:21:38.710 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 03:21:38.712 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:21:38.714 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 03:21:38.714 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 03:21:38.723 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 03:21:38.723 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:21:38.723 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:21:38.723 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:21:38.726 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 03:21:38.727 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 03:21:38.727 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 03:21:38.727 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.28.20:5700) Recv POWEROFF cmd
2026-01-29 03:21:38.727 [INFO] ctrl_if_trx.py:117 (BTS@172.18.28.20:5700) Stopping transceiver...
2026-01-29 03:21:38.727 [INFO] transceiver.py:246 Stopping clock generator
2026-01-29 03:21:38.727 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 03:21:38.728 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=292 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:21:38.728 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=292 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:21:38.728 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=292 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:21:38.728 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=292 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:21:38.728 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=292 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:21:38.728 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=292 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:21:38.728 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=292 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:21:38.728 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=293 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:21:38.728 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=293 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:21:38.729 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=293 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:21:38.729 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=293 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:21:38.729 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=293 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:21:38.729 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=293 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:21:38.729 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=293 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:21:38.729 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=293 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:21:43.727 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.28.20:5700) Recv POWEROFF cmd
2026-01-29 03:21:43.727 [INFO] ctrl_if_trx.py:117 (BTS@172.18.28.20:5700) Stopping transceiver...
2026-01-29 03:21:43.728 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 03:21:43.730 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 03:21:43.731 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 03:21:43.731 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 03:21:43.738 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 03:21:43.739 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.28.20:5700) Recv SETFORMAT cmd
2026-01-29 03:21:43.739 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.28.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:21:43.739 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.28.20:5700) Recv SETFORMAT cmd
2026-01-29 03:21:43.739 [INFO] ctrl_if_trx.py:201 (BTS@172.18.28.20:5700) TRXD header version 1 -> 1
2026-01-29 03:21:43.741 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.28.20:5700/1) Recv RXTUNE cmd
2026-01-29 03:21:43.741 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.28.20:5700/1) Recv TXTUNE cmd
2026-01-29 03:21:43.741 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.28.20:5700/1) Recv SETFORMAT cmd
2026-01-29 03:21:43.741 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.28.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:21:43.742 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 03:21:43.742 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.28.20:5700/1) Recv NOMTXPOWER cmd
2026-01-29 03:21:43.742 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.28.20:5700/1) Recv SETFORMAT cmd
2026-01-29 03:21:43.742 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.28.20:5700/1) TRXD header version 1 -> 1
2026-01-29 03:21:43.743 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.28.20:5700/2) Recv RXTUNE cmd
2026-01-29 03:21:43.743 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.28.20:5700/2) Recv TXTUNE cmd
2026-01-29 03:21:43.743 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.28.20:5700/2) Recv SETFORMAT cmd
2026-01-29 03:21:43.743 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.28.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:21:43.744 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 03:21:43.744 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.28.20:5700/2) Recv NOMTXPOWER cmd
2026-01-29 03:21:43.744 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.28.20:5700/2) Recv SETFORMAT cmd
2026-01-29 03:21:43.744 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.28.20:5700/2) TRXD header version 1 -> 1
2026-01-29 03:21:43.745 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.28.20:5700/3) Recv RXTUNE cmd
2026-01-29 03:21:43.745 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.28.20:5700/3) Recv TXTUNE cmd
2026-01-29 03:21:43.745 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.28.20:5700/3) Recv SETFORMAT cmd
2026-01-29 03:21:43.745 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.28.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:21:43.745 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 03:21:43.746 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.28.20:5700/3) Recv NOMTXPOWER cmd
2026-01-29 03:21:43.746 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.28.20:5700/3) Recv SETFORMAT cmd
2026-01-29 03:21:43.746 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.28.20:5700/3) TRXD header version 1 -> 1
2026-01-29 03:21:43.748 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.28.20:5700) Recv RXTUNE cmd
2026-01-29 03:21:43.748 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETTSC
2026-01-29 03:21:43.748 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETTSC
2026-01-29 03:21:43.748 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETTSC
2026-01-29 03:21:43.748 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.28.20:5700) Recv TXTUNE cmd
2026-01-29 03:21:43.748 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETRXGAIN
2026-01-29 03:21:43.748 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETRXGAIN
2026-01-29 03:21:43.748 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETRXGAIN
2026-01-29 03:21:43.748 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETTSC
2026-01-29 03:21:43.748 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:21:43.748 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:21:43.748 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:21:43.748 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.28.20:5700) Recv NOMTXPOWER cmd
2026-01-29 03:21:43.748 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:21:43.748 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:21:43.748 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:21:43.748 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.28.20:5700) Recv POWERON CMD
2026-01-29 03:21:43.749 [INFO] ctrl_if_trx.py:109 (BTS@172.18.28.20:5700) Starting transceiver...
2026-01-29 03:21:43.749 [INFO] transceiver.py:243 Starting clock generator
2026-01-29 03:21:43.749 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-01-29 03:21:43.749 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:21:43.749 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:21:43.749 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:21:43.749 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETRXGAIN
2026-01-29 03:21:43.749 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:21:43.749 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:21:43.749 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:21:43.749 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:21:43.749 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:21:43.749 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:21:43.749 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:21:43.749 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:21:43.749 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:21:43.749 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:21:43.749 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:21:43.749 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:21:43.749 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:21:43.749 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:21:43.749 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:21:43.749 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:21:43.750 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:21:43.750 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:21:43.750 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:21:43.750 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:21:43.750 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:21:43.750 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:21:43.750 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:21:43.753 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-01-29 03:21:44.237 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-01-29 03:21:44.280 [DEBUG] fake_trx.py:278 (BTS@172.18.28.20:5700) Recv FAKE_TOA cmd
2026-01-29 03:21:44.282 [DEBUG] fake_trx.py:297 (BTS@172.18.28.20:5700) Recv FAKE_RSSI cmd
2026-01-29 03:21:44.284 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:21:44.285 [DEBUG] fake_trx.py:322 (BTS@172.18.28.20:5700) Recv FAKE_CI cmd
2026-01-29 03:21:44.312 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 03:21:44.312 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 03:21:44.312 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 03:21:44.359 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 03:21:44.359 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 03:21:44.359 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 03:21:44.359 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.28.22:6700) Recv POWERON CMD
2026-01-29 03:21:44.359 [INFO] ctrl_if_trx.py:109 (MS@172.18.28.22:6700) Starting transceiver...
2026-01-29 03:21:44.377 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:21:44.381 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.28.22:6700) Recv SETFH cmd
2026-01-29 03:21:44.382 [INFO] transceiver.py:201 (MS@172.18.28.22:6700) Frequency hopping configured: hsn=5, maio=0, ma_len=4
2026-01-29 03:21:44.382 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 03:21:44.382 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 03:21:44.714 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-01-29 03:21:44.752 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:21:44.752 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 03:21:44.753 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:21:44.757 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:21:45.193 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-01-29 03:21:45.243 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 03:21:45.245 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:21:45.252 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 03:21:45.252 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 03:21:45.252 [INFO] transceiver.py:205 (MS@172.18.28.22:6700) Frequency hopping disabled
2026-01-29 03:21:45.261 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 03:21:45.261 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:21:45.261 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:21:45.262 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:21:45.265 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 03:21:45.265 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 03:21:45.266 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 03:21:45.266 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 03:21:45.266 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.28.20:5700) Recv POWEROFF cmd
2026-01-29 03:21:45.266 [INFO] ctrl_if_trx.py:117 (BTS@172.18.28.20:5700) Stopping transceiver...
2026-01-29 03:21:45.266 [INFO] transceiver.py:246 Stopping clock generator
2026-01-29 03:21:45.266 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=322 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:21:45.267 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=322 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:21:45.267 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=322 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:21:45.267 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=322 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:21:45.267 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=322 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:21:45.267 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=322 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:21:45.267 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=322 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:21:45.267 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=323 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:21:45.267 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=323 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:21:45.267 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=323 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:21:45.267 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=323 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:21:45.268 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=323 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:21:45.268 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=323 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:21:45.268 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=323 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:21:45.268 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=323 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:21:50.265 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.28.20:5700) Recv POWEROFF cmd
2026-01-29 03:21:50.265 [INFO] ctrl_if_trx.py:117 (BTS@172.18.28.20:5700) Stopping transceiver...
2026-01-29 03:21:50.267 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 03:21:50.268 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 03:21:50.268 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 03:21:50.268 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 03:21:50.275 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 03:21:50.276 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.28.20:5700) Recv SETFORMAT cmd
2026-01-29 03:21:50.276 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.28.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:21:50.277 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.28.20:5700) Recv SETFORMAT cmd
2026-01-29 03:21:50.277 [INFO] ctrl_if_trx.py:201 (BTS@172.18.28.20:5700) TRXD header version 1 -> 1
2026-01-29 03:21:50.278 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.28.20:5700/1) Recv RXTUNE cmd
2026-01-29 03:21:50.279 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.28.20:5700/1) Recv TXTUNE cmd
2026-01-29 03:21:50.279 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.28.20:5700/1) Recv SETFORMAT cmd
2026-01-29 03:21:50.279 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.28.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:21:50.280 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 03:21:50.280 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.28.20:5700/1) Recv NOMTXPOWER cmd
2026-01-29 03:21:50.280 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.28.20:5700/1) Recv SETFORMAT cmd
2026-01-29 03:21:50.280 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.28.20:5700/1) TRXD header version 1 -> 1
2026-01-29 03:21:50.281 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.28.20:5700/2) Recv RXTUNE cmd
2026-01-29 03:21:50.281 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.28.20:5700/2) Recv TXTUNE cmd
2026-01-29 03:21:50.281 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.28.20:5700/2) Recv SETFORMAT cmd
2026-01-29 03:21:50.281 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.28.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:21:50.281 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 03:21:50.281 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.28.20:5700/2) Recv NOMTXPOWER cmd
2026-01-29 03:21:50.281 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.28.20:5700/2) Recv SETFORMAT cmd
2026-01-29 03:21:50.281 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.28.20:5700/2) TRXD header version 1 -> 1
2026-01-29 03:21:50.283 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.28.20:5700/3) Recv RXTUNE cmd
2026-01-29 03:21:50.283 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.28.20:5700/3) Recv TXTUNE cmd
2026-01-29 03:21:50.283 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.28.20:5700/3) Recv SETFORMAT cmd
2026-01-29 03:21:50.283 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.28.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:21:50.283 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 03:21:50.283 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.28.20:5700/3) Recv NOMTXPOWER cmd
2026-01-29 03:21:50.283 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.28.20:5700/3) Recv SETFORMAT cmd
2026-01-29 03:21:50.283 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.28.20:5700/3) TRXD header version 1 -> 1
2026-01-29 03:21:50.285 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.28.20:5700) Recv RXTUNE cmd
2026-01-29 03:21:50.285 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETTSC
2026-01-29 03:21:50.285 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETTSC
2026-01-29 03:21:50.285 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETTSC
2026-01-29 03:21:50.285 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.28.20:5700) Recv TXTUNE cmd
2026-01-29 03:21:50.285 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETRXGAIN
2026-01-29 03:21:50.285 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETRXGAIN
2026-01-29 03:21:50.285 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETRXGAIN
2026-01-29 03:21:50.285 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETTSC
2026-01-29 03:21:50.285 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:21:50.286 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:21:50.286 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:21:50.286 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.28.20:5700) Recv NOMTXPOWER cmd
2026-01-29 03:21:50.286 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:21:50.286 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:21:50.286 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:21:50.286 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.28.20:5700) Recv POWERON CMD
2026-01-29 03:21:50.286 [INFO] ctrl_if_trx.py:109 (BTS@172.18.28.20:5700) Starting transceiver...
2026-01-29 03:21:50.286 [INFO] transceiver.py:243 Starting clock generator
2026-01-29 03:21:50.286 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-01-29 03:21:50.286 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:21:50.286 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:21:50.286 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:21:50.286 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETRXGAIN
2026-01-29 03:21:50.286 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:21:50.286 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:21:50.286 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:21:50.286 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:21:50.286 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:21:50.286 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:21:50.286 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:21:50.286 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:21:50.286 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:21:50.286 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:21:50.286 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:21:50.286 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:21:50.286 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:21:50.286 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:21:50.286 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:21:50.286 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:21:50.286 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:21:50.286 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:21:50.286 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:21:50.287 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:21:50.287 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:21:50.287 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:21:50.287 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:21:50.291 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-01-29 03:21:50.774 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-01-29 03:21:50.817 [DEBUG] fake_trx.py:278 (BTS@172.18.28.20:5700) Recv FAKE_TOA cmd
2026-01-29 03:21:50.819 [DEBUG] fake_trx.py:297 (BTS@172.18.28.20:5700) Recv FAKE_RSSI cmd
2026-01-29 03:21:50.822 [DEBUG] fake_trx.py:322 (BTS@172.18.28.20:5700) Recv FAKE_CI cmd
2026-01-29 03:21:50.822 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:21:50.848 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 03:21:50.848 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 03:21:50.848 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 03:21:50.870 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 03:21:50.870 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 03:21:50.870 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 03:21:50.870 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.28.22:6700) Recv POWERON CMD
2026-01-29 03:21:50.870 [INFO] ctrl_if_trx.py:109 (MS@172.18.28.22:6700) Starting transceiver...
2026-01-29 03:21:50.914 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:21:50.919 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 03:21:50.920 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 03:21:50.920 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 03:21:50.920 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 03:21:51.252 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-01-29 03:21:51.288 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 03:21:51.289 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:21:51.289 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:21:51.293 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:21:51.638 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 03:21:51.640 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:21:51.647 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 03:21:51.647 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 03:21:51.655 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 03:21:51.656 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:21:51.656 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:21:51.656 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:21:51.659 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 03:21:51.659 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 03:21:51.659 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 03:21:51.660 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 03:21:51.660 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.28.20:5700) Recv POWEROFF cmd
2026-01-29 03:21:51.660 [INFO] ctrl_if_trx.py:117 (BTS@172.18.28.20:5700) Stopping transceiver...
2026-01-29 03:21:51.660 [INFO] transceiver.py:246 Stopping clock generator
2026-01-29 03:21:51.660 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=293 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:21:51.660 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=293 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:21:51.661 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=293 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:21:51.661 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=293 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:21:51.661 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=293 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:21:51.661 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=293 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:21:51.661 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=293 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:21:51.661 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=294 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:21:51.661 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=294 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:21:51.661 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=294 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:21:51.661 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=294 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:21:51.661 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=294 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:21:51.661 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=294 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:21:51.662 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=294 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:21:51.662 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=294 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:21:56.659 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.28.20:5700) Recv POWEROFF cmd
2026-01-29 03:21:56.659 [INFO] ctrl_if_trx.py:117 (BTS@172.18.28.20:5700) Stopping transceiver...
2026-01-29 03:21:56.661 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 03:21:56.662 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 03:21:56.663 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 03:21:56.663 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 03:21:56.671 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 03:21:56.673 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.28.20:5700) Recv SETFORMAT cmd
2026-01-29 03:21:56.673 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.28.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:21:56.673 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.28.20:5700) Recv SETFORMAT cmd
2026-01-29 03:21:56.674 [INFO] ctrl_if_trx.py:201 (BTS@172.18.28.20:5700) TRXD header version 1 -> 1
2026-01-29 03:21:56.677 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.28.20:5700/1) Recv RXTUNE cmd
2026-01-29 03:21:56.677 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.28.20:5700/1) Recv TXTUNE cmd
2026-01-29 03:21:56.678 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.28.20:5700/1) Recv SETFORMAT cmd
2026-01-29 03:21:56.678 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.28.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:21:56.678 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 03:21:56.679 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.28.20:5700/1) Recv NOMTXPOWER cmd
2026-01-29 03:21:56.679 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.28.20:5700/1) Recv SETFORMAT cmd
2026-01-29 03:21:56.679 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.28.20:5700/1) TRXD header version 1 -> 1
2026-01-29 03:21:56.680 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.28.20:5700/2) Recv RXTUNE cmd
2026-01-29 03:21:56.680 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.28.20:5700/2) Recv TXTUNE cmd
2026-01-29 03:21:56.680 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.28.20:5700/2) Recv SETFORMAT cmd
2026-01-29 03:21:56.680 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.28.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:21:56.681 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 03:21:56.681 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.28.20:5700/2) Recv NOMTXPOWER cmd
2026-01-29 03:21:56.681 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.28.20:5700/2) Recv SETFORMAT cmd
2026-01-29 03:21:56.681 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.28.20:5700/2) TRXD header version 1 -> 1
2026-01-29 03:21:56.682 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.28.20:5700/3) Recv RXTUNE cmd
2026-01-29 03:21:56.682 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.28.20:5700/3) Recv TXTUNE cmd
2026-01-29 03:21:56.683 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.28.20:5700/3) Recv SETFORMAT cmd
2026-01-29 03:21:56.683 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.28.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:21:56.683 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 03:21:56.683 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.28.20:5700/3) Recv NOMTXPOWER cmd
2026-01-29 03:21:56.683 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.28.20:5700/3) Recv SETFORMAT cmd
2026-01-29 03:21:56.683 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.28.20:5700/3) TRXD header version 1 -> 1
2026-01-29 03:21:56.685 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.28.20:5700) Recv RXTUNE cmd
2026-01-29 03:21:56.685 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETTSC
2026-01-29 03:21:56.686 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETTSC
2026-01-29 03:21:56.686 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETTSC
2026-01-29 03:21:56.686 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.28.20:5700) Recv TXTUNE cmd
2026-01-29 03:21:56.686 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETRXGAIN
2026-01-29 03:21:56.686 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETRXGAIN
2026-01-29 03:21:56.686 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETRXGAIN
2026-01-29 03:21:56.686 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETTSC
2026-01-29 03:21:56.686 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:21:56.686 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:21:56.686 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:21:56.686 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.28.20:5700) Recv NOMTXPOWER cmd
2026-01-29 03:21:56.686 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:21:56.686 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:21:56.686 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:21:56.686 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.28.20:5700) Recv POWERON CMD
2026-01-29 03:21:56.686 [INFO] ctrl_if_trx.py:109 (BTS@172.18.28.20:5700) Starting transceiver...
2026-01-29 03:21:56.686 [INFO] transceiver.py:243 Starting clock generator
2026-01-29 03:21:56.686 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-01-29 03:21:56.686 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:21:56.686 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:21:56.686 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:21:56.686 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETRXGAIN
2026-01-29 03:21:56.687 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:21:56.687 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:21:56.687 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:21:56.687 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:21:56.687 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:21:56.687 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:21:56.687 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:21:56.687 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:21:56.687 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:21:56.687 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:21:56.687 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:21:56.687 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:21:56.687 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:21:56.687 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:21:56.687 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:21:56.687 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:21:56.687 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:21:56.687 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:21:56.687 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:21:56.687 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:21:56.687 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:21:56.687 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:21:56.687 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:21:56.691 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-01-29 03:21:57.174 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-01-29 03:21:57.220 [DEBUG] fake_trx.py:278 (BTS@172.18.28.20:5700) Recv FAKE_TOA cmd
2026-01-29 03:21:57.222 [DEBUG] fake_trx.py:297 (BTS@172.18.28.20:5700) Recv FAKE_RSSI cmd
2026-01-29 03:21:57.223 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:21:57.224 [DEBUG] fake_trx.py:322 (BTS@172.18.28.20:5700) Recv FAKE_CI cmd
2026-01-29 03:21:57.248 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 03:21:57.248 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 03:21:57.248 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 03:21:57.297 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 03:21:57.297 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 03:21:57.298 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 03:21:57.298 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.28.22:6700) Recv POWERON CMD
2026-01-29 03:21:57.298 [INFO] ctrl_if_trx.py:109 (MS@172.18.28.22:6700) Starting transceiver...
2026-01-29 03:21:57.315 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:21:57.321 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.28.22:6700) Recv SETFH cmd
2026-01-29 03:21:57.321 [INFO] transceiver.py:201 (MS@172.18.28.22:6700) Frequency hopping configured: hsn=5, maio=0, ma_len=4
2026-01-29 03:21:57.321 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 03:21:57.322 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 03:21:57.652 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-01-29 03:21:57.690 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:21:57.690 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 03:21:57.692 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:21:57.696 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:21:58.131 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-01-29 03:21:58.180 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 03:21:58.182 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:21:58.188 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 03:21:58.188 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 03:21:58.188 [INFO] transceiver.py:205 (MS@172.18.28.22:6700) Frequency hopping disabled
2026-01-29 03:21:58.198 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 03:21:58.198 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:21:58.198 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:21:58.198 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:21:58.201 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 03:21:58.201 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 03:21:58.201 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 03:21:58.201 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 03:21:58.201 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.28.20:5700) Recv POWEROFF cmd
2026-01-29 03:21:58.201 [INFO] ctrl_if_trx.py:117 (BTS@172.18.28.20:5700) Stopping transceiver...
2026-01-29 03:21:58.201 [INFO] transceiver.py:246 Stopping clock generator
2026-01-29 03:21:58.202 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=322 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:21:58.202 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=322 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:21:58.202 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=322 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:21:58.202 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=322 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:21:58.202 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=322 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:21:58.202 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=322 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:21:58.202 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=322 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:21:58.202 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=323 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:21:58.202 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=323 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:21:58.202 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=323 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:21:58.202 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=323 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:21:58.202 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=323 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:21:58.202 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=323 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:21:58.202 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=323 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:21:58.202 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=323 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:22:03.201 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.28.20:5700) Recv POWEROFF cmd
2026-01-29 03:22:03.201 [INFO] ctrl_if_trx.py:117 (BTS@172.18.28.20:5700) Stopping transceiver...
2026-01-29 03:22:03.203 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 03:22:03.204 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 03:22:03.205 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 03:22:03.206 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 03:22:03.215 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 03:22:03.217 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.28.20:5700) Recv SETFORMAT cmd
2026-01-29 03:22:03.217 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.28.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:22:03.218 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.28.20:5700) Recv SETFORMAT cmd
2026-01-29 03:22:03.218 [INFO] ctrl_if_trx.py:201 (BTS@172.18.28.20:5700) TRXD header version 1 -> 1
2026-01-29 03:22:03.221 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.28.20:5700/1) Recv RXTUNE cmd
2026-01-29 03:22:03.222 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.28.20:5700/1) Recv TXTUNE cmd
2026-01-29 03:22:03.222 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.28.20:5700/1) Recv SETFORMAT cmd
2026-01-29 03:22:03.222 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.28.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:22:03.222 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 03:22:03.222 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.28.20:5700/1) Recv NOMTXPOWER cmd
2026-01-29 03:22:03.222 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.28.20:5700/1) Recv SETFORMAT cmd
2026-01-29 03:22:03.222 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.28.20:5700/1) TRXD header version 1 -> 1
2026-01-29 03:22:03.225 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.28.20:5700/2) Recv RXTUNE cmd
2026-01-29 03:22:03.225 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.28.20:5700/2) Recv TXTUNE cmd
2026-01-29 03:22:03.225 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.28.20:5700/2) Recv SETFORMAT cmd
2026-01-29 03:22:03.225 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.28.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:22:03.226 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 03:22:03.226 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.28.20:5700/2) Recv NOMTXPOWER cmd
2026-01-29 03:22:03.226 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.28.20:5700/2) Recv SETFORMAT cmd
2026-01-29 03:22:03.226 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.28.20:5700/2) TRXD header version 1 -> 1
2026-01-29 03:22:03.228 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.28.20:5700/3) Recv RXTUNE cmd
2026-01-29 03:22:03.228 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.28.20:5700/3) Recv TXTUNE cmd
2026-01-29 03:22:03.228 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.28.20:5700/3) Recv SETFORMAT cmd
2026-01-29 03:22:03.228 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.28.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:22:03.228 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 03:22:03.229 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.28.20:5700/3) Recv NOMTXPOWER cmd
2026-01-29 03:22:03.229 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.28.20:5700/3) Recv SETFORMAT cmd
2026-01-29 03:22:03.229 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.28.20:5700/3) TRXD header version 1 -> 1
2026-01-29 03:22:03.232 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.28.20:5700) Recv RXTUNE cmd
2026-01-29 03:22:03.232 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETTSC
2026-01-29 03:22:03.232 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETTSC
2026-01-29 03:22:03.232 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETTSC
2026-01-29 03:22:03.232 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.28.20:5700) Recv TXTUNE cmd
2026-01-29 03:22:03.232 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETRXGAIN
2026-01-29 03:22:03.232 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETRXGAIN
2026-01-29 03:22:03.232 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETRXGAIN
2026-01-29 03:22:03.232 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETTSC
2026-01-29 03:22:03.232 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:22:03.232 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:22:03.233 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:22:03.233 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.28.20:5700) Recv NOMTXPOWER cmd
2026-01-29 03:22:03.233 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:22:03.233 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:22:03.233 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:22:03.233 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.28.20:5700) Recv POWERON CMD
2026-01-29 03:22:03.233 [INFO] ctrl_if_trx.py:109 (BTS@172.18.28.20:5700) Starting transceiver...
2026-01-29 03:22:03.233 [INFO] transceiver.py:243 Starting clock generator
2026-01-29 03:22:03.233 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-01-29 03:22:03.233 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:22:03.233 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:22:03.233 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:22:03.233 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETRXGAIN
2026-01-29 03:22:03.233 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:22:03.233 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:22:03.233 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:22:03.233 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:22:03.234 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:22:03.234 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:22:03.234 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:22:03.234 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:22:03.234 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:22:03.234 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:22:03.234 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:22:03.234 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:22:03.234 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:22:03.234 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:22:03.234 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:22:03.234 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:22:03.234 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:22:03.234 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:22:03.234 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:22:03.234 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:22:03.234 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:22:03.234 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:22:03.235 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:22:03.238 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-01-29 03:22:03.721 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-01-29 03:22:03.764 [DEBUG] fake_trx.py:278 (BTS@172.18.28.20:5700) Recv FAKE_TOA cmd
2026-01-29 03:22:03.766 [DEBUG] fake_trx.py:297 (BTS@172.18.28.20:5700) Recv FAKE_RSSI cmd
2026-01-29 03:22:03.768 [DEBUG] fake_trx.py:322 (BTS@172.18.28.20:5700) Recv FAKE_CI cmd
2026-01-29 03:22:03.768 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:22:03.788 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 03:22:03.789 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 03:22:03.789 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 03:22:03.792 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 03:22:03.792 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 03:22:03.792 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 03:22:03.792 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.28.22:6700) Recv POWERON CMD
2026-01-29 03:22:03.792 [INFO] ctrl_if_trx.py:109 (MS@172.18.28.22:6700) Starting transceiver...
2026-01-29 03:22:04.198 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-01-29 03:22:04.236 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 03:22:04.237 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:22:04.240 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:22:04.241 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:22:04.676 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-01-29 03:22:04.831 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:22:04.948 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:22:04.952 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 03:22:04.952 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 03:22:04.967 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 03:22:04.968 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 03:22:04.968 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 03:22:04.969 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 03:22:04.969 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 03:22:04.969 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 03:22:04.969 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.28.22:6700) Recv POWERON CMD
2026-01-29 03:22:04.969 [INFO] ctrl_if_trx.py:109 (MS@172.18.28.22:6700) Starting transceiver...
2026-01-29 03:22:05.154 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-01-29 03:22:05.237 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 03:22:05.238 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:22:05.241 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:22:05.241 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:22:05.632 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-01-29 03:22:06.016 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD NOHANDOVER
2026-01-29 03:22:06.110 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-01-29 03:22:06.146 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD NOHANDOVER
2026-01-29 03:22:06.149 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 03:22:06.150 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 03:22:06.156 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 03:22:06.156 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:22:06.156 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:22:06.156 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:22:06.157 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 03:22:06.157 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 03:22:06.157 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 03:22:06.157 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.28.20:5700) Recv POWEROFF cmd
2026-01-29 03:22:06.157 [INFO] ctrl_if_trx.py:117 (BTS@172.18.28.20:5700) Stopping transceiver...
2026-01-29 03:22:06.157 [INFO] transceiver.py:246 Stopping clock generator
2026-01-29 03:22:06.157 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 03:22:06.157 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=624 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:22:06.157 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=624 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:22:06.157 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=624 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:22:06.157 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=624 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:22:06.157 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=624 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:22:06.157 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=624 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:22:06.157 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=624 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:22:06.157 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=624 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:22:11.159 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.28.20:5700) Recv POWEROFF cmd
2026-01-29 03:22:11.160 [INFO] ctrl_if_trx.py:117 (BTS@172.18.28.20:5700) Stopping transceiver...
2026-01-29 03:22:11.161 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 03:22:11.162 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 03:22:11.162 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 03:22:11.163 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 03:22:11.170 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 03:22:11.172 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.28.20:5700) Recv SETFORMAT cmd
2026-01-29 03:22:11.172 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.28.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:22:11.172 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.28.20:5700) Recv SETFORMAT cmd
2026-01-29 03:22:11.172 [INFO] ctrl_if_trx.py:201 (BTS@172.18.28.20:5700) TRXD header version 1 -> 1
2026-01-29 03:22:11.175 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.28.20:5700/1) Recv RXTUNE cmd
2026-01-29 03:22:11.175 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.28.20:5700/1) Recv TXTUNE cmd
2026-01-29 03:22:11.176 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.28.20:5700/1) Recv SETFORMAT cmd
2026-01-29 03:22:11.176 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.28.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:22:11.176 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 03:22:11.176 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.28.20:5700/1) Recv NOMTXPOWER cmd
2026-01-29 03:22:11.176 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.28.20:5700/1) Recv SETFORMAT cmd
2026-01-29 03:22:11.176 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.28.20:5700/1) TRXD header version 1 -> 1
2026-01-29 03:22:11.178 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.28.20:5700/2) Recv RXTUNE cmd
2026-01-29 03:22:11.178 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.28.20:5700/2) Recv TXTUNE cmd
2026-01-29 03:22:11.179 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.28.20:5700/2) Recv SETFORMAT cmd
2026-01-29 03:22:11.179 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.28.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:22:11.179 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 03:22:11.179 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.28.20:5700/2) Recv NOMTXPOWER cmd
2026-01-29 03:22:11.179 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.28.20:5700/2) Recv SETFORMAT cmd
2026-01-29 03:22:11.179 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.28.20:5700/2) TRXD header version 1 -> 1
2026-01-29 03:22:11.181 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.28.20:5700/3) Recv RXTUNE cmd
2026-01-29 03:22:11.181 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.28.20:5700/3) Recv TXTUNE cmd
2026-01-29 03:22:11.181 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.28.20:5700/3) Recv SETFORMAT cmd
2026-01-29 03:22:11.181 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.28.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:22:11.181 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 03:22:11.181 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.28.20:5700/3) Recv NOMTXPOWER cmd
2026-01-29 03:22:11.181 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.28.20:5700/3) Recv SETFORMAT cmd
2026-01-29 03:22:11.181 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.28.20:5700/3) TRXD header version 1 -> 1
2026-01-29 03:22:11.184 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.28.20:5700) Recv RXTUNE cmd
2026-01-29 03:22:11.184 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETTSC
2026-01-29 03:22:11.184 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETTSC
2026-01-29 03:22:11.184 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETTSC
2026-01-29 03:22:11.184 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.28.20:5700) Recv TXTUNE cmd
2026-01-29 03:22:11.184 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETRXGAIN
2026-01-29 03:22:11.185 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETRXGAIN
2026-01-29 03:22:11.185 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETRXGAIN
2026-01-29 03:22:11.185 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETTSC
2026-01-29 03:22:11.185 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:22:11.185 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:22:11.185 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.28.20:5700) Recv NOMTXPOWER cmd
2026-01-29 03:22:11.185 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:22:11.185 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:22:11.185 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:22:11.185 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.28.20:5700) Recv POWERON CMD
2026-01-29 03:22:11.185 [INFO] ctrl_if_trx.py:109 (BTS@172.18.28.20:5700) Starting transceiver...
2026-01-29 03:22:11.185 [INFO] transceiver.py:243 Starting clock generator
2026-01-29 03:22:11.185 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-01-29 03:22:11.185 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:22:11.185 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:22:11.185 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:22:11.185 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETRXGAIN
2026-01-29 03:22:11.185 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:22:11.185 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:22:11.185 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:22:11.185 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:22:11.186 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:22:11.186 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:22:11.186 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:22:11.186 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:22:11.186 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:22:11.186 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:22:11.186 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:22:11.186 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:22:11.186 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:22:11.186 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:22:11.186 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:22:11.186 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:22:11.186 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:22:11.186 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:22:11.186 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:22:11.186 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:22:11.186 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:22:11.186 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:22:11.186 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:22:11.186 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:22:11.190 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-01-29 03:22:11.673 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-01-29 03:22:11.717 [DEBUG] fake_trx.py:278 (BTS@172.18.28.20:5700) Recv FAKE_TOA cmd
2026-01-29 03:22:11.719 [DEBUG] fake_trx.py:297 (BTS@172.18.28.20:5700) Recv FAKE_RSSI cmd
2026-01-29 03:22:11.720 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:22:11.721 [DEBUG] fake_trx.py:322 (BTS@172.18.28.20:5700) Recv FAKE_CI cmd
2026-01-29 03:22:11.746 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 03:22:11.746 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 03:22:11.747 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 03:22:12.151 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-01-29 03:22:12.188 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 03:22:12.189 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:22:12.189 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:22:12.192 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:22:12.629 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-01-29 03:22:13.108 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-01-29 03:22:13.189 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 03:22:13.189 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:22:13.190 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:22:13.192 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:22:13.589 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-01-29 03:22:14.068 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-01-29 03:22:14.190 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:22:14.190 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 03:22:14.191 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:22:14.193 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:22:14.549 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-01-29 03:22:15.031 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-01-29 03:22:15.191 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 03:22:15.191 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:22:15.192 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:22:15.194 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:22:15.512 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-01-29 03:22:15.993 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-01-29 03:22:16.192 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:22:16.193 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 03:22:16.193 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:22:16.196 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:22:16.474 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-01-29 03:22:16.956 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-01-29 03:22:17.435 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-01-29 03:22:17.757 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 03:22:17.758 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 03:22:17.758 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 03:22:17.759 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.28.22:6700) Recv POWERON CMD
2026-01-29 03:22:17.759 [INFO] ctrl_if_trx.py:109 (MS@172.18.28.22:6700) Starting transceiver...
2026-01-29 03:22:17.916 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-01-29 03:22:17.937 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD NOHANDOVER
2026-01-29 03:22:17.941 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 03:22:17.941 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 03:22:17.941 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 03:22:17.942 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 03:22:18.394 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-01-29 03:22:18.873 [DEBUG] clck_gen.py:113 IND CLOCK 1632
2026-01-29 03:22:19.352 [DEBUG] clck_gen.py:113 IND CLOCK 1734
2026-01-29 03:22:19.830 [DEBUG] clck_gen.py:113 IND CLOCK 1836
2026-01-29 03:22:20.309 [DEBUG] clck_gen.py:113 IND CLOCK 1938
2026-01-29 03:22:20.785 [DEBUG] clck_gen.py:113 IND CLOCK 2040
2026-01-29 03:22:20.905 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 03:22:20.905 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 03:22:20.909 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 03:22:20.909 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:22:20.909 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:22:20.910 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:22:20.910 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 03:22:20.910 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 03:22:20.911 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 03:22:20.911 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 03:22:20.911 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.28.20:5700) Recv POWEROFF cmd
2026-01-29 03:22:20.911 [INFO] ctrl_if_trx.py:117 (BTS@172.18.28.20:5700) Stopping transceiver...
2026-01-29 03:22:20.911 [INFO] transceiver.py:246 Stopping clock generator
2026-01-29 03:22:20.911 [WARNING] transceiver.py:257 (TRX3@172.18.28.20:5700/3) RX TRXD message (ver=1 fn=2069 tn=0 bl=148 pwr=8), but transceiver is not running => dropping...
2026-01-29 03:22:20.911 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=2069 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:22:20.911 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=2069 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:22:20.911 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=2069 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:22:20.911 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=2069 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:22:20.911 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=2069 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:22:20.911 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=2069 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:22:25.911 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.28.20:5700) Recv POWEROFF cmd
2026-01-29 03:22:25.911 [INFO] ctrl_if_trx.py:117 (BTS@172.18.28.20:5700) Stopping transceiver...
2026-01-29 03:22:25.912 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 03:22:25.913 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 03:22:25.914 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 03:22:25.914 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 03:22:25.923 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 03:22:25.925 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.28.20:5700) Recv SETFORMAT cmd
2026-01-29 03:22:25.925 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.28.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:22:25.925 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.28.20:5700) Recv SETFORMAT cmd
2026-01-29 03:22:25.925 [INFO] ctrl_if_trx.py:201 (BTS@172.18.28.20:5700) TRXD header version 1 -> 1
2026-01-29 03:22:25.930 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.28.20:5700/1) Recv RXTUNE cmd
2026-01-29 03:22:25.930 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.28.20:5700/1) Recv TXTUNE cmd
2026-01-29 03:22:25.930 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.28.20:5700/1) Recv SETFORMAT cmd
2026-01-29 03:22:25.930 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.28.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:22:25.931 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 03:22:25.931 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.28.20:5700/1) Recv NOMTXPOWER cmd
2026-01-29 03:22:25.932 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.28.20:5700/1) Recv SETFORMAT cmd
2026-01-29 03:22:25.932 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.28.20:5700/1) TRXD header version 1 -> 1
2026-01-29 03:22:25.933 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.28.20:5700/2) Recv RXTUNE cmd
2026-01-29 03:22:25.933 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.28.20:5700/2) Recv TXTUNE cmd
2026-01-29 03:22:25.933 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.28.20:5700/2) Recv SETFORMAT cmd
2026-01-29 03:22:25.933 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.28.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:22:25.933 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 03:22:25.933 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.28.20:5700/2) Recv NOMTXPOWER cmd
2026-01-29 03:22:25.933 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.28.20:5700/2) Recv SETFORMAT cmd
2026-01-29 03:22:25.933 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.28.20:5700/2) TRXD header version 1 -> 1
2026-01-29 03:22:25.935 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.28.20:5700/3) Recv RXTUNE cmd
2026-01-29 03:22:25.935 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.28.20:5700/3) Recv TXTUNE cmd
2026-01-29 03:22:25.935 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.28.20:5700/3) Recv SETFORMAT cmd
2026-01-29 03:22:25.935 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.28.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:22:25.935 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 03:22:25.935 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.28.20:5700/3) Recv NOMTXPOWER cmd
2026-01-29 03:22:25.935 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.28.20:5700/3) Recv SETFORMAT cmd
2026-01-29 03:22:25.935 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.28.20:5700/3) TRXD header version 1 -> 1
2026-01-29 03:22:25.938 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.28.20:5700) Recv RXTUNE cmd
2026-01-29 03:22:25.938 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETTSC
2026-01-29 03:22:25.938 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETTSC
2026-01-29 03:22:25.938 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETTSC
2026-01-29 03:22:25.938 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.28.20:5700) Recv TXTUNE cmd
2026-01-29 03:22:25.938 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETRXGAIN
2026-01-29 03:22:25.938 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETRXGAIN
2026-01-29 03:22:25.938 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETRXGAIN
2026-01-29 03:22:25.938 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETTSC
2026-01-29 03:22:25.938 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:22:25.938 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:22:25.938 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:22:25.939 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.28.20:5700) Recv NOMTXPOWER cmd
2026-01-29 03:22:25.939 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:22:25.939 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:22:25.939 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:22:25.939 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.28.20:5700) Recv POWERON CMD
2026-01-29 03:22:25.939 [INFO] ctrl_if_trx.py:109 (BTS@172.18.28.20:5700) Starting transceiver...
2026-01-29 03:22:25.939 [INFO] transceiver.py:243 Starting clock generator
2026-01-29 03:22:25.939 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-01-29 03:22:25.939 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:22:25.939 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:22:25.939 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:22:25.939 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETRXGAIN
2026-01-29 03:22:25.939 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:22:25.939 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:22:25.939 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:22:25.939 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:22:25.939 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:22:25.939 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:22:25.939 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:22:25.939 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:22:25.939 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:22:25.939 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:22:25.940 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:22:25.940 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:22:25.940 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:22:25.940 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:22:25.940 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:22:25.940 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:22:25.940 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:22:25.940 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:22:25.940 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:22:25.940 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:22:25.940 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:22:25.940 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:22:25.940 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:22:25.944 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-01-29 03:22:26.428 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-01-29 03:22:26.473 [DEBUG] fake_trx.py:278 (BTS@172.18.28.20:5700) Recv FAKE_TOA cmd
2026-01-29 03:22:26.475 [DEBUG] fake_trx.py:297 (BTS@172.18.28.20:5700) Recv FAKE_RSSI cmd
2026-01-29 03:22:26.477 [DEBUG] fake_trx.py:322 (BTS@172.18.28.20:5700) Recv FAKE_CI cmd
2026-01-29 03:22:26.478 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:22:26.501 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 03:22:26.501 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 03:22:26.501 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 03:22:26.907 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-01-29 03:22:26.942 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 03:22:26.942 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:22:26.943 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:22:26.947 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:22:27.388 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-01-29 03:22:27.867 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-01-29 03:22:27.943 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 03:22:27.943 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:22:27.945 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:22:27.948 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:22:28.343 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-01-29 03:22:28.823 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-01-29 03:22:28.944 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 03:22:28.944 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:22:28.946 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:22:28.949 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:22:29.302 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-01-29 03:22:29.783 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-01-29 03:22:29.945 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 03:22:29.945 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:22:29.947 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:22:29.950 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:22:30.264 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-01-29 03:22:30.745 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-01-29 03:22:30.946 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:22:30.946 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 03:22:30.948 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:22:30.951 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:22:31.226 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-01-29 03:22:31.707 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-01-29 03:22:32.188 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-01-29 03:22:32.512 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 03:22:32.513 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 03:22:32.513 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 03:22:32.514 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.28.22:6700) Recv POWERON CMD
2026-01-29 03:22:32.514 [INFO] ctrl_if_trx.py:109 (MS@172.18.28.22:6700) Starting transceiver...
2026-01-29 03:22:32.668 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-01-29 03:22:32.692 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD NOHANDOVER
2026-01-29 03:22:32.698 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 03:22:32.698 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 03:22:32.698 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 03:22:32.699 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 03:22:33.147 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-01-29 03:22:33.625 [DEBUG] clck_gen.py:113 IND CLOCK 1632
2026-01-29 03:22:34.105 [DEBUG] clck_gen.py:113 IND CLOCK 1734
2026-01-29 03:22:34.584 [DEBUG] clck_gen.py:113 IND CLOCK 1836
2026-01-29 03:22:35.062 [DEBUG] clck_gen.py:113 IND CLOCK 1938
2026-01-29 03:22:35.541 [DEBUG] clck_gen.py:113 IND CLOCK 2040
2026-01-29 03:22:35.662 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 03:22:35.662 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 03:22:35.665 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 03:22:35.666 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:22:35.666 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:22:35.666 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:22:35.667 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 03:22:35.667 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 03:22:35.667 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 03:22:35.667 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 03:22:35.667 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.28.20:5700) Recv POWEROFF cmd
2026-01-29 03:22:35.667 [INFO] ctrl_if_trx.py:117 (BTS@172.18.28.20:5700) Stopping transceiver...
2026-01-29 03:22:35.667 [INFO] transceiver.py:246 Stopping clock generator
2026-01-29 03:22:35.667 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=2069 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:22:35.668 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=2069 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:22:35.668 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=2069 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:22:35.668 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=2069 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:22:35.668 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=2069 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:22:35.668 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=2069 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:22:40.669 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.28.20:5700) Recv POWEROFF cmd
2026-01-29 03:22:40.669 [INFO] ctrl_if_trx.py:117 (BTS@172.18.28.20:5700) Stopping transceiver...
2026-01-29 03:22:40.670 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 03:22:40.672 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 03:22:40.673 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 03:22:40.673 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 03:22:40.677 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 03:22:40.678 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.28.20:5700) Recv SETFORMAT cmd
2026-01-29 03:22:40.678 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.28.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:22:40.678 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.28.20:5700) Recv SETFORMAT cmd
2026-01-29 03:22:40.678 [INFO] ctrl_if_trx.py:201 (BTS@172.18.28.20:5700) TRXD header version 1 -> 1
2026-01-29 03:22:40.681 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.28.20:5700/1) Recv RXTUNE cmd
2026-01-29 03:22:40.681 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.28.20:5700/1) Recv TXTUNE cmd
2026-01-29 03:22:40.682 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.28.20:5700/1) Recv SETFORMAT cmd
2026-01-29 03:22:40.682 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.28.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:22:40.682 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 03:22:40.682 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.28.20:5700/1) Recv NOMTXPOWER cmd
2026-01-29 03:22:40.682 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.28.20:5700/1) Recv SETFORMAT cmd
2026-01-29 03:22:40.682 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.28.20:5700/1) TRXD header version 1 -> 1
2026-01-29 03:22:40.684 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.28.20:5700/2) Recv RXTUNE cmd
2026-01-29 03:22:40.684 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.28.20:5700/2) Recv TXTUNE cmd
2026-01-29 03:22:40.685 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.28.20:5700/2) Recv SETFORMAT cmd
2026-01-29 03:22:40.685 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.28.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:22:40.685 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 03:22:40.685 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.28.20:5700/2) Recv NOMTXPOWER cmd
2026-01-29 03:22:40.685 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.28.20:5700/2) Recv SETFORMAT cmd
2026-01-29 03:22:40.685 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.28.20:5700/2) TRXD header version 1 -> 1
2026-01-29 03:22:40.687 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.28.20:5700/3) Recv RXTUNE cmd
2026-01-29 03:22:40.687 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.28.20:5700/3) Recv TXTUNE cmd
2026-01-29 03:22:40.687 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.28.20:5700/3) Recv SETFORMAT cmd
2026-01-29 03:22:40.687 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.28.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:22:40.687 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 03:22:40.687 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.28.20:5700/3) Recv NOMTXPOWER cmd
2026-01-29 03:22:40.687 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.28.20:5700/3) Recv SETFORMAT cmd
2026-01-29 03:22:40.687 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.28.20:5700/3) TRXD header version 1 -> 1
2026-01-29 03:22:40.690 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.28.20:5700) Recv RXTUNE cmd
2026-01-29 03:22:40.690 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETTSC
2026-01-29 03:22:40.690 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETTSC
2026-01-29 03:22:40.690 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETTSC
2026-01-29 03:22:40.690 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.28.20:5700) Recv TXTUNE cmd
2026-01-29 03:22:40.690 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETRXGAIN
2026-01-29 03:22:40.690 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETRXGAIN
2026-01-29 03:22:40.690 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETRXGAIN
2026-01-29 03:22:40.690 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETTSC
2026-01-29 03:22:40.690 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:22:40.691 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:22:40.691 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:22:40.691 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.28.20:5700) Recv NOMTXPOWER cmd
2026-01-29 03:22:40.691 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:22:40.691 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:22:40.691 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:22:40.691 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.28.20:5700) Recv POWERON CMD
2026-01-29 03:22:40.691 [INFO] ctrl_if_trx.py:109 (BTS@172.18.28.20:5700) Starting transceiver...
2026-01-29 03:22:40.691 [INFO] transceiver.py:243 Starting clock generator
2026-01-29 03:22:40.691 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-01-29 03:22:40.691 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:22:40.691 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:22:40.691 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:22:40.691 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETRXGAIN
2026-01-29 03:22:40.691 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:22:40.691 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:22:40.691 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:22:40.691 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:22:40.691 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:22:40.691 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:22:40.691 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:22:40.691 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:22:40.691 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:22:40.692 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:22:40.692 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:22:40.692 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:22:40.692 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:22:40.692 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:22:40.692 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:22:40.692 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:22:40.692 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:22:40.692 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:22:40.692 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:22:40.692 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:22:40.692 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:22:40.692 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:22:40.692 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:22:40.696 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-01-29 03:22:41.180 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-01-29 03:22:41.220 [DEBUG] fake_trx.py:278 (BTS@172.18.28.20:5700) Recv FAKE_TOA cmd
2026-01-29 03:22:41.222 [DEBUG] fake_trx.py:297 (BTS@172.18.28.20:5700) Recv FAKE_RSSI cmd
2026-01-29 03:22:41.223 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:22:41.225 [DEBUG] fake_trx.py:322 (BTS@172.18.28.20:5700) Recv FAKE_CI cmd
2026-01-29 03:22:41.251 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 03:22:41.251 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 03:22:41.252 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 03:22:41.658 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-01-29 03:22:41.694 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 03:22:41.694 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:22:41.695 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:22:41.698 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:22:42.129 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-01-29 03:22:42.604 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-01-29 03:22:42.696 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:22:42.696 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 03:22:42.696 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:22:42.699 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:22:43.078 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-01-29 03:22:43.547 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-01-29 03:22:43.697 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:22:43.697 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 03:22:43.698 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:22:43.700 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:22:44.017 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-01-29 03:22:44.495 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-01-29 03:22:44.698 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:22:44.698 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 03:22:44.698 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:22:44.701 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:22:44.973 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-01-29 03:22:45.451 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-01-29 03:22:45.699 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:22:45.699 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 03:22:45.700 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:22:45.703 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:22:45.930 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-01-29 03:22:46.408 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-01-29 03:22:46.886 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-01-29 03:22:47.263 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 03:22:47.263 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 03:22:47.264 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 03:22:47.264 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.28.22:6700) Recv POWERON CMD
2026-01-29 03:22:47.265 [INFO] ctrl_if_trx.py:109 (MS@172.18.28.22:6700) Starting transceiver...
2026-01-29 03:22:47.364 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-01-29 03:22:47.385 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD NOHANDOVER
2026-01-29 03:22:47.390 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 03:22:47.390 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 03:22:47.391 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 03:22:47.392 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 03:22:47.842 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-01-29 03:22:48.320 [DEBUG] clck_gen.py:113 IND CLOCK 1632
2026-01-29 03:22:48.798 [DEBUG] clck_gen.py:113 IND CLOCK 1734
2026-01-29 03:22:49.277 [DEBUG] clck_gen.py:113 IND CLOCK 1836
2026-01-29 03:22:49.755 [DEBUG] clck_gen.py:113 IND CLOCK 1938
2026-01-29 03:22:50.234 [DEBUG] clck_gen.py:113 IND CLOCK 2040
2026-01-29 03:22:50.354 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 03:22:50.354 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 03:22:50.356 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 03:22:50.356 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:22:50.356 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:22:50.356 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:22:50.357 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 03:22:50.357 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 03:22:50.357 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 03:22:50.357 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.28.20:5700) Recv POWEROFF cmd
2026-01-29 03:22:50.357 [INFO] ctrl_if_trx.py:117 (BTS@172.18.28.20:5700) Stopping transceiver...
2026-01-29 03:22:50.357 [INFO] transceiver.py:246 Stopping clock generator
2026-01-29 03:22:50.357 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 03:22:50.357 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=2068 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:22:50.357 [WARNING] transceiver.py:257 (TRX2@172.18.28.20:5700/2) RX TRXD message (ver=1 fn=2068 tn=0 bl=148 pwr=4), but transceiver is not running => dropping...
2026-01-29 03:22:50.357 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=2068 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:22:50.357 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=2068 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:22:50.357 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=2068 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:22:50.357 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=2068 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:22:50.357 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=2068 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:22:50.357 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=2068 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:22:50.357 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=2068 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:22:55.360 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.28.20:5700) Recv POWEROFF cmd
2026-01-29 03:22:55.360 [INFO] ctrl_if_trx.py:117 (BTS@172.18.28.20:5700) Stopping transceiver...
2026-01-29 03:22:55.362 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 03:22:55.363 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 03:22:55.364 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 03:22:55.364 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 03:22:55.373 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 03:22:55.375 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.28.20:5700) Recv SETFORMAT cmd
2026-01-29 03:22:55.375 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.28.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:22:55.375 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.28.20:5700) Recv SETFORMAT cmd
2026-01-29 03:22:55.375 [INFO] ctrl_if_trx.py:201 (BTS@172.18.28.20:5700) TRXD header version 1 -> 1
2026-01-29 03:22:55.378 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.28.20:5700/1) Recv RXTUNE cmd
2026-01-29 03:22:55.379 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.28.20:5700/1) Recv TXTUNE cmd
2026-01-29 03:22:55.379 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.28.20:5700/1) Recv SETFORMAT cmd
2026-01-29 03:22:55.379 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.28.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:22:55.380 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 03:22:55.380 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.28.20:5700/1) Recv NOMTXPOWER cmd
2026-01-29 03:22:55.380 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.28.20:5700/1) Recv SETFORMAT cmd
2026-01-29 03:22:55.380 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.28.20:5700/1) TRXD header version 1 -> 1
2026-01-29 03:22:55.382 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.28.20:5700/2) Recv RXTUNE cmd
2026-01-29 03:22:55.382 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.28.20:5700/2) Recv TXTUNE cmd
2026-01-29 03:22:55.382 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.28.20:5700/2) Recv SETFORMAT cmd
2026-01-29 03:22:55.382 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.28.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:22:55.383 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 03:22:55.383 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.28.20:5700/2) Recv NOMTXPOWER cmd
2026-01-29 03:22:55.383 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.28.20:5700/2) Recv SETFORMAT cmd
2026-01-29 03:22:55.383 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.28.20:5700/2) TRXD header version 1 -> 1
2026-01-29 03:22:55.385 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.28.20:5700/3) Recv RXTUNE cmd
2026-01-29 03:22:55.385 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.28.20:5700/3) Recv TXTUNE cmd
2026-01-29 03:22:55.385 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.28.20:5700/3) Recv SETFORMAT cmd
2026-01-29 03:22:55.385 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.28.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:22:55.385 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 03:22:55.385 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.28.20:5700/3) Recv NOMTXPOWER cmd
2026-01-29 03:22:55.385 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.28.20:5700/3) Recv SETFORMAT cmd
2026-01-29 03:22:55.385 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.28.20:5700/3) TRXD header version 1 -> 1
2026-01-29 03:22:55.387 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.28.20:5700) Recv RXTUNE cmd
2026-01-29 03:22:55.388 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETTSC
2026-01-29 03:22:55.388 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETTSC
2026-01-29 03:22:55.388 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETTSC
2026-01-29 03:22:55.388 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.28.20:5700) Recv TXTUNE cmd
2026-01-29 03:22:55.388 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETRXGAIN
2026-01-29 03:22:55.388 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETRXGAIN
2026-01-29 03:22:55.388 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETRXGAIN
2026-01-29 03:22:55.388 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETTSC
2026-01-29 03:22:55.388 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:22:55.388 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:22:55.388 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.28.20:5700) Recv NOMTXPOWER cmd
2026-01-29 03:22:55.388 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:22:55.388 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:22:55.388 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:22:55.388 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.28.20:5700) Recv POWERON CMD
2026-01-29 03:22:55.388 [INFO] ctrl_if_trx.py:109 (BTS@172.18.28.20:5700) Starting transceiver...
2026-01-29 03:22:55.388 [INFO] transceiver.py:243 Starting clock generator
2026-01-29 03:22:55.388 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-01-29 03:22:55.388 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:22:55.388 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:22:55.388 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:22:55.388 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETRXGAIN
2026-01-29 03:22:55.388 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:22:55.388 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:22:55.388 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:22:55.388 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:22:55.388 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:22:55.388 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:22:55.388 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:22:55.388 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:22:55.388 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:22:55.388 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:22:55.388 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:22:55.388 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:22:55.389 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:22:55.389 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:22:55.389 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:22:55.389 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:22:55.389 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:22:55.389 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:22:55.389 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:22:55.389 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:22:55.389 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:22:55.389 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:22:55.389 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:22:55.389 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:22:55.393 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-01-29 03:22:55.875 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-01-29 03:22:55.914 [DEBUG] fake_trx.py:278 (BTS@172.18.28.20:5700) Recv FAKE_TOA cmd
2026-01-29 03:22:55.916 [DEBUG] fake_trx.py:297 (BTS@172.18.28.20:5700) Recv FAKE_RSSI cmd
2026-01-29 03:22:55.919 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:22:55.919 [DEBUG] fake_trx.py:322 (BTS@172.18.28.20:5700) Recv FAKE_CI cmd
2026-01-29 03:22:55.945 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 03:22:55.945 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 03:22:55.945 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 03:22:56.355 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-01-29 03:22:56.390 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 03:22:56.391 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:22:56.391 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:22:56.392 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:22:56.836 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-01-29 03:22:57.315 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-01-29 03:22:57.392 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:22:57.393 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 03:22:57.393 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:22:57.393 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:22:57.793 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-01-29 03:22:58.271 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-01-29 03:22:58.393 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 03:22:58.394 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:22:58.394 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:22:58.394 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:22:58.752 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-01-29 03:22:59.234 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-01-29 03:22:59.394 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 03:22:59.395 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:22:59.395 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:22:59.395 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:22:59.715 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-01-29 03:23:00.197 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-01-29 03:23:00.396 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:23:00.396 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:23:00.396 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 03:23:00.397 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:23:00.678 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-01-29 03:23:01.160 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-01-29 03:23:01.639 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-01-29 03:23:01.956 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 03:23:01.956 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 03:23:01.957 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 03:23:01.958 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.28.22:6700) Recv POWERON CMD
2026-01-29 03:23:01.958 [INFO] ctrl_if_trx.py:109 (MS@172.18.28.22:6700) Starting transceiver...
2026-01-29 03:23:02.117 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-01-29 03:23:02.139 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD NOHANDOVER
2026-01-29 03:23:02.145 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 03:23:02.145 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 03:23:02.145 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 03:23:02.145 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 03:23:02.596 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-01-29 03:23:03.074 [DEBUG] clck_gen.py:113 IND CLOCK 1632
2026-01-29 03:23:03.555 [DEBUG] clck_gen.py:113 IND CLOCK 1734
2026-01-29 03:23:04.036 [DEBUG] clck_gen.py:113 IND CLOCK 1836
2026-01-29 03:23:04.515 [DEBUG] clck_gen.py:113 IND CLOCK 1938
2026-01-29 03:23:04.994 [DEBUG] clck_gen.py:113 IND CLOCK 2040
2026-01-29 03:23:05.112 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 03:23:05.113 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 03:23:05.113 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 03:23:05.113 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:23:05.113 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:23:05.113 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:23:05.113 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 03:23:05.113 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 03:23:05.113 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 03:23:05.113 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 03:23:05.113 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.28.20:5700) Recv POWEROFF cmd
2026-01-29 03:23:05.113 [INFO] ctrl_if_trx.py:117 (BTS@172.18.28.20:5700) Stopping transceiver...
2026-01-29 03:23:05.113 [INFO] transceiver.py:246 Stopping clock generator
2026-01-29 03:23:10.119 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.28.20:5700) Recv POWEROFF cmd
2026-01-29 03:23:10.119 [INFO] ctrl_if_trx.py:117 (BTS@172.18.28.20:5700) Stopping transceiver...
2026-01-29 03:23:10.119 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 03:23:10.119 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 03:23:10.119 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 03:23:10.119 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 03:23:10.126 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 03:23:10.128 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.28.20:5700) Recv SETFORMAT cmd
2026-01-29 03:23:10.128 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.28.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:23:10.129 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.28.20:5700) Recv SETFORMAT cmd
2026-01-29 03:23:10.129 [INFO] ctrl_if_trx.py:201 (BTS@172.18.28.20:5700) TRXD header version 1 -> 1
2026-01-29 03:23:10.133 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.28.20:5700/1) Recv RXTUNE cmd
2026-01-29 03:23:10.133 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.28.20:5700/1) Recv TXTUNE cmd
2026-01-29 03:23:10.134 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.28.20:5700/1) Recv SETFORMAT cmd
2026-01-29 03:23:10.134 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.28.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:23:10.134 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 03:23:10.135 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.28.20:5700/1) Recv NOMTXPOWER cmd
2026-01-29 03:23:10.135 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.28.20:5700/1) Recv SETFORMAT cmd
2026-01-29 03:23:10.136 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.28.20:5700/1) TRXD header version 1 -> 1
2026-01-29 03:23:10.137 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.28.20:5700/2) Recv RXTUNE cmd
2026-01-29 03:23:10.137 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.28.20:5700/2) Recv TXTUNE cmd
2026-01-29 03:23:10.138 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.28.20:5700/2) Recv SETFORMAT cmd
2026-01-29 03:23:10.138 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.28.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:23:10.138 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 03:23:10.138 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.28.20:5700/2) Recv NOMTXPOWER cmd
2026-01-29 03:23:10.138 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.28.20:5700/2) Recv SETFORMAT cmd
2026-01-29 03:23:10.138 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.28.20:5700/2) TRXD header version 1 -> 1
2026-01-29 03:23:10.140 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.28.20:5700/3) Recv RXTUNE cmd
2026-01-29 03:23:10.140 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.28.20:5700/3) Recv TXTUNE cmd
2026-01-29 03:23:10.140 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.28.20:5700/3) Recv SETFORMAT cmd
2026-01-29 03:23:10.140 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.28.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:23:10.141 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 03:23:10.141 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.28.20:5700/3) Recv NOMTXPOWER cmd
2026-01-29 03:23:10.141 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.28.20:5700/3) Recv SETFORMAT cmd
2026-01-29 03:23:10.141 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.28.20:5700/3) TRXD header version 1 -> 1
2026-01-29 03:23:10.144 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.28.20:5700) Recv RXTUNE cmd
2026-01-29 03:23:10.144 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETTSC
2026-01-29 03:23:10.144 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETTSC
2026-01-29 03:23:10.144 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETTSC
2026-01-29 03:23:10.144 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.28.20:5700) Recv TXTUNE cmd
2026-01-29 03:23:10.144 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETRXGAIN
2026-01-29 03:23:10.144 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETRXGAIN
2026-01-29 03:23:10.144 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETRXGAIN
2026-01-29 03:23:10.144 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETTSC
2026-01-29 03:23:10.144 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:23:10.144 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:23:10.144 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:23:10.144 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.28.20:5700) Recv NOMTXPOWER cmd
2026-01-29 03:23:10.144 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:23:10.144 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:23:10.144 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:23:10.144 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.28.20:5700) Recv POWERON CMD
2026-01-29 03:23:10.144 [INFO] ctrl_if_trx.py:109 (BTS@172.18.28.20:5700) Starting transceiver...
2026-01-29 03:23:10.144 [INFO] transceiver.py:243 Starting clock generator
2026-01-29 03:23:10.145 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-01-29 03:23:10.145 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:23:10.145 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:23:10.145 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:23:10.145 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETRXGAIN
2026-01-29 03:23:10.145 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:23:10.145 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:23:10.145 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:23:10.145 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:23:10.145 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:23:10.145 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:23:10.145 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:23:10.145 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:23:10.145 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:23:10.145 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:23:10.145 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:23:10.145 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:23:10.145 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:23:10.145 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:23:10.146 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:23:10.146 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:23:10.146 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:23:10.146 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:23:10.146 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:23:10.146 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:23:10.146 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:23:10.146 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:23:10.146 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:23:10.149 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-01-29 03:23:10.633 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-01-29 03:23:10.669 [DEBUG] fake_trx.py:278 (BTS@172.18.28.20:5700) Recv FAKE_TOA cmd
2026-01-29 03:23:10.670 [DEBUG] fake_trx.py:297 (BTS@172.18.28.20:5700) Recv FAKE_RSSI cmd
2026-01-29 03:23:10.671 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:23:10.671 [DEBUG] fake_trx.py:322 (BTS@172.18.28.20:5700) Recv FAKE_CI cmd
2026-01-29 03:23:10.689 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 03:23:10.689 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 03:23:10.690 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 03:23:11.113 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-01-29 03:23:11.148 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:23:11.149 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 03:23:11.149 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:23:11.153 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:23:11.594 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-01-29 03:23:12.075 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-01-29 03:23:12.149 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 03:23:12.150 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:23:12.150 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:23:12.154 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:23:12.553 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-01-29 03:23:13.031 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-01-29 03:23:13.150 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 03:23:13.151 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:23:13.151 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:23:13.155 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:23:13.509 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-01-29 03:23:13.988 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-01-29 03:23:14.152 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:23:14.152 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 03:23:14.152 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:23:14.157 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:23:14.469 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-01-29 03:23:14.950 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-01-29 03:23:15.153 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:23:15.153 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 03:23:15.153 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:23:15.158 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:23:15.431 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-01-29 03:23:15.912 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-01-29 03:23:16.391 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-01-29 03:23:16.701 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 03:23:16.701 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 03:23:16.702 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 03:23:16.703 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.28.22:6700) Recv POWERON CMD
2026-01-29 03:23:16.703 [INFO] ctrl_if_trx.py:109 (MS@172.18.28.22:6700) Starting transceiver...
2026-01-29 03:23:16.869 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-01-29 03:23:16.890 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD NOHANDOVER
2026-01-29 03:23:16.895 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 03:23:16.895 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 03:23:16.896 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 03:23:16.896 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 03:23:17.350 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-01-29 03:23:17.831 [DEBUG] clck_gen.py:113 IND CLOCK 1632
2026-01-29 03:23:18.309 [DEBUG] clck_gen.py:113 IND CLOCK 1734
2026-01-29 03:23:18.788 [DEBUG] clck_gen.py:113 IND CLOCK 1836
2026-01-29 03:23:19.266 [DEBUG] clck_gen.py:113 IND CLOCK 1938
2026-01-29 03:23:19.745 [DEBUG] clck_gen.py:113 IND CLOCK 2040
2026-01-29 03:23:19.859 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 03:23:19.859 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 03:23:19.863 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 03:23:19.863 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:23:19.864 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:23:19.864 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:23:19.867 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 03:23:19.867 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 03:23:19.867 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 03:23:19.867 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.28.20:5700) Recv POWEROFF cmd
2026-01-29 03:23:19.867 [INFO] ctrl_if_trx.py:117 (BTS@172.18.28.20:5700) Stopping transceiver...
2026-01-29 03:23:19.868 [INFO] transceiver.py:246 Stopping clock generator
2026-01-29 03:23:19.868 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 03:23:19.868 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=2068 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:23:19.868 [WARNING] transceiver.py:257 (TRX2@172.18.28.20:5700/2) RX TRXD message (ver=1 fn=2068 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:23:19.868 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=2068 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:23:19.868 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=2068 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:23:19.869 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=2068 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:23:19.869 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=2068 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:23:19.869 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=2068 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:23:19.869 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=2068 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:23:19.869 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=2068 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:23:24.866 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.28.20:5700) Recv POWEROFF cmd
2026-01-29 03:23:24.866 [INFO] ctrl_if_trx.py:117 (BTS@172.18.28.20:5700) Stopping transceiver...
2026-01-29 03:23:24.870 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 03:23:24.870 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 03:23:24.870 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 03:23:24.870 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 03:23:24.878 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 03:23:24.880 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.28.20:5700) Recv SETFORMAT cmd
2026-01-29 03:23:24.880 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.28.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:23:24.880 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.28.20:5700) Recv SETFORMAT cmd
2026-01-29 03:23:24.880 [INFO] ctrl_if_trx.py:201 (BTS@172.18.28.20:5700) TRXD header version 1 -> 1
2026-01-29 03:23:24.885 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.28.20:5700/1) Recv RXTUNE cmd
2026-01-29 03:23:24.885 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.28.20:5700/1) Recv TXTUNE cmd
2026-01-29 03:23:24.885 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.28.20:5700/1) Recv SETFORMAT cmd
2026-01-29 03:23:24.885 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.28.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:23:24.885 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 03:23:24.885 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.28.20:5700/1) Recv NOMTXPOWER cmd
2026-01-29 03:23:24.886 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.28.20:5700/1) Recv SETFORMAT cmd
2026-01-29 03:23:24.886 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.28.20:5700/1) TRXD header version 1 -> 1
2026-01-29 03:23:24.889 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.28.20:5700/2) Recv RXTUNE cmd
2026-01-29 03:23:24.889 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.28.20:5700/2) Recv TXTUNE cmd
2026-01-29 03:23:24.889 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.28.20:5700/2) Recv SETFORMAT cmd
2026-01-29 03:23:24.889 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.28.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:23:24.890 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 03:23:24.890 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.28.20:5700/2) Recv NOMTXPOWER cmd
2026-01-29 03:23:24.890 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.28.20:5700/2) Recv SETFORMAT cmd
2026-01-29 03:23:24.890 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.28.20:5700/2) TRXD header version 1 -> 1
2026-01-29 03:23:24.892 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.28.20:5700/3) Recv RXTUNE cmd
2026-01-29 03:23:24.892 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.28.20:5700/3) Recv TXTUNE cmd
2026-01-29 03:23:24.893 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.28.20:5700/3) Recv SETFORMAT cmd
2026-01-29 03:23:24.893 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.28.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:23:24.893 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 03:23:24.893 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.28.20:5700/3) Recv NOMTXPOWER cmd
2026-01-29 03:23:24.893 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.28.20:5700/3) Recv SETFORMAT cmd
2026-01-29 03:23:24.893 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.28.20:5700/3) TRXD header version 1 -> 1
2026-01-29 03:23:24.896 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.28.20:5700) Recv RXTUNE cmd
2026-01-29 03:23:24.896 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETTSC
2026-01-29 03:23:24.896 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETTSC
2026-01-29 03:23:24.896 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETTSC
2026-01-29 03:23:24.896 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.28.20:5700) Recv TXTUNE cmd
2026-01-29 03:23:24.896 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETRXGAIN
2026-01-29 03:23:24.897 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETRXGAIN
2026-01-29 03:23:24.897 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETRXGAIN
2026-01-29 03:23:24.897 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETTSC
2026-01-29 03:23:24.897 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:23:24.897 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:23:24.897 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:23:24.897 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.28.20:5700) Recv NOMTXPOWER cmd
2026-01-29 03:23:24.897 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:23:24.897 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:23:24.897 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:23:24.897 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.28.20:5700) Recv POWERON CMD
2026-01-29 03:23:24.897 [INFO] ctrl_if_trx.py:109 (BTS@172.18.28.20:5700) Starting transceiver...
2026-01-29 03:23:24.897 [INFO] transceiver.py:243 Starting clock generator
2026-01-29 03:23:24.897 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-01-29 03:23:24.897 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:23:24.897 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:23:24.897 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:23:24.897 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETRXGAIN
2026-01-29 03:23:24.897 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:23:24.897 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:23:24.897 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:23:24.898 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:23:24.898 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:23:24.898 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:23:24.898 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:23:24.898 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:23:24.898 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:23:24.898 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:23:24.898 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:23:24.898 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:23:24.898 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:23:24.898 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:23:24.898 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:23:24.898 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:23:24.898 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:23:24.898 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:23:24.898 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:23:24.898 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:23:24.898 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:23:24.898 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:23:24.899 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:23:24.902 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-01-29 03:23:25.384 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-01-29 03:23:25.430 [DEBUG] fake_trx.py:278 (BTS@172.18.28.20:5700) Recv FAKE_TOA cmd
2026-01-29 03:23:25.431 [DEBUG] fake_trx.py:297 (BTS@172.18.28.20:5700) Recv FAKE_RSSI cmd
2026-01-29 03:23:25.433 [DEBUG] fake_trx.py:322 (BTS@172.18.28.20:5700) Recv FAKE_CI cmd
2026-01-29 03:23:25.434 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:23:25.865 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-01-29 03:23:25.901 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 03:23:25.901 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:23:25.902 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:23:25.906 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:23:26.345 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-01-29 03:23:26.827 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-01-29 03:23:26.903 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:23:26.903 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 03:23:26.903 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:23:26.907 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:23:27.308 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-01-29 03:23:27.789 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-01-29 03:23:27.904 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:23:27.905 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 03:23:27.905 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:23:27.909 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:23:28.270 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-01-29 03:23:28.752 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-01-29 03:23:28.906 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 03:23:28.906 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:23:28.906 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:23:28.910 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:23:29.253 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-01-29 03:23:29.734 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-01-29 03:23:29.907 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:23:29.908 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 03:23:29.908 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:23:29.912 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:23:30.215 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-01-29 03:23:30.696 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-01-29 03:23:31.178 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-01-29 03:23:31.659 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-01-29 03:23:32.140 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-01-29 03:23:32.621 [DEBUG] clck_gen.py:113 IND CLOCK 1632
2026-01-29 03:23:33.103 [DEBUG] clck_gen.py:113 IND CLOCK 1734
2026-01-29 03:23:33.584 [DEBUG] clck_gen.py:113 IND CLOCK 1836
2026-01-29 03:23:34.063 [DEBUG] clck_gen.py:113 IND CLOCK 1938
2026-01-29 03:23:34.544 [DEBUG] clck_gen.py:113 IND CLOCK 2040
2026-01-29 03:23:35.022 [DEBUG] clck_gen.py:113 IND CLOCK 2142
2026-01-29 03:23:35.446 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 03:23:35.446 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:23:35.446 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:23:35.446 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:23:35.447 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 03:23:35.447 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 03:23:35.447 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 03:23:35.447 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 03:23:35.448 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.28.20:5700) Recv POWEROFF cmd
2026-01-29 03:23:35.448 [INFO] ctrl_if_trx.py:117 (BTS@172.18.28.20:5700) Stopping transceiver...
2026-01-29 03:23:35.448 [INFO] transceiver.py:246 Stopping clock generator
2026-01-29 03:23:35.448 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=2235 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:23:35.448 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=2235 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:23:35.448 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=2235 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:23:35.448 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=2235 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:23:35.448 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=2236 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:23:35.448 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=2236 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:23:35.448 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=2236 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:23:35.448 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=2236 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:23:35.448 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=2236 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:23:35.448 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=2236 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:23:35.448 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=2236 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:23:35.448 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=2236 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:23:40.449 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.28.20:5700) Recv POWEROFF cmd
2026-01-29 03:23:40.449 [INFO] ctrl_if_trx.py:117 (BTS@172.18.28.20:5700) Stopping transceiver...
2026-01-29 03:23:40.451 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 03:23:40.451 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 03:23:40.452 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 03:23:40.452 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 03:23:40.459 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 03:23:40.460 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.28.20:5700) Recv SETFORMAT cmd
2026-01-29 03:23:40.460 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.28.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:23:40.460 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.28.20:5700) Recv SETFORMAT cmd
2026-01-29 03:23:40.461 [INFO] ctrl_if_trx.py:201 (BTS@172.18.28.20:5700) TRXD header version 1 -> 1
2026-01-29 03:23:40.462 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.28.20:5700/1) Recv RXTUNE cmd
2026-01-29 03:23:40.462 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.28.20:5700/1) Recv TXTUNE cmd
2026-01-29 03:23:40.463 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.28.20:5700/1) Recv SETFORMAT cmd
2026-01-29 03:23:40.463 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.28.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:23:40.463 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 03:23:40.463 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.28.20:5700/1) Recv NOMTXPOWER cmd
2026-01-29 03:23:40.464 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.28.20:5700/1) Recv SETFORMAT cmd
2026-01-29 03:23:40.464 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.28.20:5700/1) TRXD header version 1 -> 1
2026-01-29 03:23:40.465 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.28.20:5700/2) Recv RXTUNE cmd
2026-01-29 03:23:40.465 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.28.20:5700/2) Recv TXTUNE cmd
2026-01-29 03:23:40.465 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.28.20:5700/2) Recv SETFORMAT cmd
2026-01-29 03:23:40.465 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.28.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:23:40.465 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 03:23:40.465 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.28.20:5700/2) Recv NOMTXPOWER cmd
2026-01-29 03:23:40.465 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.28.20:5700/2) Recv SETFORMAT cmd
2026-01-29 03:23:40.465 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.28.20:5700/2) TRXD header version 1 -> 1
2026-01-29 03:23:40.467 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.28.20:5700/3) Recv RXTUNE cmd
2026-01-29 03:23:40.467 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.28.20:5700/3) Recv TXTUNE cmd
2026-01-29 03:23:40.467 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.28.20:5700/3) Recv SETFORMAT cmd
2026-01-29 03:23:40.467 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.28.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:23:40.467 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 03:23:40.467 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.28.20:5700/3) Recv NOMTXPOWER cmd
2026-01-29 03:23:40.467 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.28.20:5700/3) Recv SETFORMAT cmd
2026-01-29 03:23:40.467 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.28.20:5700/3) TRXD header version 1 -> 1
2026-01-29 03:23:40.469 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.28.20:5700) Recv RXTUNE cmd
2026-01-29 03:23:40.469 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETTSC
2026-01-29 03:23:40.469 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETTSC
2026-01-29 03:23:40.469 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETTSC
2026-01-29 03:23:40.469 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.28.20:5700) Recv TXTUNE cmd
2026-01-29 03:23:40.469 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETRXGAIN
2026-01-29 03:23:40.469 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETRXGAIN
2026-01-29 03:23:40.470 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETRXGAIN
2026-01-29 03:23:40.470 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETTSC
2026-01-29 03:23:40.470 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:23:40.470 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:23:40.470 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:23:40.470 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.28.20:5700) Recv NOMTXPOWER cmd
2026-01-29 03:23:40.470 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:23:40.470 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:23:40.470 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:23:40.470 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.28.20:5700) Recv POWERON CMD
2026-01-29 03:23:40.470 [INFO] ctrl_if_trx.py:109 (BTS@172.18.28.20:5700) Starting transceiver...
2026-01-29 03:23:40.470 [INFO] transceiver.py:243 Starting clock generator
2026-01-29 03:23:40.470 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-01-29 03:23:40.470 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:23:40.470 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:23:40.470 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:23:40.470 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETRXGAIN
2026-01-29 03:23:40.470 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:23:40.470 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:23:40.470 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:23:40.470 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:23:40.471 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:23:40.471 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:23:40.471 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:23:40.471 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:23:40.471 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:23:40.471 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:23:40.471 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:23:40.471 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:23:40.471 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:23:40.471 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:23:40.471 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:23:40.471 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:23:40.471 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:23:40.471 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:23:40.471 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:23:40.471 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 03:23:40.471 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:23:40.471 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:23:40.471 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:23:40.471 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:23:40.471 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 03:23:40.471 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 03:23:40.472 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 03:23:40.472 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.28.20:5700) Recv POWEROFF cmd
2026-01-29 03:23:40.472 [INFO] ctrl_if_trx.py:117 (BTS@172.18.28.20:5700) Stopping transceiver...
2026-01-29 03:23:40.472 [INFO] transceiver.py:246 Stopping clock generator
2026-01-29 03:23:45.479 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.28.20:5700) Recv POWEROFF cmd
2026-01-29 03:23:45.480 [INFO] ctrl_if_trx.py:117 (BTS@172.18.28.20:5700) Stopping transceiver...
2026-01-29 03:23:45.480 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 03:23:45.480 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 03:23:45.480 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 03:23:45.480 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 03:23:45.487 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 03:23:45.488 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.28.20:5700) Recv SETFORMAT cmd
2026-01-29 03:23:45.488 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.28.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:23:45.489 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.28.20:5700) Recv SETFORMAT cmd
2026-01-29 03:23:45.489 [INFO] ctrl_if_trx.py:201 (BTS@172.18.28.20:5700) TRXD header version 1 -> 1
2026-01-29 03:23:45.492 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.28.20:5700/1) Recv RXTUNE cmd
2026-01-29 03:23:45.493 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.28.20:5700/1) Recv TXTUNE cmd
2026-01-29 03:23:45.493 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.28.20:5700/1) Recv SETFORMAT cmd
2026-01-29 03:23:45.493 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.28.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:23:45.494 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 03:23:45.494 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.28.20:5700/1) Recv NOMTXPOWER cmd
2026-01-29 03:23:45.495 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.28.20:5700/1) Recv SETFORMAT cmd
2026-01-29 03:23:45.495 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.28.20:5700/1) TRXD header version 1 -> 1
2026-01-29 03:23:45.496 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.28.20:5700/2) Recv RXTUNE cmd
2026-01-29 03:23:45.496 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.28.20:5700/2) Recv TXTUNE cmd
2026-01-29 03:23:45.496 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.28.20:5700/2) Recv SETFORMAT cmd
2026-01-29 03:23:45.496 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.28.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:23:45.497 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 03:23:45.497 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.28.20:5700/2) Recv NOMTXPOWER cmd
2026-01-29 03:23:45.497 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.28.20:5700/2) Recv SETFORMAT cmd
2026-01-29 03:23:45.497 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.28.20:5700/2) TRXD header version 1 -> 1
2026-01-29 03:23:45.499 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.28.20:5700/3) Recv RXTUNE cmd
2026-01-29 03:23:45.499 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.28.20:5700/3) Recv TXTUNE cmd
2026-01-29 03:23:45.499 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.28.20:5700/3) Recv SETFORMAT cmd
2026-01-29 03:23:45.500 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.28.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:23:45.500 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 03:23:45.500 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.28.20:5700/3) Recv NOMTXPOWER cmd
2026-01-29 03:23:45.500 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.28.20:5700/3) Recv SETFORMAT cmd
2026-01-29 03:23:45.500 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.28.20:5700/3) TRXD header version 1 -> 1
2026-01-29 03:23:45.503 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.28.20:5700) Recv RXTUNE cmd
2026-01-29 03:23:45.503 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETTSC
2026-01-29 03:23:45.503 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETTSC
2026-01-29 03:23:45.503 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETTSC
2026-01-29 03:23:45.503 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.28.20:5700) Recv TXTUNE cmd
2026-01-29 03:23:45.503 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETRXGAIN
2026-01-29 03:23:45.503 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETRXGAIN
2026-01-29 03:23:45.503 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETRXGAIN
2026-01-29 03:23:45.503 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETTSC
2026-01-29 03:23:45.503 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:23:45.503 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:23:45.503 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.28.20:5700) Recv NOMTXPOWER cmd
2026-01-29 03:23:45.503 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:23:45.503 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:23:45.503 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:23:45.503 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.28.20:5700) Recv POWERON CMD
2026-01-29 03:23:45.503 [INFO] ctrl_if_trx.py:109 (BTS@172.18.28.20:5700) Starting transceiver...
2026-01-29 03:23:45.503 [INFO] transceiver.py:243 Starting clock generator
2026-01-29 03:23:45.503 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-01-29 03:23:45.504 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:23:45.504 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:23:45.504 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:23:45.504 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETRXGAIN
2026-01-29 03:23:45.504 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:23:45.504 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:23:45.504 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:23:45.504 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:23:45.504 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:23:45.504 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:23:45.504 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:23:45.504 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:23:45.504 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:23:45.504 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:23:45.504 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:23:45.504 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:23:45.504 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:23:45.504 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:23:45.504 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:23:45.505 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:23:45.505 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:23:45.505 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:23:45.505 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:23:45.505 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:23:45.505 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:23:45.505 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:23:45.505 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:23:45.505 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:23:45.508 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-01-29 03:23:45.990 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-01-29 03:23:46.042 [DEBUG] fake_trx.py:278 (BTS@172.18.28.20:5700) Recv FAKE_TOA cmd
2026-01-29 03:23:46.043 [DEBUG] fake_trx.py:297 (BTS@172.18.28.20:5700) Recv FAKE_RSSI cmd
2026-01-29 03:23:46.044 [DEBUG] fake_trx.py:322 (BTS@172.18.28.20:5700) Recv FAKE_CI cmd
2026-01-29 03:23:46.044 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:23:46.046 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 03:23:46.046 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 03:23:46.046 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 03:23:46.047 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 03:23:46.047 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 03:23:46.047 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 03:23:46.048 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.28.22:6700) Recv POWERON CMD
2026-01-29 03:23:46.048 [INFO] ctrl_if_trx.py:109 (MS@172.18.28.22:6700) Starting transceiver...
2026-01-29 03:23:46.467 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-01-29 03:23:46.508 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:23:46.508 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 03:23:46.509 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:23:46.513 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:23:46.945 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-01-29 03:23:47.422 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-01-29 03:23:47.509 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 03:23:47.509 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:23:47.509 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:23:47.514 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:23:47.900 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-01-29 03:23:48.378 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-01-29 03:23:48.510 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 03:23:48.510 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:23:48.510 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:23:48.514 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:23:48.855 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-01-29 03:23:49.333 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-01-29 03:23:49.511 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:23:49.511 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:23:49.512 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 03:23:49.516 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:23:49.811 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-01-29 03:23:50.288 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-01-29 03:23:50.513 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 03:23:50.513 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:23:50.513 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:23:50.516 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:23:50.767 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-01-29 03:23:51.245 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-01-29 03:23:51.723 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-01-29 03:23:52.201 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-01-29 03:23:52.679 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-01-29 03:23:53.157 [DEBUG] clck_gen.py:113 IND CLOCK 1632
2026-01-29 03:23:53.634 [DEBUG] clck_gen.py:113 IND CLOCK 1734
2026-01-29 03:23:54.086 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 03:23:54.086 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 03:23:54.089 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 03:23:54.089 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:23:54.089 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:23:54.089 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:23:54.090 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 03:23:54.090 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 03:23:54.090 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 03:23:54.090 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.28.20:5700) Recv POWEROFF cmd
2026-01-29 03:23:54.090 [INFO] ctrl_if_trx.py:117 (BTS@172.18.28.20:5700) Stopping transceiver...
2026-01-29 03:23:54.090 [INFO] transceiver.py:246 Stopping clock generator
2026-01-29 03:23:54.090 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 03:23:59.093 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.28.20:5700) Recv POWEROFF cmd
2026-01-29 03:23:59.093 [INFO] ctrl_if_trx.py:117 (BTS@172.18.28.20:5700) Stopping transceiver...
2026-01-29 03:23:59.095 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 03:23:59.096 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 03:23:59.096 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 03:23:59.096 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 03:23:59.104 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 03:23:59.104 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.28.20:5700) Recv SETFORMAT cmd
2026-01-29 03:23:59.105 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.28.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:23:59.105 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.28.20:5700) Recv SETFORMAT cmd
2026-01-29 03:23:59.105 [INFO] ctrl_if_trx.py:201 (BTS@172.18.28.20:5700) TRXD header version 1 -> 1
2026-01-29 03:23:59.107 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.28.20:5700/1) Recv RXTUNE cmd
2026-01-29 03:23:59.107 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.28.20:5700/1) Recv TXTUNE cmd
2026-01-29 03:23:59.108 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.28.20:5700/1) Recv SETFORMAT cmd
2026-01-29 03:23:59.108 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.28.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:23:59.108 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 03:23:59.108 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.28.20:5700/1) Recv NOMTXPOWER cmd
2026-01-29 03:23:59.109 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.28.20:5700/1) Recv SETFORMAT cmd
2026-01-29 03:23:59.109 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.28.20:5700/1) TRXD header version 1 -> 1
2026-01-29 03:23:59.109 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.28.20:5700/2) Recv RXTUNE cmd
2026-01-29 03:23:59.110 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.28.20:5700/2) Recv TXTUNE cmd
2026-01-29 03:23:59.110 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.28.20:5700/2) Recv SETFORMAT cmd
2026-01-29 03:23:59.110 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.28.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:23:59.110 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 03:23:59.110 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.28.20:5700/2) Recv NOMTXPOWER cmd
2026-01-29 03:23:59.110 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.28.20:5700/2) Recv SETFORMAT cmd
2026-01-29 03:23:59.110 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.28.20:5700/2) TRXD header version 1 -> 1
2026-01-29 03:23:59.112 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.28.20:5700/3) Recv RXTUNE cmd
2026-01-29 03:23:59.112 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.28.20:5700/3) Recv TXTUNE cmd
2026-01-29 03:23:59.112 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.28.20:5700/3) Recv SETFORMAT cmd
2026-01-29 03:23:59.112 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.28.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:23:59.112 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 03:23:59.112 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.28.20:5700/3) Recv NOMTXPOWER cmd
2026-01-29 03:23:59.112 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.28.20:5700/3) Recv SETFORMAT cmd
2026-01-29 03:23:59.112 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.28.20:5700/3) TRXD header version 1 -> 1
2026-01-29 03:23:59.114 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.28.20:5700) Recv RXTUNE cmd
2026-01-29 03:23:59.114 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETTSC
2026-01-29 03:23:59.115 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETTSC
2026-01-29 03:23:59.115 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETTSC
2026-01-29 03:23:59.115 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.28.20:5700) Recv TXTUNE cmd
2026-01-29 03:23:59.115 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETRXGAIN
2026-01-29 03:23:59.115 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETRXGAIN
2026-01-29 03:23:59.115 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETRXGAIN
2026-01-29 03:23:59.115 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETTSC
2026-01-29 03:23:59.115 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:23:59.115 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:23:59.115 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:23:59.115 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.28.20:5700) Recv NOMTXPOWER cmd
2026-01-29 03:23:59.115 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:23:59.115 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:23:59.115 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:23:59.115 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.28.20:5700) Recv POWERON CMD
2026-01-29 03:23:59.115 [INFO] ctrl_if_trx.py:109 (BTS@172.18.28.20:5700) Starting transceiver...
2026-01-29 03:23:59.115 [INFO] transceiver.py:243 Starting clock generator
2026-01-29 03:23:59.115 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-01-29 03:23:59.115 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:23:59.115 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:23:59.115 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:23:59.115 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETRXGAIN
2026-01-29 03:23:59.115 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:23:59.115 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:23:59.115 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:23:59.115 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:23:59.116 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:23:59.116 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:23:59.116 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:23:59.116 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:23:59.116 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:23:59.117 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:23:59.117 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:23:59.117 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:23:59.117 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:23:59.117 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:23:59.117 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:23:59.117 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:23:59.117 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:23:59.117 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:23:59.117 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:23:59.117 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 03:23:59.117 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:23:59.117 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:23:59.117 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:23:59.117 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:23:59.117 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 03:23:59.117 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 03:23:59.117 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 03:23:59.117 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.28.20:5700) Recv POWEROFF cmd
2026-01-29 03:23:59.117 [INFO] ctrl_if_trx.py:117 (BTS@172.18.28.20:5700) Stopping transceiver...
2026-01-29 03:23:59.117 [INFO] transceiver.py:246 Stopping clock generator
2026-01-29 03:24:04.120 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.28.20:5700) Recv POWEROFF cmd
2026-01-29 03:24:04.120 [INFO] ctrl_if_trx.py:117 (BTS@172.18.28.20:5700) Stopping transceiver...
2026-01-29 03:24:04.122 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 03:24:04.123 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 03:24:04.124 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 03:24:04.125 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 03:24:04.133 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 03:24:04.134 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.28.20:5700) Recv SETFORMAT cmd
2026-01-29 03:24:04.134 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.28.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:24:04.135 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.28.20:5700) Recv SETFORMAT cmd
2026-01-29 03:24:04.135 [INFO] ctrl_if_trx.py:201 (BTS@172.18.28.20:5700) TRXD header version 1 -> 1
2026-01-29 03:24:04.138 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.28.20:5700/1) Recv RXTUNE cmd
2026-01-29 03:24:04.139 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.28.20:5700/1) Recv TXTUNE cmd
2026-01-29 03:24:04.139 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.28.20:5700/1) Recv SETFORMAT cmd
2026-01-29 03:24:04.139 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.28.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:24:04.140 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 03:24:04.140 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.28.20:5700/1) Recv NOMTXPOWER cmd
2026-01-29 03:24:04.140 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.28.20:5700/1) Recv SETFORMAT cmd
2026-01-29 03:24:04.140 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.28.20:5700/1) TRXD header version 1 -> 1
2026-01-29 03:24:04.141 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.28.20:5700/2) Recv RXTUNE cmd
2026-01-29 03:24:04.142 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.28.20:5700/2) Recv TXTUNE cmd
2026-01-29 03:24:04.142 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.28.20:5700/2) Recv SETFORMAT cmd
2026-01-29 03:24:04.142 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.28.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:24:04.142 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 03:24:04.142 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.28.20:5700/2) Recv NOMTXPOWER cmd
2026-01-29 03:24:04.143 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.28.20:5700/2) Recv SETFORMAT cmd
2026-01-29 03:24:04.143 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.28.20:5700/2) TRXD header version 1 -> 1
2026-01-29 03:24:04.144 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.28.20:5700/3) Recv RXTUNE cmd
2026-01-29 03:24:04.144 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.28.20:5700/3) Recv TXTUNE cmd
2026-01-29 03:24:04.144 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.28.20:5700/3) Recv SETFORMAT cmd
2026-01-29 03:24:04.144 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.28.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:24:04.144 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 03:24:04.144 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.28.20:5700/3) Recv NOMTXPOWER cmd
2026-01-29 03:24:04.144 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.28.20:5700/3) Recv SETFORMAT cmd
2026-01-29 03:24:04.144 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.28.20:5700/3) TRXD header version 1 -> 1
2026-01-29 03:24:04.147 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.28.20:5700) Recv RXTUNE cmd
2026-01-29 03:24:04.147 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETTSC
2026-01-29 03:24:04.147 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETTSC
2026-01-29 03:24:04.147 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETTSC
2026-01-29 03:24:04.147 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.28.20:5700) Recv TXTUNE cmd
2026-01-29 03:24:04.147 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETRXGAIN
2026-01-29 03:24:04.147 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETRXGAIN
2026-01-29 03:24:04.147 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETRXGAIN
2026-01-29 03:24:04.147 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETTSC
2026-01-29 03:24:04.147 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:24:04.147 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:24:04.147 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:24:04.147 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.28.20:5700) Recv NOMTXPOWER cmd
2026-01-29 03:24:04.147 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:24:04.147 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:24:04.147 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:24:04.147 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.28.20:5700) Recv POWERON CMD
2026-01-29 03:24:04.147 [INFO] ctrl_if_trx.py:109 (BTS@172.18.28.20:5700) Starting transceiver...
2026-01-29 03:24:04.147 [INFO] transceiver.py:243 Starting clock generator
2026-01-29 03:24:04.148 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-01-29 03:24:04.148 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:24:04.148 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:24:04.148 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:24:04.148 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETRXGAIN
2026-01-29 03:24:04.148 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:24:04.148 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:24:04.148 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:24:04.148 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:24:04.148 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:24:04.148 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:24:04.148 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:24:04.148 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:24:04.148 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:24:04.148 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:24:04.148 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:24:04.148 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:24:04.148 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:24:04.148 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:24:04.149 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:24:04.149 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:24:04.149 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:24:04.149 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:24:04.149 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:24:04.149 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:24:04.149 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:24:04.149 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:24:04.149 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:24:04.152 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-01-29 03:24:04.636 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-01-29 03:24:04.680 [DEBUG] fake_trx.py:278 (BTS@172.18.28.20:5700) Recv FAKE_TOA cmd
2026-01-29 03:24:04.682 [DEBUG] fake_trx.py:297 (BTS@172.18.28.20:5700) Recv FAKE_RSSI cmd
2026-01-29 03:24:04.684 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:24:04.685 [DEBUG] fake_trx.py:322 (BTS@172.18.28.20:5700) Recv FAKE_CI cmd
2026-01-29 03:24:04.688 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 03:24:04.688 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 03:24:04.688 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 03:24:04.689 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 03:24:04.689 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 03:24:04.689 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 03:24:04.689 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.28.22:6700) Recv POWERON CMD
2026-01-29 03:24:04.689 [INFO] ctrl_if_trx.py:109 (MS@172.18.28.22:6700) Starting transceiver...
2026-01-29 03:24:05.114 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-01-29 03:24:05.151 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:24:05.151 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 03:24:05.152 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:24:05.155 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:24:05.592 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-01-29 03:24:06.070 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-01-29 03:24:06.152 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:24:06.152 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 03:24:06.152 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:24:06.156 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:24:06.548 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-01-29 03:24:07.025 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-01-29 03:24:07.153 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 03:24:07.153 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:24:07.153 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:24:07.157 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:24:07.503 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-01-29 03:24:07.981 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-01-29 03:24:08.153 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 03:24:08.153 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:24:08.154 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:24:08.158 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:24:08.459 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-01-29 03:24:08.937 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-01-29 03:24:09.154 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 03:24:09.154 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:24:09.155 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:24:09.159 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:24:09.414 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-01-29 03:24:09.892 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-01-29 03:24:10.370 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-01-29 03:24:10.847 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-01-29 03:24:11.325 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-01-29 03:24:11.803 [DEBUG] clck_gen.py:113 IND CLOCK 1632
2026-01-29 03:24:12.281 [DEBUG] clck_gen.py:113 IND CLOCK 1734
2026-01-29 03:24:12.731 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 03:24:12.731 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 03:24:12.735 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 03:24:12.736 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:24:12.736 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:24:12.736 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:24:12.739 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 03:24:12.740 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 03:24:12.740 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 03:24:12.740 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 03:24:12.740 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.28.20:5700) Recv POWEROFF cmd
2026-01-29 03:24:12.740 [INFO] ctrl_if_trx.py:117 (BTS@172.18.28.20:5700) Stopping transceiver...
2026-01-29 03:24:12.740 [INFO] transceiver.py:246 Stopping clock generator
2026-01-29 03:24:12.741 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=1834 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:24:12.741 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=1834 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:24:12.741 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=1834 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:24:12.741 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=1834 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:24:12.741 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=1834 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:24:12.741 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=1834 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:24:12.741 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=1835 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:24:12.741 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=1835 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:24:12.741 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=1835 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:24:12.742 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=1835 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:24:12.742 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=1835 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:24:12.742 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=1835 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:24:12.742 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=1835 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:24:12.742 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=1835 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:24:17.743 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.28.20:5700) Recv POWEROFF cmd
2026-01-29 03:24:17.743 [INFO] ctrl_if_trx.py:117 (BTS@172.18.28.20:5700) Stopping transceiver...
2026-01-29 03:24:17.743 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 03:24:17.743 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 03:24:17.743 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 03:24:17.743 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 03:24:17.746 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 03:24:17.746 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.28.20:5700) Recv SETFORMAT cmd
2026-01-29 03:24:17.746 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.28.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:24:17.746 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.28.20:5700) Recv SETFORMAT cmd
2026-01-29 03:24:17.746 [INFO] ctrl_if_trx.py:201 (BTS@172.18.28.20:5700) TRXD header version 1 -> 1
2026-01-29 03:24:17.748 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.28.20:5700/1) Recv RXTUNE cmd
2026-01-29 03:24:17.748 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.28.20:5700/1) Recv TXTUNE cmd
2026-01-29 03:24:17.748 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.28.20:5700/1) Recv SETFORMAT cmd
2026-01-29 03:24:17.748 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.28.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:24:17.748 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 03:24:17.748 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.28.20:5700/1) Recv NOMTXPOWER cmd
2026-01-29 03:24:17.748 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.28.20:5700/1) Recv SETFORMAT cmd
2026-01-29 03:24:17.748 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.28.20:5700/1) TRXD header version 1 -> 1
2026-01-29 03:24:17.750 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.28.20:5700/2) Recv RXTUNE cmd
2026-01-29 03:24:17.750 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.28.20:5700/2) Recv TXTUNE cmd
2026-01-29 03:24:17.750 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.28.20:5700/2) Recv SETFORMAT cmd
2026-01-29 03:24:17.751 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.28.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:24:17.751 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 03:24:17.751 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.28.20:5700/2) Recv NOMTXPOWER cmd
2026-01-29 03:24:17.751 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.28.20:5700/2) Recv SETFORMAT cmd
2026-01-29 03:24:17.751 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.28.20:5700/2) TRXD header version 1 -> 1
2026-01-29 03:24:17.752 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.28.20:5700/3) Recv RXTUNE cmd
2026-01-29 03:24:17.752 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.28.20:5700/3) Recv TXTUNE cmd
2026-01-29 03:24:17.752 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.28.20:5700/3) Recv SETFORMAT cmd
2026-01-29 03:24:17.752 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.28.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:24:17.753 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 03:24:17.753 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.28.20:5700/3) Recv NOMTXPOWER cmd
2026-01-29 03:24:17.753 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.28.20:5700/3) Recv SETFORMAT cmd
2026-01-29 03:24:17.753 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.28.20:5700/3) TRXD header version 1 -> 1
2026-01-29 03:24:17.755 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.28.20:5700) Recv RXTUNE cmd
2026-01-29 03:24:17.755 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETTSC
2026-01-29 03:24:17.755 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETTSC
2026-01-29 03:24:17.755 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETTSC
2026-01-29 03:24:17.755 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.28.20:5700) Recv TXTUNE cmd
2026-01-29 03:24:17.755 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETRXGAIN
2026-01-29 03:24:17.755 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETRXGAIN
2026-01-29 03:24:17.756 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETRXGAIN
2026-01-29 03:24:17.756 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETTSC
2026-01-29 03:24:17.756 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:24:17.756 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:24:17.756 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:24:17.756 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.28.20:5700) Recv NOMTXPOWER cmd
2026-01-29 03:24:17.756 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:24:17.756 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.28.20:5700) Recv POWERON CMD
2026-01-29 03:24:17.756 [INFO] ctrl_if_trx.py:109 (BTS@172.18.28.20:5700) Starting transceiver...
2026-01-29 03:24:17.756 [INFO] transceiver.py:243 Starting clock generator
2026-01-29 03:24:17.756 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-01-29 03:24:17.756 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:24:17.756 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:24:17.756 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:24:17.756 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETRXGAIN
2026-01-29 03:24:17.756 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:24:17.756 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:24:17.756 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:24:17.756 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:24:17.756 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:24:17.756 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:24:17.756 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:24:17.756 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:24:17.756 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:24:17.756 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:24:17.756 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:24:17.756 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:24:17.757 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:24:17.757 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:24:17.757 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:24:17.757 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:24:17.757 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:24:17.757 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:24:17.757 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:24:17.757 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:24:17.757 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:24:17.757 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:24:17.757 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:24:17.757 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:24:17.757 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:24:17.758 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 03:24:17.758 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 03:24:17.758 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 03:24:17.758 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 03:24:17.758 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.28.20:5700) Recv POWEROFF cmd
2026-01-29 03:24:17.758 [INFO] ctrl_if_trx.py:117 (BTS@172.18.28.20:5700) Stopping transceiver...
2026-01-29 03:24:17.758 [INFO] transceiver.py:246 Stopping clock generator
2026-01-29 03:24:22.762 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.28.20:5700) Recv POWEROFF cmd
2026-01-29 03:24:22.762 [INFO] ctrl_if_trx.py:117 (BTS@172.18.28.20:5700) Stopping transceiver...
2026-01-29 03:24:22.764 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 03:24:22.765 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 03:24:22.766 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 03:24:22.766 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 03:24:22.774 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 03:24:22.776 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.28.20:5700) Recv SETFORMAT cmd
2026-01-29 03:24:22.776 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.28.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:24:22.777 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.28.20:5700) Recv SETFORMAT cmd
2026-01-29 03:24:22.777 [INFO] ctrl_if_trx.py:201 (BTS@172.18.28.20:5700) TRXD header version 1 -> 1
2026-01-29 03:24:22.780 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.28.20:5700/1) Recv RXTUNE cmd
2026-01-29 03:24:22.780 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.28.20:5700/1) Recv TXTUNE cmd
2026-01-29 03:24:22.781 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.28.20:5700/1) Recv SETFORMAT cmd
2026-01-29 03:24:22.781 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.28.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:24:22.781 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 03:24:22.782 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.28.20:5700/1) Recv NOMTXPOWER cmd
2026-01-29 03:24:22.782 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.28.20:5700/1) Recv SETFORMAT cmd
2026-01-29 03:24:22.782 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.28.20:5700/1) TRXD header version 1 -> 1
2026-01-29 03:24:22.783 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.28.20:5700/2) Recv RXTUNE cmd
2026-01-29 03:24:22.783 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.28.20:5700/2) Recv TXTUNE cmd
2026-01-29 03:24:22.784 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.28.20:5700/2) Recv SETFORMAT cmd
2026-01-29 03:24:22.784 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.28.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:24:22.784 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 03:24:22.784 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.28.20:5700/2) Recv NOMTXPOWER cmd
2026-01-29 03:24:22.784 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.28.20:5700/2) Recv SETFORMAT cmd
2026-01-29 03:24:22.784 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.28.20:5700/2) TRXD header version 1 -> 1
2026-01-29 03:24:22.786 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.28.20:5700/3) Recv RXTUNE cmd
2026-01-29 03:24:22.786 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.28.20:5700/3) Recv TXTUNE cmd
2026-01-29 03:24:22.786 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.28.20:5700/3) Recv SETFORMAT cmd
2026-01-29 03:24:22.786 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.28.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:24:22.786 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 03:24:22.786 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.28.20:5700/3) Recv NOMTXPOWER cmd
2026-01-29 03:24:22.786 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.28.20:5700/3) Recv SETFORMAT cmd
2026-01-29 03:24:22.786 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.28.20:5700/3) TRXD header version 1 -> 1
2026-01-29 03:24:22.788 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.28.20:5700) Recv RXTUNE cmd
2026-01-29 03:24:22.789 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETTSC
2026-01-29 03:24:22.789 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETTSC
2026-01-29 03:24:22.789 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETTSC
2026-01-29 03:24:22.789 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.28.20:5700) Recv TXTUNE cmd
2026-01-29 03:24:22.789 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETRXGAIN
2026-01-29 03:24:22.789 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETRXGAIN
2026-01-29 03:24:22.789 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETRXGAIN
2026-01-29 03:24:22.789 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETTSC
2026-01-29 03:24:22.789 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:24:22.789 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:24:22.789 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:24:22.789 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.28.20:5700) Recv NOMTXPOWER cmd
2026-01-29 03:24:22.789 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:24:22.789 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:24:22.789 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:24:22.789 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.28.20:5700) Recv POWERON CMD
2026-01-29 03:24:22.789 [INFO] ctrl_if_trx.py:109 (BTS@172.18.28.20:5700) Starting transceiver...
2026-01-29 03:24:22.789 [INFO] transceiver.py:243 Starting clock generator
2026-01-29 03:24:22.789 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-01-29 03:24:22.789 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:24:22.789 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:24:22.789 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:24:22.789 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETRXGAIN
2026-01-29 03:24:22.790 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:24:22.790 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:24:22.790 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:24:22.790 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:24:22.790 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:24:22.790 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:24:22.790 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:24:22.790 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:24:22.790 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:24:22.790 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:24:22.790 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:24:22.790 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:24:22.790 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:24:22.790 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:24:22.790 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:24:22.790 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:24:22.790 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:24:22.790 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:24:22.790 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:24:22.790 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:24:22.790 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:24:22.790 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:24:22.790 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:24:22.794 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-01-29 03:24:23.277 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-01-29 03:24:23.318 [DEBUG] fake_trx.py:278 (BTS@172.18.28.20:5700) Recv FAKE_TOA cmd
2026-01-29 03:24:23.320 [DEBUG] fake_trx.py:297 (BTS@172.18.28.20:5700) Recv FAKE_RSSI cmd
2026-01-29 03:24:23.323 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:24:23.323 [DEBUG] fake_trx.py:322 (BTS@172.18.28.20:5700) Recv FAKE_CI cmd
2026-01-29 03:24:23.326 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 03:24:23.327 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 03:24:23.327 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 03:24:23.327 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 03:24:23.327 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 03:24:23.328 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 03:24:23.328 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.28.22:6700) Recv POWERON CMD
2026-01-29 03:24:23.328 [INFO] ctrl_if_trx.py:109 (MS@172.18.28.22:6700) Starting transceiver...
2026-01-29 03:24:23.754 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-01-29 03:24:23.792 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 03:24:23.792 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:24:23.793 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:24:23.794 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:24:24.231 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-01-29 03:24:24.709 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-01-29 03:24:24.793 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 03:24:24.793 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:24:24.793 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:24:24.795 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:24:25.187 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-01-29 03:24:25.664 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-01-29 03:24:25.794 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 03:24:25.794 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:24:25.794 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:24:25.797 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:24:26.142 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-01-29 03:24:26.620 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-01-29 03:24:26.795 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:24:26.795 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:24:26.796 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 03:24:26.798 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:24:27.098 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-01-29 03:24:27.576 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-01-29 03:24:27.796 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 03:24:27.796 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:24:27.797 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:24:27.798 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:24:28.053 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-01-29 03:24:28.531 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-01-29 03:24:29.009 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-01-29 03:24:29.487 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-01-29 03:24:29.965 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-01-29 03:24:30.442 [DEBUG] clck_gen.py:113 IND CLOCK 1632
2026-01-29 03:24:30.920 [DEBUG] clck_gen.py:113 IND CLOCK 1734
2026-01-29 03:24:31.370 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 03:24:31.370 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 03:24:31.374 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 03:24:31.375 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:24:31.375 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:24:31.375 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:24:31.376 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 03:24:31.376 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 03:24:31.376 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 03:24:31.376 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.28.20:5700) Recv POWEROFF cmd
2026-01-29 03:24:31.376 [INFO] ctrl_if_trx.py:117 (BTS@172.18.28.20:5700) Stopping transceiver...
2026-01-29 03:24:31.376 [INFO] transceiver.py:246 Stopping clock generator
2026-01-29 03:24:31.376 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 03:24:31.376 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=1834 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:24:31.376 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=1834 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:24:31.376 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=1834 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:24:31.376 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=1834 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:24:31.376 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=1834 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:24:31.376 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=1834 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:24:31.376 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=1834 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:24:31.376 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=1834 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:24:36.378 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.28.20:5700) Recv POWEROFF cmd
2026-01-29 03:24:36.378 [INFO] ctrl_if_trx.py:117 (BTS@172.18.28.20:5700) Stopping transceiver...
2026-01-29 03:24:36.380 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 03:24:36.381 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 03:24:36.382 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 03:24:36.382 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 03:24:36.390 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 03:24:36.392 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.28.20:5700) Recv SETFORMAT cmd
2026-01-29 03:24:36.392 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.28.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:24:36.392 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.28.20:5700) Recv SETFORMAT cmd
2026-01-29 03:24:36.392 [INFO] ctrl_if_trx.py:201 (BTS@172.18.28.20:5700) TRXD header version 1 -> 1
2026-01-29 03:24:36.396 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.28.20:5700/1) Recv RXTUNE cmd
2026-01-29 03:24:36.396 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.28.20:5700/1) Recv TXTUNE cmd
2026-01-29 03:24:36.397 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.28.20:5700/1) Recv SETFORMAT cmd
2026-01-29 03:24:36.397 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.28.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:24:36.397 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 03:24:36.398 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.28.20:5700/1) Recv NOMTXPOWER cmd
2026-01-29 03:24:36.398 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.28.20:5700/1) Recv SETFORMAT cmd
2026-01-29 03:24:36.398 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.28.20:5700/1) TRXD header version 1 -> 1
2026-01-29 03:24:36.399 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.28.20:5700/2) Recv RXTUNE cmd
2026-01-29 03:24:36.399 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.28.20:5700/2) Recv TXTUNE cmd
2026-01-29 03:24:36.399 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.28.20:5700/2) Recv SETFORMAT cmd
2026-01-29 03:24:36.399 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.28.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:24:36.399 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 03:24:36.400 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.28.20:5700/2) Recv NOMTXPOWER cmd
2026-01-29 03:24:36.400 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.28.20:5700/2) Recv SETFORMAT cmd
2026-01-29 03:24:36.400 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.28.20:5700/2) TRXD header version 1 -> 1
2026-01-29 03:24:36.401 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.28.20:5700/3) Recv RXTUNE cmd
2026-01-29 03:24:36.401 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.28.20:5700/3) Recv TXTUNE cmd
2026-01-29 03:24:36.401 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.28.20:5700/3) Recv SETFORMAT cmd
2026-01-29 03:24:36.401 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.28.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:24:36.402 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 03:24:36.402 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.28.20:5700/3) Recv NOMTXPOWER cmd
2026-01-29 03:24:36.402 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.28.20:5700/3) Recv SETFORMAT cmd
2026-01-29 03:24:36.402 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.28.20:5700/3) TRXD header version 1 -> 1
2026-01-29 03:24:36.404 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.28.20:5700) Recv RXTUNE cmd
2026-01-29 03:24:36.404 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETTSC
2026-01-29 03:24:36.404 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETTSC
2026-01-29 03:24:36.404 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETTSC
2026-01-29 03:24:36.404 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.28.20:5700) Recv TXTUNE cmd
2026-01-29 03:24:36.404 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETRXGAIN
2026-01-29 03:24:36.404 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETRXGAIN
2026-01-29 03:24:36.405 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETRXGAIN
2026-01-29 03:24:36.405 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETTSC
2026-01-29 03:24:36.405 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:24:36.405 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:24:36.405 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:24:36.405 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.28.20:5700) Recv NOMTXPOWER cmd
2026-01-29 03:24:36.405 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:24:36.405 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:24:36.405 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:24:36.405 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.28.20:5700) Recv POWERON CMD
2026-01-29 03:24:36.405 [INFO] ctrl_if_trx.py:109 (BTS@172.18.28.20:5700) Starting transceiver...
2026-01-29 03:24:36.405 [INFO] transceiver.py:243 Starting clock generator
2026-01-29 03:24:36.405 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-01-29 03:24:36.405 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:24:36.405 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:24:36.405 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:24:36.405 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETRXGAIN
2026-01-29 03:24:36.405 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:24:36.405 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:24:36.405 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:24:36.405 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:24:36.406 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:24:36.406 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:24:36.406 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:24:36.406 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:24:36.406 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:24:36.406 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:24:36.406 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:24:36.406 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:24:36.406 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:24:36.406 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:24:36.406 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:24:36.407 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:24:36.407 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:24:36.407 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:24:36.407 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:24:36.407 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 03:24:36.407 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:24:36.407 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:24:36.407 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:24:36.407 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:24:36.407 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 03:24:36.407 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 03:24:36.407 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 03:24:36.407 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.28.20:5700) Recv POWEROFF cmd
2026-01-29 03:24:36.407 [INFO] ctrl_if_trx.py:117 (BTS@172.18.28.20:5700) Stopping transceiver...
2026-01-29 03:24:36.407 [INFO] transceiver.py:246 Stopping clock generator
2026-01-29 03:24:41.410 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.28.20:5700) Recv POWEROFF cmd
2026-01-29 03:24:41.410 [INFO] ctrl_if_trx.py:117 (BTS@172.18.28.20:5700) Stopping transceiver...
2026-01-29 03:24:41.413 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 03:24:41.413 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 03:24:41.413 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 03:24:41.413 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 03:24:41.421 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 03:24:41.421 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.28.20:5700) Recv SETFORMAT cmd
2026-01-29 03:24:41.421 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.28.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:24:41.421 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.28.20:5700) Recv SETFORMAT cmd
2026-01-29 03:24:41.422 [INFO] ctrl_if_trx.py:201 (BTS@172.18.28.20:5700) TRXD header version 1 -> 1
2026-01-29 03:24:41.424 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.28.20:5700/1) Recv RXTUNE cmd
2026-01-29 03:24:41.424 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.28.20:5700/1) Recv TXTUNE cmd
2026-01-29 03:24:41.425 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.28.20:5700/1) Recv SETFORMAT cmd
2026-01-29 03:24:41.425 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.28.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:24:41.425 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 03:24:41.426 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.28.20:5700/1) Recv NOMTXPOWER cmd
2026-01-29 03:24:41.426 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.28.20:5700/1) Recv SETFORMAT cmd
2026-01-29 03:24:41.426 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.28.20:5700/1) TRXD header version 1 -> 1
2026-01-29 03:24:41.427 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.28.20:5700/2) Recv RXTUNE cmd
2026-01-29 03:24:41.427 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.28.20:5700/2) Recv TXTUNE cmd
2026-01-29 03:24:41.428 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.28.20:5700/2) Recv SETFORMAT cmd
2026-01-29 03:24:41.428 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.28.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:24:41.428 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 03:24:41.429 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.28.20:5700/2) Recv NOMTXPOWER cmd
2026-01-29 03:24:41.429 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.28.20:5700/2) Recv SETFORMAT cmd
2026-01-29 03:24:41.429 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.28.20:5700/2) TRXD header version 1 -> 1
2026-01-29 03:24:41.430 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.28.20:5700/3) Recv RXTUNE cmd
2026-01-29 03:24:41.430 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.28.20:5700/3) Recv TXTUNE cmd
2026-01-29 03:24:41.430 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.28.20:5700/3) Recv SETFORMAT cmd
2026-01-29 03:24:41.430 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.28.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:24:41.430 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 03:24:41.430 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.28.20:5700/3) Recv NOMTXPOWER cmd
2026-01-29 03:24:41.431 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.28.20:5700/3) Recv SETFORMAT cmd
2026-01-29 03:24:41.431 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.28.20:5700/3) TRXD header version 1 -> 1
2026-01-29 03:24:41.433 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.28.20:5700) Recv RXTUNE cmd
2026-01-29 03:24:41.433 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETTSC
2026-01-29 03:24:41.433 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETTSC
2026-01-29 03:24:41.434 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETTSC
2026-01-29 03:24:41.434 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.28.20:5700) Recv TXTUNE cmd
2026-01-29 03:24:41.434 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETRXGAIN
2026-01-29 03:24:41.434 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETRXGAIN
2026-01-29 03:24:41.434 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETRXGAIN
2026-01-29 03:24:41.434 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETTSC
2026-01-29 03:24:41.434 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:24:41.434 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:24:41.434 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.28.20:5700) Recv NOMTXPOWER cmd
2026-01-29 03:24:41.434 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:24:41.434 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:24:41.434 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:24:41.434 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.28.20:5700) Recv POWERON CMD
2026-01-29 03:24:41.434 [INFO] ctrl_if_trx.py:109 (BTS@172.18.28.20:5700) Starting transceiver...
2026-01-29 03:24:41.434 [INFO] transceiver.py:243 Starting clock generator
2026-01-29 03:24:41.434 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-01-29 03:24:41.434 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:24:41.434 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:24:41.434 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:24:41.435 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETRXGAIN
2026-01-29 03:24:41.435 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:24:41.435 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:24:41.435 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:24:41.435 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:24:41.435 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:24:41.435 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:24:41.435 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:24:41.435 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:24:41.435 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:24:41.435 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:24:41.435 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:24:41.435 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:24:41.435 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:24:41.435 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:24:41.435 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:24:41.435 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:24:41.435 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:24:41.435 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:24:41.435 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:24:41.435 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:24:41.435 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:24:41.435 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:24:41.435 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:24:41.435 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:24:41.439 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-01-29 03:24:41.922 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-01-29 03:24:41.964 [DEBUG] fake_trx.py:278 (BTS@172.18.28.20:5700) Recv FAKE_TOA cmd
2026-01-29 03:24:41.967 [DEBUG] fake_trx.py:297 (BTS@172.18.28.20:5700) Recv FAKE_RSSI cmd
2026-01-29 03:24:41.967 [DEBUG] fake_trx.py:322 (BTS@172.18.28.20:5700) Recv FAKE_CI cmd
2026-01-29 03:24:41.967 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:24:41.969 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 03:24:41.969 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 03:24:41.969 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 03:24:41.970 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 03:24:41.970 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 03:24:41.970 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 03:24:41.970 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.28.22:6700) Recv POWERON CMD
2026-01-29 03:24:41.970 [INFO] ctrl_if_trx.py:109 (MS@172.18.28.22:6700) Starting transceiver...
2026-01-29 03:24:42.399 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-01-29 03:24:42.437 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 03:24:42.438 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:24:42.438 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:24:42.442 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:24:42.877 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-01-29 03:24:43.355 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-01-29 03:24:43.438 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 03:24:43.439 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:24:43.439 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:24:43.442 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:24:43.833 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-01-29 03:24:44.311 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-01-29 03:24:44.439 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 03:24:44.440 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:24:44.440 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:24:44.444 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:24:44.789 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-01-29 03:24:45.267 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-01-29 03:24:45.440 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 03:24:45.441 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:24:45.441 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:24:45.445 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:24:45.745 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-01-29 03:24:46.223 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-01-29 03:24:46.441 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 03:24:46.441 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:24:46.441 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:24:46.446 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:24:46.701 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-01-29 03:24:47.179 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-01-29 03:24:47.657 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-01-29 03:24:48.135 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-01-29 03:24:48.611 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-01-29 03:24:49.089 [DEBUG] clck_gen.py:113 IND CLOCK 1632
2026-01-29 03:24:49.567 [DEBUG] clck_gen.py:113 IND CLOCK 1734
2026-01-29 03:24:50.015 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 03:24:50.016 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 03:24:50.018 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 03:24:50.018 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:24:50.018 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:24:50.018 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:24:50.019 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 03:24:50.019 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 03:24:50.019 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 03:24:50.019 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 03:24:50.019 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.28.20:5700) Recv POWEROFF cmd
2026-01-29 03:24:50.019 [INFO] ctrl_if_trx.py:117 (BTS@172.18.28.20:5700) Stopping transceiver...
2026-01-29 03:24:50.019 [INFO] transceiver.py:246 Stopping clock generator
2026-01-29 03:24:55.026 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.28.20:5700) Recv POWEROFF cmd
2026-01-29 03:24:55.026 [INFO] ctrl_if_trx.py:117 (BTS@172.18.28.20:5700) Stopping transceiver...
2026-01-29 03:24:55.026 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 03:24:55.026 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 03:24:55.026 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 03:24:55.026 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 03:24:55.035 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 03:24:55.037 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.28.20:5700) Recv SETFORMAT cmd
2026-01-29 03:24:55.038 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.28.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:24:55.038 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.28.20:5700) Recv SETFORMAT cmd
2026-01-29 03:24:55.038 [INFO] ctrl_if_trx.py:201 (BTS@172.18.28.20:5700) TRXD header version 1 -> 1
2026-01-29 03:24:55.043 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.28.20:5700/1) Recv RXTUNE cmd
2026-01-29 03:24:55.043 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.28.20:5700/1) Recv TXTUNE cmd
2026-01-29 03:24:55.044 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.28.20:5700/1) Recv SETFORMAT cmd
2026-01-29 03:24:55.044 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.28.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:24:55.044 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 03:24:55.045 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.28.20:5700/1) Recv NOMTXPOWER cmd
2026-01-29 03:24:55.045 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.28.20:5700/1) Recv SETFORMAT cmd
2026-01-29 03:24:55.045 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.28.20:5700/1) TRXD header version 1 -> 1
2026-01-29 03:24:55.046 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.28.20:5700/2) Recv RXTUNE cmd
2026-01-29 03:24:55.047 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.28.20:5700/2) Recv TXTUNE cmd
2026-01-29 03:24:55.047 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.28.20:5700/2) Recv SETFORMAT cmd
2026-01-29 03:24:55.047 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.28.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:24:55.047 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 03:24:55.047 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.28.20:5700/2) Recv NOMTXPOWER cmd
2026-01-29 03:24:55.048 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.28.20:5700/2) Recv SETFORMAT cmd
2026-01-29 03:24:55.048 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.28.20:5700/2) TRXD header version 1 -> 1
2026-01-29 03:24:55.050 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.28.20:5700/3) Recv RXTUNE cmd
2026-01-29 03:24:55.050 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.28.20:5700/3) Recv TXTUNE cmd
2026-01-29 03:24:55.050 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.28.20:5700/3) Recv SETFORMAT cmd
2026-01-29 03:24:55.050 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.28.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:24:55.050 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 03:24:55.050 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.28.20:5700/3) Recv NOMTXPOWER cmd
2026-01-29 03:24:55.050 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.28.20:5700/3) Recv SETFORMAT cmd
2026-01-29 03:24:55.050 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.28.20:5700/3) TRXD header version 1 -> 1
2026-01-29 03:24:55.053 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.28.20:5700) Recv RXTUNE cmd
2026-01-29 03:24:55.053 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETTSC
2026-01-29 03:24:55.053 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETTSC
2026-01-29 03:24:55.054 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETTSC
2026-01-29 03:24:55.054 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.28.20:5700) Recv TXTUNE cmd
2026-01-29 03:24:55.054 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETRXGAIN
2026-01-29 03:24:55.054 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETRXGAIN
2026-01-29 03:24:55.054 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETRXGAIN
2026-01-29 03:24:55.054 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETTSC
2026-01-29 03:24:55.054 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:24:55.054 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:24:55.054 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:24:55.054 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.28.20:5700) Recv NOMTXPOWER cmd
2026-01-29 03:24:55.054 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:24:55.054 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:24:55.054 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:24:55.054 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.28.20:5700) Recv POWERON CMD
2026-01-29 03:24:55.054 [INFO] ctrl_if_trx.py:109 (BTS@172.18.28.20:5700) Starting transceiver...
2026-01-29 03:24:55.054 [INFO] transceiver.py:243 Starting clock generator
2026-01-29 03:24:55.054 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-01-29 03:24:55.054 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:24:55.054 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:24:55.055 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:24:55.055 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETRXGAIN
2026-01-29 03:24:55.055 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:24:55.055 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:24:55.055 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:24:55.055 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:24:55.055 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:24:55.055 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:24:55.055 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:24:55.055 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:24:55.056 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:24:55.056 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:24:55.056 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:24:55.056 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:24:55.056 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:24:55.056 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:24:55.056 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:24:55.056 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:24:55.056 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:24:55.056 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:24:55.056 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:24:55.056 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:24:55.056 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 03:24:55.056 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:24:55.056 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:24:55.056 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 03:24:55.056 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:24:55.056 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 03:24:55.056 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 03:24:55.056 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.28.20:5700) Recv POWEROFF cmd
2026-01-29 03:24:55.056 [INFO] ctrl_if_trx.py:117 (BTS@172.18.28.20:5700) Stopping transceiver...
2026-01-29 03:24:55.057 [INFO] transceiver.py:246 Stopping clock generator
2026-01-29 03:25:00.060 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.28.20:5700) Recv POWEROFF cmd
2026-01-29 03:25:00.060 [INFO] ctrl_if_trx.py:117 (BTS@172.18.28.20:5700) Stopping transceiver...
2026-01-29 03:25:00.062 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 03:25:00.063 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 03:25:00.063 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 03:25:00.063 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 03:25:00.068 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 03:25:00.070 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.28.20:5700) Recv SETFORMAT cmd
2026-01-29 03:25:00.070 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.28.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:25:00.070 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.28.20:5700) Recv SETFORMAT cmd
2026-01-29 03:25:00.070 [INFO] ctrl_if_trx.py:201 (BTS@172.18.28.20:5700) TRXD header version 1 -> 1
2026-01-29 03:25:00.073 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.28.20:5700/1) Recv RXTUNE cmd
2026-01-29 03:25:00.073 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.28.20:5700/1) Recv TXTUNE cmd
2026-01-29 03:25:00.074 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.28.20:5700/1) Recv SETFORMAT cmd
2026-01-29 03:25:00.074 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.28.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:25:00.074 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 03:25:00.075 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.28.20:5700/1) Recv NOMTXPOWER cmd
2026-01-29 03:25:00.075 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.28.20:5700/1) Recv SETFORMAT cmd
2026-01-29 03:25:00.075 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.28.20:5700/1) TRXD header version 1 -> 1
2026-01-29 03:25:00.076 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.28.20:5700/2) Recv RXTUNE cmd
2026-01-29 03:25:00.076 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.28.20:5700/2) Recv TXTUNE cmd
2026-01-29 03:25:00.076 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.28.20:5700/2) Recv SETFORMAT cmd
2026-01-29 03:25:00.076 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.28.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:25:00.076 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 03:25:00.076 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.28.20:5700/2) Recv NOMTXPOWER cmd
2026-01-29 03:25:00.076 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.28.20:5700/2) Recv SETFORMAT cmd
2026-01-29 03:25:00.076 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.28.20:5700/2) TRXD header version 1 -> 1
2026-01-29 03:25:00.078 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.28.20:5700/3) Recv RXTUNE cmd
2026-01-29 03:25:00.078 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.28.20:5700/3) Recv TXTUNE cmd
2026-01-29 03:25:00.079 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.28.20:5700/3) Recv SETFORMAT cmd
2026-01-29 03:25:00.079 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.28.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:25:00.079 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 03:25:00.079 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.28.20:5700/3) Recv NOMTXPOWER cmd
2026-01-29 03:25:00.079 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.28.20:5700/3) Recv SETFORMAT cmd
2026-01-29 03:25:00.079 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.28.20:5700/3) TRXD header version 1 -> 1
2026-01-29 03:25:00.081 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.28.20:5700) Recv RXTUNE cmd
2026-01-29 03:25:00.081 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETTSC
2026-01-29 03:25:00.082 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETTSC
2026-01-29 03:25:00.082 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETTSC
2026-01-29 03:25:00.082 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.28.20:5700) Recv TXTUNE cmd
2026-01-29 03:25:00.082 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETRXGAIN
2026-01-29 03:25:00.082 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETRXGAIN
2026-01-29 03:25:00.082 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETRXGAIN
2026-01-29 03:25:00.082 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETTSC
2026-01-29 03:25:00.082 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:25:00.082 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:25:00.082 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:25:00.082 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.28.20:5700) Recv NOMTXPOWER cmd
2026-01-29 03:25:00.082 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:25:00.082 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:25:00.082 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:25:00.082 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.28.20:5700) Recv POWERON CMD
2026-01-29 03:25:00.082 [INFO] ctrl_if_trx.py:109 (BTS@172.18.28.20:5700) Starting transceiver...
2026-01-29 03:25:00.082 [INFO] transceiver.py:243 Starting clock generator
2026-01-29 03:25:00.082 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-01-29 03:25:00.082 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:25:00.082 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:25:00.082 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:25:00.082 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETRXGAIN
2026-01-29 03:25:00.083 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:25:00.083 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:25:00.083 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:25:00.083 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:25:00.083 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:25:00.083 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:25:00.083 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:25:00.083 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:25:00.083 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:25:00.083 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:25:00.083 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:25:00.083 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:25:00.083 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:25:00.083 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:25:00.083 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:25:00.083 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:25:00.083 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:25:00.083 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:25:00.083 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:25:00.083 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:25:00.083 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:25:00.083 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:25:00.083 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:25:00.087 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-01-29 03:25:00.570 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-01-29 03:25:00.606 [DEBUG] fake_trx.py:278 (BTS@172.18.28.20:5700) Recv FAKE_TOA cmd
2026-01-29 03:25:00.607 [DEBUG] fake_trx.py:297 (BTS@172.18.28.20:5700) Recv FAKE_RSSI cmd
2026-01-29 03:25:00.608 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:25:00.609 [DEBUG] fake_trx.py:322 (BTS@172.18.28.20:5700) Recv FAKE_CI cmd
2026-01-29 03:25:00.610 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 03:25:00.610 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 03:25:00.610 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 03:25:00.610 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 03:25:00.610 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 03:25:00.610 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 03:25:00.610 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.28.22:6700) Recv POWERON CMD
2026-01-29 03:25:00.610 [INFO] ctrl_if_trx.py:109 (MS@172.18.28.22:6700) Starting transceiver...
2026-01-29 03:25:01.048 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-01-29 03:25:01.085 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 03:25:01.085 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:25:01.086 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:25:01.088 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:25:01.525 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-01-29 03:25:02.003 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-01-29 03:25:02.085 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 03:25:02.086 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:25:02.086 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:25:02.089 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:25:02.481 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-01-29 03:25:02.959 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-01-29 03:25:03.086 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 03:25:03.087 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:25:03.087 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:25:03.089 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:25:03.437 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-01-29 03:25:03.915 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-01-29 03:25:04.087 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 03:25:04.087 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:25:04.087 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:25:04.091 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:25:04.393 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-01-29 03:25:04.871 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-01-29 03:25:05.088 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 03:25:05.088 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:25:05.088 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:25:05.092 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:25:05.349 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-01-29 03:25:05.826 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-01-29 03:25:06.304 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-01-29 03:25:06.782 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-01-29 03:25:07.260 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-01-29 03:25:07.737 [DEBUG] clck_gen.py:113 IND CLOCK 1632
2026-01-29 03:25:08.215 [DEBUG] clck_gen.py:113 IND CLOCK 1734
2026-01-29 03:25:08.693 [DEBUG] clck_gen.py:113 IND CLOCK 1836
2026-01-29 03:25:09.170 [DEBUG] clck_gen.py:113 IND CLOCK 1938
2026-01-29 03:25:09.648 [DEBUG] clck_gen.py:113 IND CLOCK 2040
2026-01-29 03:25:10.126 [DEBUG] clck_gen.py:113 IND CLOCK 2142
2026-01-29 03:25:10.603 [DEBUG] clck_gen.py:113 IND CLOCK 2244
2026-01-29 03:25:11.081 [DEBUG] clck_gen.py:113 IND CLOCK 2346
2026-01-29 03:25:11.559 [DEBUG] clck_gen.py:113 IND CLOCK 2448
2026-01-29 03:25:12.037 [DEBUG] clck_gen.py:113 IND CLOCK 2550
2026-01-29 03:25:12.515 [DEBUG] clck_gen.py:113 IND CLOCK 2652
2026-01-29 03:25:12.993 [DEBUG] clck_gen.py:113 IND CLOCK 2754
2026-01-29 03:25:13.470 [DEBUG] clck_gen.py:113 IND CLOCK 2856
2026-01-29 03:25:13.948 [DEBUG] clck_gen.py:113 IND CLOCK 2958
2026-01-29 03:25:14.426 [DEBUG] clck_gen.py:113 IND CLOCK 3060
2026-01-29 03:25:14.618 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 03:25:14.618 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 03:25:14.620 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 03:25:14.620 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:25:14.620 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:25:14.620 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:25:14.620 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 03:25:14.620 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 03:25:14.620 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 03:25:14.621 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.28.20:5700) Recv POWEROFF cmd
2026-01-29 03:25:14.621 [INFO] ctrl_if_trx.py:117 (BTS@172.18.28.20:5700) Stopping transceiver...
2026-01-29 03:25:14.621 [INFO] transceiver.py:246 Stopping clock generator
2026-01-29 03:25:14.621 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 03:25:14.621 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=3104 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:25:14.621 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=3104 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:25:14.621 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=3104 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:25:14.621 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=3104 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:25:14.621 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=3104 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:25:14.621 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=3104 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:25:14.621 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=3104 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:25:19.623 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.28.20:5700) Recv POWEROFF cmd
2026-01-29 03:25:19.623 [INFO] ctrl_if_trx.py:117 (BTS@172.18.28.20:5700) Stopping transceiver...
2026-01-29 03:25:19.625 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 03:25:19.626 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 03:25:19.626 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 03:25:19.626 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 03:25:19.633 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 03:25:19.635 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.28.20:5700) Recv SETFORMAT cmd
2026-01-29 03:25:19.635 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.28.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:25:19.635 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.28.20:5700) Recv SETFORMAT cmd
2026-01-29 03:25:19.635 [INFO] ctrl_if_trx.py:201 (BTS@172.18.28.20:5700) TRXD header version 1 -> 1
2026-01-29 03:25:19.638 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.28.20:5700/1) Recv RXTUNE cmd
2026-01-29 03:25:19.638 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.28.20:5700/1) Recv TXTUNE cmd
2026-01-29 03:25:19.639 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.28.20:5700/1) Recv SETFORMAT cmd
2026-01-29 03:25:19.639 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.28.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:25:19.640 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 03:25:19.640 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.28.20:5700/1) Recv NOMTXPOWER cmd
2026-01-29 03:25:19.641 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.28.20:5700/1) Recv SETFORMAT cmd
2026-01-29 03:25:19.641 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.28.20:5700/1) TRXD header version 1 -> 1
2026-01-29 03:25:19.642 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.28.20:5700/2) Recv RXTUNE cmd
2026-01-29 03:25:19.642 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.28.20:5700/2) Recv TXTUNE cmd
2026-01-29 03:25:19.642 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.28.20:5700/2) Recv SETFORMAT cmd
2026-01-29 03:25:19.643 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.28.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:25:19.643 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 03:25:19.643 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.28.20:5700/2) Recv NOMTXPOWER cmd
2026-01-29 03:25:19.644 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.28.20:5700/2) Recv SETFORMAT cmd
2026-01-29 03:25:19.644 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.28.20:5700/2) TRXD header version 1 -> 1
2026-01-29 03:25:19.645 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.28.20:5700/3) Recv RXTUNE cmd
2026-01-29 03:25:19.645 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.28.20:5700/3) Recv TXTUNE cmd
2026-01-29 03:25:19.645 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.28.20:5700/3) Recv SETFORMAT cmd
2026-01-29 03:25:19.645 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.28.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:25:19.645 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 03:25:19.646 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.28.20:5700/3) Recv NOMTXPOWER cmd
2026-01-29 03:25:19.646 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.28.20:5700/3) Recv SETFORMAT cmd
2026-01-29 03:25:19.646 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.28.20:5700/3) TRXD header version 1 -> 1
2026-01-29 03:25:19.649 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.28.20:5700) Recv RXTUNE cmd
2026-01-29 03:25:19.649 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETTSC
2026-01-29 03:25:19.649 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETTSC
2026-01-29 03:25:19.649 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETTSC
2026-01-29 03:25:19.649 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.28.20:5700) Recv TXTUNE cmd
2026-01-29 03:25:19.650 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETRXGAIN
2026-01-29 03:25:19.650 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETRXGAIN
2026-01-29 03:25:19.650 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETRXGAIN
2026-01-29 03:25:19.650 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETTSC
2026-01-29 03:25:19.650 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:25:19.650 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:25:19.650 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:25:19.650 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.28.20:5700) Recv NOMTXPOWER cmd
2026-01-29 03:25:19.650 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:25:19.650 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:25:19.650 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:25:19.650 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.28.20:5700) Recv POWERON CMD
2026-01-29 03:25:19.650 [INFO] ctrl_if_trx.py:109 (BTS@172.18.28.20:5700) Starting transceiver...
2026-01-29 03:25:19.650 [INFO] transceiver.py:243 Starting clock generator
2026-01-29 03:25:19.650 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-01-29 03:25:19.651 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:25:19.651 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:25:19.651 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:25:19.651 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETRXGAIN
2026-01-29 03:25:19.651 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:25:19.651 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:25:19.651 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:25:19.651 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:25:19.652 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:25:19.652 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:25:19.652 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:25:19.652 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:25:19.652 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:25:19.652 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:25:19.652 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:25:19.652 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:25:19.652 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:25:19.653 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:25:19.653 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:25:19.653 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:25:19.653 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:25:19.653 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:25:19.653 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:25:19.653 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 03:25:19.653 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:25:19.653 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:25:19.653 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:25:19.653 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:25:19.653 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 03:25:19.653 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 03:25:19.653 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 03:25:19.653 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.28.20:5700) Recv POWEROFF cmd
2026-01-29 03:25:19.653 [INFO] ctrl_if_trx.py:117 (BTS@172.18.28.20:5700) Stopping transceiver...
2026-01-29 03:25:19.653 [INFO] transceiver.py:246 Stopping clock generator
2026-01-29 03:25:24.656 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.28.20:5700) Recv POWEROFF cmd
2026-01-29 03:25:24.656 [INFO] ctrl_if_trx.py:117 (BTS@172.18.28.20:5700) Stopping transceiver...
2026-01-29 03:25:24.657 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 03:25:24.659 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 03:25:24.660 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 03:25:24.663 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 03:25:24.677 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 03:25:24.679 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.28.20:5700) Recv SETFORMAT cmd
2026-01-29 03:25:24.679 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.28.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:25:24.679 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.28.20:5700) Recv SETFORMAT cmd
2026-01-29 03:25:24.679 [INFO] ctrl_if_trx.py:201 (BTS@172.18.28.20:5700) TRXD header version 1 -> 1
2026-01-29 03:25:24.683 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.28.20:5700/1) Recv RXTUNE cmd
2026-01-29 03:25:24.684 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.28.20:5700/1) Recv TXTUNE cmd
2026-01-29 03:25:24.684 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.28.20:5700/1) Recv SETFORMAT cmd
2026-01-29 03:25:24.684 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.28.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:25:24.685 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 03:25:24.685 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.28.20:5700/1) Recv NOMTXPOWER cmd
2026-01-29 03:25:24.686 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.28.20:5700/1) Recv SETFORMAT cmd
2026-01-29 03:25:24.686 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.28.20:5700/1) TRXD header version 1 -> 1
2026-01-29 03:25:24.686 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.28.20:5700/2) Recv RXTUNE cmd
2026-01-29 03:25:24.687 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.28.20:5700/2) Recv TXTUNE cmd
2026-01-29 03:25:24.687 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.28.20:5700/2) Recv SETFORMAT cmd
2026-01-29 03:25:24.687 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.28.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:25:24.687 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 03:25:24.687 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.28.20:5700/2) Recv NOMTXPOWER cmd
2026-01-29 03:25:24.688 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.28.20:5700/2) Recv SETFORMAT cmd
2026-01-29 03:25:24.688 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.28.20:5700/2) TRXD header version 1 -> 1
2026-01-29 03:25:24.689 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.28.20:5700/3) Recv RXTUNE cmd
2026-01-29 03:25:24.689 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.28.20:5700/3) Recv TXTUNE cmd
2026-01-29 03:25:24.689 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.28.20:5700/3) Recv SETFORMAT cmd
2026-01-29 03:25:24.689 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.28.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:25:24.689 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 03:25:24.689 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.28.20:5700/3) Recv NOMTXPOWER cmd
2026-01-29 03:25:24.689 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.28.20:5700/3) Recv SETFORMAT cmd
2026-01-29 03:25:24.689 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.28.20:5700/3) TRXD header version 1 -> 1
2026-01-29 03:25:24.692 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.28.20:5700) Recv RXTUNE cmd
2026-01-29 03:25:24.692 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETTSC
2026-01-29 03:25:24.692 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETTSC
2026-01-29 03:25:24.692 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETTSC
2026-01-29 03:25:24.692 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.28.20:5700) Recv TXTUNE cmd
2026-01-29 03:25:24.692 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETRXGAIN
2026-01-29 03:25:24.692 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETRXGAIN
2026-01-29 03:25:24.692 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETRXGAIN
2026-01-29 03:25:24.692 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETTSC
2026-01-29 03:25:24.692 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:25:24.692 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:25:24.692 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:25:24.692 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.28.20:5700) Recv NOMTXPOWER cmd
2026-01-29 03:25:24.692 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:25:24.692 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:25:24.692 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:25:24.692 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.28.20:5700) Recv POWERON CMD
2026-01-29 03:25:24.692 [INFO] ctrl_if_trx.py:109 (BTS@172.18.28.20:5700) Starting transceiver...
2026-01-29 03:25:24.692 [INFO] transceiver.py:243 Starting clock generator
2026-01-29 03:25:24.692 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-01-29 03:25:24.692 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:25:24.693 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:25:24.693 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:25:24.693 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETRXGAIN
2026-01-29 03:25:24.693 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:25:24.693 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:25:24.693 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:25:24.693 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:25:24.693 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:25:24.693 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:25:24.693 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:25:24.693 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:25:24.693 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:25:24.693 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:25:24.693 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:25:24.693 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:25:24.693 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:25:24.693 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:25:24.693 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:25:24.693 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:25:24.693 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:25:24.693 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:25:24.693 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:25:24.693 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:25:24.693 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:25:24.693 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:25:24.693 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:25:24.697 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-01-29 03:25:25.180 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-01-29 03:25:25.227 [DEBUG] fake_trx.py:278 (BTS@172.18.28.20:5700) Recv FAKE_TOA cmd
2026-01-29 03:25:25.230 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:25:25.230 [DEBUG] fake_trx.py:297 (BTS@172.18.28.20:5700) Recv FAKE_RSSI cmd
2026-01-29 03:25:25.233 [DEBUG] fake_trx.py:322 (BTS@172.18.28.20:5700) Recv FAKE_CI cmd
2026-01-29 03:25:25.237 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 03:25:25.237 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 03:25:25.237 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 03:25:25.238 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 03:25:25.238 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 03:25:25.238 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 03:25:25.238 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.28.22:6700) Recv POWERON CMD
2026-01-29 03:25:25.239 [INFO] ctrl_if_trx.py:109 (MS@172.18.28.22:6700) Starting transceiver...
2026-01-29 03:25:25.657 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-01-29 03:25:25.695 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 03:25:25.695 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:25:25.696 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:25:25.699 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:25:26.135 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-01-29 03:25:26.613 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-01-29 03:25:26.696 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 03:25:26.696 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:25:26.696 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:25:26.700 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:25:27.090 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-01-29 03:25:27.568 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-01-29 03:25:27.697 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 03:25:27.697 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:25:27.697 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:25:27.701 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:25:28.046 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-01-29 03:25:28.524 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-01-29 03:25:28.698 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 03:25:28.698 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:25:28.698 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:25:28.702 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:25:29.002 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-01-29 03:25:29.506 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-01-29 03:25:29.698 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 03:25:29.699 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:25:29.699 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:25:29.703 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:25:29.984 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-01-29 03:25:30.462 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-01-29 03:25:30.940 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-01-29 03:25:31.417 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-01-29 03:25:31.895 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-01-29 03:25:32.373 [DEBUG] clck_gen.py:113 IND CLOCK 1632
2026-01-29 03:25:32.851 [DEBUG] clck_gen.py:113 IND CLOCK 1734
2026-01-29 03:25:33.274 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 03:25:33.274 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 03:25:33.279 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 03:25:33.279 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:25:33.280 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:25:33.280 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:25:33.283 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 03:25:33.283 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 03:25:33.283 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 03:25:33.283 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 03:25:33.283 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.28.20:5700) Recv POWEROFF cmd
2026-01-29 03:25:33.283 [INFO] ctrl_if_trx.py:117 (BTS@172.18.28.20:5700) Stopping transceiver...
2026-01-29 03:25:33.283 [INFO] transceiver.py:246 Stopping clock generator
2026-01-29 03:25:33.284 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=1829 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:25:33.284 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=1829 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:25:33.284 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=1829 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:25:33.284 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=1829 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:25:33.284 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=1829 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:25:33.284 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=1829 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:25:38.282 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.28.20:5700) Recv POWEROFF cmd
2026-01-29 03:25:38.282 [INFO] ctrl_if_trx.py:117 (BTS@172.18.28.20:5700) Stopping transceiver...
2026-01-29 03:25:38.284 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 03:25:38.285 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 03:25:38.286 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 03:25:38.286 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 03:25:38.289 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 03:25:38.290 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.28.20:5700) Recv SETFORMAT cmd
2026-01-29 03:25:38.290 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.28.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:25:38.290 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.28.20:5700) Recv SETFORMAT cmd
2026-01-29 03:25:38.290 [INFO] ctrl_if_trx.py:201 (BTS@172.18.28.20:5700) TRXD header version 1 -> 1
2026-01-29 03:25:38.291 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.28.20:5700/1) Recv RXTUNE cmd
2026-01-29 03:25:38.291 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.28.20:5700/1) Recv TXTUNE cmd
2026-01-29 03:25:38.292 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.28.20:5700/1) Recv SETFORMAT cmd
2026-01-29 03:25:38.292 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.28.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:25:38.292 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 03:25:38.292 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.28.20:5700/1) Recv NOMTXPOWER cmd
2026-01-29 03:25:38.293 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.28.20:5700/1) Recv SETFORMAT cmd
2026-01-29 03:25:38.293 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.28.20:5700/1) TRXD header version 1 -> 1
2026-01-29 03:25:38.293 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.28.20:5700/2) Recv RXTUNE cmd
2026-01-29 03:25:38.293 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.28.20:5700/2) Recv TXTUNE cmd
2026-01-29 03:25:38.293 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.28.20:5700/2) Recv SETFORMAT cmd
2026-01-29 03:25:38.294 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.28.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:25:38.294 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 03:25:38.294 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.28.20:5700/2) Recv NOMTXPOWER cmd
2026-01-29 03:25:38.294 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.28.20:5700/2) Recv SETFORMAT cmd
2026-01-29 03:25:38.294 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.28.20:5700/2) TRXD header version 1 -> 1
2026-01-29 03:25:38.295 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.28.20:5700/3) Recv RXTUNE cmd
2026-01-29 03:25:38.295 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.28.20:5700/3) Recv TXTUNE cmd
2026-01-29 03:25:38.296 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.28.20:5700/3) Recv SETFORMAT cmd
2026-01-29 03:25:38.296 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.28.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:25:38.296 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 03:25:38.296 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.28.20:5700/3) Recv NOMTXPOWER cmd
2026-01-29 03:25:38.296 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.28.20:5700/3) Recv SETFORMAT cmd
2026-01-29 03:25:38.296 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.28.20:5700/3) TRXD header version 1 -> 1
2026-01-29 03:25:38.298 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.28.20:5700) Recv RXTUNE cmd
2026-01-29 03:25:38.298 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETTSC
2026-01-29 03:25:38.298 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETTSC
2026-01-29 03:25:38.298 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETTSC
2026-01-29 03:25:38.298 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.28.20:5700) Recv TXTUNE cmd
2026-01-29 03:25:38.298 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETRXGAIN
2026-01-29 03:25:38.299 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETRXGAIN
2026-01-29 03:25:38.299 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETRXGAIN
2026-01-29 03:25:38.299 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETTSC
2026-01-29 03:25:38.299 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:25:38.299 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:25:38.299 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.28.20:5700) Recv NOMTXPOWER cmd
2026-01-29 03:25:38.299 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:25:38.299 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:25:38.299 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:25:38.299 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.28.20:5700) Recv POWERON CMD
2026-01-29 03:25:38.299 [INFO] ctrl_if_trx.py:109 (BTS@172.18.28.20:5700) Starting transceiver...
2026-01-29 03:25:38.299 [INFO] transceiver.py:243 Starting clock generator
2026-01-29 03:25:38.299 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-01-29 03:25:38.299 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:25:38.299 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:25:38.299 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:25:38.299 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETRXGAIN
2026-01-29 03:25:38.299 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:25:38.299 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:25:38.299 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:25:38.299 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:25:38.300 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:25:38.300 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:25:38.300 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:25:38.300 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:25:38.300 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:25:38.300 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:25:38.301 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:25:38.301 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:25:38.301 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:25:38.301 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:25:38.301 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:25:38.301 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:25:38.301 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:25:38.301 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:25:38.301 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:25:38.301 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 03:25:38.301 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:25:38.301 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:25:38.301 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:25:38.301 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:25:38.301 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 03:25:38.301 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 03:25:38.301 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:25:38.301 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.28.20:5700) Recv POWEROFF cmd
2026-01-29 03:25:38.301 [INFO] ctrl_if_trx.py:117 (BTS@172.18.28.20:5700) Stopping transceiver...
2026-01-29 03:25:38.301 [INFO] transceiver.py:246 Stopping clock generator
2026-01-29 03:25:38.301 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 03:25:43.304 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.28.20:5700) Recv POWEROFF cmd
2026-01-29 03:25:43.304 [INFO] ctrl_if_trx.py:117 (BTS@172.18.28.20:5700) Stopping transceiver...
2026-01-29 03:25:43.306 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 03:25:43.308 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 03:25:43.308 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 03:25:43.308 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 03:25:43.318 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 03:25:43.320 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.28.20:5700) Recv SETFORMAT cmd
2026-01-29 03:25:43.320 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.28.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:25:43.320 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.28.20:5700) Recv SETFORMAT cmd
2026-01-29 03:25:43.321 [INFO] ctrl_if_trx.py:201 (BTS@172.18.28.20:5700) TRXD header version 1 -> 1
2026-01-29 03:25:43.324 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.28.20:5700/1) Recv RXTUNE cmd
2026-01-29 03:25:43.325 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.28.20:5700/1) Recv TXTUNE cmd
2026-01-29 03:25:43.325 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.28.20:5700/1) Recv SETFORMAT cmd
2026-01-29 03:25:43.325 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.28.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:25:43.326 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 03:25:43.326 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.28.20:5700/1) Recv NOMTXPOWER cmd
2026-01-29 03:25:43.327 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.28.20:5700/1) Recv SETFORMAT cmd
2026-01-29 03:25:43.327 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.28.20:5700/1) TRXD header version 1 -> 1
2026-01-29 03:25:43.328 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.28.20:5700/2) Recv RXTUNE cmd
2026-01-29 03:25:43.328 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.28.20:5700/2) Recv TXTUNE cmd
2026-01-29 03:25:43.329 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.28.20:5700/2) Recv SETFORMAT cmd
2026-01-29 03:25:43.329 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.28.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:25:43.329 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 03:25:43.329 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.28.20:5700/2) Recv NOMTXPOWER cmd
2026-01-29 03:25:43.330 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.28.20:5700/2) Recv SETFORMAT cmd
2026-01-29 03:25:43.330 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.28.20:5700/2) TRXD header version 1 -> 1
2026-01-29 03:25:43.331 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.28.20:5700/3) Recv RXTUNE cmd
2026-01-29 03:25:43.331 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.28.20:5700/3) Recv TXTUNE cmd
2026-01-29 03:25:43.331 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.28.20:5700/3) Recv SETFORMAT cmd
2026-01-29 03:25:43.331 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.28.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:25:43.331 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 03:25:43.332 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.28.20:5700/3) Recv NOMTXPOWER cmd
2026-01-29 03:25:43.332 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.28.20:5700/3) Recv SETFORMAT cmd
2026-01-29 03:25:43.332 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.28.20:5700/3) TRXD header version 1 -> 1
2026-01-29 03:25:43.334 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.28.20:5700) Recv RXTUNE cmd
2026-01-29 03:25:43.334 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETTSC
2026-01-29 03:25:43.334 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETTSC
2026-01-29 03:25:43.334 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETTSC
2026-01-29 03:25:43.334 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.28.20:5700) Recv TXTUNE cmd
2026-01-29 03:25:43.334 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETRXGAIN
2026-01-29 03:25:43.335 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETRXGAIN
2026-01-29 03:25:43.335 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETRXGAIN
2026-01-29 03:25:43.335 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETTSC
2026-01-29 03:25:43.335 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:25:43.335 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:25:43.335 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:25:43.335 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.28.20:5700) Recv NOMTXPOWER cmd
2026-01-29 03:25:43.335 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:25:43.335 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:25:43.335 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:25:43.335 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.28.20:5700) Recv POWERON CMD
2026-01-29 03:25:43.335 [INFO] ctrl_if_trx.py:109 (BTS@172.18.28.20:5700) Starting transceiver...
2026-01-29 03:25:43.335 [INFO] transceiver.py:243 Starting clock generator
2026-01-29 03:25:43.335 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-01-29 03:25:43.335 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:25:43.335 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:25:43.335 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:25:43.335 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETRXGAIN
2026-01-29 03:25:43.336 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:25:43.336 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:25:43.336 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:25:43.336 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:25:43.336 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:25:43.336 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:25:43.336 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:25:43.336 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:25:43.336 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:25:43.336 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:25:43.336 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:25:43.336 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:25:43.336 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:25:43.336 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:25:43.336 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:25:43.336 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:25:43.336 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:25:43.336 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:25:43.336 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:25:43.336 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:25:43.336 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:25:43.336 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:25:43.336 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:25:43.340 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-01-29 03:25:43.823 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-01-29 03:25:43.872 [DEBUG] fake_trx.py:278 (BTS@172.18.28.20:5700) Recv FAKE_TOA cmd
2026-01-29 03:25:43.873 [DEBUG] fake_trx.py:297 (BTS@172.18.28.20:5700) Recv FAKE_RSSI cmd
2026-01-29 03:25:43.876 [DEBUG] fake_trx.py:322 (BTS@172.18.28.20:5700) Recv FAKE_CI cmd
2026-01-29 03:25:43.877 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:25:43.879 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 03:25:43.879 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 03:25:43.879 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 03:25:43.880 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 03:25:43.880 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 03:25:43.880 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 03:25:43.880 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.28.22:6700) Recv POWERON CMD
2026-01-29 03:25:43.881 [INFO] ctrl_if_trx.py:109 (MS@172.18.28.22:6700) Starting transceiver...
2026-01-29 03:25:44.298 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-01-29 03:25:44.339 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:25:44.340 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 03:25:44.341 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:25:44.344 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:25:44.776 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-01-29 03:25:45.254 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-01-29 03:25:45.340 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 03:25:45.341 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:25:45.342 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:25:45.345 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:25:45.731 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-01-29 03:25:46.209 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-01-29 03:25:46.341 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 03:25:46.341 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:25:46.343 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:25:46.347 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:25:46.687 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-01-29 03:25:47.165 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-01-29 03:25:47.342 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 03:25:47.342 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:25:47.343 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:25:47.348 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:25:47.643 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-01-29 03:25:48.121 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-01-29 03:25:48.342 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 03:25:48.343 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:25:48.344 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:25:48.348 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:25:48.598 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-01-29 03:25:49.077 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-01-29 03:25:49.574 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-01-29 03:25:50.052 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-01-29 03:25:50.529 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-01-29 03:25:51.007 [DEBUG] clck_gen.py:113 IND CLOCK 1632
2026-01-29 03:25:51.485 [DEBUG] clck_gen.py:113 IND CLOCK 1734
2026-01-29 03:25:51.963 [DEBUG] clck_gen.py:113 IND CLOCK 1836
2026-01-29 03:25:52.441 [DEBUG] clck_gen.py:113 IND CLOCK 1938
2026-01-29 03:25:52.918 [DEBUG] clck_gen.py:113 IND CLOCK 2040
2026-01-29 03:25:53.396 [DEBUG] clck_gen.py:113 IND CLOCK 2142
2026-01-29 03:25:53.874 [DEBUG] clck_gen.py:113 IND CLOCK 2244
2026-01-29 03:25:53.919 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 03:25:53.920 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 03:25:53.923 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 03:25:53.924 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:25:53.924 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:25:53.924 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:25:53.927 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 03:25:53.927 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 03:25:53.927 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 03:25:53.927 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 03:25:53.927 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.28.20:5700) Recv POWEROFF cmd
2026-01-29 03:25:53.927 [INFO] ctrl_if_trx.py:117 (BTS@172.18.28.20:5700) Stopping transceiver...
2026-01-29 03:25:53.927 [INFO] transceiver.py:246 Stopping clock generator
2026-01-29 03:25:53.927 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=2257 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:25:53.927 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=2257 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:25:53.927 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=2257 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:25:53.927 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=2257 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:25:53.927 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=2257 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:25:53.927 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=2257 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:25:53.927 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=2257 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:25:58.930 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.28.20:5700) Recv POWEROFF cmd
2026-01-29 03:25:58.930 [INFO] ctrl_if_trx.py:117 (BTS@172.18.28.20:5700) Stopping transceiver...
2026-01-29 03:25:58.930 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 03:25:58.930 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 03:25:58.930 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 03:25:58.930 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 03:25:58.933 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 03:25:58.934 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.28.20:5700) Recv SETFORMAT cmd
2026-01-29 03:25:58.934 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.28.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:25:58.934 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.28.20:5700) Recv SETFORMAT cmd
2026-01-29 03:25:58.934 [INFO] ctrl_if_trx.py:201 (BTS@172.18.28.20:5700) TRXD header version 1 -> 1
2026-01-29 03:25:58.936 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.28.20:5700/1) Recv RXTUNE cmd
2026-01-29 03:25:58.936 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.28.20:5700/1) Recv TXTUNE cmd
2026-01-29 03:25:58.936 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.28.20:5700/1) Recv SETFORMAT cmd
2026-01-29 03:25:58.936 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.28.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:25:58.937 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 03:25:58.937 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.28.20:5700/1) Recv NOMTXPOWER cmd
2026-01-29 03:25:58.937 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.28.20:5700/1) Recv SETFORMAT cmd
2026-01-29 03:25:58.937 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.28.20:5700/1) TRXD header version 1 -> 1
2026-01-29 03:25:58.939 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.28.20:5700/2) Recv RXTUNE cmd
2026-01-29 03:25:58.939 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.28.20:5700/2) Recv TXTUNE cmd
2026-01-29 03:25:58.939 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.28.20:5700/2) Recv SETFORMAT cmd
2026-01-29 03:25:58.939 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.28.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:25:58.940 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 03:25:58.940 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.28.20:5700/2) Recv NOMTXPOWER cmd
2026-01-29 03:25:58.940 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.28.20:5700/2) Recv SETFORMAT cmd
2026-01-29 03:25:58.940 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.28.20:5700/2) TRXD header version 1 -> 1
2026-01-29 03:25:58.941 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.28.20:5700/3) Recv RXTUNE cmd
2026-01-29 03:25:58.941 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.28.20:5700/3) Recv TXTUNE cmd
2026-01-29 03:25:58.941 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.28.20:5700/3) Recv SETFORMAT cmd
2026-01-29 03:25:58.941 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.28.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:25:58.941 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 03:25:58.942 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.28.20:5700/3) Recv NOMTXPOWER cmd
2026-01-29 03:25:58.942 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.28.20:5700/3) Recv SETFORMAT cmd
2026-01-29 03:25:58.942 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.28.20:5700/3) TRXD header version 1 -> 1
2026-01-29 03:25:58.944 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.28.20:5700) Recv RXTUNE cmd
2026-01-29 03:25:58.945 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETTSC
2026-01-29 03:25:58.945 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.28.20:5700) Recv TXTUNE cmd
2026-01-29 03:25:58.945 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETTSC
2026-01-29 03:25:58.945 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETTSC
2026-01-29 03:25:58.945 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETTSC
2026-01-29 03:25:58.945 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETRXGAIN
2026-01-29 03:25:58.945 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETRXGAIN
2026-01-29 03:25:58.945 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.28.20:5700) Recv NOMTXPOWER cmd
2026-01-29 03:25:58.945 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:25:58.945 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETRXGAIN
2026-01-29 03:25:58.945 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.28.20:5700) Recv POWERON CMD
2026-01-29 03:25:58.945 [INFO] ctrl_if_trx.py:109 (BTS@172.18.28.20:5700) Starting transceiver...
2026-01-29 03:25:58.945 [INFO] transceiver.py:243 Starting clock generator
2026-01-29 03:25:58.945 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-01-29 03:25:58.946 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:25:58.946 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:25:58.946 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:25:58.946 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 03:25:58.947 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:25:58.947 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:25:58.947 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:25:58.947 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.28.20:5700) Recv POWEROFF cmd
2026-01-29 03:25:58.947 [INFO] ctrl_if_trx.py:117 (BTS@172.18.28.20:5700) Stopping transceiver...
2026-01-29 03:25:58.947 [INFO] transceiver.py:246 Stopping clock generator
2026-01-29 03:25:58.947 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:25:58.947 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:25:58.947 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:26:03.950 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.28.20:5700) Recv POWEROFF cmd
2026-01-29 03:26:03.950 [INFO] ctrl_if_trx.py:117 (BTS@172.18.28.20:5700) Stopping transceiver...
2026-01-29 03:26:03.952 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 03:26:03.953 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 03:26:03.954 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 03:26:03.954 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 03:26:03.962 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 03:26:03.963 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.28.20:5700) Recv SETFORMAT cmd
2026-01-29 03:26:03.963 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.28.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:26:03.964 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.28.20:5700) Recv SETFORMAT cmd
2026-01-29 03:26:03.964 [INFO] ctrl_if_trx.py:201 (BTS@172.18.28.20:5700) TRXD header version 1 -> 1
2026-01-29 03:26:03.967 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.28.20:5700/1) Recv RXTUNE cmd
2026-01-29 03:26:03.968 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.28.20:5700/1) Recv TXTUNE cmd
2026-01-29 03:26:03.968 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.28.20:5700/1) Recv SETFORMAT cmd
2026-01-29 03:26:03.968 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.28.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:26:03.969 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 03:26:03.969 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.28.20:5700/1) Recv NOMTXPOWER cmd
2026-01-29 03:26:03.970 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.28.20:5700/1) Recv SETFORMAT cmd
2026-01-29 03:26:03.970 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.28.20:5700/1) TRXD header version 1 -> 1
2026-01-29 03:26:03.970 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.28.20:5700/2) Recv RXTUNE cmd
2026-01-29 03:26:03.971 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.28.20:5700/2) Recv TXTUNE cmd
2026-01-29 03:26:03.971 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.28.20:5700/2) Recv SETFORMAT cmd
2026-01-29 03:26:03.971 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.28.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:26:03.971 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 03:26:03.972 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.28.20:5700/2) Recv NOMTXPOWER cmd
2026-01-29 03:26:03.972 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.28.20:5700/2) Recv SETFORMAT cmd
2026-01-29 03:26:03.972 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.28.20:5700/2) TRXD header version 1 -> 1
2026-01-29 03:26:03.973 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.28.20:5700/3) Recv RXTUNE cmd
2026-01-29 03:26:03.973 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.28.20:5700/3) Recv TXTUNE cmd
2026-01-29 03:26:03.973 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.28.20:5700/3) Recv SETFORMAT cmd
2026-01-29 03:26:03.973 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.28.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:26:03.973 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 03:26:03.974 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.28.20:5700/3) Recv NOMTXPOWER cmd
2026-01-29 03:26:03.974 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.28.20:5700/3) Recv SETFORMAT cmd
2026-01-29 03:26:03.974 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.28.20:5700/3) TRXD header version 1 -> 1
2026-01-29 03:26:03.976 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.28.20:5700) Recv RXTUNE cmd
2026-01-29 03:26:03.976 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETTSC
2026-01-29 03:26:03.976 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETTSC
2026-01-29 03:26:03.976 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETTSC
2026-01-29 03:26:03.976 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.28.20:5700) Recv TXTUNE cmd
2026-01-29 03:26:03.977 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETRXGAIN
2026-01-29 03:26:03.977 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETRXGAIN
2026-01-29 03:26:03.977 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETRXGAIN
2026-01-29 03:26:03.977 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETTSC
2026-01-29 03:26:03.977 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:26:03.977 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:26:03.977 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:26:03.977 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.28.20:5700) Recv NOMTXPOWER cmd
2026-01-29 03:26:03.977 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:26:03.977 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:26:03.977 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:26:03.977 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.28.20:5700) Recv POWERON CMD
2026-01-29 03:26:03.977 [INFO] ctrl_if_trx.py:109 (BTS@172.18.28.20:5700) Starting transceiver...
2026-01-29 03:26:03.977 [INFO] transceiver.py:243 Starting clock generator
2026-01-29 03:26:03.977 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-01-29 03:26:03.977 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:26:03.977 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:26:03.977 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:26:03.977 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETRXGAIN
2026-01-29 03:26:03.977 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:26:03.977 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:26:03.977 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:26:03.977 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:26:03.978 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:26:03.978 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:26:03.978 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:26:03.978 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:26:03.978 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:26:03.978 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:26:03.978 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:26:03.978 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:26:03.978 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:26:03.978 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:26:03.978 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:26:03.978 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:26:03.978 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:26:03.978 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:26:03.978 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:26:03.978 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:26:03.978 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:26:03.978 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:26:03.978 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:26:03.982 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-01-29 03:26:04.465 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-01-29 03:26:04.510 [DEBUG] fake_trx.py:278 (BTS@172.18.28.20:5700) Recv FAKE_TOA cmd
2026-01-29 03:26:04.512 [DEBUG] fake_trx.py:297 (BTS@172.18.28.20:5700) Recv FAKE_RSSI cmd
2026-01-29 03:26:04.514 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:26:04.515 [DEBUG] fake_trx.py:322 (BTS@172.18.28.20:5700) Recv FAKE_CI cmd
2026-01-29 03:26:04.518 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 03:26:04.518 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 03:26:04.519 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 03:26:04.519 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 03:26:04.520 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 03:26:04.521 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 03:26:04.521 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.28.22:6700) Recv POWERON CMD
2026-01-29 03:26:04.521 [INFO] ctrl_if_trx.py:109 (MS@172.18.28.22:6700) Starting transceiver...
2026-01-29 03:26:04.943 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-01-29 03:26:04.980 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 03:26:04.980 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:26:04.981 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:26:04.984 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:26:05.421 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-01-29 03:26:05.899 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-01-29 03:26:05.981 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 03:26:05.981 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:26:05.982 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:26:05.985 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:26:06.377 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-01-29 03:26:06.854 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-01-29 03:26:06.982 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 03:26:06.982 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:26:06.982 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:26:06.986 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:26:07.332 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-01-29 03:26:07.810 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-01-29 03:26:07.982 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 03:26:07.983 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:26:07.983 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:26:07.987 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:26:08.288 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-01-29 03:26:08.765 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-01-29 03:26:08.983 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 03:26:08.983 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:26:08.984 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:26:08.987 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:26:09.239 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-01-29 03:26:09.716 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-01-29 03:26:10.194 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-01-29 03:26:10.671 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-01-29 03:26:11.149 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-01-29 03:26:11.627 [DEBUG] clck_gen.py:113 IND CLOCK 1632
2026-01-29 03:26:12.105 [DEBUG] clck_gen.py:113 IND CLOCK 1734
2026-01-29 03:26:12.582 [DEBUG] clck_gen.py:113 IND CLOCK 1836
2026-01-29 03:26:13.060 [DEBUG] clck_gen.py:113 IND CLOCK 1938
2026-01-29 03:26:13.538 [DEBUG] clck_gen.py:113 IND CLOCK 2040
2026-01-29 03:26:14.016 [DEBUG] clck_gen.py:113 IND CLOCK 2142
2026-01-29 03:26:14.494 [DEBUG] clck_gen.py:113 IND CLOCK 2244
2026-01-29 03:26:14.971 [DEBUG] clck_gen.py:113 IND CLOCK 2346
2026-01-29 03:26:15.449 [DEBUG] clck_gen.py:113 IND CLOCK 2448
2026-01-29 03:26:15.560 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 03:26:15.560 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 03:26:15.564 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 03:26:15.565 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:26:15.565 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:26:15.565 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:26:15.566 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 03:26:15.566 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 03:26:15.566 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 03:26:15.566 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.28.20:5700) Recv POWEROFF cmd
2026-01-29 03:26:15.566 [INFO] ctrl_if_trx.py:117 (BTS@172.18.28.20:5700) Stopping transceiver...
2026-01-29 03:26:15.566 [INFO] transceiver.py:246 Stopping clock generator
2026-01-29 03:26:15.566 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 03:26:15.566 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=2475 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:26:15.566 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=2475 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:26:15.566 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=2475 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:26:15.566 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=2475 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:26:20.567 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.28.20:5700) Recv POWEROFF cmd
2026-01-29 03:26:20.567 [INFO] ctrl_if_trx.py:117 (BTS@172.18.28.20:5700) Stopping transceiver...
2026-01-29 03:26:20.569 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 03:26:20.570 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 03:26:20.571 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 03:26:20.571 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 03:26:20.578 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 03:26:20.578 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.28.20:5700) Recv SETFORMAT cmd
2026-01-29 03:26:20.578 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.28.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:26:20.578 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.28.20:5700) Recv SETFORMAT cmd
2026-01-29 03:26:20.578 [INFO] ctrl_if_trx.py:201 (BTS@172.18.28.20:5700) TRXD header version 1 -> 1
2026-01-29 03:26:20.579 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.28.20:5700/1) Recv RXTUNE cmd
2026-01-29 03:26:20.580 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.28.20:5700/1) Recv TXTUNE cmd
2026-01-29 03:26:20.580 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.28.20:5700/1) Recv SETFORMAT cmd
2026-01-29 03:26:20.580 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.28.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:26:20.581 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 03:26:20.581 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.28.20:5700/1) Recv NOMTXPOWER cmd
2026-01-29 03:26:20.581 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.28.20:5700/1) Recv SETFORMAT cmd
2026-01-29 03:26:20.581 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.28.20:5700/1) TRXD header version 1 -> 1
2026-01-29 03:26:20.583 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.28.20:5700/2) Recv RXTUNE cmd
2026-01-29 03:26:20.583 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.28.20:5700/2) Recv TXTUNE cmd
2026-01-29 03:26:20.584 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.28.20:5700/2) Recv SETFORMAT cmd
2026-01-29 03:26:20.584 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.28.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:26:20.584 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 03:26:20.584 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.28.20:5700/2) Recv NOMTXPOWER cmd
2026-01-29 03:26:20.584 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.28.20:5700/2) Recv SETFORMAT cmd
2026-01-29 03:26:20.584 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.28.20:5700/2) TRXD header version 1 -> 1
2026-01-29 03:26:20.587 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.28.20:5700/3) Recv RXTUNE cmd
2026-01-29 03:26:20.587 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.28.20:5700/3) Recv TXTUNE cmd
2026-01-29 03:26:20.587 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.28.20:5700/3) Recv SETFORMAT cmd
2026-01-29 03:26:20.587 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.28.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:26:20.587 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 03:26:20.587 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.28.20:5700/3) Recv NOMTXPOWER cmd
2026-01-29 03:26:20.587 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.28.20:5700/3) Recv SETFORMAT cmd
2026-01-29 03:26:20.587 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.28.20:5700/3) TRXD header version 1 -> 1
2026-01-29 03:26:20.591 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.28.20:5700) Recv RXTUNE cmd
2026-01-29 03:26:20.591 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETTSC
2026-01-29 03:26:20.591 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETTSC
2026-01-29 03:26:20.591 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETTSC
2026-01-29 03:26:20.591 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.28.20:5700) Recv TXTUNE cmd
2026-01-29 03:26:20.591 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETRXGAIN
2026-01-29 03:26:20.592 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETRXGAIN
2026-01-29 03:26:20.592 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETRXGAIN
2026-01-29 03:26:20.592 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETTSC
2026-01-29 03:26:20.592 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:26:20.592 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:26:20.592 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:26:20.592 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.28.20:5700) Recv NOMTXPOWER cmd
2026-01-29 03:26:20.592 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:26:20.592 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:26:20.592 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:26:20.592 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.28.20:5700) Recv POWERON CMD
2026-01-29 03:26:20.592 [INFO] ctrl_if_trx.py:109 (BTS@172.18.28.20:5700) Starting transceiver...
2026-01-29 03:26:20.592 [INFO] transceiver.py:243 Starting clock generator
2026-01-29 03:26:20.592 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-01-29 03:26:20.592 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:26:20.592 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:26:20.592 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:26:20.593 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETRXGAIN
2026-01-29 03:26:20.593 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:26:20.593 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:26:20.593 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:26:20.593 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:26:20.593 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:26:20.593 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:26:20.593 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:26:20.593 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:26:20.594 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:26:20.594 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:26:20.594 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:26:20.594 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:26:20.594 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:26:20.594 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:26:20.594 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:26:20.594 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:26:20.595 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:26:20.595 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:26:20.595 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:26:20.595 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 03:26:20.595 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:26:20.595 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:26:20.595 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:26:20.595 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:26:20.595 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 03:26:20.595 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 03:26:20.595 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 03:26:20.595 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.28.20:5700) Recv POWEROFF cmd
2026-01-29 03:26:20.595 [INFO] ctrl_if_trx.py:117 (BTS@172.18.28.20:5700) Stopping transceiver...
2026-01-29 03:26:20.595 [INFO] transceiver.py:246 Stopping clock generator
2026-01-29 03:26:25.598 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.28.20:5700) Recv POWEROFF cmd
2026-01-29 03:26:25.598 [INFO] ctrl_if_trx.py:117 (BTS@172.18.28.20:5700) Stopping transceiver...
2026-01-29 03:26:25.600 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 03:26:25.601 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 03:26:25.602 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 03:26:25.602 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 03:26:25.612 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 03:26:25.614 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.28.20:5700) Recv SETFORMAT cmd
2026-01-29 03:26:25.614 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.28.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:26:25.614 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.28.20:5700) Recv SETFORMAT cmd
2026-01-29 03:26:25.615 [INFO] ctrl_if_trx.py:201 (BTS@172.18.28.20:5700) TRXD header version 1 -> 1
2026-01-29 03:26:25.620 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.28.20:5700/1) Recv RXTUNE cmd
2026-01-29 03:26:25.620 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.28.20:5700/1) Recv TXTUNE cmd
2026-01-29 03:26:25.621 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.28.20:5700/1) Recv SETFORMAT cmd
2026-01-29 03:26:25.621 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.28.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:26:25.621 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 03:26:25.622 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.28.20:5700/1) Recv NOMTXPOWER cmd
2026-01-29 03:26:25.622 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.28.20:5700/1) Recv SETFORMAT cmd
2026-01-29 03:26:25.622 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.28.20:5700/1) TRXD header version 1 -> 1
2026-01-29 03:26:25.624 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.28.20:5700/2) Recv RXTUNE cmd
2026-01-29 03:26:25.624 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.28.20:5700/2) Recv TXTUNE cmd
2026-01-29 03:26:25.624 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.28.20:5700/2) Recv SETFORMAT cmd
2026-01-29 03:26:25.624 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.28.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:26:25.624 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 03:26:25.624 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.28.20:5700/2) Recv NOMTXPOWER cmd
2026-01-29 03:26:25.625 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.28.20:5700/2) Recv SETFORMAT cmd
2026-01-29 03:26:25.625 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.28.20:5700/2) TRXD header version 1 -> 1
2026-01-29 03:26:25.627 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.28.20:5700/3) Recv RXTUNE cmd
2026-01-29 03:26:25.627 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.28.20:5700/3) Recv TXTUNE cmd
2026-01-29 03:26:25.627 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.28.20:5700/3) Recv SETFORMAT cmd
2026-01-29 03:26:25.627 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.28.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:26:25.627 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 03:26:25.627 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.28.20:5700/3) Recv NOMTXPOWER cmd
2026-01-29 03:26:25.628 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.28.20:5700/3) Recv SETFORMAT cmd
2026-01-29 03:26:25.628 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.28.20:5700/3) TRXD header version 1 -> 1
2026-01-29 03:26:25.631 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.28.20:5700) Recv RXTUNE cmd
2026-01-29 03:26:25.631 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETTSC
2026-01-29 03:26:25.631 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETTSC
2026-01-29 03:26:25.631 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETTSC
2026-01-29 03:26:25.631 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.28.20:5700) Recv TXTUNE cmd
2026-01-29 03:26:25.631 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETRXGAIN
2026-01-29 03:26:25.631 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETRXGAIN
2026-01-29 03:26:25.631 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETRXGAIN
2026-01-29 03:26:25.631 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETTSC
2026-01-29 03:26:25.631 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:26:25.631 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:26:25.631 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.28.20:5700) Recv NOMTXPOWER cmd
2026-01-29 03:26:25.631 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:26:25.631 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:26:25.631 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:26:25.631 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.28.20:5700) Recv POWERON CMD
2026-01-29 03:26:25.631 [INFO] ctrl_if_trx.py:109 (BTS@172.18.28.20:5700) Starting transceiver...
2026-01-29 03:26:25.631 [INFO] transceiver.py:243 Starting clock generator
2026-01-29 03:26:25.632 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-01-29 03:26:25.632 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:26:25.632 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:26:25.632 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:26:25.632 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETRXGAIN
2026-01-29 03:26:25.632 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:26:25.632 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:26:25.632 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:26:25.632 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:26:25.632 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:26:25.632 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:26:25.632 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:26:25.632 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:26:25.632 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:26:25.632 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:26:25.632 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:26:25.632 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:26:25.632 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:26:25.632 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:26:25.632 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:26:25.632 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:26:25.632 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:26:25.632 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:26:25.632 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:26:25.632 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:26:25.632 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:26:25.632 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:26:25.632 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:26:25.632 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:26:25.636 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-01-29 03:26:26.120 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-01-29 03:26:26.165 [DEBUG] fake_trx.py:278 (BTS@172.18.28.20:5700) Recv FAKE_TOA cmd
2026-01-29 03:26:26.168 [DEBUG] fake_trx.py:297 (BTS@172.18.28.20:5700) Recv FAKE_RSSI cmd
2026-01-29 03:26:26.169 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:26:26.170 [DEBUG] fake_trx.py:322 (BTS@172.18.28.20:5700) Recv FAKE_CI cmd
2026-01-29 03:26:26.173 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 03:26:26.173 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 03:26:26.174 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 03:26:26.174 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 03:26:26.175 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 03:26:26.175 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 03:26:26.175 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.28.22:6700) Recv POWERON CMD
2026-01-29 03:26:26.175 [INFO] ctrl_if_trx.py:109 (MS@172.18.28.22:6700) Starting transceiver...
2026-01-29 03:26:26.598 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-01-29 03:26:26.634 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:26:26.634 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 03:26:26.634 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:26:26.636 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:26:27.076 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-01-29 03:26:27.554 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-01-29 03:26:27.635 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:26:27.635 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 03:26:27.635 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:26:27.637 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:26:28.031 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-01-29 03:26:28.509 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-01-29 03:26:28.636 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 03:26:28.637 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:26:28.637 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:26:28.638 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:26:28.987 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-01-29 03:26:29.465 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-01-29 03:26:29.638 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:26:29.638 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 03:26:29.638 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:26:29.640 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:26:29.942 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-01-29 03:26:30.420 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-01-29 03:26:30.639 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 03:26:30.640 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:26:30.640 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:26:30.641 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:26:30.897 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-01-29 03:26:31.375 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-01-29 03:26:31.853 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-01-29 03:26:32.331 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-01-29 03:26:32.808 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-01-29 03:26:33.285 [DEBUG] clck_gen.py:113 IND CLOCK 1632
2026-01-29 03:26:33.763 [DEBUG] clck_gen.py:113 IND CLOCK 1734
2026-01-29 03:26:34.241 [DEBUG] clck_gen.py:113 IND CLOCK 1836
2026-01-29 03:26:34.719 [DEBUG] clck_gen.py:113 IND CLOCK 1938
2026-01-29 03:26:35.196 [DEBUG] clck_gen.py:113 IND CLOCK 2040
2026-01-29 03:26:35.674 [DEBUG] clck_gen.py:113 IND CLOCK 2142
2026-01-29 03:26:36.152 [DEBUG] clck_gen.py:113 IND CLOCK 2244
2026-01-29 03:26:36.630 [DEBUG] clck_gen.py:113 IND CLOCK 2346
2026-01-29 03:26:37.108 [DEBUG] clck_gen.py:113 IND CLOCK 2448
2026-01-29 03:26:37.586 [DEBUG] clck_gen.py:113 IND CLOCK 2550
2026-01-29 03:26:38.064 [DEBUG] clck_gen.py:113 IND CLOCK 2652
2026-01-29 03:26:38.541 [DEBUG] clck_gen.py:113 IND CLOCK 2754
2026-01-29 03:26:39.019 [DEBUG] clck_gen.py:113 IND CLOCK 2856
2026-01-29 03:26:39.497 [DEBUG] clck_gen.py:113 IND CLOCK 2958
2026-01-29 03:26:39.974 [DEBUG] clck_gen.py:113 IND CLOCK 3060
2026-01-29 03:26:40.452 [DEBUG] clck_gen.py:113 IND CLOCK 3162
2026-01-29 03:26:40.930 [DEBUG] clck_gen.py:113 IND CLOCK 3264
2026-01-29 03:26:41.407 [DEBUG] clck_gen.py:113 IND CLOCK 3366
2026-01-29 03:26:41.885 [DEBUG] clck_gen.py:113 IND CLOCK 3468
2026-01-29 03:26:42.363 [DEBUG] clck_gen.py:113 IND CLOCK 3570
2026-01-29 03:26:42.841 [DEBUG] clck_gen.py:113 IND CLOCK 3672
2026-01-29 03:26:43.318 [DEBUG] clck_gen.py:113 IND CLOCK 3774
2026-01-29 03:26:43.797 [DEBUG] clck_gen.py:113 IND CLOCK 3876
2026-01-29 03:26:44.274 [DEBUG] clck_gen.py:113 IND CLOCK 3978
2026-01-29 03:26:44.752 [DEBUG] clck_gen.py:113 IND CLOCK 4080
2026-01-29 03:26:45.229 [DEBUG] clck_gen.py:113 IND CLOCK 4182
2026-01-29 03:26:45.707 [DEBUG] clck_gen.py:113 IND CLOCK 4284
2026-01-29 03:26:46.185 [DEBUG] clck_gen.py:113 IND CLOCK 4386
2026-01-29 03:26:46.222 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 03:26:46.222 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 03:26:46.223 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 03:26:46.223 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:26:46.223 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:26:46.223 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:26:46.224 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 03:26:46.224 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 03:26:46.224 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 03:26:46.224 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 03:26:46.224 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.28.20:5700) Recv POWEROFF cmd
2026-01-29 03:26:46.224 [INFO] ctrl_if_trx.py:117 (BTS@172.18.28.20:5700) Stopping transceiver...
2026-01-29 03:26:46.224 [INFO] transceiver.py:246 Stopping clock generator
2026-01-29 03:26:51.227 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.28.20:5700) Recv POWEROFF cmd
2026-01-29 03:26:51.227 [INFO] ctrl_if_trx.py:117 (BTS@172.18.28.20:5700) Stopping transceiver...
2026-01-29 03:26:51.228 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 03:26:51.230 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 03:26:51.231 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 03:26:51.231 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 03:26:51.240 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 03:26:51.241 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.28.20:5700) Recv SETFORMAT cmd
2026-01-29 03:26:51.241 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.28.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:26:51.242 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.28.20:5700) Recv SETFORMAT cmd
2026-01-29 03:26:51.242 [INFO] ctrl_if_trx.py:201 (BTS@172.18.28.20:5700) TRXD header version 1 -> 1
2026-01-29 03:26:51.246 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.28.20:5700/1) Recv RXTUNE cmd
2026-01-29 03:26:51.247 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.28.20:5700/1) Recv TXTUNE cmd
2026-01-29 03:26:51.247 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.28.20:5700/1) Recv SETFORMAT cmd
2026-01-29 03:26:51.247 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.28.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:26:51.248 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 03:26:51.248 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.28.20:5700/1) Recv NOMTXPOWER cmd
2026-01-29 03:26:51.249 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.28.20:5700/1) Recv SETFORMAT cmd
2026-01-29 03:26:51.249 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.28.20:5700/1) TRXD header version 1 -> 1
2026-01-29 03:26:51.250 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.28.20:5700/2) Recv RXTUNE cmd
2026-01-29 03:26:51.250 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.28.20:5700/2) Recv TXTUNE cmd
2026-01-29 03:26:51.251 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.28.20:5700/2) Recv SETFORMAT cmd
2026-01-29 03:26:51.251 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.28.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:26:51.251 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 03:26:51.251 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.28.20:5700/2) Recv NOMTXPOWER cmd
2026-01-29 03:26:51.251 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.28.20:5700/2) Recv SETFORMAT cmd
2026-01-29 03:26:51.251 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.28.20:5700/2) TRXD header version 1 -> 1
2026-01-29 03:26:51.253 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.28.20:5700/3) Recv RXTUNE cmd
2026-01-29 03:26:51.253 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.28.20:5700/3) Recv TXTUNE cmd
2026-01-29 03:26:51.254 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.28.20:5700/3) Recv SETFORMAT cmd
2026-01-29 03:26:51.254 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.28.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:26:51.254 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 03:26:51.254 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.28.20:5700/3) Recv NOMTXPOWER cmd
2026-01-29 03:26:51.254 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.28.20:5700/3) Recv SETFORMAT cmd
2026-01-29 03:26:51.254 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.28.20:5700/3) TRXD header version 1 -> 1
2026-01-29 03:26:51.257 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.28.20:5700) Recv RXTUNE cmd
2026-01-29 03:26:51.257 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETTSC
2026-01-29 03:26:51.257 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETTSC
2026-01-29 03:26:51.257 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.28.20:5700) Recv TXTUNE cmd
2026-01-29 03:26:51.257 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETTSC
2026-01-29 03:26:51.257 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETRXGAIN
2026-01-29 03:26:51.257 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETRXGAIN
2026-01-29 03:26:51.257 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETTSC
2026-01-29 03:26:51.257 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETRXGAIN
2026-01-29 03:26:51.257 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:26:51.257 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:26:51.257 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.28.20:5700) Recv NOMTXPOWER cmd
2026-01-29 03:26:51.257 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:26:51.257 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:26:51.257 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:26:51.257 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.28.20:5700) Recv POWERON CMD
2026-01-29 03:26:51.257 [INFO] ctrl_if_trx.py:109 (BTS@172.18.28.20:5700) Starting transceiver...
2026-01-29 03:26:51.257 [INFO] transceiver.py:243 Starting clock generator
2026-01-29 03:26:51.258 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-01-29 03:26:51.258 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:26:51.258 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:26:51.258 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:26:51.258 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETRXGAIN
2026-01-29 03:26:51.258 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:26:51.258 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:26:51.258 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:26:51.258 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:26:51.259 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:26:51.259 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:26:51.259 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:26:51.259 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:26:51.259 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:26:51.259 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:26:51.259 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:26:51.259 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:26:51.259 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:26:51.259 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:26:51.259 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:26:51.259 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:26:51.259 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:26:51.259 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:26:51.259 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:26:51.259 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 03:26:51.259 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:26:51.259 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:26:51.259 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:26:51.259 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:26:51.259 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 03:26:51.259 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 03:26:51.259 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:26:51.259 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.28.20:5700) Recv POWEROFF cmd
2026-01-29 03:26:51.259 [INFO] ctrl_if_trx.py:117 (BTS@172.18.28.20:5700) Stopping transceiver...
2026-01-29 03:26:51.260 [INFO] transceiver.py:246 Stopping clock generator
2026-01-29 03:26:51.260 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 03:26:56.263 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.28.20:5700) Recv POWEROFF cmd
2026-01-29 03:26:56.263 [INFO] ctrl_if_trx.py:117 (BTS@172.18.28.20:5700) Stopping transceiver...
2026-01-29 03:26:56.264 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 03:26:56.267 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 03:26:56.267 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 03:26:56.267 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 03:26:56.277 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 03:26:56.279 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.28.20:5700) Recv SETFORMAT cmd
2026-01-29 03:26:56.279 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.28.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:26:56.279 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.28.20:5700) Recv SETFORMAT cmd
2026-01-29 03:26:56.279 [INFO] ctrl_if_trx.py:201 (BTS@172.18.28.20:5700) TRXD header version 1 -> 1
2026-01-29 03:26:56.284 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.28.20:5700/1) Recv RXTUNE cmd
2026-01-29 03:26:56.284 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.28.20:5700/1) Recv TXTUNE cmd
2026-01-29 03:26:56.285 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.28.20:5700/1) Recv SETFORMAT cmd
2026-01-29 03:26:56.285 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.28.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:26:56.285 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 03:26:56.285 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.28.20:5700/1) Recv NOMTXPOWER cmd
2026-01-29 03:26:56.285 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.28.20:5700/1) Recv SETFORMAT cmd
2026-01-29 03:26:56.286 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.28.20:5700/1) TRXD header version 1 -> 1
2026-01-29 03:26:56.287 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.28.20:5700/2) Recv RXTUNE cmd
2026-01-29 03:26:56.288 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.28.20:5700/2) Recv TXTUNE cmd
2026-01-29 03:26:56.288 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.28.20:5700/2) Recv SETFORMAT cmd
2026-01-29 03:26:56.288 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.28.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:26:56.288 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 03:26:56.288 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.28.20:5700/2) Recv NOMTXPOWER cmd
2026-01-29 03:26:56.288 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.28.20:5700/2) Recv SETFORMAT cmd
2026-01-29 03:26:56.288 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.28.20:5700/2) TRXD header version 1 -> 1
2026-01-29 03:26:56.290 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.28.20:5700/3) Recv RXTUNE cmd
2026-01-29 03:26:56.291 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.28.20:5700/3) Recv TXTUNE cmd
2026-01-29 03:26:56.291 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.28.20:5700/3) Recv SETFORMAT cmd
2026-01-29 03:26:56.291 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.28.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:26:56.291 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 03:26:56.291 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.28.20:5700/3) Recv NOMTXPOWER cmd
2026-01-29 03:26:56.291 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.28.20:5700/3) Recv SETFORMAT cmd
2026-01-29 03:26:56.291 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.28.20:5700/3) TRXD header version 1 -> 1
2026-01-29 03:26:56.294 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.28.20:5700) Recv RXTUNE cmd
2026-01-29 03:26:56.294 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETTSC
2026-01-29 03:26:56.294 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETTSC
2026-01-29 03:26:56.294 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETTSC
2026-01-29 03:26:56.294 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.28.20:5700) Recv TXTUNE cmd
2026-01-29 03:26:56.295 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETRXGAIN
2026-01-29 03:26:56.295 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETRXGAIN
2026-01-29 03:26:56.295 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETRXGAIN
2026-01-29 03:26:56.295 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETTSC
2026-01-29 03:26:56.295 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:26:56.295 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:26:56.295 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:26:56.295 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.28.20:5700) Recv NOMTXPOWER cmd
2026-01-29 03:26:56.295 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:26:56.295 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:26:56.295 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:26:56.295 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.28.20:5700) Recv POWERON CMD
2026-01-29 03:26:56.295 [INFO] ctrl_if_trx.py:109 (BTS@172.18.28.20:5700) Starting transceiver...
2026-01-29 03:26:56.295 [INFO] transceiver.py:243 Starting clock generator
2026-01-29 03:26:56.295 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-01-29 03:26:56.295 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:26:56.296 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:26:56.296 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:26:56.296 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETRXGAIN
2026-01-29 03:26:56.296 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:26:56.296 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:26:56.296 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:26:56.296 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:26:56.296 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:26:56.296 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:26:56.296 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:26:56.296 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:26:56.296 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:26:56.296 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:26:56.296 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:26:56.296 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:26:56.296 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:26:56.296 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:26:56.297 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:26:56.297 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:26:56.297 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:26:56.297 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:26:56.297 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:26:56.297 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:26:56.297 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:26:56.297 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:26:56.297 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:26:56.300 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-01-29 03:26:56.785 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-01-29 03:26:56.829 [DEBUG] fake_trx.py:278 (BTS@172.18.28.20:5700) Recv FAKE_TOA cmd
2026-01-29 03:26:56.831 [DEBUG] fake_trx.py:297 (BTS@172.18.28.20:5700) Recv FAKE_RSSI cmd
2026-01-29 03:26:56.833 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:26:56.833 [DEBUG] fake_trx.py:322 (BTS@172.18.28.20:5700) Recv FAKE_CI cmd
2026-01-29 03:26:57.262 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-01-29 03:26:57.299 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 03:26:57.300 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:26:57.301 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:26:57.303 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:26:57.740 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-01-29 03:26:58.218 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-01-29 03:26:58.300 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 03:26:58.300 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:26:58.302 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:26:58.305 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:26:58.700 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-01-29 03:26:59.181 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-01-29 03:26:59.301 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 03:26:59.301 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:26:59.303 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:26:59.306 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:26:59.660 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-01-29 03:27:00.141 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-01-29 03:27:00.302 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 03:27:00.303 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:27:00.305 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:27:00.307 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:27:00.622 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-01-29 03:27:01.103 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-01-29 03:27:01.303 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:27:01.304 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 03:27:01.306 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:27:01.308 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:27:01.581 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-01-29 03:27:02.062 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-01-29 03:27:02.544 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-01-29 03:27:03.025 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-01-29 03:27:03.506 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-01-29 03:27:03.987 [DEBUG] clck_gen.py:113 IND CLOCK 1632
2026-01-29 03:27:04.469 [DEBUG] clck_gen.py:113 IND CLOCK 1734
2026-01-29 03:27:04.950 [DEBUG] clck_gen.py:113 IND CLOCK 1836
2026-01-29 03:27:05.429 [DEBUG] clck_gen.py:113 IND CLOCK 1938
2026-01-29 03:27:05.909 [DEBUG] clck_gen.py:113 IND CLOCK 2040
2026-01-29 03:27:06.391 [DEBUG] clck_gen.py:113 IND CLOCK 2142
2026-01-29 03:27:06.841 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 03:27:06.841 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:27:06.841 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:27:06.841 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:27:06.842 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 03:27:06.842 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 03:27:06.842 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 03:27:06.842 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 03:27:06.842 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.28.20:5700) Recv POWEROFF cmd
2026-01-29 03:27:06.842 [INFO] ctrl_if_trx.py:117 (BTS@172.18.28.20:5700) Stopping transceiver...
2026-01-29 03:27:06.842 [INFO] transceiver.py:246 Stopping clock generator
2026-01-29 03:27:11.845 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.28.20:5700) Recv POWEROFF cmd
2026-01-29 03:27:11.845 [INFO] ctrl_if_trx.py:117 (BTS@172.18.28.20:5700) Stopping transceiver...
2026-01-29 03:27:11.846 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 03:27:11.848 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 03:27:11.849 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 03:27:11.849 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 03:27:11.856 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 03:27:11.856 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.28.20:5700) Recv SETFORMAT cmd
2026-01-29 03:27:11.856 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.28.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:27:11.856 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.28.20:5700) Recv SETFORMAT cmd
2026-01-29 03:27:11.857 [INFO] ctrl_if_trx.py:201 (BTS@172.18.28.20:5700) TRXD header version 1 -> 1
2026-01-29 03:27:11.859 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.28.20:5700/1) Recv RXTUNE cmd
2026-01-29 03:27:11.860 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.28.20:5700/1) Recv TXTUNE cmd
2026-01-29 03:27:11.860 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.28.20:5700/1) Recv SETFORMAT cmd
2026-01-29 03:27:11.860 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.28.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:27:11.861 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 03:27:11.861 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.28.20:5700/1) Recv NOMTXPOWER cmd
2026-01-29 03:27:11.862 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.28.20:5700/1) Recv SETFORMAT cmd
2026-01-29 03:27:11.862 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.28.20:5700/1) TRXD header version 1 -> 1
2026-01-29 03:27:11.863 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.28.20:5700/2) Recv RXTUNE cmd
2026-01-29 03:27:11.864 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.28.20:5700/2) Recv TXTUNE cmd
2026-01-29 03:27:11.864 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.28.20:5700/2) Recv SETFORMAT cmd
2026-01-29 03:27:11.864 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.28.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:27:11.865 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 03:27:11.865 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.28.20:5700/2) Recv NOMTXPOWER cmd
2026-01-29 03:27:11.865 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.28.20:5700/2) Recv SETFORMAT cmd
2026-01-29 03:27:11.866 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.28.20:5700/2) TRXD header version 1 -> 1
2026-01-29 03:27:11.867 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.28.20:5700/3) Recv RXTUNE cmd
2026-01-29 03:27:11.867 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.28.20:5700/3) Recv TXTUNE cmd
2026-01-29 03:27:11.867 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.28.20:5700/3) Recv SETFORMAT cmd
2026-01-29 03:27:11.867 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.28.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:27:11.867 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 03:27:11.868 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.28.20:5700/3) Recv NOMTXPOWER cmd
2026-01-29 03:27:11.868 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.28.20:5700/3) Recv SETFORMAT cmd
2026-01-29 03:27:11.868 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.28.20:5700/3) TRXD header version 1 -> 1
2026-01-29 03:27:11.873 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.28.20:5700) Recv RXTUNE cmd
2026-01-29 03:27:11.873 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETTSC
2026-01-29 03:27:11.873 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETTSC
2026-01-29 03:27:11.873 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETTSC
2026-01-29 03:27:11.873 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.28.20:5700) Recv TXTUNE cmd
2026-01-29 03:27:11.873 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETRXGAIN
2026-01-29 03:27:11.873 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETRXGAIN
2026-01-29 03:27:11.873 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETRXGAIN
2026-01-29 03:27:11.873 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETTSC
2026-01-29 03:27:11.873 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:27:11.873 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:27:11.873 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:27:11.873 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.28.20:5700) Recv NOMTXPOWER cmd
2026-01-29 03:27:11.873 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:27:11.873 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:27:11.873 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.28.20:5700) Recv POWERON CMD
2026-01-29 03:27:11.873 [INFO] ctrl_if_trx.py:109 (BTS@172.18.28.20:5700) Starting transceiver...
2026-01-29 03:27:11.873 [INFO] transceiver.py:243 Starting clock generator
2026-01-29 03:27:11.874 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-01-29 03:27:11.874 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:27:11.874 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:27:11.874 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:27:11.874 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETRXGAIN
2026-01-29 03:27:11.874 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:27:11.874 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:27:11.874 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:27:11.874 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:27:11.874 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:27:11.874 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:27:11.874 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:27:11.874 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:27:11.874 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:27:11.874 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:27:11.874 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:27:11.874 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:27:11.874 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:27:11.875 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:27:11.875 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:27:11.875 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:27:11.875 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:27:11.875 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:27:11.875 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:27:11.875 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:27:11.875 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:27:11.875 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:27:11.875 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:27:11.876 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 03:27:11.876 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 03:27:11.876 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 03:27:11.876 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:27:11.876 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 03:27:11.876 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.28.20:5700) Recv POWEROFF cmd
2026-01-29 03:27:11.876 [INFO] ctrl_if_trx.py:117 (BTS@172.18.28.20:5700) Stopping transceiver...
2026-01-29 03:27:11.877 [INFO] transceiver.py:246 Stopping clock generator
2026-01-29 03:27:16.880 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.28.20:5700) Recv POWEROFF cmd
2026-01-29 03:27:16.880 [INFO] ctrl_if_trx.py:117 (BTS@172.18.28.20:5700) Stopping transceiver...
2026-01-29 03:27:16.882 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 03:27:16.883 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 03:27:16.884 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 03:27:16.885 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 03:27:16.892 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 03:27:16.893 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.28.20:5700) Recv SETFORMAT cmd
2026-01-29 03:27:16.893 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.28.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:27:16.894 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.28.20:5700) Recv SETFORMAT cmd
2026-01-29 03:27:16.894 [INFO] ctrl_if_trx.py:201 (BTS@172.18.28.20:5700) TRXD header version 1 -> 1
2026-01-29 03:27:16.896 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.28.20:5700/1) Recv RXTUNE cmd
2026-01-29 03:27:16.896 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.28.20:5700/1) Recv TXTUNE cmd
2026-01-29 03:27:16.896 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.28.20:5700/1) Recv SETFORMAT cmd
2026-01-29 03:27:16.897 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.28.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:27:16.897 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 03:27:16.897 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.28.20:5700/1) Recv NOMTXPOWER cmd
2026-01-29 03:27:16.897 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.28.20:5700/1) Recv SETFORMAT cmd
2026-01-29 03:27:16.897 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.28.20:5700/1) TRXD header version 1 -> 1
2026-01-29 03:27:16.900 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.28.20:5700/2) Recv RXTUNE cmd
2026-01-29 03:27:16.900 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.28.20:5700/2) Recv TXTUNE cmd
2026-01-29 03:27:16.900 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.28.20:5700/2) Recv SETFORMAT cmd
2026-01-29 03:27:16.900 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.28.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:27:16.900 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 03:27:16.900 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.28.20:5700/2) Recv NOMTXPOWER cmd
2026-01-29 03:27:16.900 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.28.20:5700/2) Recv SETFORMAT cmd
2026-01-29 03:27:16.900 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.28.20:5700/2) TRXD header version 1 -> 1
2026-01-29 03:27:16.903 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.28.20:5700/3) Recv RXTUNE cmd
2026-01-29 03:27:16.903 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.28.20:5700/3) Recv TXTUNE cmd
2026-01-29 03:27:16.903 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.28.20:5700/3) Recv SETFORMAT cmd
2026-01-29 03:27:16.903 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.28.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:27:16.903 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 03:27:16.903 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.28.20:5700/3) Recv NOMTXPOWER cmd
2026-01-29 03:27:16.904 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.28.20:5700/3) Recv SETFORMAT cmd
2026-01-29 03:27:16.904 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.28.20:5700/3) TRXD header version 1 -> 1
2026-01-29 03:27:16.907 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.28.20:5700) Recv RXTUNE cmd
2026-01-29 03:27:16.907 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETTSC
2026-01-29 03:27:16.907 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETTSC
2026-01-29 03:27:16.907 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETTSC
2026-01-29 03:27:16.907 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.28.20:5700) Recv TXTUNE cmd
2026-01-29 03:27:16.907 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETRXGAIN
2026-01-29 03:27:16.907 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETRXGAIN
2026-01-29 03:27:16.907 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETRXGAIN
2026-01-29 03:27:16.907 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETTSC
2026-01-29 03:27:16.907 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:27:16.907 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:27:16.907 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:27:16.907 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.28.20:5700) Recv NOMTXPOWER cmd
2026-01-29 03:27:16.907 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:27:16.908 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:27:16.908 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:27:16.908 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.28.20:5700) Recv POWERON CMD
2026-01-29 03:27:16.908 [INFO] ctrl_if_trx.py:109 (BTS@172.18.28.20:5700) Starting transceiver...
2026-01-29 03:27:16.908 [INFO] transceiver.py:243 Starting clock generator
2026-01-29 03:27:16.908 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-01-29 03:27:16.908 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:27:16.908 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:27:16.908 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:27:16.908 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETRXGAIN
2026-01-29 03:27:16.908 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:27:16.908 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:27:16.908 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:27:16.908 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:27:16.908 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:27:16.908 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:27:16.908 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:27:16.908 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:27:16.909 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:27:16.909 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:27:16.909 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:27:16.909 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:27:16.909 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:27:16.909 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:27:16.909 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:27:16.909 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:27:16.909 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:27:16.909 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:27:16.909 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:27:16.909 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:27:16.909 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:27:16.909 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:27:16.909 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:27:16.913 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-01-29 03:27:17.397 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-01-29 03:27:17.438 [DEBUG] fake_trx.py:278 (BTS@172.18.28.20:5700) Recv FAKE_TOA cmd
2026-01-29 03:27:17.440 [DEBUG] fake_trx.py:297 (BTS@172.18.28.20:5700) Recv FAKE_RSSI cmd
2026-01-29 03:27:17.442 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:27:17.443 [DEBUG] fake_trx.py:322 (BTS@172.18.28.20:5700) Recv FAKE_CI cmd
2026-01-29 03:27:17.875 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-01-29 03:27:17.912 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 03:27:17.912 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:27:17.914 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:27:17.917 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:27:18.356 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-01-29 03:27:18.839 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-01-29 03:27:18.913 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 03:27:18.914 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:27:18.915 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:27:18.918 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:27:19.320 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-01-29 03:27:19.801 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-01-29 03:27:19.915 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:27:19.915 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 03:27:19.917 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:27:19.919 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:27:20.282 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-01-29 03:27:20.763 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-01-29 03:27:20.916 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 03:27:20.917 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:27:20.918 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:27:20.920 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:27:21.244 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-01-29 03:27:21.725 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-01-29 03:27:21.918 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:27:21.918 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 03:27:21.920 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:27:21.922 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:27:22.207 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-01-29 03:27:22.688 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-01-29 03:27:23.168 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-01-29 03:27:23.649 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-01-29 03:27:24.131 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-01-29 03:27:24.612 [DEBUG] clck_gen.py:113 IND CLOCK 1632
2026-01-29 03:27:25.093 [DEBUG] clck_gen.py:113 IND CLOCK 1734
2026-01-29 03:27:25.574 [DEBUG] clck_gen.py:113 IND CLOCK 1836
2026-01-29 03:27:26.055 [DEBUG] clck_gen.py:113 IND CLOCK 1938
2026-01-29 03:27:26.537 [DEBUG] clck_gen.py:113 IND CLOCK 2040
2026-01-29 03:27:27.018 [DEBUG] clck_gen.py:113 IND CLOCK 2142
2026-01-29 03:27:27.499 [DEBUG] clck_gen.py:113 IND CLOCK 2244
2026-01-29 03:27:27.981 [DEBUG] clck_gen.py:113 IND CLOCK 2346
2026-01-29 03:27:28.461 [DEBUG] clck_gen.py:113 IND CLOCK 2448
2026-01-29 03:27:28.941 [DEBUG] clck_gen.py:113 IND CLOCK 2550
2026-01-29 03:27:29.419 [DEBUG] clck_gen.py:113 IND CLOCK 2652
2026-01-29 03:27:29.456 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 03:27:29.456 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:27:29.456 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:27:29.456 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:27:29.458 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 03:27:29.458 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 03:27:29.458 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 03:27:29.458 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 03:27:29.458 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.28.20:5700) Recv POWEROFF cmd
2026-01-29 03:27:29.458 [INFO] ctrl_if_trx.py:117 (BTS@172.18.28.20:5700) Stopping transceiver...
2026-01-29 03:27:29.458 [INFO] transceiver.py:246 Stopping clock generator
2026-01-29 03:27:29.458 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=2662 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:27:29.458 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=2662 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:27:29.458 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=2662 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:27:29.458 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=2662 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:27:29.458 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=2662 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:27:29.458 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=2662 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:27:29.458 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=2662 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:27:34.458 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.28.20:5700) Recv POWEROFF cmd
2026-01-29 03:27:34.458 [INFO] ctrl_if_trx.py:117 (BTS@172.18.28.20:5700) Stopping transceiver...
2026-01-29 03:27:34.461 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 03:27:34.461 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 03:27:34.461 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 03:27:34.461 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 03:27:34.469 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 03:27:34.469 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.28.20:5700) Recv SETFORMAT cmd
2026-01-29 03:27:34.469 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.28.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:27:34.470 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.28.20:5700) Recv SETFORMAT cmd
2026-01-29 03:27:34.470 [INFO] ctrl_if_trx.py:201 (BTS@172.18.28.20:5700) TRXD header version 1 -> 1
2026-01-29 03:27:34.472 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.28.20:5700/1) Recv RXTUNE cmd
2026-01-29 03:27:34.472 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.28.20:5700/1) Recv TXTUNE cmd
2026-01-29 03:27:34.473 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.28.20:5700/1) Recv SETFORMAT cmd
2026-01-29 03:27:34.473 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.28.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:27:34.473 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 03:27:34.473 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.28.20:5700/1) Recv NOMTXPOWER cmd
2026-01-29 03:27:34.474 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.28.20:5700/1) Recv SETFORMAT cmd
2026-01-29 03:27:34.474 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.28.20:5700/1) TRXD header version 1 -> 1
2026-01-29 03:27:34.476 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.28.20:5700/2) Recv RXTUNE cmd
2026-01-29 03:27:34.476 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.28.20:5700/2) Recv TXTUNE cmd
2026-01-29 03:27:34.476 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.28.20:5700/2) Recv SETFORMAT cmd
2026-01-29 03:27:34.476 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.28.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:27:34.476 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 03:27:34.476 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.28.20:5700/2) Recv NOMTXPOWER cmd
2026-01-29 03:27:34.476 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.28.20:5700/2) Recv SETFORMAT cmd
2026-01-29 03:27:34.476 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.28.20:5700/2) TRXD header version 1 -> 1
2026-01-29 03:27:34.478 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.28.20:5700/3) Recv RXTUNE cmd
2026-01-29 03:27:34.478 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.28.20:5700/3) Recv TXTUNE cmd
2026-01-29 03:27:34.479 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.28.20:5700/3) Recv SETFORMAT cmd
2026-01-29 03:27:34.479 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.28.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:27:34.479 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 03:27:34.479 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.28.20:5700/3) Recv NOMTXPOWER cmd
2026-01-29 03:27:34.479 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.28.20:5700/3) Recv SETFORMAT cmd
2026-01-29 03:27:34.480 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.28.20:5700/3) TRXD header version 1 -> 1
2026-01-29 03:27:34.482 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.28.20:5700) Recv RXTUNE cmd
2026-01-29 03:27:34.482 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETTSC
2026-01-29 03:27:34.482 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETTSC
2026-01-29 03:27:34.482 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.28.20:5700) Recv TXTUNE cmd
2026-01-29 03:27:34.482 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETTSC
2026-01-29 03:27:34.482 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETRXGAIN
2026-01-29 03:27:34.482 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETTSC
2026-01-29 03:27:34.482 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETRXGAIN
2026-01-29 03:27:34.482 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:27:34.482 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETRXGAIN
2026-01-29 03:27:34.482 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.28.20:5700) Recv NOMTXPOWER cmd
2026-01-29 03:27:34.482 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:27:34.482 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:27:34.482 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:27:34.482 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.28.20:5700) Recv POWERON CMD
2026-01-29 03:27:34.482 [INFO] ctrl_if_trx.py:109 (BTS@172.18.28.20:5700) Starting transceiver...
2026-01-29 03:27:34.482 [INFO] transceiver.py:243 Starting clock generator
2026-01-29 03:27:34.483 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-01-29 03:27:34.483 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:27:34.483 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:27:34.483 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:27:34.483 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETRXGAIN
2026-01-29 03:27:34.483 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:27:34.483 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:27:34.483 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:27:34.483 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:27:34.484 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:27:34.484 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:27:34.484 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:27:34.484 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:27:34.484 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:27:34.484 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:27:34.484 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:27:34.484 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:27:34.484 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:27:34.484 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:27:34.484 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:27:34.484 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:27:34.484 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:27:34.484 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 03:27:34.484 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:27:34.485 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:27:34.485 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:27:34.485 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:27:34.485 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:27:34.485 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:27:34.485 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:27:34.485 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 03:27:34.485 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:27:34.485 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.28.20:5700) Recv POWEROFF cmd
2026-01-29 03:27:34.485 [INFO] ctrl_if_trx.py:117 (BTS@172.18.28.20:5700) Stopping transceiver...
2026-01-29 03:27:34.485 [INFO] transceiver.py:246 Stopping clock generator
2026-01-29 03:27:34.485 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 03:27:34.485 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 03:27:39.488 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.28.20:5700) Recv POWEROFF cmd
2026-01-29 03:27:39.488 [INFO] ctrl_if_trx.py:117 (BTS@172.18.28.20:5700) Stopping transceiver...
2026-01-29 03:27:39.489 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 03:27:39.491 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 03:27:39.492 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 03:27:39.492 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 03:27:39.499 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 03:27:39.499 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.28.20:5700) Recv SETFORMAT cmd
2026-01-29 03:27:39.499 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.28.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:27:39.499 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.28.20:5700) Recv SETFORMAT cmd
2026-01-29 03:27:39.499 [INFO] ctrl_if_trx.py:201 (BTS@172.18.28.20:5700) TRXD header version 1 -> 1
2026-01-29 03:27:39.501 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.28.20:5700/1) Recv RXTUNE cmd
2026-01-29 03:27:39.502 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.28.20:5700/1) Recv TXTUNE cmd
2026-01-29 03:27:39.502 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.28.20:5700/1) Recv SETFORMAT cmd
2026-01-29 03:27:39.502 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.28.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:27:39.502 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 03:27:39.502 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.28.20:5700/1) Recv NOMTXPOWER cmd
2026-01-29 03:27:39.502 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.28.20:5700/1) Recv SETFORMAT cmd
2026-01-29 03:27:39.502 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.28.20:5700/1) TRXD header version 1 -> 1
2026-01-29 03:27:39.504 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.28.20:5700/2) Recv RXTUNE cmd
2026-01-29 03:27:39.504 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.28.20:5700/2) Recv TXTUNE cmd
2026-01-29 03:27:39.504 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.28.20:5700/2) Recv SETFORMAT cmd
2026-01-29 03:27:39.504 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.28.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:27:39.504 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 03:27:39.505 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.28.20:5700/2) Recv NOMTXPOWER cmd
2026-01-29 03:27:39.505 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.28.20:5700/2) Recv SETFORMAT cmd
2026-01-29 03:27:39.505 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.28.20:5700/2) TRXD header version 1 -> 1
2026-01-29 03:27:39.506 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.28.20:5700/3) Recv RXTUNE cmd
2026-01-29 03:27:39.506 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.28.20:5700/3) Recv TXTUNE cmd
2026-01-29 03:27:39.506 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.28.20:5700/3) Recv SETFORMAT cmd
2026-01-29 03:27:39.506 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.28.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:27:39.506 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 03:27:39.507 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.28.20:5700/3) Recv NOMTXPOWER cmd
2026-01-29 03:27:39.507 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.28.20:5700/3) Recv SETFORMAT cmd
2026-01-29 03:27:39.507 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.28.20:5700/3) TRXD header version 1 -> 1
2026-01-29 03:27:39.509 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.28.20:5700) Recv RXTUNE cmd
2026-01-29 03:27:39.509 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETTSC
2026-01-29 03:27:39.509 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETTSC
2026-01-29 03:27:39.509 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETTSC
2026-01-29 03:27:39.509 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.28.20:5700) Recv TXTUNE cmd
2026-01-29 03:27:39.510 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETRXGAIN
2026-01-29 03:27:39.510 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETRXGAIN
2026-01-29 03:27:39.510 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETRXGAIN
2026-01-29 03:27:39.510 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETTSC
2026-01-29 03:27:39.510 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:27:39.510 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:27:39.510 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:27:39.510 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.28.20:5700) Recv NOMTXPOWER cmd
2026-01-29 03:27:39.510 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:27:39.510 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:27:39.510 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:27:39.510 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.28.20:5700) Recv POWERON CMD
2026-01-29 03:27:39.510 [INFO] ctrl_if_trx.py:109 (BTS@172.18.28.20:5700) Starting transceiver...
2026-01-29 03:27:39.510 [INFO] transceiver.py:243 Starting clock generator
2026-01-29 03:27:39.510 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-01-29 03:27:39.510 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:27:39.511 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:27:39.511 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:27:39.511 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETRXGAIN
2026-01-29 03:27:39.511 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:27:39.511 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:27:39.511 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:27:39.511 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:27:39.511 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:27:39.511 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:27:39.511 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:27:39.511 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:27:39.511 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:27:39.511 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:27:39.511 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:27:39.511 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:27:39.511 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:27:39.511 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:27:39.512 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:27:39.512 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:27:39.512 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:27:39.512 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:27:39.512 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:27:39.512 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:27:39.512 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:27:39.512 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:27:39.512 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:27:39.515 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-01-29 03:27:39.998 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-01-29 03:27:40.042 [DEBUG] fake_trx.py:278 (BTS@172.18.28.20:5700) Recv FAKE_TOA cmd
2026-01-29 03:27:40.044 [DEBUG] fake_trx.py:297 (BTS@172.18.28.20:5700) Recv FAKE_RSSI cmd
2026-01-29 03:27:40.046 [DEBUG] fake_trx.py:322 (BTS@172.18.28.20:5700) Recv FAKE_CI cmd
2026-01-29 03:27:40.047 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:27:40.050 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 03:27:40.050 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 03:27:40.050 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 03:27:40.051 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 03:27:40.051 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 03:27:40.052 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 03:27:40.052 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.28.22:6700) Recv POWERON CMD
2026-01-29 03:27:40.053 [INFO] ctrl_if_trx.py:109 (MS@172.18.28.22:6700) Starting transceiver...
2026-01-29 03:27:40.088 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.28.22:6700) Recv SETFH cmd
2026-01-29 03:27:40.089 [INFO] transceiver.py:201 (MS@172.18.28.22:6700) Frequency hopping configured: hsn=2, maio=0, ma_len=2
2026-01-29 03:27:40.089 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 03:27:40.089 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 03:27:40.476 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-01-29 03:27:40.513 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 03:27:40.514 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:27:40.516 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:27:40.519 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:27:40.955 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-01-29 03:27:41.433 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-01-29 03:27:41.514 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 03:27:41.515 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:27:41.516 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:27:41.520 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:27:41.911 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-01-29 03:27:42.390 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-01-29 03:27:42.515 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 03:27:42.515 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:27:42.518 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:27:42.521 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:27:42.868 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-01-29 03:27:43.346 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-01-29 03:27:43.517 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 03:27:43.517 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:27:43.518 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:27:43.523 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:27:43.824 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-01-29 03:27:44.303 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-01-29 03:27:44.517 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 03:27:44.518 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:27:44.519 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:27:44.524 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:27:44.781 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-01-29 03:27:45.259 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-01-29 03:27:45.738 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-01-29 03:27:46.215 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-01-29 03:27:46.694 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-01-29 03:27:47.172 [DEBUG] clck_gen.py:113 IND CLOCK 1632
2026-01-29 03:27:47.650 [DEBUG] clck_gen.py:113 IND CLOCK 1734
2026-01-29 03:27:48.093 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 03:27:48.093 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 03:27:48.093 [INFO] transceiver.py:205 (MS@172.18.28.22:6700) Frequency hopping disabled
2026-01-29 03:27:48.097 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 03:27:48.097 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:27:48.097 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:27:48.097 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:27:48.098 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 03:27:48.098 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 03:27:48.098 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 03:27:48.098 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.28.20:5700) Recv POWEROFF cmd
2026-01-29 03:27:48.098 [INFO] ctrl_if_trx.py:117 (BTS@172.18.28.20:5700) Stopping transceiver...
2026-01-29 03:27:48.098 [INFO] transceiver.py:246 Stopping clock generator
2026-01-29 03:27:48.098 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 03:27:48.098 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=1833 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:27:48.098 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=1833 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:27:48.098 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=1833 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:27:48.098 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=1833 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:27:48.098 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=1833 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:27:48.098 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=1833 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:27:48.098 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=1833 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:27:53.101 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.28.20:5700) Recv POWEROFF cmd
2026-01-29 03:27:53.101 [INFO] ctrl_if_trx.py:117 (BTS@172.18.28.20:5700) Stopping transceiver...
2026-01-29 03:27:53.104 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 03:27:53.104 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 03:27:53.104 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 03:27:53.104 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 03:27:53.112 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 03:27:53.112 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.28.20:5700) Recv SETFORMAT cmd
2026-01-29 03:27:53.113 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.28.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:27:53.113 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.28.20:5700) Recv SETFORMAT cmd
2026-01-29 03:27:53.113 [INFO] ctrl_if_trx.py:201 (BTS@172.18.28.20:5700) TRXD header version 1 -> 1
2026-01-29 03:27:53.116 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.28.20:5700/1) Recv RXTUNE cmd
2026-01-29 03:27:53.116 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.28.20:5700/1) Recv TXTUNE cmd
2026-01-29 03:27:53.117 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.28.20:5700/1) Recv SETFORMAT cmd
2026-01-29 03:27:53.117 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.28.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:27:53.117 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 03:27:53.118 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.28.20:5700/1) Recv NOMTXPOWER cmd
2026-01-29 03:27:53.118 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.28.20:5700/1) Recv SETFORMAT cmd
2026-01-29 03:27:53.118 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.28.20:5700/1) TRXD header version 1 -> 1
2026-01-29 03:27:53.119 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.28.20:5700/2) Recv RXTUNE cmd
2026-01-29 03:27:53.120 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.28.20:5700/2) Recv TXTUNE cmd
2026-01-29 03:27:53.120 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.28.20:5700/2) Recv SETFORMAT cmd
2026-01-29 03:27:53.120 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.28.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:27:53.120 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 03:27:53.120 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.28.20:5700/2) Recv NOMTXPOWER cmd
2026-01-29 03:27:53.120 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.28.20:5700/2) Recv SETFORMAT cmd
2026-01-29 03:27:53.120 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.28.20:5700/2) TRXD header version 1 -> 1
2026-01-29 03:27:53.123 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.28.20:5700/3) Recv RXTUNE cmd
2026-01-29 03:27:53.123 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.28.20:5700/3) Recv TXTUNE cmd
2026-01-29 03:27:53.123 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.28.20:5700/3) Recv SETFORMAT cmd
2026-01-29 03:27:53.123 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.28.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:27:53.123 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 03:27:53.123 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.28.20:5700/3) Recv NOMTXPOWER cmd
2026-01-29 03:27:53.124 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.28.20:5700/3) Recv SETFORMAT cmd
2026-01-29 03:27:53.124 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.28.20:5700/3) TRXD header version 1 -> 1
2026-01-29 03:27:53.127 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.28.20:5700) Recv RXTUNE cmd
2026-01-29 03:27:53.127 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETTSC
2026-01-29 03:27:53.127 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETTSC
2026-01-29 03:27:53.127 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETTSC
2026-01-29 03:27:53.127 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.28.20:5700) Recv TXTUNE cmd
2026-01-29 03:27:53.127 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETRXGAIN
2026-01-29 03:27:53.127 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETRXGAIN
2026-01-29 03:27:53.127 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETRXGAIN
2026-01-29 03:27:53.127 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETTSC
2026-01-29 03:27:53.127 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:27:53.127 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:27:53.127 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.28.20:5700) Recv NOMTXPOWER cmd
2026-01-29 03:27:53.127 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:27:53.128 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:27:53.128 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:27:53.128 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.28.20:5700) Recv POWERON CMD
2026-01-29 03:27:53.128 [INFO] ctrl_if_trx.py:109 (BTS@172.18.28.20:5700) Starting transceiver...
2026-01-29 03:27:53.128 [INFO] transceiver.py:243 Starting clock generator
2026-01-29 03:27:53.128 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-01-29 03:27:53.128 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:27:53.128 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:27:53.128 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:27:53.128 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETRXGAIN
2026-01-29 03:27:53.128 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:27:53.128 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:27:53.128 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:27:53.128 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:27:53.128 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:27:53.128 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:27:53.128 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:27:53.128 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:27:53.130 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:27:53.130 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:27:53.130 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:27:53.130 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:27:53.130 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:27:53.130 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:27:53.130 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:27:53.130 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:27:53.130 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:27:53.130 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:27:53.130 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:27:53.130 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:27:53.130 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:27:53.130 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:27:53.130 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 03:27:53.130 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:27:53.130 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:27:53.130 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 03:27:53.130 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 03:27:53.130 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 03:27:53.130 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.28.20:5700) Recv POWEROFF cmd
2026-01-29 03:27:53.130 [INFO] ctrl_if_trx.py:117 (BTS@172.18.28.20:5700) Stopping transceiver...
2026-01-29 03:27:53.130 [INFO] transceiver.py:246 Stopping clock generator
2026-01-29 03:27:58.133 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.28.20:5700) Recv POWEROFF cmd
2026-01-29 03:27:58.133 [INFO] ctrl_if_trx.py:117 (BTS@172.18.28.20:5700) Stopping transceiver...
2026-01-29 03:27:58.135 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 03:27:58.136 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 03:27:58.137 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 03:27:58.138 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 03:27:58.142 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 03:27:58.143 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.28.20:5700) Recv SETFORMAT cmd
2026-01-29 03:27:58.143 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.28.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:27:58.143 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.28.20:5700) Recv SETFORMAT cmd
2026-01-29 03:27:58.143 [INFO] ctrl_if_trx.py:201 (BTS@172.18.28.20:5700) TRXD header version 1 -> 1
2026-01-29 03:27:58.145 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.28.20:5700/1) Recv RXTUNE cmd
2026-01-29 03:27:58.146 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.28.20:5700/1) Recv TXTUNE cmd
2026-01-29 03:27:58.146 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.28.20:5700/1) Recv SETFORMAT cmd
2026-01-29 03:27:58.146 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.28.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:27:58.146 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 03:27:58.147 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.28.20:5700/1) Recv NOMTXPOWER cmd
2026-01-29 03:27:58.147 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.28.20:5700/1) Recv SETFORMAT cmd
2026-01-29 03:27:58.147 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.28.20:5700/1) TRXD header version 1 -> 1
2026-01-29 03:27:58.148 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.28.20:5700/2) Recv RXTUNE cmd
2026-01-29 03:27:58.148 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.28.20:5700/2) Recv TXTUNE cmd
2026-01-29 03:27:58.148 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.28.20:5700/2) Recv SETFORMAT cmd
2026-01-29 03:27:58.148 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.28.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:27:58.148 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 03:27:58.148 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.28.20:5700/2) Recv NOMTXPOWER cmd
2026-01-29 03:27:58.149 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.28.20:5700/2) Recv SETFORMAT cmd
2026-01-29 03:27:58.149 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.28.20:5700/2) TRXD header version 1 -> 1
2026-01-29 03:27:58.150 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.28.20:5700/3) Recv RXTUNE cmd
2026-01-29 03:27:58.150 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.28.20:5700/3) Recv TXTUNE cmd
2026-01-29 03:27:58.150 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.28.20:5700/3) Recv SETFORMAT cmd
2026-01-29 03:27:58.150 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.28.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:27:58.150 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 03:27:58.151 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.28.20:5700/3) Recv NOMTXPOWER cmd
2026-01-29 03:27:58.151 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.28.20:5700/3) Recv SETFORMAT cmd
2026-01-29 03:27:58.151 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.28.20:5700/3) TRXD header version 1 -> 1
2026-01-29 03:27:58.153 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.28.20:5700) Recv RXTUNE cmd
2026-01-29 03:27:58.153 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETTSC
2026-01-29 03:27:58.153 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETTSC
2026-01-29 03:27:58.153 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETTSC
2026-01-29 03:27:58.153 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.28.20:5700) Recv TXTUNE cmd
2026-01-29 03:27:58.153 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETRXGAIN
2026-01-29 03:27:58.153 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETRXGAIN
2026-01-29 03:27:58.153 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETRXGAIN
2026-01-29 03:27:58.153 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETTSC
2026-01-29 03:27:58.153 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:27:58.153 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:27:58.153 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:27:58.153 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.28.20:5700) Recv NOMTXPOWER cmd
2026-01-29 03:27:58.153 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:27:58.153 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:27:58.153 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:27:58.153 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.28.20:5700) Recv POWERON CMD
2026-01-29 03:27:58.153 [INFO] ctrl_if_trx.py:109 (BTS@172.18.28.20:5700) Starting transceiver...
2026-01-29 03:27:58.153 [INFO] transceiver.py:243 Starting clock generator
2026-01-29 03:27:58.153 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-01-29 03:27:58.153 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:27:58.153 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:27:58.153 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:27:58.154 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETRXGAIN
2026-01-29 03:27:58.154 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:27:58.154 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:27:58.154 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:27:58.154 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:27:58.154 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:27:58.154 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:27:58.154 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:27:58.154 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:27:58.154 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:27:58.154 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:27:58.154 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:27:58.154 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:27:58.154 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:27:58.154 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:27:58.154 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:27:58.154 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:27:58.154 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:27:58.154 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:27:58.154 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:27:58.154 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:27:58.154 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:27:58.154 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:27:58.154 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:27:58.158 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-01-29 03:27:58.641 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-01-29 03:27:58.669 [DEBUG] fake_trx.py:278 (BTS@172.18.28.20:5700) Recv FAKE_TOA cmd
2026-01-29 03:27:58.670 [DEBUG] fake_trx.py:297 (BTS@172.18.28.20:5700) Recv FAKE_RSSI cmd
2026-01-29 03:27:58.670 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:27:58.671 [DEBUG] fake_trx.py:322 (BTS@172.18.28.20:5700) Recv FAKE_CI cmd
2026-01-29 03:27:58.672 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 03:27:58.672 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 03:27:58.672 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 03:27:58.672 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 03:27:58.672 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 03:27:58.672 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 03:27:58.672 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.28.22:6700) Recv POWERON CMD
2026-01-29 03:27:58.672 [INFO] ctrl_if_trx.py:109 (MS@172.18.28.22:6700) Starting transceiver...
2026-01-29 03:27:58.684 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.28.22:6700) Recv SETFH cmd
2026-01-29 03:27:58.684 [INFO] transceiver.py:201 (MS@172.18.28.22:6700) Frequency hopping configured: hsn=2, maio=0, ma_len=2
2026-01-29 03:27:58.684 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 03:27:58.684 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 03:27:59.119 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-01-29 03:27:59.156 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:27:59.156 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 03:27:59.157 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:27:59.159 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:27:59.597 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-01-29 03:28:00.075 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-01-29 03:28:00.157 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 03:28:00.157 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:28:00.158 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:28:00.160 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:28:00.553 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-01-29 03:28:01.031 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-01-29 03:28:01.158 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 03:28:01.158 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:28:01.158 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:28:01.161 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:28:01.510 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-01-29 03:28:01.988 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-01-29 03:28:02.158 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 03:28:02.159 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:28:02.159 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:28:02.161 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:28:02.465 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-01-29 03:28:02.943 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-01-29 03:28:03.159 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 03:28:03.159 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:28:03.160 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:28:03.163 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:28:03.422 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-01-29 03:28:03.900 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-01-29 03:28:04.378 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-01-29 03:28:04.856 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-01-29 03:28:05.334 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-01-29 03:28:05.812 [DEBUG] clck_gen.py:113 IND CLOCK 1632
2026-01-29 03:28:06.290 [DEBUG] clck_gen.py:113 IND CLOCK 1734
2026-01-29 03:28:06.688 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 03:28:06.688 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 03:28:06.688 [INFO] transceiver.py:205 (MS@172.18.28.22:6700) Frequency hopping disabled
2026-01-29 03:28:06.691 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 03:28:06.691 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:28:06.691 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:28:06.691 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:28:06.692 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 03:28:06.692 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 03:28:06.692 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 03:28:06.692 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 03:28:06.692 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.28.20:5700) Recv POWEROFF cmd
2026-01-29 03:28:06.692 [INFO] ctrl_if_trx.py:117 (BTS@172.18.28.20:5700) Stopping transceiver...
2026-01-29 03:28:06.692 [INFO] transceiver.py:246 Stopping clock generator
2026-01-29 03:28:06.692 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=1823 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:28:06.692 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=1823 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:28:06.692 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=1823 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:28:06.692 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=1823 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:28:06.692 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=1823 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:28:06.692 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=1823 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:28:06.692 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=1823 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:28:06.692 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=1823 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:28:11.695 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.28.20:5700) Recv POWEROFF cmd
2026-01-29 03:28:11.695 [INFO] ctrl_if_trx.py:117 (BTS@172.18.28.20:5700) Stopping transceiver...
2026-01-29 03:28:11.697 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 03:28:11.698 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 03:28:11.699 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 03:28:11.699 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 03:28:11.702 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 03:28:11.702 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.28.20:5700) Recv SETFORMAT cmd
2026-01-29 03:28:11.702 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.28.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:28:11.703 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.28.20:5700) Recv SETFORMAT cmd
2026-01-29 03:28:11.703 [INFO] ctrl_if_trx.py:201 (BTS@172.18.28.20:5700) TRXD header version 1 -> 1
2026-01-29 03:28:11.704 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.28.20:5700/1) Recv RXTUNE cmd
2026-01-29 03:28:11.704 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.28.20:5700/1) Recv TXTUNE cmd
2026-01-29 03:28:11.704 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.28.20:5700/1) Recv SETFORMAT cmd
2026-01-29 03:28:11.704 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.28.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:28:11.705 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 03:28:11.705 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.28.20:5700/1) Recv NOMTXPOWER cmd
2026-01-29 03:28:11.705 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.28.20:5700/1) Recv SETFORMAT cmd
2026-01-29 03:28:11.705 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.28.20:5700/1) TRXD header version 1 -> 1
2026-01-29 03:28:11.706 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.28.20:5700/2) Recv RXTUNE cmd
2026-01-29 03:28:11.706 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.28.20:5700/2) Recv TXTUNE cmd
2026-01-29 03:28:11.706 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.28.20:5700/2) Recv SETFORMAT cmd
2026-01-29 03:28:11.707 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.28.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:28:11.707 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 03:28:11.707 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.28.20:5700/2) Recv NOMTXPOWER cmd
2026-01-29 03:28:11.707 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.28.20:5700/2) Recv SETFORMAT cmd
2026-01-29 03:28:11.707 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.28.20:5700/2) TRXD header version 1 -> 1
2026-01-29 03:28:11.709 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.28.20:5700/3) Recv RXTUNE cmd
2026-01-29 03:28:11.709 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.28.20:5700/3) Recv TXTUNE cmd
2026-01-29 03:28:11.709 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.28.20:5700/3) Recv SETFORMAT cmd
2026-01-29 03:28:11.709 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.28.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:28:11.709 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 03:28:11.709 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.28.20:5700/3) Recv NOMTXPOWER cmd
2026-01-29 03:28:11.709 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.28.20:5700/3) Recv SETFORMAT cmd
2026-01-29 03:28:11.709 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.28.20:5700/3) TRXD header version 1 -> 1
2026-01-29 03:28:11.712 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.28.20:5700) Recv RXTUNE cmd
2026-01-29 03:28:11.712 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETTSC
2026-01-29 03:28:11.712 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETTSC
2026-01-29 03:28:11.712 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETTSC
2026-01-29 03:28:11.712 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.28.20:5700) Recv TXTUNE cmd
2026-01-29 03:28:11.712 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETRXGAIN
2026-01-29 03:28:11.712 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETRXGAIN
2026-01-29 03:28:11.712 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETRXGAIN
2026-01-29 03:28:11.712 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETTSC
2026-01-29 03:28:11.712 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:28:11.712 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:28:11.712 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:28:11.712 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.28.20:5700) Recv NOMTXPOWER cmd
2026-01-29 03:28:11.712 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:28:11.712 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:28:11.712 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:28:11.712 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.28.20:5700) Recv POWERON CMD
2026-01-29 03:28:11.712 [INFO] ctrl_if_trx.py:109 (BTS@172.18.28.20:5700) Starting transceiver...
2026-01-29 03:28:11.712 [INFO] transceiver.py:243 Starting clock generator
2026-01-29 03:28:11.713 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-01-29 03:28:11.713 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:28:11.713 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:28:11.713 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:28:11.713 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETRXGAIN
2026-01-29 03:28:11.713 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:28:11.713 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:28:11.713 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:28:11.713 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:28:11.714 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:28:11.714 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:28:11.714 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:28:11.714 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:28:11.714 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:28:11.714 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:28:11.714 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:28:11.714 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:28:11.714 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:28:11.714 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:28:11.714 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:28:11.714 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:28:11.714 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:28:11.714 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 03:28:11.714 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:28:11.714 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:28:11.714 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:28:11.714 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:28:11.714 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:28:11.714 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:28:11.714 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 03:28:11.714 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 03:28:11.714 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 03:28:11.715 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.28.20:5700) Recv POWEROFF cmd
2026-01-29 03:28:11.715 [INFO] ctrl_if_trx.py:117 (BTS@172.18.28.20:5700) Stopping transceiver...
2026-01-29 03:28:11.715 [INFO] transceiver.py:246 Stopping clock generator
2026-01-29 03:28:16.718 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.28.20:5700) Recv POWEROFF cmd
2026-01-29 03:28:16.718 [INFO] ctrl_if_trx.py:117 (BTS@172.18.28.20:5700) Stopping transceiver...
2026-01-29 03:28:16.719 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 03:28:16.721 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 03:28:16.722 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 03:28:16.722 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 03:28:16.730 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 03:28:16.731 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.28.20:5700) Recv SETFORMAT cmd
2026-01-29 03:28:16.731 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.28.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:28:16.732 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.28.20:5700) Recv SETFORMAT cmd
2026-01-29 03:28:16.732 [INFO] ctrl_if_trx.py:201 (BTS@172.18.28.20:5700) TRXD header version 1 -> 1
2026-01-29 03:28:16.736 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.28.20:5700/1) Recv RXTUNE cmd
2026-01-29 03:28:16.736 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.28.20:5700/1) Recv TXTUNE cmd
2026-01-29 03:28:16.736 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.28.20:5700/1) Recv SETFORMAT cmd
2026-01-29 03:28:16.737 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.28.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:28:16.737 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 03:28:16.737 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.28.20:5700/1) Recv NOMTXPOWER cmd
2026-01-29 03:28:16.737 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.28.20:5700/1) Recv SETFORMAT cmd
2026-01-29 03:28:16.737 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.28.20:5700/1) TRXD header version 1 -> 1
2026-01-29 03:28:16.739 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.28.20:5700/2) Recv RXTUNE cmd
2026-01-29 03:28:16.739 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.28.20:5700/2) Recv TXTUNE cmd
2026-01-29 03:28:16.739 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.28.20:5700/2) Recv SETFORMAT cmd
2026-01-29 03:28:16.739 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.28.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:28:16.740 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 03:28:16.740 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.28.20:5700/2) Recv NOMTXPOWER cmd
2026-01-29 03:28:16.740 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.28.20:5700/2) Recv SETFORMAT cmd
2026-01-29 03:28:16.740 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.28.20:5700/2) TRXD header version 1 -> 1
2026-01-29 03:28:16.741 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.28.20:5700/3) Recv RXTUNE cmd
2026-01-29 03:28:16.741 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.28.20:5700/3) Recv TXTUNE cmd
2026-01-29 03:28:16.741 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.28.20:5700/3) Recv SETFORMAT cmd
2026-01-29 03:28:16.742 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.28.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:28:16.742 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 03:28:16.742 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.28.20:5700/3) Recv NOMTXPOWER cmd
2026-01-29 03:28:16.742 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.28.20:5700/3) Recv SETFORMAT cmd
2026-01-29 03:28:16.742 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.28.20:5700/3) TRXD header version 1 -> 1
2026-01-29 03:28:16.744 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.28.20:5700) Recv RXTUNE cmd
2026-01-29 03:28:16.745 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETTSC
2026-01-29 03:28:16.745 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETTSC
2026-01-29 03:28:16.745 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETTSC
2026-01-29 03:28:16.745 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.28.20:5700) Recv TXTUNE cmd
2026-01-29 03:28:16.745 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETRXGAIN
2026-01-29 03:28:16.745 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETRXGAIN
2026-01-29 03:28:16.745 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETRXGAIN
2026-01-29 03:28:16.745 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETTSC
2026-01-29 03:28:16.745 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:28:16.745 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:28:16.745 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:28:16.745 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.28.20:5700) Recv NOMTXPOWER cmd
2026-01-29 03:28:16.745 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:28:16.745 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:28:16.745 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:28:16.745 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.28.20:5700) Recv POWERON CMD
2026-01-29 03:28:16.745 [INFO] ctrl_if_trx.py:109 (BTS@172.18.28.20:5700) Starting transceiver...
2026-01-29 03:28:16.745 [INFO] transceiver.py:243 Starting clock generator
2026-01-29 03:28:16.745 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-01-29 03:28:16.745 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:28:16.745 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:28:16.745 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:28:16.745 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETRXGAIN
2026-01-29 03:28:16.746 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:28:16.746 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:28:16.746 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:28:16.746 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:28:16.746 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:28:16.746 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:28:16.746 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:28:16.746 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:28:16.746 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:28:16.746 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:28:16.746 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:28:16.746 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:28:16.746 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:28:16.746 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:28:16.746 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:28:16.746 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:28:16.746 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:28:16.746 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:28:16.746 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:28:16.746 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:28:16.746 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:28:16.746 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:28:16.746 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:28:16.750 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-01-29 03:28:17.232 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-01-29 03:28:17.273 [DEBUG] fake_trx.py:278 (BTS@172.18.28.20:5700) Recv FAKE_TOA cmd
2026-01-29 03:28:17.275 [DEBUG] fake_trx.py:297 (BTS@172.18.28.20:5700) Recv FAKE_RSSI cmd
2026-01-29 03:28:17.277 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:28:17.277 [DEBUG] fake_trx.py:322 (BTS@172.18.28.20:5700) Recv FAKE_CI cmd
2026-01-29 03:28:17.281 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 03:28:17.281 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 03:28:17.281 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 03:28:17.282 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 03:28:17.282 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 03:28:17.282 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 03:28:17.282 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.28.22:6700) Recv POWERON CMD
2026-01-29 03:28:17.282 [INFO] ctrl_if_trx.py:109 (MS@172.18.28.22:6700) Starting transceiver...
2026-01-29 03:28:17.322 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.28.22:6700) Recv SETFH cmd
2026-01-29 03:28:17.323 [INFO] transceiver.py:201 (MS@172.18.28.22:6700) Frequency hopping configured: hsn=2, maio=0, ma_len=2
2026-01-29 03:28:17.323 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 03:28:17.323 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 03:28:17.711 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-01-29 03:28:17.748 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 03:28:17.748 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:28:17.749 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:28:17.752 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:28:18.189 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-01-29 03:28:18.667 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-01-29 03:28:18.748 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 03:28:18.749 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:28:18.749 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:28:18.753 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:28:19.142 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-01-29 03:28:19.611 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-01-29 03:28:19.749 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 03:28:19.749 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:28:19.750 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:28:19.755 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:28:20.088 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-01-29 03:28:20.566 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-01-29 03:28:20.750 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 03:28:20.750 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:28:20.751 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:28:20.755 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:28:21.044 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-01-29 03:28:21.522 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-01-29 03:28:21.751 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:28:21.751 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:28:21.752 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 03:28:21.756 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:28:22.000 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-01-29 03:28:22.478 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-01-29 03:28:22.956 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-01-29 03:28:23.434 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-01-29 03:28:23.912 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-01-29 03:28:24.391 [DEBUG] clck_gen.py:113 IND CLOCK 1632
2026-01-29 03:28:24.865 [DEBUG] clck_gen.py:113 IND CLOCK 1734
2026-01-29 03:28:25.327 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 03:28:25.327 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 03:28:25.327 [INFO] transceiver.py:205 (MS@172.18.28.22:6700) Frequency hopping disabled
2026-01-29 03:28:25.331 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 03:28:25.331 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:28:25.331 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:28:25.331 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:28:25.332 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 03:28:25.332 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 03:28:25.332 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 03:28:25.332 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 03:28:25.332 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.28.20:5700) Recv POWEROFF cmd
2026-01-29 03:28:25.332 [INFO] ctrl_if_trx.py:117 (BTS@172.18.28.20:5700) Stopping transceiver...
2026-01-29 03:28:25.332 [INFO] transceiver.py:246 Stopping clock generator
2026-01-29 03:28:25.332 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=1837 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:28:25.332 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=1837 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:28:25.332 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=1837 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:28:25.332 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=1837 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:28:25.332 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=1837 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:28:25.332 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=1837 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:28:30.335 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.28.20:5700) Recv POWEROFF cmd
2026-01-29 03:28:30.335 [INFO] ctrl_if_trx.py:117 (BTS@172.18.28.20:5700) Stopping transceiver...
2026-01-29 03:28:30.337 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 03:28:30.338 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 03:28:30.338 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 03:28:30.338 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 03:28:30.345 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 03:28:30.347 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.28.20:5700) Recv SETFORMAT cmd
2026-01-29 03:28:30.347 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.28.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:28:30.347 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.28.20:5700) Recv SETFORMAT cmd
2026-01-29 03:28:30.347 [INFO] ctrl_if_trx.py:201 (BTS@172.18.28.20:5700) TRXD header version 1 -> 1
2026-01-29 03:28:30.351 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.28.20:5700/1) Recv RXTUNE cmd
2026-01-29 03:28:30.351 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.28.20:5700/1) Recv TXTUNE cmd
2026-01-29 03:28:30.352 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.28.20:5700/1) Recv SETFORMAT cmd
2026-01-29 03:28:30.352 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.28.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:28:30.352 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 03:28:30.353 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.28.20:5700/1) Recv NOMTXPOWER cmd
2026-01-29 03:28:30.353 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.28.20:5700/1) Recv SETFORMAT cmd
2026-01-29 03:28:30.353 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.28.20:5700/1) TRXD header version 1 -> 1
2026-01-29 03:28:30.354 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.28.20:5700/2) Recv RXTUNE cmd
2026-01-29 03:28:30.354 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.28.20:5700/2) Recv TXTUNE cmd
2026-01-29 03:28:30.355 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.28.20:5700/2) Recv SETFORMAT cmd
2026-01-29 03:28:30.355 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.28.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:28:30.355 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 03:28:30.356 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.28.20:5700/2) Recv NOMTXPOWER cmd
2026-01-29 03:28:30.356 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.28.20:5700/2) Recv SETFORMAT cmd
2026-01-29 03:28:30.356 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.28.20:5700/2) TRXD header version 1 -> 1
2026-01-29 03:28:30.357 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.28.20:5700/3) Recv RXTUNE cmd
2026-01-29 03:28:30.357 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.28.20:5700/3) Recv TXTUNE cmd
2026-01-29 03:28:30.357 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.28.20:5700/3) Recv SETFORMAT cmd
2026-01-29 03:28:30.357 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.28.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:28:30.357 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 03:28:30.357 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.28.20:5700/3) Recv NOMTXPOWER cmd
2026-01-29 03:28:30.357 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.28.20:5700/3) Recv SETFORMAT cmd
2026-01-29 03:28:30.357 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.28.20:5700/3) TRXD header version 1 -> 1
2026-01-29 03:28:30.360 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.28.20:5700) Recv RXTUNE cmd
2026-01-29 03:28:30.360 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETTSC
2026-01-29 03:28:30.360 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETTSC
2026-01-29 03:28:30.360 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETTSC
2026-01-29 03:28:30.360 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.28.20:5700) Recv TXTUNE cmd
2026-01-29 03:28:30.360 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETRXGAIN
2026-01-29 03:28:30.361 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETRXGAIN
2026-01-29 03:28:30.361 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETRXGAIN
2026-01-29 03:28:30.361 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETTSC
2026-01-29 03:28:30.361 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:28:30.361 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:28:30.361 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.28.20:5700) Recv NOMTXPOWER cmd
2026-01-29 03:28:30.361 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:28:30.361 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:28:30.361 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:28:30.361 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.28.20:5700) Recv POWERON CMD
2026-01-29 03:28:30.361 [INFO] ctrl_if_trx.py:109 (BTS@172.18.28.20:5700) Starting transceiver...
2026-01-29 03:28:30.361 [INFO] transceiver.py:243 Starting clock generator
2026-01-29 03:28:30.361 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-01-29 03:28:30.361 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:28:30.361 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:28:30.361 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:28:30.361 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETRXGAIN
2026-01-29 03:28:30.361 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:28:30.362 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:28:30.362 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:28:30.362 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:28:30.362 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:28:30.363 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:28:30.363 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:28:30.363 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:28:30.363 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:28:30.363 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:28:30.363 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:28:30.363 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:28:30.363 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:28:30.363 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:28:30.363 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:28:30.363 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:28:30.363 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:28:30.363 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:28:30.363 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:28:30.363 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 03:28:30.363 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:28:30.363 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:28:30.363 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:28:30.363 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:28:30.363 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:28:30.363 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 03:28:30.363 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 03:28:30.363 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.28.20:5700) Recv POWEROFF cmd
2026-01-29 03:28:30.363 [INFO] ctrl_if_trx.py:117 (BTS@172.18.28.20:5700) Stopping transceiver...
2026-01-29 03:28:30.363 [INFO] transceiver.py:246 Stopping clock generator
2026-01-29 03:28:30.363 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 03:28:35.366 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.28.20:5700) Recv POWEROFF cmd
2026-01-29 03:28:35.366 [INFO] ctrl_if_trx.py:117 (BTS@172.18.28.20:5700) Stopping transceiver...
2026-01-29 03:28:35.369 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 03:28:35.369 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 03:28:35.369 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 03:28:35.369 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 03:28:35.377 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 03:28:35.378 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.28.20:5700) Recv SETFORMAT cmd
2026-01-29 03:28:35.378 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.28.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:28:35.378 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.28.20:5700) Recv SETFORMAT cmd
2026-01-29 03:28:35.379 [INFO] ctrl_if_trx.py:201 (BTS@172.18.28.20:5700) TRXD header version 1 -> 1
2026-01-29 03:28:35.382 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.28.20:5700/1) Recv RXTUNE cmd
2026-01-29 03:28:35.383 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.28.20:5700/1) Recv TXTUNE cmd
2026-01-29 03:28:35.383 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.28.20:5700/1) Recv SETFORMAT cmd
2026-01-29 03:28:35.384 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.28.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:28:35.384 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 03:28:35.385 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.28.20:5700/1) Recv NOMTXPOWER cmd
2026-01-29 03:28:35.385 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.28.20:5700/1) Recv SETFORMAT cmd
2026-01-29 03:28:35.385 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.28.20:5700/1) TRXD header version 1 -> 1
2026-01-29 03:28:35.387 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.28.20:5700/2) Recv RXTUNE cmd
2026-01-29 03:28:35.387 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.28.20:5700/2) Recv TXTUNE cmd
2026-01-29 03:28:35.388 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.28.20:5700/2) Recv SETFORMAT cmd
2026-01-29 03:28:35.388 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.28.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:28:35.388 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 03:28:35.389 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.28.20:5700/2) Recv NOMTXPOWER cmd
2026-01-29 03:28:35.389 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.28.20:5700/2) Recv SETFORMAT cmd
2026-01-29 03:28:35.389 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.28.20:5700/2) TRXD header version 1 -> 1
2026-01-29 03:28:35.391 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.28.20:5700/3) Recv RXTUNE cmd
2026-01-29 03:28:35.391 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.28.20:5700/3) Recv TXTUNE cmd
2026-01-29 03:28:35.391 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.28.20:5700/3) Recv SETFORMAT cmd
2026-01-29 03:28:35.392 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.28.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:28:35.392 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 03:28:35.392 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.28.20:5700/3) Recv NOMTXPOWER cmd
2026-01-29 03:28:35.392 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.28.20:5700/3) Recv SETFORMAT cmd
2026-01-29 03:28:35.392 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.28.20:5700/3) TRXD header version 1 -> 1
2026-01-29 03:28:35.396 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.28.20:5700) Recv RXTUNE cmd
2026-01-29 03:28:35.396 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETTSC
2026-01-29 03:28:35.396 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETTSC
2026-01-29 03:28:35.396 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETTSC
2026-01-29 03:28:35.396 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.28.20:5700) Recv TXTUNE cmd
2026-01-29 03:28:35.396 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETRXGAIN
2026-01-29 03:28:35.396 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETRXGAIN
2026-01-29 03:28:35.396 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETRXGAIN
2026-01-29 03:28:35.396 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETTSC
2026-01-29 03:28:35.396 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:28:35.396 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:28:35.396 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.28.20:5700) Recv NOMTXPOWER cmd
2026-01-29 03:28:35.396 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:28:35.396 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:28:35.396 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:28:35.396 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.28.20:5700) Recv POWERON CMD
2026-01-29 03:28:35.396 [INFO] ctrl_if_trx.py:109 (BTS@172.18.28.20:5700) Starting transceiver...
2026-01-29 03:28:35.396 [INFO] transceiver.py:243 Starting clock generator
2026-01-29 03:28:35.397 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-01-29 03:28:35.397 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:28:35.397 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:28:35.397 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:28:35.397 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETRXGAIN
2026-01-29 03:28:35.397 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:28:35.397 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:28:35.397 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:28:35.397 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:28:35.397 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:28:35.397 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:28:35.397 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:28:35.397 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:28:35.398 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:28:35.398 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:28:35.398 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:28:35.398 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:28:35.398 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:28:35.398 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:28:35.398 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:28:35.398 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:28:35.398 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:28:35.398 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:28:35.398 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:28:35.398 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:28:35.398 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:28:35.398 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:28:35.398 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:28:35.399 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:28:35.402 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-01-29 03:28:35.884 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-01-29 03:28:35.935 [DEBUG] fake_trx.py:278 (BTS@172.18.28.20:5700) Recv FAKE_TOA cmd
2026-01-29 03:28:35.937 [DEBUG] fake_trx.py:297 (BTS@172.18.28.20:5700) Recv FAKE_RSSI cmd
2026-01-29 03:28:35.939 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:28:35.939 [DEBUG] fake_trx.py:322 (BTS@172.18.28.20:5700) Recv FAKE_CI cmd
2026-01-29 03:28:35.943 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 03:28:35.943 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 03:28:35.943 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 03:28:35.944 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 03:28:35.944 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 03:28:35.944 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 03:28:35.945 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.28.22:6700) Recv POWERON CMD
2026-01-29 03:28:35.945 [INFO] ctrl_if_trx.py:109 (MS@172.18.28.22:6700) Starting transceiver...
2026-01-29 03:28:35.974 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.28.22:6700) Recv SETFH cmd
2026-01-29 03:28:35.975 [INFO] transceiver.py:201 (MS@172.18.28.22:6700) Frequency hopping configured: hsn=2, maio=0, ma_len=2
2026-01-29 03:28:35.975 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 03:28:35.975 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 03:28:36.363 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-01-29 03:28:36.401 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 03:28:36.403 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:28:36.403 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:28:36.405 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:28:36.840 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-01-29 03:28:37.319 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-01-29 03:28:37.402 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 03:28:37.404 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:28:37.404 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:28:37.406 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:28:37.797 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-01-29 03:28:38.275 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-01-29 03:28:38.403 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 03:28:38.404 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:28:38.405 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:28:38.407 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:28:38.753 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-01-29 03:28:39.231 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-01-29 03:28:39.404 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 03:28:39.406 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:28:39.406 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:28:39.409 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:28:39.708 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-01-29 03:28:40.186 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-01-29 03:28:40.405 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 03:28:40.406 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:28:40.407 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:28:40.409 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:28:40.664 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-01-29 03:28:41.142 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-01-29 03:28:41.620 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-01-29 03:28:42.098 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-01-29 03:28:42.576 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-01-29 03:28:43.054 [DEBUG] clck_gen.py:113 IND CLOCK 1632
2026-01-29 03:28:43.532 [DEBUG] clck_gen.py:113 IND CLOCK 1734
2026-01-29 03:28:43.980 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 03:28:43.980 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 03:28:43.980 [INFO] transceiver.py:205 (MS@172.18.28.22:6700) Frequency hopping disabled
2026-01-29 03:28:43.985 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 03:28:43.985 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:28:43.986 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:28:43.986 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:28:43.987 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 03:28:43.987 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 03:28:43.987 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 03:28:43.987 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 03:28:43.987 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.28.20:5700) Recv POWEROFF cmd
2026-01-29 03:28:43.987 [INFO] ctrl_if_trx.py:117 (BTS@172.18.28.20:5700) Stopping transceiver...
2026-01-29 03:28:43.987 [INFO] transceiver.py:246 Stopping clock generator
2026-01-29 03:28:48.987 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.28.20:5700) Recv POWEROFF cmd
2026-01-29 03:28:48.987 [INFO] ctrl_if_trx.py:117 (BTS@172.18.28.20:5700) Stopping transceiver...
2026-01-29 03:28:48.989 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 03:28:48.989 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 03:28:48.990 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 03:28:48.990 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 03:28:48.993 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 03:28:48.993 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.28.20:5700) Recv SETFORMAT cmd
2026-01-29 03:28:48.993 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.28.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:28:48.993 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.28.20:5700) Recv SETFORMAT cmd
2026-01-29 03:28:48.993 [INFO] ctrl_if_trx.py:201 (BTS@172.18.28.20:5700) TRXD header version 1 -> 1
2026-01-29 03:28:48.995 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.28.20:5700/1) Recv RXTUNE cmd
2026-01-29 03:28:48.995 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.28.20:5700/1) Recv TXTUNE cmd
2026-01-29 03:28:48.995 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.28.20:5700/1) Recv SETFORMAT cmd
2026-01-29 03:28:48.995 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.28.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:28:48.995 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 03:28:48.995 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.28.20:5700/1) Recv NOMTXPOWER cmd
2026-01-29 03:28:48.995 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.28.20:5700/1) Recv SETFORMAT cmd
2026-01-29 03:28:48.995 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.28.20:5700/1) TRXD header version 1 -> 1
2026-01-29 03:28:48.997 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.28.20:5700/2) Recv RXTUNE cmd
2026-01-29 03:28:48.997 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.28.20:5700/2) Recv TXTUNE cmd
2026-01-29 03:28:48.997 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.28.20:5700/2) Recv SETFORMAT cmd
2026-01-29 03:28:48.997 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.28.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:28:48.997 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 03:28:48.997 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.28.20:5700/2) Recv NOMTXPOWER cmd
2026-01-29 03:28:48.997 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.28.20:5700/2) Recv SETFORMAT cmd
2026-01-29 03:28:48.997 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.28.20:5700/2) TRXD header version 1 -> 1
2026-01-29 03:28:48.999 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.28.20:5700/3) Recv RXTUNE cmd
2026-01-29 03:28:48.999 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.28.20:5700/3) Recv TXTUNE cmd
2026-01-29 03:28:48.999 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.28.20:5700/3) Recv SETFORMAT cmd
2026-01-29 03:28:48.999 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.28.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:28:48.999 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 03:28:48.999 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.28.20:5700/3) Recv NOMTXPOWER cmd
2026-01-29 03:28:49.000 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.28.20:5700/3) Recv SETFORMAT cmd
2026-01-29 03:28:49.000 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.28.20:5700/3) TRXD header version 1 -> 1
2026-01-29 03:28:49.002 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.28.20:5700) Recv RXTUNE cmd
2026-01-29 03:28:49.002 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETTSC
2026-01-29 03:28:49.002 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETTSC
2026-01-29 03:28:49.002 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETTSC
2026-01-29 03:28:49.002 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.28.20:5700) Recv TXTUNE cmd
2026-01-29 03:28:49.002 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETRXGAIN
2026-01-29 03:28:49.002 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETRXGAIN
2026-01-29 03:28:49.002 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETRXGAIN
2026-01-29 03:28:49.002 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETTSC
2026-01-29 03:28:49.002 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:28:49.002 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:28:49.002 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:28:49.002 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.28.20:5700) Recv NOMTXPOWER cmd
2026-01-29 03:28:49.002 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:28:49.002 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:28:49.002 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:28:49.002 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.28.20:5700) Recv POWERON CMD
2026-01-29 03:28:49.002 [INFO] ctrl_if_trx.py:109 (BTS@172.18.28.20:5700) Starting transceiver...
2026-01-29 03:28:49.002 [INFO] transceiver.py:243 Starting clock generator
2026-01-29 03:28:49.002 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-01-29 03:28:49.003 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:28:49.003 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:28:49.003 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:28:49.003 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETRXGAIN
2026-01-29 03:28:49.003 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:28:49.003 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:28:49.003 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:28:49.003 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:28:49.004 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:28:49.004 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:28:49.004 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:28:49.004 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:28:49.004 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:28:49.004 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:28:49.004 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:28:49.004 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:28:49.004 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:28:49.004 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:28:49.004 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:28:49.004 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:28:49.004 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:28:49.004 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:28:49.004 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:28:49.004 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 03:28:49.004 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:28:49.004 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:28:49.004 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:28:49.004 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:28:49.004 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 03:28:49.004 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 03:28:49.004 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 03:28:49.004 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.28.20:5700) Recv POWEROFF cmd
2026-01-29 03:28:49.004 [INFO] ctrl_if_trx.py:117 (BTS@172.18.28.20:5700) Stopping transceiver...
2026-01-29 03:28:49.004 [INFO] transceiver.py:246 Stopping clock generator
2026-01-29 03:28:54.007 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.28.20:5700) Recv POWEROFF cmd
2026-01-29 03:28:54.007 [INFO] ctrl_if_trx.py:117 (BTS@172.18.28.20:5700) Stopping transceiver...
2026-01-29 03:28:54.009 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 03:28:54.009 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 03:28:54.010 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 03:28:54.010 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 03:28:54.017 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 03:28:54.018 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.28.20:5700) Recv SETFORMAT cmd
2026-01-29 03:28:54.018 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.28.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:28:54.018 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.28.20:5700) Recv SETFORMAT cmd
2026-01-29 03:28:54.018 [INFO] ctrl_if_trx.py:201 (BTS@172.18.28.20:5700) TRXD header version 1 -> 1
2026-01-29 03:28:54.020 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.28.20:5700/1) Recv RXTUNE cmd
2026-01-29 03:28:54.020 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.28.20:5700/1) Recv TXTUNE cmd
2026-01-29 03:28:54.021 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.28.20:5700/1) Recv SETFORMAT cmd
2026-01-29 03:28:54.021 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.28.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:28:54.021 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 03:28:54.022 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.28.20:5700/1) Recv NOMTXPOWER cmd
2026-01-29 03:28:54.022 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.28.20:5700/1) Recv SETFORMAT cmd
2026-01-29 03:28:54.022 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.28.20:5700/1) TRXD header version 1 -> 1
2026-01-29 03:28:54.023 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.28.20:5700/2) Recv RXTUNE cmd
2026-01-29 03:28:54.023 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.28.20:5700/2) Recv TXTUNE cmd
2026-01-29 03:28:54.023 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.28.20:5700/2) Recv SETFORMAT cmd
2026-01-29 03:28:54.024 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.28.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:28:54.024 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 03:28:54.024 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.28.20:5700/2) Recv NOMTXPOWER cmd
2026-01-29 03:28:54.024 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.28.20:5700/2) Recv SETFORMAT cmd
2026-01-29 03:28:54.024 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.28.20:5700/2) TRXD header version 1 -> 1
2026-01-29 03:28:54.027 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.28.20:5700/3) Recv RXTUNE cmd
2026-01-29 03:28:54.027 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.28.20:5700/3) Recv TXTUNE cmd
2026-01-29 03:28:54.027 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.28.20:5700/3) Recv SETFORMAT cmd
2026-01-29 03:28:54.027 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.28.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:28:54.027 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 03:28:54.027 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.28.20:5700/3) Recv NOMTXPOWER cmd
2026-01-29 03:28:54.027 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.28.20:5700/3) Recv SETFORMAT cmd
2026-01-29 03:28:54.027 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.28.20:5700/3) TRXD header version 1 -> 1
2026-01-29 03:28:54.031 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.28.20:5700) Recv RXTUNE cmd
2026-01-29 03:28:54.031 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETTSC
2026-01-29 03:28:54.031 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETTSC
2026-01-29 03:28:54.031 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETTSC
2026-01-29 03:28:54.031 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.28.20:5700) Recv TXTUNE cmd
2026-01-29 03:28:54.031 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETRXGAIN
2026-01-29 03:28:54.031 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETRXGAIN
2026-01-29 03:28:54.031 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETRXGAIN
2026-01-29 03:28:54.031 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETTSC
2026-01-29 03:28:54.031 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:28:54.031 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:28:54.032 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:28:54.032 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.28.20:5700) Recv NOMTXPOWER cmd
2026-01-29 03:28:54.032 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:28:54.032 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:28:54.032 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:28:54.032 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.28.20:5700) Recv POWERON CMD
2026-01-29 03:28:54.032 [INFO] ctrl_if_trx.py:109 (BTS@172.18.28.20:5700) Starting transceiver...
2026-01-29 03:28:54.032 [INFO] transceiver.py:243 Starting clock generator
2026-01-29 03:28:54.032 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-01-29 03:28:54.032 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:28:54.032 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:28:54.032 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:28:54.032 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETRXGAIN
2026-01-29 03:28:54.032 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:28:54.032 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:28:54.032 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:28:54.032 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:28:54.033 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:28:54.033 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:28:54.033 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:28:54.033 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:28:54.033 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:28:54.033 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:28:54.033 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:28:54.033 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:28:54.033 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:28:54.033 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:28:54.033 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:28:54.033 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:28:54.033 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:28:54.033 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:28:54.033 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:28:54.033 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:28:54.033 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:28:54.034 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:28:54.034 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:28:54.037 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-01-29 03:28:54.521 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-01-29 03:28:54.564 [DEBUG] fake_trx.py:278 (BTS@172.18.28.20:5700) Recv FAKE_TOA cmd
2026-01-29 03:28:54.567 [DEBUG] fake_trx.py:297 (BTS@172.18.28.20:5700) Recv FAKE_RSSI cmd
2026-01-29 03:28:54.569 [DEBUG] fake_trx.py:322 (BTS@172.18.28.20:5700) Recv FAKE_CI cmd
2026-01-29 03:28:54.569 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:28:54.572 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 03:28:54.572 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 03:28:54.572 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 03:28:54.572 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 03:28:54.573 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 03:28:54.573 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 03:28:54.573 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.28.22:6700) Recv POWERON CMD
2026-01-29 03:28:54.573 [INFO] ctrl_if_trx.py:109 (MS@172.18.28.22:6700) Starting transceiver...
2026-01-29 03:28:54.624 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.28.22:6700) Recv SETFH cmd
2026-01-29 03:28:54.624 [INFO] transceiver.py:201 (MS@172.18.28.22:6700) Frequency hopping configured: hsn=2, maio=0, ma_len=2
2026-01-29 03:28:54.625 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 03:28:54.625 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 03:28:54.999 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-01-29 03:28:55.036 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 03:28:55.036 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:28:55.037 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:28:55.041 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:28:55.477 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-01-29 03:28:55.956 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-01-29 03:28:56.037 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 03:28:56.037 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:28:56.037 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:28:56.042 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:28:56.434 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-01-29 03:28:56.912 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-01-29 03:28:57.037 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 03:28:57.038 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:28:57.038 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:28:57.044 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:28:57.390 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-01-29 03:28:57.868 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-01-29 03:28:58.038 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 03:28:58.039 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:28:58.039 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:28:58.045 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:28:58.346 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-01-29 03:28:58.824 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-01-29 03:28:59.039 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 03:28:59.040 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:28:59.040 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:28:59.046 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:28:59.302 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-01-29 03:28:59.780 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-01-29 03:29:00.258 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-01-29 03:29:00.736 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-01-29 03:29:01.214 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-01-29 03:29:01.692 [DEBUG] clck_gen.py:113 IND CLOCK 1632
2026-01-29 03:29:02.170 [DEBUG] clck_gen.py:113 IND CLOCK 1734
2026-01-29 03:29:02.648 [DEBUG] clck_gen.py:113 IND CLOCK 1836
2026-01-29 03:29:03.126 [DEBUG] clck_gen.py:113 IND CLOCK 1938
2026-01-29 03:29:03.604 [DEBUG] clck_gen.py:113 IND CLOCK 2040
2026-01-29 03:29:04.082 [DEBUG] clck_gen.py:113 IND CLOCK 2142
2026-01-29 03:29:04.560 [DEBUG] clck_gen.py:113 IND CLOCK 2244
2026-01-29 03:29:05.037 [DEBUG] clck_gen.py:113 IND CLOCK 2346
2026-01-29 03:29:05.514 [DEBUG] clck_gen.py:113 IND CLOCK 2448
2026-01-29 03:29:05.993 [DEBUG] clck_gen.py:113 IND CLOCK 2550
2026-01-29 03:29:06.471 [DEBUG] clck_gen.py:113 IND CLOCK 2652
2026-01-29 03:29:06.949 [DEBUG] clck_gen.py:113 IND CLOCK 2754
2026-01-29 03:29:07.428 [DEBUG] clck_gen.py:113 IND CLOCK 2856
2026-01-29 03:29:07.906 [DEBUG] clck_gen.py:113 IND CLOCK 2958
2026-01-29 03:29:08.384 [DEBUG] clck_gen.py:113 IND CLOCK 3060
2026-01-29 03:29:08.630 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 03:29:08.630 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 03:29:08.631 [INFO] transceiver.py:205 (MS@172.18.28.22:6700) Frequency hopping disabled
2026-01-29 03:29:08.635 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 03:29:08.635 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:29:08.635 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:29:08.635 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:29:08.639 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 03:29:08.639 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 03:29:08.639 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 03:29:08.639 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.28.20:5700) Recv POWEROFF cmd
2026-01-29 03:29:08.639 [INFO] ctrl_if_trx.py:117 (BTS@172.18.28.20:5700) Stopping transceiver...
2026-01-29 03:29:08.639 [INFO] transceiver.py:246 Stopping clock generator
2026-01-29 03:29:08.640 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 03:29:08.640 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=3116 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:29:08.640 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=3116 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:29:08.640 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=3116 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:29:08.640 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=3116 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:29:08.640 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=3116 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:29:08.640 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=3116 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:29:08.640 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=3116 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:29:08.640 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=3116 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:29:08.640 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=3117 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:29:08.641 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=3117 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:29:08.641 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=3117 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:29:08.641 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=3117 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:29:08.641 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=3117 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:29:08.641 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=3117 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:29:08.641 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=3117 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:29:08.641 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=3117 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:29:13.638 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.28.20:5700) Recv POWEROFF cmd
2026-01-29 03:29:13.638 [INFO] ctrl_if_trx.py:117 (BTS@172.18.28.20:5700) Stopping transceiver...
2026-01-29 03:29:13.640 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 03:29:13.641 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 03:29:13.642 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 03:29:13.643 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 03:29:13.651 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 03:29:13.652 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.28.20:5700) Recv SETFORMAT cmd
2026-01-29 03:29:13.652 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.28.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:29:13.652 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.28.20:5700) Recv SETFORMAT cmd
2026-01-29 03:29:13.653 [INFO] ctrl_if_trx.py:201 (BTS@172.18.28.20:5700) TRXD header version 1 -> 1
2026-01-29 03:29:13.656 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.28.20:5700/1) Recv RXTUNE cmd
2026-01-29 03:29:13.656 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.28.20:5700/1) Recv TXTUNE cmd
2026-01-29 03:29:13.657 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.28.20:5700/1) Recv SETFORMAT cmd
2026-01-29 03:29:13.657 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.28.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:29:13.657 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 03:29:13.658 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.28.20:5700/1) Recv NOMTXPOWER cmd
2026-01-29 03:29:13.658 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.28.20:5700/1) Recv SETFORMAT cmd
2026-01-29 03:29:13.658 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.28.20:5700/1) TRXD header version 1 -> 1
2026-01-29 03:29:13.659 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.28.20:5700/2) Recv RXTUNE cmd
2026-01-29 03:29:13.659 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.28.20:5700/2) Recv TXTUNE cmd
2026-01-29 03:29:13.659 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.28.20:5700/2) Recv SETFORMAT cmd
2026-01-29 03:29:13.660 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.28.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:29:13.660 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 03:29:13.660 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.28.20:5700/2) Recv NOMTXPOWER cmd
2026-01-29 03:29:13.660 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.28.20:5700/2) Recv SETFORMAT cmd
2026-01-29 03:29:13.660 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.28.20:5700/2) TRXD header version 1 -> 1
2026-01-29 03:29:13.662 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.28.20:5700/3) Recv RXTUNE cmd
2026-01-29 03:29:13.662 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.28.20:5700/3) Recv TXTUNE cmd
2026-01-29 03:29:13.662 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.28.20:5700/3) Recv SETFORMAT cmd
2026-01-29 03:29:13.662 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.28.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:29:13.662 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 03:29:13.662 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.28.20:5700/3) Recv NOMTXPOWER cmd
2026-01-29 03:29:13.662 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.28.20:5700/3) Recv SETFORMAT cmd
2026-01-29 03:29:13.662 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.28.20:5700/3) TRXD header version 1 -> 1
2026-01-29 03:29:13.665 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.28.20:5700) Recv RXTUNE cmd
2026-01-29 03:29:13.665 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETTSC
2026-01-29 03:29:13.665 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETTSC
2026-01-29 03:29:13.665 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETTSC
2026-01-29 03:29:13.665 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.28.20:5700) Recv TXTUNE cmd
2026-01-29 03:29:13.665 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETRXGAIN
2026-01-29 03:29:13.665 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETRXGAIN
2026-01-29 03:29:13.665 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETRXGAIN
2026-01-29 03:29:13.665 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETTSC
2026-01-29 03:29:13.665 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:29:13.665 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:29:13.665 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.28.20:5700) Recv NOMTXPOWER cmd
2026-01-29 03:29:13.665 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:29:13.665 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:29:13.665 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:29:13.665 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.28.20:5700) Recv POWERON CMD
2026-01-29 03:29:13.665 [INFO] ctrl_if_trx.py:109 (BTS@172.18.28.20:5700) Starting transceiver...
2026-01-29 03:29:13.665 [INFO] transceiver.py:243 Starting clock generator
2026-01-29 03:29:13.666 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-01-29 03:29:13.666 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:29:13.666 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:29:13.666 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:29:13.666 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETRXGAIN
2026-01-29 03:29:13.666 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:29:13.666 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:29:13.666 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:29:13.666 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:29:13.666 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:29:13.666 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:29:13.666 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:29:13.667 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:29:13.667 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:29:13.667 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:29:13.667 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:29:13.667 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:29:13.667 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:29:13.667 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:29:13.667 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:29:13.667 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:29:13.667 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:29:13.667 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:29:13.667 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 03:29:13.667 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:29:13.667 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:29:13.667 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:29:13.667 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:29:13.667 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 03:29:13.667 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:29:13.667 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:29:13.667 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 03:29:13.667 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 03:29:13.667 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.28.20:5700) Recv POWEROFF cmd
2026-01-29 03:29:13.667 [INFO] ctrl_if_trx.py:117 (BTS@172.18.28.20:5700) Stopping transceiver...
2026-01-29 03:29:13.668 [INFO] transceiver.py:246 Stopping clock generator
2026-01-29 03:29:18.670 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.28.20:5700) Recv POWEROFF cmd
2026-01-29 03:29:18.670 [INFO] ctrl_if_trx.py:117 (BTS@172.18.28.20:5700) Stopping transceiver...
2026-01-29 03:29:18.672 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 03:29:18.673 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 03:29:18.674 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 03:29:18.674 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 03:29:18.683 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 03:29:18.684 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.28.20:5700) Recv SETFORMAT cmd
2026-01-29 03:29:18.684 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.28.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:29:18.684 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.28.20:5700) Recv SETFORMAT cmd
2026-01-29 03:29:18.684 [INFO] ctrl_if_trx.py:201 (BTS@172.18.28.20:5700) TRXD header version 1 -> 1
2026-01-29 03:29:18.688 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.28.20:5700/1) Recv RXTUNE cmd
2026-01-29 03:29:18.688 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.28.20:5700/1) Recv TXTUNE cmd
2026-01-29 03:29:18.688 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.28.20:5700/1) Recv SETFORMAT cmd
2026-01-29 03:29:18.688 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.28.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:29:18.689 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 03:29:18.689 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.28.20:5700/1) Recv NOMTXPOWER cmd
2026-01-29 03:29:18.689 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.28.20:5700/1) Recv SETFORMAT cmd
2026-01-29 03:29:18.689 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.28.20:5700/1) TRXD header version 1 -> 1
2026-01-29 03:29:18.691 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.28.20:5700/2) Recv RXTUNE cmd
2026-01-29 03:29:18.691 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.28.20:5700/2) Recv TXTUNE cmd
2026-01-29 03:29:18.691 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.28.20:5700/2) Recv SETFORMAT cmd
2026-01-29 03:29:18.691 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.28.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:29:18.692 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 03:29:18.692 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.28.20:5700/2) Recv NOMTXPOWER cmd
2026-01-29 03:29:18.692 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.28.20:5700/2) Recv SETFORMAT cmd
2026-01-29 03:29:18.692 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.28.20:5700/2) TRXD header version 1 -> 1
2026-01-29 03:29:18.694 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.28.20:5700/3) Recv RXTUNE cmd
2026-01-29 03:29:18.694 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.28.20:5700/3) Recv TXTUNE cmd
2026-01-29 03:29:18.694 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.28.20:5700/3) Recv SETFORMAT cmd
2026-01-29 03:29:18.694 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.28.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:29:18.694 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 03:29:18.694 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.28.20:5700/3) Recv NOMTXPOWER cmd
2026-01-29 03:29:18.694 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.28.20:5700/3) Recv SETFORMAT cmd
2026-01-29 03:29:18.694 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.28.20:5700/3) TRXD header version 1 -> 1
2026-01-29 03:29:18.696 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.28.20:5700) Recv RXTUNE cmd
2026-01-29 03:29:18.697 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETTSC
2026-01-29 03:29:18.697 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETTSC
2026-01-29 03:29:18.697 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETTSC
2026-01-29 03:29:18.697 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.28.20:5700) Recv TXTUNE cmd
2026-01-29 03:29:18.697 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETRXGAIN
2026-01-29 03:29:18.697 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETRXGAIN
2026-01-29 03:29:18.697 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETRXGAIN
2026-01-29 03:29:18.697 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETTSC
2026-01-29 03:29:18.697 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:29:18.697 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.28.20:5700) Recv NOMTXPOWER cmd
2026-01-29 03:29:18.697 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:29:18.697 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:29:18.697 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.28.20:5700) Recv POWERON CMD
2026-01-29 03:29:18.697 [INFO] ctrl_if_trx.py:109 (BTS@172.18.28.20:5700) Starting transceiver...
2026-01-29 03:29:18.697 [INFO] transceiver.py:243 Starting clock generator
2026-01-29 03:29:18.697 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-01-29 03:29:18.697 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:29:18.697 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:29:18.697 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:29:18.698 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETRXGAIN
2026-01-29 03:29:18.698 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:29:18.698 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:29:18.698 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:29:18.698 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:29:18.698 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:29:18.698 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:29:18.698 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:29:18.698 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:29:18.698 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:29:18.698 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:29:18.698 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:29:18.698 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:29:18.698 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:29:18.698 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:29:18.698 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:29:18.698 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:29:18.698 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:29:18.698 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:29:18.698 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:29:18.698 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:29:18.698 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:29:18.698 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:29:18.698 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:29:18.698 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:29:18.698 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:29:18.698 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:29:18.702 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-01-29 03:29:19.186 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-01-29 03:29:19.224 [DEBUG] fake_trx.py:278 (BTS@172.18.28.20:5700) Recv FAKE_TOA cmd
2026-01-29 03:29:19.226 [DEBUG] fake_trx.py:297 (BTS@172.18.28.20:5700) Recv FAKE_RSSI cmd
2026-01-29 03:29:19.227 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:29:19.227 [DEBUG] fake_trx.py:322 (BTS@172.18.28.20:5700) Recv FAKE_CI cmd
2026-01-29 03:29:19.228 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 03:29:19.229 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 03:29:19.229 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 03:29:19.229 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 03:29:19.229 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 03:29:19.230 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 03:29:19.230 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.28.22:6700) Recv POWERON CMD
2026-01-29 03:29:19.230 [INFO] ctrl_if_trx.py:109 (MS@172.18.28.22:6700) Starting transceiver...
2026-01-29 03:29:19.276 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.28.22:6700) Recv SETFH cmd
2026-01-29 03:29:19.276 [INFO] transceiver.py:201 (MS@172.18.28.22:6700) Frequency hopping configured: hsn=2, maio=0, ma_len=2
2026-01-29 03:29:19.276 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 03:29:19.277 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 03:29:19.663 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-01-29 03:29:19.700 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 03:29:19.700 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:29:19.701 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:29:19.703 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:29:20.141 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-01-29 03:29:20.620 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-01-29 03:29:20.701 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 03:29:20.701 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:29:20.701 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:29:20.704 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:29:21.098 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-01-29 03:29:21.577 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-01-29 03:29:21.702 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:29:21.702 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:29:21.703 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 03:29:21.705 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:29:22.055 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-01-29 03:29:22.533 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-01-29 03:29:22.703 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:29:22.703 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:29:22.703 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 03:29:22.705 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:29:23.011 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-01-29 03:29:23.488 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-01-29 03:29:23.704 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 03:29:23.704 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:29:23.704 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:29:23.706 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:29:23.966 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-01-29 03:29:24.444 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-01-29 03:29:24.922 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-01-29 03:29:25.399 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-01-29 03:29:25.878 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-01-29 03:29:26.356 [DEBUG] clck_gen.py:113 IND CLOCK 1632
2026-01-29 03:29:26.834 [DEBUG] clck_gen.py:113 IND CLOCK 1734
2026-01-29 03:29:27.281 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 03:29:27.281 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 03:29:27.281 [INFO] transceiver.py:205 (MS@172.18.28.22:6700) Frequency hopping disabled
2026-01-29 03:29:27.284 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 03:29:27.284 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:29:27.284 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:29:27.284 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:29:27.285 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 03:29:27.285 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 03:29:27.285 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 03:29:27.285 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 03:29:27.285 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.28.20:5700) Recv POWEROFF cmd
2026-01-29 03:29:27.285 [INFO] ctrl_if_trx.py:117 (BTS@172.18.28.20:5700) Stopping transceiver...
2026-01-29 03:29:27.285 [INFO] transceiver.py:246 Stopping clock generator
2026-01-29 03:29:32.288 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.28.20:5700) Recv POWEROFF cmd
2026-01-29 03:29:32.288 [INFO] ctrl_if_trx.py:117 (BTS@172.18.28.20:5700) Stopping transceiver...
2026-01-29 03:29:32.290 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 03:29:32.291 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 03:29:32.291 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 03:29:32.291 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 03:29:32.298 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 03:29:32.299 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.28.20:5700) Recv SETFORMAT cmd
2026-01-29 03:29:32.299 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.28.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:29:32.299 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.28.20:5700) Recv SETFORMAT cmd
2026-01-29 03:29:32.299 [INFO] ctrl_if_trx.py:201 (BTS@172.18.28.20:5700) TRXD header version 1 -> 1
2026-01-29 03:29:32.302 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.28.20:5700/1) Recv RXTUNE cmd
2026-01-29 03:29:32.302 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.28.20:5700/1) Recv TXTUNE cmd
2026-01-29 03:29:32.302 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.28.20:5700/1) Recv SETFORMAT cmd
2026-01-29 03:29:32.303 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.28.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:29:32.303 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 03:29:32.303 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.28.20:5700/1) Recv NOMTXPOWER cmd
2026-01-29 03:29:32.303 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.28.20:5700/1) Recv SETFORMAT cmd
2026-01-29 03:29:32.303 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.28.20:5700/1) TRXD header version 1 -> 1
2026-01-29 03:29:32.305 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.28.20:5700/2) Recv RXTUNE cmd
2026-01-29 03:29:32.306 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.28.20:5700/2) Recv TXTUNE cmd
2026-01-29 03:29:32.306 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.28.20:5700/2) Recv SETFORMAT cmd
2026-01-29 03:29:32.306 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.28.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:29:32.306 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 03:29:32.306 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.28.20:5700/2) Recv NOMTXPOWER cmd
2026-01-29 03:29:32.306 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.28.20:5700/2) Recv SETFORMAT cmd
2026-01-29 03:29:32.306 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.28.20:5700/2) TRXD header version 1 -> 1
2026-01-29 03:29:32.309 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.28.20:5700/3) Recv RXTUNE cmd
2026-01-29 03:29:32.309 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.28.20:5700/3) Recv TXTUNE cmd
2026-01-29 03:29:32.309 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.28.20:5700/3) Recv SETFORMAT cmd
2026-01-29 03:29:32.309 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.28.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:29:32.309 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 03:29:32.309 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.28.20:5700/3) Recv NOMTXPOWER cmd
2026-01-29 03:29:32.309 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.28.20:5700/3) Recv SETFORMAT cmd
2026-01-29 03:29:32.309 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.28.20:5700/3) TRXD header version 1 -> 1
2026-01-29 03:29:32.313 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.28.20:5700) Recv RXTUNE cmd
2026-01-29 03:29:32.313 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETTSC
2026-01-29 03:29:32.313 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETTSC
2026-01-29 03:29:32.313 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETTSC
2026-01-29 03:29:32.313 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.28.20:5700) Recv TXTUNE cmd
2026-01-29 03:29:32.313 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETRXGAIN
2026-01-29 03:29:32.313 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETRXGAIN
2026-01-29 03:29:32.313 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETRXGAIN
2026-01-29 03:29:32.313 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETTSC
2026-01-29 03:29:32.313 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:29:32.313 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:29:32.313 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.28.20:5700) Recv NOMTXPOWER cmd
2026-01-29 03:29:32.313 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:29:32.313 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:29:32.313 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:29:32.313 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.28.20:5700) Recv POWERON CMD
2026-01-29 03:29:32.314 [INFO] ctrl_if_trx.py:109 (BTS@172.18.28.20:5700) Starting transceiver...
2026-01-29 03:29:32.314 [INFO] transceiver.py:243 Starting clock generator
2026-01-29 03:29:32.314 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-01-29 03:29:32.314 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:29:32.314 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:29:32.314 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:29:32.314 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETRXGAIN
2026-01-29 03:29:32.314 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:29:32.314 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:29:32.314 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:29:32.314 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:29:32.314 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:29:32.314 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:29:32.314 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:29:32.314 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:29:32.314 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:29:32.314 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:29:32.314 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:29:32.314 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:29:32.314 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:29:32.314 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:29:32.314 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:29:32.314 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:29:32.314 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:29:32.315 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:29:32.315 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:29:32.315 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:29:32.315 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:29:32.316 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 03:29:32.316 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:29:32.316 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 03:29:32.316 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 03:29:32.316 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:29:32.316 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:29:32.316 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 03:29:32.316 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.28.20:5700) Recv POWEROFF cmd
2026-01-29 03:29:32.316 [INFO] ctrl_if_trx.py:117 (BTS@172.18.28.20:5700) Stopping transceiver...
2026-01-29 03:29:32.316 [INFO] transceiver.py:246 Stopping clock generator
2026-01-29 03:29:37.349 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.28.20:5700) Recv POWEROFF cmd
2026-01-29 03:29:37.349 [INFO] ctrl_if_trx.py:117 (BTS@172.18.28.20:5700) Stopping transceiver...
2026-01-29 03:29:37.351 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 03:29:37.352 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 03:29:37.352 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 03:29:37.352 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 03:29:37.358 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 03:29:37.360 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.28.20:5700) Recv SETFORMAT cmd
2026-01-29 03:29:37.360 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.28.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:29:37.360 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.28.20:5700) Recv SETFORMAT cmd
2026-01-29 03:29:37.361 [INFO] ctrl_if_trx.py:201 (BTS@172.18.28.20:5700) TRXD header version 1 -> 1
2026-01-29 03:29:37.363 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.28.20:5700/1) Recv RXTUNE cmd
2026-01-29 03:29:37.363 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.28.20:5700/1) Recv TXTUNE cmd
2026-01-29 03:29:37.364 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.28.20:5700/1) Recv SETFORMAT cmd
2026-01-29 03:29:37.364 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.28.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:29:37.365 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 03:29:37.365 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.28.20:5700/1) Recv NOMTXPOWER cmd
2026-01-29 03:29:37.365 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.28.20:5700/1) Recv SETFORMAT cmd
2026-01-29 03:29:37.366 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.28.20:5700/1) TRXD header version 1 -> 1
2026-01-29 03:29:37.366 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.28.20:5700/2) Recv RXTUNE cmd
2026-01-29 03:29:37.367 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.28.20:5700/2) Recv TXTUNE cmd
2026-01-29 03:29:37.367 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.28.20:5700/2) Recv SETFORMAT cmd
2026-01-29 03:29:37.367 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.28.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:29:37.368 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 03:29:37.368 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.28.20:5700/2) Recv NOMTXPOWER cmd
2026-01-29 03:29:37.368 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.28.20:5700/2) Recv SETFORMAT cmd
2026-01-29 03:29:37.368 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.28.20:5700/2) TRXD header version 1 -> 1
2026-01-29 03:29:37.369 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.28.20:5700/3) Recv RXTUNE cmd
2026-01-29 03:29:37.369 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.28.20:5700/3) Recv TXTUNE cmd
2026-01-29 03:29:37.370 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.28.20:5700/3) Recv SETFORMAT cmd
2026-01-29 03:29:37.370 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.28.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:29:37.370 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 03:29:37.370 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.28.20:5700/3) Recv NOMTXPOWER cmd
2026-01-29 03:29:37.370 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.28.20:5700/3) Recv SETFORMAT cmd
2026-01-29 03:29:37.370 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.28.20:5700/3) TRXD header version 1 -> 1
2026-01-29 03:29:37.372 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.28.20:5700) Recv RXTUNE cmd
2026-01-29 03:29:37.373 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETTSC
2026-01-29 03:29:37.373 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETTSC
2026-01-29 03:29:37.373 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETTSC
2026-01-29 03:29:37.373 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.28.20:5700) Recv TXTUNE cmd
2026-01-29 03:29:37.373 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETRXGAIN
2026-01-29 03:29:37.373 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETRXGAIN
2026-01-29 03:29:37.373 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETRXGAIN
2026-01-29 03:29:37.373 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETTSC
2026-01-29 03:29:37.373 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:29:37.373 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:29:37.373 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.28.20:5700) Recv NOMTXPOWER cmd
2026-01-29 03:29:37.373 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:29:37.373 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:29:37.373 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:29:37.373 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.28.20:5700) Recv POWERON CMD
2026-01-29 03:29:37.373 [INFO] ctrl_if_trx.py:109 (BTS@172.18.28.20:5700) Starting transceiver...
2026-01-29 03:29:37.373 [INFO] transceiver.py:243 Starting clock generator
2026-01-29 03:29:37.373 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-01-29 03:29:37.373 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:29:37.373 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:29:37.374 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:29:37.374 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETRXGAIN
2026-01-29 03:29:37.374 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:29:37.374 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:29:37.374 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:29:37.374 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:29:37.374 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:29:37.374 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:29:37.374 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:29:37.374 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:29:37.374 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:29:37.374 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:29:37.374 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:29:37.374 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:29:37.374 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:29:37.374 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:29:37.374 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:29:37.374 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:29:37.374 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:29:37.374 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:29:37.374 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:29:37.374 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:29:37.374 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:29:37.375 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:29:37.375 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:29:37.375 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:29:37.378 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-01-29 03:29:37.861 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-01-29 03:29:37.905 [DEBUG] fake_trx.py:278 (BTS@172.18.28.20:5700) Recv FAKE_TOA cmd
2026-01-29 03:29:37.908 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:29:37.909 [DEBUG] fake_trx.py:297 (BTS@172.18.28.20:5700) Recv FAKE_RSSI cmd
2026-01-29 03:29:37.911 [DEBUG] fake_trx.py:322 (BTS@172.18.28.20:5700) Recv FAKE_CI cmd
2026-01-29 03:29:37.915 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 03:29:37.915 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 03:29:37.915 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 03:29:37.916 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 03:29:37.916 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 03:29:37.917 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 03:29:37.917 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.28.22:6700) Recv POWERON CMD
2026-01-29 03:29:37.917 [INFO] ctrl_if_trx.py:109 (MS@172.18.28.22:6700) Starting transceiver...
2026-01-29 03:29:38.339 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-01-29 03:29:38.376 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 03:29:38.377 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:29:38.377 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:29:38.380 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:29:38.815 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-01-29 03:29:39.293 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-01-29 03:29:39.377 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 03:29:39.377 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:29:39.378 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:29:39.381 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:29:39.771 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-01-29 03:29:40.248 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-01-29 03:29:40.378 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 03:29:40.378 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:29:40.379 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:29:40.382 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:29:40.726 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-01-29 03:29:41.204 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-01-29 03:29:41.379 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:29:41.380 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:29:41.380 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 03:29:41.383 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:29:41.681 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-01-29 03:29:42.160 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-01-29 03:29:42.380 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 03:29:42.408 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:29:42.409 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:29:42.409 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:29:42.637 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-01-29 03:29:43.114 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-01-29 03:29:43.592 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-01-29 03:29:44.070 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-01-29 03:29:44.548 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-01-29 03:29:45.026 [DEBUG] clck_gen.py:113 IND CLOCK 1632
2026-01-29 03:29:45.504 [DEBUG] clck_gen.py:113 IND CLOCK 1734
2026-01-29 03:29:45.982 [DEBUG] clck_gen.py:113 IND CLOCK 1836
2026-01-29 03:29:46.460 [DEBUG] clck_gen.py:113 IND CLOCK 1938
2026-01-29 03:29:46.937 [DEBUG] clck_gen.py:113 IND CLOCK 2040
2026-01-29 03:29:47.415 [DEBUG] clck_gen.py:113 IND CLOCK 2142
2026-01-29 03:29:47.892 [DEBUG] clck_gen.py:113 IND CLOCK 2244
2026-01-29 03:29:47.959 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 03:29:47.959 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 03:29:47.964 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 03:29:47.964 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:29:47.964 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:29:47.964 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:29:47.966 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 03:29:47.966 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 03:29:47.966 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 03:29:47.966 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 03:29:47.966 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.28.20:5700) Recv POWEROFF cmd
2026-01-29 03:29:47.966 [INFO] ctrl_if_trx.py:117 (BTS@172.18.28.20:5700) Stopping transceiver...
2026-01-29 03:29:47.966 [INFO] transceiver.py:246 Stopping clock generator
2026-01-29 03:29:47.966 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=2262 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:29:47.966 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=2262 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:29:47.966 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=2262 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:29:47.966 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=2262 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:29:47.966 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=2262 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:29:47.966 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=2262 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:29:47.966 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=2262 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:29:52.967 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.28.20:5700) Recv POWEROFF cmd
2026-01-29 03:29:52.967 [INFO] ctrl_if_trx.py:117 (BTS@172.18.28.20:5700) Stopping transceiver...
2026-01-29 03:29:52.969 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 03:29:52.970 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 03:29:52.970 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 03:29:52.970 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 03:29:52.978 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 03:29:52.978 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.28.20:5700) Recv SETFORMAT cmd
2026-01-29 03:29:52.978 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.28.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:29:52.979 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.28.20:5700) Recv SETFORMAT cmd
2026-01-29 03:29:52.979 [INFO] ctrl_if_trx.py:201 (BTS@172.18.28.20:5700) TRXD header version 1 -> 1
2026-01-29 03:29:52.981 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.28.20:5700/1) Recv RXTUNE cmd
2026-01-29 03:29:52.981 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.28.20:5700/1) Recv TXTUNE cmd
2026-01-29 03:29:52.982 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.28.20:5700/1) Recv SETFORMAT cmd
2026-01-29 03:29:52.982 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.28.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:29:52.982 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 03:29:52.983 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.28.20:5700/1) Recv NOMTXPOWER cmd
2026-01-29 03:29:52.983 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.28.20:5700/1) Recv SETFORMAT cmd
2026-01-29 03:29:52.983 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.28.20:5700/1) TRXD header version 1 -> 1
2026-01-29 03:29:52.984 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.28.20:5700/2) Recv RXTUNE cmd
2026-01-29 03:29:52.984 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.28.20:5700/2) Recv TXTUNE cmd
2026-01-29 03:29:52.984 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.28.20:5700/2) Recv SETFORMAT cmd
2026-01-29 03:29:52.984 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.28.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:29:52.984 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 03:29:52.984 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.28.20:5700/2) Recv NOMTXPOWER cmd
2026-01-29 03:29:52.984 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.28.20:5700/2) Recv SETFORMAT cmd
2026-01-29 03:29:52.984 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.28.20:5700/2) TRXD header version 1 -> 1
2026-01-29 03:29:52.986 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.28.20:5700/3) Recv RXTUNE cmd
2026-01-29 03:29:52.986 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.28.20:5700/3) Recv TXTUNE cmd
2026-01-29 03:29:52.986 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.28.20:5700/3) Recv SETFORMAT cmd
2026-01-29 03:29:52.986 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.28.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:29:52.987 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 03:29:52.987 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.28.20:5700/3) Recv NOMTXPOWER cmd
2026-01-29 03:29:52.987 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.28.20:5700/3) Recv SETFORMAT cmd
2026-01-29 03:29:52.987 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.28.20:5700/3) TRXD header version 1 -> 1
2026-01-29 03:29:52.989 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.28.20:5700) Recv RXTUNE cmd
2026-01-29 03:29:52.989 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETTSC
2026-01-29 03:29:52.989 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETTSC
2026-01-29 03:29:52.989 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETTSC
2026-01-29 03:29:52.989 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.28.20:5700) Recv TXTUNE cmd
2026-01-29 03:29:52.989 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETRXGAIN
2026-01-29 03:29:52.989 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETRXGAIN
2026-01-29 03:29:52.989 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETRXGAIN
2026-01-29 03:29:52.989 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETTSC
2026-01-29 03:29:52.989 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:29:52.989 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:29:52.989 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.28.20:5700) Recv NOMTXPOWER cmd
2026-01-29 03:29:52.989 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:29:52.989 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:29:52.989 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.28.20:5700) Recv POWERON CMD
2026-01-29 03:29:52.989 [INFO] ctrl_if_trx.py:109 (BTS@172.18.28.20:5700) Starting transceiver...
2026-01-29 03:29:52.990 [INFO] transceiver.py:243 Starting clock generator
2026-01-29 03:29:52.990 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-01-29 03:29:52.990 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:29:52.990 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:29:52.990 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:29:52.990 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETRXGAIN
2026-01-29 03:29:52.991 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:29:52.991 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:29:52.991 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:29:52.991 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:29:52.991 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:29:52.991 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:29:52.991 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:29:52.991 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:29:52.991 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:29:52.991 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:29:52.991 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:29:52.991 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:29:52.991 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:29:52.991 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:29:52.991 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:29:52.991 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:29:52.991 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:29:52.991 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 03:29:52.991 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:29:52.991 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:29:52.991 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:29:52.991 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:29:52.991 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:29:52.991 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 03:29:52.991 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:29:52.991 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.28.20:5700) Recv POWEROFF cmd
2026-01-29 03:29:52.991 [INFO] ctrl_if_trx.py:117 (BTS@172.18.28.20:5700) Stopping transceiver...
2026-01-29 03:29:52.991 [INFO] transceiver.py:246 Stopping clock generator
2026-01-29 03:29:52.991 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:29:52.992 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:29:57.994 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.28.20:5700) Recv POWEROFF cmd
2026-01-29 03:29:57.994 [INFO] ctrl_if_trx.py:117 (BTS@172.18.28.20:5700) Stopping transceiver...
2026-01-29 03:29:57.995 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 03:29:57.997 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 03:29:57.999 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 03:29:57.999 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 03:29:58.012 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 03:29:58.013 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.28.20:5700) Recv SETFORMAT cmd
2026-01-29 03:29:58.013 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.28.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:29:58.013 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.28.20:5700) Recv SETFORMAT cmd
2026-01-29 03:29:58.013 [INFO] ctrl_if_trx.py:201 (BTS@172.18.28.20:5700) TRXD header version 1 -> 1
2026-01-29 03:29:58.015 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.28.20:5700/1) Recv RXTUNE cmd
2026-01-29 03:29:58.015 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.28.20:5700/1) Recv TXTUNE cmd
2026-01-29 03:29:58.015 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.28.20:5700/1) Recv SETFORMAT cmd
2026-01-29 03:29:58.015 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.28.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:29:58.015 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 03:29:58.015 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.28.20:5700/1) Recv NOMTXPOWER cmd
2026-01-29 03:29:58.016 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.28.20:5700/1) Recv SETFORMAT cmd
2026-01-29 03:29:58.016 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.28.20:5700/1) TRXD header version 1 -> 1
2026-01-29 03:29:58.017 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.28.20:5700/2) Recv RXTUNE cmd
2026-01-29 03:29:58.017 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.28.20:5700/2) Recv TXTUNE cmd
2026-01-29 03:29:58.017 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.28.20:5700/2) Recv SETFORMAT cmd
2026-01-29 03:29:58.017 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.28.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:29:58.017 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.28.20:5700/2) Recv NOMTXPOWER cmd
2026-01-29 03:29:58.018 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 03:29:58.018 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.28.20:5700/2) Recv SETFORMAT cmd
2026-01-29 03:29:58.018 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.28.20:5700/2) TRXD header version 1 -> 1
2026-01-29 03:29:58.019 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.28.20:5700/3) Recv RXTUNE cmd
2026-01-29 03:29:58.019 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.28.20:5700/3) Recv TXTUNE cmd
2026-01-29 03:29:58.019 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.28.20:5700/3) Recv SETFORMAT cmd
2026-01-29 03:29:58.019 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.28.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:29:58.019 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 03:29:58.019 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.28.20:5700/3) Recv NOMTXPOWER cmd
2026-01-29 03:29:58.019 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.28.20:5700/3) Recv SETFORMAT cmd
2026-01-29 03:29:58.019 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.28.20:5700/3) TRXD header version 1 -> 1
2026-01-29 03:29:58.021 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.28.20:5700) Recv RXTUNE cmd
2026-01-29 03:29:58.021 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETTSC
2026-01-29 03:29:58.021 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETTSC
2026-01-29 03:29:58.021 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETTSC
2026-01-29 03:29:58.021 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.28.20:5700) Recv TXTUNE cmd
2026-01-29 03:29:58.021 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETRXGAIN
2026-01-29 03:29:58.021 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETRXGAIN
2026-01-29 03:29:58.021 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETRXGAIN
2026-01-29 03:29:58.021 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETTSC
2026-01-29 03:29:58.021 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:29:58.021 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:29:58.021 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.28.20:5700) Recv NOMTXPOWER cmd
2026-01-29 03:29:58.021 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:29:58.021 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:29:58.021 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.28.20:5700) Recv POWERON CMD
2026-01-29 03:29:58.021 [INFO] ctrl_if_trx.py:109 (BTS@172.18.28.20:5700) Starting transceiver...
2026-01-29 03:29:58.021 [INFO] transceiver.py:243 Starting clock generator
2026-01-29 03:29:58.021 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-01-29 03:29:58.021 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:29:58.021 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:29:58.021 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:29:58.021 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETRXGAIN
2026-01-29 03:29:58.021 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:29:58.022 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:29:58.022 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:29:58.022 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:29:58.022 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:29:58.022 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:29:58.022 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:29:58.022 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:29:58.022 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:29:58.022 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:29:58.022 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:29:58.022 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:29:58.022 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:29:58.022 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:29:58.022 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:29:58.022 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:29:58.022 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:29:58.022 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:29:58.022 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:29:58.022 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:29:58.022 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:29:58.022 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:29:58.022 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:29:58.022 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:29:58.022 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:29:58.026 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-01-29 03:29:58.509 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-01-29 03:29:58.548 [DEBUG] fake_trx.py:278 (BTS@172.18.28.20:5700) Recv FAKE_TOA cmd
2026-01-29 03:29:58.551 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:29:58.551 [DEBUG] fake_trx.py:297 (BTS@172.18.28.20:5700) Recv FAKE_RSSI cmd
2026-01-29 03:29:58.554 [DEBUG] fake_trx.py:322 (BTS@172.18.28.20:5700) Recv FAKE_CI cmd
2026-01-29 03:29:58.557 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 03:29:58.557 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 03:29:58.557 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 03:29:58.558 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 03:29:58.558 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 03:29:58.558 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 03:29:58.558 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.28.22:6700) Recv POWERON CMD
2026-01-29 03:29:58.558 [INFO] ctrl_if_trx.py:109 (MS@172.18.28.22:6700) Starting transceiver...
2026-01-29 03:29:58.599 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.28.22:6700) Recv SETFH cmd
2026-01-29 03:29:58.599 [INFO] transceiver.py:201 (MS@172.18.28.22:6700) Frequency hopping configured: hsn=2, maio=0, ma_len=2
2026-01-29 03:29:58.600 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 03:29:58.600 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 03:29:58.987 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-01-29 03:29:59.024 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:29:59.024 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 03:29:59.025 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:29:59.025 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:29:59.465 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-01-29 03:29:59.943 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-01-29 03:30:00.025 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:30:00.025 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 03:30:00.025 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:30:00.025 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:30:00.420 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-01-29 03:30:00.899 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-01-29 03:30:01.026 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:30:01.026 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:30:01.026 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 03:30:01.026 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:30:01.376 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-01-29 03:30:01.853 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-01-29 03:30:02.027 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:30:02.028 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 03:30:02.028 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:30:02.028 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:30:02.323 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-01-29 03:30:02.792 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-01-29 03:30:03.028 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:30:03.028 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 03:30:03.028 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:30:03.028 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:30:03.261 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-01-29 03:30:03.732 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-01-29 03:30:04.202 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-01-29 03:30:04.672 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-01-29 03:30:05.141 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-01-29 03:30:05.611 [DEBUG] clck_gen.py:113 IND CLOCK 1632
2026-01-29 03:30:06.083 [DEBUG] clck_gen.py:113 IND CLOCK 1734
2026-01-29 03:30:06.553 [DEBUG] clck_gen.py:113 IND CLOCK 1836
2026-01-29 03:30:07.026 [DEBUG] clck_gen.py:113 IND CLOCK 1938
2026-01-29 03:30:07.495 [DEBUG] clck_gen.py:113 IND CLOCK 2040
2026-01-29 03:30:07.965 [DEBUG] clck_gen.py:113 IND CLOCK 2142
2026-01-29 03:30:08.438 [DEBUG] clck_gen.py:113 IND CLOCK 2244
2026-01-29 03:30:08.908 [DEBUG] clck_gen.py:113 IND CLOCK 2346
2026-01-29 03:30:09.377 [DEBUG] clck_gen.py:113 IND CLOCK 2448
2026-01-29 03:30:09.601 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 03:30:09.601 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 03:30:09.601 [INFO] transceiver.py:205 (MS@172.18.28.22:6700) Frequency hopping disabled
2026-01-29 03:30:09.602 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 03:30:09.602 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:30:09.602 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:30:09.602 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:30:09.603 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 03:30:09.604 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 03:30:09.604 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 03:30:09.604 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 03:30:09.604 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.28.20:5700) Recv POWEROFF cmd
2026-01-29 03:30:09.604 [INFO] ctrl_if_trx.py:117 (BTS@172.18.28.20:5700) Stopping transceiver...
2026-01-29 03:30:09.604 [INFO] transceiver.py:246 Stopping clock generator
2026-01-29 03:30:09.604 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=2499 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:30:09.604 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=2499 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:30:09.604 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=2499 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:30:09.604 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=2499 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:30:09.604 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=2499 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:30:09.604 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=2499 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:30:09.604 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=2499 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:30:14.605 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.28.20:5700) Recv POWEROFF cmd
2026-01-29 03:30:14.605 [INFO] ctrl_if_trx.py:117 (BTS@172.18.28.20:5700) Stopping transceiver...
2026-01-29 03:30:14.609 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 03:30:14.609 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 03:30:14.609 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 03:30:14.609 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 03:30:14.617 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 03:30:14.617 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.28.20:5700) Recv SETFORMAT cmd
2026-01-29 03:30:14.617 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.28.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:30:14.618 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.28.20:5700) Recv SETFORMAT cmd
2026-01-29 03:30:14.618 [INFO] ctrl_if_trx.py:201 (BTS@172.18.28.20:5700) TRXD header version 1 -> 1
2026-01-29 03:30:14.621 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.28.20:5700/1) Recv RXTUNE cmd
2026-01-29 03:30:14.621 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.28.20:5700/1) Recv TXTUNE cmd
2026-01-29 03:30:14.621 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.28.20:5700/1) Recv SETFORMAT cmd
2026-01-29 03:30:14.621 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.28.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:30:14.622 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 03:30:14.622 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.28.20:5700/1) Recv NOMTXPOWER cmd
2026-01-29 03:30:14.622 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.28.20:5700/1) Recv SETFORMAT cmd
2026-01-29 03:30:14.622 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.28.20:5700/1) TRXD header version 1 -> 1
2026-01-29 03:30:14.624 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.28.20:5700/2) Recv RXTUNE cmd
2026-01-29 03:30:14.624 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.28.20:5700/2) Recv TXTUNE cmd
2026-01-29 03:30:14.624 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.28.20:5700/2) Recv SETFORMAT cmd
2026-01-29 03:30:14.624 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.28.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:30:14.624 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 03:30:14.624 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.28.20:5700/2) Recv NOMTXPOWER cmd
2026-01-29 03:30:14.624 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.28.20:5700/2) Recv SETFORMAT cmd
2026-01-29 03:30:14.624 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.28.20:5700/2) TRXD header version 1 -> 1
2026-01-29 03:30:14.626 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.28.20:5700/3) Recv RXTUNE cmd
2026-01-29 03:30:14.626 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.28.20:5700/3) Recv TXTUNE cmd
2026-01-29 03:30:14.626 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.28.20:5700/3) Recv SETFORMAT cmd
2026-01-29 03:30:14.626 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.28.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:30:14.626 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 03:30:14.626 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.28.20:5700/3) Recv NOMTXPOWER cmd
2026-01-29 03:30:14.626 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.28.20:5700/3) Recv SETFORMAT cmd
2026-01-29 03:30:14.626 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.28.20:5700/3) TRXD header version 1 -> 1
2026-01-29 03:30:14.629 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.28.20:5700) Recv RXTUNE cmd
2026-01-29 03:30:14.629 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETTSC
2026-01-29 03:30:14.629 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETTSC
2026-01-29 03:30:14.629 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETTSC
2026-01-29 03:30:14.629 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.28.20:5700) Recv TXTUNE cmd
2026-01-29 03:30:14.629 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETRXGAIN
2026-01-29 03:30:14.629 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETRXGAIN
2026-01-29 03:30:14.629 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETRXGAIN
2026-01-29 03:30:14.629 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETTSC
2026-01-29 03:30:14.629 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:30:14.629 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:30:14.630 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:30:14.630 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.28.20:5700) Recv NOMTXPOWER cmd
2026-01-29 03:30:14.630 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:30:14.630 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:30:14.630 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:30:14.630 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.28.20:5700) Recv POWERON CMD
2026-01-29 03:30:14.630 [INFO] ctrl_if_trx.py:109 (BTS@172.18.28.20:5700) Starting transceiver...
2026-01-29 03:30:14.630 [INFO] transceiver.py:243 Starting clock generator
2026-01-29 03:30:14.630 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-01-29 03:30:14.630 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:30:14.630 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:30:14.630 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:30:14.630 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETRXGAIN
2026-01-29 03:30:14.630 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:30:14.630 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:30:14.630 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:30:14.630 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:30:14.630 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:30:14.630 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:30:14.630 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:30:14.630 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:30:14.631 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:30:14.631 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:30:14.631 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:30:14.631 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:30:14.631 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:30:14.631 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:30:14.631 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:30:14.631 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:30:14.631 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:30:14.631 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:30:14.631 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:30:14.631 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:30:14.631 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:30:14.632 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 03:30:14.632 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:30:14.632 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:30:14.632 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 03:30:14.632 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 03:30:14.632 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 03:30:14.632 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.28.20:5700) Recv POWEROFF cmd
2026-01-29 03:30:14.632 [INFO] ctrl_if_trx.py:117 (BTS@172.18.28.20:5700) Stopping transceiver...
2026-01-29 03:30:14.632 [INFO] transceiver.py:246 Stopping clock generator
2026-01-29 03:30:19.639 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.28.20:5700) Recv POWEROFF cmd
2026-01-29 03:30:19.639 [INFO] ctrl_if_trx.py:117 (BTS@172.18.28.20:5700) Stopping transceiver...
2026-01-29 03:30:19.640 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 03:30:19.640 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 03:30:19.640 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 03:30:19.640 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 03:30:19.652 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 03:30:19.653 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.28.20:5700) Recv SETFORMAT cmd
2026-01-29 03:30:19.653 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.28.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:30:19.653 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.28.20:5700) Recv SETFORMAT cmd
2026-01-29 03:30:19.653 [INFO] ctrl_if_trx.py:201 (BTS@172.18.28.20:5700) TRXD header version 1 -> 1
2026-01-29 03:30:19.654 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.28.20:5700/1) Recv RXTUNE cmd
2026-01-29 03:30:19.654 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.28.20:5700/1) Recv TXTUNE cmd
2026-01-29 03:30:19.654 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.28.20:5700/1) Recv SETFORMAT cmd
2026-01-29 03:30:19.654 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.28.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:30:19.654 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 03:30:19.655 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.28.20:5700/1) Recv NOMTXPOWER cmd
2026-01-29 03:30:19.655 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.28.20:5700/1) Recv SETFORMAT cmd
2026-01-29 03:30:19.655 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.28.20:5700/1) TRXD header version 1 -> 1
2026-01-29 03:30:19.656 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.28.20:5700/2) Recv RXTUNE cmd
2026-01-29 03:30:19.656 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.28.20:5700/2) Recv TXTUNE cmd
2026-01-29 03:30:19.656 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.28.20:5700/2) Recv SETFORMAT cmd
2026-01-29 03:30:19.656 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.28.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:30:19.656 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 03:30:19.656 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.28.20:5700/2) Recv NOMTXPOWER cmd
2026-01-29 03:30:19.657 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.28.20:5700/2) Recv SETFORMAT cmd
2026-01-29 03:30:19.657 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.28.20:5700/2) TRXD header version 1 -> 1
2026-01-29 03:30:19.657 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.28.20:5700/3) Recv RXTUNE cmd
2026-01-29 03:30:19.657 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.28.20:5700/3) Recv TXTUNE cmd
2026-01-29 03:30:19.657 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.28.20:5700/3) Recv SETFORMAT cmd
2026-01-29 03:30:19.657 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.28.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:30:19.657 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 03:30:19.657 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.28.20:5700/3) Recv NOMTXPOWER cmd
2026-01-29 03:30:19.657 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.28.20:5700/3) Recv SETFORMAT cmd
2026-01-29 03:30:19.657 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.28.20:5700/3) TRXD header version 1 -> 1
2026-01-29 03:30:19.659 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.28.20:5700) Recv RXTUNE cmd
2026-01-29 03:30:19.659 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETTSC
2026-01-29 03:30:19.659 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETTSC
2026-01-29 03:30:19.659 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETTSC
2026-01-29 03:30:19.659 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.28.20:5700) Recv TXTUNE cmd
2026-01-29 03:30:19.659 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETRXGAIN
2026-01-29 03:30:19.659 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETRXGAIN
2026-01-29 03:30:19.659 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETRXGAIN
2026-01-29 03:30:19.659 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETTSC
2026-01-29 03:30:19.659 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:30:19.659 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:30:19.659 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:30:19.659 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.28.20:5700) Recv NOMTXPOWER cmd
2026-01-29 03:30:19.659 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:30:19.659 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:30:19.659 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:30:19.659 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.28.20:5700) Recv POWERON CMD
2026-01-29 03:30:19.659 [INFO] ctrl_if_trx.py:109 (BTS@172.18.28.20:5700) Starting transceiver...
2026-01-29 03:30:19.659 [INFO] transceiver.py:243 Starting clock generator
2026-01-29 03:30:19.659 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-01-29 03:30:19.660 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:30:19.660 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:30:19.660 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:30:19.660 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETRXGAIN
2026-01-29 03:30:19.660 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:30:19.660 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:30:19.660 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:30:19.660 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:30:19.660 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:30:19.660 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:30:19.660 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:30:19.660 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:30:19.660 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:30:19.660 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:30:19.660 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:30:19.660 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:30:19.660 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:30:19.660 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:30:19.660 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:30:19.660 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:30:19.660 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:30:19.660 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:30:19.660 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:30:19.660 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:30:19.660 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:30:19.660 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:30:19.660 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:30:19.664 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-01-29 03:30:20.134 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-01-29 03:30:20.194 [DEBUG] fake_trx.py:278 (BTS@172.18.28.20:5700) Recv FAKE_TOA cmd
2026-01-29 03:30:20.195 [DEBUG] fake_trx.py:297 (BTS@172.18.28.20:5700) Recv FAKE_RSSI cmd
2026-01-29 03:30:20.196 [DEBUG] fake_trx.py:322 (BTS@172.18.28.20:5700) Recv FAKE_CI cmd
2026-01-29 03:30:20.197 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:30:20.604 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-01-29 03:30:20.662 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:30:20.663 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 03:30:20.663 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:30:20.666 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:30:21.072 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-01-29 03:30:21.543 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-01-29 03:30:21.664 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:30:21.664 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 03:30:21.664 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:30:21.667 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:30:22.017 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-01-29 03:30:22.486 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-01-29 03:30:22.665 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:30:22.666 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 03:30:22.666 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:30:22.667 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:30:22.955 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-01-29 03:30:23.424 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-01-29 03:30:23.667 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:30:23.667 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 03:30:23.667 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:30:23.669 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:30:23.893 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-01-29 03:30:24.363 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-01-29 03:30:24.669 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:30:24.669 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 03:30:24.669 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:30:24.669 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:30:24.834 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-01-29 03:30:25.307 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-01-29 03:30:25.785 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-01-29 03:30:26.258 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-01-29 03:30:26.736 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-01-29 03:30:27.213 [DEBUG] clck_gen.py:113 IND CLOCK 1632
2026-01-29 03:30:27.685 [DEBUG] clck_gen.py:113 IND CLOCK 1734
2026-01-29 03:30:28.163 [DEBUG] clck_gen.py:113 IND CLOCK 1836
2026-01-29 03:30:28.638 [DEBUG] clck_gen.py:113 IND CLOCK 1938
2026-01-29 03:30:29.107 [DEBUG] clck_gen.py:113 IND CLOCK 2040
2026-01-29 03:30:29.579 [DEBUG] clck_gen.py:113 IND CLOCK 2142
2026-01-29 03:30:30.061 [DEBUG] clck_gen.py:113 IND CLOCK 2244
2026-01-29 03:30:30.205 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 03:30:30.205 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:30:30.205 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:30:30.205 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:30:30.205 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 03:30:30.205 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 03:30:30.206 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 03:30:30.206 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 03:30:30.206 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.28.20:5700) Recv POWEROFF cmd
2026-01-29 03:30:30.206 [INFO] ctrl_if_trx.py:117 (BTS@172.18.28.20:5700) Stopping transceiver...
2026-01-29 03:30:30.206 [INFO] transceiver.py:246 Stopping clock generator
2026-01-29 03:30:30.206 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=2277 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:30:30.206 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=2277 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:30:30.206 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=2277 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:30:30.206 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=2277 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:30:30.206 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=2277 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:30:30.206 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=2277 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:30:35.211 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.28.20:5700) Recv POWEROFF cmd
2026-01-29 03:30:35.212 [INFO] ctrl_if_trx.py:117 (BTS@172.18.28.20:5700) Stopping transceiver...
2026-01-29 03:30:35.212 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 03:30:35.212 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 03:30:35.212 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 03:30:35.212 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 03:30:35.225 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 03:30:35.225 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.28.20:5700) Recv SETFORMAT cmd
2026-01-29 03:30:35.225 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.28.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:30:35.226 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.28.20:5700) Recv SETFORMAT cmd
2026-01-29 03:30:35.226 [INFO] ctrl_if_trx.py:201 (BTS@172.18.28.20:5700) TRXD header version 1 -> 1
2026-01-29 03:30:35.228 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.28.20:5700/1) Recv RXTUNE cmd
2026-01-29 03:30:35.228 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.28.20:5700/1) Recv TXTUNE cmd
2026-01-29 03:30:35.228 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.28.20:5700/1) Recv SETFORMAT cmd
2026-01-29 03:30:35.228 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.28.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:30:35.228 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 03:30:35.228 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.28.20:5700/1) Recv NOMTXPOWER cmd
2026-01-29 03:30:35.228 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.28.20:5700/1) Recv SETFORMAT cmd
2026-01-29 03:30:35.228 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.28.20:5700/1) TRXD header version 1 -> 1
2026-01-29 03:30:35.230 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.28.20:5700/2) Recv RXTUNE cmd
2026-01-29 03:30:35.230 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.28.20:5700/2) Recv TXTUNE cmd
2026-01-29 03:30:35.230 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.28.20:5700/2) Recv SETFORMAT cmd
2026-01-29 03:30:35.230 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.28.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:30:35.230 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 03:30:35.230 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.28.20:5700/2) Recv NOMTXPOWER cmd
2026-01-29 03:30:35.230 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.28.20:5700/2) Recv SETFORMAT cmd
2026-01-29 03:30:35.230 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.28.20:5700/2) TRXD header version 1 -> 1
2026-01-29 03:30:35.232 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.28.20:5700/3) Recv RXTUNE cmd
2026-01-29 03:30:35.232 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.28.20:5700/3) Recv TXTUNE cmd
2026-01-29 03:30:35.232 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.28.20:5700/3) Recv SETFORMAT cmd
2026-01-29 03:30:35.232 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.28.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:30:35.232 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 03:30:35.232 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.28.20:5700/3) Recv NOMTXPOWER cmd
2026-01-29 03:30:35.232 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.28.20:5700/3) Recv SETFORMAT cmd
2026-01-29 03:30:35.232 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.28.20:5700/3) TRXD header version 1 -> 1
2026-01-29 03:30:35.235 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.28.20:5700) Recv RXTUNE cmd
2026-01-29 03:30:35.235 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETTSC
2026-01-29 03:30:35.235 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETTSC
2026-01-29 03:30:35.235 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETTSC
2026-01-29 03:30:35.235 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.28.20:5700) Recv TXTUNE cmd
2026-01-29 03:30:35.235 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETRXGAIN
2026-01-29 03:30:35.235 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETRXGAIN
2026-01-29 03:30:35.235 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETRXGAIN
2026-01-29 03:30:35.235 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETTSC
2026-01-29 03:30:35.235 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:30:35.235 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:30:35.235 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:30:35.235 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.28.20:5700) Recv NOMTXPOWER cmd
2026-01-29 03:30:35.235 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:30:35.235 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:30:35.235 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:30:35.235 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.28.20:5700) Recv POWERON CMD
2026-01-29 03:30:35.235 [INFO] ctrl_if_trx.py:109 (BTS@172.18.28.20:5700) Starting transceiver...
2026-01-29 03:30:35.235 [INFO] transceiver.py:243 Starting clock generator
2026-01-29 03:30:35.235 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-01-29 03:30:35.235 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:30:35.236 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:30:35.236 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:30:35.236 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETRXGAIN
2026-01-29 03:30:35.236 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:30:35.236 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:30:35.236 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:30:35.236 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:30:35.236 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:30:35.236 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:30:35.237 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:30:35.237 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:30:35.237 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:30:35.237 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:30:35.237 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:30:35.237 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:30:35.237 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:30:35.237 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:30:35.237 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:30:35.237 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 03:30:35.237 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:30:35.237 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:30:35.237 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:30:35.237 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:30:35.237 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:30:35.237 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:30:35.237 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:30:35.237 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 03:30:35.237 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:30:35.237 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.28.20:5700) Recv POWEROFF cmd
2026-01-29 03:30:35.237 [INFO] ctrl_if_trx.py:117 (BTS@172.18.28.20:5700) Stopping transceiver...
2026-01-29 03:30:35.237 [INFO] transceiver.py:246 Stopping clock generator
2026-01-29 03:30:35.237 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 03:30:35.237 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 03:30:40.240 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.28.20:5700) Recv POWEROFF cmd
2026-01-29 03:30:40.240 [INFO] ctrl_if_trx.py:117 (BTS@172.18.28.20:5700) Stopping transceiver...
2026-01-29 03:30:40.242 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 03:30:40.243 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 03:30:40.244 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 03:30:40.244 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 03:30:40.253 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 03:30:40.255 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.28.20:5700) Recv SETFORMAT cmd
2026-01-29 03:30:40.255 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.28.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:30:40.255 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.28.20:5700) Recv SETFORMAT cmd
2026-01-29 03:30:40.255 [INFO] ctrl_if_trx.py:201 (BTS@172.18.28.20:5700) TRXD header version 1 -> 1
2026-01-29 03:30:40.259 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.28.20:5700/1) Recv RXTUNE cmd
2026-01-29 03:30:40.260 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.28.20:5700/1) Recv TXTUNE cmd
2026-01-29 03:30:40.260 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.28.20:5700/1) Recv SETFORMAT cmd
2026-01-29 03:30:40.260 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.28.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:30:40.261 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 03:30:40.261 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.28.20:5700/1) Recv NOMTXPOWER cmd
2026-01-29 03:30:40.262 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.28.20:5700/1) Recv SETFORMAT cmd
2026-01-29 03:30:40.262 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.28.20:5700/1) TRXD header version 1 -> 1
2026-01-29 03:30:40.263 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.28.20:5700/2) Recv RXTUNE cmd
2026-01-29 03:30:40.263 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.28.20:5700/2) Recv TXTUNE cmd
2026-01-29 03:30:40.263 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.28.20:5700/2) Recv SETFORMAT cmd
2026-01-29 03:30:40.263 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.28.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:30:40.264 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 03:30:40.264 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.28.20:5700/2) Recv NOMTXPOWER cmd
2026-01-29 03:30:40.264 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.28.20:5700/2) Recv SETFORMAT cmd
2026-01-29 03:30:40.264 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.28.20:5700/2) TRXD header version 1 -> 1
2026-01-29 03:30:40.266 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.28.20:5700/3) Recv RXTUNE cmd
2026-01-29 03:30:40.266 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.28.20:5700/3) Recv TXTUNE cmd
2026-01-29 03:30:40.267 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.28.20:5700/3) Recv SETFORMAT cmd
2026-01-29 03:30:40.267 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.28.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:30:40.267 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 03:30:40.267 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.28.20:5700/3) Recv NOMTXPOWER cmd
2026-01-29 03:30:40.267 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.28.20:5700/3) Recv SETFORMAT cmd
2026-01-29 03:30:40.267 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.28.20:5700/3) TRXD header version 1 -> 1
2026-01-29 03:30:40.270 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.28.20:5700) Recv RXTUNE cmd
2026-01-29 03:30:40.270 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETTSC
2026-01-29 03:30:40.270 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETTSC
2026-01-29 03:30:40.270 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETTSC
2026-01-29 03:30:40.270 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.28.20:5700) Recv TXTUNE cmd
2026-01-29 03:30:40.271 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETRXGAIN
2026-01-29 03:30:40.271 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETRXGAIN
2026-01-29 03:30:40.271 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETRXGAIN
2026-01-29 03:30:40.271 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETTSC
2026-01-29 03:30:40.271 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:30:40.271 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:30:40.271 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:30:40.271 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.28.20:5700) Recv NOMTXPOWER cmd
2026-01-29 03:30:40.271 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:30:40.271 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:30:40.271 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:30:40.271 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.28.20:5700) Recv POWERON CMD
2026-01-29 03:30:40.271 [INFO] ctrl_if_trx.py:109 (BTS@172.18.28.20:5700) Starting transceiver...
2026-01-29 03:30:40.271 [INFO] transceiver.py:243 Starting clock generator
2026-01-29 03:30:40.271 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-01-29 03:30:40.271 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:30:40.272 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:30:40.272 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:30:40.272 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETRXGAIN
2026-01-29 03:30:40.272 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:30:40.272 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:30:40.272 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:30:40.272 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:30:40.272 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:30:40.272 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:30:40.272 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:30:40.272 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:30:40.272 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:30:40.272 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:30:40.272 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:30:40.272 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:30:40.272 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:30:40.272 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:30:40.272 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:30:40.273 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:30:40.273 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:30:40.273 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:30:40.273 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:30:40.273 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:30:40.273 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:30:40.273 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:30:40.273 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:30:40.276 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-01-29 03:30:40.757 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-01-29 03:30:40.805 [DEBUG] fake_trx.py:278 (BTS@172.18.28.20:5700) Recv FAKE_TOA cmd
2026-01-29 03:30:40.807 [DEBUG] fake_trx.py:297 (BTS@172.18.28.20:5700) Recv FAKE_RSSI cmd
2026-01-29 03:30:40.809 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:30:40.810 [DEBUG] fake_trx.py:322 (BTS@172.18.28.20:5700) Recv FAKE_CI cmd
2026-01-29 03:30:41.233 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-01-29 03:30:41.274 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 03:30:41.276 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:30:41.277 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:30:41.280 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:30:41.709 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-01-29 03:30:42.188 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-01-29 03:30:42.276 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 03:30:42.276 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:30:42.277 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:30:42.281 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:30:42.670 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-01-29 03:30:43.151 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-01-29 03:30:43.277 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 03:30:43.277 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:30:43.278 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:30:43.306 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:30:43.630 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-01-29 03:30:44.108 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-01-29 03:30:44.278 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 03:30:44.279 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:30:44.279 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:30:44.307 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:30:44.589 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-01-29 03:30:45.058 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-01-29 03:30:45.280 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:30:45.280 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 03:30:45.280 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:30:45.308 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:30:45.527 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-01-29 03:30:45.998 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-01-29 03:30:46.469 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-01-29 03:30:46.945 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-01-29 03:30:47.413 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-01-29 03:30:47.883 [DEBUG] clck_gen.py:113 IND CLOCK 1632
2026-01-29 03:30:48.361 [DEBUG] clck_gen.py:113 IND CLOCK 1734
2026-01-29 03:30:48.839 [DEBUG] clck_gen.py:113 IND CLOCK 1836
2026-01-29 03:30:49.318 [DEBUG] clck_gen.py:113 IND CLOCK 1938
2026-01-29 03:30:49.796 [DEBUG] clck_gen.py:113 IND CLOCK 2040
2026-01-29 03:30:50.275 [DEBUG] clck_gen.py:113 IND CLOCK 2142
2026-01-29 03:30:50.756 [DEBUG] clck_gen.py:113 IND CLOCK 2244
2026-01-29 03:30:51.237 [DEBUG] clck_gen.py:113 IND CLOCK 2346
2026-01-29 03:30:51.719 [DEBUG] clck_gen.py:113 IND CLOCK 2448
2026-01-29 03:30:52.192 [DEBUG] clck_gen.py:113 IND CLOCK 2550
2026-01-29 03:30:52.661 [DEBUG] clck_gen.py:113 IND CLOCK 2652
2026-01-29 03:30:52.825 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 03:30:52.825 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:30:52.826 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:30:52.826 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:30:52.828 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 03:30:52.828 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 03:30:52.828 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 03:30:52.828 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 03:30:52.828 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.28.20:5700) Recv POWEROFF cmd
2026-01-29 03:30:52.828 [INFO] ctrl_if_trx.py:117 (BTS@172.18.28.20:5700) Stopping transceiver...
2026-01-29 03:30:52.828 [INFO] transceiver.py:246 Stopping clock generator
2026-01-29 03:30:52.828 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=2689 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:30:52.828 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=2689 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:30:52.829 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=2689 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:30:52.829 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=2689 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:30:52.829 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=2689 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:30:52.829 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=2689 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:30:52.829 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=2690 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:30:52.829 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=2690 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:30:52.829 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=2690 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:30:52.829 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=2690 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:30:52.829 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=2690 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:30:52.829 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=2690 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:30:52.829 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=2690 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:30:52.829 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=2690 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:30:57.828 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.28.20:5700) Recv POWEROFF cmd
2026-01-29 03:30:57.829 [INFO] ctrl_if_trx.py:117 (BTS@172.18.28.20:5700) Stopping transceiver...
2026-01-29 03:30:57.830 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 03:30:57.831 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 03:30:57.831 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 03:30:57.832 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 03:30:57.838 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 03:30:57.840 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.28.20:5700) Recv SETFORMAT cmd
2026-01-29 03:30:57.840 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.28.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:30:57.840 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.28.20:5700) Recv SETFORMAT cmd
2026-01-29 03:30:57.840 [INFO] ctrl_if_trx.py:201 (BTS@172.18.28.20:5700) TRXD header version 1 -> 1
2026-01-29 03:30:57.843 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.28.20:5700/1) Recv RXTUNE cmd
2026-01-29 03:30:57.843 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.28.20:5700/1) Recv TXTUNE cmd
2026-01-29 03:30:57.843 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.28.20:5700/1) Recv SETFORMAT cmd
2026-01-29 03:30:57.843 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.28.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:30:57.843 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 03:30:57.843 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.28.20:5700/1) Recv NOMTXPOWER cmd
2026-01-29 03:30:57.843 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.28.20:5700/1) Recv SETFORMAT cmd
2026-01-29 03:30:57.843 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.28.20:5700/1) TRXD header version 1 -> 1
2026-01-29 03:30:57.845 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.28.20:5700/2) Recv RXTUNE cmd
2026-01-29 03:30:57.845 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.28.20:5700/2) Recv TXTUNE cmd
2026-01-29 03:30:57.845 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.28.20:5700/2) Recv SETFORMAT cmd
2026-01-29 03:30:57.845 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.28.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:30:57.845 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 03:30:57.846 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.28.20:5700/2) Recv NOMTXPOWER cmd
2026-01-29 03:30:57.846 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.28.20:5700/2) Recv SETFORMAT cmd
2026-01-29 03:30:57.846 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.28.20:5700/2) TRXD header version 1 -> 1
2026-01-29 03:30:57.847 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.28.20:5700/3) Recv RXTUNE cmd
2026-01-29 03:30:57.847 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.28.20:5700/3) Recv TXTUNE cmd
2026-01-29 03:30:57.847 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.28.20:5700/3) Recv SETFORMAT cmd
2026-01-29 03:30:57.847 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.28.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:30:57.847 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 03:30:57.847 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.28.20:5700/3) Recv NOMTXPOWER cmd
2026-01-29 03:30:57.847 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.28.20:5700/3) Recv SETFORMAT cmd
2026-01-29 03:30:57.848 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.28.20:5700/3) TRXD header version 1 -> 1
2026-01-29 03:30:57.850 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.28.20:5700) Recv RXTUNE cmd
2026-01-29 03:30:57.850 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETTSC
2026-01-29 03:30:57.850 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETTSC
2026-01-29 03:30:57.850 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETTSC
2026-01-29 03:30:57.850 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.28.20:5700) Recv TXTUNE cmd
2026-01-29 03:30:57.850 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETRXGAIN
2026-01-29 03:30:57.850 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETRXGAIN
2026-01-29 03:30:57.851 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETRXGAIN
2026-01-29 03:30:57.851 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETTSC
2026-01-29 03:30:57.851 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:30:57.851 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:30:57.851 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.28.20:5700) Recv NOMTXPOWER cmd
2026-01-29 03:30:57.851 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:30:57.851 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:30:57.851 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:30:57.851 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.28.20:5700) Recv POWERON CMD
2026-01-29 03:30:57.851 [INFO] ctrl_if_trx.py:109 (BTS@172.18.28.20:5700) Starting transceiver...
2026-01-29 03:30:57.851 [INFO] transceiver.py:243 Starting clock generator
2026-01-29 03:30:57.851 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-01-29 03:30:57.851 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:30:57.851 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:30:57.851 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:30:57.851 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETRXGAIN
2026-01-29 03:30:57.851 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:30:57.851 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:30:57.851 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:30:57.851 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:30:57.851 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:30:57.852 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:30:57.852 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:30:57.852 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:30:57.852 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:30:57.852 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:30:57.852 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:30:57.852 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:30:57.852 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:30:57.852 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:30:57.852 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:30:57.852 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:30:57.852 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:30:57.852 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:30:57.852 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:30:57.852 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:30:57.852 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:30:57.852 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:30:57.852 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:30:57.852 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:30:57.856 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-01-29 03:30:58.332 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-01-29 03:30:58.377 [DEBUG] fake_trx.py:278 (BTS@172.18.28.20:5700) Recv FAKE_TOA cmd
2026-01-29 03:30:58.378 [DEBUG] fake_trx.py:297 (BTS@172.18.28.20:5700) Recv FAKE_RSSI cmd
2026-01-29 03:30:58.379 [DEBUG] fake_trx.py:322 (BTS@172.18.28.20:5700) Recv FAKE_CI cmd
2026-01-29 03:30:58.379 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:30:58.380 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 03:30:58.381 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 03:30:58.381 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 03:30:58.381 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 03:30:58.381 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 03:30:58.381 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 03:30:58.381 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.28.22:6700) Recv POWERON CMD
2026-01-29 03:30:58.381 [INFO] ctrl_if_trx.py:109 (MS@172.18.28.22:6700) Starting transceiver...
2026-01-29 03:30:58.809 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-01-29 03:30:58.855 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:30:58.855 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 03:30:58.856 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:30:58.858 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:30:59.285 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-01-29 03:30:59.762 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-01-29 03:30:59.855 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:30:59.856 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 03:30:59.856 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:30:59.859 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:31:00.239 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-01-29 03:31:00.716 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-01-29 03:31:00.856 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 03:31:00.857 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:31:00.857 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:31:00.860 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:31:01.192 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-01-29 03:31:01.668 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-01-29 03:31:01.858 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:31:01.858 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:31:01.858 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 03:31:01.860 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:31:02.146 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-01-29 03:31:02.622 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-01-29 03:31:02.858 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:31:02.859 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:31:02.859 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 03:31:02.861 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:31:03.099 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-01-29 03:31:03.571 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-01-29 03:31:04.041 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-01-29 03:31:04.512 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-01-29 03:31:04.983 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-01-29 03:31:05.454 [DEBUG] clck_gen.py:113 IND CLOCK 1632
2026-01-29 03:31:05.925 [DEBUG] clck_gen.py:113 IND CLOCK 1734
2026-01-29 03:31:06.395 [DEBUG] clck_gen.py:113 IND CLOCK 1836
2026-01-29 03:31:06.866 [DEBUG] clck_gen.py:113 IND CLOCK 1938
2026-01-29 03:31:07.337 [DEBUG] clck_gen.py:113 IND CLOCK 2040
2026-01-29 03:31:07.808 [DEBUG] clck_gen.py:113 IND CLOCK 2142
2026-01-29 03:31:08.279 [DEBUG] clck_gen.py:113 IND CLOCK 2244
2026-01-29 03:31:08.749 [DEBUG] clck_gen.py:113 IND CLOCK 2346
2026-01-29 03:31:09.220 [DEBUG] clck_gen.py:113 IND CLOCK 2448
2026-01-29 03:31:09.426 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 03:31:09.426 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 03:31:09.430 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 03:31:09.430 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:31:09.430 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:31:09.430 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:31:09.433 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 03:31:09.434 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 03:31:09.434 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 03:31:09.434 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 03:31:09.434 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.28.20:5700) Recv POWEROFF cmd
2026-01-29 03:31:09.434 [INFO] ctrl_if_trx.py:117 (BTS@172.18.28.20:5700) Stopping transceiver...
2026-01-29 03:31:09.434 [INFO] transceiver.py:246 Stopping clock generator
2026-01-29 03:31:09.435 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=2495 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:31:09.435 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=2496 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:31:09.435 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=2496 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:31:09.435 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=2496 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:31:09.435 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=2496 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:31:09.435 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=2496 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:31:09.435 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=2496 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:31:09.435 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=2496 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:31:09.435 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=2496 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:31:14.433 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.28.20:5700) Recv POWEROFF cmd
2026-01-29 03:31:14.433 [INFO] ctrl_if_trx.py:117 (BTS@172.18.28.20:5700) Stopping transceiver...
2026-01-29 03:31:14.434 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 03:31:14.436 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 03:31:14.437 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 03:31:14.437 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 03:31:14.440 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 03:31:14.441 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.28.20:5700) Recv SETFORMAT cmd
2026-01-29 03:31:14.441 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.28.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:31:14.441 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.28.20:5700) Recv SETFORMAT cmd
2026-01-29 03:31:14.441 [INFO] ctrl_if_trx.py:201 (BTS@172.18.28.20:5700) TRXD header version 1 -> 1
2026-01-29 03:31:14.444 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.28.20:5700/1) Recv RXTUNE cmd
2026-01-29 03:31:14.444 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.28.20:5700/1) Recv TXTUNE cmd
2026-01-29 03:31:14.444 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.28.20:5700/1) Recv SETFORMAT cmd
2026-01-29 03:31:14.444 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.28.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:31:14.445 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 03:31:14.445 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.28.20:5700/1) Recv NOMTXPOWER cmd
2026-01-29 03:31:14.445 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.28.20:5700/1) Recv SETFORMAT cmd
2026-01-29 03:31:14.445 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.28.20:5700/1) TRXD header version 1 -> 1
2026-01-29 03:31:14.447 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.28.20:5700/2) Recv RXTUNE cmd
2026-01-29 03:31:14.448 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.28.20:5700/2) Recv TXTUNE cmd
2026-01-29 03:31:14.448 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.28.20:5700/2) Recv SETFORMAT cmd
2026-01-29 03:31:14.448 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.28.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:31:14.448 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 03:31:14.448 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.28.20:5700/2) Recv NOMTXPOWER cmd
2026-01-29 03:31:14.448 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.28.20:5700/2) Recv SETFORMAT cmd
2026-01-29 03:31:14.448 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.28.20:5700/2) TRXD header version 1 -> 1
2026-01-29 03:31:14.450 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.28.20:5700/3) Recv RXTUNE cmd
2026-01-29 03:31:14.451 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.28.20:5700/3) Recv TXTUNE cmd
2026-01-29 03:31:14.451 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.28.20:5700/3) Recv SETFORMAT cmd
2026-01-29 03:31:14.451 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.28.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:31:14.451 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 03:31:14.451 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.28.20:5700/3) Recv NOMTXPOWER cmd
2026-01-29 03:31:14.451 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.28.20:5700/3) Recv SETFORMAT cmd
2026-01-29 03:31:14.451 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.28.20:5700/3) TRXD header version 1 -> 1
2026-01-29 03:31:14.454 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.28.20:5700) Recv RXTUNE cmd
2026-01-29 03:31:14.454 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETTSC
2026-01-29 03:31:14.454 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETTSC
2026-01-29 03:31:14.455 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETTSC
2026-01-29 03:31:14.455 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.28.20:5700) Recv TXTUNE cmd
2026-01-29 03:31:14.455 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETRXGAIN
2026-01-29 03:31:14.455 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETRXGAIN
2026-01-29 03:31:14.455 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETRXGAIN
2026-01-29 03:31:14.455 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETTSC
2026-01-29 03:31:14.455 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:31:14.455 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:31:14.455 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.28.20:5700) Recv NOMTXPOWER cmd
2026-01-29 03:31:14.455 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:31:14.455 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:31:14.455 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:31:14.455 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.28.20:5700) Recv POWERON CMD
2026-01-29 03:31:14.455 [INFO] ctrl_if_trx.py:109 (BTS@172.18.28.20:5700) Starting transceiver...
2026-01-29 03:31:14.455 [INFO] transceiver.py:243 Starting clock generator
2026-01-29 03:31:14.455 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-01-29 03:31:14.456 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:31:14.456 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:31:14.456 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:31:14.456 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETRXGAIN
2026-01-29 03:31:14.456 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:31:14.456 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:31:14.456 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:31:14.456 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:31:14.456 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:31:14.456 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:31:14.456 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:31:14.456 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:31:14.456 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:31:14.456 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:31:14.456 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:31:14.456 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:31:14.456 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:31:14.456 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:31:14.456 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:31:14.457 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:31:14.457 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:31:14.457 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:31:14.457 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:31:14.457 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:31:14.457 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:31:14.457 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:31:14.457 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:31:14.457 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:31:14.460 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-01-29 03:31:14.936 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-01-29 03:31:14.991 [DEBUG] fake_trx.py:278 (BTS@172.18.28.20:5700) Recv FAKE_TOA cmd
2026-01-29 03:31:14.993 [DEBUG] fake_trx.py:297 (BTS@172.18.28.20:5700) Recv FAKE_RSSI cmd
2026-01-29 03:31:14.994 [DEBUG] fake_trx.py:322 (BTS@172.18.28.20:5700) Recv FAKE_CI cmd
2026-01-29 03:31:14.994 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:31:14.996 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 03:31:14.996 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 03:31:14.996 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 03:31:14.997 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 03:31:14.997 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 03:31:14.997 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 03:31:14.997 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.28.22:6700) Recv POWERON CMD
2026-01-29 03:31:14.997 [INFO] ctrl_if_trx.py:109 (MS@172.18.28.22:6700) Starting transceiver...
2026-01-29 03:31:15.413 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-01-29 03:31:15.458 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 03:31:15.459 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:31:15.461 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:31:15.466 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:31:15.889 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-01-29 03:31:16.360 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-01-29 03:31:16.459 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:31:16.460 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 03:31:16.462 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:31:16.466 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:31:16.833 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-01-29 03:31:17.309 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-01-29 03:31:17.460 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:31:17.460 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 03:31:17.462 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:31:17.467 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:31:17.785 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-01-29 03:31:18.261 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-01-29 03:31:18.461 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 03:31:18.461 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:31:18.464 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:31:18.468 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:31:18.737 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-01-29 03:31:19.214 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-01-29 03:31:19.461 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 03:31:19.461 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:31:19.464 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:31:19.468 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:31:19.691 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-01-29 03:31:20.166 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-01-29 03:31:20.643 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-01-29 03:31:21.118 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-01-29 03:31:21.594 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-01-29 03:31:22.070 [DEBUG] clck_gen.py:113 IND CLOCK 1632
2026-01-29 03:31:22.547 [DEBUG] clck_gen.py:113 IND CLOCK 1734
2026-01-29 03:31:23.023 [DEBUG] clck_gen.py:113 IND CLOCK 1836
2026-01-29 03:31:23.496 [DEBUG] clck_gen.py:113 IND CLOCK 1938
2026-01-29 03:31:23.972 [DEBUG] clck_gen.py:113 IND CLOCK 2040
2026-01-29 03:31:24.443 [DEBUG] clck_gen.py:113 IND CLOCK 2142
2026-01-29 03:31:24.914 [DEBUG] clck_gen.py:113 IND CLOCK 2244
2026-01-29 03:31:25.385 [DEBUG] clck_gen.py:113 IND CLOCK 2346
2026-01-29 03:31:25.856 [DEBUG] clck_gen.py:113 IND CLOCK 2448
2026-01-29 03:31:26.329 [DEBUG] clck_gen.py:113 IND CLOCK 2550
2026-01-29 03:31:26.803 [DEBUG] clck_gen.py:113 IND CLOCK 2652
2026-01-29 03:31:27.275 [DEBUG] clck_gen.py:113 IND CLOCK 2754
2026-01-29 03:31:27.749 [DEBUG] clck_gen.py:113 IND CLOCK 2856
2026-01-29 03:31:28.224 [DEBUG] clck_gen.py:113 IND CLOCK 2958
2026-01-29 03:31:28.700 [DEBUG] clck_gen.py:113 IND CLOCK 3060
2026-01-29 03:31:29.176 [DEBUG] clck_gen.py:113 IND CLOCK 3162
2026-01-29 03:31:29.649 [DEBUG] clck_gen.py:113 IND CLOCK 3264
2026-01-29 03:31:30.030 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 03:31:30.030 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 03:31:30.034 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 03:31:30.035 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:31:30.035 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:31:30.035 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:31:30.039 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 03:31:30.040 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 03:31:30.040 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 03:31:30.040 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 03:31:30.040 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.28.20:5700) Recv POWEROFF cmd
2026-01-29 03:31:30.040 [INFO] ctrl_if_trx.py:117 (BTS@172.18.28.20:5700) Stopping transceiver...
2026-01-29 03:31:30.040 [INFO] transceiver.py:246 Stopping clock generator
2026-01-29 03:31:30.041 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=3351 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:31:30.041 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=3351 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:31:30.041 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=3351 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:31:30.041 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=3351 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:31:30.041 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=3351 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:31:30.041 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=3351 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:31:35.038 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.28.20:5700) Recv POWEROFF cmd
2026-01-29 03:31:35.038 [INFO] ctrl_if_trx.py:117 (BTS@172.18.28.20:5700) Stopping transceiver...
2026-01-29 03:31:35.039 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 03:31:35.041 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 03:31:35.042 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 03:31:35.045 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 03:31:35.052 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 03:31:35.053 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.28.20:5700) Recv SETFORMAT cmd
2026-01-29 03:31:35.053 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.28.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:31:35.053 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.28.20:5700) Recv SETFORMAT cmd
2026-01-29 03:31:35.053 [INFO] ctrl_if_trx.py:201 (BTS@172.18.28.20:5700) TRXD header version 1 -> 1
2026-01-29 03:31:35.055 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.28.20:5700/1) Recv RXTUNE cmd
2026-01-29 03:31:35.055 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.28.20:5700/1) Recv TXTUNE cmd
2026-01-29 03:31:35.055 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.28.20:5700/1) Recv SETFORMAT cmd
2026-01-29 03:31:35.055 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.28.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:31:35.055 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.28.20:5700/1) Recv NOMTXPOWER cmd
2026-01-29 03:31:35.055 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 03:31:35.055 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.28.20:5700/1) Recv SETFORMAT cmd
2026-01-29 03:31:35.055 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.28.20:5700/1) TRXD header version 1 -> 1
2026-01-29 03:31:35.058 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.28.20:5700/2) Recv RXTUNE cmd
2026-01-29 03:31:35.059 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.28.20:5700/2) Recv TXTUNE cmd
2026-01-29 03:31:35.059 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.28.20:5700/2) Recv SETFORMAT cmd
2026-01-29 03:31:35.059 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.28.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:31:35.059 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 03:31:35.059 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.28.20:5700/2) Recv NOMTXPOWER cmd
2026-01-29 03:31:35.059 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.28.20:5700/2) Recv SETFORMAT cmd
2026-01-29 03:31:35.059 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.28.20:5700/2) TRXD header version 1 -> 1
2026-01-29 03:31:35.060 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.28.20:5700/3) Recv RXTUNE cmd
2026-01-29 03:31:35.060 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.28.20:5700/3) Recv TXTUNE cmd
2026-01-29 03:31:35.060 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.28.20:5700/3) Recv SETFORMAT cmd
2026-01-29 03:31:35.060 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.28.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:31:35.061 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 03:31:35.061 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.28.20:5700/3) Recv NOMTXPOWER cmd
2026-01-29 03:31:35.061 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.28.20:5700/3) Recv SETFORMAT cmd
2026-01-29 03:31:35.061 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.28.20:5700/3) TRXD header version 1 -> 1
2026-01-29 03:31:35.063 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.28.20:5700) Recv RXTUNE cmd
2026-01-29 03:31:35.063 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETTSC
2026-01-29 03:31:35.063 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETTSC
2026-01-29 03:31:35.063 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETTSC
2026-01-29 03:31:35.063 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.28.20:5700) Recv TXTUNE cmd
2026-01-29 03:31:35.063 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETRXGAIN
2026-01-29 03:31:35.063 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETRXGAIN
2026-01-29 03:31:35.063 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETRXGAIN
2026-01-29 03:31:35.063 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETTSC
2026-01-29 03:31:35.063 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:31:35.063 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:31:35.063 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.28.20:5700) Recv NOMTXPOWER cmd
2026-01-29 03:31:35.063 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:31:35.063 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:31:35.063 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:31:35.063 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.28.20:5700) Recv POWERON CMD
2026-01-29 03:31:35.063 [INFO] ctrl_if_trx.py:109 (BTS@172.18.28.20:5700) Starting transceiver...
2026-01-29 03:31:35.063 [INFO] transceiver.py:243 Starting clock generator
2026-01-29 03:31:35.063 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-01-29 03:31:35.064 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:31:35.064 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:31:35.064 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:31:35.064 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETRXGAIN
2026-01-29 03:31:35.064 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:31:35.064 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:31:35.064 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:31:35.064 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:31:35.064 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:31:35.064 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:31:35.064 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:31:35.064 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:31:35.064 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:31:35.064 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:31:35.064 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:31:35.064 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:31:35.064 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:31:35.064 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:31:35.064 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:31:35.064 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:31:35.064 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:31:35.064 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:31:35.064 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:31:35.064 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:31:35.064 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:31:35.064 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:31:35.064 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:31:35.064 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:31:35.068 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-01-29 03:31:35.545 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-01-29 03:31:35.585 [DEBUG] fake_trx.py:278 (BTS@172.18.28.20:5700) Recv FAKE_TOA cmd
2026-01-29 03:31:35.587 [DEBUG] fake_trx.py:297 (BTS@172.18.28.20:5700) Recv FAKE_RSSI cmd
2026-01-29 03:31:35.588 [DEBUG] fake_trx.py:322 (BTS@172.18.28.20:5700) Recv FAKE_CI cmd
2026-01-29 03:31:35.588 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:31:35.592 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 03:31:35.592 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 03:31:35.592 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 03:31:35.593 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 03:31:35.593 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 03:31:35.593 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 03:31:35.593 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.28.22:6700) Recv POWERON CMD
2026-01-29 03:31:35.593 [INFO] ctrl_if_trx.py:109 (MS@172.18.28.22:6700) Starting transceiver...
2026-01-29 03:31:35.639 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 03:31:35.640 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 03:31:35.644 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 03:31:35.644 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:31:35.645 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:31:35.645 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:31:35.646 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 03:31:35.646 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 03:31:35.646 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 03:31:35.646 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 03:31:35.646 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.28.20:5700) Recv POWEROFF cmd
2026-01-29 03:31:35.646 [INFO] ctrl_if_trx.py:117 (BTS@172.18.28.20:5700) Stopping transceiver...
2026-01-29 03:31:35.646 [INFO] transceiver.py:246 Stopping clock generator
2026-01-29 03:31:40.646 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.28.20:5700) Recv POWEROFF cmd
2026-01-29 03:31:40.646 [INFO] ctrl_if_trx.py:117 (BTS@172.18.28.20:5700) Stopping transceiver...
2026-01-29 03:31:40.648 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 03:31:40.649 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 03:31:40.651 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 03:31:40.654 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 03:31:40.666 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 03:31:40.667 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.28.20:5700) Recv SETFORMAT cmd
2026-01-29 03:31:40.667 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.28.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:31:40.667 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.28.20:5700) Recv SETFORMAT cmd
2026-01-29 03:31:40.667 [INFO] ctrl_if_trx.py:201 (BTS@172.18.28.20:5700) TRXD header version 1 -> 1
2026-01-29 03:31:40.670 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.28.20:5700/1) Recv RXTUNE cmd
2026-01-29 03:31:40.670 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.28.20:5700/1) Recv TXTUNE cmd
2026-01-29 03:31:40.671 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.28.20:5700/1) Recv SETFORMAT cmd
2026-01-29 03:31:40.671 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.28.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:31:40.671 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 03:31:40.671 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.28.20:5700/1) Recv NOMTXPOWER cmd
2026-01-29 03:31:40.671 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.28.20:5700/1) Recv SETFORMAT cmd
2026-01-29 03:31:40.671 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.28.20:5700/1) TRXD header version 1 -> 1
2026-01-29 03:31:40.673 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.28.20:5700/2) Recv RXTUNE cmd
2026-01-29 03:31:40.673 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.28.20:5700/2) Recv TXTUNE cmd
2026-01-29 03:31:40.673 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.28.20:5700/2) Recv SETFORMAT cmd
2026-01-29 03:31:40.674 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.28.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:31:40.674 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 03:31:40.674 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.28.20:5700/2) Recv NOMTXPOWER cmd
2026-01-29 03:31:40.674 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.28.20:5700/2) Recv SETFORMAT cmd
2026-01-29 03:31:40.674 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.28.20:5700/2) TRXD header version 1 -> 1
2026-01-29 03:31:40.676 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.28.20:5700/3) Recv RXTUNE cmd
2026-01-29 03:31:40.676 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.28.20:5700/3) Recv TXTUNE cmd
2026-01-29 03:31:40.676 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.28.20:5700/3) Recv SETFORMAT cmd
2026-01-29 03:31:40.676 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.28.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:31:40.676 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 03:31:40.676 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.28.20:5700/3) Recv NOMTXPOWER cmd
2026-01-29 03:31:40.676 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.28.20:5700/3) Recv SETFORMAT cmd
2026-01-29 03:31:40.676 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.28.20:5700/3) TRXD header version 1 -> 1
2026-01-29 03:31:40.679 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.28.20:5700) Recv RXTUNE cmd
2026-01-29 03:31:40.679 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETTSC
2026-01-29 03:31:40.679 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETTSC
2026-01-29 03:31:40.679 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETTSC
2026-01-29 03:31:40.679 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.28.20:5700) Recv TXTUNE cmd
2026-01-29 03:31:40.679 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETRXGAIN
2026-01-29 03:31:40.679 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETRXGAIN
2026-01-29 03:31:40.679 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETRXGAIN
2026-01-29 03:31:40.679 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETTSC
2026-01-29 03:31:40.679 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:31:40.679 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:31:40.679 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:31:40.679 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.28.20:5700) Recv NOMTXPOWER cmd
2026-01-29 03:31:40.679 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:31:40.679 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:31:40.679 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:31:40.680 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.28.20:5700) Recv POWERON CMD
2026-01-29 03:31:40.680 [INFO] ctrl_if_trx.py:109 (BTS@172.18.28.20:5700) Starting transceiver...
2026-01-29 03:31:40.680 [INFO] transceiver.py:243 Starting clock generator
2026-01-29 03:31:40.680 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-01-29 03:31:40.680 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:31:40.680 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:31:40.680 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:31:40.680 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETRXGAIN
2026-01-29 03:31:40.680 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:31:40.680 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:31:40.680 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:31:40.680 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:31:40.680 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:31:40.680 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:31:40.680 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:31:40.680 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:31:40.680 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:31:40.680 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:31:40.680 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:31:40.681 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:31:40.681 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:31:40.681 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:31:40.681 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:31:40.681 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:31:40.681 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:31:40.681 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:31:40.681 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:31:40.681 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:31:40.681 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:31:40.681 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:31:40.681 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:31:40.685 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-01-29 03:31:41.161 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-01-29 03:31:41.203 [DEBUG] fake_trx.py:278 (BTS@172.18.28.20:5700) Recv FAKE_TOA cmd
2026-01-29 03:31:41.205 [DEBUG] fake_trx.py:297 (BTS@172.18.28.20:5700) Recv FAKE_RSSI cmd
2026-01-29 03:31:41.205 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:31:41.206 [DEBUG] fake_trx.py:322 (BTS@172.18.28.20:5700) Recv FAKE_CI cmd
2026-01-29 03:31:41.215 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 03:31:41.215 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 03:31:41.215 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 03:31:41.225 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 03:31:41.225 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 03:31:41.225 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 03:31:41.226 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:31:41.230 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 03:31:41.230 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 03:31:41.230 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 03:31:41.230 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.28.22:6700) Recv POWERON CMD
2026-01-29 03:31:41.230 [INFO] ctrl_if_trx.py:109 (MS@172.18.28.22:6700) Starting transceiver...
2026-01-29 03:31:41.252 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 03:31:41.253 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 03:31:41.253 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 03:31:41.253 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 03:31:41.357 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 03:31:41.358 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:31:41.360 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 03:31:41.360 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 03:31:41.375 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 03:31:41.375 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 03:31:41.376 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 03:31:41.382 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 03:31:41.382 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 03:31:41.382 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 03:31:41.382 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:31:41.384 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 03:31:41.384 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 03:31:41.384 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 03:31:41.384 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.28.22:6700) Recv POWERON CMD
2026-01-29 03:31:41.384 [INFO] ctrl_if_trx.py:109 (MS@172.18.28.22:6700) Starting transceiver...
2026-01-29 03:31:41.393 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.28.22:6700) Recv SETFH cmd
2026-01-29 03:31:41.393 [INFO] transceiver.py:201 (MS@172.18.28.22:6700) Frequency hopping configured: hsn=5, maio=0, ma_len=4
2026-01-29 03:31:41.393 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 03:31:41.393 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 03:31:41.556 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 03:31:41.557 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:31:41.560 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 03:31:41.560 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 03:31:41.560 [INFO] transceiver.py:205 (MS@172.18.28.22:6700) Frequency hopping disabled
2026-01-29 03:31:41.570 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 03:31:41.570 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 03:31:41.570 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 03:31:41.576 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 03:31:41.576 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 03:31:41.576 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 03:31:41.577 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:31:41.578 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 03:31:41.578 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 03:31:41.578 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 03:31:41.578 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.28.22:6700) Recv POWERON CMD
2026-01-29 03:31:41.578 [INFO] ctrl_if_trx.py:109 (MS@172.18.28.22:6700) Starting transceiver...
2026-01-29 03:31:41.630 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-01-29 03:31:41.630 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 03:31:41.631 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 03:31:41.631 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 03:31:41.632 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 03:31:41.683 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 03:31:41.683 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:31:41.684 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:31:41.688 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:31:42.018 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 03:31:42.018 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:31:42.022 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 03:31:42.022 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 03:31:42.040 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 03:31:42.040 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 03:31:42.040 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 03:31:42.046 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 03:31:42.046 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 03:31:42.046 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 03:31:42.046 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:31:42.047 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 03:31:42.047 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 03:31:42.048 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 03:31:42.048 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.28.22:6700) Recv POWERON CMD
2026-01-29 03:31:42.048 [INFO] ctrl_if_trx.py:109 (MS@172.18.28.22:6700) Starting transceiver...
2026-01-29 03:31:42.096 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.28.22:6700) Recv SETFH cmd
2026-01-29 03:31:42.097 [INFO] transceiver.py:201 (MS@172.18.28.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2026-01-29 03:31:42.097 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 03:31:42.097 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 03:31:42.103 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-01-29 03:31:42.575 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-01-29 03:31:42.684 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 03:31:42.684 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:31:42.685 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:31:42.688 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:31:42.892 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 03:31:42.892 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:31:42.896 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 03:31:42.896 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 03:31:42.896 [INFO] transceiver.py:205 (MS@172.18.28.22:6700) Frequency hopping disabled
2026-01-29 03:31:42.906 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 03:31:42.906 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:31:42.906 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:31:42.906 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:31:42.910 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 03:31:42.910 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 03:31:42.910 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 03:31:42.910 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 03:31:42.911 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.28.20:5700) Recv POWEROFF cmd
2026-01-29 03:31:42.911 [INFO] ctrl_if_trx.py:117 (BTS@172.18.28.20:5700) Stopping transceiver...
2026-01-29 03:31:42.911 [INFO] transceiver.py:246 Stopping clock generator
2026-01-29 03:31:42.911 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=482 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:31:42.911 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=482 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:31:42.911 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=482 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:31:42.911 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=482 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:31:42.912 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=482 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:31:42.912 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=482 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:31:47.909 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.28.20:5700) Recv POWEROFF cmd
2026-01-29 03:31:47.909 [INFO] ctrl_if_trx.py:117 (BTS@172.18.28.20:5700) Stopping transceiver...
2026-01-29 03:31:47.910 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 03:31:47.912 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 03:31:47.913 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 03:31:47.915 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 03:31:47.928 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 03:31:47.929 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.28.20:5700) Recv SETFORMAT cmd
2026-01-29 03:31:47.929 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.28.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:31:47.929 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.28.20:5700) Recv SETFORMAT cmd
2026-01-29 03:31:47.929 [INFO] ctrl_if_trx.py:201 (BTS@172.18.28.20:5700) TRXD header version 1 -> 1
2026-01-29 03:31:47.932 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.28.20:5700/1) Recv RXTUNE cmd
2026-01-29 03:31:47.932 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.28.20:5700/1) Recv TXTUNE cmd
2026-01-29 03:31:47.932 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.28.20:5700/1) Recv SETFORMAT cmd
2026-01-29 03:31:47.932 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.28.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:31:47.932 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 03:31:47.932 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.28.20:5700/1) Recv NOMTXPOWER cmd
2026-01-29 03:31:47.932 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.28.20:5700/1) Recv SETFORMAT cmd
2026-01-29 03:31:47.932 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.28.20:5700/1) TRXD header version 1 -> 1
2026-01-29 03:31:47.935 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.28.20:5700/2) Recv RXTUNE cmd
2026-01-29 03:31:47.935 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.28.20:5700/2) Recv TXTUNE cmd
2026-01-29 03:31:47.935 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.28.20:5700/2) Recv SETFORMAT cmd
2026-01-29 03:31:47.935 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.28.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:31:47.935 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 03:31:47.935 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.28.20:5700/2) Recv NOMTXPOWER cmd
2026-01-29 03:31:47.935 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.28.20:5700/2) Recv SETFORMAT cmd
2026-01-29 03:31:47.935 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.28.20:5700/2) TRXD header version 1 -> 1
2026-01-29 03:31:47.937 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.28.20:5700/3) Recv RXTUNE cmd
2026-01-29 03:31:47.937 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.28.20:5700/3) Recv TXTUNE cmd
2026-01-29 03:31:47.937 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.28.20:5700/3) Recv SETFORMAT cmd
2026-01-29 03:31:47.937 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.28.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:31:47.937 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 03:31:47.937 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.28.20:5700/3) Recv NOMTXPOWER cmd
2026-01-29 03:31:47.937 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.28.20:5700/3) Recv SETFORMAT cmd
2026-01-29 03:31:47.937 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.28.20:5700/3) TRXD header version 1 -> 1
2026-01-29 03:31:47.940 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.28.20:5700) Recv RXTUNE cmd
2026-01-29 03:31:47.940 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETTSC
2026-01-29 03:31:47.940 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETTSC
2026-01-29 03:31:47.940 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETTSC
2026-01-29 03:31:47.940 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.28.20:5700) Recv TXTUNE cmd
2026-01-29 03:31:47.940 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETRXGAIN
2026-01-29 03:31:47.940 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETRXGAIN
2026-01-29 03:31:47.940 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETRXGAIN
2026-01-29 03:31:47.940 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETTSC
2026-01-29 03:31:47.940 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:31:47.940 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:31:47.940 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:31:47.940 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.28.20:5700) Recv NOMTXPOWER cmd
2026-01-29 03:31:47.940 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:31:47.940 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:31:47.940 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:31:47.940 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.28.20:5700) Recv POWERON CMD
2026-01-29 03:31:47.940 [INFO] ctrl_if_trx.py:109 (BTS@172.18.28.20:5700) Starting transceiver...
2026-01-29 03:31:47.940 [INFO] transceiver.py:243 Starting clock generator
2026-01-29 03:31:47.940 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-01-29 03:31:47.941 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:31:47.941 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:31:47.941 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:31:47.941 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETRXGAIN
2026-01-29 03:31:47.941 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:31:47.941 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:31:47.941 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:31:47.941 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:31:47.941 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:31:47.941 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:31:47.941 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:31:47.941 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:31:47.941 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:31:47.941 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:31:47.941 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:31:47.941 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:31:47.941 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:31:47.941 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:31:47.941 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:31:47.941 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:31:47.941 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:31:47.941 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:31:47.941 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:31:47.941 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:31:47.941 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:31:47.941 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:31:47.942 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:31:47.945 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-01-29 03:31:48.423 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-01-29 03:31:48.477 [DEBUG] fake_trx.py:278 (BTS@172.18.28.20:5700) Recv FAKE_TOA cmd
2026-01-29 03:31:48.479 [DEBUG] fake_trx.py:297 (BTS@172.18.28.20:5700) Recv FAKE_RSSI cmd
2026-01-29 03:31:48.480 [DEBUG] fake_trx.py:322 (BTS@172.18.28.20:5700) Recv FAKE_CI cmd
2026-01-29 03:31:48.481 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:31:48.502 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 03:31:48.502 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 03:31:48.502 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 03:31:48.521 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 03:31:48.521 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 03:31:48.521 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 03:31:48.523 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:31:48.529 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 03:31:48.529 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 03:31:48.530 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 03:31:48.530 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.28.22:6700) Recv POWERON CMD
2026-01-29 03:31:48.530 [INFO] ctrl_if_trx.py:109 (MS@172.18.28.22:6700) Starting transceiver...
2026-01-29 03:31:48.560 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 03:31:48.560 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 03:31:48.560 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 03:31:48.561 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 03:31:48.900 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-01-29 03:31:48.944 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 03:31:48.944 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:31:48.946 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:31:48.949 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:31:49.373 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-01-29 03:31:49.842 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-01-29 03:31:49.945 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 03:31:49.945 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:31:49.947 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:31:49.951 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:31:50.317 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-01-29 03:31:50.789 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-01-29 03:31:50.946 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 03:31:50.946 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:31:50.947 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:31:50.951 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:31:51.265 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-01-29 03:31:51.742 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-01-29 03:31:51.947 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 03:31:51.947 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:31:51.947 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:31:51.951 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:31:52.219 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-01-29 03:31:52.697 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-01-29 03:31:52.947 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 03:31:52.947 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:31:52.948 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:31:52.952 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:31:53.173 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-01-29 03:31:53.564 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 03:31:53.564 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:31:53.567 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 03:31:53.568 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 03:31:53.579 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 03:31:53.579 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 03:31:53.579 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 03:31:53.585 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 03:31:53.585 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 03:31:53.586 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 03:31:53.586 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:31:53.587 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 03:31:53.587 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 03:31:53.587 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 03:31:53.587 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.28.22:6700) Recv POWERON CMD
2026-01-29 03:31:53.587 [INFO] ctrl_if_trx.py:109 (MS@172.18.28.22:6700) Starting transceiver...
2026-01-29 03:31:53.590 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.28.22:6700) Recv SETFH cmd
2026-01-29 03:31:53.590 [INFO] transceiver.py:201 (MS@172.18.28.22:6700) Frequency hopping configured: hsn=5, maio=0, ma_len=4
2026-01-29 03:31:53.590 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 03:31:53.590 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 03:31:53.648 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-01-29 03:31:54.117 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-01-29 03:31:54.591 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-01-29 03:31:55.065 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-01-29 03:31:55.534 [DEBUG] clck_gen.py:113 IND CLOCK 1632
2026-01-29 03:31:56.004 [DEBUG] clck_gen.py:113 IND CLOCK 1734
2026-01-29 03:31:56.475 [DEBUG] clck_gen.py:113 IND CLOCK 1836
2026-01-29 03:31:56.946 [DEBUG] clck_gen.py:113 IND CLOCK 1938
2026-01-29 03:31:57.424 [DEBUG] clck_gen.py:113 IND CLOCK 2040
2026-01-29 03:31:57.898 [DEBUG] clck_gen.py:113 IND CLOCK 2142
2026-01-29 03:31:58.373 [DEBUG] clck_gen.py:113 IND CLOCK 2244
2026-01-29 03:31:58.593 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 03:31:58.593 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:31:58.597 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 03:31:58.597 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 03:31:58.598 [INFO] transceiver.py:205 (MS@172.18.28.22:6700) Frequency hopping disabled
2026-01-29 03:31:58.617 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 03:31:58.617 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 03:31:58.617 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 03:31:58.623 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 03:31:58.623 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 03:31:58.623 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 03:31:58.623 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:31:58.625 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 03:31:58.625 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 03:31:58.625 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 03:31:58.625 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.28.22:6700) Recv POWERON CMD
2026-01-29 03:31:58.625 [INFO] ctrl_if_trx.py:109 (MS@172.18.28.22:6700) Starting transceiver...
2026-01-29 03:31:58.653 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 03:31:58.654 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 03:31:58.654 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 03:31:58.654 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 03:31:58.849 [DEBUG] clck_gen.py:113 IND CLOCK 2346
2026-01-29 03:31:59.326 [DEBUG] clck_gen.py:113 IND CLOCK 2448
2026-01-29 03:31:59.803 [DEBUG] clck_gen.py:113 IND CLOCK 2550
2026-01-29 03:32:00.280 [DEBUG] clck_gen.py:113 IND CLOCK 2652
2026-01-29 03:32:00.757 [DEBUG] clck_gen.py:113 IND CLOCK 2754
2026-01-29 03:32:01.234 [DEBUG] clck_gen.py:113 IND CLOCK 2856
2026-01-29 03:32:01.711 [DEBUG] clck_gen.py:113 IND CLOCK 2958
2026-01-29 03:32:02.188 [DEBUG] clck_gen.py:113 IND CLOCK 3060
2026-01-29 03:32:02.666 [DEBUG] clck_gen.py:113 IND CLOCK 3162
2026-01-29 03:32:03.143 [DEBUG] clck_gen.py:113 IND CLOCK 3264
2026-01-29 03:32:03.620 [DEBUG] clck_gen.py:113 IND CLOCK 3366
2026-01-29 03:32:03.658 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 03:32:03.659 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:32:03.662 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 03:32:03.662 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 03:32:03.682 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 03:32:03.682 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 03:32:03.682 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 03:32:03.688 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 03:32:03.688 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 03:32:03.688 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 03:32:03.688 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:32:03.689 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 03:32:03.689 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 03:32:03.690 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 03:32:03.690 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.28.22:6700) Recv POWERON CMD
2026-01-29 03:32:03.690 [INFO] ctrl_if_trx.py:109 (MS@172.18.28.22:6700) Starting transceiver...
2026-01-29 03:32:03.712 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.28.22:6700) Recv SETFH cmd
2026-01-29 03:32:03.712 [INFO] transceiver.py:201 (MS@172.18.28.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2026-01-29 03:32:03.712 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 03:32:03.712 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 03:32:04.098 [DEBUG] clck_gen.py:113 IND CLOCK 3468
2026-01-29 03:32:04.575 [DEBUG] clck_gen.py:113 IND CLOCK 3570
2026-01-29 03:32:05.047 [DEBUG] clck_gen.py:113 IND CLOCK 3672
2026-01-29 03:32:05.524 [DEBUG] clck_gen.py:113 IND CLOCK 3774
2026-01-29 03:32:05.997 [DEBUG] clck_gen.py:113 IND CLOCK 3876
2026-01-29 03:32:06.467 [DEBUG] clck_gen.py:113 IND CLOCK 3978
2026-01-29 03:32:06.937 [DEBUG] clck_gen.py:113 IND CLOCK 4080
2026-01-29 03:32:07.408 [DEBUG] clck_gen.py:113 IND CLOCK 4182
2026-01-29 03:32:07.881 [DEBUG] clck_gen.py:113 IND CLOCK 4284
2026-01-29 03:32:08.360 [DEBUG] clck_gen.py:113 IND CLOCK 4386
2026-01-29 03:32:08.716 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 03:32:08.717 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:32:08.720 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 03:32:08.721 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 03:32:08.721 [INFO] transceiver.py:205 (MS@172.18.28.22:6700) Frequency hopping disabled
2026-01-29 03:32:08.731 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 03:32:08.731 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:32:08.731 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:32:08.731 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:32:08.735 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 03:32:08.735 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 03:32:08.735 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 03:32:08.735 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.28.20:5700) Recv POWEROFF cmd
2026-01-29 03:32:08.735 [INFO] ctrl_if_trx.py:117 (BTS@172.18.28.20:5700) Stopping transceiver...
2026-01-29 03:32:08.735 [INFO] transceiver.py:246 Stopping clock generator
2026-01-29 03:32:08.736 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 03:32:08.736 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=4468 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:32:08.736 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=4468 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:32:08.736 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=4468 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:32:08.736 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=4468 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:32:08.736 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=4468 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:32:08.737 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=4468 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:32:08.737 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=4468 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:32:08.737 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=4468 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:32:08.737 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=4469 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:32:08.737 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=4469 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:32:08.737 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=4469 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:32:08.737 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=4469 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:32:08.737 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=4469 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:32:08.737 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=4469 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:32:08.737 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=4469 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:32:08.737 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=4469 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:32:13.734 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.28.20:5700) Recv POWEROFF cmd
2026-01-29 03:32:13.734 [INFO] ctrl_if_trx.py:117 (BTS@172.18.28.20:5700) Stopping transceiver...
2026-01-29 03:32:13.738 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 03:32:13.739 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 03:32:13.739 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 03:32:13.739 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 03:32:13.751 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 03:32:13.751 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.28.20:5700) Recv SETFORMAT cmd
2026-01-29 03:32:13.751 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.28.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:32:13.752 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.28.20:5700) Recv SETFORMAT cmd
2026-01-29 03:32:13.752 [INFO] ctrl_if_trx.py:201 (BTS@172.18.28.20:5700) TRXD header version 1 -> 1
2026-01-29 03:32:13.754 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.28.20:5700/1) Recv RXTUNE cmd
2026-01-29 03:32:13.754 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.28.20:5700/1) Recv TXTUNE cmd
2026-01-29 03:32:13.755 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.28.20:5700/1) Recv SETFORMAT cmd
2026-01-29 03:32:13.755 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.28.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:32:13.755 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 03:32:13.755 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.28.20:5700/1) Recv NOMTXPOWER cmd
2026-01-29 03:32:13.756 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.28.20:5700/1) Recv SETFORMAT cmd
2026-01-29 03:32:13.756 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.28.20:5700/1) TRXD header version 1 -> 1
2026-01-29 03:32:13.757 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.28.20:5700/2) Recv RXTUNE cmd
2026-01-29 03:32:13.757 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.28.20:5700/2) Recv TXTUNE cmd
2026-01-29 03:32:13.758 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.28.20:5700/2) Recv SETFORMAT cmd
2026-01-29 03:32:13.758 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.28.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:32:13.758 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 03:32:13.758 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.28.20:5700/2) Recv NOMTXPOWER cmd
2026-01-29 03:32:13.758 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.28.20:5700/2) Recv SETFORMAT cmd
2026-01-29 03:32:13.758 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.28.20:5700/2) TRXD header version 1 -> 1
2026-01-29 03:32:13.759 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.28.20:5700/3) Recv RXTUNE cmd
2026-01-29 03:32:13.760 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.28.20:5700/3) Recv TXTUNE cmd
2026-01-29 03:32:13.760 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.28.20:5700/3) Recv SETFORMAT cmd
2026-01-29 03:32:13.760 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.28.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:32:13.760 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 03:32:13.760 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.28.20:5700/3) Recv NOMTXPOWER cmd
2026-01-29 03:32:13.760 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.28.20:5700/3) Recv SETFORMAT cmd
2026-01-29 03:32:13.760 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.28.20:5700/3) TRXD header version 1 -> 1
2026-01-29 03:32:13.762 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.28.20:5700) Recv RXTUNE cmd
2026-01-29 03:32:13.762 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETTSC
2026-01-29 03:32:13.763 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETTSC
2026-01-29 03:32:13.763 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.28.20:5700) Recv TXTUNE cmd
2026-01-29 03:32:13.763 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETTSC
2026-01-29 03:32:13.763 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETRXGAIN
2026-01-29 03:32:13.763 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETRXGAIN
2026-01-29 03:32:13.763 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETTSC
2026-01-29 03:32:13.763 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETRXGAIN
2026-01-29 03:32:13.763 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:32:13.763 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.28.20:5700) Recv NOMTXPOWER cmd
2026-01-29 03:32:13.763 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:32:13.763 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:32:13.763 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.28.20:5700) Recv POWERON CMD
2026-01-29 03:32:13.763 [INFO] ctrl_if_trx.py:109 (BTS@172.18.28.20:5700) Starting transceiver...
2026-01-29 03:32:13.763 [INFO] transceiver.py:243 Starting clock generator
2026-01-29 03:32:13.763 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-01-29 03:32:13.763 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:32:13.763 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:32:13.763 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:32:13.763 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETRXGAIN
2026-01-29 03:32:13.763 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:32:13.764 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:32:13.764 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:32:13.764 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:32:13.764 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:32:13.764 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:32:13.764 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:32:13.764 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:32:13.764 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:32:13.764 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:32:13.764 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:32:13.764 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:32:13.764 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:32:13.764 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:32:13.764 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:32:13.764 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:32:13.764 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:32:13.764 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:32:13.764 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:32:13.764 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:32:13.764 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:32:13.764 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:32:13.764 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:32:13.764 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:32:13.764 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:32:13.764 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:32:13.768 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-01-29 03:32:14.245 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-01-29 03:32:14.281 [DEBUG] fake_trx.py:278 (BTS@172.18.28.20:5700) Recv FAKE_TOA cmd
2026-01-29 03:32:14.282 [DEBUG] fake_trx.py:297 (BTS@172.18.28.20:5700) Recv FAKE_RSSI cmd
2026-01-29 03:32:14.282 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:32:14.282 [DEBUG] fake_trx.py:322 (BTS@172.18.28.20:5700) Recv FAKE_CI cmd
2026-01-29 03:32:14.294 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 03:32:14.294 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 03:32:14.294 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 03:32:14.313 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 03:32:14.313 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 03:32:14.313 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 03:32:14.315 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:32:14.320 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 03:32:14.320 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 03:32:14.320 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 03:32:14.321 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.28.22:6700) Recv POWERON CMD
2026-01-29 03:32:14.321 [INFO] ctrl_if_trx.py:109 (MS@172.18.28.22:6700) Starting transceiver...
2026-01-29 03:32:14.336 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 03:32:14.337 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 03:32:14.337 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 03:32:14.337 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 03:32:14.722 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-01-29 03:32:14.766 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:32:14.766 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 03:32:14.766 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:32:14.769 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:32:15.194 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-01-29 03:32:15.672 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-01-29 03:32:15.767 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 03:32:15.767 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:32:15.767 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:32:15.770 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:32:16.150 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-01-29 03:32:16.627 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-01-29 03:32:16.768 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 03:32:16.768 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:32:16.768 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:32:16.771 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:32:17.104 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-01-29 03:32:17.581 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-01-29 03:32:17.768 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 03:32:17.769 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:32:17.769 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:32:17.771 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:32:18.058 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-01-29 03:32:18.536 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-01-29 03:32:18.769 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:32:18.770 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:32:18.770 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 03:32:18.772 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:32:19.013 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-01-29 03:32:19.340 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 03:32:19.342 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:32:19.346 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 03:32:19.346 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 03:32:19.364 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 03:32:19.364 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 03:32:19.364 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 03:32:19.370 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 03:32:19.370 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 03:32:19.370 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 03:32:19.371 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:32:19.372 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 03:32:19.373 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 03:32:19.373 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 03:32:19.373 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.28.22:6700) Recv POWERON CMD
2026-01-29 03:32:19.373 [INFO] ctrl_if_trx.py:109 (MS@172.18.28.22:6700) Starting transceiver...
2026-01-29 03:32:19.384 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.28.22:6700) Recv SETFH cmd
2026-01-29 03:32:19.384 [INFO] transceiver.py:201 (MS@172.18.28.22:6700) Frequency hopping configured: hsn=5, maio=0, ma_len=4
2026-01-29 03:32:19.384 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 03:32:19.384 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 03:32:19.487 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-01-29 03:32:19.956 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-01-29 03:32:20.429 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-01-29 03:32:20.906 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-01-29 03:32:21.375 [DEBUG] clck_gen.py:113 IND CLOCK 1632
2026-01-29 03:32:21.845 [DEBUG] clck_gen.py:113 IND CLOCK 1734
2026-01-29 03:32:22.315 [DEBUG] clck_gen.py:113 IND CLOCK 1836
2026-01-29 03:32:22.786 [DEBUG] clck_gen.py:113 IND CLOCK 1938
2026-01-29 03:32:23.256 [DEBUG] clck_gen.py:113 IND CLOCK 2040
2026-01-29 03:32:23.726 [DEBUG] clck_gen.py:113 IND CLOCK 2142
2026-01-29 03:32:24.195 [DEBUG] clck_gen.py:113 IND CLOCK 2244
2026-01-29 03:32:24.387 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 03:32:24.388 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:32:24.392 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 03:32:24.392 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 03:32:24.392 [INFO] transceiver.py:205 (MS@172.18.28.22:6700) Frequency hopping disabled
2026-01-29 03:32:24.403 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 03:32:24.403 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 03:32:24.403 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 03:32:24.409 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 03:32:24.409 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 03:32:24.409 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 03:32:24.409 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:32:24.410 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 03:32:24.410 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 03:32:24.410 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 03:32:24.410 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.28.22:6700) Recv POWERON CMD
2026-01-29 03:32:24.410 [INFO] ctrl_if_trx.py:109 (MS@172.18.28.22:6700) Starting transceiver...
2026-01-29 03:32:24.425 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 03:32:24.425 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 03:32:24.425 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 03:32:24.425 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 03:32:24.667 [DEBUG] clck_gen.py:113 IND CLOCK 2346
2026-01-29 03:32:25.145 [DEBUG] clck_gen.py:113 IND CLOCK 2448
2026-01-29 03:32:25.621 [DEBUG] clck_gen.py:113 IND CLOCK 2550
2026-01-29 03:32:26.098 [DEBUG] clck_gen.py:113 IND CLOCK 2652
2026-01-29 03:32:26.576 [DEBUG] clck_gen.py:113 IND CLOCK 2754
2026-01-29 03:32:27.051 [DEBUG] clck_gen.py:113 IND CLOCK 2856
2026-01-29 03:32:27.527 [DEBUG] clck_gen.py:113 IND CLOCK 2958
2026-01-29 03:32:28.000 [DEBUG] clck_gen.py:113 IND CLOCK 3060
2026-01-29 03:32:28.478 [DEBUG] clck_gen.py:113 IND CLOCK 3162
2026-01-29 03:32:28.956 [DEBUG] clck_gen.py:113 IND CLOCK 3264
2026-01-29 03:32:29.428 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 03:32:29.430 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:32:29.434 [DEBUG] clck_gen.py:113 IND CLOCK 3366
2026-01-29 03:32:29.434 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 03:32:29.435 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 03:32:29.455 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 03:32:29.455 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 03:32:29.455 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 03:32:29.461 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 03:32:29.461 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 03:32:29.461 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 03:32:29.461 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:32:29.462 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 03:32:29.463 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 03:32:29.463 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 03:32:29.463 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.28.22:6700) Recv POWERON CMD
2026-01-29 03:32:29.463 [INFO] ctrl_if_trx.py:109 (MS@172.18.28.22:6700) Starting transceiver...
2026-01-29 03:32:29.479 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.28.22:6700) Recv SETFH cmd
2026-01-29 03:32:29.479 [INFO] transceiver.py:201 (MS@172.18.28.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2026-01-29 03:32:29.479 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 03:32:29.479 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 03:32:29.912 [DEBUG] clck_gen.py:113 IND CLOCK 3468
2026-01-29 03:32:30.391 [DEBUG] clck_gen.py:113 IND CLOCK 3570
2026-01-29 03:32:30.870 [DEBUG] clck_gen.py:113 IND CLOCK 3672
2026-01-29 03:32:31.344 [DEBUG] clck_gen.py:113 IND CLOCK 3774
2026-01-29 03:32:31.815 [DEBUG] clck_gen.py:113 IND CLOCK 3876
2026-01-29 03:32:32.286 [DEBUG] clck_gen.py:113 IND CLOCK 3978
2026-01-29 03:32:32.755 [DEBUG] clck_gen.py:113 IND CLOCK 4080
2026-01-29 03:32:33.229 [DEBUG] clck_gen.py:113 IND CLOCK 4182
2026-01-29 03:32:33.708 [DEBUG] clck_gen.py:113 IND CLOCK 4284
2026-01-29 03:32:34.186 [DEBUG] clck_gen.py:113 IND CLOCK 4386
2026-01-29 03:32:34.484 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 03:32:34.484 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:32:34.488 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 03:32:34.488 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 03:32:34.488 [INFO] transceiver.py:205 (MS@172.18.28.22:6700) Frequency hopping disabled
2026-01-29 03:32:34.493 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 03:32:34.493 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:32:34.493 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:32:34.494 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:32:34.494 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 03:32:34.494 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 03:32:34.494 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 03:32:34.494 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 03:32:34.494 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.28.20:5700) Recv POWEROFF cmd
2026-01-29 03:32:34.494 [INFO] ctrl_if_trx.py:117 (BTS@172.18.28.20:5700) Stopping transceiver...
2026-01-29 03:32:34.494 [INFO] transceiver.py:246 Stopping clock generator
2026-01-29 03:32:39.497 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.28.20:5700) Recv POWEROFF cmd
2026-01-29 03:32:39.497 [INFO] ctrl_if_trx.py:117 (BTS@172.18.28.20:5700) Stopping transceiver...
2026-01-29 03:32:39.498 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 03:32:39.499 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 03:32:39.501 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 03:32:39.503 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 03:32:39.510 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 03:32:39.510 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.28.20:5700) Recv SETFORMAT cmd
2026-01-29 03:32:39.510 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.28.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:32:39.511 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.28.20:5700) Recv SETFORMAT cmd
2026-01-29 03:32:39.511 [INFO] ctrl_if_trx.py:201 (BTS@172.18.28.20:5700) TRXD header version 1 -> 1
2026-01-29 03:32:39.511 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.28.20:5700/1) Recv RXTUNE cmd
2026-01-29 03:32:39.512 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.28.20:5700/1) Recv TXTUNE cmd
2026-01-29 03:32:39.512 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.28.20:5700/1) Recv SETFORMAT cmd
2026-01-29 03:32:39.512 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.28.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:32:39.512 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 03:32:39.512 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.28.20:5700/1) Recv NOMTXPOWER cmd
2026-01-29 03:32:39.512 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.28.20:5700/1) Recv SETFORMAT cmd
2026-01-29 03:32:39.512 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.28.20:5700/1) TRXD header version 1 -> 1
2026-01-29 03:32:39.513 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.28.20:5700/2) Recv RXTUNE cmd
2026-01-29 03:32:39.513 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.28.20:5700/2) Recv TXTUNE cmd
2026-01-29 03:32:39.514 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.28.20:5700/2) Recv SETFORMAT cmd
2026-01-29 03:32:39.514 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.28.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:32:39.514 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 03:32:39.514 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.28.20:5700/2) Recv NOMTXPOWER cmd
2026-01-29 03:32:39.514 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.28.20:5700/2) Recv SETFORMAT cmd
2026-01-29 03:32:39.514 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.28.20:5700/2) TRXD header version 1 -> 1
2026-01-29 03:32:39.515 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.28.20:5700/3) Recv RXTUNE cmd
2026-01-29 03:32:39.515 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.28.20:5700/3) Recv TXTUNE cmd
2026-01-29 03:32:39.515 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.28.20:5700/3) Recv SETFORMAT cmd
2026-01-29 03:32:39.515 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.28.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:32:39.515 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 03:32:39.515 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.28.20:5700/3) Recv NOMTXPOWER cmd
2026-01-29 03:32:39.515 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.28.20:5700/3) Recv SETFORMAT cmd
2026-01-29 03:32:39.515 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.28.20:5700/3) TRXD header version 1 -> 1
2026-01-29 03:32:39.517 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.28.20:5700) Recv RXTUNE cmd
2026-01-29 03:32:39.517 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETTSC
2026-01-29 03:32:39.517 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETTSC
2026-01-29 03:32:39.517 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETTSC
2026-01-29 03:32:39.517 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.28.20:5700) Recv TXTUNE cmd
2026-01-29 03:32:39.517 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETRXGAIN
2026-01-29 03:32:39.517 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETRXGAIN
2026-01-29 03:32:39.518 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETRXGAIN
2026-01-29 03:32:39.518 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETTSC
2026-01-29 03:32:39.518 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:32:39.518 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:32:39.518 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.28.20:5700) Recv NOMTXPOWER cmd
2026-01-29 03:32:39.518 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:32:39.518 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:32:39.518 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:32:39.518 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.28.20:5700) Recv POWERON CMD
2026-01-29 03:32:39.518 [INFO] ctrl_if_trx.py:109 (BTS@172.18.28.20:5700) Starting transceiver...
2026-01-29 03:32:39.518 [INFO] transceiver.py:243 Starting clock generator
2026-01-29 03:32:39.518 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-01-29 03:32:39.518 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:32:39.518 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:32:39.518 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:32:39.518 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETRXGAIN
2026-01-29 03:32:39.518 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:32:39.518 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:32:39.518 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:32:39.518 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:32:39.518 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:32:39.518 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:32:39.518 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:32:39.518 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:32:39.518 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:32:39.518 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:32:39.518 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:32:39.518 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:32:39.518 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:32:39.518 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:32:39.518 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:32:39.518 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:32:39.519 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:32:39.519 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:32:39.519 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:32:39.519 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:32:39.519 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:32:39.519 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:32:39.519 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:32:39.519 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:32:39.523 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-01-29 03:32:39.999 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-01-29 03:32:40.053 [DEBUG] fake_trx.py:278 (BTS@172.18.28.20:5700) Recv FAKE_TOA cmd
2026-01-29 03:32:40.055 [DEBUG] fake_trx.py:297 (BTS@172.18.28.20:5700) Recv FAKE_RSSI cmd
2026-01-29 03:32:40.056 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:32:40.057 [DEBUG] fake_trx.py:322 (BTS@172.18.28.20:5700) Recv FAKE_CI cmd
2026-01-29 03:32:40.080 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 03:32:40.080 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 03:32:40.080 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 03:32:40.096 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 03:32:40.096 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 03:32:40.096 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 03:32:40.098 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:32:40.103 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 03:32:40.104 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 03:32:40.104 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 03:32:40.104 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.28.22:6700) Recv POWERON CMD
2026-01-29 03:32:40.104 [INFO] ctrl_if_trx.py:109 (MS@172.18.28.22:6700) Starting transceiver...
2026-01-29 03:32:40.136 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 03:32:40.136 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 03:32:40.136 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 03:32:40.136 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 03:32:40.471 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-01-29 03:32:40.520 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 03:32:40.520 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:32:40.520 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:32:40.524 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:32:40.942 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-01-29 03:32:41.418 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-01-29 03:32:41.521 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 03:32:41.521 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:32:41.521 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:32:41.524 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:32:41.895 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-01-29 03:32:42.372 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-01-29 03:32:42.521 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 03:32:42.522 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:32:42.522 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:32:42.525 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:32:42.846 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-01-29 03:32:43.315 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-01-29 03:32:43.522 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 03:32:43.523 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:32:43.523 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:32:43.526 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:32:43.790 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-01-29 03:32:44.267 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-01-29 03:32:44.523 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 03:32:44.523 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:32:44.523 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:32:44.527 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:32:44.744 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-01-29 03:32:45.140 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 03:32:45.141 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:32:45.145 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 03:32:45.145 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 03:32:45.162 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 03:32:45.162 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 03:32:45.162 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 03:32:45.168 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 03:32:45.168 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 03:32:45.168 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 03:32:45.169 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:32:45.170 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 03:32:45.170 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 03:32:45.170 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 03:32:45.170 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.28.22:6700) Recv POWERON CMD
2026-01-29 03:32:45.170 [INFO] ctrl_if_trx.py:109 (MS@172.18.28.22:6700) Starting transceiver...
2026-01-29 03:32:45.214 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.28.22:6700) Recv SETFH cmd
2026-01-29 03:32:45.215 [INFO] transceiver.py:201 (MS@172.18.28.22:6700) Frequency hopping configured: hsn=5, maio=0, ma_len=4
2026-01-29 03:32:45.215 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 03:32:45.215 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 03:32:45.220 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-01-29 03:32:45.698 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-01-29 03:32:46.174 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-01-29 03:32:46.643 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-01-29 03:32:47.113 [DEBUG] clck_gen.py:113 IND CLOCK 1632
2026-01-29 03:32:47.583 [DEBUG] clck_gen.py:113 IND CLOCK 1734
2026-01-29 03:32:48.059 [DEBUG] clck_gen.py:113 IND CLOCK 1836
2026-01-29 03:32:48.537 [DEBUG] clck_gen.py:113 IND CLOCK 1938
2026-01-29 03:32:49.017 [DEBUG] clck_gen.py:113 IND CLOCK 2040
2026-01-29 03:32:49.496 [DEBUG] clck_gen.py:113 IND CLOCK 2142
2026-01-29 03:32:49.974 [DEBUG] clck_gen.py:113 IND CLOCK 2244
2026-01-29 03:32:50.220 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 03:32:50.221 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:32:50.225 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 03:32:50.225 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 03:32:50.225 [INFO] transceiver.py:205 (MS@172.18.28.22:6700) Frequency hopping disabled
2026-01-29 03:32:50.243 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 03:32:50.244 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 03:32:50.244 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 03:32:50.250 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 03:32:50.250 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 03:32:50.250 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 03:32:50.250 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:32:50.252 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 03:32:50.252 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 03:32:50.252 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 03:32:50.252 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.28.22:6700) Recv POWERON CMD
2026-01-29 03:32:50.252 [INFO] ctrl_if_trx.py:109 (MS@172.18.28.22:6700) Starting transceiver...
2026-01-29 03:32:50.301 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 03:32:50.301 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 03:32:50.301 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 03:32:50.302 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 03:32:50.450 [DEBUG] clck_gen.py:113 IND CLOCK 2346
2026-01-29 03:32:50.927 [DEBUG] clck_gen.py:113 IND CLOCK 2448
2026-01-29 03:32:51.400 [DEBUG] clck_gen.py:113 IND CLOCK 2550
2026-01-29 03:32:51.879 [DEBUG] clck_gen.py:113 IND CLOCK 2652
2026-01-29 03:32:52.356 [DEBUG] clck_gen.py:113 IND CLOCK 2754
2026-01-29 03:32:52.833 [DEBUG] clck_gen.py:113 IND CLOCK 2856
2026-01-29 03:32:53.310 [DEBUG] clck_gen.py:113 IND CLOCK 2958
2026-01-29 03:32:53.782 [DEBUG] clck_gen.py:113 IND CLOCK 3060
2026-01-29 03:32:54.259 [DEBUG] clck_gen.py:113 IND CLOCK 3162
2026-01-29 03:32:54.731 [DEBUG] clck_gen.py:113 IND CLOCK 3264
2026-01-29 03:32:55.209 [DEBUG] clck_gen.py:113 IND CLOCK 3366
2026-01-29 03:32:55.306 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 03:32:55.307 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:32:55.309 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 03:32:55.309 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 03:32:55.324 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 03:32:55.324 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 03:32:55.325 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 03:32:55.331 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 03:32:55.331 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 03:32:55.331 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 03:32:55.331 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:32:55.333 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 03:32:55.333 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 03:32:55.333 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 03:32:55.333 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.28.22:6700) Recv POWERON CMD
2026-01-29 03:32:55.333 [INFO] ctrl_if_trx.py:109 (MS@172.18.28.22:6700) Starting transceiver...
2026-01-29 03:32:55.344 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.28.22:6700) Recv SETFH cmd
2026-01-29 03:32:55.344 [INFO] transceiver.py:201 (MS@172.18.28.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2026-01-29 03:32:55.344 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 03:32:55.344 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 03:32:55.680 [DEBUG] clck_gen.py:113 IND CLOCK 3468
2026-01-29 03:32:56.156 [DEBUG] clck_gen.py:113 IND CLOCK 3570
2026-01-29 03:32:56.634 [DEBUG] clck_gen.py:113 IND CLOCK 3672
2026-01-29 03:32:57.110 [DEBUG] clck_gen.py:113 IND CLOCK 3774
2026-01-29 03:32:57.588 [DEBUG] clck_gen.py:113 IND CLOCK 3876
2026-01-29 03:32:58.065 [DEBUG] clck_gen.py:113 IND CLOCK 3978
2026-01-29 03:32:58.542 [DEBUG] clck_gen.py:113 IND CLOCK 4080
2026-01-29 03:32:59.019 [DEBUG] clck_gen.py:113 IND CLOCK 4182
2026-01-29 03:32:59.497 [DEBUG] clck_gen.py:113 IND CLOCK 4284
2026-01-29 03:32:59.967 [DEBUG] clck_gen.py:113 IND CLOCK 4386
2026-01-29 03:33:00.347 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 03:33:00.348 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:33:00.350 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 03:33:00.350 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 03:33:00.351 [INFO] transceiver.py:205 (MS@172.18.28.22:6700) Frequency hopping disabled
2026-01-29 03:33:00.365 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 03:33:00.365 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:33:00.365 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:33:00.365 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:33:00.369 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 03:33:00.369 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 03:33:00.369 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 03:33:00.369 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 03:33:00.369 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.28.20:5700) Recv POWEROFF cmd
2026-01-29 03:33:00.369 [INFO] ctrl_if_trx.py:117 (BTS@172.18.28.20:5700) Stopping transceiver...
2026-01-29 03:33:00.369 [INFO] transceiver.py:246 Stopping clock generator
2026-01-29 03:33:00.370 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=4475 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:33:00.370 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=4475 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:33:00.370 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=4475 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:33:00.370 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=4475 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:33:00.370 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=4475 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:33:00.370 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=4475 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:33:00.371 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=4476 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:33:00.371 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=4476 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:33:00.371 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=4476 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:33:00.371 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=4476 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:33:00.371 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=4476 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:33:00.371 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=4476 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:33:00.371 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=4476 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:33:00.371 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=4476 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:33:05.368 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.28.20:5700) Recv POWEROFF cmd
2026-01-29 03:33:05.368 [INFO] ctrl_if_trx.py:117 (BTS@172.18.28.20:5700) Stopping transceiver...
2026-01-29 03:33:05.369 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 03:33:05.370 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 03:33:05.371 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 03:33:05.373 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 03:33:05.382 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 03:33:05.383 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.28.20:5700) Recv SETFORMAT cmd
2026-01-29 03:33:05.383 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.28.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:33:05.383 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.28.20:5700) Recv SETFORMAT cmd
2026-01-29 03:33:05.383 [INFO] ctrl_if_trx.py:201 (BTS@172.18.28.20:5700) TRXD header version 1 -> 1
2026-01-29 03:33:05.386 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.28.20:5700/1) Recv RXTUNE cmd
2026-01-29 03:33:05.386 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.28.20:5700/1) Recv TXTUNE cmd
2026-01-29 03:33:05.386 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.28.20:5700/1) Recv SETFORMAT cmd
2026-01-29 03:33:05.386 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.28.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:33:05.386 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 03:33:05.386 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.28.20:5700/1) Recv NOMTXPOWER cmd
2026-01-29 03:33:05.386 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.28.20:5700/1) Recv SETFORMAT cmd
2026-01-29 03:33:05.386 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.28.20:5700/1) TRXD header version 1 -> 1
2026-01-29 03:33:05.389 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.28.20:5700/2) Recv RXTUNE cmd
2026-01-29 03:33:05.389 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.28.20:5700/2) Recv TXTUNE cmd
2026-01-29 03:33:05.389 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.28.20:5700/2) Recv SETFORMAT cmd
2026-01-29 03:33:05.389 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.28.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:33:05.389 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 03:33:05.389 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.28.20:5700/2) Recv NOMTXPOWER cmd
2026-01-29 03:33:05.389 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.28.20:5700/2) Recv SETFORMAT cmd
2026-01-29 03:33:05.389 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.28.20:5700/2) TRXD header version 1 -> 1
2026-01-29 03:33:05.391 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.28.20:5700/3) Recv RXTUNE cmd
2026-01-29 03:33:05.391 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.28.20:5700/3) Recv TXTUNE cmd
2026-01-29 03:33:05.391 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.28.20:5700/3) Recv SETFORMAT cmd
2026-01-29 03:33:05.391 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.28.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:33:05.391 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 03:33:05.391 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.28.20:5700/3) Recv NOMTXPOWER cmd
2026-01-29 03:33:05.391 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.28.20:5700/3) Recv SETFORMAT cmd
2026-01-29 03:33:05.391 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.28.20:5700/3) TRXD header version 1 -> 1
2026-01-29 03:33:05.394 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.28.20:5700) Recv RXTUNE cmd
2026-01-29 03:33:05.394 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETTSC
2026-01-29 03:33:05.394 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETTSC
2026-01-29 03:33:05.394 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETTSC
2026-01-29 03:33:05.394 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.28.20:5700) Recv TXTUNE cmd
2026-01-29 03:33:05.394 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETRXGAIN
2026-01-29 03:33:05.394 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETRXGAIN
2026-01-29 03:33:05.394 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETTSC
2026-01-29 03:33:05.394 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:33:05.394 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETRXGAIN
2026-01-29 03:33:05.394 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:33:05.394 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.28.20:5700) Recv NOMTXPOWER cmd
2026-01-29 03:33:05.394 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:33:05.394 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:33:05.394 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:33:05.394 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.28.20:5700) Recv POWERON CMD
2026-01-29 03:33:05.394 [INFO] ctrl_if_trx.py:109 (BTS@172.18.28.20:5700) Starting transceiver...
2026-01-29 03:33:05.394 [INFO] transceiver.py:243 Starting clock generator
2026-01-29 03:33:05.394 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-01-29 03:33:05.394 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:33:05.394 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:33:05.394 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:33:05.395 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETRXGAIN
2026-01-29 03:33:05.395 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:33:05.395 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:33:05.395 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:33:05.395 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:33:05.395 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:33:05.395 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:33:05.395 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:33:05.395 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:33:05.395 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:33:05.395 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:33:05.395 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:33:05.395 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:33:05.395 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:33:05.395 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:33:05.395 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:33:05.395 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:33:05.395 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:33:05.395 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:33:05.395 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:33:05.395 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:33:05.395 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:33:05.395 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:33:05.395 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:33:05.395 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:33:05.399 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-01-29 03:33:05.876 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-01-29 03:33:05.924 [DEBUG] fake_trx.py:278 (BTS@172.18.28.20:5700) Recv FAKE_TOA cmd
2026-01-29 03:33:05.925 [DEBUG] fake_trx.py:297 (BTS@172.18.28.20:5700) Recv FAKE_RSSI cmd
2026-01-29 03:33:05.925 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:33:05.926 [DEBUG] fake_trx.py:322 (BTS@172.18.28.20:5700) Recv FAKE_CI cmd
2026-01-29 03:33:05.941 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 03:33:05.941 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 03:33:05.941 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 03:33:05.954 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 03:33:05.954 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 03:33:05.954 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 03:33:05.956 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:33:05.959 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 03:33:05.959 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 03:33:05.959 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 03:33:05.959 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.28.22:6700) Recv POWERON CMD
2026-01-29 03:33:05.959 [INFO] ctrl_if_trx.py:109 (MS@172.18.28.22:6700) Starting transceiver...
2026-01-29 03:33:05.966 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 03:33:05.966 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 03:33:05.966 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 03:33:05.966 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 03:33:06.352 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-01-29 03:33:06.397 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 03:33:06.397 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:33:06.398 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:33:06.402 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:33:06.829 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-01-29 03:33:07.305 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-01-29 03:33:07.398 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 03:33:07.398 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:33:07.399 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:33:07.403 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:33:07.782 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-01-29 03:33:08.259 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-01-29 03:33:08.399 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:33:08.399 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 03:33:08.400 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:33:08.403 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:33:08.733 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-01-29 03:33:09.209 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-01-29 03:33:09.399 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:33:09.400 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 03:33:09.402 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:33:09.404 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:33:09.683 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-01-29 03:33:10.152 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-01-29 03:33:10.400 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 03:33:10.400 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:33:10.403 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:33:10.404 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:33:10.629 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-01-29 03:33:10.968 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 03:33:10.969 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:33:10.972 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 03:33:10.972 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 03:33:10.989 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 03:33:10.989 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 03:33:10.989 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 03:33:10.995 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 03:33:10.995 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 03:33:10.995 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 03:33:10.996 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:33:10.997 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 03:33:10.997 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 03:33:10.997 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 03:33:10.997 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.28.22:6700) Recv POWERON CMD
2026-01-29 03:33:10.997 [INFO] ctrl_if_trx.py:109 (MS@172.18.28.22:6700) Starting transceiver...
2026-01-29 03:33:10.999 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.28.22:6700) Recv SETFH cmd
2026-01-29 03:33:10.999 [INFO] transceiver.py:201 (MS@172.18.28.22:6700) Frequency hopping configured: hsn=5, maio=0, ma_len=4
2026-01-29 03:33:10.999 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 03:33:10.999 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 03:33:11.103 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-01-29 03:33:11.572 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-01-29 03:33:12.042 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-01-29 03:33:12.519 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-01-29 03:33:12.997 [DEBUG] clck_gen.py:113 IND CLOCK 1632
2026-01-29 03:33:13.473 [DEBUG] clck_gen.py:113 IND CLOCK 1734
2026-01-29 03:33:13.945 [DEBUG] clck_gen.py:113 IND CLOCK 1836
2026-01-29 03:33:14.423 [DEBUG] clck_gen.py:113 IND CLOCK 1938
2026-01-29 03:33:14.901 [DEBUG] clck_gen.py:113 IND CLOCK 2040
2026-01-29 03:33:15.379 [DEBUG] clck_gen.py:113 IND CLOCK 2142
2026-01-29 03:33:15.856 [DEBUG] clck_gen.py:113 IND CLOCK 2244
2026-01-29 03:33:16.001 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 03:33:16.002 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:33:16.005 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 03:33:16.005 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 03:33:16.005 [INFO] transceiver.py:205 (MS@172.18.28.22:6700) Frequency hopping disabled
2026-01-29 03:33:16.024 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 03:33:16.024 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 03:33:16.024 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 03:33:16.031 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 03:33:16.031 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 03:33:16.031 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 03:33:16.031 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:33:16.032 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 03:33:16.032 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 03:33:16.032 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 03:33:16.032 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.28.22:6700) Recv POWERON CMD
2026-01-29 03:33:16.032 [INFO] ctrl_if_trx.py:109 (MS@172.18.28.22:6700) Starting transceiver...
2026-01-29 03:33:16.037 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 03:33:16.037 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 03:33:16.037 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 03:33:16.037 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 03:33:16.329 [DEBUG] clck_gen.py:113 IND CLOCK 2346
2026-01-29 03:33:16.806 [DEBUG] clck_gen.py:113 IND CLOCK 2448
2026-01-29 03:33:17.282 [DEBUG] clck_gen.py:113 IND CLOCK 2550
2026-01-29 03:33:17.759 [DEBUG] clck_gen.py:113 IND CLOCK 2652
2026-01-29 03:33:18.233 [DEBUG] clck_gen.py:113 IND CLOCK 2754
2026-01-29 03:33:18.702 [DEBUG] clck_gen.py:113 IND CLOCK 2856
2026-01-29 03:33:19.178 [DEBUG] clck_gen.py:113 IND CLOCK 2958
2026-01-29 03:33:19.654 [DEBUG] clck_gen.py:113 IND CLOCK 3060
2026-01-29 03:33:20.132 [DEBUG] clck_gen.py:113 IND CLOCK 3162
2026-01-29 03:33:20.607 [DEBUG] clck_gen.py:113 IND CLOCK 3264
2026-01-29 03:33:21.038 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 03:33:21.039 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:33:21.044 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 03:33:21.044 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 03:33:21.064 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 03:33:21.064 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 03:33:21.064 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 03:33:21.070 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 03:33:21.070 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 03:33:21.071 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 03:33:21.071 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:33:21.073 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 03:33:21.073 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 03:33:21.073 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 03:33:21.073 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.28.22:6700) Recv POWERON CMD
2026-01-29 03:33:21.073 [INFO] ctrl_if_trx.py:109 (MS@172.18.28.22:6700) Starting transceiver...
2026-01-29 03:33:21.083 [DEBUG] clck_gen.py:113 IND CLOCK 3366
2026-01-29 03:33:21.129 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.28.22:6700) Recv SETFH cmd
2026-01-29 03:33:21.129 [INFO] transceiver.py:201 (MS@172.18.28.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2026-01-29 03:33:21.129 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 03:33:21.130 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 03:33:21.560 [DEBUG] clck_gen.py:113 IND CLOCK 3468
2026-01-29 03:33:22.037 [DEBUG] clck_gen.py:113 IND CLOCK 3570
2026-01-29 03:33:22.514 [DEBUG] clck_gen.py:113 IND CLOCK 3672
2026-01-29 03:33:22.992 [DEBUG] clck_gen.py:113 IND CLOCK 3774
2026-01-29 03:33:23.470 [DEBUG] clck_gen.py:113 IND CLOCK 3876
2026-01-29 03:33:23.947 [DEBUG] clck_gen.py:113 IND CLOCK 3978
2026-01-29 03:33:24.425 [DEBUG] clck_gen.py:113 IND CLOCK 4080
2026-01-29 03:33:24.903 [DEBUG] clck_gen.py:113 IND CLOCK 4182
2026-01-29 03:33:25.375 [DEBUG] clck_gen.py:113 IND CLOCK 4284
2026-01-29 03:33:25.849 [DEBUG] clck_gen.py:113 IND CLOCK 4386
2026-01-29 03:33:26.133 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 03:33:26.134 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:33:26.138 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 03:33:26.138 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 03:33:26.138 [INFO] transceiver.py:205 (MS@172.18.28.22:6700) Frequency hopping disabled
2026-01-29 03:33:26.149 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 03:33:26.149 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:33:26.149 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:33:26.149 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:33:26.153 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 03:33:26.153 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 03:33:26.153 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 03:33:26.153 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.28.20:5700) Recv POWEROFF cmd
2026-01-29 03:33:26.153 [INFO] ctrl_if_trx.py:117 (BTS@172.18.28.20:5700) Stopping transceiver...
2026-01-29 03:33:26.153 [INFO] transceiver.py:246 Stopping clock generator
2026-01-29 03:33:26.154 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 03:33:26.154 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=4454 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:33:26.154 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=4454 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:33:26.154 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=4454 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:33:26.154 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=4454 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:33:26.154 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=4454 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:33:26.155 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=4454 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:33:26.155 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=4454 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:33:31.150 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.28.20:5700) Recv POWEROFF cmd
2026-01-29 03:33:31.151 [INFO] ctrl_if_trx.py:117 (BTS@172.18.28.20:5700) Stopping transceiver...
2026-01-29 03:33:31.152 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 03:33:31.154 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 03:33:31.154 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 03:33:31.155 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 03:33:31.157 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 03:33:31.157 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.28.20:5700) Recv SETFORMAT cmd
2026-01-29 03:33:31.157 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.28.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:33:31.157 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.28.20:5700) Recv SETFORMAT cmd
2026-01-29 03:33:31.157 [INFO] ctrl_if_trx.py:201 (BTS@172.18.28.20:5700) TRXD header version 1 -> 1
2026-01-29 03:33:31.159 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.28.20:5700/1) Recv RXTUNE cmd
2026-01-29 03:33:31.159 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.28.20:5700/1) Recv TXTUNE cmd
2026-01-29 03:33:31.159 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.28.20:5700/1) Recv SETFORMAT cmd
2026-01-29 03:33:31.160 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.28.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:33:31.160 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 03:33:31.160 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.28.20:5700/1) Recv NOMTXPOWER cmd
2026-01-29 03:33:31.160 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.28.20:5700/1) Recv SETFORMAT cmd
2026-01-29 03:33:31.160 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.28.20:5700/1) TRXD header version 1 -> 1
2026-01-29 03:33:31.162 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.28.20:5700/2) Recv RXTUNE cmd
2026-01-29 03:33:31.162 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.28.20:5700/2) Recv TXTUNE cmd
2026-01-29 03:33:31.162 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.28.20:5700/2) Recv SETFORMAT cmd
2026-01-29 03:33:31.162 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.28.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:33:31.162 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 03:33:31.162 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.28.20:5700/2) Recv NOMTXPOWER cmd
2026-01-29 03:33:31.162 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.28.20:5700/2) Recv SETFORMAT cmd
2026-01-29 03:33:31.162 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.28.20:5700/2) TRXD header version 1 -> 1
2026-01-29 03:33:31.164 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.28.20:5700/3) Recv RXTUNE cmd
2026-01-29 03:33:31.164 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.28.20:5700/3) Recv TXTUNE cmd
2026-01-29 03:33:31.164 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.28.20:5700/3) Recv SETFORMAT cmd
2026-01-29 03:33:31.164 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.28.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:33:31.164 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 03:33:31.164 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.28.20:5700/3) Recv NOMTXPOWER cmd
2026-01-29 03:33:31.164 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.28.20:5700/3) Recv SETFORMAT cmd
2026-01-29 03:33:31.164 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.28.20:5700/3) TRXD header version 1 -> 1
2026-01-29 03:33:31.166 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.28.20:5700) Recv RXTUNE cmd
2026-01-29 03:33:31.166 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETTSC
2026-01-29 03:33:31.166 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETTSC
2026-01-29 03:33:31.166 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETTSC
2026-01-29 03:33:31.166 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.28.20:5700) Recv TXTUNE cmd
2026-01-29 03:33:31.166 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETRXGAIN
2026-01-29 03:33:31.166 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETRXGAIN
2026-01-29 03:33:31.166 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETRXGAIN
2026-01-29 03:33:31.166 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETTSC
2026-01-29 03:33:31.166 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:33:31.166 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:33:31.166 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:33:31.166 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.28.20:5700) Recv NOMTXPOWER cmd
2026-01-29 03:33:31.166 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:33:31.166 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:33:31.166 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:33:31.166 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.28.20:5700) Recv POWERON CMD
2026-01-29 03:33:31.166 [INFO] ctrl_if_trx.py:109 (BTS@172.18.28.20:5700) Starting transceiver...
2026-01-29 03:33:31.166 [INFO] transceiver.py:243 Starting clock generator
2026-01-29 03:33:31.166 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-01-29 03:33:31.166 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:33:31.166 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:33:31.167 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:33:31.167 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETRXGAIN
2026-01-29 03:33:31.167 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:33:31.167 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:33:31.167 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:33:31.167 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:33:31.167 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:33:31.167 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:33:31.167 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:33:31.167 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:33:31.167 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:33:31.167 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:33:31.167 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:33:31.167 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:33:31.167 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:33:31.167 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:33:31.167 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:33:31.167 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:33:31.167 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:33:31.167 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:33:31.167 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:33:31.167 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:33:31.167 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:33:31.167 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:33:31.167 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:33:31.171 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-01-29 03:33:31.648 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-01-29 03:33:31.693 [DEBUG] fake_trx.py:278 (BTS@172.18.28.20:5700) Recv FAKE_TOA cmd
2026-01-29 03:33:31.695 [DEBUG] fake_trx.py:297 (BTS@172.18.28.20:5700) Recv FAKE_RSSI cmd
2026-01-29 03:33:31.697 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:33:31.697 [DEBUG] fake_trx.py:322 (BTS@172.18.28.20:5700) Recv FAKE_CI cmd
2026-01-29 03:33:31.723 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 03:33:31.723 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 03:33:31.724 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 03:33:31.746 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 03:33:31.746 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 03:33:31.746 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 03:33:31.747 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:33:31.754 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 03:33:31.754 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 03:33:31.754 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 03:33:31.755 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.28.22:6700) Recv POWERON CMD
2026-01-29 03:33:31.755 [INFO] ctrl_if_trx.py:109 (MS@172.18.28.22:6700) Starting transceiver...
2026-01-29 03:33:31.786 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 03:33:31.787 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 03:33:31.787 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 03:33:31.788 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 03:33:32.026 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 03:33:32.026 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:33:32.029 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 03:33:32.029 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 03:33:32.047 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 03:33:32.047 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 03:33:32.047 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 03:33:32.054 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 03:33:32.054 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 03:33:32.054 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 03:33:32.054 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:33:32.055 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 03:33:32.056 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 03:33:32.056 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 03:33:32.056 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.28.22:6700) Recv POWERON CMD
2026-01-29 03:33:32.056 [INFO] ctrl_if_trx.py:109 (MS@172.18.28.22:6700) Starting transceiver...
2026-01-29 03:33:32.065 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.28.22:6700) Recv SETFH cmd
2026-01-29 03:33:32.065 [INFO] transceiver.py:201 (MS@172.18.28.22:6700) Frequency hopping configured: hsn=5, maio=0, ma_len=4
2026-01-29 03:33:32.065 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 03:33:32.066 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 03:33:32.122 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-01-29 03:33:32.169 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:33:32.169 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 03:33:32.169 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:33:32.172 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:33:32.446 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 03:33:32.446 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:33:32.450 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 03:33:32.450 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 03:33:32.450 [INFO] transceiver.py:205 (MS@172.18.28.22:6700) Frequency hopping disabled
2026-01-29 03:33:32.468 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 03:33:32.468 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 03:33:32.468 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 03:33:32.475 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 03:33:32.475 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 03:33:32.475 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 03:33:32.475 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:33:32.476 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 03:33:32.476 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 03:33:32.476 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 03:33:32.477 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.28.22:6700) Recv POWERON CMD
2026-01-29 03:33:32.477 [INFO] ctrl_if_trx.py:109 (MS@172.18.28.22:6700) Starting transceiver...
2026-01-29 03:33:32.490 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 03:33:32.490 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 03:33:32.490 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 03:33:32.490 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 03:33:32.591 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-01-29 03:33:33.069 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-01-29 03:33:33.170 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 03:33:33.170 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:33:33.170 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:33:33.173 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:33:33.225 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 03:33:33.226 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:33:33.230 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 03:33:33.230 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 03:33:33.249 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 03:33:33.249 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 03:33:33.249 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 03:33:33.255 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 03:33:33.255 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 03:33:33.255 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 03:33:33.256 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:33:33.257 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 03:33:33.257 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 03:33:33.257 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 03:33:33.257 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.28.22:6700) Recv POWERON CMD
2026-01-29 03:33:33.257 [INFO] ctrl_if_trx.py:109 (MS@172.18.28.22:6700) Starting transceiver...
2026-01-29 03:33:33.304 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.28.22:6700) Recv SETFH cmd
2026-01-29 03:33:33.304 [INFO] transceiver.py:201 (MS@172.18.28.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2026-01-29 03:33:33.304 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 03:33:33.304 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 03:33:33.544 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-01-29 03:33:33.857 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 03:33:33.858 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:33:33.861 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 03:33:33.861 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 03:33:33.861 [INFO] transceiver.py:205 (MS@172.18.28.22:6700) Frequency hopping disabled
2026-01-29 03:33:33.871 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 03:33:33.871 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:33:33.872 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:33:33.872 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:33:33.875 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 03:33:33.875 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 03:33:33.875 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 03:33:33.875 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 03:33:33.876 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.28.20:5700) Recv POWEROFF cmd
2026-01-29 03:33:33.876 [INFO] ctrl_if_trx.py:117 (BTS@172.18.28.20:5700) Stopping transceiver...
2026-01-29 03:33:33.876 [INFO] transceiver.py:246 Stopping clock generator
2026-01-29 03:33:33.876 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=584 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:33:33.876 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=584 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:33:33.876 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=584 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:33:33.876 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=584 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:33:33.877 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=584 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:33:33.877 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=584 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:33:38.874 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.28.20:5700) Recv POWEROFF cmd
2026-01-29 03:33:38.874 [INFO] ctrl_if_trx.py:117 (BTS@172.18.28.20:5700) Stopping transceiver...
2026-01-29 03:33:38.877 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 03:33:38.877 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 03:33:38.877 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 03:33:38.877 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 03:33:38.886 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 03:33:38.887 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.28.20:5700) Recv SETFORMAT cmd
2026-01-29 03:33:38.887 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.28.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:33:38.888 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.28.20:5700) Recv SETFORMAT cmd
2026-01-29 03:33:38.888 [INFO] ctrl_if_trx.py:201 (BTS@172.18.28.20:5700) TRXD header version 1 -> 1
2026-01-29 03:33:38.892 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.28.20:5700/1) Recv RXTUNE cmd
2026-01-29 03:33:38.892 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.28.20:5700/1) Recv TXTUNE cmd
2026-01-29 03:33:38.892 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.28.20:5700/1) Recv SETFORMAT cmd
2026-01-29 03:33:38.892 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.28.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:33:38.893 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 03:33:38.893 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.28.20:5700/1) Recv NOMTXPOWER cmd
2026-01-29 03:33:38.893 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.28.20:5700/1) Recv SETFORMAT cmd
2026-01-29 03:33:38.893 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.28.20:5700/1) TRXD header version 1 -> 1
2026-01-29 03:33:38.896 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.28.20:5700/2) Recv RXTUNE cmd
2026-01-29 03:33:38.896 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.28.20:5700/2) Recv TXTUNE cmd
2026-01-29 03:33:38.896 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.28.20:5700/2) Recv SETFORMAT cmd
2026-01-29 03:33:38.896 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.28.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:33:38.896 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 03:33:38.896 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.28.20:5700/2) Recv NOMTXPOWER cmd
2026-01-29 03:33:38.896 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.28.20:5700/2) Recv SETFORMAT cmd
2026-01-29 03:33:38.896 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.28.20:5700/2) TRXD header version 1 -> 1
2026-01-29 03:33:38.898 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.28.20:5700/3) Recv RXTUNE cmd
2026-01-29 03:33:38.899 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.28.20:5700/3) Recv TXTUNE cmd
2026-01-29 03:33:38.899 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.28.20:5700/3) Recv SETFORMAT cmd
2026-01-29 03:33:38.899 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.28.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:33:38.899 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 03:33:38.899 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.28.20:5700/3) Recv NOMTXPOWER cmd
2026-01-29 03:33:38.899 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.28.20:5700/3) Recv SETFORMAT cmd
2026-01-29 03:33:38.899 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.28.20:5700/3) TRXD header version 1 -> 1
2026-01-29 03:33:38.902 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.28.20:5700) Recv RXTUNE cmd
2026-01-29 03:33:38.902 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETTSC
2026-01-29 03:33:38.902 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETTSC
2026-01-29 03:33:38.902 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETTSC
2026-01-29 03:33:38.902 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.28.20:5700) Recv TXTUNE cmd
2026-01-29 03:33:38.902 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETRXGAIN
2026-01-29 03:33:38.902 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETRXGAIN
2026-01-29 03:33:38.902 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETRXGAIN
2026-01-29 03:33:38.902 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETTSC
2026-01-29 03:33:38.902 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:33:38.902 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:33:38.902 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.28.20:5700) Recv NOMTXPOWER cmd
2026-01-29 03:33:38.902 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:33:38.902 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:33:38.903 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:33:38.903 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.28.20:5700) Recv POWERON CMD
2026-01-29 03:33:38.903 [INFO] ctrl_if_trx.py:109 (BTS@172.18.28.20:5700) Starting transceiver...
2026-01-29 03:33:38.903 [INFO] transceiver.py:243 Starting clock generator
2026-01-29 03:33:38.903 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-01-29 03:33:38.903 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:33:38.903 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:33:38.903 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:33:38.903 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETRXGAIN
2026-01-29 03:33:38.903 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:33:38.903 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:33:38.903 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:33:38.903 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:33:38.903 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:33:38.903 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:33:38.903 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:33:38.903 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:33:38.903 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:33:38.903 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:33:38.903 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:33:38.903 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:33:38.904 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:33:38.904 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:33:38.904 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:33:38.904 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:33:38.904 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:33:38.904 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:33:38.904 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:33:38.904 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:33:38.904 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:33:38.904 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:33:38.904 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:33:38.904 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:33:38.908 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-01-29 03:33:39.379 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-01-29 03:33:39.433 [DEBUG] fake_trx.py:278 (BTS@172.18.28.20:5700) Recv FAKE_TOA cmd
2026-01-29 03:33:39.436 [DEBUG] fake_trx.py:297 (BTS@172.18.28.20:5700) Recv FAKE_RSSI cmd
2026-01-29 03:33:39.437 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:33:39.438 [DEBUG] fake_trx.py:322 (BTS@172.18.28.20:5700) Recv FAKE_CI cmd
2026-01-29 03:33:39.459 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 03:33:39.459 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 03:33:39.459 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 03:33:39.479 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 03:33:39.480 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 03:33:39.480 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 03:33:39.482 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:33:39.487 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 03:33:39.488 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 03:33:39.488 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 03:33:39.488 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.28.22:6700) Recv POWERON CMD
2026-01-29 03:33:39.488 [INFO] ctrl_if_trx.py:109 (MS@172.18.28.22:6700) Starting transceiver...
2026-01-29 03:33:39.516 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 03:33:39.516 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 03:33:39.516 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 03:33:39.516 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 03:33:39.852 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-01-29 03:33:39.905 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 03:33:39.906 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:33:39.907 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:33:39.910 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:33:40.328 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-01-29 03:33:40.806 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-01-29 03:33:40.907 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 03:33:40.907 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:33:40.907 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:33:40.911 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:33:41.284 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-01-29 03:33:41.761 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-01-29 03:33:41.908 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:33:41.908 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:33:41.908 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 03:33:41.913 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:33:42.238 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-01-29 03:33:42.715 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-01-29 03:33:42.909 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 03:33:42.909 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:33:42.909 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:33:42.913 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:33:43.189 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-01-29 03:33:43.661 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-01-29 03:33:43.910 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:33:43.910 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:33:43.910 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 03:33:43.914 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:33:44.134 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-01-29 03:33:44.611 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-01-29 03:33:45.088 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-01-29 03:33:45.565 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-01-29 03:33:46.042 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-01-29 03:33:46.519 [DEBUG] clck_gen.py:113 IND CLOCK 1632
2026-01-29 03:33:46.995 [DEBUG] clck_gen.py:113 IND CLOCK 1734
2026-01-29 03:33:47.472 [DEBUG] clck_gen.py:113 IND CLOCK 1836
2026-01-29 03:33:47.949 [DEBUG] clck_gen.py:113 IND CLOCK 1938
2026-01-29 03:33:48.425 [DEBUG] clck_gen.py:113 IND CLOCK 2040
2026-01-29 03:33:48.902 [DEBUG] clck_gen.py:113 IND CLOCK 2142
2026-01-29 03:33:49.379 [DEBUG] clck_gen.py:113 IND CLOCK 2244
2026-01-29 03:33:49.856 [DEBUG] clck_gen.py:113 IND CLOCK 2346
2026-01-29 03:33:50.332 [DEBUG] clck_gen.py:113 IND CLOCK 2448
2026-01-29 03:33:50.809 [DEBUG] clck_gen.py:113 IND CLOCK 2550
2026-01-29 03:33:51.285 [DEBUG] clck_gen.py:113 IND CLOCK 2652
2026-01-29 03:33:51.762 [DEBUG] clck_gen.py:113 IND CLOCK 2754
2026-01-29 03:33:52.238 [DEBUG] clck_gen.py:113 IND CLOCK 2856
2026-01-29 03:33:52.715 [DEBUG] clck_gen.py:113 IND CLOCK 2958
2026-01-29 03:33:53.192 [DEBUG] clck_gen.py:113 IND CLOCK 3060
2026-01-29 03:33:53.668 [DEBUG] clck_gen.py:113 IND CLOCK 3162
2026-01-29 03:33:54.145 [DEBUG] clck_gen.py:113 IND CLOCK 3264
2026-01-29 03:33:54.622 [DEBUG] clck_gen.py:113 IND CLOCK 3366
2026-01-29 03:33:55.098 [DEBUG] clck_gen.py:113 IND CLOCK 3468
2026-01-29 03:33:55.575 [DEBUG] clck_gen.py:113 IND CLOCK 3570
2026-01-29 03:33:56.051 [DEBUG] clck_gen.py:113 IND CLOCK 3672
2026-01-29 03:33:56.528 [DEBUG] clck_gen.py:113 IND CLOCK 3774
2026-01-29 03:33:57.004 [DEBUG] clck_gen.py:113 IND CLOCK 3876
2026-01-29 03:33:57.481 [DEBUG] clck_gen.py:113 IND CLOCK 3978
2026-01-29 03:33:57.958 [DEBUG] clck_gen.py:113 IND CLOCK 4080
2026-01-29 03:33:58.430 [DEBUG] clck_gen.py:113 IND CLOCK 4182
2026-01-29 03:33:58.904 [DEBUG] clck_gen.py:113 IND CLOCK 4284
2026-01-29 03:33:59.381 [DEBUG] clck_gen.py:113 IND CLOCK 4386
2026-01-29 03:33:59.518 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 03:33:59.519 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:33:59.526 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 03:33:59.526 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 03:33:59.542 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 03:33:59.542 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 03:33:59.542 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 03:33:59.548 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 03:33:59.548 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 03:33:59.549 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 03:33:59.549 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:33:59.550 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 03:33:59.550 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 03:33:59.550 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 03:33:59.550 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.28.22:6700) Recv POWERON CMD
2026-01-29 03:33:59.550 [INFO] ctrl_if_trx.py:109 (MS@172.18.28.22:6700) Starting transceiver...
2026-01-29 03:33:59.563 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.28.22:6700) Recv SETFH cmd
2026-01-29 03:33:59.563 [INFO] transceiver.py:201 (MS@172.18.28.22:6700) Frequency hopping configured: hsn=5, maio=0, ma_len=4
2026-01-29 03:33:59.563 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 03:33:59.563 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 03:33:59.853 [DEBUG] clck_gen.py:113 IND CLOCK 4488
2026-01-29 03:34:00.324 [DEBUG] clck_gen.py:113 IND CLOCK 4590
2026-01-29 03:34:00.796 [DEBUG] clck_gen.py:113 IND CLOCK 4692
2026-01-29 03:34:01.265 [DEBUG] clck_gen.py:113 IND CLOCK 4794
2026-01-29 03:34:01.736 [DEBUG] clck_gen.py:113 IND CLOCK 4896
2026-01-29 03:34:02.210 [DEBUG] clck_gen.py:113 IND CLOCK 4998
2026-01-29 03:34:02.682 [DEBUG] clck_gen.py:113 IND CLOCK 5100
2026-01-29 03:34:03.151 [DEBUG] clck_gen.py:113 IND CLOCK 5202
2026-01-29 03:34:03.620 [DEBUG] clck_gen.py:113 IND CLOCK 5304
2026-01-29 03:34:04.091 [DEBUG] clck_gen.py:113 IND CLOCK 5406
2026-01-29 03:34:04.561 [DEBUG] clck_gen.py:113 IND CLOCK 5508
2026-01-29 03:34:05.037 [DEBUG] clck_gen.py:113 IND CLOCK 5610
2026-01-29 03:34:05.515 [DEBUG] clck_gen.py:113 IND CLOCK 5712
2026-01-29 03:34:05.988 [DEBUG] clck_gen.py:113 IND CLOCK 5814
2026-01-29 03:34:06.464 [DEBUG] clck_gen.py:113 IND CLOCK 5916
2026-01-29 03:34:06.933 [DEBUG] clck_gen.py:113 IND CLOCK 6018
2026-01-29 03:34:07.402 [DEBUG] clck_gen.py:113 IND CLOCK 6120
2026-01-29 03:34:07.873 [DEBUG] clck_gen.py:113 IND CLOCK 6222
2026-01-29 03:34:08.350 [DEBUG] clck_gen.py:113 IND CLOCK 6324
2026-01-29 03:34:08.824 [DEBUG] clck_gen.py:113 IND CLOCK 6426
2026-01-29 03:34:09.293 [DEBUG] clck_gen.py:113 IND CLOCK 6528
2026-01-29 03:34:09.762 [DEBUG] clck_gen.py:113 IND CLOCK 6630
2026-01-29 03:34:10.230 [DEBUG] clck_gen.py:113 IND CLOCK 6732
2026-01-29 03:34:10.700 [DEBUG] clck_gen.py:113 IND CLOCK 6834
2026-01-29 03:34:11.171 [DEBUG] clck_gen.py:113 IND CLOCK 6936
2026-01-29 03:34:11.641 [DEBUG] clck_gen.py:113 IND CLOCK 7038
2026-01-29 03:34:12.112 [DEBUG] clck_gen.py:113 IND CLOCK 7140
2026-01-29 03:34:12.583 [DEBUG] clck_gen.py:113 IND CLOCK 7242
2026-01-29 03:34:13.054 [DEBUG] clck_gen.py:113 IND CLOCK 7344
2026-01-29 03:34:13.531 [DEBUG] clck_gen.py:113 IND CLOCK 7446
2026-01-29 03:34:14.005 [DEBUG] clck_gen.py:113 IND CLOCK 7548
2026-01-29 03:34:14.474 [DEBUG] clck_gen.py:113 IND CLOCK 7650
2026-01-29 03:34:14.944 [DEBUG] clck_gen.py:113 IND CLOCK 7752
2026-01-29 03:34:15.418 [DEBUG] clck_gen.py:113 IND CLOCK 7854
2026-01-29 03:34:15.890 [DEBUG] clck_gen.py:113 IND CLOCK 7956
2026-01-29 03:34:16.364 [DEBUG] clck_gen.py:113 IND CLOCK 8058
2026-01-29 03:34:16.842 [DEBUG] clck_gen.py:113 IND CLOCK 8160
2026-01-29 03:34:17.319 [DEBUG] clck_gen.py:113 IND CLOCK 8262
2026-01-29 03:34:17.797 [DEBUG] clck_gen.py:113 IND CLOCK 8364
2026-01-29 03:34:18.274 [DEBUG] clck_gen.py:113 IND CLOCK 8466
2026-01-29 03:34:18.752 [DEBUG] clck_gen.py:113 IND CLOCK 8568
2026-01-29 03:34:19.229 [DEBUG] clck_gen.py:113 IND CLOCK 8670
2026-01-29 03:34:19.566 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 03:34:19.566 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:34:19.575 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 03:34:19.576 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 03:34:19.576 [INFO] transceiver.py:205 (MS@172.18.28.22:6700) Frequency hopping disabled
2026-01-29 03:34:19.591 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 03:34:19.591 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 03:34:19.591 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 03:34:19.597 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 03:34:19.597 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 03:34:19.597 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 03:34:19.597 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:34:19.599 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 03:34:19.599 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 03:34:19.599 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 03:34:19.599 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.28.22:6700) Recv POWERON CMD
2026-01-29 03:34:19.599 [INFO] ctrl_if_trx.py:109 (MS@172.18.28.22:6700) Starting transceiver...
2026-01-29 03:34:19.648 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 03:34:19.648 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 03:34:19.648 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 03:34:19.648 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 03:34:19.704 [DEBUG] clck_gen.py:113 IND CLOCK 8772
2026-01-29 03:34:20.174 [DEBUG] clck_gen.py:113 IND CLOCK 8874
2026-01-29 03:34:20.651 [DEBUG] clck_gen.py:113 IND CLOCK 8976
2026-01-29 03:34:21.128 [DEBUG] clck_gen.py:113 IND CLOCK 9078
2026-01-29 03:34:21.604 [DEBUG] clck_gen.py:113 IND CLOCK 9180
2026-01-29 03:34:22.082 [DEBUG] clck_gen.py:113 IND CLOCK 9282
2026-01-29 03:34:22.560 [DEBUG] clck_gen.py:113 IND CLOCK 9384
2026-01-29 03:34:23.037 [DEBUG] clck_gen.py:113 IND CLOCK 9486
2026-01-29 03:34:23.514 [DEBUG] clck_gen.py:113 IND CLOCK 9588
2026-01-29 03:34:23.992 [DEBUG] clck_gen.py:113 IND CLOCK 9690
2026-01-29 03:34:24.470 [DEBUG] clck_gen.py:113 IND CLOCK 9792
2026-01-29 03:34:24.947 [DEBUG] clck_gen.py:113 IND CLOCK 9894
2026-01-29 03:34:25.425 [DEBUG] clck_gen.py:113 IND CLOCK 9996
2026-01-29 03:34:25.897 [DEBUG] clck_gen.py:113 IND CLOCK 10098
2026-01-29 03:34:26.374 [DEBUG] clck_gen.py:113 IND CLOCK 10200
2026-01-29 03:34:26.852 [DEBUG] clck_gen.py:113 IND CLOCK 10302
2026-01-29 03:34:27.329 [DEBUG] clck_gen.py:113 IND CLOCK 10404
2026-01-29 03:34:27.806 [DEBUG] clck_gen.py:113 IND CLOCK 10506
2026-01-29 03:34:28.283 [DEBUG] clck_gen.py:113 IND CLOCK 10608
2026-01-29 03:34:28.760 [DEBUG] clck_gen.py:113 IND CLOCK 10710
2026-01-29 03:34:29.238 [DEBUG] clck_gen.py:113 IND CLOCK 10812
2026-01-29 03:34:29.716 [DEBUG] clck_gen.py:113 IND CLOCK 10914
2026-01-29 03:34:30.193 [DEBUG] clck_gen.py:113 IND CLOCK 11016
2026-01-29 03:34:30.667 [DEBUG] clck_gen.py:113 IND CLOCK 11118
2026-01-29 03:34:31.144 [DEBUG] clck_gen.py:113 IND CLOCK 11220
2026-01-29 03:34:31.621 [DEBUG] clck_gen.py:113 IND CLOCK 11322
2026-01-29 03:34:32.099 [DEBUG] clck_gen.py:113 IND CLOCK 11424
2026-01-29 03:34:32.576 [DEBUG] clck_gen.py:113 IND CLOCK 11526
2026-01-29 03:34:33.053 [DEBUG] clck_gen.py:113 IND CLOCK 11628
2026-01-29 03:34:33.530 [DEBUG] clck_gen.py:113 IND CLOCK 11730
2026-01-29 03:34:34.007 [DEBUG] clck_gen.py:113 IND CLOCK 11832
2026-01-29 03:34:34.484 [DEBUG] clck_gen.py:113 IND CLOCK 11934
2026-01-29 03:34:34.962 [DEBUG] clck_gen.py:113 IND CLOCK 12036
2026-01-29 03:34:35.439 [DEBUG] clck_gen.py:113 IND CLOCK 12138
2026-01-29 03:34:35.916 [DEBUG] clck_gen.py:113 IND CLOCK 12240
2026-01-29 03:34:36.393 [DEBUG] clck_gen.py:113 IND CLOCK 12342
2026-01-29 03:34:36.870 [DEBUG] clck_gen.py:113 IND CLOCK 12444
2026-01-29 03:34:37.347 [DEBUG] clck_gen.py:113 IND CLOCK 12546
2026-01-29 03:34:37.822 [DEBUG] clck_gen.py:113 IND CLOCK 12648
2026-01-29 03:34:38.294 [DEBUG] clck_gen.py:113 IND CLOCK 12750
2026-01-29 03:34:38.771 [DEBUG] clck_gen.py:113 IND CLOCK 12852
2026-01-29 03:34:39.248 [DEBUG] clck_gen.py:113 IND CLOCK 12954
2026-01-29 03:34:39.652 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 03:34:39.653 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:34:39.658 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 03:34:39.658 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 03:34:39.671 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 03:34:39.671 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 03:34:39.671 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 03:34:39.677 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 03:34:39.677 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 03:34:39.677 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 03:34:39.677 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:34:39.678 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 03:34:39.679 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 03:34:39.679 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 03:34:39.679 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.28.22:6700) Recv POWERON CMD
2026-01-29 03:34:39.679 [INFO] ctrl_if_trx.py:109 (MS@172.18.28.22:6700) Starting transceiver...
2026-01-29 03:34:39.719 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.28.22:6700) Recv SETFH cmd
2026-01-29 03:34:39.719 [INFO] transceiver.py:201 (MS@172.18.28.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2026-01-29 03:34:39.720 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 03:34:39.720 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 03:34:39.723 [DEBUG] clck_gen.py:113 IND CLOCK 13056
2026-01-29 03:34:40.192 [DEBUG] clck_gen.py:113 IND CLOCK 13158
2026-01-29 03:34:40.663 [DEBUG] clck_gen.py:113 IND CLOCK 13260
2026-01-29 03:34:41.141 [DEBUG] clck_gen.py:113 IND CLOCK 13362
2026-01-29 03:34:41.618 [DEBUG] clck_gen.py:113 IND CLOCK 13464
2026-01-29 03:34:42.090 [DEBUG] clck_gen.py:113 IND CLOCK 13566
2026-01-29 03:34:42.568 [DEBUG] clck_gen.py:113 IND CLOCK 13668
2026-01-29 03:34:43.045 [DEBUG] clck_gen.py:113 IND CLOCK 13770
2026-01-29 03:34:43.522 [DEBUG] clck_gen.py:113 IND CLOCK 13872
2026-01-29 03:34:43.999 [DEBUG] clck_gen.py:113 IND CLOCK 13974
2026-01-29 03:34:44.470 [DEBUG] clck_gen.py:113 IND CLOCK 14076
2026-01-29 03:34:44.948 [DEBUG] clck_gen.py:113 IND CLOCK 14178
2026-01-29 03:34:45.426 [DEBUG] clck_gen.py:113 IND CLOCK 14280
2026-01-29 03:34:45.903 [DEBUG] clck_gen.py:113 IND CLOCK 14382
2026-01-29 03:34:46.380 [DEBUG] clck_gen.py:113 IND CLOCK 14484
2026-01-29 03:34:46.858 [DEBUG] clck_gen.py:113 IND CLOCK 14586
2026-01-29 03:34:47.336 [DEBUG] clck_gen.py:113 IND CLOCK 14688
2026-01-29 03:34:47.813 [DEBUG] clck_gen.py:113 IND CLOCK 14790
2026-01-29 03:34:48.291 [DEBUG] clck_gen.py:113 IND CLOCK 14892
2026-01-29 03:34:48.768 [DEBUG] clck_gen.py:113 IND CLOCK 14994
2026-01-29 03:34:49.246 [DEBUG] clck_gen.py:113 IND CLOCK 15096
2026-01-29 03:34:49.724 [DEBUG] clck_gen.py:113 IND CLOCK 15198
2026-01-29 03:34:50.201 [DEBUG] clck_gen.py:113 IND CLOCK 15300
2026-01-29 03:34:50.678 [DEBUG] clck_gen.py:113 IND CLOCK 15402
2026-01-29 03:34:51.156 [DEBUG] clck_gen.py:113 IND CLOCK 15504
2026-01-29 03:34:51.634 [DEBUG] clck_gen.py:113 IND CLOCK 15606
2026-01-29 03:34:52.106 [DEBUG] clck_gen.py:113 IND CLOCK 15708
2026-01-29 03:34:52.577 [DEBUG] clck_gen.py:113 IND CLOCK 15810
2026-01-29 03:34:53.055 [DEBUG] clck_gen.py:113 IND CLOCK 15912
2026-01-29 03:34:53.532 [DEBUG] clck_gen.py:113 IND CLOCK 16014
2026-01-29 03:34:54.010 [DEBUG] clck_gen.py:113 IND CLOCK 16116
2026-01-29 03:34:54.479 [DEBUG] clck_gen.py:113 IND CLOCK 16218
2026-01-29 03:34:54.952 [DEBUG] clck_gen.py:113 IND CLOCK 16320
2026-01-29 03:34:55.430 [DEBUG] clck_gen.py:113 IND CLOCK 16422
2026-01-29 03:34:55.909 [DEBUG] clck_gen.py:113 IND CLOCK 16524
2026-01-29 03:34:56.387 [DEBUG] clck_gen.py:113 IND CLOCK 16626
2026-01-29 03:34:56.866 [DEBUG] clck_gen.py:113 IND CLOCK 16728
2026-01-29 03:34:57.343 [DEBUG] clck_gen.py:113 IND CLOCK 16830
2026-01-29 03:34:57.820 [DEBUG] clck_gen.py:113 IND CLOCK 16932
2026-01-29 03:34:58.292 [DEBUG] clck_gen.py:113 IND CLOCK 17034
2026-01-29 03:34:58.759 [DEBUG] clck_gen.py:113 IND CLOCK 17136
2026-01-29 03:34:59.229 [DEBUG] clck_gen.py:113 IND CLOCK 17238
2026-01-29 03:34:59.707 [DEBUG] clck_gen.py:113 IND CLOCK 17340
2026-01-29 03:34:59.723 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 03:34:59.724 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:34:59.734 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 03:34:59.735 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 03:34:59.735 [INFO] transceiver.py:205 (MS@172.18.28.22:6700) Frequency hopping disabled
2026-01-29 03:34:59.752 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 03:34:59.752 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:34:59.753 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:34:59.753 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:34:59.756 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 03:34:59.757 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 03:34:59.757 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 03:34:59.757 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 03:34:59.757 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.28.20:5700) Recv POWEROFF cmd
2026-01-29 03:34:59.757 [INFO] ctrl_if_trx.py:117 (BTS@172.18.28.20:5700) Stopping transceiver...
2026-01-29 03:34:59.757 [INFO] transceiver.py:246 Stopping clock generator
2026-01-29 03:34:59.758 [WARNING] transceiver.py:257 (TRX1@172.18.28.20:5700/1) RX TRXD message (ver=1 fn=17351 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:34:59.758 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=17351 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:34:59.758 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=17351 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:34:59.758 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=17351 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:34:59.758 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=17351 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:34:59.758 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=17351 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:34:59.758 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=17351 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:34:59.758 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=17351 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:34:59.758 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=17352 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:34:59.759 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=17352 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:34:59.759 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=17352 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:34:59.759 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=17352 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:34:59.759 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=17352 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:34:59.759 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=17352 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:34:59.759 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=17352 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:34:59.759 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=17352 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:34:59.759 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=17353 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:35:04.756 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.28.20:5700) Recv POWEROFF cmd
2026-01-29 03:35:04.756 [INFO] ctrl_if_trx.py:117 (BTS@172.18.28.20:5700) Stopping transceiver...
2026-01-29 03:35:04.758 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 03:35:04.759 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 03:35:04.760 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 03:35:04.760 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 03:35:04.768 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 03:35:04.769 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.28.20:5700) Recv SETFORMAT cmd
2026-01-29 03:35:04.769 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.28.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:35:04.770 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.28.20:5700) Recv SETFORMAT cmd
2026-01-29 03:35:04.770 [INFO] ctrl_if_trx.py:201 (BTS@172.18.28.20:5700) TRXD header version 1 -> 1
2026-01-29 03:35:04.772 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.28.20:5700/1) Recv RXTUNE cmd
2026-01-29 03:35:04.772 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.28.20:5700/1) Recv TXTUNE cmd
2026-01-29 03:35:04.773 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.28.20:5700/1) Recv SETFORMAT cmd
2026-01-29 03:35:04.773 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.28.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:35:04.773 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 03:35:04.773 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.28.20:5700/1) Recv NOMTXPOWER cmd
2026-01-29 03:35:04.773 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.28.20:5700/1) Recv SETFORMAT cmd
2026-01-29 03:35:04.773 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.28.20:5700/1) TRXD header version 1 -> 1
2026-01-29 03:35:04.775 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.28.20:5700/2) Recv RXTUNE cmd
2026-01-29 03:35:04.775 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.28.20:5700/2) Recv TXTUNE cmd
2026-01-29 03:35:04.775 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.28.20:5700/2) Recv SETFORMAT cmd
2026-01-29 03:35:04.775 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.28.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:35:04.775 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 03:35:04.775 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.28.20:5700/2) Recv NOMTXPOWER cmd
2026-01-29 03:35:04.775 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.28.20:5700/2) Recv SETFORMAT cmd
2026-01-29 03:35:04.775 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.28.20:5700/2) TRXD header version 1 -> 1
2026-01-29 03:35:04.777 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.28.20:5700/3) Recv RXTUNE cmd
2026-01-29 03:35:04.777 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.28.20:5700/3) Recv TXTUNE cmd
2026-01-29 03:35:04.777 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.28.20:5700/3) Recv SETFORMAT cmd
2026-01-29 03:35:04.777 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.28.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:35:04.777 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 03:35:04.777 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.28.20:5700/3) Recv NOMTXPOWER cmd
2026-01-29 03:35:04.777 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.28.20:5700/3) Recv SETFORMAT cmd
2026-01-29 03:35:04.777 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.28.20:5700/3) TRXD header version 1 -> 1
2026-01-29 03:35:04.780 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.28.20:5700) Recv RXTUNE cmd
2026-01-29 03:35:04.780 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETTSC
2026-01-29 03:35:04.780 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETTSC
2026-01-29 03:35:04.780 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETTSC
2026-01-29 03:35:04.780 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.28.20:5700) Recv TXTUNE cmd
2026-01-29 03:35:04.780 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETRXGAIN
2026-01-29 03:35:04.780 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETRXGAIN
2026-01-29 03:35:04.781 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETRXGAIN
2026-01-29 03:35:04.781 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETTSC
2026-01-29 03:35:04.781 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:35:04.781 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:35:04.781 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:35:04.781 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.28.20:5700) Recv NOMTXPOWER cmd
2026-01-29 03:35:04.781 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:35:04.781 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:35:04.781 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:35:04.781 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.28.20:5700) Recv POWERON CMD
2026-01-29 03:35:04.781 [INFO] ctrl_if_trx.py:109 (BTS@172.18.28.20:5700) Starting transceiver...
2026-01-29 03:35:04.781 [INFO] transceiver.py:243 Starting clock generator
2026-01-29 03:35:04.781 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-01-29 03:35:04.781 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:35:04.781 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:35:04.781 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:35:04.781 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETRXGAIN
2026-01-29 03:35:04.781 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:35:04.781 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:35:04.781 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:35:04.781 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:35:04.782 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:35:04.782 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:35:04.782 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:35:04.782 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:35:04.782 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:35:04.782 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:35:04.782 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:35:04.782 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:35:04.782 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:35:04.782 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:35:04.782 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:35:04.782 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:35:04.782 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:35:04.782 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:35:04.782 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 03:35:04.782 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:35:04.783 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:35:04.783 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:35:04.783 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:35:04.783 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:35:04.783 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 03:35:04.783 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 03:35:04.783 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.28.20:5700) Recv POWEROFF cmd
2026-01-29 03:35:04.783 [INFO] ctrl_if_trx.py:117 (BTS@172.18.28.20:5700) Stopping transceiver...
2026-01-29 03:35:04.783 [INFO] transceiver.py:246 Stopping clock generator
2026-01-29 03:35:04.783 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 03:35:09.785 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.28.20:5700) Recv POWEROFF cmd
2026-01-29 03:35:09.786 [INFO] ctrl_if_trx.py:117 (BTS@172.18.28.20:5700) Stopping transceiver...
2026-01-29 03:35:09.790 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 03:35:09.790 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 03:35:09.790 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 03:35:09.790 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 03:35:09.800 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 03:35:09.801 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.28.20:5700) Recv SETFORMAT cmd
2026-01-29 03:35:09.801 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.28.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:35:09.801 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.28.20:5700) Recv SETFORMAT cmd
2026-01-29 03:35:09.801 [INFO] ctrl_if_trx.py:201 (BTS@172.18.28.20:5700) TRXD header version 1 -> 1
2026-01-29 03:35:09.804 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.28.20:5700/1) Recv RXTUNE cmd
2026-01-29 03:35:09.805 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.28.20:5700/1) Recv TXTUNE cmd
2026-01-29 03:35:09.805 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.28.20:5700/1) Recv SETFORMAT cmd
2026-01-29 03:35:09.805 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.28.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:35:09.805 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 03:35:09.805 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.28.20:5700/1) Recv NOMTXPOWER cmd
2026-01-29 03:35:09.805 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.28.20:5700/1) Recv SETFORMAT cmd
2026-01-29 03:35:09.805 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.28.20:5700/1) TRXD header version 1 -> 1
2026-01-29 03:35:09.808 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.28.20:5700/2) Recv RXTUNE cmd
2026-01-29 03:35:09.808 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.28.20:5700/2) Recv TXTUNE cmd
2026-01-29 03:35:09.808 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.28.20:5700/2) Recv SETFORMAT cmd
2026-01-29 03:35:09.808 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.28.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:35:09.808 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 03:35:09.809 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.28.20:5700/2) Recv NOMTXPOWER cmd
2026-01-29 03:35:09.809 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.28.20:5700/2) Recv SETFORMAT cmd
2026-01-29 03:35:09.809 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.28.20:5700/2) TRXD header version 1 -> 1
2026-01-29 03:35:09.811 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.28.20:5700/3) Recv RXTUNE cmd
2026-01-29 03:35:09.811 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.28.20:5700/3) Recv TXTUNE cmd
2026-01-29 03:35:09.811 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.28.20:5700/3) Recv SETFORMAT cmd
2026-01-29 03:35:09.811 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.28.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:35:09.811 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 03:35:09.811 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.28.20:5700/3) Recv NOMTXPOWER cmd
2026-01-29 03:35:09.811 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.28.20:5700/3) Recv SETFORMAT cmd
2026-01-29 03:35:09.811 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.28.20:5700/3) TRXD header version 1 -> 1
2026-01-29 03:35:09.814 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.28.20:5700) Recv RXTUNE cmd
2026-01-29 03:35:09.814 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETTSC
2026-01-29 03:35:09.814 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETTSC
2026-01-29 03:35:09.814 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETTSC
2026-01-29 03:35:09.814 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.28.20:5700) Recv TXTUNE cmd
2026-01-29 03:35:09.815 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETRXGAIN
2026-01-29 03:35:09.815 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETRXGAIN
2026-01-29 03:35:09.815 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETRXGAIN
2026-01-29 03:35:09.815 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETTSC
2026-01-29 03:35:09.815 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:35:09.815 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:35:09.815 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.28.20:5700) Recv NOMTXPOWER cmd
2026-01-29 03:35:09.815 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:35:09.815 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:35:09.815 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:35:09.815 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.28.20:5700) Recv POWERON CMD
2026-01-29 03:35:09.815 [INFO] ctrl_if_trx.py:109 (BTS@172.18.28.20:5700) Starting transceiver...
2026-01-29 03:35:09.815 [INFO] transceiver.py:243 Starting clock generator
2026-01-29 03:35:09.815 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-01-29 03:35:09.815 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:35:09.815 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:35:09.815 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:35:09.815 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETRXGAIN
2026-01-29 03:35:09.815 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:35:09.815 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:35:09.815 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:35:09.815 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:35:09.816 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:35:09.816 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:35:09.816 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:35:09.816 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:35:09.816 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:35:09.816 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:35:09.816 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:35:09.816 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:35:09.816 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:35:09.816 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:35:09.816 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:35:09.816 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:35:09.816 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:35:09.816 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:35:09.816 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:35:09.816 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:35:09.816 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:35:09.816 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:35:09.816 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:35:09.816 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:35:09.820 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-01-29 03:35:10.292 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-01-29 03:35:10.342 [DEBUG] fake_trx.py:278 (BTS@172.18.28.20:5700) Recv FAKE_TOA cmd
2026-01-29 03:35:10.344 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:35:10.345 [DEBUG] fake_trx.py:297 (BTS@172.18.28.20:5700) Recv FAKE_RSSI cmd
2026-01-29 03:35:10.346 [DEBUG] fake_trx.py:322 (BTS@172.18.28.20:5700) Recv FAKE_CI cmd
2026-01-29 03:35:10.365 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 03:35:10.366 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 03:35:10.366 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 03:35:10.382 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 03:35:10.382 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 03:35:10.383 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 03:35:10.384 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:35:10.388 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 03:35:10.388 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 03:35:10.388 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 03:35:10.388 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.28.22:6700) Recv POWERON CMD
2026-01-29 03:35:10.388 [INFO] ctrl_if_trx.py:109 (MS@172.18.28.22:6700) Starting transceiver...
2026-01-29 03:35:10.429 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 03:35:10.430 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 03:35:10.430 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 03:35:10.430 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 03:35:10.627 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 03:35:10.627 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:35:10.631 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 03:35:10.631 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 03:35:10.645 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:35:10.646 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 03:35:10.646 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 03:35:10.646 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 03:35:10.648 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 03:35:10.648 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 03:35:10.648 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 03:35:10.648 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.28.22:6700) Recv POWERON CMD
2026-01-29 03:35:10.648 [INFO] ctrl_if_trx.py:109 (MS@172.18.28.22:6700) Starting transceiver...
2026-01-29 03:35:10.663 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 03:35:10.663 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 03:35:10.663 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 03:35:10.663 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 03:35:10.767 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-01-29 03:35:10.818 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:35:10.819 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 03:35:10.819 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:35:10.822 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:35:10.867 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 03:35:10.867 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:35:10.870 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 03:35:10.870 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 03:35:10.883 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:35:10.884 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 03:35:10.884 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 03:35:10.885 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 03:35:10.886 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 03:35:10.886 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 03:35:10.887 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 03:35:10.887 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.28.22:6700) Recv POWERON CMD
2026-01-29 03:35:10.887 [INFO] ctrl_if_trx.py:109 (MS@172.18.28.22:6700) Starting transceiver...
2026-01-29 03:35:10.898 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 03:35:10.898 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 03:35:10.898 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 03:35:10.898 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 03:35:11.107 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 03:35:11.108 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:35:11.111 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 03:35:11.111 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 03:35:11.128 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 03:35:11.128 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 03:35:11.128 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 03:35:11.135 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 03:35:11.135 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 03:35:11.135 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 03:35:11.136 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:35:11.137 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 03:35:11.137 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 03:35:11.137 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 03:35:11.137 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.28.22:6700) Recv POWERON CMD
2026-01-29 03:35:11.137 [INFO] ctrl_if_trx.py:109 (MS@172.18.28.22:6700) Starting transceiver...
2026-01-29 03:35:11.182 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.28.22:6700) Recv SETFH cmd
2026-01-29 03:35:11.182 [INFO] transceiver.py:201 (MS@172.18.28.22:6700) Frequency hopping configured: hsn=5, maio=0, ma_len=4
2026-01-29 03:35:11.182 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 03:35:11.183 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 03:35:11.242 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-01-29 03:35:11.495 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 03:35:11.496 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:35:11.499 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 03:35:11.500 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 03:35:11.500 [INFO] transceiver.py:205 (MS@172.18.28.22:6700) Frequency hopping disabled
2026-01-29 03:35:11.514 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:35:11.515 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 03:35:11.515 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 03:35:11.515 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 03:35:11.516 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 03:35:11.517 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 03:35:11.517 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 03:35:11.517 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.28.22:6700) Recv POWERON CMD
2026-01-29 03:35:11.517 [INFO] ctrl_if_trx.py:109 (MS@172.18.28.22:6700) Starting transceiver...
2026-01-29 03:35:11.520 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.28.22:6700) Recv SETFH cmd
2026-01-29 03:35:11.520 [INFO] transceiver.py:201 (MS@172.18.28.22:6700) Frequency hopping configured: hsn=5, maio=0, ma_len=4
2026-01-29 03:35:11.520 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 03:35:11.520 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 03:35:11.715 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-01-29 03:35:11.817 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 03:35:11.818 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:35:11.819 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:35:11.820 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 03:35:11.820 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:35:11.821 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 03:35:11.822 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 03:35:11.822 [INFO] transceiver.py:205 (MS@172.18.28.22:6700) Frequency hopping disabled
2026-01-29 03:35:11.822 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:35:11.838 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:35:11.839 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 03:35:11.839 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 03:35:11.839 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 03:35:11.841 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 03:35:11.841 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 03:35:11.841 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 03:35:11.841 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.28.22:6700) Recv POWERON CMD
2026-01-29 03:35:11.841 [INFO] ctrl_if_trx.py:109 (MS@172.18.28.22:6700) Starting transceiver...
2026-01-29 03:35:11.847 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.28.22:6700) Recv SETFH cmd
2026-01-29 03:35:11.847 [INFO] transceiver.py:201 (MS@172.18.28.22:6700) Frequency hopping configured: hsn=5, maio=0, ma_len=4
2026-01-29 03:35:11.847 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 03:35:11.847 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 03:35:12.135 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 03:35:12.135 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:35:12.138 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 03:35:12.139 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 03:35:12.139 [INFO] transceiver.py:205 (MS@172.18.28.22:6700) Frequency hopping disabled
2026-01-29 03:35:12.153 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 03:35:12.153 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 03:35:12.153 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 03:35:12.160 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 03:35:12.160 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 03:35:12.160 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 03:35:12.161 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:35:12.162 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 03:35:12.162 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 03:35:12.162 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 03:35:12.162 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.28.22:6700) Recv POWERON CMD
2026-01-29 03:35:12.162 [INFO] ctrl_if_trx.py:109 (MS@172.18.28.22:6700) Starting transceiver...
2026-01-29 03:35:12.181 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 03:35:12.181 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 03:35:12.181 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 03:35:12.182 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 03:35:12.184 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-01-29 03:35:12.661 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-01-29 03:35:12.821 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 03:35:12.821 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:35:12.821 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:35:12.823 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:35:13.139 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-01-29 03:35:13.610 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-01-29 03:35:13.821 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:35:13.822 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 03:35:13.822 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:35:13.824 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:35:14.081 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-01-29 03:35:14.559 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-01-29 03:35:14.713 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 03:35:14.715 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:35:14.718 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 03:35:14.718 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 03:35:14.733 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:35:14.734 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 03:35:14.734 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 03:35:14.734 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 03:35:14.736 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 03:35:14.736 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 03:35:14.736 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 03:35:14.736 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.28.22:6700) Recv POWERON CMD
2026-01-29 03:35:14.736 [INFO] ctrl_if_trx.py:109 (MS@172.18.28.22:6700) Starting transceiver...
2026-01-29 03:35:14.740 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 03:35:14.740 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 03:35:14.740 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 03:35:14.740 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 03:35:14.822 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 03:35:14.822 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:35:14.823 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:35:14.825 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:35:15.035 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-01-29 03:35:15.512 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-01-29 03:35:15.989 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-01-29 03:35:16.466 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-01-29 03:35:16.941 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-01-29 03:35:17.328 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 03:35:17.329 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:35:17.332 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 03:35:17.333 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 03:35:17.347 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:35:17.348 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 03:35:17.348 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 03:35:17.348 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 03:35:17.349 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 03:35:17.349 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 03:35:17.349 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 03:35:17.349 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.28.22:6700) Recv POWERON CMD
2026-01-29 03:35:17.349 [INFO] ctrl_if_trx.py:109 (MS@172.18.28.22:6700) Starting transceiver...
2026-01-29 03:35:17.353 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 03:35:17.354 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 03:35:17.354 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 03:35:17.354 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 03:35:17.410 [DEBUG] clck_gen.py:113 IND CLOCK 1632
2026-01-29 03:35:17.886 [DEBUG] clck_gen.py:113 IND CLOCK 1734
2026-01-29 03:35:18.362 [DEBUG] clck_gen.py:113 IND CLOCK 1836
2026-01-29 03:35:18.840 [DEBUG] clck_gen.py:113 IND CLOCK 1938
2026-01-29 03:35:19.318 [DEBUG] clck_gen.py:113 IND CLOCK 2040
2026-01-29 03:35:19.795 [DEBUG] clck_gen.py:113 IND CLOCK 2142
2026-01-29 03:35:19.950 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 03:35:19.951 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:35:19.954 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 03:35:19.954 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 03:35:19.975 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 03:35:19.975 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 03:35:19.975 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 03:35:19.981 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 03:35:19.982 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 03:35:19.982 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 03:35:19.982 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:35:19.983 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 03:35:19.983 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 03:35:19.983 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 03:35:19.983 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.28.22:6700) Recv POWERON CMD
2026-01-29 03:35:19.983 [INFO] ctrl_if_trx.py:109 (MS@172.18.28.22:6700) Starting transceiver...
2026-01-29 03:35:20.030 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.28.22:6700) Recv SETFH cmd
2026-01-29 03:35:20.030 [INFO] transceiver.py:201 (MS@172.18.28.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2026-01-29 03:35:20.030 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 03:35:20.031 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 03:35:20.267 [DEBUG] clck_gen.py:113 IND CLOCK 2244
2026-01-29 03:35:20.744 [DEBUG] clck_gen.py:113 IND CLOCK 2346
2026-01-29 03:35:21.218 [DEBUG] clck_gen.py:113 IND CLOCK 2448
2026-01-29 03:35:21.696 [DEBUG] clck_gen.py:113 IND CLOCK 2550
2026-01-29 03:35:22.173 [DEBUG] clck_gen.py:113 IND CLOCK 2652
2026-01-29 03:35:22.645 [DEBUG] clck_gen.py:113 IND CLOCK 2754
2026-01-29 03:35:22.726 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 03:35:22.726 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:35:22.730 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 03:35:22.730 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 03:35:22.730 [INFO] transceiver.py:205 (MS@172.18.28.22:6700) Frequency hopping disabled
2026-01-29 03:35:22.746 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:35:22.747 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 03:35:22.747 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 03:35:22.747 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 03:35:22.749 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 03:35:22.749 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 03:35:22.749 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 03:35:22.749 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.28.22:6700) Recv POWERON CMD
2026-01-29 03:35:22.749 [INFO] ctrl_if_trx.py:109 (MS@172.18.28.22:6700) Starting transceiver...
2026-01-29 03:35:22.781 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.28.22:6700) Recv SETFH cmd
2026-01-29 03:35:22.781 [INFO] transceiver.py:201 (MS@172.18.28.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2026-01-29 03:35:22.781 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 03:35:22.781 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 03:35:23.120 [DEBUG] clck_gen.py:113 IND CLOCK 2856
2026-01-29 03:35:23.595 [DEBUG] clck_gen.py:113 IND CLOCK 2958
2026-01-29 03:35:24.063 [DEBUG] clck_gen.py:113 IND CLOCK 3060
2026-01-29 03:35:24.534 [DEBUG] clck_gen.py:113 IND CLOCK 3162
2026-01-29 03:35:25.011 [DEBUG] clck_gen.py:113 IND CLOCK 3264
2026-01-29 03:35:25.480 [DEBUG] clck_gen.py:113 IND CLOCK 3366
2026-01-29 03:35:25.558 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 03:35:25.559 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:35:25.562 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 03:35:25.562 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 03:35:25.562 [INFO] transceiver.py:205 (MS@172.18.28.22:6700) Frequency hopping disabled
2026-01-29 03:35:25.577 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:35:25.578 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 03:35:25.578 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 03:35:25.578 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 03:35:25.580 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 03:35:25.580 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 03:35:25.580 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 03:35:25.580 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.28.22:6700) Recv POWERON CMD
2026-01-29 03:35:25.580 [INFO] ctrl_if_trx.py:109 (MS@172.18.28.22:6700) Starting transceiver...
2026-01-29 03:35:25.615 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.28.22:6700) Recv SETFH cmd
2026-01-29 03:35:25.615 [INFO] transceiver.py:201 (MS@172.18.28.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2026-01-29 03:35:25.616 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 03:35:25.616 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 03:35:25.948 [DEBUG] clck_gen.py:113 IND CLOCK 3468
2026-01-29 03:35:26.421 [DEBUG] clck_gen.py:113 IND CLOCK 3570
2026-01-29 03:35:26.892 [DEBUG] clck_gen.py:113 IND CLOCK 3672
2026-01-29 03:35:27.369 [DEBUG] clck_gen.py:113 IND CLOCK 3774
2026-01-29 03:35:27.845 [DEBUG] clck_gen.py:113 IND CLOCK 3876
2026-01-29 03:35:28.317 [DEBUG] clck_gen.py:113 IND CLOCK 3978
2026-01-29 03:35:28.397 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 03:35:28.398 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:35:28.401 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 03:35:28.401 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 03:35:28.401 [INFO] transceiver.py:205 (MS@172.18.28.22:6700) Frequency hopping disabled
2026-01-29 03:35:28.411 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 03:35:28.411 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:35:28.412 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:35:28.412 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:35:28.415 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 03:35:28.415 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 03:35:28.415 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 03:35:28.415 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.28.20:5700) Recv POWEROFF cmd
2026-01-29 03:35:28.415 [INFO] ctrl_if_trx.py:117 (BTS@172.18.28.20:5700) Stopping transceiver...
2026-01-29 03:35:28.416 [INFO] transceiver.py:246 Stopping clock generator
2026-01-29 03:35:28.416 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 03:35:28.416 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=4000 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:35:28.416 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=4000 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:35:28.416 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=4000 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:35:28.416 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=4000 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:35:28.417 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=4000 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:35:28.417 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=4000 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:35:28.417 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=4000 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:35:28.417 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=4000 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:35:28.417 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=4001 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:35:28.417 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=4001 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:35:28.417 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=4001 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:35:28.417 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=4001 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:35:28.417 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=4001 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:35:28.417 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=4001 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:35:28.417 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=4001 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:35:28.418 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=4001 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:35:33.414 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.28.20:5700) Recv POWEROFF cmd
2026-01-29 03:35:33.414 [INFO] ctrl_if_trx.py:117 (BTS@172.18.28.20:5700) Stopping transceiver...
2026-01-29 03:35:33.417 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 03:35:33.417 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 03:35:33.417 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 03:35:33.417 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 03:35:33.426 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 03:35:33.427 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.28.20:5700) Recv SETFORMAT cmd
2026-01-29 03:35:33.427 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.28.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:35:33.427 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.28.20:5700) Recv SETFORMAT cmd
2026-01-29 03:35:33.428 [INFO] ctrl_if_trx.py:201 (BTS@172.18.28.20:5700) TRXD header version 1 -> 1
2026-01-29 03:35:33.430 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.28.20:5700/1) Recv RXTUNE cmd
2026-01-29 03:35:33.430 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.28.20:5700/1) Recv TXTUNE cmd
2026-01-29 03:35:33.431 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.28.20:5700/1) Recv SETFORMAT cmd
2026-01-29 03:35:33.431 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.28.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:35:33.431 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 03:35:33.432 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.28.20:5700/1) Recv NOMTXPOWER cmd
2026-01-29 03:35:33.432 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.28.20:5700/1) Recv SETFORMAT cmd
2026-01-29 03:35:33.432 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.28.20:5700/1) TRXD header version 1 -> 1
2026-01-29 03:35:33.434 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.28.20:5700/2) Recv RXTUNE cmd
2026-01-29 03:35:33.434 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.28.20:5700/2) Recv TXTUNE cmd
2026-01-29 03:35:33.434 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.28.20:5700/2) Recv SETFORMAT cmd
2026-01-29 03:35:33.434 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.28.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:35:33.434 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 03:35:33.434 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.28.20:5700/2) Recv NOMTXPOWER cmd
2026-01-29 03:35:33.434 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.28.20:5700/2) Recv SETFORMAT cmd
2026-01-29 03:35:33.434 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.28.20:5700/2) TRXD header version 1 -> 1
2026-01-29 03:35:33.437 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.28.20:5700/3) Recv RXTUNE cmd
2026-01-29 03:35:33.437 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.28.20:5700/3) Recv TXTUNE cmd
2026-01-29 03:35:33.437 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.28.20:5700/3) Recv SETFORMAT cmd
2026-01-29 03:35:33.437 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.28.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:35:33.438 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 03:35:33.438 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.28.20:5700/3) Recv NOMTXPOWER cmd
2026-01-29 03:35:33.438 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.28.20:5700/3) Recv SETFORMAT cmd
2026-01-29 03:35:33.438 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.28.20:5700/3) TRXD header version 1 -> 1
2026-01-29 03:35:33.442 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.28.20:5700) Recv RXTUNE cmd
2026-01-29 03:35:33.442 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETTSC
2026-01-29 03:35:33.442 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETTSC
2026-01-29 03:35:33.442 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETTSC
2026-01-29 03:35:33.442 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.28.20:5700) Recv TXTUNE cmd
2026-01-29 03:35:33.442 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETRXGAIN
2026-01-29 03:35:33.442 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETRXGAIN
2026-01-29 03:35:33.443 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETRXGAIN
2026-01-29 03:35:33.443 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETTSC
2026-01-29 03:35:33.443 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:35:33.443 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:35:33.443 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:35:33.443 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.28.20:5700) Recv NOMTXPOWER cmd
2026-01-29 03:35:33.443 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:35:33.443 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:35:33.443 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:35:33.443 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.28.20:5700) Recv POWERON CMD
2026-01-29 03:35:33.443 [INFO] ctrl_if_trx.py:109 (BTS@172.18.28.20:5700) Starting transceiver...
2026-01-29 03:35:33.443 [INFO] transceiver.py:243 Starting clock generator
2026-01-29 03:35:33.443 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-01-29 03:35:33.443 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:35:33.443 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:35:33.444 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:35:33.444 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETRXGAIN
2026-01-29 03:35:33.444 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:35:33.444 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:35:33.444 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:35:33.444 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:35:33.444 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:35:33.444 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:35:33.444 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:35:33.444 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:35:33.444 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:35:33.444 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:35:33.444 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:35:33.444 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:35:33.444 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:35:33.444 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:35:33.444 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:35:33.445 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:35:33.445 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:35:33.445 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:35:33.445 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:35:33.445 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:35:33.445 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:35:33.445 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:35:33.445 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:35:33.448 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-01-29 03:35:33.924 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-01-29 03:35:33.982 [DEBUG] fake_trx.py:278 (BTS@172.18.28.20:5700) Recv FAKE_TOA cmd
2026-01-29 03:35:33.984 [DEBUG] fake_trx.py:297 (BTS@172.18.28.20:5700) Recv FAKE_RSSI cmd
2026-01-29 03:35:33.986 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:35:33.986 [DEBUG] fake_trx.py:322 (BTS@172.18.28.20:5700) Recv FAKE_CI cmd
2026-01-29 03:35:34.005 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 03:35:34.006 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 03:35:34.006 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 03:35:34.025 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 03:35:34.025 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 03:35:34.025 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 03:35:34.027 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:35:34.032 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 03:35:34.032 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 03:35:34.032 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 03:35:34.032 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.28.22:6700) Recv POWERON CMD
2026-01-29 03:35:34.032 [INFO] ctrl_if_trx.py:109 (MS@172.18.28.22:6700) Starting transceiver...
2026-01-29 03:35:34.062 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 03:35:34.062 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 03:35:34.062 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 03:35:34.062 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 03:35:34.397 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-01-29 03:35:34.449 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 03:35:34.449 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:35:34.451 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:35:34.455 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:35:34.869 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-01-29 03:35:35.345 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-01-29 03:35:35.449 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 03:35:35.449 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:35:35.452 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:35:35.456 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:35:35.822 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-01-29 03:35:36.299 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-01-29 03:35:36.450 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:35:36.450 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 03:35:36.452 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:35:36.457 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:35:36.776 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-01-29 03:35:37.173 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 03:35:37.174 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:35:37.176 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 03:35:37.176 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 03:35:37.187 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 03:35:37.187 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 03:35:37.188 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 03:35:37.194 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 03:35:37.194 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 03:35:37.194 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 03:35:37.195 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:35:37.196 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 03:35:37.196 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 03:35:37.196 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 03:35:37.196 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.28.22:6700) Recv POWERON CMD
2026-01-29 03:35:37.196 [INFO] ctrl_if_trx.py:109 (MS@172.18.28.22:6700) Starting transceiver...
2026-01-29 03:35:37.246 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.28.22:6700) Recv SETFH cmd
2026-01-29 03:35:37.246 [INFO] transceiver.py:201 (MS@172.18.28.22:6700) Frequency hopping configured: hsn=5, maio=0, ma_len=4
2026-01-29 03:35:37.246 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 03:35:37.247 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 03:35:37.252 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-01-29 03:35:37.450 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:35:37.451 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 03:35:37.453 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:35:37.458 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:35:37.725 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-01-29 03:35:38.199 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-01-29 03:35:38.452 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 03:35:38.452 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:35:38.453 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:35:38.458 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:35:38.671 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-01-29 03:35:39.144 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-01-29 03:35:39.614 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-01-29 03:35:40.083 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-01-29 03:35:40.449 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 03:35:40.450 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:35:40.453 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 03:35:40.453 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 03:35:40.453 [INFO] transceiver.py:205 (MS@172.18.28.22:6700) Frequency hopping disabled
2026-01-29 03:35:40.470 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 03:35:40.470 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 03:35:40.470 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 03:35:40.476 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 03:35:40.476 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 03:35:40.476 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 03:35:40.476 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:35:40.478 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 03:35:40.478 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 03:35:40.478 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 03:35:40.478 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.28.22:6700) Recv POWERON CMD
2026-01-29 03:35:40.478 [INFO] ctrl_if_trx.py:109 (MS@172.18.28.22:6700) Starting transceiver...
2026-01-29 03:35:40.500 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 03:35:40.500 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 03:35:40.500 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 03:35:40.501 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 03:35:40.559 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-01-29 03:35:41.033 [DEBUG] clck_gen.py:113 IND CLOCK 1632
2026-01-29 03:35:41.510 [DEBUG] clck_gen.py:113 IND CLOCK 1734
2026-01-29 03:35:41.986 [DEBUG] clck_gen.py:113 IND CLOCK 1836
2026-01-29 03:35:42.463 [DEBUG] clck_gen.py:113 IND CLOCK 1938
2026-01-29 03:35:42.940 [DEBUG] clck_gen.py:113 IND CLOCK 2040
2026-01-29 03:35:43.412 [DEBUG] clck_gen.py:113 IND CLOCK 2142
2026-01-29 03:35:43.785 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 03:35:43.786 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:35:43.789 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 03:35:43.789 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 03:35:43.806 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 03:35:43.806 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 03:35:43.806 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 03:35:43.812 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 03:35:43.813 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 03:35:43.813 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 03:35:43.813 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:35:43.814 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 03:35:43.814 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 03:35:43.814 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 03:35:43.814 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.28.22:6700) Recv POWERON CMD
2026-01-29 03:35:43.814 [INFO] ctrl_if_trx.py:109 (MS@172.18.28.22:6700) Starting transceiver...
2026-01-29 03:35:43.828 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.28.22:6700) Recv SETFH cmd
2026-01-29 03:35:43.829 [INFO] transceiver.py:201 (MS@172.18.28.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2026-01-29 03:35:43.829 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 03:35:43.829 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 03:35:43.884 [DEBUG] clck_gen.py:113 IND CLOCK 2244
2026-01-29 03:35:44.354 [DEBUG] clck_gen.py:113 IND CLOCK 2346
2026-01-29 03:35:44.824 [DEBUG] clck_gen.py:113 IND CLOCK 2448
2026-01-29 03:35:45.294 [DEBUG] clck_gen.py:113 IND CLOCK 2550
2026-01-29 03:35:45.764 [DEBUG] clck_gen.py:113 IND CLOCK 2652
2026-01-29 03:35:46.233 [DEBUG] clck_gen.py:113 IND CLOCK 2754
2026-01-29 03:35:46.706 [DEBUG] clck_gen.py:113 IND CLOCK 2856
2026-01-29 03:35:47.034 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 03:35:47.035 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:35:47.037 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 03:35:47.038 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 03:35:47.038 [INFO] transceiver.py:205 (MS@172.18.28.22:6700) Frequency hopping disabled
2026-01-29 03:35:47.048 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 03:35:47.048 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:35:47.049 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:35:47.049 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:35:47.052 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 03:35:47.052 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 03:35:47.052 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 03:35:47.053 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.28.20:5700) Recv POWEROFF cmd
2026-01-29 03:35:47.053 [INFO] ctrl_if_trx.py:117 (BTS@172.18.28.20:5700) Stopping transceiver...
2026-01-29 03:35:47.053 [INFO] transceiver.py:246 Stopping clock generator
2026-01-29 03:35:47.053 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 03:35:47.053 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=2933 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:35:47.053 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=2933 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:35:47.054 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=2933 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:35:47.054 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=2933 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:35:47.054 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=2933 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:35:47.054 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=2933 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:35:47.054 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=2933 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:35:47.054 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=2934 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:35:47.054 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=2934 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:35:47.054 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=2934 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:35:47.054 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=2934 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:35:47.054 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=2934 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:35:47.054 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=2934 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:35:47.054 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=2934 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:35:47.055 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=2934 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:35:52.051 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.28.20:5700) Recv POWEROFF cmd
2026-01-29 03:35:52.052 [INFO] ctrl_if_trx.py:117 (BTS@172.18.28.20:5700) Stopping transceiver...
2026-01-29 03:35:52.052 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 03:35:52.052 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 03:35:52.053 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 03:35:52.053 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 03:35:52.061 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 03:35:52.062 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.28.20:5700) Recv SETFORMAT cmd
2026-01-29 03:35:52.062 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.28.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:35:52.063 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.28.20:5700) Recv SETFORMAT cmd
2026-01-29 03:35:52.063 [INFO] ctrl_if_trx.py:201 (BTS@172.18.28.20:5700) TRXD header version 1 -> 1
2026-01-29 03:35:52.065 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.28.20:5700/1) Recv RXTUNE cmd
2026-01-29 03:35:52.065 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.28.20:5700/1) Recv TXTUNE cmd
2026-01-29 03:35:52.065 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.28.20:5700/1) Recv SETFORMAT cmd
2026-01-29 03:35:52.065 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.28.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:35:52.066 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 03:35:52.066 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.28.20:5700/1) Recv NOMTXPOWER cmd
2026-01-29 03:35:52.066 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.28.20:5700/1) Recv SETFORMAT cmd
2026-01-29 03:35:52.066 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.28.20:5700/1) TRXD header version 1 -> 1
2026-01-29 03:35:52.067 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.28.20:5700/2) Recv RXTUNE cmd
2026-01-29 03:35:52.067 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.28.20:5700/2) Recv TXTUNE cmd
2026-01-29 03:35:52.068 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.28.20:5700/2) Recv SETFORMAT cmd
2026-01-29 03:35:52.068 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.28.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:35:52.068 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 03:35:52.068 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.28.20:5700/2) Recv NOMTXPOWER cmd
2026-01-29 03:35:52.068 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.28.20:5700/2) Recv SETFORMAT cmd
2026-01-29 03:35:52.068 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.28.20:5700/2) TRXD header version 1 -> 1
2026-01-29 03:35:52.070 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.28.20:5700/3) Recv RXTUNE cmd
2026-01-29 03:35:52.070 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.28.20:5700/3) Recv TXTUNE cmd
2026-01-29 03:35:52.070 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.28.20:5700/3) Recv SETFORMAT cmd
2026-01-29 03:35:52.070 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.28.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:35:52.070 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 03:35:52.071 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.28.20:5700/3) Recv NOMTXPOWER cmd
2026-01-29 03:35:52.071 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.28.20:5700/3) Recv SETFORMAT cmd
2026-01-29 03:35:52.071 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.28.20:5700/3) TRXD header version 1 -> 1
2026-01-29 03:35:52.074 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.28.20:5700) Recv RXTUNE cmd
2026-01-29 03:35:52.074 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETTSC
2026-01-29 03:35:52.074 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.28.20:5700) Recv TXTUNE cmd
2026-01-29 03:35:52.074 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETTSC
2026-01-29 03:35:52.074 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETTSC
2026-01-29 03:35:52.074 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETRXGAIN
2026-01-29 03:35:52.074 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETTSC
2026-01-29 03:35:52.074 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETRXGAIN
2026-01-29 03:35:52.074 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETRXGAIN
2026-01-29 03:35:52.074 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:35:52.074 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.28.20:5700) Recv NOMTXPOWER cmd
2026-01-29 03:35:52.074 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:35:52.074 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:35:52.075 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.28.20:5700) Recv POWERON CMD
2026-01-29 03:35:52.075 [INFO] ctrl_if_trx.py:109 (BTS@172.18.28.20:5700) Starting transceiver...
2026-01-29 03:35:52.075 [INFO] transceiver.py:243 Starting clock generator
2026-01-29 03:35:52.075 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-01-29 03:35:52.075 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:35:52.075 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:35:52.075 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:35:52.075 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETRXGAIN
2026-01-29 03:35:52.075 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:35:52.075 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:35:52.075 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:35:52.075 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:35:52.075 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:35:52.075 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:35:52.075 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:35:52.075 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:35:52.076 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:35:52.076 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:35:52.076 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:35:52.076 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:35:52.076 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:35:52.076 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:35:52.076 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:35:52.076 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:35:52.076 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:35:52.076 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:35:52.076 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:35:52.076 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:35:52.076 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:35:52.076 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:35:52.076 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:35:52.076 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:35:52.076 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:35:52.076 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:35:52.080 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-01-29 03:35:52.556 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-01-29 03:35:52.599 [DEBUG] fake_trx.py:278 (BTS@172.18.28.20:5700) Recv FAKE_TOA cmd
2026-01-29 03:35:52.600 [DEBUG] fake_trx.py:297 (BTS@172.18.28.20:5700) Recv FAKE_RSSI cmd
2026-01-29 03:35:52.601 [DEBUG] fake_trx.py:322 (BTS@172.18.28.20:5700) Recv FAKE_CI cmd
2026-01-29 03:35:52.602 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:35:52.622 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 03:35:52.622 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 03:35:52.622 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 03:35:52.639 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 03:35:52.640 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 03:35:52.640 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 03:35:52.641 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:35:52.644 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 03:35:52.644 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 03:35:52.645 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 03:35:52.645 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.28.22:6700) Recv POWERON CMD
2026-01-29 03:35:52.645 [INFO] ctrl_if_trx.py:109 (MS@172.18.28.22:6700) Starting transceiver...
2026-01-29 03:35:52.693 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 03:35:52.693 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 03:35:52.693 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 03:35:52.693 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 03:35:53.011 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 03:35:53.012 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:35:53.015 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 03:35:53.016 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 03:35:53.030 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-01-29 03:35:53.034 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 03:35:53.034 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 03:35:53.034 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 03:35:53.041 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 03:35:53.041 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 03:35:53.041 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 03:35:53.041 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:35:53.042 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 03:35:53.042 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 03:35:53.043 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 03:35:53.043 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.28.22:6700) Recv POWERON CMD
2026-01-29 03:35:53.043 [INFO] ctrl_if_trx.py:109 (MS@172.18.28.22:6700) Starting transceiver...
2026-01-29 03:35:53.072 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.28.22:6700) Recv SETFH cmd
2026-01-29 03:35:53.073 [INFO] transceiver.py:201 (MS@172.18.28.22:6700) Frequency hopping configured: hsn=5, maio=0, ma_len=4
2026-01-29 03:35:53.073 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 03:35:53.073 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 03:35:53.078 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 03:35:53.079 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:35:53.080 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:35:53.084 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:35:53.500 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-01-29 03:35:53.552 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:35:53.553 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 03:35:53.555 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 03:35:53.555 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 03:35:53.555 [INFO] transceiver.py:205 (MS@172.18.28.22:6700) Frequency hopping disabled
2026-01-29 03:35:53.572 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 03:35:53.572 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 03:35:53.572 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 03:35:53.578 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 03:35:53.578 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 03:35:53.578 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 03:35:53.579 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:35:53.580 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 03:35:53.580 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 03:35:53.580 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 03:35:53.580 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.28.22:6700) Recv POWERON CMD
2026-01-29 03:35:53.580 [INFO] ctrl_if_trx.py:109 (MS@172.18.28.22:6700) Starting transceiver...
2026-01-29 03:35:53.586 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 03:35:53.586 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 03:35:53.586 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 03:35:53.586 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 03:35:53.970 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-01-29 03:35:54.078 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 03:35:54.080 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:35:54.081 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:35:54.084 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:35:54.445 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-01-29 03:35:54.921 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-01-29 03:35:55.079 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 03:35:55.081 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:35:55.082 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:35:55.085 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:35:55.398 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-01-29 03:35:55.875 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-01-29 03:35:56.079 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 03:35:56.081 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:35:56.083 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:35:56.085 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:35:56.352 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-01-29 03:35:56.507 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 03:35:56.508 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:35:56.510 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 03:35:56.510 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 03:35:56.528 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 03:35:56.528 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 03:35:56.528 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 03:35:56.534 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 03:35:56.534 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 03:35:56.535 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 03:35:56.535 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:35:56.536 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 03:35:56.536 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 03:35:56.536 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 03:35:56.536 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.28.22:6700) Recv POWERON CMD
2026-01-29 03:35:56.536 [INFO] ctrl_if_trx.py:109 (MS@172.18.28.22:6700) Starting transceiver...
2026-01-29 03:35:56.587 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.28.22:6700) Recv SETFH cmd
2026-01-29 03:35:56.587 [INFO] transceiver.py:201 (MS@172.18.28.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2026-01-29 03:35:56.587 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 03:35:56.587 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 03:35:56.824 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-01-29 03:35:57.080 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 03:35:57.082 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:35:57.083 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:35:57.087 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:35:57.297 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-01-29 03:35:57.774 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-01-29 03:35:58.251 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-01-29 03:35:58.725 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-01-29 03:35:59.194 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-01-29 03:35:59.511 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 03:35:59.512 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:35:59.516 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 03:35:59.516 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 03:35:59.516 [INFO] transceiver.py:205 (MS@172.18.28.22:6700) Frequency hopping disabled
2026-01-29 03:35:59.525 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 03:35:59.526 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:35:59.526 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:35:59.526 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:35:59.529 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 03:35:59.529 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 03:35:59.530 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 03:35:59.530 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 03:35:59.530 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.28.20:5700) Recv POWEROFF cmd
2026-01-29 03:35:59.530 [INFO] ctrl_if_trx.py:117 (BTS@172.18.28.20:5700) Stopping transceiver...
2026-01-29 03:35:59.530 [INFO] transceiver.py:246 Stopping clock generator
2026-01-29 03:35:59.530 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=1604 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:35:59.531 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=1604 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:35:59.531 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=1604 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:35:59.531 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=1604 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:35:59.531 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=1604 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:35:59.531 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=1604 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:35:59.531 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=1605 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:35:59.531 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=1605 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:35:59.531 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=1605 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:35:59.531 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=1605 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:35:59.531 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=1605 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:35:59.531 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=1605 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:35:59.532 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=1605 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:35:59.532 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=1605 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:36:04.529 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.28.20:5700) Recv POWEROFF cmd
2026-01-29 03:36:04.529 [INFO] ctrl_if_trx.py:117 (BTS@172.18.28.20:5700) Stopping transceiver...
2026-01-29 03:36:04.530 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 03:36:04.532 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 03:36:04.532 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 03:36:04.532 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 03:36:04.541 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 03:36:04.542 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.28.20:5700) Recv SETFORMAT cmd
2026-01-29 03:36:04.542 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.28.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:36:04.542 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.28.20:5700) Recv SETFORMAT cmd
2026-01-29 03:36:04.542 [INFO] ctrl_if_trx.py:201 (BTS@172.18.28.20:5700) TRXD header version 1 -> 1
2026-01-29 03:36:04.544 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.28.20:5700/1) Recv RXTUNE cmd
2026-01-29 03:36:04.545 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.28.20:5700/1) Recv TXTUNE cmd
2026-01-29 03:36:04.545 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.28.20:5700/1) Recv SETFORMAT cmd
2026-01-29 03:36:04.545 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.28.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:36:04.545 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 03:36:04.545 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.28.20:5700/1) Recv NOMTXPOWER cmd
2026-01-29 03:36:04.545 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.28.20:5700/1) Recv SETFORMAT cmd
2026-01-29 03:36:04.545 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.28.20:5700/1) TRXD header version 1 -> 1
2026-01-29 03:36:04.547 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.28.20:5700/2) Recv RXTUNE cmd
2026-01-29 03:36:04.547 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.28.20:5700/2) Recv TXTUNE cmd
2026-01-29 03:36:04.547 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.28.20:5700/2) Recv SETFORMAT cmd
2026-01-29 03:36:04.547 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.28.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:36:04.548 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 03:36:04.548 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.28.20:5700/2) Recv NOMTXPOWER cmd
2026-01-29 03:36:04.548 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.28.20:5700/2) Recv SETFORMAT cmd
2026-01-29 03:36:04.548 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.28.20:5700/2) TRXD header version 1 -> 1
2026-01-29 03:36:04.550 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.28.20:5700/3) Recv RXTUNE cmd
2026-01-29 03:36:04.550 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.28.20:5700/3) Recv TXTUNE cmd
2026-01-29 03:36:04.550 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.28.20:5700/3) Recv SETFORMAT cmd
2026-01-29 03:36:04.550 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.28.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:36:04.550 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 03:36:04.550 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.28.20:5700/3) Recv NOMTXPOWER cmd
2026-01-29 03:36:04.550 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.28.20:5700/3) Recv SETFORMAT cmd
2026-01-29 03:36:04.550 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.28.20:5700/3) TRXD header version 1 -> 1
2026-01-29 03:36:04.552 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.28.20:5700) Recv RXTUNE cmd
2026-01-29 03:36:04.552 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETTSC
2026-01-29 03:36:04.552 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETTSC
2026-01-29 03:36:04.553 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETTSC
2026-01-29 03:36:04.553 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.28.20:5700) Recv TXTUNE cmd
2026-01-29 03:36:04.553 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETRXGAIN
2026-01-29 03:36:04.553 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETRXGAIN
2026-01-29 03:36:04.553 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETRXGAIN
2026-01-29 03:36:04.553 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETTSC
2026-01-29 03:36:04.553 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:36:04.553 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:36:04.553 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:36:04.553 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.28.20:5700) Recv NOMTXPOWER cmd
2026-01-29 03:36:04.553 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:36:04.553 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:36:04.553 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:36:04.553 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.28.20:5700) Recv POWERON CMD
2026-01-29 03:36:04.553 [INFO] ctrl_if_trx.py:109 (BTS@172.18.28.20:5700) Starting transceiver...
2026-01-29 03:36:04.553 [INFO] transceiver.py:243 Starting clock generator
2026-01-29 03:36:04.553 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-01-29 03:36:04.553 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:36:04.553 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:36:04.553 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:36:04.553 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETRXGAIN
2026-01-29 03:36:04.553 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:36:04.553 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:36:04.553 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:36:04.553 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:36:04.553 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:36:04.553 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:36:04.553 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:36:04.554 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:36:04.554 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:36:04.554 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:36:04.554 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:36:04.554 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:36:04.554 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:36:04.554 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:36:04.554 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:36:04.554 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:36:04.554 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:36:04.554 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:36:04.554 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:36:04.554 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:36:04.554 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:36:04.554 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:36:04.554 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:36:04.558 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-01-29 03:36:05.035 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-01-29 03:36:05.079 [DEBUG] fake_trx.py:278 (BTS@172.18.28.20:5700) Recv FAKE_TOA cmd
2026-01-29 03:36:05.080 [DEBUG] fake_trx.py:297 (BTS@172.18.28.20:5700) Recv FAKE_RSSI cmd
2026-01-29 03:36:05.082 [DEBUG] fake_trx.py:322 (BTS@172.18.28.20:5700) Recv FAKE_CI cmd
2026-01-29 03:36:05.082 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:36:05.101 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 03:36:05.101 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 03:36:05.102 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 03:36:05.122 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 03:36:05.122 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 03:36:05.122 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 03:36:05.124 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:36:05.128 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 03:36:05.129 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 03:36:05.129 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 03:36:05.129 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.28.22:6700) Recv POWERON CMD
2026-01-29 03:36:05.129 [INFO] ctrl_if_trx.py:109 (MS@172.18.28.22:6700) Starting transceiver...
2026-01-29 03:36:05.173 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 03:36:05.173 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 03:36:05.173 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 03:36:05.173 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 03:36:05.507 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-01-29 03:36:05.557 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:36:05.557 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 03:36:05.557 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:36:05.559 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:36:05.984 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-01-29 03:36:06.462 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-01-29 03:36:06.485 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 03:36:06.486 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:36:06.489 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 03:36:06.489 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 03:36:06.505 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 03:36:06.505 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 03:36:06.505 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 03:36:06.512 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 03:36:06.512 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 03:36:06.512 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 03:36:06.512 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:36:06.514 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 03:36:06.514 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 03:36:06.514 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 03:36:06.514 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.28.22:6700) Recv POWERON CMD
2026-01-29 03:36:06.514 [INFO] ctrl_if_trx.py:109 (MS@172.18.28.22:6700) Starting transceiver...
2026-01-29 03:36:06.554 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.28.22:6700) Recv SETFH cmd
2026-01-29 03:36:06.554 [INFO] transceiver.py:201 (MS@172.18.28.22:6700) Frequency hopping configured: hsn=5, maio=0, ma_len=4
2026-01-29 03:36:06.554 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 03:36:06.554 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 03:36:06.557 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 03:36:06.558 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:36:06.558 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:36:06.560 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:36:06.936 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-01-29 03:36:07.407 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-01-29 03:36:07.558 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:36:07.559 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 03:36:07.559 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:36:07.561 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:36:07.876 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-01-29 03:36:08.349 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-01-29 03:36:08.559 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 03:36:08.559 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:36:08.559 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:36:08.561 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:36:08.668 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 03:36:08.668 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:36:08.672 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 03:36:08.672 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 03:36:08.672 [INFO] transceiver.py:205 (MS@172.18.28.22:6700) Frequency hopping disabled
2026-01-29 03:36:08.689 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 03:36:08.689 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 03:36:08.689 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 03:36:08.695 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 03:36:08.695 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 03:36:08.695 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 03:36:08.696 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:36:08.697 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 03:36:08.697 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 03:36:08.697 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 03:36:08.697 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.28.22:6700) Recv POWERON CMD
2026-01-29 03:36:08.697 [INFO] ctrl_if_trx.py:109 (MS@172.18.28.22:6700) Starting transceiver...
2026-01-29 03:36:08.718 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 03:36:08.718 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 03:36:08.719 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 03:36:08.719 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 03:36:08.819 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-01-29 03:36:09.288 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-01-29 03:36:09.560 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 03:36:09.560 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:36:09.560 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:36:09.562 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:36:09.763 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-01-29 03:36:10.236 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-01-29 03:36:10.714 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-01-29 03:36:11.191 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-01-29 03:36:11.668 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-01-29 03:36:12.145 [DEBUG] clck_gen.py:113 IND CLOCK 1632
2026-01-29 03:36:12.619 [DEBUG] clck_gen.py:113 IND CLOCK 1734
2026-01-29 03:36:13.092 [DEBUG] clck_gen.py:113 IND CLOCK 1836
2026-01-29 03:36:13.553 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 03:36:13.554 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:36:13.557 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 03:36:13.557 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 03:36:13.567 [DEBUG] clck_gen.py:113 IND CLOCK 1938
2026-01-29 03:36:13.574 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 03:36:13.574 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 03:36:13.574 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 03:36:13.581 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 03:36:13.581 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 03:36:13.581 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 03:36:13.581 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:36:13.582 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 03:36:13.582 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 03:36:13.582 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 03:36:13.582 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.28.22:6700) Recv POWERON CMD
2026-01-29 03:36:13.582 [INFO] ctrl_if_trx.py:109 (MS@172.18.28.22:6700) Starting transceiver...
2026-01-29 03:36:13.607 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.28.22:6700) Recv SETFH cmd
2026-01-29 03:36:13.607 [INFO] transceiver.py:201 (MS@172.18.28.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2026-01-29 03:36:13.608 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 03:36:13.608 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 03:36:14.035 [DEBUG] clck_gen.py:113 IND CLOCK 2040
2026-01-29 03:36:14.505 [DEBUG] clck_gen.py:113 IND CLOCK 2142
2026-01-29 03:36:14.978 [DEBUG] clck_gen.py:113 IND CLOCK 2244
2026-01-29 03:36:15.456 [DEBUG] clck_gen.py:113 IND CLOCK 2346
2026-01-29 03:36:15.934 [DEBUG] clck_gen.py:113 IND CLOCK 2448
2026-01-29 03:36:16.407 [DEBUG] clck_gen.py:113 IND CLOCK 2550
2026-01-29 03:36:16.876 [DEBUG] clck_gen.py:113 IND CLOCK 2652
2026-01-29 03:36:17.352 [DEBUG] clck_gen.py:113 IND CLOCK 2754
2026-01-29 03:36:17.821 [DEBUG] clck_gen.py:113 IND CLOCK 2856
2026-01-29 03:36:18.290 [DEBUG] clck_gen.py:113 IND CLOCK 2958
2026-01-29 03:36:18.767 [DEBUG] clck_gen.py:113 IND CLOCK 3060
2026-01-29 03:36:19.244 [DEBUG] clck_gen.py:113 IND CLOCK 3162
2026-01-29 03:36:19.722 [DEBUG] clck_gen.py:113 IND CLOCK 3264
2026-01-29 03:36:20.199 [DEBUG] clck_gen.py:113 IND CLOCK 3366
2026-01-29 03:36:20.676 [DEBUG] clck_gen.py:113 IND CLOCK 3468
2026-01-29 03:36:21.153 [DEBUG] clck_gen.py:113 IND CLOCK 3570
2026-01-29 03:36:21.630 [DEBUG] clck_gen.py:113 IND CLOCK 3672
2026-01-29 03:36:22.108 [DEBUG] clck_gen.py:113 IND CLOCK 3774
2026-01-29 03:36:22.586 [DEBUG] clck_gen.py:113 IND CLOCK 3876
2026-01-29 03:36:23.059 [DEBUG] clck_gen.py:113 IND CLOCK 3978
2026-01-29 03:36:23.534 [DEBUG] clck_gen.py:113 IND CLOCK 4080
2026-01-29 03:36:24.011 [DEBUG] clck_gen.py:113 IND CLOCK 4182
2026-01-29 03:36:24.488 [DEBUG] clck_gen.py:113 IND CLOCK 4284
2026-01-29 03:36:24.966 [DEBUG] clck_gen.py:113 IND CLOCK 4386
2026-01-29 03:36:25.443 [DEBUG] clck_gen.py:113 IND CLOCK 4488
2026-01-29 03:36:25.915 [DEBUG] clck_gen.py:113 IND CLOCK 4590
2026-01-29 03:36:26.385 [DEBUG] clck_gen.py:113 IND CLOCK 4692
2026-01-29 03:36:26.863 [DEBUG] clck_gen.py:113 IND CLOCK 4794
2026-01-29 03:36:27.342 [DEBUG] clck_gen.py:113 IND CLOCK 4896
2026-01-29 03:36:27.819 [DEBUG] clck_gen.py:113 IND CLOCK 4998
2026-01-29 03:36:28.296 [DEBUG] clck_gen.py:113 IND CLOCK 5100
2026-01-29 03:36:28.774 [DEBUG] clck_gen.py:113 IND CLOCK 5202
2026-01-29 03:36:29.252 [DEBUG] clck_gen.py:113 IND CLOCK 5304
2026-01-29 03:36:29.729 [DEBUG] clck_gen.py:113 IND CLOCK 5406
2026-01-29 03:36:30.198 [DEBUG] clck_gen.py:113 IND CLOCK 5508
2026-01-29 03:36:30.667 [DEBUG] clck_gen.py:113 IND CLOCK 5610
2026-01-29 03:36:31.142 [DEBUG] clck_gen.py:113 IND CLOCK 5712
2026-01-29 03:36:31.616 [DEBUG] clck_gen.py:113 IND CLOCK 5814
2026-01-29 03:36:32.090 [DEBUG] clck_gen.py:113 IND CLOCK 5916
2026-01-29 03:36:32.566 [DEBUG] clck_gen.py:113 IND CLOCK 6018
2026-01-29 03:36:33.044 [DEBUG] clck_gen.py:113 IND CLOCK 6120
2026-01-29 03:36:33.518 [DEBUG] clck_gen.py:113 IND CLOCK 6222
2026-01-29 03:36:33.580 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 03:36:33.580 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 03:36:33.580 [INFO] transceiver.py:205 (MS@172.18.28.22:6700) Frequency hopping disabled
2026-01-29 03:36:33.581 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 03:36:33.581 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:36:33.581 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:36:33.581 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:36:33.581 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 03:36:33.582 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 03:36:33.582 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 03:36:33.582 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.28.20:5700) Recv POWEROFF cmd
2026-01-29 03:36:33.582 [INFO] ctrl_if_trx.py:117 (BTS@172.18.28.20:5700) Stopping transceiver...
2026-01-29 03:36:33.582 [INFO] transceiver.py:246 Stopping clock generator
2026-01-29 03:36:33.582 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 03:36:33.582 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=6238 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:36:33.582 [WARNING] transceiver.py:257 (TRX3@172.18.28.20:5700/3) RX TRXD message (ver=1 fn=6238 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:36:33.582 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=6238 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:36:33.582 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=6238 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:36:33.582 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=6238 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:36:33.582 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=6238 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:36:33.582 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=6238 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:36:33.582 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=6238 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:36:33.582 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=6238 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:36:38.582 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.28.20:5700) Recv POWEROFF cmd
2026-01-29 03:36:38.582 [INFO] ctrl_if_trx.py:117 (BTS@172.18.28.20:5700) Stopping transceiver...
2026-01-29 03:36:38.582 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 03:36:38.583 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 03:36:38.583 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 03:36:38.583 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 03:36:38.586 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 03:36:38.586 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.28.20:5700) Recv SETFORMAT cmd
2026-01-29 03:36:38.586 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.28.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:36:38.586 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.28.20:5700) Recv SETFORMAT cmd
2026-01-29 03:36:38.586 [INFO] ctrl_if_trx.py:201 (BTS@172.18.28.20:5700) TRXD header version 1 -> 1
2026-01-29 03:36:38.587 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.28.20:5700/1) Recv RXTUNE cmd
2026-01-29 03:36:38.587 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.28.20:5700/1) Recv TXTUNE cmd
2026-01-29 03:36:38.587 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.28.20:5700/1) Recv SETFORMAT cmd
2026-01-29 03:36:38.587 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.28.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:36:38.587 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 03:36:38.587 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.28.20:5700/1) Recv NOMTXPOWER cmd
2026-01-29 03:36:38.587 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.28.20:5700/1) Recv SETFORMAT cmd
2026-01-29 03:36:38.587 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.28.20:5700/1) TRXD header version 1 -> 1
2026-01-29 03:36:38.588 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.28.20:5700/2) Recv RXTUNE cmd
2026-01-29 03:36:38.588 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.28.20:5700/2) Recv TXTUNE cmd
2026-01-29 03:36:38.588 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.28.20:5700/2) Recv SETFORMAT cmd
2026-01-29 03:36:38.588 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.28.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:36:38.588 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 03:36:38.588 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.28.20:5700/2) Recv NOMTXPOWER cmd
2026-01-29 03:36:38.588 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.28.20:5700/2) Recv SETFORMAT cmd
2026-01-29 03:36:38.588 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.28.20:5700/2) TRXD header version 1 -> 1
2026-01-29 03:36:38.589 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.28.20:5700/3) Recv RXTUNE cmd
2026-01-29 03:36:38.589 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.28.20:5700/3) Recv TXTUNE cmd
2026-01-29 03:36:38.589 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.28.20:5700/3) Recv SETFORMAT cmd
2026-01-29 03:36:38.589 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.28.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:36:38.589 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 03:36:38.589 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.28.20:5700/3) Recv NOMTXPOWER cmd
2026-01-29 03:36:38.589 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.28.20:5700/3) Recv SETFORMAT cmd
2026-01-29 03:36:38.589 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.28.20:5700/3) TRXD header version 1 -> 1
2026-01-29 03:36:38.590 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.28.20:5700) Recv RXTUNE cmd
2026-01-29 03:36:38.590 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETTSC
2026-01-29 03:36:38.590 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETTSC
2026-01-29 03:36:38.590 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETTSC
2026-01-29 03:36:38.591 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.28.20:5700) Recv TXTUNE cmd
2026-01-29 03:36:38.591 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETRXGAIN
2026-01-29 03:36:38.591 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETRXGAIN
2026-01-29 03:36:38.591 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETRXGAIN
2026-01-29 03:36:38.591 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETTSC
2026-01-29 03:36:38.591 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:36:38.591 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:36:38.591 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:36:38.591 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.28.20:5700) Recv NOMTXPOWER cmd
2026-01-29 03:36:38.591 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:36:38.591 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:36:38.591 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:36:38.591 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.28.20:5700) Recv POWERON CMD
2026-01-29 03:36:38.591 [INFO] ctrl_if_trx.py:109 (BTS@172.18.28.20:5700) Starting transceiver...
2026-01-29 03:36:38.591 [INFO] transceiver.py:243 Starting clock generator
2026-01-29 03:36:38.591 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-01-29 03:36:38.591 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:36:38.591 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:36:38.591 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:36:38.591 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETRXGAIN
2026-01-29 03:36:38.591 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:36:38.591 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:36:38.591 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:36:38.591 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:36:38.591 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:36:38.591 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:36:38.591 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:36:38.591 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:36:38.591 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:36:38.591 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:36:38.591 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:36:38.591 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:36:38.591 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:36:38.591 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:36:38.591 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:36:38.591 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:36:38.591 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:36:38.591 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:36:38.591 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:36:38.591 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:36:38.591 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:36:38.592 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:36:38.592 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:36:38.596 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-01-29 03:36:39.078 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-01-29 03:36:39.118 [DEBUG] fake_trx.py:278 (BTS@172.18.28.20:5700) Recv FAKE_TOA cmd
2026-01-29 03:36:39.120 [DEBUG] fake_trx.py:297 (BTS@172.18.28.20:5700) Recv FAKE_RSSI cmd
2026-01-29 03:36:39.121 [DEBUG] fake_trx.py:322 (BTS@172.18.28.20:5700) Recv FAKE_CI cmd
2026-01-29 03:36:39.122 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:36:39.145 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 03:36:39.145 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 03:36:39.146 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 03:36:39.160 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 03:36:39.160 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 03:36:39.161 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 03:36:39.161 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:36:39.165 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 03:36:39.165 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 03:36:39.165 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 03:36:39.165 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.28.22:6700) Recv POWERON CMD
2026-01-29 03:36:39.165 [INFO] ctrl_if_trx.py:109 (MS@172.18.28.22:6700) Starting transceiver...
2026-01-29 03:36:39.168 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 03:36:39.168 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 03:36:39.168 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 03:36:39.168 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 03:36:39.555 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-01-29 03:36:39.593 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 03:36:39.593 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:36:39.594 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:36:39.595 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:36:39.780 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 03:36:39.781 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:36:39.785 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 03:36:39.785 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 03:36:39.804 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 03:36:39.804 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 03:36:39.804 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 03:36:39.810 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 03:36:39.810 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 03:36:39.810 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 03:36:39.811 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:36:39.812 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 03:36:39.812 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 03:36:39.812 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 03:36:39.812 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.28.22:6700) Recv POWERON CMD
2026-01-29 03:36:39.812 [INFO] ctrl_if_trx.py:109 (MS@172.18.28.22:6700) Starting transceiver...
2026-01-29 03:36:39.835 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.28.22:6700) Recv SETFH cmd
2026-01-29 03:36:39.835 [INFO] transceiver.py:201 (MS@172.18.28.22:6700) Frequency hopping configured: hsn=5, maio=0, ma_len=4
2026-01-29 03:36:39.836 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 03:36:39.836 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 03:36:40.029 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-01-29 03:36:40.498 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-01-29 03:36:40.594 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 03:36:40.594 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:36:40.594 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:36:40.596 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:36:40.759 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:36:40.760 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 03:36:40.764 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 03:36:40.764 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 03:36:40.764 [INFO] transceiver.py:205 (MS@172.18.28.22:6700) Frequency hopping disabled
2026-01-29 03:36:40.786 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 03:36:40.786 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 03:36:40.786 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 03:36:40.793 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 03:36:40.793 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 03:36:40.793 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 03:36:40.793 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:36:40.794 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 03:36:40.794 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 03:36:40.794 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 03:36:40.794 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.28.22:6700) Recv POWERON CMD
2026-01-29 03:36:40.794 [INFO] ctrl_if_trx.py:109 (MS@172.18.28.22:6700) Starting transceiver...
2026-01-29 03:36:40.823 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 03:36:40.824 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 03:36:40.824 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 03:36:40.824 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 03:36:40.969 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-01-29 03:36:41.448 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-01-29 03:36:41.594 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 03:36:41.595 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:36:41.595 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:36:41.597 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:36:41.926 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-01-29 03:36:42.404 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-01-29 03:36:42.596 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:36:42.596 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:36:42.596 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 03:36:42.598 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:36:42.795 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 03:36:42.796 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:36:42.799 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 03:36:42.799 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 03:36:42.817 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 03:36:42.817 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 03:36:42.817 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 03:36:42.823 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 03:36:42.823 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 03:36:42.823 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 03:36:42.824 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:36:42.825 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 03:36:42.825 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 03:36:42.825 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 03:36:42.825 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.28.22:6700) Recv POWERON CMD
2026-01-29 03:36:42.825 [INFO] ctrl_if_trx.py:109 (MS@172.18.28.22:6700) Starting transceiver...
2026-01-29 03:36:42.875 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.28.22:6700) Recv SETFH cmd
2026-01-29 03:36:42.875 [INFO] transceiver.py:201 (MS@172.18.28.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2026-01-29 03:36:42.875 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 03:36:42.875 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 03:36:42.881 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-01-29 03:36:43.360 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-01-29 03:36:43.597 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 03:36:43.597 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:36:43.597 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:36:43.599 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:36:43.838 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-01-29 03:36:44.315 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-01-29 03:36:44.790 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-01-29 03:36:45.265 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-01-29 03:36:45.739 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-01-29 03:36:46.210 [DEBUG] clck_gen.py:113 IND CLOCK 1632
2026-01-29 03:36:46.681 [DEBUG] clck_gen.py:113 IND CLOCK 1734
2026-01-29 03:36:47.151 [DEBUG] clck_gen.py:113 IND CLOCK 1836
2026-01-29 03:36:47.622 [DEBUG] clck_gen.py:113 IND CLOCK 1938
2026-01-29 03:36:48.098 [DEBUG] clck_gen.py:113 IND CLOCK 2040
2026-01-29 03:36:48.575 [DEBUG] clck_gen.py:113 IND CLOCK 2142
2026-01-29 03:36:49.049 [DEBUG] clck_gen.py:113 IND CLOCK 2244
2026-01-29 03:36:49.527 [DEBUG] clck_gen.py:113 IND CLOCK 2346
2026-01-29 03:36:50.005 [DEBUG] clck_gen.py:113 IND CLOCK 2448
2026-01-29 03:36:50.478 [DEBUG] clck_gen.py:113 IND CLOCK 2550
2026-01-29 03:36:50.956 [DEBUG] clck_gen.py:113 IND CLOCK 2652
2026-01-29 03:36:51.433 [DEBUG] clck_gen.py:113 IND CLOCK 2754
2026-01-29 03:36:51.909 [DEBUG] clck_gen.py:113 IND CLOCK 2856
2026-01-29 03:36:52.383 [DEBUG] clck_gen.py:113 IND CLOCK 2958
2026-01-29 03:36:52.852 [DEBUG] clck_gen.py:113 IND CLOCK 3060
2026-01-29 03:36:53.324 [DEBUG] clck_gen.py:113 IND CLOCK 3162
2026-01-29 03:36:53.796 [DEBUG] clck_gen.py:113 IND CLOCK 3264
2026-01-29 03:36:54.273 [DEBUG] clck_gen.py:113 IND CLOCK 3366
2026-01-29 03:36:54.750 [DEBUG] clck_gen.py:113 IND CLOCK 3468
2026-01-29 03:36:55.224 [DEBUG] clck_gen.py:113 IND CLOCK 3570
2026-01-29 03:36:55.697 [DEBUG] clck_gen.py:113 IND CLOCK 3672
2026-01-29 03:36:56.171 [DEBUG] clck_gen.py:113 IND CLOCK 3774
2026-01-29 03:36:56.646 [DEBUG] clck_gen.py:113 IND CLOCK 3876
2026-01-29 03:36:57.118 [DEBUG] clck_gen.py:113 IND CLOCK 3978
2026-01-29 03:36:57.596 [DEBUG] clck_gen.py:113 IND CLOCK 4080
2026-01-29 03:36:58.073 [DEBUG] clck_gen.py:113 IND CLOCK 4182
2026-01-29 03:36:58.549 [DEBUG] clck_gen.py:113 IND CLOCK 4284
2026-01-29 03:36:59.018 [DEBUG] clck_gen.py:113 IND CLOCK 4386
2026-01-29 03:36:59.494 [DEBUG] clck_gen.py:113 IND CLOCK 4488
2026-01-29 03:36:59.971 [DEBUG] clck_gen.py:113 IND CLOCK 4590
2026-01-29 03:37:00.448 [DEBUG] clck_gen.py:113 IND CLOCK 4692
2026-01-29 03:37:00.918 [DEBUG] clck_gen.py:113 IND CLOCK 4794
2026-01-29 03:37:01.396 [DEBUG] clck_gen.py:113 IND CLOCK 4896
2026-01-29 03:37:01.868 [DEBUG] clck_gen.py:113 IND CLOCK 4998
2026-01-29 03:37:02.338 [DEBUG] clck_gen.py:113 IND CLOCK 5100
2026-01-29 03:37:02.813 [DEBUG] clck_gen.py:113 IND CLOCK 5202
2026-01-29 03:37:02.821 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 03:37:02.821 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 03:37:02.821 [INFO] transceiver.py:205 (MS@172.18.28.22:6700) Frequency hopping disabled
2026-01-29 03:37:02.824 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 03:37:02.825 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:37:02.825 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:37:02.825 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:37:02.826 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 03:37:02.826 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 03:37:02.826 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 03:37:02.826 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 03:37:02.826 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.28.20:5700) Recv POWEROFF cmd
2026-01-29 03:37:02.826 [INFO] ctrl_if_trx.py:117 (BTS@172.18.28.20:5700) Stopping transceiver...
2026-01-29 03:37:02.826 [INFO] transceiver.py:246 Stopping clock generator
2026-01-29 03:37:07.826 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.28.20:5700) Recv POWEROFF cmd
2026-01-29 03:37:07.826 [INFO] ctrl_if_trx.py:117 (BTS@172.18.28.20:5700) Stopping transceiver...
2026-01-29 03:37:07.827 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 03:37:07.828 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 03:37:07.830 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 03:37:07.831 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 03:37:07.835 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 03:37:07.836 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.28.20:5700) Recv SETFORMAT cmd
2026-01-29 03:37:07.836 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.28.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:37:07.836 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.28.20:5700) Recv SETFORMAT cmd
2026-01-29 03:37:07.836 [INFO] ctrl_if_trx.py:201 (BTS@172.18.28.20:5700) TRXD header version 1 -> 1
2026-01-29 03:37:07.838 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.28.20:5700/1) Recv RXTUNE cmd
2026-01-29 03:37:07.838 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.28.20:5700/1) Recv TXTUNE cmd
2026-01-29 03:37:07.838 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.28.20:5700/1) Recv SETFORMAT cmd
2026-01-29 03:37:07.838 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.28.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:37:07.838 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 03:37:07.838 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.28.20:5700/1) Recv NOMTXPOWER cmd
2026-01-29 03:37:07.838 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.28.20:5700/1) Recv SETFORMAT cmd
2026-01-29 03:37:07.838 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.28.20:5700/1) TRXD header version 1 -> 1
2026-01-29 03:37:07.840 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.28.20:5700/2) Recv RXTUNE cmd
2026-01-29 03:37:07.840 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.28.20:5700/2) Recv TXTUNE cmd
2026-01-29 03:37:07.840 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.28.20:5700/2) Recv SETFORMAT cmd
2026-01-29 03:37:07.840 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.28.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:37:07.840 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 03:37:07.840 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.28.20:5700/2) Recv NOMTXPOWER cmd
2026-01-29 03:37:07.840 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.28.20:5700/2) Recv SETFORMAT cmd
2026-01-29 03:37:07.840 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.28.20:5700/2) TRXD header version 1 -> 1
2026-01-29 03:37:07.842 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.28.20:5700/3) Recv RXTUNE cmd
2026-01-29 03:37:07.842 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.28.20:5700/3) Recv TXTUNE cmd
2026-01-29 03:37:07.842 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.28.20:5700/3) Recv SETFORMAT cmd
2026-01-29 03:37:07.842 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.28.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:37:07.842 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 03:37:07.842 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.28.20:5700/3) Recv NOMTXPOWER cmd
2026-01-29 03:37:07.842 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.28.20:5700/3) Recv SETFORMAT cmd
2026-01-29 03:37:07.842 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.28.20:5700/3) TRXD header version 1 -> 1
2026-01-29 03:37:07.844 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.28.20:5700) Recv RXTUNE cmd
2026-01-29 03:37:07.844 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETTSC
2026-01-29 03:37:07.844 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETTSC
2026-01-29 03:37:07.844 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETTSC
2026-01-29 03:37:07.844 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.28.20:5700) Recv TXTUNE cmd
2026-01-29 03:37:07.844 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETRXGAIN
2026-01-29 03:37:07.845 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETRXGAIN
2026-01-29 03:37:07.845 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETRXGAIN
2026-01-29 03:37:07.845 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETTSC
2026-01-29 03:37:07.845 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:37:07.845 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:37:07.845 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:37:07.845 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.28.20:5700) Recv NOMTXPOWER cmd
2026-01-29 03:37:07.845 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:37:07.845 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:37:07.845 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:37:07.845 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.28.20:5700) Recv POWERON CMD
2026-01-29 03:37:07.845 [INFO] ctrl_if_trx.py:109 (BTS@172.18.28.20:5700) Starting transceiver...
2026-01-29 03:37:07.845 [INFO] transceiver.py:243 Starting clock generator
2026-01-29 03:37:07.845 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-01-29 03:37:07.845 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:37:07.845 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:37:07.845 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:37:07.845 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETRXGAIN
2026-01-29 03:37:07.845 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:37:07.845 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:37:07.845 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:37:07.845 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:37:07.845 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:37:07.845 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:37:07.845 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:37:07.845 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:37:07.845 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:37:07.846 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:37:07.846 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:37:07.846 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:37:07.846 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:37:07.846 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:37:07.846 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:37:07.846 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:37:07.846 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:37:07.846 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:37:07.846 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:37:07.846 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:37:07.846 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:37:07.846 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:37:07.846 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:37:07.850 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-01-29 03:37:08.326 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-01-29 03:37:08.367 [DEBUG] fake_trx.py:278 (BTS@172.18.28.20:5700) Recv FAKE_TOA cmd
2026-01-29 03:37:08.368 [DEBUG] fake_trx.py:297 (BTS@172.18.28.20:5700) Recv FAKE_RSSI cmd
2026-01-29 03:37:08.370 [DEBUG] fake_trx.py:322 (BTS@172.18.28.20:5700) Recv FAKE_CI cmd
2026-01-29 03:37:08.370 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:37:08.382 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 03:37:08.382 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 03:37:08.382 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 03:37:08.393 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 03:37:08.393 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 03:37:08.393 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 03:37:08.394 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:37:08.397 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 03:37:08.397 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 03:37:08.397 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 03:37:08.397 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.28.22:6700) Recv POWERON CMD
2026-01-29 03:37:08.397 [INFO] ctrl_if_trx.py:109 (MS@172.18.28.22:6700) Starting transceiver...
2026-01-29 03:37:08.418 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 03:37:08.418 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 03:37:08.418 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 03:37:08.418 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 03:37:08.802 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-01-29 03:37:08.848 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:37:08.849 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 03:37:08.849 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:37:08.850 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:37:09.279 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-01-29 03:37:09.755 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-01-29 03:37:09.849 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:37:09.849 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 03:37:09.849 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:37:09.851 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:37:10.233 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-01-29 03:37:10.711 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-01-29 03:37:10.850 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:37:10.850 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 03:37:10.850 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:37:10.851 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:37:10.853 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 03:37:10.854 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:37:10.857 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 03:37:10.857 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 03:37:10.874 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 03:37:10.874 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 03:37:10.874 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 03:37:10.880 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 03:37:10.880 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 03:37:10.880 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 03:37:10.881 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:37:10.882 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 03:37:10.882 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 03:37:10.882 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 03:37:10.882 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.28.22:6700) Recv POWERON CMD
2026-01-29 03:37:10.882 [INFO] ctrl_if_trx.py:109 (MS@172.18.28.22:6700) Starting transceiver...
2026-01-29 03:37:10.892 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.28.22:6700) Recv SETFH cmd
2026-01-29 03:37:10.892 [INFO] transceiver.py:201 (MS@172.18.28.22:6700) Frequency hopping configured: hsn=5, maio=0, ma_len=4
2026-01-29 03:37:10.892 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 03:37:10.892 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 03:37:11.182 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-01-29 03:37:11.655 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-01-29 03:37:11.851 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 03:37:11.851 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:37:11.851 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:37:11.852 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:37:12.133 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-01-29 03:37:12.610 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-01-29 03:37:12.852 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:37:12.852 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:37:12.853 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 03:37:12.853 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:37:13.089 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-01-29 03:37:13.565 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-01-29 03:37:13.628 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 03:37:13.629 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:37:13.632 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 03:37:13.632 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 03:37:13.633 [INFO] transceiver.py:205 (MS@172.18.28.22:6700) Frequency hopping disabled
2026-01-29 03:37:13.651 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 03:37:13.651 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 03:37:13.651 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 03:37:13.658 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 03:37:13.658 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 03:37:13.658 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 03:37:13.658 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:37:13.659 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 03:37:13.659 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 03:37:13.659 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 03:37:13.659 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.28.22:6700) Recv POWERON CMD
2026-01-29 03:37:13.659 [INFO] ctrl_if_trx.py:109 (MS@172.18.28.22:6700) Starting transceiver...
2026-01-29 03:37:13.700 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 03:37:13.700 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 03:37:13.700 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 03:37:13.701 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 03:37:14.041 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-01-29 03:37:14.520 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-01-29 03:37:14.997 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-01-29 03:37:15.476 [DEBUG] clck_gen.py:113 IND CLOCK 1632
2026-01-29 03:37:15.954 [DEBUG] clck_gen.py:113 IND CLOCK 1734
2026-01-29 03:37:16.432 [DEBUG] clck_gen.py:113 IND CLOCK 1836
2026-01-29 03:37:16.910 [DEBUG] clck_gen.py:113 IND CLOCK 1938
2026-01-29 03:37:17.063 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 03:37:17.063 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:37:17.064 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 03:37:17.064 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 03:37:17.071 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 03:37:17.071 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 03:37:17.071 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 03:37:17.077 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 03:37:17.077 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 03:37:17.077 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 03:37:17.077 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:37:17.078 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 03:37:17.078 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 03:37:17.078 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 03:37:17.078 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.28.22:6700) Recv POWERON CMD
2026-01-29 03:37:17.078 [INFO] ctrl_if_trx.py:109 (MS@172.18.28.22:6700) Starting transceiver...
2026-01-29 03:37:17.091 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.28.22:6700) Recv SETFH cmd
2026-01-29 03:37:17.091 [INFO] transceiver.py:201 (MS@172.18.28.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2026-01-29 03:37:17.091 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 03:37:17.091 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 03:37:17.380 [DEBUG] clck_gen.py:113 IND CLOCK 2040
2026-01-29 03:37:17.855 [DEBUG] clck_gen.py:113 IND CLOCK 2142
2026-01-29 03:37:18.334 [DEBUG] clck_gen.py:113 IND CLOCK 2244
2026-01-29 03:37:18.811 [DEBUG] clck_gen.py:113 IND CLOCK 2346
2026-01-29 03:37:19.287 [DEBUG] clck_gen.py:113 IND CLOCK 2448
2026-01-29 03:37:19.763 [DEBUG] clck_gen.py:113 IND CLOCK 2550
2026-01-29 03:37:20.240 [DEBUG] clck_gen.py:113 IND CLOCK 2652
2026-01-29 03:37:20.717 [DEBUG] clck_gen.py:113 IND CLOCK 2754
2026-01-29 03:37:21.193 [DEBUG] clck_gen.py:113 IND CLOCK 2856
2026-01-29 03:37:21.669 [DEBUG] clck_gen.py:113 IND CLOCK 2958
2026-01-29 03:37:22.145 [DEBUG] clck_gen.py:113 IND CLOCK 3060
2026-01-29 03:37:22.617 [DEBUG] clck_gen.py:113 IND CLOCK 3162
2026-01-29 03:37:23.089 [DEBUG] clck_gen.py:113 IND CLOCK 3264
2026-01-29 03:37:23.558 [DEBUG] clck_gen.py:113 IND CLOCK 3366
2026-01-29 03:37:24.036 [DEBUG] clck_gen.py:113 IND CLOCK 3468
2026-01-29 03:37:24.513 [DEBUG] clck_gen.py:113 IND CLOCK 3570
2026-01-29 03:37:24.987 [DEBUG] clck_gen.py:113 IND CLOCK 3672
2026-01-29 03:37:25.462 [DEBUG] clck_gen.py:113 IND CLOCK 3774
2026-01-29 03:37:25.939 [DEBUG] clck_gen.py:113 IND CLOCK 3876
2026-01-29 03:37:26.415 [DEBUG] clck_gen.py:113 IND CLOCK 3978
2026-01-29 03:37:26.889 [DEBUG] clck_gen.py:113 IND CLOCK 4080
2026-01-29 03:37:27.367 [DEBUG] clck_gen.py:113 IND CLOCK 4182
2026-01-29 03:37:27.844 [DEBUG] clck_gen.py:113 IND CLOCK 4284
2026-01-29 03:37:28.322 [DEBUG] clck_gen.py:113 IND CLOCK 4386
2026-01-29 03:37:28.799 [DEBUG] clck_gen.py:113 IND CLOCK 4488
2026-01-29 03:37:29.277 [DEBUG] clck_gen.py:113 IND CLOCK 4590
2026-01-29 03:37:29.754 [DEBUG] clck_gen.py:113 IND CLOCK 4692
2026-01-29 03:37:30.231 [DEBUG] clck_gen.py:113 IND CLOCK 4794
2026-01-29 03:37:30.708 [DEBUG] clck_gen.py:113 IND CLOCK 4896
2026-01-29 03:37:31.181 [DEBUG] clck_gen.py:113 IND CLOCK 4998
2026-01-29 03:37:31.659 [DEBUG] clck_gen.py:113 IND CLOCK 5100
2026-01-29 03:37:32.137 [DEBUG] clck_gen.py:113 IND CLOCK 5202
2026-01-29 03:37:32.608 [DEBUG] clck_gen.py:113 IND CLOCK 5304
2026-01-29 03:37:33.079 [DEBUG] clck_gen.py:113 IND CLOCK 5406
2026-01-29 03:37:33.549 [DEBUG] clck_gen.py:113 IND CLOCK 5508
2026-01-29 03:37:34.018 [DEBUG] clck_gen.py:113 IND CLOCK 5610
2026-01-29 03:37:34.487 [DEBUG] clck_gen.py:113 IND CLOCK 5712
2026-01-29 03:37:34.962 [DEBUG] clck_gen.py:113 IND CLOCK 5814
2026-01-29 03:37:35.439 [DEBUG] clck_gen.py:113 IND CLOCK 5916
2026-01-29 03:37:35.917 [DEBUG] clck_gen.py:113 IND CLOCK 6018
2026-01-29 03:37:36.395 [DEBUG] clck_gen.py:113 IND CLOCK 6120
2026-01-29 03:37:36.870 [DEBUG] clck_gen.py:113 IND CLOCK 6222
2026-01-29 03:37:37.073 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 03:37:37.074 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 03:37:37.074 [INFO] transceiver.py:205 (MS@172.18.28.22:6700) Frequency hopping disabled
2026-01-29 03:37:37.077 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 03:37:37.077 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:37:37.077 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:37:37.077 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:37:37.079 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 03:37:37.079 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 03:37:37.079 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 03:37:37.079 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 03:37:37.079 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.28.20:5700) Recv POWEROFF cmd
2026-01-29 03:37:37.079 [INFO] ctrl_if_trx.py:117 (BTS@172.18.28.20:5700) Stopping transceiver...
2026-01-29 03:37:37.079 [INFO] transceiver.py:246 Stopping clock generator
2026-01-29 03:37:37.079 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=6269 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:37:37.079 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=6269 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:37:37.080 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=6269 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:37:37.080 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=6269 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:37:37.080 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=6269 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:37:37.080 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=6269 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:37:37.080 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=6269 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:37:37.080 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=6270 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:37:37.080 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=6270 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:37:37.080 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=6270 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:37:37.080 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=6270 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:37:37.080 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=6270 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:37:37.080 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=6270 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:37:37.080 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=6270 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:37:37.080 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=6270 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:37:42.081 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.28.20:5700) Recv POWEROFF cmd
2026-01-29 03:37:42.081 [INFO] ctrl_if_trx.py:117 (BTS@172.18.28.20:5700) Stopping transceiver...
2026-01-29 03:37:42.082 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 03:37:42.083 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 03:37:42.084 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 03:37:42.084 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 03:37:42.090 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 03:37:42.090 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.28.20:5700) Recv SETFORMAT cmd
2026-01-29 03:37:42.090 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.28.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:37:42.091 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.28.20:5700) Recv SETFORMAT cmd
2026-01-29 03:37:42.091 [INFO] ctrl_if_trx.py:201 (BTS@172.18.28.20:5700) TRXD header version 1 -> 1
2026-01-29 03:37:42.093 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.28.20:5700/1) Recv RXTUNE cmd
2026-01-29 03:37:42.093 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.28.20:5700/1) Recv TXTUNE cmd
2026-01-29 03:37:42.093 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.28.20:5700/1) Recv SETFORMAT cmd
2026-01-29 03:37:42.093 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.28.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:37:42.093 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 03:37:42.093 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.28.20:5700/1) Recv NOMTXPOWER cmd
2026-01-29 03:37:42.094 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.28.20:5700/1) Recv SETFORMAT cmd
2026-01-29 03:37:42.094 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.28.20:5700/1) TRXD header version 1 -> 1
2026-01-29 03:37:42.096 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.28.20:5700/2) Recv RXTUNE cmd
2026-01-29 03:37:42.096 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.28.20:5700/2) Recv TXTUNE cmd
2026-01-29 03:37:42.096 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.28.20:5700/2) Recv SETFORMAT cmd
2026-01-29 03:37:42.096 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.28.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:37:42.096 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 03:37:42.096 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.28.20:5700/2) Recv NOMTXPOWER cmd
2026-01-29 03:37:42.096 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.28.20:5700/2) Recv SETFORMAT cmd
2026-01-29 03:37:42.096 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.28.20:5700/2) TRXD header version 1 -> 1
2026-01-29 03:37:42.098 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.28.20:5700/3) Recv RXTUNE cmd
2026-01-29 03:37:42.098 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.28.20:5700/3) Recv TXTUNE cmd
2026-01-29 03:37:42.098 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.28.20:5700/3) Recv SETFORMAT cmd
2026-01-29 03:37:42.098 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.28.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:37:42.098 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 03:37:42.098 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.28.20:5700/3) Recv NOMTXPOWER cmd
2026-01-29 03:37:42.098 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.28.20:5700/3) Recv SETFORMAT cmd
2026-01-29 03:37:42.098 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.28.20:5700/3) TRXD header version 1 -> 1
2026-01-29 03:37:42.101 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.28.20:5700) Recv RXTUNE cmd
2026-01-29 03:37:42.101 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETTSC
2026-01-29 03:37:42.101 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETTSC
2026-01-29 03:37:42.101 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETTSC
2026-01-29 03:37:42.101 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.28.20:5700) Recv TXTUNE cmd
2026-01-29 03:37:42.101 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETRXGAIN
2026-01-29 03:37:42.101 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETRXGAIN
2026-01-29 03:37:42.101 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETRXGAIN
2026-01-29 03:37:42.102 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETTSC
2026-01-29 03:37:42.102 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:37:42.102 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:37:42.102 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.28.20:5700) Recv NOMTXPOWER cmd
2026-01-29 03:37:42.102 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:37:42.102 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:37:42.102 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:37:42.102 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.28.20:5700) Recv POWERON CMD
2026-01-29 03:37:42.102 [INFO] ctrl_if_trx.py:109 (BTS@172.18.28.20:5700) Starting transceiver...
2026-01-29 03:37:42.102 [INFO] transceiver.py:243 Starting clock generator
2026-01-29 03:37:42.102 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-01-29 03:37:42.102 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:37:42.102 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:37:42.102 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:37:42.102 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETRXGAIN
2026-01-29 03:37:42.102 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:37:42.102 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:37:42.102 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:37:42.102 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:37:42.102 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:37:42.102 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:37:42.102 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:37:42.102 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:37:42.103 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:37:42.103 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:37:42.103 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:37:42.103 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:37:42.103 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:37:42.103 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:37:42.103 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:37:42.103 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:37:42.103 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:37:42.103 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:37:42.103 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:37:42.103 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:37:42.103 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:37:42.103 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:37:42.103 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:37:42.103 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:37:42.107 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-01-29 03:37:42.581 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-01-29 03:37:42.631 [DEBUG] fake_trx.py:278 (BTS@172.18.28.20:5700) Recv FAKE_TOA cmd
2026-01-29 03:37:42.631 [DEBUG] fake_trx.py:297 (BTS@172.18.28.20:5700) Recv FAKE_RSSI cmd
2026-01-29 03:37:42.632 [DEBUG] fake_trx.py:322 (BTS@172.18.28.20:5700) Recv FAKE_CI cmd
2026-01-29 03:37:42.633 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:37:42.652 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 03:37:42.652 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 03:37:42.652 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 03:37:42.667 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 03:37:42.667 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 03:37:42.667 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 03:37:42.667 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:37:42.670 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 03:37:42.670 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 03:37:42.670 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 03:37:42.670 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.28.22:6700) Recv POWERON CMD
2026-01-29 03:37:42.670 [INFO] ctrl_if_trx.py:109 (MS@172.18.28.22:6700) Starting transceiver...
2026-01-29 03:37:42.718 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 03:37:42.719 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 03:37:42.719 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 03:37:42.719 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 03:37:42.935 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 03:37:42.935 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:37:42.939 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 03:37:42.939 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 03:37:42.957 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 03:37:42.957 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 03:37:42.957 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 03:37:42.964 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 03:37:42.964 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 03:37:42.964 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 03:37:42.964 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:37:42.966 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 03:37:42.966 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 03:37:42.966 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 03:37:42.966 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.28.22:6700) Recv POWERON CMD
2026-01-29 03:37:42.966 [INFO] ctrl_if_trx.py:109 (MS@172.18.28.22:6700) Starting transceiver...
2026-01-29 03:37:43.001 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.28.22:6700) Recv SETFH cmd
2026-01-29 03:37:43.001 [INFO] transceiver.py:201 (MS@172.18.28.22:6700) Frequency hopping configured: hsn=5, maio=0, ma_len=4
2026-01-29 03:37:43.001 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 03:37:43.001 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 03:37:43.057 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-01-29 03:37:43.105 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 03:37:43.106 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:37:43.108 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:37:43.113 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:37:43.342 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 03:37:43.342 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:37:43.346 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 03:37:43.346 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 03:37:43.346 [INFO] transceiver.py:205 (MS@172.18.28.22:6700) Frequency hopping disabled
2026-01-29 03:37:43.364 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 03:37:43.364 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 03:37:43.365 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 03:37:43.370 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 03:37:43.371 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 03:37:43.371 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:37:43.371 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 03:37:43.372 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 03:37:43.372 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 03:37:43.372 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 03:37:43.372 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.28.22:6700) Recv POWERON CMD
2026-01-29 03:37:43.372 [INFO] ctrl_if_trx.py:109 (MS@172.18.28.22:6700) Starting transceiver...
2026-01-29 03:37:43.382 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 03:37:43.382 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 03:37:43.382 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 03:37:43.382 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 03:37:43.534 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-01-29 03:37:43.925 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 03:37:43.926 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:37:43.929 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 03:37:43.929 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 03:37:43.947 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 03:37:43.947 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 03:37:43.947 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 03:37:43.953 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 03:37:43.954 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 03:37:43.954 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 03:37:43.954 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:37:43.956 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 03:37:43.956 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 03:37:43.956 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 03:37:43.956 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.28.22:6700) Recv POWERON CMD
2026-01-29 03:37:43.956 [INFO] ctrl_if_trx.py:109 (MS@172.18.28.22:6700) Starting transceiver...
2026-01-29 03:37:44.004 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.28.22:6700) Recv SETFH cmd
2026-01-29 03:37:44.005 [INFO] transceiver.py:201 (MS@172.18.28.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2026-01-29 03:37:44.005 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 03:37:44.005 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 03:37:44.011 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-01-29 03:37:44.106 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 03:37:44.107 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:37:44.109 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:37:44.114 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:37:44.489 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-01-29 03:37:44.572 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 03:37:44.572 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:37:44.575 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 03:37:44.575 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 03:37:44.575 [INFO] transceiver.py:205 (MS@172.18.28.22:6700) Frequency hopping disabled
2026-01-29 03:37:44.584 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 03:37:44.585 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:37:44.585 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:37:44.585 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:37:44.588 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 03:37:44.589 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 03:37:44.589 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 03:37:44.589 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.28.20:5700) Recv POWEROFF cmd
2026-01-29 03:37:44.589 [INFO] ctrl_if_trx.py:117 (BTS@172.18.28.20:5700) Stopping transceiver...
2026-01-29 03:37:44.589 [INFO] transceiver.py:246 Stopping clock generator
2026-01-29 03:37:44.589 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 03:37:44.590 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=533 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:37:44.590 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=533 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:37:44.590 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=533 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:37:44.590 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=533 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:37:44.590 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=533 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:37:44.590 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=533 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:37:44.590 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=533 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:37:49.587 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.28.20:5700) Recv POWEROFF cmd
2026-01-29 03:37:49.587 [INFO] ctrl_if_trx.py:117 (BTS@172.18.28.20:5700) Stopping transceiver...
2026-01-29 03:37:49.588 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 03:37:49.590 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 03:37:49.590 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 03:37:49.591 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 03:37:49.600 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 03:37:49.601 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.28.20:5700) Recv SETFORMAT cmd
2026-01-29 03:37:49.602 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.28.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:37:49.602 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.28.20:5700) Recv SETFORMAT cmd
2026-01-29 03:37:49.602 [INFO] ctrl_if_trx.py:201 (BTS@172.18.28.20:5700) TRXD header version 1 -> 1
2026-01-29 03:37:49.605 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.28.20:5700/1) Recv RXTUNE cmd
2026-01-29 03:37:49.606 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.28.20:5700/1) Recv TXTUNE cmd
2026-01-29 03:37:49.606 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.28.20:5700/1) Recv SETFORMAT cmd
2026-01-29 03:37:49.606 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.28.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:37:49.607 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 03:37:49.607 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.28.20:5700/1) Recv NOMTXPOWER cmd
2026-01-29 03:37:49.607 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.28.20:5700/1) Recv SETFORMAT cmd
2026-01-29 03:37:49.607 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.28.20:5700/1) TRXD header version 1 -> 1
2026-01-29 03:37:49.608 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.28.20:5700/2) Recv RXTUNE cmd
2026-01-29 03:37:49.608 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.28.20:5700/2) Recv TXTUNE cmd
2026-01-29 03:37:49.608 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.28.20:5700/2) Recv SETFORMAT cmd
2026-01-29 03:37:49.608 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.28.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:37:49.609 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 03:37:49.609 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.28.20:5700/2) Recv NOMTXPOWER cmd
2026-01-29 03:37:49.609 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.28.20:5700/2) Recv SETFORMAT cmd
2026-01-29 03:37:49.609 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.28.20:5700/2) TRXD header version 1 -> 1
2026-01-29 03:37:49.611 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.28.20:5700/3) Recv RXTUNE cmd
2026-01-29 03:37:49.611 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.28.20:5700/3) Recv TXTUNE cmd
2026-01-29 03:37:49.611 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.28.20:5700/3) Recv SETFORMAT cmd
2026-01-29 03:37:49.611 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.28.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:37:49.611 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 03:37:49.611 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.28.20:5700/3) Recv NOMTXPOWER cmd
2026-01-29 03:37:49.611 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.28.20:5700/3) Recv SETFORMAT cmd
2026-01-29 03:37:49.611 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.28.20:5700/3) TRXD header version 1 -> 1
2026-01-29 03:37:49.614 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.28.20:5700) Recv RXTUNE cmd
2026-01-29 03:37:49.614 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETTSC
2026-01-29 03:37:49.614 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETTSC
2026-01-29 03:37:49.614 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETTSC
2026-01-29 03:37:49.614 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.28.20:5700) Recv TXTUNE cmd
2026-01-29 03:37:49.614 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETRXGAIN
2026-01-29 03:37:49.614 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETRXGAIN
2026-01-29 03:37:49.614 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETTSC
2026-01-29 03:37:49.614 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:37:49.614 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETRXGAIN
2026-01-29 03:37:49.614 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:37:49.614 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.28.20:5700) Recv NOMTXPOWER cmd
2026-01-29 03:37:49.614 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:37:49.614 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:37:49.614 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:37:49.614 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.28.20:5700) Recv POWERON CMD
2026-01-29 03:37:49.614 [INFO] ctrl_if_trx.py:109 (BTS@172.18.28.20:5700) Starting transceiver...
2026-01-29 03:37:49.614 [INFO] transceiver.py:243 Starting clock generator
2026-01-29 03:37:49.614 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-01-29 03:37:49.614 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:37:49.614 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:37:49.614 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:37:49.615 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETRXGAIN
2026-01-29 03:37:49.615 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:37:49.615 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:37:49.615 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:37:49.615 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:37:49.615 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:37:49.615 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:37:49.615 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:37:49.615 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:37:49.615 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:37:49.615 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:37:49.615 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:37:49.615 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:37:49.615 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:37:49.615 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:37:49.615 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:37:49.615 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:37:49.615 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:37:49.615 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:37:49.615 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:37:49.615 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:37:49.615 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:37:49.615 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:37:49.615 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:37:49.615 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:37:49.619 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-01-29 03:37:50.099 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-01-29 03:37:50.148 [DEBUG] fake_trx.py:278 (BTS@172.18.28.20:5700) Recv FAKE_TOA cmd
2026-01-29 03:37:50.151 [DEBUG] fake_trx.py:297 (BTS@172.18.28.20:5700) Recv FAKE_RSSI cmd
2026-01-29 03:37:50.152 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:37:50.153 [DEBUG] fake_trx.py:322 (BTS@172.18.28.20:5700) Recv FAKE_CI cmd
2026-01-29 03:37:50.175 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 03:37:50.175 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 03:37:50.176 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 03:37:50.195 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 03:37:50.195 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 03:37:50.195 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 03:37:50.196 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:37:50.200 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 03:37:50.200 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 03:37:50.200 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 03:37:50.201 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.28.22:6700) Recv POWERON CMD
2026-01-29 03:37:50.201 [INFO] ctrl_if_trx.py:109 (MS@172.18.28.22:6700) Starting transceiver...
2026-01-29 03:37:50.236 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 03:37:50.237 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 03:37:50.237 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 03:37:50.237 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 03:37:50.575 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-01-29 03:37:50.618 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 03:37:50.618 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:37:50.620 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:37:50.624 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:37:51.054 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-01-29 03:37:51.532 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-01-29 03:37:51.618 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 03:37:51.619 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:37:51.621 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:37:51.625 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:37:52.007 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-01-29 03:37:52.483 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-01-29 03:37:52.620 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 03:37:52.620 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:37:52.622 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:37:52.626 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:37:52.962 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-01-29 03:37:53.440 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-01-29 03:37:53.620 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 03:37:53.621 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:37:53.623 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:37:53.627 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:37:53.918 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-01-29 03:37:54.393 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-01-29 03:37:54.621 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 03:37:54.621 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:37:54.624 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:37:54.628 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:37:54.870 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-01-29 03:37:55.341 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-01-29 03:37:55.812 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-01-29 03:37:56.283 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-01-29 03:37:56.754 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-01-29 03:37:57.225 [DEBUG] clck_gen.py:113 IND CLOCK 1632
2026-01-29 03:37:57.698 [DEBUG] clck_gen.py:113 IND CLOCK 1734
2026-01-29 03:37:58.174 [DEBUG] clck_gen.py:113 IND CLOCK 1836
2026-01-29 03:37:58.650 [DEBUG] clck_gen.py:113 IND CLOCK 1938
2026-01-29 03:37:59.126 [DEBUG] clck_gen.py:113 IND CLOCK 2040
2026-01-29 03:37:59.603 [DEBUG] clck_gen.py:113 IND CLOCK 2142
2026-01-29 03:38:00.080 [DEBUG] clck_gen.py:113 IND CLOCK 2244
2026-01-29 03:38:00.554 [DEBUG] clck_gen.py:113 IND CLOCK 2346
2026-01-29 03:38:01.029 [DEBUG] clck_gen.py:113 IND CLOCK 2448
2026-01-29 03:38:01.506 [DEBUG] clck_gen.py:113 IND CLOCK 2550
2026-01-29 03:38:01.982 [DEBUG] clck_gen.py:113 IND CLOCK 2652
2026-01-29 03:38:02.454 [DEBUG] clck_gen.py:113 IND CLOCK 2754
2026-01-29 03:38:02.930 [DEBUG] clck_gen.py:113 IND CLOCK 2856
2026-01-29 03:38:03.406 [DEBUG] clck_gen.py:113 IND CLOCK 2958
2026-01-29 03:38:03.882 [DEBUG] clck_gen.py:113 IND CLOCK 3060
2026-01-29 03:38:04.359 [DEBUG] clck_gen.py:113 IND CLOCK 3162
2026-01-29 03:38:04.831 [DEBUG] clck_gen.py:113 IND CLOCK 3264
2026-01-29 03:38:05.302 [DEBUG] clck_gen.py:113 IND CLOCK 3366
2026-01-29 03:38:05.779 [DEBUG] clck_gen.py:113 IND CLOCK 3468
2026-01-29 03:38:06.255 [DEBUG] clck_gen.py:113 IND CLOCK 3570
2026-01-29 03:38:06.732 [DEBUG] clck_gen.py:113 IND CLOCK 3672
2026-01-29 03:38:07.209 [DEBUG] clck_gen.py:113 IND CLOCK 3774
2026-01-29 03:38:07.686 [DEBUG] clck_gen.py:113 IND CLOCK 3876
2026-01-29 03:38:08.163 [DEBUG] clck_gen.py:113 IND CLOCK 3978
2026-01-29 03:38:08.640 [DEBUG] clck_gen.py:113 IND CLOCK 4080
2026-01-29 03:38:09.116 [DEBUG] clck_gen.py:113 IND CLOCK 4182
2026-01-29 03:38:09.593 [DEBUG] clck_gen.py:113 IND CLOCK 4284
2026-01-29 03:38:10.070 [DEBUG] clck_gen.py:113 IND CLOCK 4386
2026-01-29 03:38:10.545 [DEBUG] clck_gen.py:113 IND CLOCK 4488
2026-01-29 03:38:11.021 [DEBUG] clck_gen.py:113 IND CLOCK 4590
2026-01-29 03:38:11.498 [DEBUG] clck_gen.py:113 IND CLOCK 4692
2026-01-29 03:38:11.974 [DEBUG] clck_gen.py:113 IND CLOCK 4794
2026-01-29 03:38:12.450 [DEBUG] clck_gen.py:113 IND CLOCK 4896
2026-01-29 03:38:12.926 [DEBUG] clck_gen.py:113 IND CLOCK 4998
2026-01-29 03:38:13.403 [DEBUG] clck_gen.py:113 IND CLOCK 5100
2026-01-29 03:38:13.880 [DEBUG] clck_gen.py:113 IND CLOCK 5202
2026-01-29 03:38:14.357 [DEBUG] clck_gen.py:113 IND CLOCK 5304
2026-01-29 03:38:14.833 [DEBUG] clck_gen.py:113 IND CLOCK 5406
2026-01-29 03:38:15.310 [DEBUG] clck_gen.py:113 IND CLOCK 5508
2026-01-29 03:38:15.787 [DEBUG] clck_gen.py:113 IND CLOCK 5610
2026-01-29 03:38:16.265 [DEBUG] clck_gen.py:113 IND CLOCK 5712
2026-01-29 03:38:16.741 [DEBUG] clck_gen.py:113 IND CLOCK 5814
2026-01-29 03:38:17.219 [DEBUG] clck_gen.py:113 IND CLOCK 5916
2026-01-29 03:38:17.696 [DEBUG] clck_gen.py:113 IND CLOCK 6018
2026-01-29 03:38:18.173 [DEBUG] clck_gen.py:113 IND CLOCK 6120
2026-01-29 03:38:18.650 [DEBUG] clck_gen.py:113 IND CLOCK 6222
2026-01-29 03:38:19.127 [DEBUG] clck_gen.py:113 IND CLOCK 6324
2026-01-29 03:38:19.602 [DEBUG] clck_gen.py:113 IND CLOCK 6426
2026-01-29 03:38:20.079 [DEBUG] clck_gen.py:113 IND CLOCK 6528
2026-01-29 03:38:20.558 [DEBUG] clck_gen.py:113 IND CLOCK 6630
2026-01-29 03:38:21.035 [DEBUG] clck_gen.py:113 IND CLOCK 6732
2026-01-29 03:38:21.511 [DEBUG] clck_gen.py:113 IND CLOCK 6834
2026-01-29 03:38:21.983 [DEBUG] clck_gen.py:113 IND CLOCK 6936
2026-01-29 03:38:22.458 [DEBUG] clck_gen.py:113 IND CLOCK 7038
2026-01-29 03:38:22.929 [DEBUG] clck_gen.py:113 IND CLOCK 7140
2026-01-29 03:38:23.197 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 03:38:23.198 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:38:23.203 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 03:38:23.203 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 03:38:23.210 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 03:38:23.210 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 03:38:23.210 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 03:38:23.216 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 03:38:23.216 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 03:38:23.217 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 03:38:23.217 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:38:23.218 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 03:38:23.218 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 03:38:23.218 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 03:38:23.218 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.28.22:6700) Recv POWERON CMD
2026-01-29 03:38:23.218 [INFO] ctrl_if_trx.py:109 (MS@172.18.28.22:6700) Starting transceiver...
2026-01-29 03:38:23.256 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.28.22:6700) Recv SETFH cmd
2026-01-29 03:38:23.256 [INFO] transceiver.py:201 (MS@172.18.28.22:6700) Frequency hopping configured: hsn=5, maio=0, ma_len=4
2026-01-29 03:38:23.257 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 03:38:23.257 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 03:38:23.405 [DEBUG] clck_gen.py:113 IND CLOCK 7242
2026-01-29 03:38:23.883 [DEBUG] clck_gen.py:113 IND CLOCK 7344
2026-01-29 03:38:24.360 [DEBUG] clck_gen.py:113 IND CLOCK 7446
2026-01-29 03:38:24.839 [DEBUG] clck_gen.py:113 IND CLOCK 7548
2026-01-29 03:38:25.316 [DEBUG] clck_gen.py:113 IND CLOCK 7650
2026-01-29 03:38:25.789 [DEBUG] clck_gen.py:113 IND CLOCK 7752
2026-01-29 03:38:26.260 [DEBUG] clck_gen.py:113 IND CLOCK 7854
2026-01-29 03:38:26.731 [DEBUG] clck_gen.py:113 IND CLOCK 7956
2026-01-29 03:38:27.200 [DEBUG] clck_gen.py:113 IND CLOCK 8058
2026-01-29 03:38:27.672 [DEBUG] clck_gen.py:113 IND CLOCK 8160
2026-01-29 03:38:28.142 [DEBUG] clck_gen.py:113 IND CLOCK 8262
2026-01-29 03:38:28.612 [DEBUG] clck_gen.py:113 IND CLOCK 8364
2026-01-29 03:38:29.085 [DEBUG] clck_gen.py:113 IND CLOCK 8466
2026-01-29 03:38:29.554 [DEBUG] clck_gen.py:113 IND CLOCK 8568
2026-01-29 03:38:30.028 [DEBUG] clck_gen.py:113 IND CLOCK 8670
2026-01-29 03:38:30.506 [DEBUG] clck_gen.py:113 IND CLOCK 8772
2026-01-29 03:38:30.983 [DEBUG] clck_gen.py:113 IND CLOCK 8874
2026-01-29 03:38:31.460 [DEBUG] clck_gen.py:113 IND CLOCK 8976
2026-01-29 03:38:31.937 [DEBUG] clck_gen.py:113 IND CLOCK 9078
2026-01-29 03:38:32.415 [DEBUG] clck_gen.py:113 IND CLOCK 9180
2026-01-29 03:38:32.893 [DEBUG] clck_gen.py:113 IND CLOCK 9282
2026-01-29 03:38:33.371 [DEBUG] clck_gen.py:113 IND CLOCK 9384
2026-01-29 03:38:33.849 [DEBUG] clck_gen.py:113 IND CLOCK 9486
2026-01-29 03:38:34.326 [DEBUG] clck_gen.py:113 IND CLOCK 9588
2026-01-29 03:38:34.803 [DEBUG] clck_gen.py:113 IND CLOCK 9690
2026-01-29 03:38:35.272 [DEBUG] clck_gen.py:113 IND CLOCK 9792
2026-01-29 03:38:35.741 [DEBUG] clck_gen.py:113 IND CLOCK 9894
2026-01-29 03:38:36.220 [DEBUG] clck_gen.py:113 IND CLOCK 9996
2026-01-29 03:38:36.697 [DEBUG] clck_gen.py:113 IND CLOCK 10098
2026-01-29 03:38:37.174 [DEBUG] clck_gen.py:113 IND CLOCK 10200
2026-01-29 03:38:37.652 [DEBUG] clck_gen.py:113 IND CLOCK 10302
2026-01-29 03:38:38.129 [DEBUG] clck_gen.py:113 IND CLOCK 10404
2026-01-29 03:38:38.602 [DEBUG] clck_gen.py:113 IND CLOCK 10506
2026-01-29 03:38:39.072 [DEBUG] clck_gen.py:113 IND CLOCK 10608
2026-01-29 03:38:39.543 [DEBUG] clck_gen.py:113 IND CLOCK 10710
2026-01-29 03:38:40.013 [DEBUG] clck_gen.py:113 IND CLOCK 10812
2026-01-29 03:38:40.484 [DEBUG] clck_gen.py:113 IND CLOCK 10914
2026-01-29 03:38:40.955 [DEBUG] clck_gen.py:113 IND CLOCK 11016
2026-01-29 03:38:41.432 [DEBUG] clck_gen.py:113 IND CLOCK 11118
2026-01-29 03:38:41.911 [DEBUG] clck_gen.py:113 IND CLOCK 11220
2026-01-29 03:38:42.389 [DEBUG] clck_gen.py:113 IND CLOCK 11322
2026-01-29 03:38:42.867 [DEBUG] clck_gen.py:113 IND CLOCK 11424
2026-01-29 03:38:43.346 [DEBUG] clck_gen.py:113 IND CLOCK 11526
2026-01-29 03:38:43.825 [DEBUG] clck_gen.py:113 IND CLOCK 11628
2026-01-29 03:38:44.304 [DEBUG] clck_gen.py:113 IND CLOCK 11730
2026-01-29 03:38:44.780 [DEBUG] clck_gen.py:113 IND CLOCK 11832
2026-01-29 03:38:45.251 [DEBUG] clck_gen.py:113 IND CLOCK 11934
2026-01-29 03:38:45.729 [DEBUG] clck_gen.py:113 IND CLOCK 12036
2026-01-29 03:38:46.208 [DEBUG] clck_gen.py:113 IND CLOCK 12138
2026-01-29 03:38:46.680 [DEBUG] clck_gen.py:113 IND CLOCK 12240
2026-01-29 03:38:47.150 [DEBUG] clck_gen.py:113 IND CLOCK 12342
2026-01-29 03:38:47.621 [DEBUG] clck_gen.py:113 IND CLOCK 12444
2026-01-29 03:38:48.091 [DEBUG] clck_gen.py:113 IND CLOCK 12546
2026-01-29 03:38:48.562 [DEBUG] clck_gen.py:113 IND CLOCK 12648
2026-01-29 03:38:49.033 [DEBUG] clck_gen.py:113 IND CLOCK 12750
2026-01-29 03:38:49.504 [DEBUG] clck_gen.py:113 IND CLOCK 12852
2026-01-29 03:38:49.975 [DEBUG] clck_gen.py:113 IND CLOCK 12954
2026-01-29 03:38:50.445 [DEBUG] clck_gen.py:113 IND CLOCK 13056
2026-01-29 03:38:50.916 [DEBUG] clck_gen.py:113 IND CLOCK 13158
2026-01-29 03:38:51.387 [DEBUG] clck_gen.py:113 IND CLOCK 13260
2026-01-29 03:38:51.858 [DEBUG] clck_gen.py:113 IND CLOCK 13362
2026-01-29 03:38:52.328 [DEBUG] clck_gen.py:113 IND CLOCK 13464
2026-01-29 03:38:52.799 [DEBUG] clck_gen.py:113 IND CLOCK 13566
2026-01-29 03:38:53.270 [DEBUG] clck_gen.py:113 IND CLOCK 13668
2026-01-29 03:38:53.741 [DEBUG] clck_gen.py:113 IND CLOCK 13770
2026-01-29 03:38:54.211 [DEBUG] clck_gen.py:113 IND CLOCK 13872
2026-01-29 03:38:54.682 [DEBUG] clck_gen.py:113 IND CLOCK 13974
2026-01-29 03:38:55.153 [DEBUG] clck_gen.py:113 IND CLOCK 14076
2026-01-29 03:38:55.624 [DEBUG] clck_gen.py:113 IND CLOCK 14178
2026-01-29 03:38:56.101 [DEBUG] clck_gen.py:113 IND CLOCK 14280
2026-01-29 03:38:56.580 [DEBUG] clck_gen.py:113 IND CLOCK 14382
2026-01-29 03:38:56.860 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 03:38:56.861 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:38:56.874 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 03:38:56.874 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 03:38:56.874 [INFO] transceiver.py:205 (MS@172.18.28.22:6700) Frequency hopping disabled
2026-01-29 03:38:56.888 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 03:38:56.888 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 03:38:56.888 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 03:38:56.893 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 03:38:56.893 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 03:38:56.893 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:38:56.894 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 03:38:56.895 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 03:38:56.895 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 03:38:56.895 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 03:38:56.895 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.28.22:6700) Recv POWERON CMD
2026-01-29 03:38:56.895 [INFO] ctrl_if_trx.py:109 (MS@172.18.28.22:6700) Starting transceiver...
2026-01-29 03:38:56.905 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 03:38:56.905 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 03:38:56.905 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 03:38:56.905 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 03:38:57.055 [DEBUG] clck_gen.py:113 IND CLOCK 14484
2026-01-29 03:38:57.532 [DEBUG] clck_gen.py:113 IND CLOCK 14586
2026-01-29 03:38:58.010 [DEBUG] clck_gen.py:113 IND CLOCK 14688
2026-01-29 03:38:58.488 [DEBUG] clck_gen.py:113 IND CLOCK 14790
2026-01-29 03:38:58.966 [DEBUG] clck_gen.py:113 IND CLOCK 14892
2026-01-29 03:38:59.441 [DEBUG] clck_gen.py:113 IND CLOCK 14994
2026-01-29 03:38:59.918 [DEBUG] clck_gen.py:113 IND CLOCK 15096
2026-01-29 03:39:00.396 [DEBUG] clck_gen.py:113 IND CLOCK 15198
2026-01-29 03:39:00.870 [DEBUG] clck_gen.py:113 IND CLOCK 15300
2026-01-29 03:39:01.339 [DEBUG] clck_gen.py:113 IND CLOCK 15402
2026-01-29 03:39:01.811 [DEBUG] clck_gen.py:113 IND CLOCK 15504
2026-01-29 03:39:02.288 [DEBUG] clck_gen.py:113 IND CLOCK 15606
2026-01-29 03:39:02.762 [DEBUG] clck_gen.py:113 IND CLOCK 15708
2026-01-29 03:39:03.237 [DEBUG] clck_gen.py:113 IND CLOCK 15810
2026-01-29 03:39:03.706 [DEBUG] clck_gen.py:113 IND CLOCK 15912
2026-01-29 03:39:04.175 [DEBUG] clck_gen.py:113 IND CLOCK 16014
2026-01-29 03:39:04.645 [DEBUG] clck_gen.py:113 IND CLOCK 16116
2026-01-29 03:39:05.117 [DEBUG] clck_gen.py:113 IND CLOCK 16218
2026-01-29 03:39:05.587 [DEBUG] clck_gen.py:113 IND CLOCK 16320
2026-01-29 03:39:06.058 [DEBUG] clck_gen.py:113 IND CLOCK 16422
2026-01-29 03:39:06.529 [DEBUG] clck_gen.py:113 IND CLOCK 16524
2026-01-29 03:39:07.000 [DEBUG] clck_gen.py:113 IND CLOCK 16626
2026-01-29 03:39:07.470 [DEBUG] clck_gen.py:113 IND CLOCK 16728
2026-01-29 03:39:07.941 [DEBUG] clck_gen.py:113 IND CLOCK 16830
2026-01-29 03:39:08.412 [DEBUG] clck_gen.py:113 IND CLOCK 16932
2026-01-29 03:39:08.883 [DEBUG] clck_gen.py:113 IND CLOCK 17034
2026-01-29 03:39:09.353 [DEBUG] clck_gen.py:113 IND CLOCK 17136
2026-01-29 03:39:09.829 [DEBUG] clck_gen.py:113 IND CLOCK 17238
2026-01-29 03:39:10.303 [DEBUG] clck_gen.py:113 IND CLOCK 17340
2026-01-29 03:39:10.779 [DEBUG] clck_gen.py:113 IND CLOCK 17442
2026-01-29 03:39:11.256 [DEBUG] clck_gen.py:113 IND CLOCK 17544
2026-01-29 03:39:11.733 [DEBUG] clck_gen.py:113 IND CLOCK 17646
2026-01-29 03:39:12.211 [DEBUG] clck_gen.py:113 IND CLOCK 17748
2026-01-29 03:39:12.689 [DEBUG] clck_gen.py:113 IND CLOCK 17850
2026-01-29 03:39:13.167 [DEBUG] clck_gen.py:113 IND CLOCK 17952
2026-01-29 03:39:13.641 [DEBUG] clck_gen.py:113 IND CLOCK 18054
2026-01-29 03:39:14.119 [DEBUG] clck_gen.py:113 IND CLOCK 18156
2026-01-29 03:39:14.597 [DEBUG] clck_gen.py:113 IND CLOCK 18258
2026-01-29 03:39:15.075 [DEBUG] clck_gen.py:113 IND CLOCK 18360
2026-01-29 03:39:15.552 [DEBUG] clck_gen.py:113 IND CLOCK 18462
2026-01-29 03:39:16.027 [DEBUG] clck_gen.py:113 IND CLOCK 18564
2026-01-29 03:39:16.499 [DEBUG] clck_gen.py:113 IND CLOCK 18666
2026-01-29 03:39:16.971 [DEBUG] clck_gen.py:113 IND CLOCK 18768
2026-01-29 03:39:17.444 [DEBUG] clck_gen.py:113 IND CLOCK 18870
2026-01-29 03:39:17.922 [DEBUG] clck_gen.py:113 IND CLOCK 18972
2026-01-29 03:39:18.399 [DEBUG] clck_gen.py:113 IND CLOCK 19074
2026-01-29 03:39:18.871 [DEBUG] clck_gen.py:113 IND CLOCK 19176
2026-01-29 03:39:19.346 [DEBUG] clck_gen.py:113 IND CLOCK 19278
2026-01-29 03:39:19.820 [DEBUG] clck_gen.py:113 IND CLOCK 19380
2026-01-29 03:39:20.291 [DEBUG] clck_gen.py:113 IND CLOCK 19482
2026-01-29 03:39:20.765 [DEBUG] clck_gen.py:113 IND CLOCK 19584
2026-01-29 03:39:21.240 [DEBUG] clck_gen.py:113 IND CLOCK 19686
2026-01-29 03:39:21.715 [DEBUG] clck_gen.py:113 IND CLOCK 19788
2026-01-29 03:39:22.192 [DEBUG] clck_gen.py:113 IND CLOCK 19890
2026-01-29 03:39:22.668 [DEBUG] clck_gen.py:113 IND CLOCK 19992
2026-01-29 03:39:23.141 [DEBUG] clck_gen.py:113 IND CLOCK 20094
2026-01-29 03:39:23.611 [DEBUG] clck_gen.py:113 IND CLOCK 20196
2026-01-29 03:39:24.087 [DEBUG] clck_gen.py:113 IND CLOCK 20298
2026-01-29 03:39:24.565 [DEBUG] clck_gen.py:113 IND CLOCK 20400
2026-01-29 03:39:25.041 [DEBUG] clck_gen.py:113 IND CLOCK 20502
2026-01-29 03:39:25.517 [DEBUG] clck_gen.py:113 IND CLOCK 20604
2026-01-29 03:39:25.988 [DEBUG] clck_gen.py:113 IND CLOCK 20706
2026-01-29 03:39:26.462 [DEBUG] clck_gen.py:113 IND CLOCK 20808
2026-01-29 03:39:26.939 [DEBUG] clck_gen.py:113 IND CLOCK 20910
2026-01-29 03:39:27.417 [DEBUG] clck_gen.py:113 IND CLOCK 21012
2026-01-29 03:39:27.894 [DEBUG] clck_gen.py:113 IND CLOCK 21114
2026-01-29 03:39:28.372 [DEBUG] clck_gen.py:113 IND CLOCK 21216
2026-01-29 03:39:28.849 [DEBUG] clck_gen.py:113 IND CLOCK 21318
2026-01-29 03:39:29.327 [DEBUG] clck_gen.py:113 IND CLOCK 21420
2026-01-29 03:39:29.804 [DEBUG] clck_gen.py:113 IND CLOCK 21522
2026-01-29 03:39:30.283 [DEBUG] clck_gen.py:113 IND CLOCK 21624
2026-01-29 03:39:30.760 [DEBUG] clck_gen.py:113 IND CLOCK 21726
2026-01-29 03:39:31.238 [DEBUG] clck_gen.py:113 IND CLOCK 21828
2026-01-29 03:39:31.716 [DEBUG] clck_gen.py:113 IND CLOCK 21930
2026-01-29 03:39:32.183 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 03:39:32.184 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:39:32.188 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 03:39:32.188 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 03:39:32.191 [DEBUG] clck_gen.py:113 IND CLOCK 22032
2026-01-29 03:39:32.200 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 03:39:32.200 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 03:39:32.201 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 03:39:32.206 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 03:39:32.206 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 03:39:32.206 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 03:39:32.207 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:39:32.208 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 03:39:32.208 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 03:39:32.208 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 03:39:32.208 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.28.22:6700) Recv POWERON CMD
2026-01-29 03:39:32.208 [INFO] ctrl_if_trx.py:109 (MS@172.18.28.22:6700) Starting transceiver...
2026-01-29 03:39:32.231 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.28.22:6700) Recv SETFH cmd
2026-01-29 03:39:32.231 [INFO] transceiver.py:201 (MS@172.18.28.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2026-01-29 03:39:32.231 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 03:39:32.232 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 03:39:32.663 [DEBUG] clck_gen.py:113 IND CLOCK 22134
2026-01-29 03:39:33.140 [DEBUG] clck_gen.py:113 IND CLOCK 22236
2026-01-29 03:39:33.618 [DEBUG] clck_gen.py:113 IND CLOCK 22338
2026-01-29 03:39:34.096 [DEBUG] clck_gen.py:113 IND CLOCK 22440
2026-01-29 03:39:34.573 [DEBUG] clck_gen.py:113 IND CLOCK 22542
2026-01-29 03:39:35.047 [DEBUG] clck_gen.py:113 IND CLOCK 22644
2026-01-29 03:39:35.516 [DEBUG] clck_gen.py:113 IND CLOCK 22746
2026-01-29 03:39:35.990 [DEBUG] clck_gen.py:113 IND CLOCK 22848
2026-01-29 03:39:36.468 [DEBUG] clck_gen.py:113 IND CLOCK 22950
2026-01-29 03:39:36.944 [DEBUG] clck_gen.py:113 IND CLOCK 23052
2026-01-29 03:39:37.413 [DEBUG] clck_gen.py:113 IND CLOCK 23154
2026-01-29 03:39:37.882 [DEBUG] clck_gen.py:113 IND CLOCK 23256
2026-01-29 03:39:38.354 [DEBUG] clck_gen.py:113 IND CLOCK 23358
2026-01-29 03:39:38.824 [DEBUG] clck_gen.py:113 IND CLOCK 23460
2026-01-29 03:39:39.297 [DEBUG] clck_gen.py:113 IND CLOCK 23562
2026-01-29 03:39:39.775 [DEBUG] clck_gen.py:113 IND CLOCK 23664
2026-01-29 03:39:40.252 [DEBUG] clck_gen.py:113 IND CLOCK 23766
2026-01-29 03:39:40.730 [DEBUG] clck_gen.py:113 IND CLOCK 23868
2026-01-29 03:39:41.207 [DEBUG] clck_gen.py:113 IND CLOCK 23970
2026-01-29 03:39:41.685 [DEBUG] clck_gen.py:113 IND CLOCK 24072
2026-01-29 03:39:42.163 [DEBUG] clck_gen.py:113 IND CLOCK 24174
2026-01-29 03:39:42.640 [DEBUG] clck_gen.py:113 IND CLOCK 24276
2026-01-29 03:39:43.118 [DEBUG] clck_gen.py:113 IND CLOCK 24378
2026-01-29 03:39:43.596 [DEBUG] clck_gen.py:113 IND CLOCK 24480
2026-01-29 03:39:44.071 [DEBUG] clck_gen.py:113 IND CLOCK 24582
2026-01-29 03:39:44.550 [DEBUG] clck_gen.py:113 IND CLOCK 24684
2026-01-29 03:39:45.027 [DEBUG] clck_gen.py:113 IND CLOCK 24786
2026-01-29 03:39:45.505 [DEBUG] clck_gen.py:113 IND CLOCK 24888
2026-01-29 03:39:45.984 [DEBUG] clck_gen.py:113 IND CLOCK 24990
2026-01-29 03:39:46.463 [DEBUG] clck_gen.py:113 IND CLOCK 25092
2026-01-29 03:39:46.941 [DEBUG] clck_gen.py:113 IND CLOCK 25194
2026-01-29 03:39:47.416 [DEBUG] clck_gen.py:113 IND CLOCK 25296
2026-01-29 03:39:47.895 [DEBUG] clck_gen.py:113 IND CLOCK 25398
2026-01-29 03:39:48.373 [DEBUG] clck_gen.py:113 IND CLOCK 25500
2026-01-29 03:39:48.847 [DEBUG] clck_gen.py:113 IND CLOCK 25602
2026-01-29 03:39:49.320 [DEBUG] clck_gen.py:113 IND CLOCK 25704
2026-01-29 03:39:49.792 [DEBUG] clck_gen.py:113 IND CLOCK 25806
2026-01-29 03:39:50.072 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 03:39:50.072 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:39:50.072 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:39:50.072 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:39:50.075 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 03:39:50.075 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 03:39:50.075 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 03:39:50.075 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 03:39:50.075 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.28.20:5700) Recv POWEROFF cmd
2026-01-29 03:39:50.075 [INFO] ctrl_if_trx.py:117 (BTS@172.18.28.20:5700) Stopping transceiver...
2026-01-29 03:39:50.075 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 03:39:50.075 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 03:39:50.075 [INFO] transceiver.py:205 (MS@172.18.28.22:6700) Frequency hopping disabled
2026-01-29 03:39:50.075 [INFO] transceiver.py:246 Stopping clock generator
2026-01-29 03:39:50.075 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=25869 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:39:50.076 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=25869 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:39:50.076 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=25869 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:39:50.076 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=25869 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:39:50.076 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=25869 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:39:50.076 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=25869 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:39:55.076 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.28.20:5700) Recv POWEROFF cmd
2026-01-29 03:39:55.076 [INFO] ctrl_if_trx.py:117 (BTS@172.18.28.20:5700) Stopping transceiver...
2026-01-29 03:39:55.078 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 03:39:55.080 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 03:39:55.080 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 03:39:55.080 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 03:39:55.088 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 03:39:55.089 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.28.20:5700) Recv SETFORMAT cmd
2026-01-29 03:39:55.089 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.28.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:39:55.089 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.28.20:5700) Recv SETFORMAT cmd
2026-01-29 03:39:55.089 [INFO] ctrl_if_trx.py:201 (BTS@172.18.28.20:5700) TRXD header version 1 -> 1
2026-01-29 03:39:55.091 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.28.20:5700/1) Recv RXTUNE cmd
2026-01-29 03:39:55.092 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.28.20:5700/1) Recv TXTUNE cmd
2026-01-29 03:39:55.092 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.28.20:5700/1) Recv SETFORMAT cmd
2026-01-29 03:39:55.092 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.28.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:39:55.093 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 03:39:55.093 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.28.20:5700/1) Recv NOMTXPOWER cmd
2026-01-29 03:39:55.094 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.28.20:5700/1) Recv SETFORMAT cmd
2026-01-29 03:39:55.094 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.28.20:5700/1) TRXD header version 1 -> 1
2026-01-29 03:39:55.094 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.28.20:5700/2) Recv RXTUNE cmd
2026-01-29 03:39:55.094 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.28.20:5700/2) Recv TXTUNE cmd
2026-01-29 03:39:55.094 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.28.20:5700/2) Recv SETFORMAT cmd
2026-01-29 03:39:55.094 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.28.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:39:55.095 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 03:39:55.095 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.28.20:5700/2) Recv NOMTXPOWER cmd
2026-01-29 03:39:55.095 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.28.20:5700/2) Recv SETFORMAT cmd
2026-01-29 03:39:55.095 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.28.20:5700/2) TRXD header version 1 -> 1
2026-01-29 03:39:55.095 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.28.20:5700/3) Recv RXTUNE cmd
2026-01-29 03:39:55.095 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.28.20:5700/3) Recv TXTUNE cmd
2026-01-29 03:39:55.095 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.28.20:5700/3) Recv SETFORMAT cmd
2026-01-29 03:39:55.095 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.28.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:39:55.095 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 03:39:55.095 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.28.20:5700/3) Recv NOMTXPOWER cmd
2026-01-29 03:39:55.095 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.28.20:5700/3) Recv SETFORMAT cmd
2026-01-29 03:39:55.095 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.28.20:5700/3) TRXD header version 1 -> 1
2026-01-29 03:39:55.097 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.28.20:5700) Recv RXTUNE cmd
2026-01-29 03:39:55.097 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETTSC
2026-01-29 03:39:55.097 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETTSC
2026-01-29 03:39:55.097 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETTSC
2026-01-29 03:39:55.097 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.28.20:5700) Recv TXTUNE cmd
2026-01-29 03:39:55.097 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETRXGAIN
2026-01-29 03:39:55.097 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETRXGAIN
2026-01-29 03:39:55.097 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETRXGAIN
2026-01-29 03:39:55.097 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETTSC
2026-01-29 03:39:55.097 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:39:55.097 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:39:55.097 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:39:55.097 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.28.20:5700) Recv NOMTXPOWER cmd
2026-01-29 03:39:55.097 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:39:55.097 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:39:55.097 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:39:55.097 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.28.20:5700) Recv POWERON CMD
2026-01-29 03:39:55.097 [INFO] ctrl_if_trx.py:109 (BTS@172.18.28.20:5700) Starting transceiver...
2026-01-29 03:39:55.097 [INFO] transceiver.py:243 Starting clock generator
2026-01-29 03:39:55.097 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-01-29 03:39:55.097 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:39:55.097 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:39:55.097 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:39:55.097 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETRXGAIN
2026-01-29 03:39:55.097 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:39:55.097 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:39:55.097 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:39:55.097 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:39:55.098 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:39:55.098 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:39:55.098 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:39:55.098 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:39:55.098 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:39:55.098 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:39:55.098 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:39:55.098 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:39:55.098 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:39:55.098 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:39:55.098 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:39:55.098 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:39:55.098 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:39:55.098 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 03:39:55.098 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:39:55.098 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:39:55.098 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:39:55.098 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:39:55.098 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:39:55.098 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:39:55.098 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 03:39:55.098 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 03:39:55.098 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 03:39:55.098 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.28.20:5700) Recv POWEROFF cmd
2026-01-29 03:39:55.098 [INFO] ctrl_if_trx.py:117 (BTS@172.18.28.20:5700) Stopping transceiver...
2026-01-29 03:39:55.098 [INFO] transceiver.py:246 Stopping clock generator
2026-01-29 03:40:00.102 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.28.20:5700) Recv POWEROFF cmd
2026-01-29 03:40:00.102 [INFO] ctrl_if_trx.py:117 (BTS@172.18.28.20:5700) Stopping transceiver...
2026-01-29 03:40:00.104 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 03:40:00.105 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 03:40:00.105 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 03:40:00.105 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 03:40:00.114 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 03:40:00.115 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.28.20:5700) Recv SETFORMAT cmd
2026-01-29 03:40:00.115 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.28.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:40:00.115 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.28.20:5700) Recv SETFORMAT cmd
2026-01-29 03:40:00.115 [INFO] ctrl_if_trx.py:201 (BTS@172.18.28.20:5700) TRXD header version 1 -> 1
2026-01-29 03:40:00.117 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.28.20:5700/1) Recv RXTUNE cmd
2026-01-29 03:40:00.117 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.28.20:5700/1) Recv TXTUNE cmd
2026-01-29 03:40:00.117 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.28.20:5700/1) Recv SETFORMAT cmd
2026-01-29 03:40:00.117 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.28.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:40:00.117 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 03:40:00.118 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.28.20:5700/1) Recv NOMTXPOWER cmd
2026-01-29 03:40:00.118 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.28.20:5700/1) Recv SETFORMAT cmd
2026-01-29 03:40:00.118 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.28.20:5700/1) TRXD header version 1 -> 1
2026-01-29 03:40:00.119 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.28.20:5700/2) Recv RXTUNE cmd
2026-01-29 03:40:00.119 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.28.20:5700/2) Recv TXTUNE cmd
2026-01-29 03:40:00.119 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.28.20:5700/2) Recv SETFORMAT cmd
2026-01-29 03:40:00.119 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.28.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:40:00.120 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 03:40:00.120 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.28.20:5700/2) Recv NOMTXPOWER cmd
2026-01-29 03:40:00.120 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.28.20:5700/2) Recv SETFORMAT cmd
2026-01-29 03:40:00.120 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.28.20:5700/2) TRXD header version 1 -> 1
2026-01-29 03:40:00.121 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.28.20:5700/3) Recv RXTUNE cmd
2026-01-29 03:40:00.121 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.28.20:5700/3) Recv TXTUNE cmd
2026-01-29 03:40:00.121 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.28.20:5700/3) Recv SETFORMAT cmd
2026-01-29 03:40:00.121 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.28.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:40:00.121 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.28.20:5700/3) Recv NOMTXPOWER cmd
2026-01-29 03:40:00.121 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 03:40:00.121 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.28.20:5700/3) Recv SETFORMAT cmd
2026-01-29 03:40:00.121 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.28.20:5700/3) TRXD header version 1 -> 1
2026-01-29 03:40:00.123 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.28.20:5700) Recv RXTUNE cmd
2026-01-29 03:40:00.123 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETTSC
2026-01-29 03:40:00.123 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETTSC
2026-01-29 03:40:00.123 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETTSC
2026-01-29 03:40:00.123 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.28.20:5700) Recv TXTUNE cmd
2026-01-29 03:40:00.123 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETRXGAIN
2026-01-29 03:40:00.123 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETRXGAIN
2026-01-29 03:40:00.123 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETRXGAIN
2026-01-29 03:40:00.123 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETTSC
2026-01-29 03:40:00.123 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:40:00.123 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:40:00.123 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.28.20:5700) Recv NOMTXPOWER cmd
2026-01-29 03:40:00.123 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:40:00.123 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:40:00.123 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:40:00.123 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.28.20:5700) Recv POWERON CMD
2026-01-29 03:40:00.123 [INFO] ctrl_if_trx.py:109 (BTS@172.18.28.20:5700) Starting transceiver...
2026-01-29 03:40:00.123 [INFO] transceiver.py:243 Starting clock generator
2026-01-29 03:40:00.123 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-01-29 03:40:00.123 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:40:00.123 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:40:00.123 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:40:00.123 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETRXGAIN
2026-01-29 03:40:00.124 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:40:00.124 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:40:00.124 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:40:00.124 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:40:00.124 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:40:00.124 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:40:00.124 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:40:00.124 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:40:00.124 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:40:00.124 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:40:00.124 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:40:00.124 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:40:00.124 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:40:00.124 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:40:00.124 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:40:00.124 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:40:00.124 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:40:00.124 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:40:00.124 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:40:00.124 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:40:00.124 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:40:00.124 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:40:00.124 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:40:00.124 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:40:00.128 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-01-29 03:40:00.611 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-01-29 03:40:00.644 [DEBUG] fake_trx.py:278 (BTS@172.18.28.20:5700) Recv FAKE_TOA cmd
2026-01-29 03:40:00.645 [DEBUG] fake_trx.py:297 (BTS@172.18.28.20:5700) Recv FAKE_RSSI cmd
2026-01-29 03:40:00.646 [DEBUG] fake_trx.py:322 (BTS@172.18.28.20:5700) Recv FAKE_CI cmd
2026-01-29 03:40:00.646 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:40:00.665 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 03:40:00.665 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 03:40:00.665 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 03:40:00.675 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 03:40:00.675 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 03:40:00.676 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 03:40:00.676 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:40:00.678 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 03:40:00.678 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 03:40:00.678 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 03:40:00.678 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.28.22:6700) Recv POWERON CMD
2026-01-29 03:40:00.678 [INFO] ctrl_if_trx.py:109 (MS@172.18.28.22:6700) Starting transceiver...
2026-01-29 03:40:00.702 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 03:40:00.702 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 03:40:00.703 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 03:40:00.703 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 03:40:01.088 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-01-29 03:40:01.126 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 03:40:01.126 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:40:01.126 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:40:01.127 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:40:01.566 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-01-29 03:40:02.043 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-01-29 03:40:02.127 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 03:40:02.127 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:40:02.127 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:40:02.128 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:40:02.148 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 03:40:02.150 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:40:02.153 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 03:40:02.153 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 03:40:02.170 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 03:40:02.171 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 03:40:02.171 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 03:40:02.177 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 03:40:02.177 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 03:40:02.177 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 03:40:02.177 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:40:02.179 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 03:40:02.179 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 03:40:02.179 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 03:40:02.179 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.28.22:6700) Recv POWERON CMD
2026-01-29 03:40:02.179 [INFO] ctrl_if_trx.py:109 (MS@172.18.28.22:6700) Starting transceiver...
2026-01-29 03:40:02.227 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.28.22:6700) Recv SETFH cmd
2026-01-29 03:40:02.228 [INFO] transceiver.py:201 (MS@172.18.28.22:6700) Frequency hopping configured: hsn=5, maio=0, ma_len=4
2026-01-29 03:40:02.228 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 03:40:02.228 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 03:40:02.515 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-01-29 03:40:02.986 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-01-29 03:40:03.127 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 03:40:03.128 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:40:03.128 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:40:03.128 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:40:03.457 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-01-29 03:40:03.934 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-01-29 03:40:04.128 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:40:04.129 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 03:40:04.129 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:40:04.129 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:40:04.403 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-01-29 03:40:04.510 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 03:40:04.511 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:40:04.515 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 03:40:04.515 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 03:40:04.515 [INFO] transceiver.py:205 (MS@172.18.28.22:6700) Frequency hopping disabled
2026-01-29 03:40:04.535 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 03:40:04.535 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 03:40:04.535 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 03:40:04.541 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 03:40:04.542 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 03:40:04.542 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 03:40:04.542 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:40:04.543 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 03:40:04.543 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 03:40:04.543 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 03:40:04.543 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.28.22:6700) Recv POWERON CMD
2026-01-29 03:40:04.543 [INFO] ctrl_if_trx.py:109 (MS@172.18.28.22:6700) Starting transceiver...
2026-01-29 03:40:04.584 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 03:40:04.584 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 03:40:04.584 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 03:40:04.584 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 03:40:04.877 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-01-29 03:40:05.130 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:40:05.130 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:40:05.130 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 03:40:05.130 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:40:05.354 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-01-29 03:40:05.832 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-01-29 03:40:06.309 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-01-29 03:40:06.788 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-01-29 03:40:07.266 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-01-29 03:40:07.744 [DEBUG] clck_gen.py:113 IND CLOCK 1632
2026-01-29 03:40:07.900 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 03:40:07.900 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:40:07.904 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 03:40:07.904 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 03:40:07.916 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 03:40:07.916 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 03:40:07.916 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 03:40:07.922 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 03:40:07.922 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 03:40:07.922 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 03:40:07.923 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:40:07.924 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 03:40:07.924 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 03:40:07.924 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 03:40:07.924 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.28.22:6700) Recv POWERON CMD
2026-01-29 03:40:07.924 [INFO] ctrl_if_trx.py:109 (MS@172.18.28.22:6700) Starting transceiver...
2026-01-29 03:40:07.978 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.28.22:6700) Recv SETFH cmd
2026-01-29 03:40:07.979 [INFO] transceiver.py:201 (MS@172.18.28.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2026-01-29 03:40:07.979 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 03:40:07.979 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 03:40:08.216 [DEBUG] clck_gen.py:113 IND CLOCK 1734
2026-01-29 03:40:08.691 [DEBUG] clck_gen.py:113 IND CLOCK 1836
2026-01-29 03:40:09.169 [DEBUG] clck_gen.py:113 IND CLOCK 1938
2026-01-29 03:40:09.252 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 03:40:09.252 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 03:40:09.253 [INFO] transceiver.py:205 (MS@172.18.28.22:6700) Frequency hopping disabled
2026-01-29 03:40:09.256 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 03:40:09.256 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:40:09.256 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:40:09.256 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:40:09.257 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 03:40:09.257 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 03:40:09.257 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 03:40:09.257 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 03:40:09.257 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.28.20:5700) Recv POWEROFF cmd
2026-01-29 03:40:09.257 [INFO] ctrl_if_trx.py:117 (BTS@172.18.28.20:5700) Stopping transceiver...
2026-01-29 03:40:09.257 [INFO] transceiver.py:246 Stopping clock generator
2026-01-29 03:40:09.257 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=1959 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:40:09.257 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=1959 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:40:09.257 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=1959 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:40:09.257 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=1959 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:40:09.257 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=1959 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:40:09.257 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=1959 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:40:09.257 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=1959 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:40:14.280 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.28.20:5700) Recv POWEROFF cmd
2026-01-29 03:40:14.280 [INFO] ctrl_if_trx.py:117 (BTS@172.18.28.20:5700) Stopping transceiver...
2026-01-29 03:40:14.280 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 03:40:14.280 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 03:40:14.280 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 03:40:14.280 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 03:40:14.287 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 03:40:14.288 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.28.20:5700) Recv SETFORMAT cmd
2026-01-29 03:40:14.288 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.28.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:40:14.288 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.28.20:5700) Recv SETFORMAT cmd
2026-01-29 03:40:14.288 [INFO] ctrl_if_trx.py:201 (BTS@172.18.28.20:5700) TRXD header version 1 -> 1
2026-01-29 03:40:14.290 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.28.20:5700/1) Recv RXTUNE cmd
2026-01-29 03:40:14.290 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.28.20:5700/1) Recv TXTUNE cmd
2026-01-29 03:40:14.290 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.28.20:5700/1) Recv SETFORMAT cmd
2026-01-29 03:40:14.290 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.28.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:40:14.290 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 03:40:14.290 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.28.20:5700/1) Recv NOMTXPOWER cmd
2026-01-29 03:40:14.290 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.28.20:5700/1) Recv SETFORMAT cmd
2026-01-29 03:40:14.290 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.28.20:5700/1) TRXD header version 1 -> 1
2026-01-29 03:40:14.291 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.28.20:5700/2) Recv RXTUNE cmd
2026-01-29 03:40:14.291 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.28.20:5700/2) Recv TXTUNE cmd
2026-01-29 03:40:14.291 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.28.20:5700/2) Recv SETFORMAT cmd
2026-01-29 03:40:14.291 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.28.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:40:14.291 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 03:40:14.292 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.28.20:5700/2) Recv NOMTXPOWER cmd
2026-01-29 03:40:14.292 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.28.20:5700/2) Recv SETFORMAT cmd
2026-01-29 03:40:14.292 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.28.20:5700/2) TRXD header version 1 -> 1
2026-01-29 03:40:14.293 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.28.20:5700/3) Recv RXTUNE cmd
2026-01-29 03:40:14.293 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.28.20:5700/3) Recv TXTUNE cmd
2026-01-29 03:40:14.293 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.28.20:5700/3) Recv SETFORMAT cmd
2026-01-29 03:40:14.293 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.28.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:40:14.293 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 03:40:14.293 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.28.20:5700/3) Recv NOMTXPOWER cmd
2026-01-29 03:40:14.293 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.28.20:5700/3) Recv SETFORMAT cmd
2026-01-29 03:40:14.293 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.28.20:5700/3) TRXD header version 1 -> 1
2026-01-29 03:40:14.295 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.28.20:5700) Recv RXTUNE cmd
2026-01-29 03:40:14.295 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETTSC
2026-01-29 03:40:14.295 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETTSC
2026-01-29 03:40:14.295 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETTSC
2026-01-29 03:40:14.295 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.28.20:5700) Recv TXTUNE cmd
2026-01-29 03:40:14.295 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETRXGAIN
2026-01-29 03:40:14.295 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETRXGAIN
2026-01-29 03:40:14.295 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETRXGAIN
2026-01-29 03:40:14.295 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETTSC
2026-01-29 03:40:14.295 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:40:14.295 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:40:14.295 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:40:14.295 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.28.20:5700) Recv NOMTXPOWER cmd
2026-01-29 03:40:14.295 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:40:14.295 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:40:14.295 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:40:14.295 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.28.20:5700) Recv POWERON CMD
2026-01-29 03:40:14.295 [INFO] ctrl_if_trx.py:109 (BTS@172.18.28.20:5700) Starting transceiver...
2026-01-29 03:40:14.295 [INFO] transceiver.py:243 Starting clock generator
2026-01-29 03:40:14.295 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-01-29 03:40:14.295 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:40:14.295 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:40:14.295 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:40:14.295 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETRXGAIN
2026-01-29 03:40:14.296 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:40:14.296 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:40:14.296 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:40:14.296 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:40:14.296 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:40:14.296 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:40:14.296 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:40:14.296 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:40:14.296 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:40:14.296 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:40:14.296 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:40:14.296 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:40:14.296 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:40:14.296 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:40:14.296 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:40:14.296 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:40:14.296 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:40:14.296 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:40:14.296 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:40:14.296 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:40:14.296 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:40:14.296 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:40:14.296 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:40:14.300 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-01-29 03:40:14.775 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-01-29 03:40:14.821 [DEBUG] fake_trx.py:278 (BTS@172.18.28.20:5700) Recv FAKE_TOA cmd
2026-01-29 03:40:14.823 [DEBUG] fake_trx.py:297 (BTS@172.18.28.20:5700) Recv FAKE_RSSI cmd
2026-01-29 03:40:14.824 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:40:14.824 [DEBUG] fake_trx.py:322 (BTS@172.18.28.20:5700) Recv FAKE_CI cmd
2026-01-29 03:40:14.839 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 03:40:14.839 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 03:40:14.839 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 03:40:14.854 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 03:40:14.854 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 03:40:14.854 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 03:40:14.856 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:40:14.859 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 03:40:14.860 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 03:40:14.860 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 03:40:14.860 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.28.22:6700) Recv POWERON CMD
2026-01-29 03:40:14.860 [INFO] ctrl_if_trx.py:109 (MS@172.18.28.22:6700) Starting transceiver...
2026-01-29 03:40:14.866 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 03:40:14.866 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 03:40:14.866 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 03:40:14.866 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 03:40:15.252 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-01-29 03:40:15.298 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:40:15.299 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 03:40:15.299 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:40:15.300 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:40:15.730 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-01-29 03:40:16.207 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-01-29 03:40:16.299 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 03:40:16.299 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:40:16.300 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:40:16.301 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:40:16.685 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-01-29 03:40:17.163 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-01-29 03:40:17.300 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:40:17.301 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:40:17.301 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 03:40:17.301 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:40:17.640 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-01-29 03:40:18.118 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-01-29 03:40:18.302 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 03:40:18.302 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:40:18.302 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:40:18.302 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:40:18.595 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-01-29 03:40:19.074 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-01-29 03:40:19.302 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 03:40:19.302 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:40:19.303 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:40:19.303 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:40:19.551 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-01-29 03:40:20.029 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-01-29 03:40:20.507 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-01-29 03:40:20.984 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-01-29 03:40:21.461 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-01-29 03:40:21.938 [DEBUG] clck_gen.py:113 IND CLOCK 1632
2026-01-29 03:40:22.412 [DEBUG] clck_gen.py:113 IND CLOCK 1734
2026-01-29 03:40:22.882 [DEBUG] clck_gen.py:113 IND CLOCK 1836
2026-01-29 03:40:23.355 [DEBUG] clck_gen.py:113 IND CLOCK 1938
2026-01-29 03:40:23.827 [DEBUG] clck_gen.py:113 IND CLOCK 2040
2026-01-29 03:40:24.304 [DEBUG] clck_gen.py:113 IND CLOCK 2142
2026-01-29 03:40:24.782 [DEBUG] clck_gen.py:113 IND CLOCK 2244
2026-01-29 03:40:25.260 [DEBUG] clck_gen.py:113 IND CLOCK 2346
2026-01-29 03:40:25.738 [DEBUG] clck_gen.py:113 IND CLOCK 2448
2026-01-29 03:40:26.216 [DEBUG] clck_gen.py:113 IND CLOCK 2550
2026-01-29 03:40:26.693 [DEBUG] clck_gen.py:113 IND CLOCK 2652
2026-01-29 03:40:27.170 [DEBUG] clck_gen.py:113 IND CLOCK 2754
2026-01-29 03:40:27.648 [DEBUG] clck_gen.py:113 IND CLOCK 2856
2026-01-29 03:40:28.126 [DEBUG] clck_gen.py:113 IND CLOCK 2958
2026-01-29 03:40:28.604 [DEBUG] clck_gen.py:113 IND CLOCK 3060
2026-01-29 03:40:29.082 [DEBUG] clck_gen.py:113 IND CLOCK 3162
2026-01-29 03:40:29.561 [DEBUG] clck_gen.py:113 IND CLOCK 3264
2026-01-29 03:40:29.846 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 03:40:29.847 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:40:29.849 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 03:40:29.849 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 03:40:29.858 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 03:40:29.858 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 03:40:29.858 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 03:40:29.864 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 03:40:29.864 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 03:40:29.864 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 03:40:29.865 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:40:29.866 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 03:40:29.866 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 03:40:29.866 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 03:40:29.866 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.28.22:6700) Recv POWERON CMD
2026-01-29 03:40:29.866 [INFO] ctrl_if_trx.py:109 (MS@172.18.28.22:6700) Starting transceiver...
2026-01-29 03:40:29.885 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.28.22:6700) Recv SETFH cmd
2026-01-29 03:40:29.885 [INFO] transceiver.py:201 (MS@172.18.28.22:6700) Frequency hopping configured: hsn=5, maio=0, ma_len=4
2026-01-29 03:40:29.885 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 03:40:29.885 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 03:40:30.036 [DEBUG] clck_gen.py:113 IND CLOCK 3366
2026-01-29 03:40:30.505 [DEBUG] clck_gen.py:113 IND CLOCK 3468
2026-01-29 03:40:30.974 [DEBUG] clck_gen.py:113 IND CLOCK 3570
2026-01-29 03:40:31.450 [DEBUG] clck_gen.py:113 IND CLOCK 3672
2026-01-29 03:40:31.927 [DEBUG] clck_gen.py:113 IND CLOCK 3774
2026-01-29 03:40:32.406 [DEBUG] clck_gen.py:113 IND CLOCK 3876
2026-01-29 03:40:32.885 [DEBUG] clck_gen.py:113 IND CLOCK 3978
2026-01-29 03:40:33.363 [DEBUG] clck_gen.py:113 IND CLOCK 4080
2026-01-29 03:40:33.841 [DEBUG] clck_gen.py:113 IND CLOCK 4182
2026-01-29 03:40:34.320 [DEBUG] clck_gen.py:113 IND CLOCK 4284
2026-01-29 03:40:34.798 [DEBUG] clck_gen.py:113 IND CLOCK 4386
2026-01-29 03:40:35.277 [DEBUG] clck_gen.py:113 IND CLOCK 4488
2026-01-29 03:40:35.750 [DEBUG] clck_gen.py:113 IND CLOCK 4590
2026-01-29 03:40:36.219 [DEBUG] clck_gen.py:113 IND CLOCK 4692
2026-01-29 03:40:36.690 [DEBUG] clck_gen.py:113 IND CLOCK 4794
2026-01-29 03:40:37.164 [DEBUG] clck_gen.py:113 IND CLOCK 4896
2026-01-29 03:40:37.643 [DEBUG] clck_gen.py:113 IND CLOCK 4998
2026-01-29 03:40:38.119 [DEBUG] clck_gen.py:113 IND CLOCK 5100
2026-01-29 03:40:38.592 [DEBUG] clck_gen.py:113 IND CLOCK 5202
2026-01-29 03:40:39.062 [DEBUG] clck_gen.py:113 IND CLOCK 5304
2026-01-29 03:40:39.533 [DEBUG] clck_gen.py:113 IND CLOCK 5406
2026-01-29 03:40:40.003 [DEBUG] clck_gen.py:113 IND CLOCK 5508
2026-01-29 03:40:40.474 [DEBUG] clck_gen.py:113 IND CLOCK 5610
2026-01-29 03:40:40.944 [DEBUG] clck_gen.py:113 IND CLOCK 5712
2026-01-29 03:40:41.415 [DEBUG] clck_gen.py:113 IND CLOCK 5814
2026-01-29 03:40:41.886 [DEBUG] clck_gen.py:113 IND CLOCK 5916
2026-01-29 03:40:42.357 [DEBUG] clck_gen.py:113 IND CLOCK 6018
2026-01-29 03:40:42.833 [DEBUG] clck_gen.py:113 IND CLOCK 6120
2026-01-29 03:40:43.305 [DEBUG] clck_gen.py:113 IND CLOCK 6222
2026-01-29 03:40:43.776 [DEBUG] clck_gen.py:113 IND CLOCK 6324
2026-01-29 03:40:44.246 [DEBUG] clck_gen.py:113 IND CLOCK 6426
2026-01-29 03:40:44.717 [DEBUG] clck_gen.py:113 IND CLOCK 6528
2026-01-29 03:40:45.056 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 03:40:45.058 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:40:45.062 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 03:40:45.062 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 03:40:45.062 [INFO] transceiver.py:205 (MS@172.18.28.22:6700) Frequency hopping disabled
2026-01-29 03:40:45.079 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 03:40:45.079 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 03:40:45.079 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 03:40:45.085 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 03:40:45.085 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 03:40:45.085 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 03:40:45.085 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:40:45.086 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 03:40:45.086 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 03:40:45.087 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 03:40:45.087 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.28.22:6700) Recv POWERON CMD
2026-01-29 03:40:45.087 [INFO] ctrl_if_trx.py:109 (MS@172.18.28.22:6700) Starting transceiver...
2026-01-29 03:40:45.136 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 03:40:45.136 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 03:40:45.136 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 03:40:45.137 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 03:40:45.188 [DEBUG] clck_gen.py:113 IND CLOCK 6630
2026-01-29 03:40:45.659 [DEBUG] clck_gen.py:113 IND CLOCK 6732
2026-01-29 03:40:46.136 [DEBUG] clck_gen.py:113 IND CLOCK 6834
2026-01-29 03:40:46.608 [DEBUG] clck_gen.py:113 IND CLOCK 6936
2026-01-29 03:40:47.078 [DEBUG] clck_gen.py:113 IND CLOCK 7038
2026-01-29 03:40:47.556 [DEBUG] clck_gen.py:113 IND CLOCK 7140
2026-01-29 03:40:48.033 [DEBUG] clck_gen.py:113 IND CLOCK 7242
2026-01-29 03:40:48.506 [DEBUG] clck_gen.py:113 IND CLOCK 7344
2026-01-29 03:40:48.984 [DEBUG] clck_gen.py:113 IND CLOCK 7446
2026-01-29 03:40:49.461 [DEBUG] clck_gen.py:113 IND CLOCK 7548
2026-01-29 03:40:49.939 [DEBUG] clck_gen.py:113 IND CLOCK 7650
2026-01-29 03:40:50.416 [DEBUG] clck_gen.py:113 IND CLOCK 7752
2026-01-29 03:40:50.893 [DEBUG] clck_gen.py:113 IND CLOCK 7854
2026-01-29 03:40:51.370 [DEBUG] clck_gen.py:113 IND CLOCK 7956
2026-01-29 03:40:51.848 [DEBUG] clck_gen.py:113 IND CLOCK 8058
2026-01-29 03:40:52.322 [DEBUG] clck_gen.py:113 IND CLOCK 8160
2026-01-29 03:40:52.801 [DEBUG] clck_gen.py:113 IND CLOCK 8262
2026-01-29 03:40:53.279 [DEBUG] clck_gen.py:113 IND CLOCK 8364
2026-01-29 03:40:53.755 [DEBUG] clck_gen.py:113 IND CLOCK 8466
2026-01-29 03:40:54.234 [DEBUG] clck_gen.py:113 IND CLOCK 8568
2026-01-29 03:40:54.713 [DEBUG] clck_gen.py:113 IND CLOCK 8670
2026-01-29 03:40:55.190 [DEBUG] clck_gen.py:113 IND CLOCK 8772
2026-01-29 03:40:55.663 [DEBUG] clck_gen.py:113 IND CLOCK 8874
2026-01-29 03:40:56.141 [DEBUG] clck_gen.py:113 IND CLOCK 8976
2026-01-29 03:40:56.620 [DEBUG] clck_gen.py:113 IND CLOCK 9078
2026-01-29 03:40:57.097 [DEBUG] clck_gen.py:113 IND CLOCK 9180
2026-01-29 03:40:57.574 [DEBUG] clck_gen.py:113 IND CLOCK 9282
2026-01-29 03:40:58.050 [DEBUG] clck_gen.py:113 IND CLOCK 9384
2026-01-29 03:40:58.527 [DEBUG] clck_gen.py:113 IND CLOCK 9486
2026-01-29 03:40:59.004 [DEBUG] clck_gen.py:113 IND CLOCK 9588
2026-01-29 03:40:59.441 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 03:40:59.442 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:40:59.446 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 03:40:59.446 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 03:40:59.464 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 03:40:59.464 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 03:40:59.465 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 03:40:59.471 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 03:40:59.471 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 03:40:59.471 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 03:40:59.471 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:40:59.473 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 03:40:59.473 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 03:40:59.473 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 03:40:59.473 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.28.22:6700) Recv POWERON CMD
2026-01-29 03:40:59.473 [INFO] ctrl_if_trx.py:109 (MS@172.18.28.22:6700) Starting transceiver...
2026-01-29 03:40:59.481 [DEBUG] clck_gen.py:113 IND CLOCK 9690
2026-01-29 03:40:59.527 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.28.22:6700) Recv SETFH cmd
2026-01-29 03:40:59.527 [INFO] transceiver.py:201 (MS@172.18.28.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2026-01-29 03:40:59.528 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 03:40:59.528 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 03:40:59.958 [DEBUG] clck_gen.py:113 IND CLOCK 9792
2026-01-29 03:41:00.436 [DEBUG] clck_gen.py:113 IND CLOCK 9894
2026-01-29 03:41:00.913 [DEBUG] clck_gen.py:113 IND CLOCK 9996
2026-01-29 03:41:01.392 [DEBUG] clck_gen.py:113 IND CLOCK 10098
2026-01-29 03:41:01.869 [DEBUG] clck_gen.py:113 IND CLOCK 10200
2026-01-29 03:41:02.338 [DEBUG] clck_gen.py:113 IND CLOCK 10302
2026-01-29 03:41:02.729 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 03:41:02.729 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 03:41:02.730 [INFO] transceiver.py:205 (MS@172.18.28.22:6700) Frequency hopping disabled
2026-01-29 03:41:02.731 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 03:41:02.731 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:41:02.731 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:41:02.731 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:41:02.731 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 03:41:02.731 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 03:41:02.731 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 03:41:02.731 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 03:41:02.731 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.28.20:5700) Recv POWEROFF cmd
2026-01-29 03:41:02.731 [INFO] ctrl_if_trx.py:117 (BTS@172.18.28.20:5700) Stopping transceiver...
2026-01-29 03:41:02.732 [INFO] transceiver.py:246 Stopping clock generator
2026-01-29 03:41:07.733 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.28.20:5700) Recv POWEROFF cmd
2026-01-29 03:41:07.734 [INFO] ctrl_if_trx.py:117 (BTS@172.18.28.20:5700) Stopping transceiver...
2026-01-29 03:41:07.735 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 03:41:07.736 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 03:41:07.737 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 03:41:07.738 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 03:41:07.747 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 03:41:07.747 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.28.20:5700) Recv SETFORMAT cmd
2026-01-29 03:41:07.747 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.28.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:41:07.748 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.28.20:5700) Recv SETFORMAT cmd
2026-01-29 03:41:07.748 [INFO] ctrl_if_trx.py:201 (BTS@172.18.28.20:5700) TRXD header version 1 -> 1
2026-01-29 03:41:07.750 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.28.20:5700/1) Recv RXTUNE cmd
2026-01-29 03:41:07.751 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.28.20:5700/1) Recv TXTUNE cmd
2026-01-29 03:41:07.751 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.28.20:5700/1) Recv SETFORMAT cmd
2026-01-29 03:41:07.751 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.28.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:41:07.751 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 03:41:07.751 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.28.20:5700/1) Recv NOMTXPOWER cmd
2026-01-29 03:41:07.751 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.28.20:5700/1) Recv SETFORMAT cmd
2026-01-29 03:41:07.751 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.28.20:5700/1) TRXD header version 1 -> 1
2026-01-29 03:41:07.753 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.28.20:5700/2) Recv RXTUNE cmd
2026-01-29 03:41:07.753 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.28.20:5700/2) Recv TXTUNE cmd
2026-01-29 03:41:07.753 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.28.20:5700/2) Recv SETFORMAT cmd
2026-01-29 03:41:07.753 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.28.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:41:07.753 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 03:41:07.754 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.28.20:5700/2) Recv NOMTXPOWER cmd
2026-01-29 03:41:07.754 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.28.20:5700/2) Recv SETFORMAT cmd
2026-01-29 03:41:07.754 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.28.20:5700/2) TRXD header version 1 -> 1
2026-01-29 03:41:07.756 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.28.20:5700/3) Recv RXTUNE cmd
2026-01-29 03:41:07.756 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.28.20:5700/3) Recv TXTUNE cmd
2026-01-29 03:41:07.756 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.28.20:5700/3) Recv SETFORMAT cmd
2026-01-29 03:41:07.756 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.28.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:41:07.756 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 03:41:07.756 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.28.20:5700/3) Recv NOMTXPOWER cmd
2026-01-29 03:41:07.756 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.28.20:5700/3) Recv SETFORMAT cmd
2026-01-29 03:41:07.756 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.28.20:5700/3) TRXD header version 1 -> 1
2026-01-29 03:41:07.760 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.28.20:5700) Recv RXTUNE cmd
2026-01-29 03:41:07.760 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETTSC
2026-01-29 03:41:07.761 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETTSC
2026-01-29 03:41:07.761 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETTSC
2026-01-29 03:41:07.761 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.28.20:5700) Recv TXTUNE cmd
2026-01-29 03:41:07.761 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETRXGAIN
2026-01-29 03:41:07.761 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETRXGAIN
2026-01-29 03:41:07.761 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETRXGAIN
2026-01-29 03:41:07.761 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETTSC
2026-01-29 03:41:07.761 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:41:07.761 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:41:07.761 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:41:07.761 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.28.20:5700) Recv NOMTXPOWER cmd
2026-01-29 03:41:07.761 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:41:07.761 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:41:07.761 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:41:07.761 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.28.20:5700) Recv POWERON CMD
2026-01-29 03:41:07.761 [INFO] ctrl_if_trx.py:109 (BTS@172.18.28.20:5700) Starting transceiver...
2026-01-29 03:41:07.761 [INFO] transceiver.py:243 Starting clock generator
2026-01-29 03:41:07.762 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-01-29 03:41:07.762 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:41:07.762 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:41:07.762 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:41:07.762 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETRXGAIN
2026-01-29 03:41:07.762 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:41:07.762 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:41:07.762 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:41:07.762 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:41:07.763 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:41:07.763 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:41:07.763 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:41:07.763 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:41:07.763 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:41:07.763 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:41:07.763 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:41:07.763 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:41:07.763 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:41:07.763 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:41:07.763 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:41:07.763 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:41:07.763 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:41:07.763 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:41:07.763 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:41:07.763 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:41:07.763 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:41:07.763 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:41:07.764 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:41:07.766 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-01-29 03:41:08.238 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-01-29 03:41:08.300 [DEBUG] fake_trx.py:278 (BTS@172.18.28.20:5700) Recv FAKE_TOA cmd
2026-01-29 03:41:08.301 [DEBUG] fake_trx.py:297 (BTS@172.18.28.20:5700) Recv FAKE_RSSI cmd
2026-01-29 03:41:08.303 [DEBUG] fake_trx.py:322 (BTS@172.18.28.20:5700) Recv FAKE_CI cmd
2026-01-29 03:41:08.303 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:41:08.324 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 03:41:08.324 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 03:41:08.324 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 03:41:08.335 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 03:41:08.335 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 03:41:08.335 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 03:41:08.337 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:41:08.338 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 03:41:08.338 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 03:41:08.339 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 03:41:08.339 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.28.22:6700) Recv POWERON CMD
2026-01-29 03:41:08.339 [INFO] ctrl_if_trx.py:109 (MS@172.18.28.22:6700) Starting transceiver...
2026-01-29 03:41:08.373 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 03:41:08.373 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 03:41:08.373 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 03:41:08.373 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 03:41:08.707 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-01-29 03:41:08.766 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 03:41:08.767 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:41:08.769 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:41:08.773 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:41:09.176 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-01-29 03:41:09.653 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-01-29 03:41:09.767 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 03:41:09.768 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:41:09.770 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:41:09.774 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:41:10.126 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-01-29 03:41:10.601 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-01-29 03:41:10.768 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 03:41:10.768 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:41:10.771 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:41:10.775 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:41:11.074 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-01-29 03:41:11.549 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-01-29 03:41:11.769 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 03:41:11.769 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:41:11.771 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:41:11.776 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:41:12.026 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-01-29 03:41:12.503 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-01-29 03:41:12.769 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:41:12.770 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 03:41:12.772 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:41:12.776 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:41:12.981 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-01-29 03:41:13.458 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-01-29 03:41:13.935 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-01-29 03:41:14.413 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-01-29 03:41:14.892 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-01-29 03:41:15.370 [DEBUG] clck_gen.py:113 IND CLOCK 1632
2026-01-29 03:41:15.845 [DEBUG] clck_gen.py:113 IND CLOCK 1734
2026-01-29 03:41:16.323 [DEBUG] clck_gen.py:113 IND CLOCK 1836
2026-01-29 03:41:16.801 [DEBUG] clck_gen.py:113 IND CLOCK 1938
2026-01-29 03:41:17.276 [DEBUG] clck_gen.py:113 IND CLOCK 2040
2026-01-29 03:41:17.752 [DEBUG] clck_gen.py:113 IND CLOCK 2142
2026-01-29 03:41:18.225 [DEBUG] clck_gen.py:113 IND CLOCK 2244
2026-01-29 03:41:18.698 [DEBUG] clck_gen.py:113 IND CLOCK 2346
2026-01-29 03:41:18.897 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 03:41:18.897 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:41:18.900 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 03:41:18.900 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 03:41:18.917 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 03:41:18.917 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 03:41:18.917 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 03:41:18.923 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 03:41:18.923 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 03:41:18.923 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 03:41:18.924 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:41:18.925 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 03:41:18.925 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 03:41:18.925 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 03:41:18.925 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.28.22:6700) Recv POWERON CMD
2026-01-29 03:41:18.925 [INFO] ctrl_if_trx.py:109 (MS@172.18.28.22:6700) Starting transceiver...
2026-01-29 03:41:18.975 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.28.22:6700) Recv SETFH cmd
2026-01-29 03:41:18.975 [INFO] transceiver.py:201 (MS@172.18.28.22:6700) Frequency hopping configured: hsn=5, maio=0, ma_len=4
2026-01-29 03:41:18.975 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 03:41:18.975 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 03:41:19.173 [DEBUG] clck_gen.py:113 IND CLOCK 2448
2026-01-29 03:41:19.642 [DEBUG] clck_gen.py:113 IND CLOCK 2550
2026-01-29 03:41:20.111 [DEBUG] clck_gen.py:113 IND CLOCK 2652
2026-01-29 03:41:20.581 [DEBUG] clck_gen.py:113 IND CLOCK 2754
2026-01-29 03:41:21.057 [DEBUG] clck_gen.py:113 IND CLOCK 2856
2026-01-29 03:41:21.526 [DEBUG] clck_gen.py:113 IND CLOCK 2958
2026-01-29 03:41:21.995 [DEBUG] clck_gen.py:113 IND CLOCK 3060
2026-01-29 03:41:22.465 [DEBUG] clck_gen.py:113 IND CLOCK 3162
2026-01-29 03:41:22.937 [DEBUG] clck_gen.py:113 IND CLOCK 3264
2026-01-29 03:41:23.413 [DEBUG] clck_gen.py:113 IND CLOCK 3366
2026-01-29 03:41:23.890 [DEBUG] clck_gen.py:113 IND CLOCK 3468
2026-01-29 03:41:24.368 [DEBUG] clck_gen.py:113 IND CLOCK 3570
2026-01-29 03:41:24.842 [DEBUG] clck_gen.py:113 IND CLOCK 3672
2026-01-29 03:41:25.311 [DEBUG] clck_gen.py:113 IND CLOCK 3774
2026-01-29 03:41:25.781 [DEBUG] clck_gen.py:113 IND CLOCK 3876
2026-01-29 03:41:26.253 [DEBUG] clck_gen.py:113 IND CLOCK 3978
2026-01-29 03:41:26.730 [DEBUG] clck_gen.py:113 IND CLOCK 4080
2026-01-29 03:41:27.202 [DEBUG] clck_gen.py:113 IND CLOCK 4182
2026-01-29 03:41:27.675 [DEBUG] clck_gen.py:113 IND CLOCK 4284
2026-01-29 03:41:28.153 [DEBUG] clck_gen.py:113 IND CLOCK 4386
2026-01-29 03:41:28.630 [DEBUG] clck_gen.py:113 IND CLOCK 4488
2026-01-29 03:41:29.108 [DEBUG] clck_gen.py:113 IND CLOCK 4590
2026-01-29 03:41:29.276 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:41:29.276 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 03:41:29.279 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 03:41:29.279 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 03:41:29.279 [INFO] transceiver.py:205 (MS@172.18.28.22:6700) Frequency hopping disabled
2026-01-29 03:41:29.296 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 03:41:29.296 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 03:41:29.296 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 03:41:29.303 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 03:41:29.303 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 03:41:29.303 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 03:41:29.303 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:41:29.304 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 03:41:29.304 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 03:41:29.305 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 03:41:29.305 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.28.22:6700) Recv POWERON CMD
2026-01-29 03:41:29.305 [INFO] ctrl_if_trx.py:109 (MS@172.18.28.22:6700) Starting transceiver...
2026-01-29 03:41:29.343 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 03:41:29.343 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 03:41:29.343 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 03:41:29.344 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 03:41:29.585 [DEBUG] clck_gen.py:113 IND CLOCK 4692
2026-01-29 03:41:30.061 [DEBUG] clck_gen.py:113 IND CLOCK 4794
2026-01-29 03:41:30.539 [DEBUG] clck_gen.py:113 IND CLOCK 4896
2026-01-29 03:41:31.015 [DEBUG] clck_gen.py:113 IND CLOCK 4998
2026-01-29 03:41:31.493 [DEBUG] clck_gen.py:113 IND CLOCK 5100
2026-01-29 03:41:31.970 [DEBUG] clck_gen.py:113 IND CLOCK 5202
2026-01-29 03:41:32.446 [DEBUG] clck_gen.py:113 IND CLOCK 5304
2026-01-29 03:41:32.923 [DEBUG] clck_gen.py:113 IND CLOCK 5406
2026-01-29 03:41:33.398 [DEBUG] clck_gen.py:113 IND CLOCK 5508
2026-01-29 03:41:33.870 [DEBUG] clck_gen.py:113 IND CLOCK 5610
2026-01-29 03:41:34.347 [DEBUG] clck_gen.py:113 IND CLOCK 5712
2026-01-29 03:41:34.833 [DEBUG] clck_gen.py:113 IND CLOCK 5814
2026-01-29 03:41:35.310 [DEBUG] clck_gen.py:113 IND CLOCK 5916
2026-01-29 03:41:35.788 [DEBUG] clck_gen.py:113 IND CLOCK 6018
2026-01-29 03:41:36.266 [DEBUG] clck_gen.py:113 IND CLOCK 6120
2026-01-29 03:41:36.305 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 03:41:36.306 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:41:36.310 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 03:41:36.310 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 03:41:36.330 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 03:41:36.330 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 03:41:36.330 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 03:41:36.336 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 03:41:36.336 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 03:41:36.337 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 03:41:36.337 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:41:36.338 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 03:41:36.339 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 03:41:36.339 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 03:41:36.339 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.28.22:6700) Recv POWERON CMD
2026-01-29 03:41:36.339 [INFO] ctrl_if_trx.py:109 (MS@172.18.28.22:6700) Starting transceiver...
2026-01-29 03:41:36.357 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.28.22:6700) Recv SETFH cmd
2026-01-29 03:41:36.357 [INFO] transceiver.py:201 (MS@172.18.28.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2026-01-29 03:41:36.357 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 03:41:36.357 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 03:41:36.745 [DEBUG] clck_gen.py:113 IND CLOCK 6222
2026-01-29 03:41:37.222 [DEBUG] clck_gen.py:113 IND CLOCK 6324
2026-01-29 03:41:37.698 [DEBUG] clck_gen.py:113 IND CLOCK 6426
2026-01-29 03:41:38.176 [DEBUG] clck_gen.py:113 IND CLOCK 6528
2026-01-29 03:41:38.654 [DEBUG] clck_gen.py:113 IND CLOCK 6630
2026-01-29 03:41:39.127 [DEBUG] clck_gen.py:113 IND CLOCK 6732
2026-01-29 03:41:39.603 [DEBUG] clck_gen.py:113 IND CLOCK 6834
2026-01-29 03:41:40.080 [DEBUG] clck_gen.py:113 IND CLOCK 6936
2026-01-29 03:41:40.557 [DEBUG] clck_gen.py:113 IND CLOCK 7038
2026-01-29 03:41:41.034 [DEBUG] clck_gen.py:113 IND CLOCK 7140
2026-01-29 03:41:41.511 [DEBUG] clck_gen.py:113 IND CLOCK 7242
2026-01-29 03:41:41.988 [DEBUG] clck_gen.py:113 IND CLOCK 7344
2026-01-29 03:41:42.462 [DEBUG] clck_gen.py:113 IND CLOCK 7446
2026-01-29 03:41:42.938 [DEBUG] clck_gen.py:113 IND CLOCK 7548
2026-01-29 03:41:43.415 [DEBUG] clck_gen.py:113 IND CLOCK 7650
2026-01-29 03:41:43.892 [DEBUG] clck_gen.py:113 IND CLOCK 7752
2026-01-29 03:41:44.368 [DEBUG] clck_gen.py:113 IND CLOCK 7854
2026-01-29 03:41:44.846 [DEBUG] clck_gen.py:113 IND CLOCK 7956
2026-01-29 03:41:45.323 [DEBUG] clck_gen.py:113 IND CLOCK 8058
2026-01-29 03:41:45.801 [DEBUG] clck_gen.py:113 IND CLOCK 8160
2026-01-29 03:41:46.277 [DEBUG] clck_gen.py:113 IND CLOCK 8262
2026-01-29 03:41:46.754 [DEBUG] clck_gen.py:113 IND CLOCK 8364
2026-01-29 03:41:47.231 [DEBUG] clck_gen.py:113 IND CLOCK 8466
2026-01-29 03:41:47.708 [DEBUG] clck_gen.py:113 IND CLOCK 8568
2026-01-29 03:41:47.760 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 03:41:47.761 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:41:47.763 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 03:41:47.763 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 03:41:47.763 [INFO] transceiver.py:205 (MS@172.18.28.22:6700) Frequency hopping disabled
2026-01-29 03:41:47.773 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 03:41:47.774 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:41:47.774 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:41:47.774 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:41:47.777 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 03:41:47.778 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 03:41:47.778 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.28.20:5700) Recv POWEROFF cmd
2026-01-29 03:41:47.778 [INFO] ctrl_if_trx.py:117 (BTS@172.18.28.20:5700) Stopping transceiver...
2026-01-29 03:41:47.778 [INFO] transceiver.py:246 Stopping clock generator
2026-01-29 03:41:47.779 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 03:41:47.779 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 03:41:47.779 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=8584 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:41:47.779 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=8584 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:41:47.779 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=8584 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:41:47.779 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=8584 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:41:47.779 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=8584 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:41:47.779 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=8584 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:41:47.780 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=8584 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:41:47.780 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=8585 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:41:47.780 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=8585 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:41:47.780 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=8585 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:41:47.780 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=8585 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:41:47.780 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=8585 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:41:47.780 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=8585 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:41:47.780 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=8585 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:41:47.780 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=8585 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:41:52.776 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.28.20:5700) Recv POWEROFF cmd
2026-01-29 03:41:52.776 [INFO] ctrl_if_trx.py:117 (BTS@172.18.28.20:5700) Stopping transceiver...
2026-01-29 03:41:52.777 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 03:41:52.780 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 03:41:52.780 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 03:41:52.780 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 03:41:52.790 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 03:41:52.790 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.28.20:5700) Recv SETFORMAT cmd
2026-01-29 03:41:52.791 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.28.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:41:52.791 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.28.20:5700) Recv SETFORMAT cmd
2026-01-29 03:41:52.791 [INFO] ctrl_if_trx.py:201 (BTS@172.18.28.20:5700) TRXD header version 1 -> 1
2026-01-29 03:41:52.794 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.28.20:5700/1) Recv RXTUNE cmd
2026-01-29 03:41:52.794 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.28.20:5700/1) Recv TXTUNE cmd
2026-01-29 03:41:52.795 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.28.20:5700/1) Recv SETFORMAT cmd
2026-01-29 03:41:52.795 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.28.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:41:52.795 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 03:41:52.796 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.28.20:5700/1) Recv NOMTXPOWER cmd
2026-01-29 03:41:52.796 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.28.20:5700/1) Recv SETFORMAT cmd
2026-01-29 03:41:52.796 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.28.20:5700/1) TRXD header version 1 -> 1
2026-01-29 03:41:52.797 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.28.20:5700/2) Recv RXTUNE cmd
2026-01-29 03:41:52.797 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.28.20:5700/2) Recv TXTUNE cmd
2026-01-29 03:41:52.798 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.28.20:5700/2) Recv SETFORMAT cmd
2026-01-29 03:41:52.798 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.28.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:41:52.798 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 03:41:52.798 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.28.20:5700/2) Recv NOMTXPOWER cmd
2026-01-29 03:41:52.798 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.28.20:5700/2) Recv SETFORMAT cmd
2026-01-29 03:41:52.798 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.28.20:5700/2) TRXD header version 1 -> 1
2026-01-29 03:41:52.799 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.28.20:5700/3) Recv RXTUNE cmd
2026-01-29 03:41:52.799 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.28.20:5700/3) Recv TXTUNE cmd
2026-01-29 03:41:52.799 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.28.20:5700/3) Recv SETFORMAT cmd
2026-01-29 03:41:52.799 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.28.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:41:52.800 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 03:41:52.800 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.28.20:5700/3) Recv NOMTXPOWER cmd
2026-01-29 03:41:52.800 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.28.20:5700/3) Recv SETFORMAT cmd
2026-01-29 03:41:52.800 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.28.20:5700/3) TRXD header version 1 -> 1
2026-01-29 03:41:52.802 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.28.20:5700) Recv RXTUNE cmd
2026-01-29 03:41:52.803 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETTSC
2026-01-29 03:41:52.803 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETTSC
2026-01-29 03:41:52.803 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETTSC
2026-01-29 03:41:52.803 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.28.20:5700) Recv TXTUNE cmd
2026-01-29 03:41:52.803 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETRXGAIN
2026-01-29 03:41:52.803 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETRXGAIN
2026-01-29 03:41:52.803 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETRXGAIN
2026-01-29 03:41:52.803 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETTSC
2026-01-29 03:41:52.803 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:41:52.803 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:41:52.803 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:41:52.803 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.28.20:5700) Recv NOMTXPOWER cmd
2026-01-29 03:41:52.803 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:41:52.803 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:41:52.803 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:41:52.803 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.28.20:5700) Recv POWERON CMD
2026-01-29 03:41:52.803 [INFO] ctrl_if_trx.py:109 (BTS@172.18.28.20:5700) Starting transceiver...
2026-01-29 03:41:52.803 [INFO] transceiver.py:243 Starting clock generator
2026-01-29 03:41:52.803 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-01-29 03:41:52.803 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:41:52.803 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:41:52.803 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:41:52.803 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETRXGAIN
2026-01-29 03:41:52.803 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:41:52.803 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:41:52.803 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:41:52.803 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:41:52.803 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:41:52.803 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:41:52.803 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:41:52.803 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:41:52.803 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:41:52.804 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:41:52.804 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:41:52.804 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:41:52.804 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:41:52.804 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:41:52.804 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:41:52.804 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:41:52.804 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:41:52.804 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:41:52.804 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:41:52.804 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:41:52.804 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:41:52.804 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:41:52.804 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:41:52.808 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-01-29 03:41:53.283 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-01-29 03:41:53.333 [DEBUG] fake_trx.py:278 (BTS@172.18.28.20:5700) Recv FAKE_TOA cmd
2026-01-29 03:41:53.334 [DEBUG] fake_trx.py:297 (BTS@172.18.28.20:5700) Recv FAKE_RSSI cmd
2026-01-29 03:41:53.335 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:41:53.336 [DEBUG] fake_trx.py:322 (BTS@172.18.28.20:5700) Recv FAKE_CI cmd
2026-01-29 03:41:53.347 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 03:41:53.347 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 03:41:53.347 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 03:41:53.356 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 03:41:53.356 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 03:41:53.356 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 03:41:53.357 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:41:53.360 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 03:41:53.360 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 03:41:53.360 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 03:41:53.360 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.28.22:6700) Recv POWERON CMD
2026-01-29 03:41:53.360 [INFO] ctrl_if_trx.py:109 (MS@172.18.28.22:6700) Starting transceiver...
2026-01-29 03:41:53.373 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 03:41:53.374 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 03:41:53.374 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 03:41:53.374 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 03:41:53.679 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 03:41:53.680 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:41:53.683 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 03:41:53.683 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 03:41:53.697 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 03:41:53.697 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 03:41:53.697 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 03:41:53.703 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 03:41:53.703 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 03:41:53.704 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 03:41:53.704 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:41:53.705 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 03:41:53.705 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 03:41:53.705 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 03:41:53.706 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.28.22:6700) Recv POWERON CMD
2026-01-29 03:41:53.706 [INFO] ctrl_if_trx.py:109 (MS@172.18.28.22:6700) Starting transceiver...
2026-01-29 03:41:53.754 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.28.22:6700) Recv SETFH cmd
2026-01-29 03:41:53.754 [INFO] transceiver.py:201 (MS@172.18.28.22:6700) Frequency hopping configured: hsn=5, maio=0, ma_len=4
2026-01-29 03:41:53.754 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 03:41:53.754 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 03:41:53.758 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-01-29 03:41:53.805 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:41:53.806 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 03:41:53.806 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:41:53.806 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:41:54.232 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-01-29 03:41:54.244 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 03:41:54.245 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:41:54.249 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 03:41:54.249 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 03:41:54.249 [INFO] transceiver.py:205 (MS@172.18.28.22:6700) Frequency hopping disabled
2026-01-29 03:41:54.259 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 03:41:54.259 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 03:41:54.259 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 03:41:54.266 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 03:41:54.266 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 03:41:54.266 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 03:41:54.266 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:41:54.267 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 03:41:54.267 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 03:41:54.267 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 03:41:54.267 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.28.22:6700) Recv POWERON CMD
2026-01-29 03:41:54.267 [INFO] ctrl_if_trx.py:109 (MS@172.18.28.22:6700) Starting transceiver...
2026-01-29 03:41:54.274 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 03:41:54.275 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 03:41:54.275 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 03:41:54.275 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 03:41:54.708 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-01-29 03:41:54.806 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:41:54.807 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 03:41:54.807 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:41:54.807 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:41:55.098 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 03:41:55.099 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:41:55.102 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 03:41:55.102 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 03:41:55.121 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 03:41:55.121 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 03:41:55.121 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 03:41:55.127 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 03:41:55.127 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 03:41:55.127 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 03:41:55.128 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:41:55.129 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 03:41:55.129 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 03:41:55.129 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 03:41:55.129 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.28.22:6700) Recv POWERON CMD
2026-01-29 03:41:55.129 [INFO] ctrl_if_trx.py:109 (MS@172.18.28.22:6700) Starting transceiver...
2026-01-29 03:41:55.178 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.28.22:6700) Recv SETFH cmd
2026-01-29 03:41:55.178 [INFO] transceiver.py:201 (MS@172.18.28.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2026-01-29 03:41:55.178 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 03:41:55.179 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 03:41:55.184 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-01-29 03:41:55.658 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-01-29 03:41:55.807 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:41:55.808 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 03:41:55.808 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:41:55.808 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:41:56.131 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-01-29 03:41:56.610 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-01-29 03:41:56.808 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 03:41:56.809 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:41:56.809 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:41:56.809 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:41:57.088 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-01-29 03:41:57.567 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-01-29 03:41:57.809 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 03:41:57.809 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:41:57.810 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:41:57.810 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:41:58.045 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-01-29 03:41:58.522 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-01-29 03:41:58.998 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-01-29 03:41:59.215 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 03:41:59.216 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:41:59.220 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 03:41:59.220 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 03:41:59.220 [INFO] transceiver.py:205 (MS@172.18.28.22:6700) Frequency hopping disabled
2026-01-29 03:41:59.227 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 03:41:59.227 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:41:59.227 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:41:59.227 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:41:59.227 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 03:41:59.227 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 03:41:59.227 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 03:41:59.227 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.28.20:5700) Recv POWEROFF cmd
2026-01-29 03:41:59.227 [INFO] ctrl_if_trx.py:117 (BTS@172.18.28.20:5700) Stopping transceiver...
2026-01-29 03:41:59.227 [INFO] transceiver.py:246 Stopping clock generator
2026-01-29 03:41:59.227 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 03:42:04.229 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.28.20:5700) Recv POWEROFF cmd
2026-01-29 03:42:04.229 [INFO] ctrl_if_trx.py:117 (BTS@172.18.28.20:5700) Stopping transceiver...
2026-01-29 03:42:04.233 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 03:42:04.233 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 03:42:04.233 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 03:42:04.233 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 03:42:04.240 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 03:42:04.241 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.28.20:5700) Recv SETFORMAT cmd
2026-01-29 03:42:04.241 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.28.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:42:04.242 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.28.20:5700) Recv SETFORMAT cmd
2026-01-29 03:42:04.242 [INFO] ctrl_if_trx.py:201 (BTS@172.18.28.20:5700) TRXD header version 1 -> 1
2026-01-29 03:42:04.244 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.28.20:5700/1) Recv RXTUNE cmd
2026-01-29 03:42:04.244 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.28.20:5700/1) Recv TXTUNE cmd
2026-01-29 03:42:04.244 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.28.20:5700/1) Recv SETFORMAT cmd
2026-01-29 03:42:04.244 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.28.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:42:04.244 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 03:42:04.244 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.28.20:5700/1) Recv NOMTXPOWER cmd
2026-01-29 03:42:04.245 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.28.20:5700/1) Recv SETFORMAT cmd
2026-01-29 03:42:04.245 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.28.20:5700/1) TRXD header version 1 -> 1
2026-01-29 03:42:04.247 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.28.20:5700/2) Recv RXTUNE cmd
2026-01-29 03:42:04.247 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.28.20:5700/2) Recv TXTUNE cmd
2026-01-29 03:42:04.247 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.28.20:5700/2) Recv SETFORMAT cmd
2026-01-29 03:42:04.247 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.28.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:42:04.247 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 03:42:04.247 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.28.20:5700/2) Recv NOMTXPOWER cmd
2026-01-29 03:42:04.247 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.28.20:5700/2) Recv SETFORMAT cmd
2026-01-29 03:42:04.247 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.28.20:5700/2) TRXD header version 1 -> 1
2026-01-29 03:42:04.249 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.28.20:5700/3) Recv RXTUNE cmd
2026-01-29 03:42:04.249 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.28.20:5700/3) Recv TXTUNE cmd
2026-01-29 03:42:04.249 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.28.20:5700/3) Recv SETFORMAT cmd
2026-01-29 03:42:04.249 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.28.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:42:04.249 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 03:42:04.249 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.28.20:5700/3) Recv NOMTXPOWER cmd
2026-01-29 03:42:04.249 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.28.20:5700/3) Recv SETFORMAT cmd
2026-01-29 03:42:04.249 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.28.20:5700/3) TRXD header version 1 -> 1
2026-01-29 03:42:04.252 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.28.20:5700) Recv RXTUNE cmd
2026-01-29 03:42:04.252 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETTSC
2026-01-29 03:42:04.252 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETTSC
2026-01-29 03:42:04.252 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETTSC
2026-01-29 03:42:04.252 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.28.20:5700) Recv TXTUNE cmd
2026-01-29 03:42:04.252 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETRXGAIN
2026-01-29 03:42:04.252 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETRXGAIN
2026-01-29 03:42:04.252 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETRXGAIN
2026-01-29 03:42:04.252 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETTSC
2026-01-29 03:42:04.252 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:42:04.252 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:42:04.252 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:42:04.252 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.28.20:5700) Recv NOMTXPOWER cmd
2026-01-29 03:42:04.252 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:42:04.252 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:42:04.252 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:42:04.252 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.28.20:5700) Recv POWERON CMD
2026-01-29 03:42:04.252 [INFO] ctrl_if_trx.py:109 (BTS@172.18.28.20:5700) Starting transceiver...
2026-01-29 03:42:04.252 [INFO] transceiver.py:243 Starting clock generator
2026-01-29 03:42:04.252 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-01-29 03:42:04.253 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:42:04.253 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:42:04.253 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:42:04.253 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETRXGAIN
2026-01-29 03:42:04.253 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:42:04.253 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:42:04.253 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:42:04.253 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:42:04.253 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:42:04.253 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:42:04.253 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:42:04.253 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:42:04.253 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:42:04.253 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:42:04.253 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:42:04.253 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:42:04.253 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:42:04.253 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:42:04.253 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:42:04.253 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:42:04.253 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:42:04.253 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:42:04.253 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:42:04.253 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:42:04.254 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:42:04.254 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:42:04.254 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:42:04.257 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-01-29 03:42:04.735 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-01-29 03:42:04.787 [DEBUG] fake_trx.py:278 (BTS@172.18.28.20:5700) Recv FAKE_TOA cmd
2026-01-29 03:42:04.789 [DEBUG] fake_trx.py:297 (BTS@172.18.28.20:5700) Recv FAKE_RSSI cmd
2026-01-29 03:42:04.790 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:42:04.791 [DEBUG] fake_trx.py:322 (BTS@172.18.28.20:5700) Recv FAKE_CI cmd
2026-01-29 03:42:04.807 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 03:42:04.808 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 03:42:04.808 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 03:42:04.826 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 03:42:04.826 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 03:42:04.826 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 03:42:04.828 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:42:04.834 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 03:42:04.834 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 03:42:04.834 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 03:42:04.834 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.28.22:6700) Recv POWERON CMD
2026-01-29 03:42:04.834 [INFO] ctrl_if_trx.py:109 (MS@172.18.28.22:6700) Starting transceiver...
2026-01-29 03:42:04.872 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 03:42:04.872 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 03:42:04.872 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 03:42:04.872 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 03:42:05.210 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-01-29 03:42:05.256 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 03:42:05.256 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:42:05.257 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:42:05.260 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:42:05.688 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-01-29 03:42:06.164 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-01-29 03:42:06.257 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 03:42:06.257 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:42:06.258 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:42:06.262 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:42:06.641 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-01-29 03:42:07.118 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-01-29 03:42:07.257 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 03:42:07.258 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:42:07.258 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:42:07.262 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:42:07.595 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-01-29 03:42:08.071 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-01-29 03:42:08.111 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 03:42:08.113 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:42:08.116 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 03:42:08.116 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 03:42:08.133 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 03:42:08.133 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 03:42:08.133 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 03:42:08.139 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 03:42:08.139 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 03:42:08.139 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 03:42:08.139 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:42:08.140 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 03:42:08.140 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 03:42:08.141 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 03:42:08.141 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.28.22:6700) Recv POWERON CMD
2026-01-29 03:42:08.141 [INFO] ctrl_if_trx.py:109 (MS@172.18.28.22:6700) Starting transceiver...
2026-01-29 03:42:08.163 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.28.22:6700) Recv SETFH cmd
2026-01-29 03:42:08.163 [INFO] transceiver.py:201 (MS@172.18.28.22:6700) Frequency hopping configured: hsn=5, maio=0, ma_len=4
2026-01-29 03:42:08.163 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 03:42:08.163 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 03:42:08.258 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:42:08.259 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 03:42:08.259 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:42:08.263 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:42:08.543 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-01-29 03:42:09.014 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-01-29 03:42:09.259 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:42:09.260 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 03:42:09.260 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:42:09.264 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:42:09.484 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-01-29 03:42:09.959 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-01-29 03:42:10.435 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-01-29 03:42:10.912 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-01-29 03:42:11.387 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-01-29 03:42:11.506 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 03:42:11.507 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:42:11.510 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 03:42:11.510 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 03:42:11.510 [INFO] transceiver.py:205 (MS@172.18.28.22:6700) Frequency hopping disabled
2026-01-29 03:42:11.530 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 03:42:11.530 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 03:42:11.530 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 03:42:11.537 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 03:42:11.537 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 03:42:11.537 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 03:42:11.537 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:42:11.538 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 03:42:11.538 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 03:42:11.539 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 03:42:11.539 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.28.22:6700) Recv POWERON CMD
2026-01-29 03:42:11.539 [INFO] ctrl_if_trx.py:109 (MS@172.18.28.22:6700) Starting transceiver...
2026-01-29 03:42:11.567 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 03:42:11.567 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 03:42:11.567 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 03:42:11.567 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 03:42:11.860 [DEBUG] clck_gen.py:113 IND CLOCK 1632
2026-01-29 03:42:12.334 [DEBUG] clck_gen.py:113 IND CLOCK 1734
2026-01-29 03:42:12.812 [DEBUG] clck_gen.py:113 IND CLOCK 1836
2026-01-29 03:42:13.289 [DEBUG] clck_gen.py:113 IND CLOCK 1938
2026-01-29 03:42:13.766 [DEBUG] clck_gen.py:113 IND CLOCK 2040
2026-01-29 03:42:14.243 [DEBUG] clck_gen.py:113 IND CLOCK 2142
2026-01-29 03:42:14.719 [DEBUG] clck_gen.py:113 IND CLOCK 2244
2026-01-29 03:42:15.110 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 03:42:15.111 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:42:15.115 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 03:42:15.115 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 03:42:15.134 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 03:42:15.134 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 03:42:15.134 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 03:42:15.140 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 03:42:15.140 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 03:42:15.140 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 03:42:15.140 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:42:15.141 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 03:42:15.142 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 03:42:15.142 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 03:42:15.142 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.28.22:6700) Recv POWERON CMD
2026-01-29 03:42:15.142 [INFO] ctrl_if_trx.py:109 (MS@172.18.28.22:6700) Starting transceiver...
2026-01-29 03:42:15.190 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.28.22:6700) Recv SETFH cmd
2026-01-29 03:42:15.190 [INFO] transceiver.py:201 (MS@172.18.28.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2026-01-29 03:42:15.191 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 03:42:15.191 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 03:42:15.196 [DEBUG] clck_gen.py:113 IND CLOCK 2346
2026-01-29 03:42:15.674 [DEBUG] clck_gen.py:113 IND CLOCK 2448
2026-01-29 03:42:16.150 [DEBUG] clck_gen.py:113 IND CLOCK 2550
2026-01-29 03:42:16.619 [DEBUG] clck_gen.py:113 IND CLOCK 2652
2026-01-29 03:42:17.092 [DEBUG] clck_gen.py:113 IND CLOCK 2754
2026-01-29 03:42:17.568 [DEBUG] clck_gen.py:113 IND CLOCK 2856
2026-01-29 03:42:18.046 [DEBUG] clck_gen.py:113 IND CLOCK 2958
2026-01-29 03:42:18.524 [DEBUG] clck_gen.py:113 IND CLOCK 3060
2026-01-29 03:42:19.002 [DEBUG] clck_gen.py:113 IND CLOCK 3162
2026-01-29 03:42:19.480 [DEBUG] clck_gen.py:113 IND CLOCK 3264
2026-01-29 03:42:19.562 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 03:42:19.563 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:42:19.568 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 03:42:19.568 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 03:42:19.568 [INFO] transceiver.py:205 (MS@172.18.28.22:6700) Frequency hopping disabled
2026-01-29 03:42:19.577 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 03:42:19.577 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:42:19.577 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:42:19.577 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:42:19.578 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 03:42:19.578 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 03:42:19.578 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 03:42:19.578 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 03:42:19.578 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.28.20:5700) Recv POWEROFF cmd
2026-01-29 03:42:19.578 [INFO] ctrl_if_trx.py:117 (BTS@172.18.28.20:5700) Stopping transceiver...
2026-01-29 03:42:19.578 [INFO] transceiver.py:246 Stopping clock generator
2026-01-29 03:42:19.578 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=3287 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:42:19.578 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=3287 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:42:19.578 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=3287 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:42:19.578 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=3287 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:42:19.578 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=3287 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:42:19.578 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=3287 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:42:19.578 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=3287 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:42:24.581 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.28.20:5700) Recv POWEROFF cmd
2026-01-29 03:42:24.581 [INFO] ctrl_if_trx.py:117 (BTS@172.18.28.20:5700) Stopping transceiver...
2026-01-29 03:42:24.583 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 03:42:24.584 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 03:42:24.585 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 03:42:24.585 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 03:42:24.592 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 03:42:24.592 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.28.20:5700) Recv SETFORMAT cmd
2026-01-29 03:42:24.593 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.28.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:42:24.593 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.28.20:5700) Recv SETFORMAT cmd
2026-01-29 03:42:24.593 [INFO] ctrl_if_trx.py:201 (BTS@172.18.28.20:5700) TRXD header version 1 -> 1
2026-01-29 03:42:24.595 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.28.20:5700/1) Recv RXTUNE cmd
2026-01-29 03:42:24.595 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.28.20:5700/1) Recv TXTUNE cmd
2026-01-29 03:42:24.596 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.28.20:5700/1) Recv SETFORMAT cmd
2026-01-29 03:42:24.596 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.28.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:42:24.596 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 03:42:24.596 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.28.20:5700/1) Recv NOMTXPOWER cmd
2026-01-29 03:42:24.597 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.28.20:5700/1) Recv SETFORMAT cmd
2026-01-29 03:42:24.597 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.28.20:5700/1) TRXD header version 1 -> 1
2026-01-29 03:42:24.597 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.28.20:5700/2) Recv RXTUNE cmd
2026-01-29 03:42:24.598 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.28.20:5700/2) Recv TXTUNE cmd
2026-01-29 03:42:24.598 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.28.20:5700/2) Recv SETFORMAT cmd
2026-01-29 03:42:24.598 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.28.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:42:24.598 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 03:42:24.598 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.28.20:5700/2) Recv NOMTXPOWER cmd
2026-01-29 03:42:24.598 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.28.20:5700/2) Recv SETFORMAT cmd
2026-01-29 03:42:24.598 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.28.20:5700/2) TRXD header version 1 -> 1
2026-01-29 03:42:24.600 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.28.20:5700/3) Recv RXTUNE cmd
2026-01-29 03:42:24.600 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.28.20:5700/3) Recv TXTUNE cmd
2026-01-29 03:42:24.600 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.28.20:5700/3) Recv SETFORMAT cmd
2026-01-29 03:42:24.600 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.28.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:42:24.600 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 03:42:24.600 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.28.20:5700/3) Recv NOMTXPOWER cmd
2026-01-29 03:42:24.600 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.28.20:5700/3) Recv SETFORMAT cmd
2026-01-29 03:42:24.600 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.28.20:5700/3) TRXD header version 1 -> 1
2026-01-29 03:42:24.603 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.28.20:5700) Recv RXTUNE cmd
2026-01-29 03:42:24.603 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETTSC
2026-01-29 03:42:24.603 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETTSC
2026-01-29 03:42:24.603 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETTSC
2026-01-29 03:42:24.603 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.28.20:5700) Recv TXTUNE cmd
2026-01-29 03:42:24.603 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETRXGAIN
2026-01-29 03:42:24.603 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETRXGAIN
2026-01-29 03:42:24.603 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETRXGAIN
2026-01-29 03:42:24.603 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETTSC
2026-01-29 03:42:24.603 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:42:24.603 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:42:24.603 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:42:24.603 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.28.20:5700) Recv NOMTXPOWER cmd
2026-01-29 03:42:24.603 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:42:24.603 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:42:24.603 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:42:24.603 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.28.20:5700) Recv POWERON CMD
2026-01-29 03:42:24.603 [INFO] ctrl_if_trx.py:109 (BTS@172.18.28.20:5700) Starting transceiver...
2026-01-29 03:42:24.603 [INFO] transceiver.py:243 Starting clock generator
2026-01-29 03:42:24.603 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-01-29 03:42:24.603 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:42:24.603 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:42:24.603 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:42:24.603 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETRXGAIN
2026-01-29 03:42:24.604 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:42:24.604 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:42:24.604 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:42:24.604 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:42:24.604 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:42:24.604 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:42:24.604 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:42:24.604 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:42:24.604 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:42:24.604 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:42:24.604 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:42:24.604 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:42:24.604 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:42:24.604 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:42:24.604 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:42:24.604 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:42:24.604 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:42:24.604 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:42:24.604 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:42:24.604 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:42:24.604 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:42:24.604 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:42:24.604 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:42:24.608 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-01-29 03:42:25.089 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-01-29 03:42:25.131 [DEBUG] fake_trx.py:278 (BTS@172.18.28.20:5700) Recv FAKE_TOA cmd
2026-01-29 03:42:25.134 [DEBUG] fake_trx.py:297 (BTS@172.18.28.20:5700) Recv FAKE_RSSI cmd
2026-01-29 03:42:25.135 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:42:25.136 [DEBUG] fake_trx.py:322 (BTS@172.18.28.20:5700) Recv FAKE_CI cmd
2026-01-29 03:42:25.162 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 03:42:25.162 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 03:42:25.162 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 03:42:25.181 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 03:42:25.181 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 03:42:25.181 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 03:42:25.181 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:42:25.186 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 03:42:25.186 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 03:42:25.186 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 03:42:25.186 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.28.22:6700) Recv POWERON CMD
2026-01-29 03:42:25.186 [INFO] ctrl_if_trx.py:109 (MS@172.18.28.22:6700) Starting transceiver...
2026-01-29 03:42:25.227 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 03:42:25.228 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 03:42:25.228 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 03:42:25.228 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 03:42:25.567 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-01-29 03:42:25.606 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:42:25.607 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 03:42:25.607 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:42:25.610 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:42:25.612 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 03:42:25.612 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:42:25.615 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 03:42:25.615 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 03:42:25.625 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 03:42:25.625 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 03:42:25.626 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 03:42:25.632 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 03:42:25.632 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 03:42:25.632 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 03:42:25.633 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:42:25.634 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 03:42:25.634 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 03:42:25.634 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 03:42:25.634 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.28.22:6700) Recv POWERON CMD
2026-01-29 03:42:25.634 [INFO] ctrl_if_trx.py:109 (MS@172.18.28.22:6700) Starting transceiver...
2026-01-29 03:42:25.660 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.28.22:6700) Recv SETFH cmd
2026-01-29 03:42:25.660 [INFO] transceiver.py:201 (MS@172.18.28.22:6700) Frequency hopping configured: hsn=5, maio=0, ma_len=4
2026-01-29 03:42:25.660 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 03:42:25.660 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 03:42:26.043 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-01-29 03:42:26.259 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 03:42:26.260 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:42:26.264 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 03:42:26.264 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 03:42:26.265 [INFO] transceiver.py:205 (MS@172.18.28.22:6700) Frequency hopping disabled
2026-01-29 03:42:26.284 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 03:42:26.284 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 03:42:26.285 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 03:42:26.291 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 03:42:26.291 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 03:42:26.291 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 03:42:26.291 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:42:26.293 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 03:42:26.293 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 03:42:26.293 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 03:42:26.293 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.28.22:6700) Recv POWERON CMD
2026-01-29 03:42:26.293 [INFO] ctrl_if_trx.py:109 (MS@172.18.28.22:6700) Starting transceiver...
2026-01-29 03:42:26.324 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 03:42:26.324 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 03:42:26.324 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 03:42:26.325 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 03:42:26.520 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-01-29 03:42:26.608 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 03:42:26.608 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:42:26.609 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:42:26.611 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:42:26.997 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-01-29 03:42:27.387 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 03:42:27.388 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:42:27.390 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 03:42:27.391 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 03:42:27.402 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 03:42:27.402 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 03:42:27.402 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 03:42:27.409 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 03:42:27.409 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 03:42:27.409 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 03:42:27.410 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:42:27.411 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 03:42:27.411 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 03:42:27.411 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 03:42:27.411 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.28.22:6700) Recv POWERON CMD
2026-01-29 03:42:27.411 [INFO] ctrl_if_trx.py:109 (MS@172.18.28.22:6700) Starting transceiver...
2026-01-29 03:42:27.413 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.28.22:6700) Recv SETFH cmd
2026-01-29 03:42:27.413 [INFO] transceiver.py:201 (MS@172.18.28.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2026-01-29 03:42:27.413 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 03:42:27.413 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 03:42:27.469 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-01-29 03:42:27.609 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 03:42:27.609 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:42:27.609 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:42:27.612 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:42:27.947 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-01-29 03:42:28.425 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-01-29 03:42:28.610 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:42:28.610 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:42:28.611 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 03:42:28.613 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:42:28.900 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-01-29 03:42:29.378 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-01-29 03:42:29.612 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 03:42:29.612 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:42:29.612 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:42:29.614 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:42:29.856 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-01-29 03:42:30.333 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-01-29 03:42:30.810 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-01-29 03:42:31.287 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-01-29 03:42:31.765 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-01-29 03:42:32.238 [DEBUG] clck_gen.py:113 IND CLOCK 1632
2026-01-29 03:42:32.707 [DEBUG] clck_gen.py:113 IND CLOCK 1734
2026-01-29 03:42:33.178 [DEBUG] clck_gen.py:113 IND CLOCK 1836
2026-01-29 03:42:33.649 [DEBUG] clck_gen.py:113 IND CLOCK 1938
2026-01-29 03:42:34.126 [DEBUG] clck_gen.py:113 IND CLOCK 2040
2026-01-29 03:42:34.603 [DEBUG] clck_gen.py:113 IND CLOCK 2142
2026-01-29 03:42:35.079 [DEBUG] clck_gen.py:113 IND CLOCK 2244
2026-01-29 03:42:35.556 [DEBUG] clck_gen.py:113 IND CLOCK 2346
2026-01-29 03:42:36.033 [DEBUG] clck_gen.py:113 IND CLOCK 2448
2026-01-29 03:42:36.510 [DEBUG] clck_gen.py:113 IND CLOCK 2550
2026-01-29 03:42:36.987 [DEBUG] clck_gen.py:113 IND CLOCK 2652
2026-01-29 03:42:37.463 [DEBUG] clck_gen.py:113 IND CLOCK 2754
2026-01-29 03:42:37.940 [DEBUG] clck_gen.py:113 IND CLOCK 2856
2026-01-29 03:42:38.417 [DEBUG] clck_gen.py:113 IND CLOCK 2958
2026-01-29 03:42:38.891 [DEBUG] clck_gen.py:113 IND CLOCK 3060
2026-01-29 03:42:39.368 [DEBUG] clck_gen.py:113 IND CLOCK 3162
2026-01-29 03:42:39.845 [DEBUG] clck_gen.py:113 IND CLOCK 3264
2026-01-29 03:42:40.323 [DEBUG] clck_gen.py:113 IND CLOCK 3366
2026-01-29 03:42:40.800 [DEBUG] clck_gen.py:113 IND CLOCK 3468
2026-01-29 03:42:41.270 [DEBUG] clck_gen.py:113 IND CLOCK 3570
2026-01-29 03:42:41.739 [DEBUG] clck_gen.py:113 IND CLOCK 3672
2026-01-29 03:42:42.211 [DEBUG] clck_gen.py:113 IND CLOCK 3774
2026-01-29 03:42:42.689 [DEBUG] clck_gen.py:113 IND CLOCK 3876
2026-01-29 03:42:43.165 [DEBUG] clck_gen.py:113 IND CLOCK 3978
2026-01-29 03:42:43.641 [DEBUG] clck_gen.py:113 IND CLOCK 4080
2026-01-29 03:42:44.118 [DEBUG] clck_gen.py:113 IND CLOCK 4182
2026-01-29 03:42:44.592 [DEBUG] clck_gen.py:113 IND CLOCK 4284
2026-01-29 03:42:45.061 [DEBUG] clck_gen.py:113 IND CLOCK 4386
2026-01-29 03:42:45.533 [DEBUG] clck_gen.py:113 IND CLOCK 4488
2026-01-29 03:42:46.011 [DEBUG] clck_gen.py:113 IND CLOCK 4590
2026-01-29 03:42:46.490 [DEBUG] clck_gen.py:113 IND CLOCK 4692
2026-01-29 03:42:46.967 [DEBUG] clck_gen.py:113 IND CLOCK 4794
2026-01-29 03:42:47.406 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 03:42:47.406 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 03:42:47.407 [INFO] transceiver.py:205 (MS@172.18.28.22:6700) Frequency hopping disabled
2026-01-29 03:42:47.409 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 03:42:47.409 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:42:47.409 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:42:47.409 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:42:47.409 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 03:42:47.409 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 03:42:47.409 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 03:42:47.409 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 03:42:47.409 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.28.20:5700) Recv POWEROFF cmd
2026-01-29 03:42:47.409 [INFO] ctrl_if_trx.py:117 (BTS@172.18.28.20:5700) Stopping transceiver...
2026-01-29 03:42:47.409 [INFO] transceiver.py:246 Stopping clock generator
2026-01-29 03:42:47.410 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=4891 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:42:47.410 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=4891 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:42:47.410 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=4891 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:42:47.410 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=4891 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:42:47.410 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=4891 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:42:47.410 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=4891 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:42:47.410 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=4891 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:42:52.412 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.28.20:5700) Recv POWEROFF cmd
2026-01-29 03:42:52.412 [INFO] ctrl_if_trx.py:117 (BTS@172.18.28.20:5700) Stopping transceiver...
2026-01-29 03:42:52.413 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 03:42:52.417 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 03:42:52.417 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 03:42:52.417 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 03:42:52.425 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 03:42:52.427 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.28.20:5700) Recv SETFORMAT cmd
2026-01-29 03:42:52.427 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.28.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:42:52.427 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.28.20:5700) Recv SETFORMAT cmd
2026-01-29 03:42:52.427 [INFO] ctrl_if_trx.py:201 (BTS@172.18.28.20:5700) TRXD header version 1 -> 1
2026-01-29 03:42:52.431 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.28.20:5700/1) Recv RXTUNE cmd
2026-01-29 03:42:52.432 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.28.20:5700/1) Recv TXTUNE cmd
2026-01-29 03:42:52.432 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.28.20:5700/1) Recv SETFORMAT cmd
2026-01-29 03:42:52.432 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.28.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:42:52.432 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 03:42:52.432 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.28.20:5700/1) Recv NOMTXPOWER cmd
2026-01-29 03:42:52.432 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.28.20:5700/1) Recv SETFORMAT cmd
2026-01-29 03:42:52.432 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.28.20:5700/1) TRXD header version 1 -> 1
2026-01-29 03:42:52.435 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.28.20:5700/2) Recv RXTUNE cmd
2026-01-29 03:42:52.435 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.28.20:5700/2) Recv TXTUNE cmd
2026-01-29 03:42:52.435 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.28.20:5700/2) Recv SETFORMAT cmd
2026-01-29 03:42:52.435 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.28.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:42:52.435 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 03:42:52.435 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.28.20:5700/2) Recv NOMTXPOWER cmd
2026-01-29 03:42:52.435 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.28.20:5700/2) Recv SETFORMAT cmd
2026-01-29 03:42:52.435 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.28.20:5700/2) TRXD header version 1 -> 1
2026-01-29 03:42:52.438 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.28.20:5700/3) Recv RXTUNE cmd
2026-01-29 03:42:52.438 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.28.20:5700/3) Recv TXTUNE cmd
2026-01-29 03:42:52.438 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.28.20:5700/3) Recv SETFORMAT cmd
2026-01-29 03:42:52.438 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.28.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:42:52.438 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 03:42:52.438 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.28.20:5700/3) Recv NOMTXPOWER cmd
2026-01-29 03:42:52.438 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.28.20:5700/3) Recv SETFORMAT cmd
2026-01-29 03:42:52.438 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.28.20:5700/3) TRXD header version 1 -> 1
2026-01-29 03:42:52.441 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.28.20:5700) Recv RXTUNE cmd
2026-01-29 03:42:52.441 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETTSC
2026-01-29 03:42:52.441 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETTSC
2026-01-29 03:42:52.441 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETTSC
2026-01-29 03:42:52.441 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.28.20:5700) Recv TXTUNE cmd
2026-01-29 03:42:52.441 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETRXGAIN
2026-01-29 03:42:52.441 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETRXGAIN
2026-01-29 03:42:52.441 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETRXGAIN
2026-01-29 03:42:52.441 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETTSC
2026-01-29 03:42:52.441 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:42:52.441 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:42:52.441 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:42:52.441 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.28.20:5700) Recv NOMTXPOWER cmd
2026-01-29 03:42:52.441 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:42:52.441 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:42:52.441 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:42:52.441 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.28.20:5700) Recv POWERON CMD
2026-01-29 03:42:52.442 [INFO] ctrl_if_trx.py:109 (BTS@172.18.28.20:5700) Starting transceiver...
2026-01-29 03:42:52.442 [INFO] transceiver.py:243 Starting clock generator
2026-01-29 03:42:52.442 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-01-29 03:42:52.442 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:42:52.442 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:42:52.442 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:42:52.442 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETRXGAIN
2026-01-29 03:42:52.442 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:42:52.442 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:42:52.442 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:42:52.442 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:42:52.442 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:42:52.442 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:42:52.442 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:42:52.442 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:42:52.442 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:42:52.442 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:42:52.442 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:42:52.442 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:42:52.442 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:42:52.443 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:42:52.443 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:42:52.443 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:42:52.443 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:42:52.443 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:42:52.443 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:42:52.443 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:42:52.443 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:42:52.443 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:42:52.443 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:42:52.447 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-01-29 03:42:52.915 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-01-29 03:42:52.972 [DEBUG] fake_trx.py:278 (BTS@172.18.28.20:5700) Recv FAKE_TOA cmd
2026-01-29 03:42:52.974 [DEBUG] fake_trx.py:297 (BTS@172.18.28.20:5700) Recv FAKE_RSSI cmd
2026-01-29 03:42:52.975 [DEBUG] fake_trx.py:322 (BTS@172.18.28.20:5700) Recv FAKE_CI cmd
2026-01-29 03:42:52.975 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:42:52.994 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 03:42:52.994 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 03:42:52.994 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 03:42:53.007 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 03:42:53.007 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 03:42:53.007 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 03:42:53.007 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:42:53.009 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 03:42:53.009 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 03:42:53.009 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 03:42:53.009 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.28.22:6700) Recv POWERON CMD
2026-01-29 03:42:53.009 [INFO] ctrl_if_trx.py:109 (MS@172.18.28.22:6700) Starting transceiver...
2026-01-29 03:42:53.053 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 03:42:53.053 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 03:42:53.053 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 03:42:53.054 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 03:42:53.384 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-01-29 03:42:53.445 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:42:53.445 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 03:42:53.446 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:42:53.449 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:42:53.853 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-01-29 03:42:54.324 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-01-29 03:42:54.446 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 03:42:54.446 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:42:54.446 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:42:54.450 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:42:54.795 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-01-29 03:42:55.265 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-01-29 03:42:55.446 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:42:55.447 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 03:42:55.447 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:42:55.450 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:42:55.736 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-01-29 03:42:55.885 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 03:42:55.886 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:42:55.889 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 03:42:55.889 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 03:42:55.909 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 03:42:55.909 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 03:42:55.909 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 03:42:55.916 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 03:42:55.916 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 03:42:55.916 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 03:42:55.917 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:42:55.919 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 03:42:55.919 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 03:42:55.919 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 03:42:55.919 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.28.22:6700) Recv POWERON CMD
2026-01-29 03:42:55.919 [INFO] ctrl_if_trx.py:109 (MS@172.18.28.22:6700) Starting transceiver...
2026-01-29 03:42:55.970 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.28.22:6700) Recv SETFH cmd
2026-01-29 03:42:55.970 [INFO] transceiver.py:201 (MS@172.18.28.22:6700) Frequency hopping configured: hsn=5, maio=0, ma_len=4
2026-01-29 03:42:55.970 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 03:42:55.970 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 03:42:56.207 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-01-29 03:42:56.448 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:42:56.448 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 03:42:56.448 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:42:56.450 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:42:56.678 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-01-29 03:42:57.148 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-01-29 03:42:57.448 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:42:57.449 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 03:42:57.449 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:42:57.451 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:42:57.619 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-01-29 03:42:58.090 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-01-29 03:42:58.560 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-01-29 03:42:59.031 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-01-29 03:42:59.502 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-01-29 03:42:59.972 [DEBUG] clck_gen.py:113 IND CLOCK 1632
2026-01-29 03:43:00.443 [DEBUG] clck_gen.py:113 IND CLOCK 1734
2026-01-29 03:43:00.464 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 03:43:00.465 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:43:00.468 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 03:43:00.469 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 03:43:00.469 [INFO] transceiver.py:205 (MS@172.18.28.22:6700) Frequency hopping disabled
2026-01-29 03:43:00.485 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 03:43:00.485 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 03:43:00.485 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 03:43:00.492 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 03:43:00.492 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 03:43:00.492 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 03:43:00.493 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:43:00.494 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 03:43:00.494 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 03:43:00.494 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 03:43:00.494 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.28.22:6700) Recv POWERON CMD
2026-01-29 03:43:00.494 [INFO] ctrl_if_trx.py:109 (MS@172.18.28.22:6700) Starting transceiver...
2026-01-29 03:43:00.534 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 03:43:00.534 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 03:43:00.535 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 03:43:00.535 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 03:43:00.914 [DEBUG] clck_gen.py:113 IND CLOCK 1836
2026-01-29 03:43:01.385 [DEBUG] clck_gen.py:113 IND CLOCK 1938
2026-01-29 03:43:01.856 [DEBUG] clck_gen.py:113 IND CLOCK 2040
2026-01-29 03:43:02.327 [DEBUG] clck_gen.py:113 IND CLOCK 2142
2026-01-29 03:43:02.798 [DEBUG] clck_gen.py:113 IND CLOCK 2244
2026-01-29 03:43:03.268 [DEBUG] clck_gen.py:113 IND CLOCK 2346
2026-01-29 03:43:03.739 [DEBUG] clck_gen.py:113 IND CLOCK 2448
2026-01-29 03:43:04.210 [DEBUG] clck_gen.py:113 IND CLOCK 2550
2026-01-29 03:43:04.681 [DEBUG] clck_gen.py:113 IND CLOCK 2652
2026-01-29 03:43:05.151 [DEBUG] clck_gen.py:113 IND CLOCK 2754
2026-01-29 03:43:05.622 [DEBUG] clck_gen.py:113 IND CLOCK 2856
2026-01-29 03:43:06.093 [DEBUG] clck_gen.py:113 IND CLOCK 2958
2026-01-29 03:43:06.564 [DEBUG] clck_gen.py:113 IND CLOCK 3060
2026-01-29 03:43:07.034 [DEBUG] clck_gen.py:113 IND CLOCK 3162
2026-01-29 03:43:07.188 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 03:43:07.189 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:43:07.193 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 03:43:07.193 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 03:43:07.211 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 03:43:07.211 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 03:43:07.211 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 03:43:07.218 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 03:43:07.218 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 03:43:07.218 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 03:43:07.219 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:43:07.220 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 03:43:07.220 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 03:43:07.220 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 03:43:07.220 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.28.22:6700) Recv POWERON CMD
2026-01-29 03:43:07.220 [INFO] ctrl_if_trx.py:109 (MS@172.18.28.22:6700) Starting transceiver...
2026-01-29 03:43:07.268 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.28.22:6700) Recv SETFH cmd
2026-01-29 03:43:07.268 [INFO] transceiver.py:201 (MS@172.18.28.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2026-01-29 03:43:07.269 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 03:43:07.269 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 03:43:07.505 [DEBUG] clck_gen.py:113 IND CLOCK 3264
2026-01-29 03:43:07.975 [DEBUG] clck_gen.py:113 IND CLOCK 3366
2026-01-29 03:43:08.058 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 03:43:08.058 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 03:43:08.058 [INFO] transceiver.py:205 (MS@172.18.28.22:6700) Frequency hopping disabled
2026-01-29 03:43:08.063 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 03:43:08.064 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:43:08.064 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:43:08.064 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:43:08.065 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 03:43:08.065 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 03:43:08.065 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 03:43:08.065 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.28.20:5700) Recv POWEROFF cmd
2026-01-29 03:43:08.065 [INFO] ctrl_if_trx.py:117 (BTS@172.18.28.20:5700) Stopping transceiver...
2026-01-29 03:43:08.065 [INFO] transceiver.py:246 Stopping clock generator
2026-01-29 03:43:08.065 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 03:43:08.065 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=3387 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:43:08.065 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=3387 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:43:08.065 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=3387 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:43:08.065 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=3387 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:43:08.065 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=3387 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:43:08.065 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=3387 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:43:08.065 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=3387 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:43:08.065 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=3387 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:43:13.066 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.28.20:5700) Recv POWEROFF cmd
2026-01-29 03:43:13.066 [INFO] ctrl_if_trx.py:117 (BTS@172.18.28.20:5700) Stopping transceiver...
2026-01-29 03:43:13.067 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 03:43:13.069 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 03:43:13.070 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 03:43:13.070 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 03:43:13.080 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 03:43:13.081 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.28.20:5700) Recv SETFORMAT cmd
2026-01-29 03:43:13.081 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.28.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:43:13.081 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.28.20:5700) Recv SETFORMAT cmd
2026-01-29 03:43:13.081 [INFO] ctrl_if_trx.py:201 (BTS@172.18.28.20:5700) TRXD header version 1 -> 1
2026-01-29 03:43:13.083 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.28.20:5700/1) Recv RXTUNE cmd
2026-01-29 03:43:13.084 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.28.20:5700/1) Recv TXTUNE cmd
2026-01-29 03:43:13.084 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.28.20:5700/1) Recv SETFORMAT cmd
2026-01-29 03:43:13.084 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.28.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:43:13.084 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 03:43:13.084 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.28.20:5700/1) Recv NOMTXPOWER cmd
2026-01-29 03:43:13.084 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.28.20:5700/1) Recv SETFORMAT cmd
2026-01-29 03:43:13.084 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.28.20:5700/1) TRXD header version 1 -> 1
2026-01-29 03:43:13.086 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.28.20:5700/2) Recv RXTUNE cmd
2026-01-29 03:43:13.086 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.28.20:5700/2) Recv TXTUNE cmd
2026-01-29 03:43:13.086 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.28.20:5700/2) Recv SETFORMAT cmd
2026-01-29 03:43:13.086 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.28.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:43:13.087 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 03:43:13.087 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.28.20:5700/2) Recv NOMTXPOWER cmd
2026-01-29 03:43:13.087 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.28.20:5700/2) Recv SETFORMAT cmd
2026-01-29 03:43:13.087 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.28.20:5700/2) TRXD header version 1 -> 1
2026-01-29 03:43:13.088 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.28.20:5700/3) Recv RXTUNE cmd
2026-01-29 03:43:13.088 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.28.20:5700/3) Recv TXTUNE cmd
2026-01-29 03:43:13.089 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.28.20:5700/3) Recv SETFORMAT cmd
2026-01-29 03:43:13.089 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.28.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:43:13.089 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 03:43:13.089 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.28.20:5700/3) Recv NOMTXPOWER cmd
2026-01-29 03:43:13.089 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.28.20:5700/3) Recv SETFORMAT cmd
2026-01-29 03:43:13.089 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.28.20:5700/3) TRXD header version 1 -> 1
2026-01-29 03:43:13.091 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.28.20:5700) Recv RXTUNE cmd
2026-01-29 03:43:13.091 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETTSC
2026-01-29 03:43:13.091 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETTSC
2026-01-29 03:43:13.091 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETTSC
2026-01-29 03:43:13.091 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.28.20:5700) Recv TXTUNE cmd
2026-01-29 03:43:13.091 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETRXGAIN
2026-01-29 03:43:13.091 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETRXGAIN
2026-01-29 03:43:13.091 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETRXGAIN
2026-01-29 03:43:13.091 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETTSC
2026-01-29 03:43:13.091 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:43:13.091 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:43:13.091 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.28.20:5700) Recv NOMTXPOWER cmd
2026-01-29 03:43:13.091 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:43:13.091 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:43:13.091 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:43:13.091 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.28.20:5700) Recv POWERON CMD
2026-01-29 03:43:13.091 [INFO] ctrl_if_trx.py:109 (BTS@172.18.28.20:5700) Starting transceiver...
2026-01-29 03:43:13.092 [INFO] transceiver.py:243 Starting clock generator
2026-01-29 03:43:13.092 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-01-29 03:43:13.092 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:43:13.092 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:43:13.092 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:43:13.092 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETRXGAIN
2026-01-29 03:43:13.092 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:43:13.092 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:43:13.092 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:43:13.092 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:43:13.092 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:43:13.092 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:43:13.092 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:43:13.092 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:43:13.092 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:43:13.092 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:43:13.092 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:43:13.092 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:43:13.092 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:43:13.092 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:43:13.092 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:43:13.092 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:43:13.092 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:43:13.092 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:43:13.092 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:43:13.092 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:43:13.092 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:43:13.092 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:43:13.093 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:43:13.093 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:43:13.096 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-01-29 03:43:13.564 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-01-29 03:43:13.622 [DEBUG] fake_trx.py:278 (BTS@172.18.28.20:5700) Recv FAKE_TOA cmd
2026-01-29 03:43:13.623 [DEBUG] fake_trx.py:297 (BTS@172.18.28.20:5700) Recv FAKE_RSSI cmd
2026-01-29 03:43:13.624 [DEBUG] fake_trx.py:322 (BTS@172.18.28.20:5700) Recv FAKE_CI cmd
2026-01-29 03:43:13.625 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:43:13.643 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 03:43:13.643 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 03:43:13.643 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 03:43:13.663 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 03:43:13.663 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 03:43:13.663 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 03:43:13.663 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:43:13.666 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 03:43:13.666 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 03:43:13.667 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 03:43:13.667 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.28.22:6700) Recv POWERON CMD
2026-01-29 03:43:13.667 [INFO] ctrl_if_trx.py:109 (MS@172.18.28.22:6700) Starting transceiver...
2026-01-29 03:43:13.703 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 03:43:13.703 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 03:43:13.703 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 03:43:13.704 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 03:43:14.039 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-01-29 03:43:14.094 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:43:14.094 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 03:43:14.094 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:43:14.096 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:43:14.508 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-01-29 03:43:14.978 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-01-29 03:43:15.095 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 03:43:15.096 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:43:15.096 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:43:15.097 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:43:15.441 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 03:43:15.442 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:43:15.445 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 03:43:15.445 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 03:43:15.449 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-01-29 03:43:15.460 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 03:43:15.460 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 03:43:15.460 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 03:43:15.467 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 03:43:15.467 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 03:43:15.467 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 03:43:15.468 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:43:15.469 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 03:43:15.469 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 03:43:15.469 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 03:43:15.469 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.28.22:6700) Recv POWERON CMD
2026-01-29 03:43:15.469 [INFO] ctrl_if_trx.py:109 (MS@172.18.28.22:6700) Starting transceiver...
2026-01-29 03:43:15.493 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.28.22:6700) Recv SETFH cmd
2026-01-29 03:43:15.493 [INFO] transceiver.py:201 (MS@172.18.28.22:6700) Frequency hopping configured: hsn=5, maio=0, ma_len=4
2026-01-29 03:43:15.493 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 03:43:15.493 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 03:43:15.922 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-01-29 03:43:16.097 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:43:16.097 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:43:16.097 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 03:43:16.097 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:43:16.391 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-01-29 03:43:16.861 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-01-29 03:43:17.098 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:43:17.098 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 03:43:17.099 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:43:17.099 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:43:17.331 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-01-29 03:43:17.801 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-01-29 03:43:18.099 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:43:18.099 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 03:43:18.099 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:43:18.099 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:43:18.197 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 03:43:18.197 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:43:18.201 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 03:43:18.201 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 03:43:18.201 [INFO] transceiver.py:205 (MS@172.18.28.22:6700) Frequency hopping disabled
2026-01-29 03:43:18.219 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 03:43:18.219 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 03:43:18.219 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 03:43:18.227 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 03:43:18.227 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 03:43:18.227 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 03:43:18.227 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:43:18.228 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 03:43:18.229 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 03:43:18.229 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 03:43:18.229 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.28.22:6700) Recv POWERON CMD
2026-01-29 03:43:18.229 [INFO] ctrl_if_trx.py:109 (MS@172.18.28.22:6700) Starting transceiver...
2026-01-29 03:43:18.266 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 03:43:18.267 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 03:43:18.267 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 03:43:18.267 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 03:43:18.269 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-01-29 03:43:18.740 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-01-29 03:43:19.210 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-01-29 03:43:19.681 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-01-29 03:43:20.151 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-01-29 03:43:20.622 [DEBUG] clck_gen.py:113 IND CLOCK 1632
2026-01-29 03:43:21.093 [DEBUG] clck_gen.py:113 IND CLOCK 1734
2026-01-29 03:43:21.564 [DEBUG] clck_gen.py:113 IND CLOCK 1836
2026-01-29 03:43:22.035 [DEBUG] clck_gen.py:113 IND CLOCK 1938
2026-01-29 03:43:22.506 [DEBUG] clck_gen.py:113 IND CLOCK 2040
2026-01-29 03:43:22.660 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 03:43:22.661 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:43:22.665 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 03:43:22.665 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 03:43:22.684 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 03:43:22.684 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 03:43:22.684 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 03:43:22.692 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 03:43:22.692 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 03:43:22.692 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 03:43:22.693 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:43:22.694 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 03:43:22.694 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 03:43:22.694 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 03:43:22.694 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.28.22:6700) Recv POWERON CMD
2026-01-29 03:43:22.694 [INFO] ctrl_if_trx.py:109 (MS@172.18.28.22:6700) Starting transceiver...
2026-01-29 03:43:22.740 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.28.22:6700) Recv SETFH cmd
2026-01-29 03:43:22.740 [INFO] transceiver.py:201 (MS@172.18.28.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2026-01-29 03:43:22.740 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 03:43:22.740 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 03:43:22.976 [DEBUG] clck_gen.py:113 IND CLOCK 2142
2026-01-29 03:43:23.450 [DEBUG] clck_gen.py:113 IND CLOCK 2244
2026-01-29 03:43:23.930 [DEBUG] clck_gen.py:113 IND CLOCK 2346
2026-01-29 03:43:24.409 [DEBUG] clck_gen.py:113 IND CLOCK 2448
2026-01-29 03:43:24.888 [DEBUG] clck_gen.py:113 IND CLOCK 2550
2026-01-29 03:43:24.973 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 03:43:24.973 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 03:43:24.973 [INFO] transceiver.py:205 (MS@172.18.28.22:6700) Frequency hopping disabled
2026-01-29 03:43:24.976 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 03:43:24.976 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:43:24.976 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:43:24.976 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:43:24.978 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 03:43:24.978 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 03:43:24.978 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.28.20:5700) Recv POWEROFF cmd
2026-01-29 03:43:24.978 [INFO] ctrl_if_trx.py:117 (BTS@172.18.28.20:5700) Stopping transceiver...
2026-01-29 03:43:24.978 [INFO] transceiver.py:246 Stopping clock generator
2026-01-29 03:43:24.978 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 03:43:24.978 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 03:43:24.978 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=2571 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:43:24.978 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=2571 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:43:24.978 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=2571 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:43:24.978 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=2571 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:43:24.978 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=2571 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:43:24.978 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=2571 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:43:24.978 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=2571 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:43:29.983 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.28.20:5700) Recv POWEROFF cmd
2026-01-29 03:43:29.983 [INFO] ctrl_if_trx.py:117 (BTS@172.18.28.20:5700) Stopping transceiver...
2026-01-29 03:43:29.983 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 03:43:29.983 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 03:43:29.983 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 03:43:29.983 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 03:43:29.985 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 03:43:29.986 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.28.20:5700) Recv SETFORMAT cmd
2026-01-29 03:43:29.986 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.28.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:43:29.986 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.28.20:5700) Recv SETFORMAT cmd
2026-01-29 03:43:29.986 [INFO] ctrl_if_trx.py:201 (BTS@172.18.28.20:5700) TRXD header version 1 -> 1
2026-01-29 03:43:29.987 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.28.20:5700/1) Recv RXTUNE cmd
2026-01-29 03:43:29.987 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.28.20:5700/1) Recv TXTUNE cmd
2026-01-29 03:43:29.987 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.28.20:5700/1) Recv SETFORMAT cmd
2026-01-29 03:43:29.987 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.28.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:43:29.987 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 03:43:29.988 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.28.20:5700/1) Recv NOMTXPOWER cmd
2026-01-29 03:43:29.988 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.28.20:5700/1) Recv SETFORMAT cmd
2026-01-29 03:43:29.988 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.28.20:5700/1) TRXD header version 1 -> 1
2026-01-29 03:43:29.990 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.28.20:5700/2) Recv RXTUNE cmd
2026-01-29 03:43:29.990 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.28.20:5700/2) Recv TXTUNE cmd
2026-01-29 03:43:29.991 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.28.20:5700/2) Recv SETFORMAT cmd
2026-01-29 03:43:29.991 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.28.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:43:29.991 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 03:43:29.991 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.28.20:5700/2) Recv NOMTXPOWER cmd
2026-01-29 03:43:29.991 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.28.20:5700/2) Recv SETFORMAT cmd
2026-01-29 03:43:29.991 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.28.20:5700/2) TRXD header version 1 -> 1
2026-01-29 03:43:29.993 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.28.20:5700/3) Recv RXTUNE cmd
2026-01-29 03:43:29.993 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.28.20:5700/3) Recv TXTUNE cmd
2026-01-29 03:43:29.993 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.28.20:5700/3) Recv SETFORMAT cmd
2026-01-29 03:43:29.993 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.28.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:43:29.993 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 03:43:29.993 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.28.20:5700/3) Recv NOMTXPOWER cmd
2026-01-29 03:43:29.993 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.28.20:5700/3) Recv SETFORMAT cmd
2026-01-29 03:43:29.993 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.28.20:5700/3) TRXD header version 1 -> 1
2026-01-29 03:43:29.996 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.28.20:5700) Recv RXTUNE cmd
2026-01-29 03:43:29.996 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETTSC
2026-01-29 03:43:29.996 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETTSC
2026-01-29 03:43:29.996 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETTSC
2026-01-29 03:43:29.996 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.28.20:5700) Recv TXTUNE cmd
2026-01-29 03:43:29.996 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETRXGAIN
2026-01-29 03:43:29.996 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETRXGAIN
2026-01-29 03:43:29.996 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETRXGAIN
2026-01-29 03:43:29.996 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETTSC
2026-01-29 03:43:29.996 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:43:29.996 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:43:29.996 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.28.20:5700) Recv NOMTXPOWER cmd
2026-01-29 03:43:29.996 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:43:29.996 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:43:29.996 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.28.20:5700) Recv POWERON CMD
2026-01-29 03:43:29.996 [INFO] ctrl_if_trx.py:109 (BTS@172.18.28.20:5700) Starting transceiver...
2026-01-29 03:43:29.996 [INFO] transceiver.py:243 Starting clock generator
2026-01-29 03:43:29.996 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-01-29 03:43:29.996 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:43:29.996 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:43:29.996 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:43:29.996 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETRXGAIN
2026-01-29 03:43:29.996 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:43:29.996 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:43:29.996 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:43:29.996 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:43:29.997 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:43:29.997 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:43:29.997 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:43:29.997 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:43:29.997 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:43:29.997 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:43:29.997 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:43:29.997 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:43:29.997 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:43:29.997 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:43:29.997 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:43:29.997 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:43:29.997 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:43:29.997 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:43:29.997 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:43:29.997 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:43:29.997 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:43:29.997 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:43:29.997 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:43:29.997 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:43:29.997 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:43:30.001 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-01-29 03:43:30.476 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-01-29 03:43:30.523 [DEBUG] fake_trx.py:278 (BTS@172.18.28.20:5700) Recv FAKE_TOA cmd
2026-01-29 03:43:30.525 [DEBUG] fake_trx.py:297 (BTS@172.18.28.20:5700) Recv FAKE_RSSI cmd
2026-01-29 03:43:30.526 [DEBUG] fake_trx.py:322 (BTS@172.18.28.20:5700) Recv FAKE_CI cmd
2026-01-29 03:43:30.527 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:43:30.554 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:43:30.566 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:43:30.859 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:43:30.869 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:43:30.885 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:43:30.890 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:43:30.951 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-01-29 03:43:31.001 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:43:31.001 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 03:43:31.002 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:43:31.004 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:43:31.188 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:43:31.192 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:43:31.205 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:43:31.210 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:43:31.426 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-01-29 03:43:31.508 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:43:31.512 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:43:31.534 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:43:31.539 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:43:31.838 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:43:31.841 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:43:31.853 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 03:43:31.853 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:43:31.853 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:43:31.853 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:43:31.854 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 03:43:31.854 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 03:43:31.854 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 03:43:31.854 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 03:43:31.854 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.28.20:5700) Recv POWEROFF cmd
2026-01-29 03:43:31.854 [INFO] ctrl_if_trx.py:117 (BTS@172.18.28.20:5700) Stopping transceiver...
2026-01-29 03:43:31.854 [INFO] transceiver.py:246 Stopping clock generator
2026-01-29 03:43:31.854 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=400 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:43:31.854 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=400 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:43:31.854 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=400 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:43:31.854 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=400 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:43:31.854 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=400 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:43:31.854 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=400 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:43:31.854 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=400 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:43:36.856 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.28.20:5700) Recv POWEROFF cmd
2026-01-29 03:43:36.856 [INFO] ctrl_if_trx.py:117 (BTS@172.18.28.20:5700) Stopping transceiver...
2026-01-29 03:43:36.857 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 03:43:36.861 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 03:43:36.861 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 03:43:36.861 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 03:43:36.874 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 03:43:36.875 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.28.20:5700) Recv SETFORMAT cmd
2026-01-29 03:43:36.875 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.28.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:43:36.875 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.28.20:5700) Recv SETFORMAT cmd
2026-01-29 03:43:36.875 [INFO] ctrl_if_trx.py:201 (BTS@172.18.28.20:5700) TRXD header version 1 -> 1
2026-01-29 03:43:36.878 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.28.20:5700/1) Recv RXTUNE cmd
2026-01-29 03:43:36.878 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.28.20:5700/1) Recv TXTUNE cmd
2026-01-29 03:43:36.878 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.28.20:5700/1) Recv SETFORMAT cmd
2026-01-29 03:43:36.878 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.28.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:43:36.878 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 03:43:36.878 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.28.20:5700/1) Recv NOMTXPOWER cmd
2026-01-29 03:43:36.878 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.28.20:5700/1) Recv SETFORMAT cmd
2026-01-29 03:43:36.878 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.28.20:5700/1) TRXD header version 1 -> 1
2026-01-29 03:43:36.881 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.28.20:5700/2) Recv RXTUNE cmd
2026-01-29 03:43:36.881 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.28.20:5700/2) Recv TXTUNE cmd
2026-01-29 03:43:36.881 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.28.20:5700/2) Recv SETFORMAT cmd
2026-01-29 03:43:36.881 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.28.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:43:36.881 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 03:43:36.881 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.28.20:5700/2) Recv NOMTXPOWER cmd
2026-01-29 03:43:36.881 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.28.20:5700/2) Recv SETFORMAT cmd
2026-01-29 03:43:36.881 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.28.20:5700/2) TRXD header version 1 -> 1
2026-01-29 03:43:36.883 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.28.20:5700/3) Recv RXTUNE cmd
2026-01-29 03:43:36.883 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.28.20:5700/3) Recv TXTUNE cmd
2026-01-29 03:43:36.883 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.28.20:5700/3) Recv SETFORMAT cmd
2026-01-29 03:43:36.883 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.28.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:43:36.883 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 03:43:36.883 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.28.20:5700/3) Recv NOMTXPOWER cmd
2026-01-29 03:43:36.883 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.28.20:5700/3) Recv SETFORMAT cmd
2026-01-29 03:43:36.883 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.28.20:5700/3) TRXD header version 1 -> 1
2026-01-29 03:43:36.886 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.28.20:5700) Recv RXTUNE cmd
2026-01-29 03:43:36.886 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETTSC
2026-01-29 03:43:36.886 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETTSC
2026-01-29 03:43:36.886 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETTSC
2026-01-29 03:43:36.886 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.28.20:5700) Recv TXTUNE cmd
2026-01-29 03:43:36.886 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETRXGAIN
2026-01-29 03:43:36.886 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETRXGAIN
2026-01-29 03:43:36.886 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETRXGAIN
2026-01-29 03:43:36.886 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETTSC
2026-01-29 03:43:36.887 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:43:36.887 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:43:36.887 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.28.20:5700) Recv NOMTXPOWER cmd
2026-01-29 03:43:36.887 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:43:36.887 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:43:36.887 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:43:36.887 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.28.20:5700) Recv POWERON CMD
2026-01-29 03:43:36.887 [INFO] ctrl_if_trx.py:109 (BTS@172.18.28.20:5700) Starting transceiver...
2026-01-29 03:43:36.887 [INFO] transceiver.py:243 Starting clock generator
2026-01-29 03:43:36.887 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-01-29 03:43:36.887 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:43:36.887 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:43:36.887 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:43:36.887 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETRXGAIN
2026-01-29 03:43:36.887 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:43:36.887 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:43:36.887 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:43:36.887 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:43:36.887 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:43:36.887 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:43:36.887 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:43:36.887 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:43:36.887 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:43:36.887 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:43:36.887 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:43:36.887 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:43:36.887 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:43:36.887 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:43:36.888 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:43:36.888 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:43:36.888 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:43:36.888 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:43:36.888 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:43:36.888 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:43:36.888 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:43:36.888 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:43:36.888 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:43:36.888 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:43:36.892 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-01-29 03:43:37.362 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-01-29 03:43:37.421 [DEBUG] fake_trx.py:278 (BTS@172.18.28.20:5700) Recv FAKE_TOA cmd
2026-01-29 03:43:37.423 [DEBUG] fake_trx.py:297 (BTS@172.18.28.20:5700) Recv FAKE_RSSI cmd
2026-01-29 03:43:37.424 [DEBUG] fake_trx.py:322 (BTS@172.18.28.20:5700) Recv FAKE_CI cmd
2026-01-29 03:43:37.425 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:43:37.443 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:43:37.450 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:43:37.456 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:43:37.461 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:43:37.747 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:43:37.752 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:43:37.758 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:43:37.764 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:43:37.775 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:43:37.781 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:43:37.784 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:43:37.788 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:43:37.831 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-01-29 03:43:37.890 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:43:37.890 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 03:43:37.890 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:43:37.891 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:43:38.079 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:43:38.083 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:43:38.087 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:43:38.091 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:43:38.109 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:43:38.116 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:43:38.119 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:43:38.123 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:43:38.300 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-01-29 03:43:38.411 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:43:38.418 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:43:38.421 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:43:38.424 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:43:38.432 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:43:38.437 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:43:38.441 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:43:38.445 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:43:38.735 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:43:38.739 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:43:38.742 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:43:38.747 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:43:38.757 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 03:43:38.757 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:43:38.757 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:43:38.758 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:43:38.761 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 03:43:38.761 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 03:43:38.761 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 03:43:38.761 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.28.20:5700) Recv POWEROFF cmd
2026-01-29 03:43:38.762 [INFO] ctrl_if_trx.py:117 (BTS@172.18.28.20:5700) Stopping transceiver...
2026-01-29 03:43:38.762 [INFO] transceiver.py:246 Stopping clock generator
2026-01-29 03:43:38.762 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 03:43:38.762 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=407 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:43:38.762 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=407 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:43:38.762 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=407 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:43:38.763 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=407 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:43:38.763 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=407 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:43:38.763 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=407 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:43:38.763 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=407 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:43:38.763 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=407 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:43:38.763 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=408 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:43:38.763 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=408 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:43:38.763 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=408 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:43:38.763 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=408 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:43:38.763 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=408 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:43:38.764 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=408 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:43:38.764 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=408 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:43:38.764 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=408 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:43:43.761 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.28.20:5700) Recv POWEROFF cmd
2026-01-29 03:43:43.761 [INFO] ctrl_if_trx.py:117 (BTS@172.18.28.20:5700) Stopping transceiver...
2026-01-29 03:43:43.762 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 03:43:43.763 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 03:43:43.765 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 03:43:43.766 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 03:43:43.776 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 03:43:43.777 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.28.20:5700) Recv SETFORMAT cmd
2026-01-29 03:43:43.777 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.28.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:43:43.778 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.28.20:5700) Recv SETFORMAT cmd
2026-01-29 03:43:43.778 [INFO] ctrl_if_trx.py:201 (BTS@172.18.28.20:5700) TRXD header version 1 -> 1
2026-01-29 03:43:43.781 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.28.20:5700/1) Recv RXTUNE cmd
2026-01-29 03:43:43.781 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.28.20:5700/1) Recv TXTUNE cmd
2026-01-29 03:43:43.781 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.28.20:5700/1) Recv SETFORMAT cmd
2026-01-29 03:43:43.781 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.28.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:43:43.781 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 03:43:43.781 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.28.20:5700/1) Recv NOMTXPOWER cmd
2026-01-29 03:43:43.781 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.28.20:5700/1) Recv SETFORMAT cmd
2026-01-29 03:43:43.781 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.28.20:5700/1) TRXD header version 1 -> 1
2026-01-29 03:43:43.783 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.28.20:5700/2) Recv RXTUNE cmd
2026-01-29 03:43:43.783 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.28.20:5700/2) Recv TXTUNE cmd
2026-01-29 03:43:43.783 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.28.20:5700/2) Recv SETFORMAT cmd
2026-01-29 03:43:43.783 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.28.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:43:43.784 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 03:43:43.784 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.28.20:5700/2) Recv NOMTXPOWER cmd
2026-01-29 03:43:43.784 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.28.20:5700/2) Recv SETFORMAT cmd
2026-01-29 03:43:43.784 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.28.20:5700/2) TRXD header version 1 -> 1
2026-01-29 03:43:43.785 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.28.20:5700/3) Recv RXTUNE cmd
2026-01-29 03:43:43.785 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.28.20:5700/3) Recv TXTUNE cmd
2026-01-29 03:43:43.785 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.28.20:5700/3) Recv SETFORMAT cmd
2026-01-29 03:43:43.785 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.28.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:43:43.785 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 03:43:43.786 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.28.20:5700/3) Recv NOMTXPOWER cmd
2026-01-29 03:43:43.786 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.28.20:5700/3) Recv SETFORMAT cmd
2026-01-29 03:43:43.786 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.28.20:5700/3) TRXD header version 1 -> 1
2026-01-29 03:43:43.787 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.28.20:5700) Recv RXTUNE cmd
2026-01-29 03:43:43.787 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETTSC
2026-01-29 03:43:43.787 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETTSC
2026-01-29 03:43:43.787 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETTSC
2026-01-29 03:43:43.787 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.28.20:5700) Recv TXTUNE cmd
2026-01-29 03:43:43.788 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETRXGAIN
2026-01-29 03:43:43.788 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETRXGAIN
2026-01-29 03:43:43.788 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETRXGAIN
2026-01-29 03:43:43.788 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETTSC
2026-01-29 03:43:43.788 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:43:43.788 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:43:43.788 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.28.20:5700) Recv NOMTXPOWER cmd
2026-01-29 03:43:43.788 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:43:43.788 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:43:43.788 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:43:43.788 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.28.20:5700) Recv POWERON CMD
2026-01-29 03:43:43.788 [INFO] ctrl_if_trx.py:109 (BTS@172.18.28.20:5700) Starting transceiver...
2026-01-29 03:43:43.788 [INFO] transceiver.py:243 Starting clock generator
2026-01-29 03:43:43.788 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-01-29 03:43:43.788 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:43:43.788 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:43:43.788 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:43:43.788 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETRXGAIN
2026-01-29 03:43:43.788 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:43:43.788 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:43:43.788 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:43:43.788 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:43:43.788 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:43:43.788 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:43:43.788 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:43:43.788 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:43:43.788 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:43:43.788 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:43:43.788 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:43:43.788 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:43:43.788 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:43:43.788 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:43:43.788 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:43:43.788 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:43:43.788 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:43:43.789 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:43:43.789 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:43:43.789 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:43:43.789 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:43:43.789 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:43:43.789 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:43:43.789 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:43:43.793 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-01-29 03:43:44.269 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-01-29 03:43:44.309 [DEBUG] fake_trx.py:278 (BTS@172.18.28.20:5700) Recv FAKE_TOA cmd
2026-01-29 03:43:44.311 [DEBUG] fake_trx.py:297 (BTS@172.18.28.20:5700) Recv FAKE_RSSI cmd
2026-01-29 03:43:44.312 [DEBUG] fake_trx.py:322 (BTS@172.18.28.20:5700) Recv FAKE_CI cmd
2026-01-29 03:43:44.313 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:43:44.333 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:43:44.338 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:43:44.344 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:43:44.636 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:43:44.640 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:43:44.647 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:43:44.663 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:43:44.669 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:43:44.673 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:43:44.745 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-01-29 03:43:44.790 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:43:44.791 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 03:43:44.791 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:43:44.793 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:43:44.967 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:43:44.972 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:43:44.974 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:43:44.991 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:43:44.995 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:43:45.000 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:43:45.217 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-01-29 03:43:45.294 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:43:45.298 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:43:45.301 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:43:45.317 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:43:45.321 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:43:45.326 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:43:45.620 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:43:45.625 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:43:45.628 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:43:45.640 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 03:43:45.640 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:43:45.640 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:43:45.640 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:43:45.644 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 03:43:45.644 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 03:43:45.644 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 03:43:45.644 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 03:43:45.644 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.28.20:5700) Recv POWEROFF cmd
2026-01-29 03:43:45.644 [INFO] ctrl_if_trx.py:117 (BTS@172.18.28.20:5700) Stopping transceiver...
2026-01-29 03:43:45.645 [INFO] transceiver.py:246 Stopping clock generator
2026-01-29 03:43:45.645 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=400 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:43:45.645 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=400 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:43:45.645 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=400 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:43:45.645 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=400 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:43:45.645 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=400 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:43:45.646 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=400 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:43:45.646 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=400 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:43:50.643 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.28.20:5700) Recv POWEROFF cmd
2026-01-29 03:43:50.643 [INFO] ctrl_if_trx.py:117 (BTS@172.18.28.20:5700) Stopping transceiver...
2026-01-29 03:43:50.644 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 03:43:50.646 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 03:43:50.646 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 03:43:50.646 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 03:43:50.654 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 03:43:50.654 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.28.20:5700) Recv SETFORMAT cmd
2026-01-29 03:43:50.654 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.28.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:43:50.655 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.28.20:5700) Recv SETFORMAT cmd
2026-01-29 03:43:50.655 [INFO] ctrl_if_trx.py:201 (BTS@172.18.28.20:5700) TRXD header version 1 -> 1
2026-01-29 03:43:50.657 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.28.20:5700/1) Recv RXTUNE cmd
2026-01-29 03:43:50.657 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.28.20:5700/1) Recv TXTUNE cmd
2026-01-29 03:43:50.657 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.28.20:5700/1) Recv SETFORMAT cmd
2026-01-29 03:43:50.657 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.28.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:43:50.658 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 03:43:50.658 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.28.20:5700/1) Recv NOMTXPOWER cmd
2026-01-29 03:43:50.658 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.28.20:5700/1) Recv SETFORMAT cmd
2026-01-29 03:43:50.658 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.28.20:5700/1) TRXD header version 1 -> 1
2026-01-29 03:43:50.659 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.28.20:5700/2) Recv RXTUNE cmd
2026-01-29 03:43:50.659 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.28.20:5700/2) Recv TXTUNE cmd
2026-01-29 03:43:50.659 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.28.20:5700/2) Recv SETFORMAT cmd
2026-01-29 03:43:50.659 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.28.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:43:50.659 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 03:43:50.659 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.28.20:5700/2) Recv NOMTXPOWER cmd
2026-01-29 03:43:50.660 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.28.20:5700/2) Recv SETFORMAT cmd
2026-01-29 03:43:50.660 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.28.20:5700/2) TRXD header version 1 -> 1
2026-01-29 03:43:50.661 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.28.20:5700/3) Recv RXTUNE cmd
2026-01-29 03:43:50.661 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.28.20:5700/3) Recv TXTUNE cmd
2026-01-29 03:43:50.661 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.28.20:5700/3) Recv SETFORMAT cmd
2026-01-29 03:43:50.661 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.28.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:43:50.661 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 03:43:50.661 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.28.20:5700/3) Recv NOMTXPOWER cmd
2026-01-29 03:43:50.662 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.28.20:5700/3) Recv SETFORMAT cmd
2026-01-29 03:43:50.662 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.28.20:5700/3) TRXD header version 1 -> 1
2026-01-29 03:43:50.664 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.28.20:5700) Recv RXTUNE cmd
2026-01-29 03:43:50.664 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETTSC
2026-01-29 03:43:50.664 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETTSC
2026-01-29 03:43:50.664 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETTSC
2026-01-29 03:43:50.664 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.28.20:5700) Recv TXTUNE cmd
2026-01-29 03:43:50.664 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETRXGAIN
2026-01-29 03:43:50.664 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETRXGAIN
2026-01-29 03:43:50.664 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETRXGAIN
2026-01-29 03:43:50.664 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETTSC
2026-01-29 03:43:50.664 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:43:50.664 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:43:50.664 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.28.20:5700) Recv NOMTXPOWER cmd
2026-01-29 03:43:50.664 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:43:50.664 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:43:50.664 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:43:50.664 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.28.20:5700) Recv POWERON CMD
2026-01-29 03:43:50.664 [INFO] ctrl_if_trx.py:109 (BTS@172.18.28.20:5700) Starting transceiver...
2026-01-29 03:43:50.664 [INFO] transceiver.py:243 Starting clock generator
2026-01-29 03:43:50.664 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-01-29 03:43:50.665 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:43:50.665 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:43:50.665 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:43:50.665 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETRXGAIN
2026-01-29 03:43:50.665 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:43:50.665 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:43:50.665 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:43:50.665 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:43:50.665 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:43:50.665 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:43:50.665 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:43:50.665 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:43:50.665 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:43:50.665 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:43:50.665 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:43:50.665 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:43:50.665 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:43:50.665 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:43:50.665 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:43:50.665 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:43:50.665 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:43:50.665 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:43:50.665 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:43:50.665 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:43:50.665 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:43:50.665 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:43:50.666 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:43:50.666 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:43:50.669 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-01-29 03:43:51.146 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-01-29 03:43:51.196 [DEBUG] fake_trx.py:278 (BTS@172.18.28.20:5700) Recv FAKE_TOA cmd
2026-01-29 03:43:51.198 [DEBUG] fake_trx.py:297 (BTS@172.18.28.20:5700) Recv FAKE_RSSI cmd
2026-01-29 03:43:51.199 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:43:51.199 [DEBUG] fake_trx.py:322 (BTS@172.18.28.20:5700) Recv FAKE_CI cmd
2026-01-29 03:43:51.229 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:43:51.235 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:43:51.533 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:43:51.539 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:43:51.559 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:43:51.564 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:43:51.619 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-01-29 03:43:51.668 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 03:43:51.668 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:43:51.668 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:43:51.670 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:43:51.861 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:43:51.866 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:43:51.886 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:43:51.891 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:43:52.092 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-01-29 03:43:52.189 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:43:52.194 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:43:52.212 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:43:52.216 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:43:52.515 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:43:52.518 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:43:52.532 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 03:43:52.533 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:43:52.533 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:43:52.533 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:43:52.536 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 03:43:52.536 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 03:43:52.536 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 03:43:52.536 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 03:43:52.536 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.28.20:5700) Recv POWEROFF cmd
2026-01-29 03:43:52.536 [INFO] ctrl_if_trx.py:117 (BTS@172.18.28.20:5700) Stopping transceiver...
2026-01-29 03:43:52.536 [INFO] transceiver.py:246 Stopping clock generator
2026-01-29 03:43:52.536 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=404 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:43:52.536 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=404 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:43:52.536 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=404 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:43:52.536 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=404 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:43:52.536 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=404 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:43:52.536 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=404 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:43:52.536 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=404 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:43:52.536 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=405 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:43:52.536 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=405 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:43:52.536 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=405 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:43:52.536 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=405 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:43:52.536 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=405 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:43:52.536 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=405 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:43:52.536 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=405 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:43:52.536 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=405 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:43:57.536 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.28.20:5700) Recv POWEROFF cmd
2026-01-29 03:43:57.536 [INFO] ctrl_if_trx.py:117 (BTS@172.18.28.20:5700) Stopping transceiver...
2026-01-29 03:43:57.537 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 03:43:57.539 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 03:43:57.540 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 03:43:57.540 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 03:43:57.550 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 03:43:57.551 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.28.20:5700) Recv SETFORMAT cmd
2026-01-29 03:43:57.552 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.28.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:43:57.552 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.28.20:5700) Recv SETFORMAT cmd
2026-01-29 03:43:57.552 [INFO] ctrl_if_trx.py:201 (BTS@172.18.28.20:5700) TRXD header version 1 -> 1
2026-01-29 03:43:57.555 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.28.20:5700/1) Recv RXTUNE cmd
2026-01-29 03:43:57.555 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.28.20:5700/1) Recv TXTUNE cmd
2026-01-29 03:43:57.556 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.28.20:5700/1) Recv SETFORMAT cmd
2026-01-29 03:43:57.556 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.28.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:43:57.556 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 03:43:57.556 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.28.20:5700/1) Recv NOMTXPOWER cmd
2026-01-29 03:43:57.556 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.28.20:5700/1) Recv SETFORMAT cmd
2026-01-29 03:43:57.556 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.28.20:5700/1) TRXD header version 1 -> 1
2026-01-29 03:43:57.559 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.28.20:5700/2) Recv RXTUNE cmd
2026-01-29 03:43:57.559 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.28.20:5700/2) Recv TXTUNE cmd
2026-01-29 03:43:57.559 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.28.20:5700/2) Recv SETFORMAT cmd
2026-01-29 03:43:57.559 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.28.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:43:57.559 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 03:43:57.560 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.28.20:5700/2) Recv NOMTXPOWER cmd
2026-01-29 03:43:57.560 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.28.20:5700/2) Recv SETFORMAT cmd
2026-01-29 03:43:57.560 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.28.20:5700/2) TRXD header version 1 -> 1
2026-01-29 03:43:57.562 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.28.20:5700/3) Recv RXTUNE cmd
2026-01-29 03:43:57.562 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.28.20:5700/3) Recv TXTUNE cmd
2026-01-29 03:43:57.562 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.28.20:5700/3) Recv SETFORMAT cmd
2026-01-29 03:43:57.562 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.28.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:43:57.563 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 03:43:57.563 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.28.20:5700/3) Recv NOMTXPOWER cmd
2026-01-29 03:43:57.563 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.28.20:5700/3) Recv SETFORMAT cmd
2026-01-29 03:43:57.563 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.28.20:5700/3) TRXD header version 1 -> 1
2026-01-29 03:43:57.566 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.28.20:5700) Recv RXTUNE cmd
2026-01-29 03:43:57.566 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETTSC
2026-01-29 03:43:57.566 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETTSC
2026-01-29 03:43:57.566 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.28.20:5700) Recv TXTUNE cmd
2026-01-29 03:43:57.566 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETTSC
2026-01-29 03:43:57.566 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETRXGAIN
2026-01-29 03:43:57.566 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETRXGAIN
2026-01-29 03:43:57.566 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETTSC
2026-01-29 03:43:57.566 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETRXGAIN
2026-01-29 03:43:57.566 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:43:57.567 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:43:57.567 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.28.20:5700) Recv NOMTXPOWER cmd
2026-01-29 03:43:57.567 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:43:57.567 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:43:57.567 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:43:57.567 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.28.20:5700) Recv POWERON CMD
2026-01-29 03:43:57.567 [INFO] ctrl_if_trx.py:109 (BTS@172.18.28.20:5700) Starting transceiver...
2026-01-29 03:43:57.567 [INFO] transceiver.py:243 Starting clock generator
2026-01-29 03:43:57.567 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-01-29 03:43:57.567 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:43:57.567 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:43:57.567 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:43:57.567 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETRXGAIN
2026-01-29 03:43:57.567 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:43:57.567 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:43:57.567 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:43:57.567 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:43:57.567 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:43:57.567 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:43:57.567 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:43:57.567 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:43:57.568 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:43:57.568 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:43:57.568 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:43:57.568 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:43:57.568 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:43:57.568 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:43:57.568 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:43:57.568 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:43:57.568 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:43:57.568 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:43:57.568 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:43:57.568 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:43:57.568 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:43:57.568 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:43:57.568 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:43:57.568 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:43:57.572 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-01-29 03:43:58.049 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-01-29 03:43:58.101 [DEBUG] fake_trx.py:278 (BTS@172.18.28.20:5700) Recv FAKE_TOA cmd
2026-01-29 03:43:58.103 [DEBUG] fake_trx.py:297 (BTS@172.18.28.20:5700) Recv FAKE_RSSI cmd
2026-01-29 03:43:58.103 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:43:58.105 [DEBUG] fake_trx.py:322 (BTS@172.18.28.20:5700) Recv FAKE_CI cmd
2026-01-29 03:43:58.125 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:43:58.125 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:43:58.131 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:43:58.428 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:43:58.435 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:43:58.451 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:43:58.456 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:43:58.524 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-01-29 03:43:58.570 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 03:43:58.570 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:43:58.571 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:43:58.576 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:43:58.755 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:43:58.758 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:43:58.781 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:43:58.786 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:43:58.992 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-01-29 03:43:59.084 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:43:59.089 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:43:59.112 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:43:59.116 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:43:59.414 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:43:59.417 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:43:59.420 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 03:43:59.420 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:43:59.420 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:43:59.420 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:43:59.422 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 03:43:59.422 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 03:43:59.422 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 03:43:59.422 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 03:43:59.422 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.28.20:5700) Recv POWEROFF cmd
2026-01-29 03:43:59.422 [INFO] ctrl_if_trx.py:117 (BTS@172.18.28.20:5700) Stopping transceiver...
2026-01-29 03:43:59.422 [INFO] transceiver.py:246 Stopping clock generator
2026-01-29 03:43:59.422 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=401 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:43:59.422 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=401 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:43:59.422 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=401 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:43:59.423 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=401 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:43:59.423 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=401 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:43:59.423 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=401 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:43:59.423 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=401 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:44:04.428 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.28.20:5700) Recv POWEROFF cmd
2026-01-29 03:44:04.428 [INFO] ctrl_if_trx.py:117 (BTS@172.18.28.20:5700) Stopping transceiver...
2026-01-29 03:44:04.428 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 03:44:04.428 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 03:44:04.428 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 03:44:04.428 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 03:44:04.439 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 03:44:04.440 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.28.20:5700) Recv SETFORMAT cmd
2026-01-29 03:44:04.440 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.28.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:44:04.440 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.28.20:5700) Recv SETFORMAT cmd
2026-01-29 03:44:04.440 [INFO] ctrl_if_trx.py:201 (BTS@172.18.28.20:5700) TRXD header version 1 -> 1
2026-01-29 03:44:04.441 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.28.20:5700/1) Recv RXTUNE cmd
2026-01-29 03:44:04.441 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.28.20:5700/1) Recv TXTUNE cmd
2026-01-29 03:44:04.442 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.28.20:5700/1) Recv SETFORMAT cmd
2026-01-29 03:44:04.442 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.28.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:44:04.442 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 03:44:04.442 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.28.20:5700/1) Recv NOMTXPOWER cmd
2026-01-29 03:44:04.442 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.28.20:5700/1) Recv SETFORMAT cmd
2026-01-29 03:44:04.442 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.28.20:5700/1) TRXD header version 1 -> 1
2026-01-29 03:44:04.443 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.28.20:5700/2) Recv RXTUNE cmd
2026-01-29 03:44:04.443 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.28.20:5700/2) Recv TXTUNE cmd
2026-01-29 03:44:04.443 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.28.20:5700/2) Recv SETFORMAT cmd
2026-01-29 03:44:04.443 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.28.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:44:04.443 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 03:44:04.444 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.28.20:5700/2) Recv NOMTXPOWER cmd
2026-01-29 03:44:04.444 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.28.20:5700/2) Recv SETFORMAT cmd
2026-01-29 03:44:04.444 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.28.20:5700/2) TRXD header version 1 -> 1
2026-01-29 03:44:04.445 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.28.20:5700/3) Recv RXTUNE cmd
2026-01-29 03:44:04.445 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.28.20:5700/3) Recv TXTUNE cmd
2026-01-29 03:44:04.445 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.28.20:5700/3) Recv SETFORMAT cmd
2026-01-29 03:44:04.445 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.28.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:44:04.445 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 03:44:04.445 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.28.20:5700/3) Recv NOMTXPOWER cmd
2026-01-29 03:44:04.445 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.28.20:5700/3) Recv SETFORMAT cmd
2026-01-29 03:44:04.445 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.28.20:5700/3) TRXD header version 1 -> 1
2026-01-29 03:44:04.447 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.28.20:5700) Recv RXTUNE cmd
2026-01-29 03:44:04.447 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETTSC
2026-01-29 03:44:04.447 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETTSC
2026-01-29 03:44:04.447 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETTSC
2026-01-29 03:44:04.447 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.28.20:5700) Recv TXTUNE cmd
2026-01-29 03:44:04.447 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETRXGAIN
2026-01-29 03:44:04.447 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETRXGAIN
2026-01-29 03:44:04.447 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETRXGAIN
2026-01-29 03:44:04.447 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETTSC
2026-01-29 03:44:04.447 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:44:04.447 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:44:04.447 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:44:04.447 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.28.20:5700) Recv NOMTXPOWER cmd
2026-01-29 03:44:04.447 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:44:04.447 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:44:04.447 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:44:04.447 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.28.20:5700) Recv POWERON CMD
2026-01-29 03:44:04.447 [INFO] ctrl_if_trx.py:109 (BTS@172.18.28.20:5700) Starting transceiver...
2026-01-29 03:44:04.447 [INFO] transceiver.py:243 Starting clock generator
2026-01-29 03:44:04.447 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-01-29 03:44:04.447 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:44:04.447 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:44:04.447 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:44:04.447 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETRXGAIN
2026-01-29 03:44:04.447 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:44:04.447 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:44:04.447 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:44:04.447 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:44:04.447 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:44:04.447 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:44:04.447 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:44:04.447 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:44:04.447 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:44:04.447 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:44:04.447 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:44:04.447 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:44:04.447 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:44:04.447 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:44:04.448 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:44:04.448 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:44:04.448 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:44:04.448 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:44:04.448 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:44:04.448 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:44:04.448 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:44:04.448 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:44:04.448 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:44:04.452 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-01-29 03:44:04.929 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-01-29 03:44:04.974 [DEBUG] fake_trx.py:278 (BTS@172.18.28.20:5700) Recv FAKE_TOA cmd
2026-01-29 03:44:04.976 [DEBUG] fake_trx.py:297 (BTS@172.18.28.20:5700) Recv FAKE_RSSI cmd
2026-01-29 03:44:04.978 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:44:04.978 [DEBUG] fake_trx.py:322 (BTS@172.18.28.20:5700) Recv FAKE_CI cmd
2026-01-29 03:44:05.006 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:44:05.007 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:44:05.014 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:44:05.020 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:44:05.026 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:44:05.311 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:44:05.317 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:44:05.323 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:44:05.328 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:44:05.342 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:44:05.347 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:44:05.351 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:44:05.355 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:44:05.402 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-01-29 03:44:05.450 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:44:05.450 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 03:44:05.450 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:44:05.452 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:44:05.646 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:44:05.650 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:44:05.654 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:44:05.658 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:44:05.685 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:44:05.691 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:44:05.695 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:44:05.698 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:44:05.874 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-01-29 03:44:05.990 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:44:05.994 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:44:05.997 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:44:06.000 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:44:06.008 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:44:06.013 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:44:06.017 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:44:06.021 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:44:06.311 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:44:06.316 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:44:06.320 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:44:06.323 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:44:06.329 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 03:44:06.329 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:44:06.330 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:44:06.330 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:44:06.330 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 03:44:06.330 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 03:44:06.330 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 03:44:06.330 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 03:44:06.330 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.28.20:5700) Recv POWEROFF cmd
2026-01-29 03:44:06.330 [INFO] ctrl_if_trx.py:117 (BTS@172.18.28.20:5700) Stopping transceiver...
2026-01-29 03:44:06.330 [INFO] transceiver.py:246 Stopping clock generator
2026-01-29 03:44:11.332 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.28.20:5700) Recv POWEROFF cmd
2026-01-29 03:44:11.333 [INFO] ctrl_if_trx.py:117 (BTS@172.18.28.20:5700) Stopping transceiver...
2026-01-29 03:44:11.334 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 03:44:11.335 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 03:44:11.336 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 03:44:11.336 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 03:44:11.343 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 03:44:11.343 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.28.20:5700) Recv SETFORMAT cmd
2026-01-29 03:44:11.343 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.28.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:44:11.344 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.28.20:5700) Recv SETFORMAT cmd
2026-01-29 03:44:11.344 [INFO] ctrl_if_trx.py:201 (BTS@172.18.28.20:5700) TRXD header version 1 -> 1
2026-01-29 03:44:11.346 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.28.20:5700/1) Recv RXTUNE cmd
2026-01-29 03:44:11.346 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.28.20:5700/1) Recv TXTUNE cmd
2026-01-29 03:44:11.346 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.28.20:5700/1) Recv SETFORMAT cmd
2026-01-29 03:44:11.346 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.28.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:44:11.346 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 03:44:11.346 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.28.20:5700/1) Recv NOMTXPOWER cmd
2026-01-29 03:44:11.346 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.28.20:5700/1) Recv SETFORMAT cmd
2026-01-29 03:44:11.346 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.28.20:5700/1) TRXD header version 1 -> 1
2026-01-29 03:44:11.348 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.28.20:5700/2) Recv RXTUNE cmd
2026-01-29 03:44:11.348 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.28.20:5700/2) Recv TXTUNE cmd
2026-01-29 03:44:11.348 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.28.20:5700/2) Recv SETFORMAT cmd
2026-01-29 03:44:11.348 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.28.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:44:11.348 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 03:44:11.349 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.28.20:5700/2) Recv NOMTXPOWER cmd
2026-01-29 03:44:11.349 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.28.20:5700/2) Recv SETFORMAT cmd
2026-01-29 03:44:11.349 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.28.20:5700/2) TRXD header version 1 -> 1
2026-01-29 03:44:11.350 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.28.20:5700/3) Recv RXTUNE cmd
2026-01-29 03:44:11.350 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.28.20:5700/3) Recv TXTUNE cmd
2026-01-29 03:44:11.350 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.28.20:5700/3) Recv SETFORMAT cmd
2026-01-29 03:44:11.350 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.28.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:44:11.350 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 03:44:11.351 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.28.20:5700/3) Recv NOMTXPOWER cmd
2026-01-29 03:44:11.351 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.28.20:5700/3) Recv SETFORMAT cmd
2026-01-29 03:44:11.351 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.28.20:5700/3) TRXD header version 1 -> 1
2026-01-29 03:44:11.353 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.28.20:5700) Recv RXTUNE cmd
2026-01-29 03:44:11.353 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETTSC
2026-01-29 03:44:11.353 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETTSC
2026-01-29 03:44:11.353 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETTSC
2026-01-29 03:44:11.353 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.28.20:5700) Recv TXTUNE cmd
2026-01-29 03:44:11.353 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETRXGAIN
2026-01-29 03:44:11.353 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETRXGAIN
2026-01-29 03:44:11.353 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETRXGAIN
2026-01-29 03:44:11.353 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETTSC
2026-01-29 03:44:11.353 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:44:11.353 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:44:11.353 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:44:11.353 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.28.20:5700) Recv NOMTXPOWER cmd
2026-01-29 03:44:11.353 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:44:11.353 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:44:11.353 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:44:11.353 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.28.20:5700) Recv POWERON CMD
2026-01-29 03:44:11.353 [INFO] ctrl_if_trx.py:109 (BTS@172.18.28.20:5700) Starting transceiver...
2026-01-29 03:44:11.353 [INFO] transceiver.py:243 Starting clock generator
2026-01-29 03:44:11.353 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-01-29 03:44:11.353 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:44:11.353 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:44:11.353 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:44:11.353 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETRXGAIN
2026-01-29 03:44:11.353 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:44:11.354 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:44:11.354 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:44:11.354 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:44:11.354 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:44:11.354 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:44:11.354 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:44:11.354 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:44:11.354 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:44:11.354 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:44:11.354 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:44:11.354 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:44:11.354 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:44:11.354 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:44:11.354 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:44:11.354 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:44:11.354 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:44:11.354 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:44:11.354 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:44:11.354 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:44:11.354 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:44:11.354 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:44:11.354 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:44:11.358 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-01-29 03:44:11.835 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-01-29 03:44:11.882 [DEBUG] fake_trx.py:278 (BTS@172.18.28.20:5700) Recv FAKE_TOA cmd
2026-01-29 03:44:11.883 [DEBUG] fake_trx.py:297 (BTS@172.18.28.20:5700) Recv FAKE_RSSI cmd
2026-01-29 03:44:11.884 [DEBUG] fake_trx.py:322 (BTS@172.18.28.20:5700) Recv FAKE_CI cmd
2026-01-29 03:44:11.885 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:44:11.912 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:44:11.913 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:44:11.924 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:44:11.933 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:44:12.218 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:44:12.228 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:44:12.236 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:44:12.247 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:44:12.251 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:44:12.255 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:44:12.306 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-01-29 03:44:12.357 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:44:12.357 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 03:44:12.357 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:44:12.360 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:44:12.550 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:44:12.554 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:44:12.558 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:44:12.566 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:44:12.571 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:44:12.575 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:44:12.783 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-01-29 03:44:12.869 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:44:12.873 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:44:12.877 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:44:12.888 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:44:12.893 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:44:12.897 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:44:13.191 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:44:13.196 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:44:13.199 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:44:13.210 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 03:44:13.211 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:44:13.211 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:44:13.211 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:44:13.214 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 03:44:13.214 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 03:44:13.214 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 03:44:13.215 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 03:44:13.215 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.28.20:5700) Recv POWEROFF cmd
2026-01-29 03:44:13.215 [INFO] ctrl_if_trx.py:117 (BTS@172.18.28.20:5700) Stopping transceiver...
2026-01-29 03:44:13.215 [INFO] transceiver.py:246 Stopping clock generator
2026-01-29 03:44:13.215 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=400 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:44:13.215 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=400 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:44:13.216 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=400 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:44:13.216 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=400 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:44:13.216 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=400 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:44:13.216 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=400 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:44:13.216 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=400 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:44:13.216 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=401 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:44:13.216 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=401 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:44:13.216 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=401 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:44:13.216 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=401 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:44:13.216 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=401 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:44:13.216 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=401 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:44:13.217 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=401 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:44:13.217 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=401 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:44:18.213 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.28.20:5700) Recv POWEROFF cmd
2026-01-29 03:44:18.213 [INFO] ctrl_if_trx.py:117 (BTS@172.18.28.20:5700) Stopping transceiver...
2026-01-29 03:44:18.215 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 03:44:18.216 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 03:44:18.218 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 03:44:18.220 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 03:44:18.228 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 03:44:18.228 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.28.20:5700) Recv SETFORMAT cmd
2026-01-29 03:44:18.228 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.28.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:44:18.228 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.28.20:5700) Recv SETFORMAT cmd
2026-01-29 03:44:18.228 [INFO] ctrl_if_trx.py:201 (BTS@172.18.28.20:5700) TRXD header version 1 -> 1
2026-01-29 03:44:18.229 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.28.20:5700/1) Recv RXTUNE cmd
2026-01-29 03:44:18.230 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.28.20:5700/1) Recv TXTUNE cmd
2026-01-29 03:44:18.230 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.28.20:5700/1) Recv SETFORMAT cmd
2026-01-29 03:44:18.230 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.28.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:44:18.230 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 03:44:18.230 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.28.20:5700/1) Recv NOMTXPOWER cmd
2026-01-29 03:44:18.231 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.28.20:5700/1) Recv SETFORMAT cmd
2026-01-29 03:44:18.231 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.28.20:5700/1) TRXD header version 1 -> 1
2026-01-29 03:44:18.232 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.28.20:5700/2) Recv RXTUNE cmd
2026-01-29 03:44:18.232 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.28.20:5700/2) Recv TXTUNE cmd
2026-01-29 03:44:18.232 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.28.20:5700/2) Recv SETFORMAT cmd
2026-01-29 03:44:18.232 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.28.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:44:18.232 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 03:44:18.232 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.28.20:5700/2) Recv NOMTXPOWER cmd
2026-01-29 03:44:18.233 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.28.20:5700/2) Recv SETFORMAT cmd
2026-01-29 03:44:18.233 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.28.20:5700/2) TRXD header version 1 -> 1
2026-01-29 03:44:18.234 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.28.20:5700/3) Recv RXTUNE cmd
2026-01-29 03:44:18.234 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.28.20:5700/3) Recv TXTUNE cmd
2026-01-29 03:44:18.234 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.28.20:5700/3) Recv SETFORMAT cmd
2026-01-29 03:44:18.234 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.28.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:44:18.235 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 03:44:18.235 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.28.20:5700/3) Recv NOMTXPOWER cmd
2026-01-29 03:44:18.235 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.28.20:5700/3) Recv SETFORMAT cmd
2026-01-29 03:44:18.235 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.28.20:5700/3) TRXD header version 1 -> 1
2026-01-29 03:44:18.237 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.28.20:5700) Recv RXTUNE cmd
2026-01-29 03:44:18.237 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETTSC
2026-01-29 03:44:18.237 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETTSC
2026-01-29 03:44:18.237 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETTSC
2026-01-29 03:44:18.237 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.28.20:5700) Recv TXTUNE cmd
2026-01-29 03:44:18.237 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETRXGAIN
2026-01-29 03:44:18.237 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETRXGAIN
2026-01-29 03:44:18.237 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETRXGAIN
2026-01-29 03:44:18.237 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETTSC
2026-01-29 03:44:18.237 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:44:18.237 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:44:18.237 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.28.20:5700) Recv NOMTXPOWER cmd
2026-01-29 03:44:18.238 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:44:18.238 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:44:18.238 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:44:18.238 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.28.20:5700) Recv POWERON CMD
2026-01-29 03:44:18.238 [INFO] ctrl_if_trx.py:109 (BTS@172.18.28.20:5700) Starting transceiver...
2026-01-29 03:44:18.238 [INFO] transceiver.py:243 Starting clock generator
2026-01-29 03:44:18.238 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-01-29 03:44:18.238 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:44:18.238 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:44:18.238 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:44:18.238 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETRXGAIN
2026-01-29 03:44:18.238 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:44:18.238 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:44:18.238 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:44:18.238 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:44:18.238 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:44:18.238 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:44:18.238 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:44:18.238 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:44:18.238 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:44:18.238 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:44:18.238 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:44:18.238 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:44:18.238 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:44:18.239 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:44:18.239 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:44:18.239 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:44:18.239 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:44:18.239 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:44:18.239 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:44:18.239 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:44:18.239 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:44:18.239 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:44:18.239 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:44:18.239 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:44:18.243 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-01-29 03:44:18.719 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-01-29 03:44:18.765 [DEBUG] fake_trx.py:278 (BTS@172.18.28.20:5700) Recv FAKE_TOA cmd
2026-01-29 03:44:18.765 [DEBUG] fake_trx.py:297 (BTS@172.18.28.20:5700) Recv FAKE_RSSI cmd
2026-01-29 03:44:18.766 [DEBUG] fake_trx.py:322 (BTS@172.18.28.20:5700) Recv FAKE_CI cmd
2026-01-29 03:44:18.766 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:44:18.790 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:44:18.792 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:44:18.794 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:44:18.798 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:44:18.799 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:44:18.800 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:44:18.808 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:44:18.809 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:44:18.810 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:44:18.813 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:44:18.814 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:44:18.814 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:44:18.822 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:44:18.823 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:44:18.823 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:44:18.827 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:44:18.827 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:44:18.828 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:44:18.836 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:44:18.837 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:44:18.838 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:44:18.840 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:44:18.841 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:44:18.841 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:44:18.843 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 03:44:18.844 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:44:18.844 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:44:18.844 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:44:18.845 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 03:44:18.845 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 03:44:18.845 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 03:44:18.845 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 03:44:18.845 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.28.20:5700) Recv POWEROFF cmd
2026-01-29 03:44:18.845 [INFO] ctrl_if_trx.py:117 (BTS@172.18.28.20:5700) Stopping transceiver...
2026-01-29 03:44:18.845 [INFO] transceiver.py:246 Stopping clock generator
2026-01-29 03:44:18.845 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=131 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:44:18.845 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=131 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:44:18.845 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=131 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:44:18.845 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=131 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:44:18.845 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=131 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:44:18.845 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=131 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:44:18.845 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=131 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:44:18.845 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=131 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:44:23.850 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.28.20:5700) Recv POWEROFF cmd
2026-01-29 03:44:23.850 [INFO] ctrl_if_trx.py:117 (BTS@172.18.28.20:5700) Stopping transceiver...
2026-01-29 03:44:23.850 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 03:44:23.851 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 03:44:23.851 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 03:44:23.851 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 03:44:23.858 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 03:44:23.859 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.28.20:5700) Recv SETFORMAT cmd
2026-01-29 03:44:23.859 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.28.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:44:23.859 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.28.20:5700) Recv SETFORMAT cmd
2026-01-29 03:44:23.860 [INFO] ctrl_if_trx.py:201 (BTS@172.18.28.20:5700) TRXD header version 1 -> 1
2026-01-29 03:44:23.862 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.28.20:5700/1) Recv RXTUNE cmd
2026-01-29 03:44:23.862 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.28.20:5700/1) Recv TXTUNE cmd
2026-01-29 03:44:23.863 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.28.20:5700/1) Recv SETFORMAT cmd
2026-01-29 03:44:23.863 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.28.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:44:23.863 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 03:44:23.864 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.28.20:5700/1) Recv NOMTXPOWER cmd
2026-01-29 03:44:23.864 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.28.20:5700/1) Recv SETFORMAT cmd
2026-01-29 03:44:23.864 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.28.20:5700/1) TRXD header version 1 -> 1
2026-01-29 03:44:23.869 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.28.20:5700/2) Recv RXTUNE cmd
2026-01-29 03:44:23.869 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.28.20:5700/2) Recv TXTUNE cmd
2026-01-29 03:44:23.869 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.28.20:5700/2) Recv SETFORMAT cmd
2026-01-29 03:44:23.869 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.28.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:44:23.870 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 03:44:23.870 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.28.20:5700/2) Recv NOMTXPOWER cmd
2026-01-29 03:44:23.870 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.28.20:5700/2) Recv SETFORMAT cmd
2026-01-29 03:44:23.870 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.28.20:5700/2) TRXD header version 1 -> 1
2026-01-29 03:44:23.874 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.28.20:5700/3) Recv RXTUNE cmd
2026-01-29 03:44:23.874 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.28.20:5700/3) Recv TXTUNE cmd
2026-01-29 03:44:23.874 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.28.20:5700/3) Recv SETFORMAT cmd
2026-01-29 03:44:23.874 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.28.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:44:23.874 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 03:44:23.874 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.28.20:5700/3) Recv NOMTXPOWER cmd
2026-01-29 03:44:23.874 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.28.20:5700/3) Recv SETFORMAT cmd
2026-01-29 03:44:23.874 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.28.20:5700/3) TRXD header version 1 -> 1
2026-01-29 03:44:23.879 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.28.20:5700) Recv RXTUNE cmd
2026-01-29 03:44:23.879 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETTSC
2026-01-29 03:44:23.879 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETTSC
2026-01-29 03:44:23.879 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETTSC
2026-01-29 03:44:23.879 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.28.20:5700) Recv TXTUNE cmd
2026-01-29 03:44:23.879 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETRXGAIN
2026-01-29 03:44:23.879 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETRXGAIN
2026-01-29 03:44:23.879 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETRXGAIN
2026-01-29 03:44:23.879 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETTSC
2026-01-29 03:44:23.879 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:44:23.879 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:44:23.879 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.28.20:5700) Recv NOMTXPOWER cmd
2026-01-29 03:44:23.880 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:44:23.880 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:44:23.880 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:44:23.880 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.28.20:5700) Recv POWERON CMD
2026-01-29 03:44:23.880 [INFO] ctrl_if_trx.py:109 (BTS@172.18.28.20:5700) Starting transceiver...
2026-01-29 03:44:23.880 [INFO] transceiver.py:243 Starting clock generator
2026-01-29 03:44:23.880 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-01-29 03:44:23.880 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:44:23.880 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:44:23.880 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:44:23.880 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETRXGAIN
2026-01-29 03:44:23.880 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:44:23.880 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:44:23.880 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:44:23.880 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:44:23.880 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:44:23.881 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:44:23.881 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:44:23.881 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:44:23.881 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:44:23.881 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:44:23.881 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:44:23.881 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:44:23.881 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:44:23.881 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:44:23.881 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:44:23.881 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:44:23.881 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:44:23.881 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:44:23.881 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:44:23.881 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:44:23.882 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:44:23.882 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:44:23.882 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:44:23.882 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:44:23.885 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-01-29 03:44:24.362 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-01-29 03:44:24.414 [DEBUG] fake_trx.py:278 (BTS@172.18.28.20:5700) Recv FAKE_TOA cmd
2026-01-29 03:44:24.416 [DEBUG] fake_trx.py:297 (BTS@172.18.28.20:5700) Recv FAKE_RSSI cmd
2026-01-29 03:44:24.417 [DEBUG] fake_trx.py:322 (BTS@172.18.28.20:5700) Recv FAKE_CI cmd
2026-01-29 03:44:24.418 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:44:24.443 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:44:24.447 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:44:24.450 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:44:24.456 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:44:24.458 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:44:24.459 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:44:24.463 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:44:24.464 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:44:24.465 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:44:24.468 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:44:24.469 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:44:24.470 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:44:24.478 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:44:24.479 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:44:24.479 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:44:24.482 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:44:24.483 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:44:24.483 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:44:24.486 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:44:24.487 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:44:24.487 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:44:24.491 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:44:24.492 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:44:24.492 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:44:24.499 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:44:24.501 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:44:24.501 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:44:24.505 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:44:24.506 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:44:24.506 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:44:24.509 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:44:24.510 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:44:24.510 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:44:24.513 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:44:24.514 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:44:24.515 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:44:24.523 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:44:24.523 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:44:24.524 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:44:24.526 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:44:24.527 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:44:24.528 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:44:24.530 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:44:24.531 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:44:24.532 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:44:24.535 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:44:24.536 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:44:24.536 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:44:24.539 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 03:44:24.539 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:44:24.539 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:44:24.539 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:44:24.540 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 03:44:24.540 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 03:44:24.540 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 03:44:24.540 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 03:44:24.540 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.28.20:5700) Recv POWEROFF cmd
2026-01-29 03:44:24.540 [INFO] ctrl_if_trx.py:117 (BTS@172.18.28.20:5700) Stopping transceiver...
2026-01-29 03:44:24.540 [INFO] transceiver.py:246 Stopping clock generator
2026-01-29 03:44:29.542 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.28.20:5700) Recv POWEROFF cmd
2026-01-29 03:44:29.543 [INFO] ctrl_if_trx.py:117 (BTS@172.18.28.20:5700) Stopping transceiver...
2026-01-29 03:44:29.544 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 03:44:29.545 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 03:44:29.547 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 03:44:29.549 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 03:44:29.558 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 03:44:29.559 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.28.20:5700) Recv SETFORMAT cmd
2026-01-29 03:44:29.559 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.28.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:44:29.559 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.28.20:5700) Recv SETFORMAT cmd
2026-01-29 03:44:29.559 [INFO] ctrl_if_trx.py:201 (BTS@172.18.28.20:5700) TRXD header version 1 -> 1
2026-01-29 03:44:29.561 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.28.20:5700/1) Recv RXTUNE cmd
2026-01-29 03:44:29.561 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.28.20:5700/1) Recv TXTUNE cmd
2026-01-29 03:44:29.561 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.28.20:5700/1) Recv SETFORMAT cmd
2026-01-29 03:44:29.561 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.28.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:44:29.561 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 03:44:29.561 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.28.20:5700/1) Recv NOMTXPOWER cmd
2026-01-29 03:44:29.561 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.28.20:5700/1) Recv SETFORMAT cmd
2026-01-29 03:44:29.561 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.28.20:5700/1) TRXD header version 1 -> 1
2026-01-29 03:44:29.562 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.28.20:5700/2) Recv RXTUNE cmd
2026-01-29 03:44:29.562 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.28.20:5700/2) Recv TXTUNE cmd
2026-01-29 03:44:29.562 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.28.20:5700/2) Recv SETFORMAT cmd
2026-01-29 03:44:29.562 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.28.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:44:29.562 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.28.20:5700/2) Recv NOMTXPOWER cmd
2026-01-29 03:44:29.562 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 03:44:29.562 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.28.20:5700/2) Recv SETFORMAT cmd
2026-01-29 03:44:29.562 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.28.20:5700/2) TRXD header version 1 -> 1
2026-01-29 03:44:29.564 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.28.20:5700/3) Recv RXTUNE cmd
2026-01-29 03:44:29.564 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.28.20:5700/3) Recv TXTUNE cmd
2026-01-29 03:44:29.564 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.28.20:5700/3) Recv SETFORMAT cmd
2026-01-29 03:44:29.564 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.28.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:44:29.564 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.28.20:5700/3) Recv NOMTXPOWER cmd
2026-01-29 03:44:29.564 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 03:44:29.564 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.28.20:5700/3) Recv SETFORMAT cmd
2026-01-29 03:44:29.564 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.28.20:5700/3) TRXD header version 1 -> 1
2026-01-29 03:44:29.565 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.28.20:5700) Recv RXTUNE cmd
2026-01-29 03:44:29.565 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETTSC
2026-01-29 03:44:29.565 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETTSC
2026-01-29 03:44:29.565 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETTSC
2026-01-29 03:44:29.566 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.28.20:5700) Recv TXTUNE cmd
2026-01-29 03:44:29.566 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETRXGAIN
2026-01-29 03:44:29.566 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETRXGAIN
2026-01-29 03:44:29.566 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETRXGAIN
2026-01-29 03:44:29.566 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETTSC
2026-01-29 03:44:29.566 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:44:29.566 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:44:29.566 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.28.20:5700) Recv NOMTXPOWER cmd
2026-01-29 03:44:29.566 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:44:29.566 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:44:29.566 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.28.20:5700) Recv POWERON CMD
2026-01-29 03:44:29.566 [INFO] ctrl_if_trx.py:109 (BTS@172.18.28.20:5700) Starting transceiver...
2026-01-29 03:44:29.566 [INFO] transceiver.py:243 Starting clock generator
2026-01-29 03:44:29.566 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-01-29 03:44:29.566 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:44:29.566 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:44:29.566 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:44:29.566 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETRXGAIN
2026-01-29 03:44:29.566 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:44:29.566 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:44:29.566 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:44:29.566 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:44:29.566 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:44:29.566 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:44:29.566 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:44:29.566 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:44:29.566 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:44:29.566 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:44:29.566 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:44:29.566 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:44:29.566 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:44:29.566 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:44:29.566 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:44:29.566 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:44:29.566 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:44:29.566 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:44:29.566 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:44:29.566 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:44:29.566 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:44:29.566 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:44:29.566 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:44:29.566 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:44:29.566 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:44:29.571 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-01-29 03:44:30.039 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-01-29 03:44:30.091 [DEBUG] fake_trx.py:278 (BTS@172.18.28.20:5700) Recv FAKE_TOA cmd
2026-01-29 03:44:30.093 [DEBUG] fake_trx.py:297 (BTS@172.18.28.20:5700) Recv FAKE_RSSI cmd
2026-01-29 03:44:30.095 [DEBUG] fake_trx.py:322 (BTS@172.18.28.20:5700) Recv FAKE_CI cmd
2026-01-29 03:44:30.095 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:44:30.115 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:44:30.117 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:44:30.119 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:44:30.121 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:44:30.123 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:44:30.123 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:44:30.126 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:44:30.128 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:44:30.129 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:44:30.136 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:44:30.137 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:44:30.138 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:44:30.141 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:44:30.142 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:44:30.143 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:44:30.145 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:44:30.146 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:44:30.146 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:44:30.154 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:44:30.155 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:44:30.156 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:44:30.158 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:44:30.159 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:44:30.160 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:44:30.163 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:44:30.164 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:44:30.164 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:44:30.172 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:44:30.173 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:44:30.174 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:44:30.176 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:44:30.177 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:44:30.177 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:44:30.181 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:44:30.182 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:44:30.182 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:44:30.185 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 03:44:30.185 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:44:30.185 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:44:30.185 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:44:30.185 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 03:44:30.185 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 03:44:30.185 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 03:44:30.185 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 03:44:30.185 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.28.20:5700) Recv POWEROFF cmd
2026-01-29 03:44:30.186 [INFO] ctrl_if_trx.py:117 (BTS@172.18.28.20:5700) Stopping transceiver...
2026-01-29 03:44:30.186 [INFO] transceiver.py:246 Stopping clock generator
2026-01-29 03:44:35.188 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.28.20:5700) Recv POWEROFF cmd
2026-01-29 03:44:35.188 [INFO] ctrl_if_trx.py:117 (BTS@172.18.28.20:5700) Stopping transceiver...
2026-01-29 03:44:35.190 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 03:44:35.191 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 03:44:35.191 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 03:44:35.191 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 03:44:35.198 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 03:44:35.199 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.28.20:5700) Recv SETFORMAT cmd
2026-01-29 03:44:35.199 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.28.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:44:35.199 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.28.20:5700) Recv SETFORMAT cmd
2026-01-29 03:44:35.199 [INFO] ctrl_if_trx.py:201 (BTS@172.18.28.20:5700) TRXD header version 1 -> 1
2026-01-29 03:44:35.202 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.28.20:5700/1) Recv RXTUNE cmd
2026-01-29 03:44:35.202 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.28.20:5700/1) Recv TXTUNE cmd
2026-01-29 03:44:35.202 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.28.20:5700/1) Recv SETFORMAT cmd
2026-01-29 03:44:35.203 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.28.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:44:35.203 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 03:44:35.203 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.28.20:5700/1) Recv NOMTXPOWER cmd
2026-01-29 03:44:35.204 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.28.20:5700/1) Recv SETFORMAT cmd
2026-01-29 03:44:35.204 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.28.20:5700/1) TRXD header version 1 -> 1
2026-01-29 03:44:35.205 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.28.20:5700/2) Recv RXTUNE cmd
2026-01-29 03:44:35.205 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.28.20:5700/2) Recv TXTUNE cmd
2026-01-29 03:44:35.205 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.28.20:5700/2) Recv SETFORMAT cmd
2026-01-29 03:44:35.205 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.28.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:44:35.205 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 03:44:35.205 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.28.20:5700/2) Recv NOMTXPOWER cmd
2026-01-29 03:44:35.205 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.28.20:5700/2) Recv SETFORMAT cmd
2026-01-29 03:44:35.205 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.28.20:5700/2) TRXD header version 1 -> 1
2026-01-29 03:44:35.207 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.28.20:5700/3) Recv RXTUNE cmd
2026-01-29 03:44:35.207 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.28.20:5700/3) Recv TXTUNE cmd
2026-01-29 03:44:35.207 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.28.20:5700/3) Recv SETFORMAT cmd
2026-01-29 03:44:35.207 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.28.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:44:35.208 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 03:44:35.208 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.28.20:5700/3) Recv NOMTXPOWER cmd
2026-01-29 03:44:35.208 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.28.20:5700/3) Recv SETFORMAT cmd
2026-01-29 03:44:35.208 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.28.20:5700/3) TRXD header version 1 -> 1
2026-01-29 03:44:35.210 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.28.20:5700) Recv RXTUNE cmd
2026-01-29 03:44:35.210 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETTSC
2026-01-29 03:44:35.211 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETTSC
2026-01-29 03:44:35.211 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.28.20:5700) Recv TXTUNE cmd
2026-01-29 03:44:35.211 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETTSC
2026-01-29 03:44:35.211 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETRXGAIN
2026-01-29 03:44:35.211 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETRXGAIN
2026-01-29 03:44:35.211 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETTSC
2026-01-29 03:44:35.211 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETRXGAIN
2026-01-29 03:44:35.211 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:44:35.211 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.28.20:5700) Recv NOMTXPOWER cmd
2026-01-29 03:44:35.211 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:44:35.211 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:44:35.211 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:44:35.211 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.28.20:5700) Recv POWERON CMD
2026-01-29 03:44:35.211 [INFO] ctrl_if_trx.py:109 (BTS@172.18.28.20:5700) Starting transceiver...
2026-01-29 03:44:35.211 [INFO] transceiver.py:243 Starting clock generator
2026-01-29 03:44:35.211 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-01-29 03:44:35.211 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:44:35.211 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:44:35.211 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:44:35.212 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETRXGAIN
2026-01-29 03:44:35.212 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:44:35.212 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:44:35.212 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:44:35.212 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:44:35.212 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:44:35.212 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:44:35.212 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:44:35.212 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:44:35.212 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:44:35.212 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:44:35.212 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:44:35.212 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:44:35.212 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:44:35.212 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:44:35.212 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:44:35.212 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:44:35.212 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:44:35.212 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:44:35.212 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:44:35.212 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:44:35.212 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:44:35.212 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:44:35.212 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:44:35.212 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:44:35.212 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:44:35.216 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-01-29 03:44:35.700 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-01-29 03:44:35.739 [DEBUG] fake_trx.py:278 (BTS@172.18.28.20:5700) Recv FAKE_TOA cmd
2026-01-29 03:44:35.740 [DEBUG] fake_trx.py:297 (BTS@172.18.28.20:5700) Recv FAKE_RSSI cmd
2026-01-29 03:44:35.740 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:44:35.741 [DEBUG] fake_trx.py:322 (BTS@172.18.28.20:5700) Recv FAKE_CI cmd
2026-01-29 03:44:35.757 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:44:35.760 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:44:35.761 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:44:35.764 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:44:35.766 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:44:35.767 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:44:35.775 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:44:35.776 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:44:35.776 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:44:35.779 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:44:35.780 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:44:35.781 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:44:35.788 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:44:35.789 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:44:35.790 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:44:35.793 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:44:35.794 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:44:35.794 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:44:35.802 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:44:35.803 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:44:35.803 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:44:35.805 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:44:35.806 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:44:35.807 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:44:35.809 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 03:44:35.809 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:44:35.809 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:44:35.809 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:44:35.810 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 03:44:35.810 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 03:44:35.810 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.28.20:5700) Recv POWEROFF cmd
2026-01-29 03:44:35.810 [INFO] ctrl_if_trx.py:117 (BTS@172.18.28.20:5700) Stopping transceiver...
2026-01-29 03:44:35.810 [INFO] transceiver.py:246 Stopping clock generator
2026-01-29 03:44:35.810 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 03:44:35.810 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 03:44:40.811 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.28.20:5700) Recv POWEROFF cmd
2026-01-29 03:44:40.811 [INFO] ctrl_if_trx.py:117 (BTS@172.18.28.20:5700) Stopping transceiver...
2026-01-29 03:44:40.812 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 03:44:40.814 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 03:44:40.815 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 03:44:40.815 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 03:44:40.827 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 03:44:40.828 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.28.20:5700) Recv SETFORMAT cmd
2026-01-29 03:44:40.828 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.28.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:44:40.828 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.28.20:5700) Recv SETFORMAT cmd
2026-01-29 03:44:40.828 [INFO] ctrl_if_trx.py:201 (BTS@172.18.28.20:5700) TRXD header version 1 -> 1
2026-01-29 03:44:40.832 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.28.20:5700/1) Recv RXTUNE cmd
2026-01-29 03:44:40.832 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.28.20:5700/1) Recv TXTUNE cmd
2026-01-29 03:44:40.832 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.28.20:5700/1) Recv SETFORMAT cmd
2026-01-29 03:44:40.832 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.28.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:44:40.832 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 03:44:40.833 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.28.20:5700/1) Recv NOMTXPOWER cmd
2026-01-29 03:44:40.833 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.28.20:5700/1) Recv SETFORMAT cmd
2026-01-29 03:44:40.833 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.28.20:5700/1) TRXD header version 1 -> 1
2026-01-29 03:44:40.835 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.28.20:5700/2) Recv RXTUNE cmd
2026-01-29 03:44:40.835 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.28.20:5700/2) Recv TXTUNE cmd
2026-01-29 03:44:40.835 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.28.20:5700/2) Recv SETFORMAT cmd
2026-01-29 03:44:40.835 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.28.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:44:40.835 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 03:44:40.835 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.28.20:5700/2) Recv NOMTXPOWER cmd
2026-01-29 03:44:40.836 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.28.20:5700/2) Recv SETFORMAT cmd
2026-01-29 03:44:40.836 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.28.20:5700/2) TRXD header version 1 -> 1
2026-01-29 03:44:40.838 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.28.20:5700/3) Recv RXTUNE cmd
2026-01-29 03:44:40.838 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.28.20:5700/3) Recv TXTUNE cmd
2026-01-29 03:44:40.838 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.28.20:5700/3) Recv SETFORMAT cmd
2026-01-29 03:44:40.838 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.28.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:44:40.838 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 03:44:40.838 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.28.20:5700/3) Recv NOMTXPOWER cmd
2026-01-29 03:44:40.838 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.28.20:5700/3) Recv SETFORMAT cmd
2026-01-29 03:44:40.838 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.28.20:5700/3) TRXD header version 1 -> 1
2026-01-29 03:44:40.841 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.28.20:5700) Recv RXTUNE cmd
2026-01-29 03:44:40.841 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETTSC
2026-01-29 03:44:40.841 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETTSC
2026-01-29 03:44:40.841 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETTSC
2026-01-29 03:44:40.841 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.28.20:5700) Recv TXTUNE cmd
2026-01-29 03:44:40.841 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETRXGAIN
2026-01-29 03:44:40.841 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETRXGAIN
2026-01-29 03:44:40.841 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETRXGAIN
2026-01-29 03:44:40.841 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETTSC
2026-01-29 03:44:40.841 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:44:40.842 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:44:40.842 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:44:40.842 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.28.20:5700) Recv NOMTXPOWER cmd
2026-01-29 03:44:40.842 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:44:40.842 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:44:40.842 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:44:40.842 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.28.20:5700) Recv POWERON CMD
2026-01-29 03:44:40.842 [INFO] ctrl_if_trx.py:109 (BTS@172.18.28.20:5700) Starting transceiver...
2026-01-29 03:44:40.842 [INFO] transceiver.py:243 Starting clock generator
2026-01-29 03:44:40.842 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-01-29 03:44:40.842 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:44:40.842 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:44:40.842 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:44:40.842 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETRXGAIN
2026-01-29 03:44:40.842 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:44:40.842 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:44:40.842 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:44:40.842 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:44:40.842 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:44:40.842 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:44:40.843 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:44:40.843 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:44:40.843 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:44:40.843 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:44:40.843 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:44:40.843 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:44:40.843 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:44:40.843 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:44:40.843 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:44:40.843 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:44:40.843 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:44:40.843 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:44:40.843 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:44:40.843 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:44:40.843 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:44:40.843 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:44:40.843 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:44:40.847 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-01-29 03:44:41.315 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-01-29 03:44:41.378 [DEBUG] fake_trx.py:278 (BTS@172.18.28.20:5700) Recv FAKE_TOA cmd
2026-01-29 03:44:41.380 [DEBUG] fake_trx.py:297 (BTS@172.18.28.20:5700) Recv FAKE_RSSI cmd
2026-01-29 03:44:41.382 [DEBUG] fake_trx.py:322 (BTS@172.18.28.20:5700) Recv FAKE_CI cmd
2026-01-29 03:44:41.383 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:44:41.396 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:44:41.396 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:44:41.397 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:44:41.398 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:44:41.400 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:44:41.401 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:44:41.401 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:44:41.409 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:44:41.409 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:44:41.410 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:44:41.414 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:44:41.415 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:44:41.415 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:44:41.423 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:44:41.423 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:44:41.424 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:44:41.427 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:44:41.428 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:44:41.428 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:44:41.436 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:44:41.437 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:44:41.437 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:44:41.440 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:44:41.440 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:44:41.441 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:44:41.443 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 03:44:41.443 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:44:41.444 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:44:41.444 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:44:41.444 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 03:44:41.444 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 03:44:41.444 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 03:44:41.444 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 03:44:41.444 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.28.20:5700) Recv POWEROFF cmd
2026-01-29 03:44:41.444 [INFO] ctrl_if_trx.py:117 (BTS@172.18.28.20:5700) Stopping transceiver...
2026-01-29 03:44:41.444 [INFO] transceiver.py:246 Stopping clock generator
2026-01-29 03:44:41.444 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=132 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:44:46.446 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.28.20:5700) Recv POWEROFF cmd
2026-01-29 03:44:46.446 [INFO] ctrl_if_trx.py:117 (BTS@172.18.28.20:5700) Stopping transceiver...
2026-01-29 03:44:46.450 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 03:44:46.450 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 03:44:46.450 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 03:44:46.450 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 03:44:46.456 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 03:44:46.456 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.28.20:5700) Recv SETFORMAT cmd
2026-01-29 03:44:46.457 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.28.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:44:46.457 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.28.20:5700) Recv SETFORMAT cmd
2026-01-29 03:44:46.457 [INFO] ctrl_if_trx.py:201 (BTS@172.18.28.20:5700) TRXD header version 1 -> 1
2026-01-29 03:44:46.457 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.28.20:5700/1) Recv RXTUNE cmd
2026-01-29 03:44:46.457 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.28.20:5700/1) Recv TXTUNE cmd
2026-01-29 03:44:46.457 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.28.20:5700/1) Recv SETFORMAT cmd
2026-01-29 03:44:46.457 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.28.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:44:46.457 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 03:44:46.457 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.28.20:5700/1) Recv NOMTXPOWER cmd
2026-01-29 03:44:46.457 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.28.20:5700/1) Recv SETFORMAT cmd
2026-01-29 03:44:46.457 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.28.20:5700/1) TRXD header version 1 -> 1
2026-01-29 03:44:46.458 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.28.20:5700/2) Recv RXTUNE cmd
2026-01-29 03:44:46.458 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.28.20:5700/2) Recv TXTUNE cmd
2026-01-29 03:44:46.458 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.28.20:5700/2) Recv SETFORMAT cmd
2026-01-29 03:44:46.458 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.28.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:44:46.458 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 03:44:46.458 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.28.20:5700/2) Recv NOMTXPOWER cmd
2026-01-29 03:44:46.458 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.28.20:5700/2) Recv SETFORMAT cmd
2026-01-29 03:44:46.458 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.28.20:5700/2) TRXD header version 1 -> 1
2026-01-29 03:44:46.459 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.28.20:5700/3) Recv RXTUNE cmd
2026-01-29 03:44:46.459 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.28.20:5700/3) Recv TXTUNE cmd
2026-01-29 03:44:46.459 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.28.20:5700/3) Recv SETFORMAT cmd
2026-01-29 03:44:46.459 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.28.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:44:46.459 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 03:44:46.459 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.28.20:5700/3) Recv NOMTXPOWER cmd
2026-01-29 03:44:46.459 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.28.20:5700/3) Recv SETFORMAT cmd
2026-01-29 03:44:46.459 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.28.20:5700/3) TRXD header version 1 -> 1
2026-01-29 03:44:46.460 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.28.20:5700) Recv RXTUNE cmd
2026-01-29 03:44:46.461 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETTSC
2026-01-29 03:44:46.461 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETTSC
2026-01-29 03:44:46.461 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETTSC
2026-01-29 03:44:46.461 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.28.20:5700) Recv TXTUNE cmd
2026-01-29 03:44:46.461 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETRXGAIN
2026-01-29 03:44:46.461 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETRXGAIN
2026-01-29 03:44:46.461 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETRXGAIN
2026-01-29 03:44:46.461 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETTSC
2026-01-29 03:44:46.461 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:44:46.461 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:44:46.461 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:44:46.461 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.28.20:5700) Recv NOMTXPOWER cmd
2026-01-29 03:44:46.461 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:44:46.461 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:44:46.461 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.28.20:5700) Recv POWERON CMD
2026-01-29 03:44:46.461 [INFO] ctrl_if_trx.py:109 (BTS@172.18.28.20:5700) Starting transceiver...
2026-01-29 03:44:46.461 [INFO] transceiver.py:243 Starting clock generator
2026-01-29 03:44:46.461 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-01-29 03:44:46.461 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:44:46.461 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:44:46.461 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETRXGAIN
2026-01-29 03:44:46.461 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:44:46.461 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:44:46.461 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:44:46.461 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:44:46.461 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:44:46.461 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:44:46.461 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:44:46.461 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:44:46.461 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:44:46.461 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:44:46.461 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:44:46.461 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:44:46.461 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:44:46.462 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:44:46.462 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:44:46.462 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:44:46.462 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:44:46.462 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:44:46.462 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:44:46.462 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:44:46.462 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:44:46.462 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:44:46.462 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:44:46.462 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:44:46.462 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:44:46.466 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-01-29 03:44:46.937 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-01-29 03:44:46.994 [DEBUG] fake_trx.py:278 (BTS@172.18.28.20:5700) Recv FAKE_TOA cmd
2026-01-29 03:44:46.996 [DEBUG] fake_trx.py:297 (BTS@172.18.28.20:5700) Recv FAKE_RSSI cmd
2026-01-29 03:44:46.998 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:44:46.998 [DEBUG] fake_trx.py:322 (BTS@172.18.28.20:5700) Recv FAKE_CI cmd
2026-01-29 03:44:47.014 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:44:47.015 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:44:47.017 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:44:47.018 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:44:47.020 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:44:47.021 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:44:47.022 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:44:47.025 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:44:47.025 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:44:47.026 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:44:47.030 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:44:47.031 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:44:47.031 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:44:47.039 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:44:47.040 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:44:47.040 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:44:47.042 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:44:47.043 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:44:47.044 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:44:47.047 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:44:47.048 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:44:47.049 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:44:47.052 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:44:47.053 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:44:47.053 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:44:47.061 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:44:47.062 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:44:47.062 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:44:47.065 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:44:47.066 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:44:47.067 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:44:47.070 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:44:47.071 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:44:47.072 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:44:47.075 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:44:47.076 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:44:47.076 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:44:47.084 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:44:47.085 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:44:47.086 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:44:47.088 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:44:47.088 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:44:47.089 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:44:47.092 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:44:47.093 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:44:47.094 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:44:47.097 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:44:47.098 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:44:47.098 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:44:47.101 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 03:44:47.101 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:44:47.101 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:44:47.101 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:44:47.102 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 03:44:47.102 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 03:44:47.102 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 03:44:47.102 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 03:44:47.102 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.28.20:5700) Recv POWEROFF cmd
2026-01-29 03:44:47.102 [INFO] ctrl_if_trx.py:117 (BTS@172.18.28.20:5700) Stopping transceiver...
2026-01-29 03:44:47.102 [INFO] transceiver.py:246 Stopping clock generator
2026-01-29 03:44:52.104 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.28.20:5700) Recv POWEROFF cmd
2026-01-29 03:44:52.105 [INFO] ctrl_if_trx.py:117 (BTS@172.18.28.20:5700) Stopping transceiver...
2026-01-29 03:44:52.106 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 03:44:52.110 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 03:44:52.110 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 03:44:52.110 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 03:44:52.121 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 03:44:52.121 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.28.20:5700) Recv SETFORMAT cmd
2026-01-29 03:44:52.121 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.28.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:44:52.121 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.28.20:5700) Recv SETFORMAT cmd
2026-01-29 03:44:52.121 [INFO] ctrl_if_trx.py:201 (BTS@172.18.28.20:5700) TRXD header version 1 -> 1
2026-01-29 03:44:52.123 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.28.20:5700/1) Recv RXTUNE cmd
2026-01-29 03:44:52.123 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.28.20:5700/1) Recv TXTUNE cmd
2026-01-29 03:44:52.123 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.28.20:5700/1) Recv SETFORMAT cmd
2026-01-29 03:44:52.123 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.28.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:44:52.124 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 03:44:52.124 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.28.20:5700/1) Recv NOMTXPOWER cmd
2026-01-29 03:44:52.124 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.28.20:5700/1) Recv SETFORMAT cmd
2026-01-29 03:44:52.124 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.28.20:5700/1) TRXD header version 1 -> 1
2026-01-29 03:44:52.125 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.28.20:5700/2) Recv RXTUNE cmd
2026-01-29 03:44:52.125 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.28.20:5700/2) Recv TXTUNE cmd
2026-01-29 03:44:52.125 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.28.20:5700/2) Recv SETFORMAT cmd
2026-01-29 03:44:52.125 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.28.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:44:52.125 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 03:44:52.125 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.28.20:5700/2) Recv NOMTXPOWER cmd
2026-01-29 03:44:52.125 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.28.20:5700/2) Recv SETFORMAT cmd
2026-01-29 03:44:52.125 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.28.20:5700/2) TRXD header version 1 -> 1
2026-01-29 03:44:52.126 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.28.20:5700/3) Recv RXTUNE cmd
2026-01-29 03:44:52.126 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.28.20:5700/3) Recv TXTUNE cmd
2026-01-29 03:44:52.126 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.28.20:5700/3) Recv SETFORMAT cmd
2026-01-29 03:44:52.126 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.28.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:44:52.126 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 03:44:52.126 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.28.20:5700/3) Recv NOMTXPOWER cmd
2026-01-29 03:44:52.126 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.28.20:5700/3) Recv SETFORMAT cmd
2026-01-29 03:44:52.126 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.28.20:5700/3) TRXD header version 1 -> 1
2026-01-29 03:44:52.128 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.28.20:5700) Recv RXTUNE cmd
2026-01-29 03:44:52.128 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETTSC
2026-01-29 03:44:52.128 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETTSC
2026-01-29 03:44:52.128 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETTSC
2026-01-29 03:44:52.128 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.28.20:5700) Recv TXTUNE cmd
2026-01-29 03:44:52.128 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETRXGAIN
2026-01-29 03:44:52.128 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETRXGAIN
2026-01-29 03:44:52.128 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETRXGAIN
2026-01-29 03:44:52.128 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETTSC
2026-01-29 03:44:52.128 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:44:52.128 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.28.20:5700) Recv NOMTXPOWER cmd
2026-01-29 03:44:52.128 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:44:52.128 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:44:52.128 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.28.20:5700) Recv POWERON CMD
2026-01-29 03:44:52.128 [INFO] ctrl_if_trx.py:109 (BTS@172.18.28.20:5700) Starting transceiver...
2026-01-29 03:44:52.128 [INFO] transceiver.py:243 Starting clock generator
2026-01-29 03:44:52.128 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-01-29 03:44:52.128 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:44:52.128 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:44:52.128 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:44:52.128 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETRXGAIN
2026-01-29 03:44:52.128 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:44:52.128 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:44:52.129 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:44:52.129 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:44:52.129 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:44:52.129 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:44:52.129 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:44:52.129 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:44:52.129 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:44:52.129 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:44:52.129 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:44:52.129 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:44:52.129 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:44:52.129 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:44:52.129 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:44:52.129 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:44:52.129 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:44:52.129 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:44:52.129 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:44:52.129 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:44:52.129 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:44:52.129 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:44:52.129 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:44:52.129 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:44:52.129 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:44:52.129 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:44:52.133 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-01-29 03:44:52.601 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-01-29 03:44:52.648 [DEBUG] fake_trx.py:278 (BTS@172.18.28.20:5700) Recv FAKE_TOA cmd
2026-01-29 03:44:52.649 [DEBUG] fake_trx.py:297 (BTS@172.18.28.20:5700) Recv FAKE_RSSI cmd
2026-01-29 03:44:52.650 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:44:52.650 [DEBUG] fake_trx.py:322 (BTS@172.18.28.20:5700) Recv FAKE_CI cmd
2026-01-29 03:44:52.668 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:44:52.668 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:44:52.671 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:44:52.672 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:44:52.676 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:44:52.677 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:44:52.678 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:44:52.681 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:44:52.682 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:44:52.683 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:44:52.691 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:44:52.692 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:44:52.693 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:44:52.695 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:44:52.697 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:44:52.697 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:44:52.699 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:44:52.700 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:44:52.700 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:44:52.708 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:44:52.709 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:44:52.710 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:44:52.712 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:44:52.713 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:44:52.714 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:44:52.716 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:44:52.717 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:44:52.718 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:44:52.726 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:44:52.727 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:44:52.728 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:44:52.730 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:44:52.732 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:44:52.732 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:44:52.734 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:44:52.735 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:44:52.736 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:44:52.738 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 03:44:52.738 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:44:52.738 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:44:52.738 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:44:52.739 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 03:44:52.739 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 03:44:52.739 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 03:44:52.739 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.28.20:5700) Recv POWEROFF cmd
2026-01-29 03:44:52.739 [INFO] ctrl_if_trx.py:117 (BTS@172.18.28.20:5700) Stopping transceiver...
2026-01-29 03:44:52.739 [INFO] transceiver.py:246 Stopping clock generator
2026-01-29 03:44:52.739 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 03:44:57.742 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.28.20:5700) Recv POWEROFF cmd
2026-01-29 03:44:57.742 [INFO] ctrl_if_trx.py:117 (BTS@172.18.28.20:5700) Stopping transceiver...
2026-01-29 03:44:57.745 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 03:44:57.745 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 03:44:57.745 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 03:44:57.745 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 03:44:57.753 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 03:44:57.753 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.28.20:5700) Recv SETFORMAT cmd
2026-01-29 03:44:57.753 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.28.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:44:57.754 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.28.20:5700) Recv SETFORMAT cmd
2026-01-29 03:44:57.754 [INFO] ctrl_if_trx.py:201 (BTS@172.18.28.20:5700) TRXD header version 1 -> 1
2026-01-29 03:44:57.757 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.28.20:5700/1) Recv RXTUNE cmd
2026-01-29 03:44:57.757 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.28.20:5700/1) Recv TXTUNE cmd
2026-01-29 03:44:57.757 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.28.20:5700/1) Recv SETFORMAT cmd
2026-01-29 03:44:57.757 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.28.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:44:57.757 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 03:44:57.758 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.28.20:5700/1) Recv NOMTXPOWER cmd
2026-01-29 03:44:57.758 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.28.20:5700/1) Recv SETFORMAT cmd
2026-01-29 03:44:57.758 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.28.20:5700/1) TRXD header version 1 -> 1
2026-01-29 03:44:57.761 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.28.20:5700/2) Recv RXTUNE cmd
2026-01-29 03:44:57.761 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.28.20:5700/2) Recv TXTUNE cmd
2026-01-29 03:44:57.761 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.28.20:5700/2) Recv SETFORMAT cmd
2026-01-29 03:44:57.761 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.28.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:44:57.761 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 03:44:57.761 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.28.20:5700/2) Recv NOMTXPOWER cmd
2026-01-29 03:44:57.761 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.28.20:5700/2) Recv SETFORMAT cmd
2026-01-29 03:44:57.761 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.28.20:5700/2) TRXD header version 1 -> 1
2026-01-29 03:44:57.764 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.28.20:5700/3) Recv RXTUNE cmd
2026-01-29 03:44:57.764 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.28.20:5700/3) Recv TXTUNE cmd
2026-01-29 03:44:57.764 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.28.20:5700/3) Recv SETFORMAT cmd
2026-01-29 03:44:57.764 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.28.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:44:57.764 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 03:44:57.764 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.28.20:5700/3) Recv NOMTXPOWER cmd
2026-01-29 03:44:57.764 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.28.20:5700/3) Recv SETFORMAT cmd
2026-01-29 03:44:57.764 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.28.20:5700/3) TRXD header version 1 -> 1
2026-01-29 03:44:57.768 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.28.20:5700) Recv RXTUNE cmd
2026-01-29 03:44:57.768 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETTSC
2026-01-29 03:44:57.768 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETTSC
2026-01-29 03:44:57.768 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETTSC
2026-01-29 03:44:57.768 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.28.20:5700) Recv TXTUNE cmd
2026-01-29 03:44:57.768 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETRXGAIN
2026-01-29 03:44:57.768 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETRXGAIN
2026-01-29 03:44:57.768 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETRXGAIN
2026-01-29 03:44:57.768 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETTSC
2026-01-29 03:44:57.769 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:44:57.769 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:44:57.769 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:44:57.769 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.28.20:5700) Recv NOMTXPOWER cmd
2026-01-29 03:44:57.769 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:44:57.769 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:44:57.769 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:44:57.769 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.28.20:5700) Recv POWERON CMD
2026-01-29 03:44:57.769 [INFO] ctrl_if_trx.py:109 (BTS@172.18.28.20:5700) Starting transceiver...
2026-01-29 03:44:57.769 [INFO] transceiver.py:243 Starting clock generator
2026-01-29 03:44:57.769 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-01-29 03:44:57.769 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:44:57.769 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:44:57.769 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:44:57.769 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETRXGAIN
2026-01-29 03:44:57.769 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:44:57.769 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:44:57.769 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:44:57.769 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:44:57.770 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:44:57.770 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:44:57.770 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:44:57.770 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:44:57.770 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:44:57.770 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:44:57.770 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:44:57.770 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:44:57.770 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:44:57.770 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:44:57.770 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:44:57.770 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:44:57.770 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:44:57.770 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:44:57.770 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:44:57.770 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:44:57.771 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:44:57.771 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:44:57.771 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:44:57.774 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-01-29 03:44:58.254 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-01-29 03:44:58.292 [DEBUG] fake_trx.py:278 (BTS@172.18.28.20:5700) Recv FAKE_TOA cmd
2026-01-29 03:44:58.292 [DEBUG] fake_trx.py:297 (BTS@172.18.28.20:5700) Recv FAKE_RSSI cmd
2026-01-29 03:44:58.292 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:44:58.293 [DEBUG] fake_trx.py:322 (BTS@172.18.28.20:5700) Recv FAKE_CI cmd
2026-01-29 03:44:58.293 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 03:44:58.294 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 03:44:58.294 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 03:44:58.294 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 03:44:58.294 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 03:44:58.294 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 03:44:58.294 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.28.22:6700) Recv POWERON CMD
2026-01-29 03:44:58.294 [INFO] ctrl_if_trx.py:109 (MS@172.18.28.22:6700) Starting transceiver...
2026-01-29 03:44:58.730 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-01-29 03:44:58.772 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 03:44:58.773 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:44:58.775 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:44:58.780 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:44:59.208 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-01-29 03:44:59.686 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-01-29 03:44:59.773 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:44:59.774 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 03:44:59.776 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:44:59.781 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:45:00.158 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-01-29 03:45:00.628 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-01-29 03:45:00.775 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 03:45:00.775 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:45:00.777 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:45:00.782 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:45:01.099 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-01-29 03:45:01.570 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-01-29 03:45:01.770 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 03:45:01.770 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 03:45:01.773 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 03:45:01.773 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:45:01.774 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:45:01.774 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:45:01.777 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 03:45:01.777 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 03:45:01.777 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 03:45:01.778 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.28.20:5700) Recv POWEROFF cmd
2026-01-29 03:45:01.778 [INFO] ctrl_if_trx.py:117 (BTS@172.18.28.20:5700) Stopping transceiver...
2026-01-29 03:45:01.778 [INFO] transceiver.py:246 Stopping clock generator
2026-01-29 03:45:01.778 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 03:45:01.778 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=862 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:45:01.778 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=862 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:45:01.778 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=862 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:45:01.779 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=862 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:45:01.779 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=862 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:45:01.779 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=862 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:45:01.779 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=862 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:45:01.779 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=863 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:45:01.779 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=863 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:45:01.779 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=863 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:45:01.779 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=863 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:45:01.779 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=863 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:45:01.779 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=863 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:45:01.779 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=863 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:45:01.780 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=863 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:45:06.776 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.28.20:5700) Recv POWEROFF cmd
2026-01-29 03:45:06.776 [INFO] ctrl_if_trx.py:117 (BTS@172.18.28.20:5700) Stopping transceiver...
2026-01-29 03:45:06.777 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 03:45:06.780 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 03:45:06.780 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 03:45:06.780 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 03:45:06.783 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 03:45:06.783 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.28.20:5700) Recv SETFORMAT cmd
2026-01-29 03:45:06.783 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.28.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:45:06.783 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.28.20:5700) Recv SETFORMAT cmd
2026-01-29 03:45:06.783 [INFO] ctrl_if_trx.py:201 (BTS@172.18.28.20:5700) TRXD header version 1 -> 1
2026-01-29 03:45:06.784 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.28.20:5700/1) Recv RXTUNE cmd
2026-01-29 03:45:06.784 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.28.20:5700/1) Recv TXTUNE cmd
2026-01-29 03:45:06.785 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.28.20:5700/1) Recv SETFORMAT cmd
2026-01-29 03:45:06.785 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.28.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:45:06.785 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 03:45:06.785 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.28.20:5700/1) Recv NOMTXPOWER cmd
2026-01-29 03:45:06.785 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.28.20:5700/1) Recv SETFORMAT cmd
2026-01-29 03:45:06.785 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.28.20:5700/1) TRXD header version 1 -> 1
2026-01-29 03:45:06.787 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.28.20:5700/2) Recv RXTUNE cmd
2026-01-29 03:45:06.787 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.28.20:5700/2) Recv TXTUNE cmd
2026-01-29 03:45:06.787 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.28.20:5700/2) Recv SETFORMAT cmd
2026-01-29 03:45:06.787 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.28.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:45:06.787 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 03:45:06.787 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.28.20:5700/2) Recv NOMTXPOWER cmd
2026-01-29 03:45:06.787 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.28.20:5700/2) Recv SETFORMAT cmd
2026-01-29 03:45:06.787 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.28.20:5700/2) TRXD header version 1 -> 1
2026-01-29 03:45:06.788 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.28.20:5700/3) Recv RXTUNE cmd
2026-01-29 03:45:06.789 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.28.20:5700/3) Recv TXTUNE cmd
2026-01-29 03:45:06.789 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.28.20:5700/3) Recv SETFORMAT cmd
2026-01-29 03:45:06.789 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.28.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:45:06.789 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 03:45:06.789 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.28.20:5700/3) Recv NOMTXPOWER cmd
2026-01-29 03:45:06.789 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.28.20:5700/3) Recv SETFORMAT cmd
2026-01-29 03:45:06.789 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.28.20:5700/3) TRXD header version 1 -> 1
2026-01-29 03:45:06.791 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.28.20:5700) Recv RXTUNE cmd
2026-01-29 03:45:06.791 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETTSC
2026-01-29 03:45:06.791 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETTSC
2026-01-29 03:45:06.791 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETTSC
2026-01-29 03:45:06.791 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.28.20:5700) Recv TXTUNE cmd
2026-01-29 03:45:06.791 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETRXGAIN
2026-01-29 03:45:06.791 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETRXGAIN
2026-01-29 03:45:06.791 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETRXGAIN
2026-01-29 03:45:06.791 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETTSC
2026-01-29 03:45:06.791 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:45:06.791 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:45:06.791 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:45:06.791 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.28.20:5700) Recv NOMTXPOWER cmd
2026-01-29 03:45:06.791 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:45:06.791 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:45:06.791 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:45:06.791 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.28.20:5700) Recv POWERON CMD
2026-01-29 03:45:06.791 [INFO] ctrl_if_trx.py:109 (BTS@172.18.28.20:5700) Starting transceiver...
2026-01-29 03:45:06.791 [INFO] transceiver.py:243 Starting clock generator
2026-01-29 03:45:06.791 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-01-29 03:45:06.791 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:45:06.791 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:45:06.791 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:45:06.791 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETRXGAIN
2026-01-29 03:45:06.791 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:45:06.791 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:45:06.791 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:45:06.791 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:45:06.792 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:45:06.792 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:45:06.792 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:45:06.792 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:45:06.792 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:45:06.792 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:45:06.792 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:45:06.792 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:45:06.792 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:45:06.792 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:45:06.792 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:45:06.792 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:45:06.792 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:45:06.792 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:45:06.792 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:45:06.792 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:45:06.792 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:45:06.792 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:45:06.792 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:45:06.796 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-01-29 03:45:07.265 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-01-29 03:45:07.322 [DEBUG] fake_trx.py:278 (BTS@172.18.28.20:5700) Recv FAKE_TOA cmd
2026-01-29 03:45:07.323 [DEBUG] fake_trx.py:297 (BTS@172.18.28.20:5700) Recv FAKE_RSSI cmd
2026-01-29 03:45:07.324 [DEBUG] fake_trx.py:322 (BTS@172.18.28.20:5700) Recv FAKE_CI cmd
2026-01-29 03:45:07.324 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:45:07.333 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 03:45:07.333 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 03:45:07.333 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 03:45:07.335 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 03:45:07.335 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 03:45:07.335 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 03:45:07.335 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.28.22:6700) Recv POWERON CMD
2026-01-29 03:45:07.335 [INFO] ctrl_if_trx.py:109 (MS@172.18.28.22:6700) Starting transceiver...
2026-01-29 03:45:07.361 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD HANDOVER
2026-01-29 03:45:07.366 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 03:45:07.367 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 03:45:07.367 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 03:45:07.367 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 03:45:07.734 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-01-29 03:45:07.794 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:45:07.794 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 03:45:07.794 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:45:07.796 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:45:07.853 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 03:45:07.853 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 03:45:07.853 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 03:45:07.854 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 03:45:07.854 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 03:45:07.854 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 03:45:07.854 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 03:45:07.854 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.28.22:6700) Recv POWERON CMD
2026-01-29 03:45:07.854 [INFO] ctrl_if_trx.py:109 (MS@172.18.28.22:6700) Starting transceiver...
2026-01-29 03:45:07.868 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:45:07.870 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 03:45:07.870 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 03:45:07.876 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 03:45:07.877 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:45:07.877 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:45:07.877 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:45:07.880 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 03:45:07.881 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 03:45:07.881 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 03:45:07.881 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 03:45:07.881 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.28.20:5700) Recv POWEROFF cmd
2026-01-29 03:45:07.881 [INFO] ctrl_if_trx.py:117 (BTS@172.18.28.20:5700) Stopping transceiver...
2026-01-29 03:45:07.881 [INFO] transceiver.py:246 Stopping clock generator
2026-01-29 03:45:07.881 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=237 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:45:07.882 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=237 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:45:07.882 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=237 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:45:07.882 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=237 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:45:07.882 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=237 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:45:07.882 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=237 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:45:07.882 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=237 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:45:07.882 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=238 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:45:07.882 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=238 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:45:07.882 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=238 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:45:07.882 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=238 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:45:07.883 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=238 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:45:07.883 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=238 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:45:07.883 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=238 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:45:07.883 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=238 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:45:12.880 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.28.20:5700) Recv POWEROFF cmd
2026-01-29 03:45:12.880 [INFO] ctrl_if_trx.py:117 (BTS@172.18.28.20:5700) Stopping transceiver...
2026-01-29 03:45:12.882 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 03:45:12.883 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 03:45:12.884 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 03:45:12.884 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 03:45:12.893 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 03:45:12.894 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.28.20:5700) Recv SETFORMAT cmd
2026-01-29 03:45:12.895 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.28.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:45:12.895 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.28.20:5700) Recv SETFORMAT cmd
2026-01-29 03:45:12.895 [INFO] ctrl_if_trx.py:201 (BTS@172.18.28.20:5700) TRXD header version 1 -> 1
2026-01-29 03:45:12.899 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.28.20:5700/1) Recv RXTUNE cmd
2026-01-29 03:45:12.899 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.28.20:5700/1) Recv TXTUNE cmd
2026-01-29 03:45:12.899 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.28.20:5700/1) Recv SETFORMAT cmd
2026-01-29 03:45:12.900 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.28.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:45:12.900 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 03:45:12.900 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.28.20:5700/1) Recv NOMTXPOWER cmd
2026-01-29 03:45:12.901 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.28.20:5700/1) Recv SETFORMAT cmd
2026-01-29 03:45:12.901 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.28.20:5700/1) TRXD header version 1 -> 1
2026-01-29 03:45:12.902 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.28.20:5700/2) Recv RXTUNE cmd
2026-01-29 03:45:12.902 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.28.20:5700/2) Recv TXTUNE cmd
2026-01-29 03:45:12.902 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.28.20:5700/2) Recv SETFORMAT cmd
2026-01-29 03:45:12.902 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.28.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:45:12.903 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 03:45:12.903 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.28.20:5700/2) Recv NOMTXPOWER cmd
2026-01-29 03:45:12.903 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.28.20:5700/2) Recv SETFORMAT cmd
2026-01-29 03:45:12.903 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.28.20:5700/2) TRXD header version 1 -> 1
2026-01-29 03:45:12.904 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.28.20:5700/3) Recv RXTUNE cmd
2026-01-29 03:45:12.905 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.28.20:5700/3) Recv TXTUNE cmd
2026-01-29 03:45:12.905 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.28.20:5700/3) Recv SETFORMAT cmd
2026-01-29 03:45:12.905 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.28.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:45:12.905 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 03:45:12.905 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.28.20:5700/3) Recv NOMTXPOWER cmd
2026-01-29 03:45:12.905 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.28.20:5700/3) Recv SETFORMAT cmd
2026-01-29 03:45:12.905 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.28.20:5700/3) TRXD header version 1 -> 1
2026-01-29 03:45:12.907 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.28.20:5700) Recv RXTUNE cmd
2026-01-29 03:45:12.908 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETTSC
2026-01-29 03:45:12.908 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETTSC
2026-01-29 03:45:12.908 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETTSC
2026-01-29 03:45:12.908 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.28.20:5700) Recv TXTUNE cmd
2026-01-29 03:45:12.908 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETRXGAIN
2026-01-29 03:45:12.908 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETRXGAIN
2026-01-29 03:45:12.908 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETRXGAIN
2026-01-29 03:45:12.908 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETTSC
2026-01-29 03:45:12.908 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:45:12.908 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:45:12.908 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:45:12.908 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.28.20:5700) Recv NOMTXPOWER cmd
2026-01-29 03:45:12.908 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:45:12.908 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:45:12.908 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:45:12.908 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.28.20:5700) Recv POWERON CMD
2026-01-29 03:45:12.908 [INFO] ctrl_if_trx.py:109 (BTS@172.18.28.20:5700) Starting transceiver...
2026-01-29 03:45:12.908 [INFO] transceiver.py:243 Starting clock generator
2026-01-29 03:45:12.908 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-01-29 03:45:12.908 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:45:12.908 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:45:12.908 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:45:12.909 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETRXGAIN
2026-01-29 03:45:12.909 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:45:12.909 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:45:12.909 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:45:12.909 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:45:12.909 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:45:12.909 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:45:12.909 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:45:12.909 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:45:12.909 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:45:12.909 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:45:12.909 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:45:12.909 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:45:12.909 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:45:12.909 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:45:12.909 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:45:12.909 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:45:12.909 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:45:12.909 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:45:12.909 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:45:12.909 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:45:12.909 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:45:12.909 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:45:12.909 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:45:12.913 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-01-29 03:45:13.396 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-01-29 03:45:13.440 [DEBUG] fake_trx.py:278 (BTS@172.18.28.20:5700) Recv FAKE_TOA cmd
2026-01-29 03:45:13.443 [DEBUG] fake_trx.py:297 (BTS@172.18.28.20:5700) Recv FAKE_RSSI cmd
2026-01-29 03:45:13.444 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:45:13.445 [DEBUG] fake_trx.py:322 (BTS@172.18.28.20:5700) Recv FAKE_CI cmd
2026-01-29 03:45:13.471 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 03:45:13.471 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 03:45:13.471 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 03:45:13.475 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 03:45:13.475 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 03:45:13.476 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 03:45:13.476 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.28.22:6700) Recv POWERON CMD
2026-01-29 03:45:13.476 [INFO] ctrl_if_trx.py:109 (MS@172.18.28.22:6700) Starting transceiver...
2026-01-29 03:45:13.491 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD HANDOVER
2026-01-29 03:45:13.494 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 03:45:13.495 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 03:45:13.495 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 03:45:13.495 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 03:45:13.554 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:45:13.611 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 03:45:13.611 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 03:45:13.612 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 03:45:13.612 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 03:45:13.612 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 03:45:13.613 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 03:45:13.613 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 03:45:13.613 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.28.22:6700) Recv POWERON CMD
2026-01-29 03:45:13.613 [INFO] ctrl_if_trx.py:109 (MS@172.18.28.22:6700) Starting transceiver...
2026-01-29 03:45:13.868 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-01-29 03:45:13.912 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:45:13.912 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 03:45:13.913 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:45:13.916 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:45:14.340 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-01-29 03:45:14.814 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-01-29 03:45:14.912 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:45:14.913 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 03:45:14.914 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:45:14.917 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:45:15.288 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-01-29 03:45:15.757 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-01-29 03:45:15.913 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:45:15.913 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 03:45:15.916 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:45:15.918 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:45:16.227 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-01-29 03:45:16.698 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-01-29 03:45:16.914 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 03:45:16.914 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:45:16.916 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:45:16.919 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:45:17.169 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-01-29 03:45:17.640 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-01-29 03:45:17.915 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 03:45:17.915 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:45:17.917 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:45:17.919 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:45:18.111 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-01-29 03:45:18.581 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-01-29 03:45:19.052 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-01-29 03:45:19.523 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-01-29 03:45:19.993 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-01-29 03:45:20.464 [DEBUG] clck_gen.py:113 IND CLOCK 1632
2026-01-29 03:45:20.935 [DEBUG] clck_gen.py:113 IND CLOCK 1734
2026-01-29 03:45:21.406 [DEBUG] clck_gen.py:113 IND CLOCK 1836
2026-01-29 03:45:21.877 [DEBUG] clck_gen.py:113 IND CLOCK 1938
2026-01-29 03:45:22.350 [DEBUG] clck_gen.py:113 IND CLOCK 2040
2026-01-29 03:45:22.820 [DEBUG] clck_gen.py:113 IND CLOCK 2142
2026-01-29 03:45:23.290 [DEBUG] clck_gen.py:113 IND CLOCK 2244
2026-01-29 03:45:23.761 [DEBUG] clck_gen.py:113 IND CLOCK 2346
2026-01-29 03:45:24.231 [DEBUG] clck_gen.py:113 IND CLOCK 2448
2026-01-29 03:45:24.710 [DEBUG] clck_gen.py:113 IND CLOCK 2550
2026-01-29 03:45:25.182 [DEBUG] clck_gen.py:113 IND CLOCK 2652
2026-01-29 03:45:25.652 [DEBUG] clck_gen.py:113 IND CLOCK 2754
2026-01-29 03:45:26.123 [DEBUG] clck_gen.py:113 IND CLOCK 2856
2026-01-29 03:45:26.599 [DEBUG] clck_gen.py:113 IND CLOCK 2958
2026-01-29 03:45:27.074 [DEBUG] clck_gen.py:113 IND CLOCK 3060
2026-01-29 03:45:27.547 [DEBUG] clck_gen.py:113 IND CLOCK 3162
2026-01-29 03:45:28.019 [DEBUG] clck_gen.py:113 IND CLOCK 3264
2026-01-29 03:45:28.499 [DEBUG] clck_gen.py:113 IND CLOCK 3366
2026-01-29 03:45:28.796 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 03:45:28.797 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 03:45:28.797 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 03:45:28.797 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 03:45:28.805 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 03:45:28.805 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 03:45:28.805 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 03:45:28.805 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.28.22:6700) Recv POWERON CMD
2026-01-29 03:45:28.805 [INFO] ctrl_if_trx.py:109 (MS@172.18.28.22:6700) Starting transceiver...
2026-01-29 03:45:28.825 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:45:28.829 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 03:45:28.829 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 03:45:28.839 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 03:45:28.839 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:45:28.839 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:45:28.840 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:45:28.843 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 03:45:28.843 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 03:45:28.843 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 03:45:28.843 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.28.20:5700) Recv POWEROFF cmd
2026-01-29 03:45:28.843 [INFO] ctrl_if_trx.py:117 (BTS@172.18.28.20:5700) Stopping transceiver...
2026-01-29 03:45:28.843 [INFO] transceiver.py:246 Stopping clock generator
2026-01-29 03:45:28.843 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 03:45:28.843 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=3441 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:45:28.843 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=3441 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:45:28.843 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=3441 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:45:28.843 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=3441 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:45:28.843 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=3441 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:45:28.843 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=3441 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:45:28.843 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=3441 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:45:28.843 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=3442 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:45:28.843 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=3442 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:45:28.843 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=3442 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:45:28.843 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=3442 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:45:28.844 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=3442 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:45:28.844 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=3442 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:45:28.844 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=3442 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:45:28.844 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=3442 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:45:33.842 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.28.20:5700) Recv POWEROFF cmd
2026-01-29 03:45:33.843 [INFO] ctrl_if_trx.py:117 (BTS@172.18.28.20:5700) Stopping transceiver...
2026-01-29 03:45:33.844 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 03:45:33.846 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 03:45:33.846 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 03:45:33.846 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 03:45:33.850 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 03:45:33.851 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.28.20:5700) Recv SETFORMAT cmd
2026-01-29 03:45:33.851 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.28.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:45:33.851 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.28.20:5700) Recv SETFORMAT cmd
2026-01-29 03:45:33.851 [INFO] ctrl_if_trx.py:201 (BTS@172.18.28.20:5700) TRXD header version 1 -> 1
2026-01-29 03:45:33.854 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.28.20:5700/1) Recv RXTUNE cmd
2026-01-29 03:45:33.854 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.28.20:5700/1) Recv TXTUNE cmd
2026-01-29 03:45:33.854 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.28.20:5700/1) Recv SETFORMAT cmd
2026-01-29 03:45:33.854 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.28.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:45:33.854 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 03:45:33.855 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.28.20:5700/1) Recv NOMTXPOWER cmd
2026-01-29 03:45:33.855 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.28.20:5700/1) Recv SETFORMAT cmd
2026-01-29 03:45:33.855 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.28.20:5700/1) TRXD header version 1 -> 1
2026-01-29 03:45:33.857 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.28.20:5700/2) Recv RXTUNE cmd
2026-01-29 03:45:33.857 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.28.20:5700/2) Recv TXTUNE cmd
2026-01-29 03:45:33.857 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.28.20:5700/2) Recv SETFORMAT cmd
2026-01-29 03:45:33.857 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.28.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:45:33.857 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 03:45:33.857 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.28.20:5700/2) Recv NOMTXPOWER cmd
2026-01-29 03:45:33.857 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.28.20:5700/2) Recv SETFORMAT cmd
2026-01-29 03:45:33.857 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.28.20:5700/2) TRXD header version 1 -> 1
2026-01-29 03:45:33.859 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.28.20:5700/3) Recv RXTUNE cmd
2026-01-29 03:45:33.859 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.28.20:5700/3) Recv TXTUNE cmd
2026-01-29 03:45:33.859 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.28.20:5700/3) Recv SETFORMAT cmd
2026-01-29 03:45:33.859 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.28.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:45:33.859 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 03:45:33.859 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.28.20:5700/3) Recv NOMTXPOWER cmd
2026-01-29 03:45:33.860 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.28.20:5700/3) Recv SETFORMAT cmd
2026-01-29 03:45:33.860 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.28.20:5700/3) TRXD header version 1 -> 1
2026-01-29 03:45:33.862 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.28.20:5700) Recv RXTUNE cmd
2026-01-29 03:45:33.862 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETTSC
2026-01-29 03:45:33.862 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETTSC
2026-01-29 03:45:33.862 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.28.20:5700) Recv TXTUNE cmd
2026-01-29 03:45:33.862 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETTSC
2026-01-29 03:45:33.862 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETRXGAIN
2026-01-29 03:45:33.862 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETRXGAIN
2026-01-29 03:45:33.862 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETTSC
2026-01-29 03:45:33.862 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETRXGAIN
2026-01-29 03:45:33.862 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:45:33.862 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:45:33.862 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.28.20:5700) Recv NOMTXPOWER cmd
2026-01-29 03:45:33.862 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:45:33.863 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:45:33.863 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:45:33.863 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.28.20:5700) Recv POWERON CMD
2026-01-29 03:45:33.863 [INFO] ctrl_if_trx.py:109 (BTS@172.18.28.20:5700) Starting transceiver...
2026-01-29 03:45:33.863 [INFO] transceiver.py:243 Starting clock generator
2026-01-29 03:45:33.863 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-01-29 03:45:33.863 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:45:33.863 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:45:33.863 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:45:33.863 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETRXGAIN
2026-01-29 03:45:33.863 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:45:33.863 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:45:33.863 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:45:33.863 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:45:33.863 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:45:33.863 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:45:33.863 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:45:33.863 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:45:33.863 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:45:33.863 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:45:33.863 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:45:33.864 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:45:33.864 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:45:33.864 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:45:33.864 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:45:33.864 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:45:33.864 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:45:33.864 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:45:33.864 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:45:33.864 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:45:33.864 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:45:33.864 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:45:33.864 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:45:33.864 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:45:33.868 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-01-29 03:45:34.336 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-01-29 03:45:34.397 [DEBUG] fake_trx.py:278 (BTS@172.18.28.20:5700) Recv FAKE_TOA cmd
2026-01-29 03:45:34.399 [DEBUG] fake_trx.py:297 (BTS@172.18.28.20:5700) Recv FAKE_RSSI cmd
2026-01-29 03:45:34.399 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:45:34.401 [DEBUG] fake_trx.py:322 (BTS@172.18.28.20:5700) Recv FAKE_CI cmd
2026-01-29 03:45:34.422 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 03:45:34.422 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 03:45:34.423 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 03:45:34.426 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 03:45:34.426 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 03:45:34.426 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 03:45:34.426 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.28.22:6700) Recv POWERON CMD
2026-01-29 03:45:34.426 [INFO] ctrl_if_trx.py:109 (MS@172.18.28.22:6700) Starting transceiver...
2026-01-29 03:45:34.477 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD HANDOVER
2026-01-29 03:45:34.482 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 03:45:34.482 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 03:45:34.482 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 03:45:34.482 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 03:45:34.554 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:45:34.713 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD HANDOVER
2026-01-29 03:45:34.790 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 03:45:34.791 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 03:45:34.791 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 03:45:34.792 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 03:45:34.792 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 03:45:34.792 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 03:45:34.792 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 03:45:34.792 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.28.22:6700) Recv POWERON CMD
2026-01-29 03:45:34.792 [INFO] ctrl_if_trx.py:109 (MS@172.18.28.22:6700) Starting transceiver...
2026-01-29 03:45:34.805 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:45:34.806 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-01-29 03:45:34.807 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 03:45:34.807 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 03:45:34.814 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 03:45:34.814 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:45:34.814 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:45:34.814 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:45:34.814 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 03:45:34.814 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 03:45:34.815 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 03:45:34.815 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 03:45:34.815 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.28.20:5700) Recv POWEROFF cmd
2026-01-29 03:45:34.815 [INFO] ctrl_if_trx.py:117 (BTS@172.18.28.20:5700) Stopping transceiver...
2026-01-29 03:45:34.815 [INFO] transceiver.py:246 Stopping clock generator
2026-01-29 03:45:34.815 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=208 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:45:34.815 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=208 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:45:34.815 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=208 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:45:34.815 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=208 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:45:34.815 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=208 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:45:39.817 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.28.20:5700) Recv POWEROFF cmd
2026-01-29 03:45:39.817 [INFO] ctrl_if_trx.py:117 (BTS@172.18.28.20:5700) Stopping transceiver...
2026-01-29 03:45:39.819 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 03:45:39.819 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 03:45:39.820 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 03:45:39.820 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 03:45:39.827 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 03:45:39.828 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.28.20:5700) Recv SETFORMAT cmd
2026-01-29 03:45:39.828 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.28.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:45:39.829 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.28.20:5700) Recv SETFORMAT cmd
2026-01-29 03:45:39.829 [INFO] ctrl_if_trx.py:201 (BTS@172.18.28.20:5700) TRXD header version 1 -> 1
2026-01-29 03:45:39.830 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.28.20:5700/1) Recv RXTUNE cmd
2026-01-29 03:45:39.831 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.28.20:5700/1) Recv TXTUNE cmd
2026-01-29 03:45:39.831 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.28.20:5700/1) Recv SETFORMAT cmd
2026-01-29 03:45:39.831 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.28.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:45:39.832 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 03:45:39.832 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.28.20:5700/1) Recv NOMTXPOWER cmd
2026-01-29 03:45:39.832 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.28.20:5700/1) Recv SETFORMAT cmd
2026-01-29 03:45:39.832 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.28.20:5700/1) TRXD header version 1 -> 1
2026-01-29 03:45:39.833 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.28.20:5700/2) Recv RXTUNE cmd
2026-01-29 03:45:39.833 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.28.20:5700/2) Recv TXTUNE cmd
2026-01-29 03:45:39.833 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.28.20:5700/2) Recv SETFORMAT cmd
2026-01-29 03:45:39.833 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.28.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:45:39.833 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 03:45:39.833 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.28.20:5700/2) Recv NOMTXPOWER cmd
2026-01-29 03:45:39.834 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.28.20:5700/2) Recv SETFORMAT cmd
2026-01-29 03:45:39.834 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.28.20:5700/2) TRXD header version 1 -> 1
2026-01-29 03:45:39.835 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.28.20:5700/3) Recv RXTUNE cmd
2026-01-29 03:45:39.835 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.28.20:5700/3) Recv TXTUNE cmd
2026-01-29 03:45:39.835 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.28.20:5700/3) Recv SETFORMAT cmd
2026-01-29 03:45:39.835 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.28.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:45:39.835 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 03:45:39.835 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.28.20:5700/3) Recv NOMTXPOWER cmd
2026-01-29 03:45:39.836 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.28.20:5700/3) Recv SETFORMAT cmd
2026-01-29 03:45:39.836 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.28.20:5700/3) TRXD header version 1 -> 1
2026-01-29 03:45:39.837 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.28.20:5700) Recv RXTUNE cmd
2026-01-29 03:45:39.837 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETTSC
2026-01-29 03:45:39.838 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETTSC
2026-01-29 03:45:39.838 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETTSC
2026-01-29 03:45:39.838 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.28.20:5700) Recv TXTUNE cmd
2026-01-29 03:45:39.838 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETRXGAIN
2026-01-29 03:45:39.838 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETTSC
2026-01-29 03:45:39.838 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETRXGAIN
2026-01-29 03:45:39.838 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETRXGAIN
2026-01-29 03:45:39.838 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.28.20:5700) Recv NOMTXPOWER cmd
2026-01-29 03:45:39.838 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:45:39.838 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:45:39.838 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:45:39.838 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.28.20:5700) Recv POWERON CMD
2026-01-29 03:45:39.838 [INFO] ctrl_if_trx.py:109 (BTS@172.18.28.20:5700) Starting transceiver...
2026-01-29 03:45:39.838 [INFO] transceiver.py:243 Starting clock generator
2026-01-29 03:45:39.839 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-01-29 03:45:39.839 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:45:39.839 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:45:39.839 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETRXGAIN
2026-01-29 03:45:39.839 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:45:39.839 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:45:39.839 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:45:39.839 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:45:39.839 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:45:39.839 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:45:39.839 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:45:39.839 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:45:39.840 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:45:39.840 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:45:39.840 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:45:39.840 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:45:39.840 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:45:39.840 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:45:39.840 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:45:39.840 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:45:39.840 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:45:39.840 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:45:39.840 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:45:39.840 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:45:39.841 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:45:39.841 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:45:39.841 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:45:39.841 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETSLOT
2026-01-29 03:45:39.841 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:45:39.841 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:45:39.842 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:45:39.844 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-01-29 03:45:40.329 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-01-29 03:45:40.365 [DEBUG] fake_trx.py:278 (BTS@172.18.28.20:5700) Recv FAKE_TOA cmd
2026-01-29 03:45:40.367 [DEBUG] fake_trx.py:297 (BTS@172.18.28.20:5700) Recv FAKE_RSSI cmd
2026-01-29 03:45:40.368 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:45:40.369 [DEBUG] fake_trx.py:322 (BTS@172.18.28.20:5700) Recv FAKE_CI cmd
2026-01-29 03:45:40.392 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 03:45:40.392 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 03:45:40.393 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 03:45:40.397 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 03:45:40.397 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 03:45:40.398 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 03:45:40.398 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.28.22:6700) Recv POWERON CMD
2026-01-29 03:45:40.398 [INFO] ctrl_if_trx.py:109 (MS@172.18.28.22:6700) Starting transceiver...
2026-01-29 03:45:40.425 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD HANDOVER
2026-01-29 03:45:40.431 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 03:45:40.431 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 03:45:40.432 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 03:45:40.433 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 03:45:40.813 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-01-29 03:45:40.841 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:45:40.841 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 03:45:40.842 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:45:40.843 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:45:41.300 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-01-29 03:45:41.785 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-01-29 03:45:41.841 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:45:41.842 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 03:45:41.843 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:45:41.844 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:45:42.269 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-01-29 03:45:42.437 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 03:45:42.438 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 03:45:42.438 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 03:45:42.438 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD ECHO
2026-01-29 03:45:42.453 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.28.22:6700) Ignore CMD SETSLOT
2026-01-29 03:45:42.453 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.28.22:6700) Recv RXTUNE cmd
2026-01-29 03:45:42.453 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.28.22:6700) Recv TXTUNE cmd
2026-01-29 03:45:42.453 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.28.22:6700) Recv POWERON CMD
2026-01-29 03:45:42.453 [INFO] ctrl_if_trx.py:109 (MS@172.18.28.22:6700) Starting transceiver...
2026-01-29 03:45:42.503 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:45:42.506 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.28.22:6700) Recv POWEROFF cmd
2026-01-29 03:45:42.506 [INFO] ctrl_if_trx.py:117 (MS@172.18.28.22:6700) Stopping transceiver...
2026-01-29 03:45:42.515 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.28.20:5700) Recv SETPOWER cmd
2026-01-29 03:45:42.516 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.28.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:45:42.516 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.28.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:45:42.516 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.28.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:45:42.517 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 03:45:42.518 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 03:45:42.518 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 03:45:42.518 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 03:45:42.518 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.28.20:5700) Recv POWEROFF cmd
2026-01-29 03:45:42.518 [INFO] ctrl_if_trx.py:117 (BTS@172.18.28.20:5700) Stopping transceiver...
2026-01-29 03:45:42.518 [INFO] transceiver.py:246 Stopping clock generator
2026-01-29 03:45:42.518 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=565 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:45:42.518 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=565 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:45:42.518 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=565 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:45:42.518 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=565 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:45:42.518 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=565 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:45:42.518 [WARNING] transceiver.py:257 (BTS@172.18.28.20:5700) RX TRXD message (ver=1 fn=565 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:45:47.519 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.28.20:5700) Recv POWEROFF cmd
2026-01-29 03:45:47.519 [INFO] ctrl_if_trx.py:117 (BTS@172.18.28.20:5700) Stopping transceiver...
2026-01-29 03:45:47.521 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 03:45:47.522 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 03:45:47.523 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 03:45:47.524 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 03:45:47.531 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.28.20:5700) Recv RFMUTE cmd
2026-01-29 03:45:47.532 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.28.20:5700) Recv SETFORMAT cmd
2026-01-29 03:45:47.532 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.28.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:45:47.532 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.28.20:5700) Recv SETFORMAT cmd
2026-01-29 03:45:47.532 [INFO] ctrl_if_trx.py:201 (BTS@172.18.28.20:5700) TRXD header version 1 -> 1
2026-01-29 03:45:47.534 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.28.20:5700/1) Recv RXTUNE cmd
2026-01-29 03:45:47.534 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.28.20:5700/1) Recv TXTUNE cmd
2026-01-29 03:45:47.534 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.28.20:5700/1) Recv SETFORMAT cmd
2026-01-29 03:45:47.535 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.28.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:45:47.535 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.28.20:5700/1) Recv RFMUTE cmd
2026-01-29 03:45:47.535 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.28.20:5700/1) Recv NOMTXPOWER cmd
2026-01-29 03:45:47.535 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.28.20:5700/1) Recv SETFORMAT cmd
2026-01-29 03:45:47.536 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.28.20:5700/1) TRXD header version 1 -> 1
2026-01-29 03:45:47.536 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.28.20:5700/2) Recv RXTUNE cmd
2026-01-29 03:45:47.536 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.28.20:5700/2) Recv TXTUNE cmd
2026-01-29 03:45:47.536 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.28.20:5700/2) Recv SETFORMAT cmd
2026-01-29 03:45:47.536 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.28.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:45:47.536 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.28.20:5700/2) Recv RFMUTE cmd
2026-01-29 03:45:47.537 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.28.20:5700/2) Recv NOMTXPOWER cmd
2026-01-29 03:45:47.537 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.28.20:5700/2) Recv SETFORMAT cmd
2026-01-29 03:45:47.537 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.28.20:5700/2) TRXD header version 1 -> 1
2026-01-29 03:45:47.538 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.28.20:5700/3) Recv RXTUNE cmd
2026-01-29 03:45:47.538 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.28.20:5700/3) Recv TXTUNE cmd
2026-01-29 03:45:47.538 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.28.20:5700/3) Recv SETFORMAT cmd
2026-01-29 03:45:47.538 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.28.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:45:47.538 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.28.20:5700/3) Recv RFMUTE cmd
2026-01-29 03:45:47.538 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.28.20:5700/3) Recv NOMTXPOWER cmd
2026-01-29 03:45:47.539 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.28.20:5700/3) Recv SETFORMAT cmd
2026-01-29 03:45:47.539 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.28.20:5700/3) TRXD header version 1 -> 1
2026-01-29 03:45:47.540 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.28.20:5700) Recv RXTUNE cmd
2026-01-29 03:45:47.540 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETTSC
2026-01-29 03:45:47.541 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETTSC
2026-01-29 03:45:47.541 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETTSC
2026-01-29 03:45:47.541 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.28.20:5700) Recv TXTUNE cmd
2026-01-29 03:45:47.541 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETRXGAIN
2026-01-29 03:45:47.541 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETRXGAIN
2026-01-29 03:45:47.541 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.28.20:5700) Ignore CMD SETTSC
2026-01-29 03:45:47.541 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:45:47.541 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.28.20:5700/3) Ignore CMD SETRXGAIN
2026-01-29 03:45:47.541 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.28.20:5700) Recv NOMTXPOWER cmd
2026-01-29 03:45:47.541 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.28.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:45:47.541 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.28.20:5700/1) Ignore CMD SETSLOT